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target-alpha: make cpu-qom.h not target specific
[qemu/ar7.git] / target-tricore / translate.c
blob2d17aebaa31d49e5e989d67828e722ce4a8f4b58
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "tricore-opcodes.h"
31 #include "exec/log.h"
32
33 /*
34 * TCG registers
35 */
36 static TCGv cpu_PC;
37 static TCGv cpu_PCXI;
38 static TCGv cpu_PSW;
39 static TCGv cpu_ICR;
40 /* GPR registers */
41 static TCGv cpu_gpr_a[16];
42 static TCGv cpu_gpr_d[16];
43 /* PSW Flag cache */
44 static TCGv cpu_PSW_C;
45 static TCGv cpu_PSW_V;
46 static TCGv cpu_PSW_SV;
47 static TCGv cpu_PSW_AV;
48 static TCGv cpu_PSW_SAV;
49 /* CPU env */
50 static TCGv_env cpu_env;
51
52 #include "exec/gen-icount.h"
53
54 static const char *regnames_a[] = {
55 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
56 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
57 "a12" , "a13" , "a14" , "a15",
58 };
59
60 static const char *regnames_d[] = {
61 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
62 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
63 "d12" , "d13" , "d14" , "d15",
64 };
65
66 typedef struct DisasContext {
67 struct TranslationBlock *tb;
68 target_ulong pc, saved_pc, next_pc;
69 uint32_t opcode;
70 int singlestep_enabled;
71 /* Routine used to access memory */
72 int mem_idx;
73 uint32_t hflags, saved_hflags;
74 int bstate;
75 } DisasContext;
76
77 enum {
78
79 BS_NONE = 0,
80 BS_STOP = 1,
81 BS_BRANCH = 2,
82 BS_EXCP = 3,
83 };
84
85 enum {
86 MODE_LL = 0,
87 MODE_LU = 1,
88 MODE_UL = 2,
89 MODE_UU = 3,
90 };
91
92 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
93 fprintf_function cpu_fprintf, int flags)
94 {
95 TriCoreCPU *cpu = TRICORE_CPU(cs);
96 CPUTriCoreState *env = &cpu->env;
97 uint32_t psw;
98 int i;
99
100 psw = psw_read(env);
101
102 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
103 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
104 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
105 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
106 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
107 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
108
109 for (i = 0; i < 16; ++i) {
110 if ((i & 3) == 0) {
111 cpu_fprintf(f, "\nGPR A%02d:", i);
112 }
113 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
114 }
115 for (i = 0; i < 16; ++i) {
116 if ((i & 3) == 0) {
117 cpu_fprintf(f, "\nGPR D%02d:", i);
118 }
119 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
120 }
121 cpu_fprintf(f, "\n");
122 }
123
124 /*
125 * Functions to generate micro-ops
126 */
127
128 /* Makros for generating helpers */
129
130 #define gen_helper_1arg(name, arg) do { \
131 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
132 gen_helper_##name(cpu_env, helper_tmp); \
133 tcg_temp_free_i32(helper_tmp); \
134 } while (0)
135
136 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
137 TCGv arg00 = tcg_temp_new(); \
138 TCGv arg01 = tcg_temp_new(); \
139 TCGv arg11 = tcg_temp_new(); \
140 tcg_gen_sari_tl(arg00, arg0, 16); \
141 tcg_gen_ext16s_tl(arg01, arg0); \
142 tcg_gen_ext16s_tl(arg11, arg1); \
143 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
144 tcg_temp_free(arg00); \
145 tcg_temp_free(arg01); \
146 tcg_temp_free(arg11); \
147 } while (0)
148
149 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
150 TCGv arg00 = tcg_temp_new(); \
151 TCGv arg01 = tcg_temp_new(); \
152 TCGv arg10 = tcg_temp_new(); \
153 TCGv arg11 = tcg_temp_new(); \
154 tcg_gen_sari_tl(arg00, arg0, 16); \
155 tcg_gen_ext16s_tl(arg01, arg0); \
156 tcg_gen_sari_tl(arg11, arg1, 16); \
157 tcg_gen_ext16s_tl(arg10, arg1); \
158 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
159 tcg_temp_free(arg00); \
160 tcg_temp_free(arg01); \
161 tcg_temp_free(arg10); \
162 tcg_temp_free(arg11); \
163 } while (0)
164
165 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
166 TCGv arg00 = tcg_temp_new(); \
167 TCGv arg01 = tcg_temp_new(); \
168 TCGv arg10 = tcg_temp_new(); \
169 TCGv arg11 = tcg_temp_new(); \
170 tcg_gen_sari_tl(arg00, arg0, 16); \
171 tcg_gen_ext16s_tl(arg01, arg0); \
172 tcg_gen_sari_tl(arg10, arg1, 16); \
173 tcg_gen_ext16s_tl(arg11, arg1); \
174 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
175 tcg_temp_free(arg00); \
176 tcg_temp_free(arg01); \
177 tcg_temp_free(arg10); \
178 tcg_temp_free(arg11); \
179 } while (0)
180
181 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
182 TCGv arg00 = tcg_temp_new(); \
183 TCGv arg01 = tcg_temp_new(); \
184 TCGv arg11 = tcg_temp_new(); \
185 tcg_gen_sari_tl(arg01, arg0, 16); \
186 tcg_gen_ext16s_tl(arg00, arg0); \
187 tcg_gen_sari_tl(arg11, arg1, 16); \
188 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
189 tcg_temp_free(arg00); \
190 tcg_temp_free(arg01); \
191 tcg_temp_free(arg11); \
192 } while (0)
193
194 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
195 TCGv_i64 ret = tcg_temp_new_i64(); \
196 TCGv_i64 arg1 = tcg_temp_new_i64(); \
197 \
198 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
199 gen_helper_##name(ret, arg1, arg2); \
200 tcg_gen_extr_i64_i32(rl, rh, ret); \
201 \
202 tcg_temp_free_i64(ret); \
203 tcg_temp_free_i64(arg1); \
204 } while (0)
205
206 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
207 TCGv_i64 ret = tcg_temp_new_i64(); \
208 \
209 gen_helper_##name(ret, cpu_env, arg1, arg2); \
210 tcg_gen_extr_i64_i32(rl, rh, ret); \
211 \
212 tcg_temp_free_i64(ret); \
213 } while (0)
214
215 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
216 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
217 ((offset & 0x0fffff) << 1))
218
219 /* For two 32-bit registers used a 64-bit register, the first
220 registernumber needs to be even. Otherwise we trap. */
221 static inline void generate_trap(DisasContext *ctx, int class, int tin);
222 #define CHECK_REG_PAIR(reg) do { \
223 if (reg & 0x1) { \
224 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
225 } \
226 } while (0)
227
228 /* Functions for load/save to/from memory */
229
230 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
231 int16_t con, TCGMemOp mop)
232 {
233 TCGv temp = tcg_temp_new();
234 tcg_gen_addi_tl(temp, r2, con);
235 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
236 tcg_temp_free(temp);
237 }
238
239 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
240 int16_t con, TCGMemOp mop)
241 {
242 TCGv temp = tcg_temp_new();
243 tcg_gen_addi_tl(temp, r2, con);
244 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
245 tcg_temp_free(temp);
246 }
247
248 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
249 {
250 TCGv_i64 temp = tcg_temp_new_i64();
251
252 tcg_gen_concat_i32_i64(temp, rl, rh);
253 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
254
255 tcg_temp_free_i64(temp);
256 }
257
258 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
259 DisasContext *ctx)
260 {
261 TCGv temp = tcg_temp_new();
262 tcg_gen_addi_tl(temp, base, con);
263 gen_st_2regs_64(rh, rl, temp, ctx);
264 tcg_temp_free(temp);
265 }
266
267 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
268 {
269 TCGv_i64 temp = tcg_temp_new_i64();
270
271 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
272 /* write back to two 32 bit regs */
273 tcg_gen_extr_i64_i32(rl, rh, temp);
274
275 tcg_temp_free_i64(temp);
276 }
277
278 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
279 DisasContext *ctx)
280 {
281 TCGv temp = tcg_temp_new();
282 tcg_gen_addi_tl(temp, base, con);
283 gen_ld_2regs_64(rh, rl, temp, ctx);
284 tcg_temp_free(temp);
285 }
286
287 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
288 TCGMemOp mop)
289 {
290 TCGv temp = tcg_temp_new();
291 tcg_gen_addi_tl(temp, r2, off);
292 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
293 tcg_gen_mov_tl(r2, temp);
294 tcg_temp_free(temp);
295 }
296
297 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
298 TCGMemOp mop)
299 {
300 TCGv temp = tcg_temp_new();
301 tcg_gen_addi_tl(temp, r2, off);
302 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
303 tcg_gen_mov_tl(r2, temp);
304 tcg_temp_free(temp);
305 }
306
307 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
308 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
309 {
310 TCGv temp = tcg_temp_new();
311 TCGv temp2 = tcg_temp_new();
312
313 CHECK_REG_PAIR(ereg);
314 /* temp = (M(EA, word) */
315 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
316 /* temp = temp & ~E[a][63:32]) */
317 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
318 /* temp2 = (E[a][31:0] & E[a][63:32]); */
319 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
320 /* temp = temp | temp2; */
321 tcg_gen_or_tl(temp, temp, temp2);
322 /* M(EA, word) = temp; */
323 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
324
325 tcg_temp_free(temp);
326 tcg_temp_free(temp2);
327 }
328
329 /* tmp = M(EA, word);
330 M(EA, word) = D[a];
331 D[a] = tmp[31:0];*/
332 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
333 {
334 TCGv temp = tcg_temp_new();
335
336 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
337 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
338 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
339
340 tcg_temp_free(temp);
341 }
342
343 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
344 {
345 TCGv temp = tcg_temp_new();
346 TCGv temp2 = tcg_temp_new();
347 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
348 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
349 cpu_gpr_d[reg], temp);
350 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
351 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
352
353 tcg_temp_free(temp);
354 tcg_temp_free(temp2);
355 }
356
357 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
358 {
359 TCGv temp = tcg_temp_new();
360 TCGv temp2 = tcg_temp_new();
361 TCGv temp3 = tcg_temp_new();
362
363 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
364 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
365 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
366 tcg_gen_or_tl(temp2, temp2, temp3);
367 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
368 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
369
370 tcg_temp_free(temp);
371 tcg_temp_free(temp2);
372 tcg_temp_free(temp3);
373 }
374
375
376 /* We generate loads and store to core special function register (csfr) through
377 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
378 makros R, A and E, which allow read-only, all and endinit protected access.
379 These makros also specify in which ISA version the csfr was introduced. */
380 #define R(ADDRESS, REG, FEATURE) \
381 case ADDRESS: \
382 if (tricore_feature(env, FEATURE)) { \
383 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
384 } \
385 break;
386 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
387 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
388 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
389 {
390 /* since we're caching PSW make this a special case */
391 if (offset == 0xfe04) {
392 gen_helper_psw_read(ret, cpu_env);
393 } else {
394 switch (offset) {
395 #include "csfr.def"
396 }
397 }
398 }
399 #undef R
400 #undef A
401 #undef E
402
403 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
404 since no execption occurs */
405 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
406 case ADDRESS: \
407 if (tricore_feature(env, FEATURE)) { \
408 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
409 } \
410 break;
411 /* Endinit protected registers
412 TODO: Since the endinit bit is in a register of a not yet implemented
413 watchdog device, we handle endinit protected registers like
414 all-access registers for now. */
415 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
416 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
417 int32_t offset)
418 {
419 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
420 /* since we're caching PSW make this a special case */
421 if (offset == 0xfe04) {
422 gen_helper_psw_write(cpu_env, r1);
423 } else {
424 switch (offset) {
425 #include "csfr.def"
426 }
427 }
428 } else {
429 /* generate privilege trap */
430 }
431 }
432
433 /* Functions for arithmetic instructions */
434
435 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
436 {
437 TCGv t0 = tcg_temp_new_i32();
438 TCGv result = tcg_temp_new_i32();
439 /* Addition and set V/SV bits */
440 tcg_gen_add_tl(result, r1, r2);
441 /* calc V bit */
442 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
443 tcg_gen_xor_tl(t0, r1, r2);
444 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
445 /* Calc SV bit */
446 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
447 /* Calc AV/SAV bits */
448 tcg_gen_add_tl(cpu_PSW_AV, result, result);
449 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
450 /* calc SAV */
451 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
452 /* write back result */
453 tcg_gen_mov_tl(ret, result);
454
455 tcg_temp_free(result);
456 tcg_temp_free(t0);
457 }
458
459 static inline void
460 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
461 {
462 TCGv temp = tcg_temp_new();
463 TCGv_i64 t0 = tcg_temp_new_i64();
464 TCGv_i64 t1 = tcg_temp_new_i64();
465 TCGv_i64 result = tcg_temp_new_i64();
466
467 tcg_gen_add_i64(result, r1, r2);
468 /* calc v bit */
469 tcg_gen_xor_i64(t1, result, r1);
470 tcg_gen_xor_i64(t0, r1, r2);
471 tcg_gen_andc_i64(t1, t1, t0);
472 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
473 /* calc SV bit */
474 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
475 /* calc AV/SAV bits */
476 tcg_gen_extrh_i64_i32(temp, result);
477 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
478 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
479 /* calc SAV */
480 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
481 /* write back result */
482 tcg_gen_mov_i64(ret, result);
483
484 tcg_temp_free(temp);
485 tcg_temp_free_i64(result);
486 tcg_temp_free_i64(t0);
487 tcg_temp_free_i64(t1);
488 }
489
490 static inline void
491 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
492 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
493 void(*op2)(TCGv, TCGv, TCGv))
494 {
495 TCGv temp = tcg_temp_new();
496 TCGv temp2 = tcg_temp_new();
497 TCGv temp3 = tcg_temp_new();
498 TCGv temp4 = tcg_temp_new();
499
500 (*op1)(temp, r1_low, r2);
501 /* calc V0 bit */
502 tcg_gen_xor_tl(temp2, temp, r1_low);
503 tcg_gen_xor_tl(temp3, r1_low, r2);
504 if (op1 == tcg_gen_add_tl) {
505 tcg_gen_andc_tl(temp2, temp2, temp3);
506 } else {
507 tcg_gen_and_tl(temp2, temp2, temp3);
508 }
509
510 (*op2)(temp3, r1_high, r3);
511 /* calc V1 bit */
512 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
513 tcg_gen_xor_tl(temp4, r1_high, r3);
514 if (op2 == tcg_gen_add_tl) {
515 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
516 } else {
517 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
518 }
519 /* combine V0/V1 bits */
520 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
521 /* calc sv bit */
522 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
523 /* write result */
524 tcg_gen_mov_tl(ret_low, temp);
525 tcg_gen_mov_tl(ret_high, temp3);
526 /* calc AV bit */
527 tcg_gen_add_tl(temp, ret_low, ret_low);
528 tcg_gen_xor_tl(temp, temp, ret_low);
529 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
530 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
531 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
532 /* calc SAV bit */
533 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
534
535 tcg_temp_free(temp);
536 tcg_temp_free(temp2);
537 tcg_temp_free(temp3);
538 tcg_temp_free(temp4);
539 }
540
541 /* ret = r2 + (r1 * r3); */
542 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
543 {
544 TCGv_i64 t1 = tcg_temp_new_i64();
545 TCGv_i64 t2 = tcg_temp_new_i64();
546 TCGv_i64 t3 = tcg_temp_new_i64();
547
548 tcg_gen_ext_i32_i64(t1, r1);
549 tcg_gen_ext_i32_i64(t2, r2);
550 tcg_gen_ext_i32_i64(t3, r3);
551
552 tcg_gen_mul_i64(t1, t1, t3);
553 tcg_gen_add_i64(t1, t2, t1);
554
555 tcg_gen_extrl_i64_i32(ret, t1);
556 /* calc V
557 t1 > 0x7fffffff */
558 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
559 /* t1 < -0x80000000 */
560 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
561 tcg_gen_or_i64(t2, t2, t3);
562 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
563 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
564 /* Calc SV bit */
565 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
566 /* Calc AV/SAV bits */
567 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
568 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
569 /* calc SAV */
570 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
571
572 tcg_temp_free_i64(t1);
573 tcg_temp_free_i64(t2);
574 tcg_temp_free_i64(t3);
575 }
576
577 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
578 {
579 TCGv temp = tcg_const_i32(con);
580 gen_madd32_d(ret, r1, r2, temp);
581 tcg_temp_free(temp);
582 }
583
584 static inline void
585 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
586 TCGv r3)
587 {
588 TCGv t1 = tcg_temp_new();
589 TCGv t2 = tcg_temp_new();
590 TCGv t3 = tcg_temp_new();
591 TCGv t4 = tcg_temp_new();
592
593 tcg_gen_muls2_tl(t1, t2, r1, r3);
594 /* only the add can overflow */
595 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
596 /* calc V bit */
597 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
598 tcg_gen_xor_tl(t1, r2_high, t2);
599 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
600 /* Calc SV bit */
601 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
602 /* Calc AV/SAV bits */
603 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
604 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
605 /* calc SAV */
606 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
607 /* write back the result */
608 tcg_gen_mov_tl(ret_low, t3);
609 tcg_gen_mov_tl(ret_high, t4);
610
611 tcg_temp_free(t1);
612 tcg_temp_free(t2);
613 tcg_temp_free(t3);
614 tcg_temp_free(t4);
615 }
616
617 static inline void
618 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
619 TCGv r3)
620 {
621 TCGv_i64 t1 = tcg_temp_new_i64();
622 TCGv_i64 t2 = tcg_temp_new_i64();
623 TCGv_i64 t3 = tcg_temp_new_i64();
624
625 tcg_gen_extu_i32_i64(t1, r1);
626 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
627 tcg_gen_extu_i32_i64(t3, r3);
628
629 tcg_gen_mul_i64(t1, t1, t3);
630 tcg_gen_add_i64(t2, t2, t1);
631 /* write back result */
632 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
633 /* only the add overflows, if t2 < t1
634 calc V bit */
635 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
636 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
637 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
638 /* Calc SV bit */
639 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
640 /* Calc AV/SAV bits */
641 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
642 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
643 /* calc SAV */
644 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
645
646 tcg_temp_free_i64(t1);
647 tcg_temp_free_i64(t2);
648 tcg_temp_free_i64(t3);
649 }
650
651 static inline void
652 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
653 int32_t con)
654 {
655 TCGv temp = tcg_const_i32(con);
656 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
657 tcg_temp_free(temp);
658 }
659
660 static inline void
661 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
662 int32_t con)
663 {
664 TCGv temp = tcg_const_i32(con);
665 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
666 tcg_temp_free(temp);
667 }
668
669 static inline void
670 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
671 TCGv r3, uint32_t n, uint32_t mode)
672 {
673 TCGv temp = tcg_const_i32(n);
674 TCGv temp2 = tcg_temp_new();
675 TCGv_i64 temp64 = tcg_temp_new_i64();
676 switch (mode) {
677 case MODE_LL:
678 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
679 break;
680 case MODE_LU:
681 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
682 break;
683 case MODE_UL:
684 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
685 break;
686 case MODE_UU:
687 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
688 break;
689 }
690 tcg_gen_extr_i64_i32(temp, temp2, temp64);
691 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
692 tcg_gen_add_tl, tcg_gen_add_tl);
693 tcg_temp_free(temp);
694 tcg_temp_free(temp2);
695 tcg_temp_free_i64(temp64);
696 }
697
698 static inline void
699 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
700 TCGv r3, uint32_t n, uint32_t mode)
701 {
702 TCGv temp = tcg_const_i32(n);
703 TCGv temp2 = tcg_temp_new();
704 TCGv_i64 temp64 = tcg_temp_new_i64();
705 switch (mode) {
706 case MODE_LL:
707 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
708 break;
709 case MODE_LU:
710 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
711 break;
712 case MODE_UL:
713 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
714 break;
715 case MODE_UU:
716 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
717 break;
718 }
719 tcg_gen_extr_i64_i32(temp, temp2, temp64);
720 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
721 tcg_gen_sub_tl, tcg_gen_add_tl);
722 tcg_temp_free(temp);
723 tcg_temp_free(temp2);
724 tcg_temp_free_i64(temp64);
725 }
726
727 static inline void
728 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
729 TCGv r3, uint32_t n, uint32_t mode)
730 {
731 TCGv temp = tcg_const_i32(n);
732 TCGv_i64 temp64 = tcg_temp_new_i64();
733 TCGv_i64 temp64_2 = tcg_temp_new_i64();
734 TCGv_i64 temp64_3 = tcg_temp_new_i64();
735 switch (mode) {
736 case MODE_LL:
737 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
738 break;
739 case MODE_LU:
740 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
741 break;
742 case MODE_UL:
743 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
744 break;
745 case MODE_UU:
746 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
747 break;
748 }
749 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
750 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
751 tcg_gen_ext32s_i64(temp64, temp64); /* low */
752 tcg_gen_sub_i64(temp64, temp64_2, temp64);
753 tcg_gen_shli_i64(temp64, temp64, 16);
754
755 gen_add64_d(temp64_2, temp64_3, temp64);
756 /* write back result */
757 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
758
759 tcg_temp_free(temp);
760 tcg_temp_free_i64(temp64);
761 tcg_temp_free_i64(temp64_2);
762 tcg_temp_free_i64(temp64_3);
763 }
764
765 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
766
767 static inline void
768 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
769 TCGv r3, uint32_t n, uint32_t mode)
770 {
771 TCGv temp = tcg_const_i32(n);
772 TCGv temp2 = tcg_temp_new();
773 TCGv temp3 = tcg_temp_new();
774 TCGv_i64 temp64 = tcg_temp_new_i64();
775
776 switch (mode) {
777 case MODE_LL:
778 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
779 break;
780 case MODE_LU:
781 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
782 break;
783 case MODE_UL:
784 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
785 break;
786 case MODE_UU:
787 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
788 break;
789 }
790 tcg_gen_extr_i64_i32(temp, temp2, temp64);
791 gen_adds(ret_low, r1_low, temp);
792 tcg_gen_mov_tl(temp, cpu_PSW_V);
793 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
794 gen_adds(ret_high, r1_high, temp2);
795 /* combine v bits */
796 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
797 /* combine av bits */
798 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
799
800 tcg_temp_free(temp);
801 tcg_temp_free(temp2);
802 tcg_temp_free(temp3);
803 tcg_temp_free_i64(temp64);
804
805 }
806
807 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
808
809 static inline void
810 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
811 TCGv r3, uint32_t n, uint32_t mode)
812 {
813 TCGv temp = tcg_const_i32(n);
814 TCGv temp2 = tcg_temp_new();
815 TCGv temp3 = tcg_temp_new();
816 TCGv_i64 temp64 = tcg_temp_new_i64();
817
818 switch (mode) {
819 case MODE_LL:
820 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
821 break;
822 case MODE_LU:
823 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
824 break;
825 case MODE_UL:
826 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
827 break;
828 case MODE_UU:
829 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
830 break;
831 }
832 tcg_gen_extr_i64_i32(temp, temp2, temp64);
833 gen_subs(ret_low, r1_low, temp);
834 tcg_gen_mov_tl(temp, cpu_PSW_V);
835 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
836 gen_adds(ret_high, r1_high, temp2);
837 /* combine v bits */
838 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
839 /* combine av bits */
840 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
841
842 tcg_temp_free(temp);
843 tcg_temp_free(temp2);
844 tcg_temp_free(temp3);
845 tcg_temp_free_i64(temp64);
846
847 }
848
849 static inline void
850 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
851 TCGv r3, uint32_t n, uint32_t mode)
852 {
853 TCGv temp = tcg_const_i32(n);
854 TCGv_i64 temp64 = tcg_temp_new_i64();
855 TCGv_i64 temp64_2 = tcg_temp_new_i64();
856
857 switch (mode) {
858 case MODE_LL:
859 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
860 break;
861 case MODE_LU:
862 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
863 break;
864 case MODE_UL:
865 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
866 break;
867 case MODE_UU:
868 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
869 break;
870 }
871 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
872 tcg_gen_ext32s_i64(temp64, temp64); /* low */
873 tcg_gen_sub_i64(temp64, temp64_2, temp64);
874 tcg_gen_shli_i64(temp64, temp64, 16);
875 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
876
877 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
878 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
879
880 tcg_temp_free(temp);
881 tcg_temp_free_i64(temp64);
882 tcg_temp_free_i64(temp64_2);
883 }
884
885
886 static inline void
887 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
888 TCGv r3, uint32_t n, uint32_t mode)
889 {
890 TCGv temp = tcg_const_i32(n);
891 TCGv_i64 temp64 = tcg_temp_new_i64();
892 TCGv_i64 temp64_2 = tcg_temp_new_i64();
893 TCGv_i64 temp64_3 = tcg_temp_new_i64();
894 switch (mode) {
895 case MODE_LL:
896 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
897 break;
898 case MODE_LU:
899 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
900 break;
901 case MODE_UL:
902 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
903 break;
904 case MODE_UU:
905 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
906 break;
907 }
908 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
909 gen_add64_d(temp64_3, temp64_2, temp64);
910 /* write back result */
911 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
912
913 tcg_temp_free(temp);
914 tcg_temp_free_i64(temp64);
915 tcg_temp_free_i64(temp64_2);
916 tcg_temp_free_i64(temp64_3);
917 }
918
919 static inline void
920 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
921 TCGv r3, uint32_t n, uint32_t mode)
922 {
923 TCGv temp = tcg_const_i32(n);
924 TCGv_i64 temp64 = tcg_temp_new_i64();
925 TCGv_i64 temp64_2 = tcg_temp_new_i64();
926 switch (mode) {
927 case MODE_LL:
928 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
929 break;
930 case MODE_LU:
931 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
932 break;
933 case MODE_UL:
934 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
935 break;
936 case MODE_UU:
937 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
938 break;
939 }
940 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
941 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
942 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
943
944 tcg_temp_free(temp);
945 tcg_temp_free_i64(temp64);
946 tcg_temp_free_i64(temp64_2);
947 }
948
949 static inline void
950 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
951 uint32_t mode)
952 {
953 TCGv temp = tcg_const_i32(n);
954 TCGv_i64 temp64 = tcg_temp_new_i64();
955 switch (mode) {
956 case MODE_LL:
957 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
958 break;
959 case MODE_LU:
960 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
961 break;
962 case MODE_UL:
963 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
964 break;
965 case MODE_UU:
966 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
967 break;
968 }
969 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
970
971 tcg_temp_free(temp);
972 tcg_temp_free_i64(temp64);
973 }
974
975 static inline void
976 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
977 {
978 TCGv temp = tcg_temp_new();
979 TCGv temp2 = tcg_temp_new();
980
981 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
982 tcg_gen_shli_tl(temp, r1, 16);
983 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
984
985 tcg_temp_free(temp);
986 tcg_temp_free(temp2);
987 }
988
989 static inline void
990 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
991 {
992 TCGv temp = tcg_const_i32(n);
993 TCGv temp2 = tcg_temp_new();
994 TCGv_i64 temp64 = tcg_temp_new_i64();
995 switch (mode) {
996 case MODE_LL:
997 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
998 break;
999 case MODE_LU:
1000 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1001 break;
1002 case MODE_UL:
1003 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1004 break;
1005 case MODE_UU:
1006 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1007 break;
1008 }
1009 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1010 tcg_gen_shli_tl(temp, r1, 16);
1011 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
1012
1013 tcg_temp_free(temp);
1014 tcg_temp_free(temp2);
1015 tcg_temp_free_i64(temp64);
1016 }
1017
1018
1019 static inline void
1020 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1021 uint32_t n, uint32_t mode)
1022 {
1023 TCGv temp = tcg_const_i32(n);
1024 TCGv_i64 temp64 = tcg_temp_new_i64();
1025 switch (mode) {
1026 case MODE_LL:
1027 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1028 break;
1029 case MODE_LU:
1030 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1031 break;
1032 case MODE_UL:
1033 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1034 break;
1035 case MODE_UU:
1036 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1037 break;
1038 }
1039 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1040
1041 tcg_temp_free(temp);
1042 tcg_temp_free_i64(temp64);
1043 }
1044
1045 static inline void
1046 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1047 {
1048 TCGv temp = tcg_temp_new();
1049 TCGv temp2 = tcg_temp_new();
1050
1051 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1052 tcg_gen_shli_tl(temp, r1, 16);
1053 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1054
1055 tcg_temp_free(temp);
1056 tcg_temp_free(temp2);
1057 }
1058
1059 static inline void
1060 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1061 {
1062 TCGv temp = tcg_const_i32(n);
1063 TCGv temp2 = tcg_temp_new();
1064 TCGv_i64 temp64 = tcg_temp_new_i64();
1065 switch (mode) {
1066 case MODE_LL:
1067 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1068 break;
1069 case MODE_LU:
1070 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1071 break;
1072 case MODE_UL:
1073 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1074 break;
1075 case MODE_UU:
1076 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1077 break;
1078 }
1079 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1080 tcg_gen_shli_tl(temp, r1, 16);
1081 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1082
1083 tcg_temp_free(temp);
1084 tcg_temp_free(temp2);
1085 tcg_temp_free_i64(temp64);
1086 }
1087
1088 static inline void
1089 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1090 {
1091 TCGv temp = tcg_const_i32(n);
1092 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1093 tcg_temp_free(temp);
1094 }
1095
1096 static inline void
1097 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1098 {
1099 TCGv temp = tcg_const_i32(n);
1100 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1101 tcg_temp_free(temp);
1102 }
1103
1104 static inline void
1105 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1106 uint32_t up_shift, CPUTriCoreState *env)
1107 {
1108 TCGv temp = tcg_temp_new();
1109 TCGv temp2 = tcg_temp_new();
1110 TCGv temp3 = tcg_temp_new();
1111 TCGv_i64 t1 = tcg_temp_new_i64();
1112 TCGv_i64 t2 = tcg_temp_new_i64();
1113 TCGv_i64 t3 = tcg_temp_new_i64();
1114
1115 tcg_gen_ext_i32_i64(t2, arg2);
1116 tcg_gen_ext_i32_i64(t3, arg3);
1117
1118 tcg_gen_mul_i64(t2, t2, t3);
1119 tcg_gen_shli_i64(t2, t2, n);
1120
1121 tcg_gen_ext_i32_i64(t1, arg1);
1122 tcg_gen_sari_i64(t2, t2, up_shift);
1123
1124 tcg_gen_add_i64(t3, t1, t2);
1125 tcg_gen_extrl_i64_i32(temp3, t3);
1126 /* calc v bit */
1127 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1128 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1129 tcg_gen_or_i64(t1, t1, t2);
1130 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1131 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1132 /* We produce an overflow on the host if the mul before was
1133 (0x80000000 * 0x80000000) << 1). If this is the
1134 case, we negate the ovf. */
1135 if (n == 1) {
1136 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1137 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1138 tcg_gen_and_tl(temp, temp, temp2);
1139 tcg_gen_shli_tl(temp, temp, 31);
1140 /* negate v bit, if special condition */
1141 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1142 }
1143 /* Calc SV bit */
1144 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1145 /* Calc AV/SAV bits */
1146 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1147 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1148 /* calc SAV */
1149 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1150 /* write back result */
1151 tcg_gen_mov_tl(ret, temp3);
1152
1153 tcg_temp_free(temp);
1154 tcg_temp_free(temp2);
1155 tcg_temp_free(temp3);
1156 tcg_temp_free_i64(t1);
1157 tcg_temp_free_i64(t2);
1158 tcg_temp_free_i64(t3);
1159 }
1160
1161 static inline void
1162 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1163 {
1164 TCGv temp = tcg_temp_new();
1165 TCGv temp2 = tcg_temp_new();
1166 if (n == 0) {
1167 tcg_gen_mul_tl(temp, arg2, arg3);
1168 } else { /* n is expected to be 1 */
1169 tcg_gen_mul_tl(temp, arg2, arg3);
1170 tcg_gen_shli_tl(temp, temp, 1);
1171 /* catch special case r1 = r2 = 0x8000 */
1172 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1173 tcg_gen_sub_tl(temp, temp, temp2);
1174 }
1175 gen_add_d(ret, arg1, temp);
1176
1177 tcg_temp_free(temp);
1178 tcg_temp_free(temp2);
1179 }
1180
1181 static inline void
1182 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1183 {
1184 TCGv temp = tcg_temp_new();
1185 TCGv temp2 = tcg_temp_new();
1186 if (n == 0) {
1187 tcg_gen_mul_tl(temp, arg2, arg3);
1188 } else { /* n is expected to be 1 */
1189 tcg_gen_mul_tl(temp, arg2, arg3);
1190 tcg_gen_shli_tl(temp, temp, 1);
1191 /* catch special case r1 = r2 = 0x8000 */
1192 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1193 tcg_gen_sub_tl(temp, temp, temp2);
1194 }
1195 gen_adds(ret, arg1, temp);
1196
1197 tcg_temp_free(temp);
1198 tcg_temp_free(temp2);
1199 }
1200
1201 static inline void
1202 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1203 TCGv arg3, uint32_t n)
1204 {
1205 TCGv temp = tcg_temp_new();
1206 TCGv temp2 = tcg_temp_new();
1207 TCGv_i64 t1 = tcg_temp_new_i64();
1208 TCGv_i64 t2 = tcg_temp_new_i64();
1209 TCGv_i64 t3 = tcg_temp_new_i64();
1210
1211 if (n == 0) {
1212 tcg_gen_mul_tl(temp, arg2, arg3);
1213 } else { /* n is expected to be 1 */
1214 tcg_gen_mul_tl(temp, arg2, arg3);
1215 tcg_gen_shli_tl(temp, temp, 1);
1216 /* catch special case r1 = r2 = 0x8000 */
1217 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1218 tcg_gen_sub_tl(temp, temp, temp2);
1219 }
1220 tcg_gen_ext_i32_i64(t2, temp);
1221 tcg_gen_shli_i64(t2, t2, 16);
1222 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1223 gen_add64_d(t3, t1, t2);
1224 /* write back result */
1225 tcg_gen_extr_i64_i32(rl, rh, t3);
1226
1227 tcg_temp_free_i64(t1);
1228 tcg_temp_free_i64(t2);
1229 tcg_temp_free_i64(t3);
1230 tcg_temp_free(temp);
1231 tcg_temp_free(temp2);
1232 }
1233
1234 static inline void
1235 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1236 TCGv arg3, uint32_t n)
1237 {
1238 TCGv temp = tcg_temp_new();
1239 TCGv temp2 = tcg_temp_new();
1240 TCGv_i64 t1 = tcg_temp_new_i64();
1241 TCGv_i64 t2 = tcg_temp_new_i64();
1242
1243 if (n == 0) {
1244 tcg_gen_mul_tl(temp, arg2, arg3);
1245 } else { /* n is expected to be 1 */
1246 tcg_gen_mul_tl(temp, arg2, arg3);
1247 tcg_gen_shli_tl(temp, temp, 1);
1248 /* catch special case r1 = r2 = 0x8000 */
1249 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1250 tcg_gen_sub_tl(temp, temp, temp2);
1251 }
1252 tcg_gen_ext_i32_i64(t2, temp);
1253 tcg_gen_shli_i64(t2, t2, 16);
1254 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1255
1256 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1257 tcg_gen_extr_i64_i32(rl, rh, t1);
1258
1259 tcg_temp_free(temp);
1260 tcg_temp_free(temp2);
1261 tcg_temp_free_i64(t1);
1262 tcg_temp_free_i64(t2);
1263 }
1264
1265 static inline void
1266 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1267 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1268 {
1269 TCGv_i64 t1 = tcg_temp_new_i64();
1270 TCGv_i64 t2 = tcg_temp_new_i64();
1271 TCGv_i64 t3 = tcg_temp_new_i64();
1272 TCGv_i64 t4 = tcg_temp_new_i64();
1273 TCGv temp, temp2;
1274
1275 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1276 tcg_gen_ext_i32_i64(t2, arg2);
1277 tcg_gen_ext_i32_i64(t3, arg3);
1278
1279 tcg_gen_mul_i64(t2, t2, t3);
1280 if (n != 0) {
1281 tcg_gen_shli_i64(t2, t2, 1);
1282 }
1283 tcg_gen_add_i64(t4, t1, t2);
1284 /* calc v bit */
1285 tcg_gen_xor_i64(t3, t4, t1);
1286 tcg_gen_xor_i64(t2, t1, t2);
1287 tcg_gen_andc_i64(t3, t3, t2);
1288 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1289 /* We produce an overflow on the host if the mul before was
1290 (0x80000000 * 0x80000000) << 1). If this is the
1291 case, we negate the ovf. */
1292 if (n == 1) {
1293 temp = tcg_temp_new();
1294 temp2 = tcg_temp_new();
1295 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1296 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1297 tcg_gen_and_tl(temp, temp, temp2);
1298 tcg_gen_shli_tl(temp, temp, 31);
1299 /* negate v bit, if special condition */
1300 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1301
1302 tcg_temp_free(temp);
1303 tcg_temp_free(temp2);
1304 }
1305 /* write back result */
1306 tcg_gen_extr_i64_i32(rl, rh, t4);
1307 /* Calc SV bit */
1308 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1309 /* Calc AV/SAV bits */
1310 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1311 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1312 /* calc SAV */
1313 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1314
1315 tcg_temp_free_i64(t1);
1316 tcg_temp_free_i64(t2);
1317 tcg_temp_free_i64(t3);
1318 tcg_temp_free_i64(t4);
1319 }
1320
1321 static inline void
1322 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1323 uint32_t up_shift)
1324 {
1325 TCGv_i64 t1 = tcg_temp_new_i64();
1326 TCGv_i64 t2 = tcg_temp_new_i64();
1327 TCGv_i64 t3 = tcg_temp_new_i64();
1328
1329 tcg_gen_ext_i32_i64(t1, arg1);
1330 tcg_gen_ext_i32_i64(t2, arg2);
1331 tcg_gen_ext_i32_i64(t3, arg3);
1332
1333 tcg_gen_mul_i64(t2, t2, t3);
1334 tcg_gen_sari_i64(t2, t2, up_shift - n);
1335
1336 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1337
1338 tcg_temp_free_i64(t1);
1339 tcg_temp_free_i64(t2);
1340 tcg_temp_free_i64(t3);
1341 }
1342
1343 static inline void
1344 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1345 TCGv arg3, uint32_t n)
1346 {
1347 TCGv_i64 r1 = tcg_temp_new_i64();
1348 TCGv temp = tcg_const_i32(n);
1349
1350 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1351 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1352 tcg_gen_extr_i64_i32(rl, rh, r1);
1353
1354 tcg_temp_free_i64(r1);
1355 tcg_temp_free(temp);
1356 }
1357 /* ret = r2 - (r1 * r3); */
1358 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1359 {
1360 TCGv_i64 t1 = tcg_temp_new_i64();
1361 TCGv_i64 t2 = tcg_temp_new_i64();
1362 TCGv_i64 t3 = tcg_temp_new_i64();
1363
1364 tcg_gen_ext_i32_i64(t1, r1);
1365 tcg_gen_ext_i32_i64(t2, r2);
1366 tcg_gen_ext_i32_i64(t3, r3);
1367
1368 tcg_gen_mul_i64(t1, t1, t3);
1369 tcg_gen_sub_i64(t1, t2, t1);
1370
1371 tcg_gen_extrl_i64_i32(ret, t1);
1372 /* calc V
1373 t2 > 0x7fffffff */
1374 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1375 /* result < -0x80000000 */
1376 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1377 tcg_gen_or_i64(t2, t2, t3);
1378 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1379 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1380
1381 /* Calc SV bit */
1382 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1383 /* Calc AV/SAV bits */
1384 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1385 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1386 /* calc SAV */
1387 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1388
1389 tcg_temp_free_i64(t1);
1390 tcg_temp_free_i64(t2);
1391 tcg_temp_free_i64(t3);
1392 }
1393
1394 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1395 {
1396 TCGv temp = tcg_const_i32(con);
1397 gen_msub32_d(ret, r1, r2, temp);
1398 tcg_temp_free(temp);
1399 }
1400
1401 static inline void
1402 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1403 TCGv r3)
1404 {
1405 TCGv t1 = tcg_temp_new();
1406 TCGv t2 = tcg_temp_new();
1407 TCGv t3 = tcg_temp_new();
1408 TCGv t4 = tcg_temp_new();
1409
1410 tcg_gen_muls2_tl(t1, t2, r1, r3);
1411 /* only the sub can overflow */
1412 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1413 /* calc V bit */
1414 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1415 tcg_gen_xor_tl(t1, r2_high, t2);
1416 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1417 /* Calc SV bit */
1418 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1419 /* Calc AV/SAV bits */
1420 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1421 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1422 /* calc SAV */
1423 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1424 /* write back the result */
1425 tcg_gen_mov_tl(ret_low, t3);
1426 tcg_gen_mov_tl(ret_high, t4);
1427
1428 tcg_temp_free(t1);
1429 tcg_temp_free(t2);
1430 tcg_temp_free(t3);
1431 tcg_temp_free(t4);
1432 }
1433
1434 static inline void
1435 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1436 int32_t con)
1437 {
1438 TCGv temp = tcg_const_i32(con);
1439 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1440 tcg_temp_free(temp);
1441 }
1442
1443 static inline void
1444 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1445 TCGv r3)
1446 {
1447 TCGv_i64 t1 = tcg_temp_new_i64();
1448 TCGv_i64 t2 = tcg_temp_new_i64();
1449 TCGv_i64 t3 = tcg_temp_new_i64();
1450
1451 tcg_gen_extu_i32_i64(t1, r1);
1452 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1453 tcg_gen_extu_i32_i64(t3, r3);
1454
1455 tcg_gen_mul_i64(t1, t1, t3);
1456 tcg_gen_sub_i64(t3, t2, t1);
1457 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1458 /* calc V bit, only the sub can overflow, if t1 > t2 */
1459 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1460 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1461 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1462 /* Calc SV bit */
1463 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1464 /* Calc AV/SAV bits */
1465 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1466 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1467 /* calc SAV */
1468 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1469
1470 tcg_temp_free_i64(t1);
1471 tcg_temp_free_i64(t2);
1472 tcg_temp_free_i64(t3);
1473 }
1474
1475 static inline void
1476 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1477 int32_t con)
1478 {
1479 TCGv temp = tcg_const_i32(con);
1480 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1481 tcg_temp_free(temp);
1482 }
1483
1484 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1485 {
1486 TCGv temp = tcg_const_i32(r2);
1487 gen_add_d(ret, r1, temp);
1488 tcg_temp_free(temp);
1489 }
1490 /* calculate the carry bit too */
1491 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1492 {
1493 TCGv t0 = tcg_temp_new_i32();
1494 TCGv result = tcg_temp_new_i32();
1495
1496 tcg_gen_movi_tl(t0, 0);
1497 /* Addition and set C/V/SV bits */
1498 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1499 /* calc V bit */
1500 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1501 tcg_gen_xor_tl(t0, r1, r2);
1502 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1503 /* Calc SV bit */
1504 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1505 /* Calc AV/SAV bits */
1506 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1507 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1508 /* calc SAV */
1509 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1510 /* write back result */
1511 tcg_gen_mov_tl(ret, result);
1512
1513 tcg_temp_free(result);
1514 tcg_temp_free(t0);
1515 }
1516
1517 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1518 {
1519 TCGv temp = tcg_const_i32(con);
1520 gen_add_CC(ret, r1, temp);
1521 tcg_temp_free(temp);
1522 }
1523
1524 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1525 {
1526 TCGv carry = tcg_temp_new_i32();
1527 TCGv t0 = tcg_temp_new_i32();
1528 TCGv result = tcg_temp_new_i32();
1529
1530 tcg_gen_movi_tl(t0, 0);
1531 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1532 /* Addition, carry and set C/V/SV bits */
1533 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1534 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1535 /* calc V bit */
1536 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1537 tcg_gen_xor_tl(t0, r1, r2);
1538 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1539 /* Calc SV bit */
1540 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1541 /* Calc AV/SAV bits */
1542 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1543 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1544 /* calc SAV */
1545 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1546 /* write back result */
1547 tcg_gen_mov_tl(ret, result);
1548
1549 tcg_temp_free(result);
1550 tcg_temp_free(t0);
1551 tcg_temp_free(carry);
1552 }
1553
1554 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1555 {
1556 TCGv temp = tcg_const_i32(con);
1557 gen_addc_CC(ret, r1, temp);
1558 tcg_temp_free(temp);
1559 }
1560
1561 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1562 TCGv r4)
1563 {
1564 TCGv temp = tcg_temp_new();
1565 TCGv temp2 = tcg_temp_new();
1566 TCGv result = tcg_temp_new();
1567 TCGv mask = tcg_temp_new();
1568 TCGv t0 = tcg_const_i32(0);
1569
1570 /* create mask for sticky bits */
1571 tcg_gen_setcond_tl(cond, mask, r4, t0);
1572 tcg_gen_shli_tl(mask, mask, 31);
1573
1574 tcg_gen_add_tl(result, r1, r2);
1575 /* Calc PSW_V */
1576 tcg_gen_xor_tl(temp, result, r1);
1577 tcg_gen_xor_tl(temp2, r1, r2);
1578 tcg_gen_andc_tl(temp, temp, temp2);
1579 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1580 /* Set PSW_SV */
1581 tcg_gen_and_tl(temp, temp, mask);
1582 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1583 /* calc AV bit */
1584 tcg_gen_add_tl(temp, result, result);
1585 tcg_gen_xor_tl(temp, temp, result);
1586 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1587 /* calc SAV bit */
1588 tcg_gen_and_tl(temp, temp, mask);
1589 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1590 /* write back result */
1591 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1592
1593 tcg_temp_free(t0);
1594 tcg_temp_free(temp);
1595 tcg_temp_free(temp2);
1596 tcg_temp_free(result);
1597 tcg_temp_free(mask);
1598 }
1599
1600 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1601 TCGv r3, TCGv r4)
1602 {
1603 TCGv temp = tcg_const_i32(r2);
1604 gen_cond_add(cond, r1, temp, r3, r4);
1605 tcg_temp_free(temp);
1606 }
1607
1608 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1609 {
1610 TCGv temp = tcg_temp_new_i32();
1611 TCGv result = tcg_temp_new_i32();
1612
1613 tcg_gen_sub_tl(result, r1, r2);
1614 /* calc V bit */
1615 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1616 tcg_gen_xor_tl(temp, r1, r2);
1617 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1618 /* calc SV bit */
1619 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1620 /* Calc AV bit */
1621 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1622 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1623 /* calc SAV bit */
1624 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1625 /* write back result */
1626 tcg_gen_mov_tl(ret, result);
1627
1628 tcg_temp_free(temp);
1629 tcg_temp_free(result);
1630 }
1631
1632 static inline void
1633 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1634 {
1635 TCGv temp = tcg_temp_new();
1636 TCGv_i64 t0 = tcg_temp_new_i64();
1637 TCGv_i64 t1 = tcg_temp_new_i64();
1638 TCGv_i64 result = tcg_temp_new_i64();
1639
1640 tcg_gen_sub_i64(result, r1, r2);
1641 /* calc v bit */
1642 tcg_gen_xor_i64(t1, result, r1);
1643 tcg_gen_xor_i64(t0, r1, r2);
1644 tcg_gen_and_i64(t1, t1, t0);
1645 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1646 /* calc SV bit */
1647 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1648 /* calc AV/SAV bits */
1649 tcg_gen_extrh_i64_i32(temp, result);
1650 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1651 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1652 /* calc SAV */
1653 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1654 /* write back result */
1655 tcg_gen_mov_i64(ret, result);
1656
1657 tcg_temp_free(temp);
1658 tcg_temp_free_i64(result);
1659 tcg_temp_free_i64(t0);
1660 tcg_temp_free_i64(t1);
1661 }
1662
1663 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1664 {
1665 TCGv result = tcg_temp_new();
1666 TCGv temp = tcg_temp_new();
1667
1668 tcg_gen_sub_tl(result, r1, r2);
1669 /* calc C bit */
1670 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1671 /* calc V bit */
1672 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1673 tcg_gen_xor_tl(temp, r1, r2);
1674 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1675 /* calc SV bit */
1676 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1677 /* Calc AV bit */
1678 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1679 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1680 /* calc SAV bit */
1681 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1682 /* write back result */
1683 tcg_gen_mov_tl(ret, result);
1684
1685 tcg_temp_free(result);
1686 tcg_temp_free(temp);
1687 }
1688
1689 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1690 {
1691 TCGv temp = tcg_temp_new();
1692 tcg_gen_not_tl(temp, r2);
1693 gen_addc_CC(ret, r1, temp);
1694 tcg_temp_free(temp);
1695 }
1696
1697 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1698 TCGv r4)
1699 {
1700 TCGv temp = tcg_temp_new();
1701 TCGv temp2 = tcg_temp_new();
1702 TCGv result = tcg_temp_new();
1703 TCGv mask = tcg_temp_new();
1704 TCGv t0 = tcg_const_i32(0);
1705
1706 /* create mask for sticky bits */
1707 tcg_gen_setcond_tl(cond, mask, r4, t0);
1708 tcg_gen_shli_tl(mask, mask, 31);
1709
1710 tcg_gen_sub_tl(result, r1, r2);
1711 /* Calc PSW_V */
1712 tcg_gen_xor_tl(temp, result, r1);
1713 tcg_gen_xor_tl(temp2, r1, r2);
1714 tcg_gen_and_tl(temp, temp, temp2);
1715 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1716 /* Set PSW_SV */
1717 tcg_gen_and_tl(temp, temp, mask);
1718 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1719 /* calc AV bit */
1720 tcg_gen_add_tl(temp, result, result);
1721 tcg_gen_xor_tl(temp, temp, result);
1722 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1723 /* calc SAV bit */
1724 tcg_gen_and_tl(temp, temp, mask);
1725 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1726 /* write back result */
1727 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1728
1729 tcg_temp_free(t0);
1730 tcg_temp_free(temp);
1731 tcg_temp_free(temp2);
1732 tcg_temp_free(result);
1733 tcg_temp_free(mask);
1734 }
1735
1736 static inline void
1737 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1738 TCGv r3, uint32_t n, uint32_t mode)
1739 {
1740 TCGv temp = tcg_const_i32(n);
1741 TCGv temp2 = tcg_temp_new();
1742 TCGv_i64 temp64 = tcg_temp_new_i64();
1743 switch (mode) {
1744 case MODE_LL:
1745 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1746 break;
1747 case MODE_LU:
1748 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1749 break;
1750 case MODE_UL:
1751 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1752 break;
1753 case MODE_UU:
1754 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1755 break;
1756 }
1757 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1758 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1759 tcg_gen_sub_tl, tcg_gen_sub_tl);
1760 tcg_temp_free(temp);
1761 tcg_temp_free(temp2);
1762 tcg_temp_free_i64(temp64);
1763 }
1764
1765 static inline void
1766 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1767 TCGv r3, uint32_t n, uint32_t mode)
1768 {
1769 TCGv temp = tcg_const_i32(n);
1770 TCGv temp2 = tcg_temp_new();
1771 TCGv temp3 = tcg_temp_new();
1772 TCGv_i64 temp64 = tcg_temp_new_i64();
1773
1774 switch (mode) {
1775 case MODE_LL:
1776 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1777 break;
1778 case MODE_LU:
1779 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1780 break;
1781 case MODE_UL:
1782 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1783 break;
1784 case MODE_UU:
1785 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1786 break;
1787 }
1788 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1789 gen_subs(ret_low, r1_low, temp);
1790 tcg_gen_mov_tl(temp, cpu_PSW_V);
1791 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1792 gen_subs(ret_high, r1_high, temp2);
1793 /* combine v bits */
1794 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1795 /* combine av bits */
1796 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1797
1798 tcg_temp_free(temp);
1799 tcg_temp_free(temp2);
1800 tcg_temp_free(temp3);
1801 tcg_temp_free_i64(temp64);
1802 }
1803
1804 static inline void
1805 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1806 TCGv r3, uint32_t n, uint32_t mode)
1807 {
1808 TCGv temp = tcg_const_i32(n);
1809 TCGv_i64 temp64 = tcg_temp_new_i64();
1810 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1811 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1812 switch (mode) {
1813 case MODE_LL:
1814 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1815 break;
1816 case MODE_LU:
1817 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1818 break;
1819 case MODE_UL:
1820 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1821 break;
1822 case MODE_UU:
1823 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1824 break;
1825 }
1826 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1827 gen_sub64_d(temp64_3, temp64_2, temp64);
1828 /* write back result */
1829 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1830
1831 tcg_temp_free(temp);
1832 tcg_temp_free_i64(temp64);
1833 tcg_temp_free_i64(temp64_2);
1834 tcg_temp_free_i64(temp64_3);
1835 }
1836
1837 static inline void
1838 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1839 TCGv r3, uint32_t n, uint32_t mode)
1840 {
1841 TCGv temp = tcg_const_i32(n);
1842 TCGv_i64 temp64 = tcg_temp_new_i64();
1843 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1844 switch (mode) {
1845 case MODE_LL:
1846 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1847 break;
1848 case MODE_LU:
1849 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1850 break;
1851 case MODE_UL:
1852 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1853 break;
1854 case MODE_UU:
1855 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1856 break;
1857 }
1858 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1859 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1860 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1861
1862 tcg_temp_free(temp);
1863 tcg_temp_free_i64(temp64);
1864 tcg_temp_free_i64(temp64_2);
1865 }
1866
1867 static inline void
1868 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1869 uint32_t mode)
1870 {
1871 TCGv temp = tcg_const_i32(n);
1872 TCGv_i64 temp64 = tcg_temp_new_i64();
1873 switch (mode) {
1874 case MODE_LL:
1875 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1876 break;
1877 case MODE_LU:
1878 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1879 break;
1880 case MODE_UL:
1881 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1882 break;
1883 case MODE_UU:
1884 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1885 break;
1886 }
1887 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1888
1889 tcg_temp_free(temp);
1890 tcg_temp_free_i64(temp64);
1891 }
1892
1893 static inline void
1894 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1895 {
1896 TCGv temp = tcg_temp_new();
1897 TCGv temp2 = tcg_temp_new();
1898
1899 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1900 tcg_gen_shli_tl(temp, r1, 16);
1901 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1902
1903 tcg_temp_free(temp);
1904 tcg_temp_free(temp2);
1905 }
1906
1907 static inline void
1908 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1909 uint32_t n, uint32_t mode)
1910 {
1911 TCGv temp = tcg_const_i32(n);
1912 TCGv_i64 temp64 = tcg_temp_new_i64();
1913 switch (mode) {
1914 case MODE_LL:
1915 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1916 break;
1917 case MODE_LU:
1918 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1919 break;
1920 case MODE_UL:
1921 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1922 break;
1923 case MODE_UU:
1924 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1925 break;
1926 }
1927 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1928
1929 tcg_temp_free(temp);
1930 tcg_temp_free_i64(temp64);
1931 }
1932
1933 static inline void
1934 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1935 {
1936 TCGv temp = tcg_temp_new();
1937 TCGv temp2 = tcg_temp_new();
1938
1939 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1940 tcg_gen_shli_tl(temp, r1, 16);
1941 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1942
1943 tcg_temp_free(temp);
1944 tcg_temp_free(temp2);
1945 }
1946
1947 static inline void
1948 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1949 {
1950 TCGv temp = tcg_const_i32(n);
1951 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1952 tcg_temp_free(temp);
1953 }
1954
1955 static inline void
1956 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1957 {
1958 TCGv temp = tcg_const_i32(n);
1959 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1960 tcg_temp_free(temp);
1961 }
1962
1963 static inline void
1964 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1965 uint32_t up_shift, CPUTriCoreState *env)
1966 {
1967 TCGv temp = tcg_temp_new();
1968 TCGv temp2 = tcg_temp_new();
1969 TCGv temp3 = tcg_temp_new();
1970 TCGv_i64 t1 = tcg_temp_new_i64();
1971 TCGv_i64 t2 = tcg_temp_new_i64();
1972 TCGv_i64 t3 = tcg_temp_new_i64();
1973 TCGv_i64 t4 = tcg_temp_new_i64();
1974
1975 tcg_gen_ext_i32_i64(t2, arg2);
1976 tcg_gen_ext_i32_i64(t3, arg3);
1977
1978 tcg_gen_mul_i64(t2, t2, t3);
1979
1980 tcg_gen_ext_i32_i64(t1, arg1);
1981 /* if we shift part of the fraction out, we need to round up */
1982 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1983 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1984 tcg_gen_sari_i64(t2, t2, up_shift - n);
1985 tcg_gen_add_i64(t2, t2, t4);
1986
1987 tcg_gen_sub_i64(t3, t1, t2);
1988 tcg_gen_extrl_i64_i32(temp3, t3);
1989 /* calc v bit */
1990 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1991 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1992 tcg_gen_or_i64(t1, t1, t2);
1993 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1994 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1995 /* Calc SV bit */
1996 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1997 /* Calc AV/SAV bits */
1998 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1999 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
2000 /* calc SAV */
2001 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2002 /* write back result */
2003 tcg_gen_mov_tl(ret, temp3);
2004
2005 tcg_temp_free(temp);
2006 tcg_temp_free(temp2);
2007 tcg_temp_free(temp3);
2008 tcg_temp_free_i64(t1);
2009 tcg_temp_free_i64(t2);
2010 tcg_temp_free_i64(t3);
2011 tcg_temp_free_i64(t4);
2012 }
2013
2014 static inline void
2015 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2016 {
2017 TCGv temp = tcg_temp_new();
2018 TCGv temp2 = tcg_temp_new();
2019 if (n == 0) {
2020 tcg_gen_mul_tl(temp, arg2, arg3);
2021 } else { /* n is expected to be 1 */
2022 tcg_gen_mul_tl(temp, arg2, arg3);
2023 tcg_gen_shli_tl(temp, temp, 1);
2024 /* catch special case r1 = r2 = 0x8000 */
2025 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2026 tcg_gen_sub_tl(temp, temp, temp2);
2027 }
2028 gen_sub_d(ret, arg1, temp);
2029
2030 tcg_temp_free(temp);
2031 tcg_temp_free(temp2);
2032 }
2033
2034 static inline void
2035 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2036 {
2037 TCGv temp = tcg_temp_new();
2038 TCGv temp2 = tcg_temp_new();
2039 if (n == 0) {
2040 tcg_gen_mul_tl(temp, arg2, arg3);
2041 } else { /* n is expected to be 1 */
2042 tcg_gen_mul_tl(temp, arg2, arg3);
2043 tcg_gen_shli_tl(temp, temp, 1);
2044 /* catch special case r1 = r2 = 0x8000 */
2045 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2046 tcg_gen_sub_tl(temp, temp, temp2);
2047 }
2048 gen_subs(ret, arg1, temp);
2049
2050 tcg_temp_free(temp);
2051 tcg_temp_free(temp2);
2052 }
2053
2054 static inline void
2055 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2056 TCGv arg3, uint32_t n)
2057 {
2058 TCGv temp = tcg_temp_new();
2059 TCGv temp2 = tcg_temp_new();
2060 TCGv_i64 t1 = tcg_temp_new_i64();
2061 TCGv_i64 t2 = tcg_temp_new_i64();
2062 TCGv_i64 t3 = tcg_temp_new_i64();
2063
2064 if (n == 0) {
2065 tcg_gen_mul_tl(temp, arg2, arg3);
2066 } else { /* n is expected to be 1 */
2067 tcg_gen_mul_tl(temp, arg2, arg3);
2068 tcg_gen_shli_tl(temp, temp, 1);
2069 /* catch special case r1 = r2 = 0x8000 */
2070 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2071 tcg_gen_sub_tl(temp, temp, temp2);
2072 }
2073 tcg_gen_ext_i32_i64(t2, temp);
2074 tcg_gen_shli_i64(t2, t2, 16);
2075 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2076 gen_sub64_d(t3, t1, t2);
2077 /* write back result */
2078 tcg_gen_extr_i64_i32(rl, rh, t3);
2079
2080 tcg_temp_free_i64(t1);
2081 tcg_temp_free_i64(t2);
2082 tcg_temp_free_i64(t3);
2083 tcg_temp_free(temp);
2084 tcg_temp_free(temp2);
2085 }
2086
2087 static inline void
2088 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2089 TCGv arg3, uint32_t n)
2090 {
2091 TCGv temp = tcg_temp_new();
2092 TCGv temp2 = tcg_temp_new();
2093 TCGv_i64 t1 = tcg_temp_new_i64();
2094 TCGv_i64 t2 = tcg_temp_new_i64();
2095
2096 if (n == 0) {
2097 tcg_gen_mul_tl(temp, arg2, arg3);
2098 } else { /* n is expected to be 1 */
2099 tcg_gen_mul_tl(temp, arg2, arg3);
2100 tcg_gen_shli_tl(temp, temp, 1);
2101 /* catch special case r1 = r2 = 0x8000 */
2102 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2103 tcg_gen_sub_tl(temp, temp, temp2);
2104 }
2105 tcg_gen_ext_i32_i64(t2, temp);
2106 tcg_gen_shli_i64(t2, t2, 16);
2107 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2108
2109 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
2110 tcg_gen_extr_i64_i32(rl, rh, t1);
2111
2112 tcg_temp_free(temp);
2113 tcg_temp_free(temp2);
2114 tcg_temp_free_i64(t1);
2115 tcg_temp_free_i64(t2);
2116 }
2117
2118 static inline void
2119 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2120 TCGv arg3, uint32_t n, CPUTriCoreState *env)
2121 {
2122 TCGv_i64 t1 = tcg_temp_new_i64();
2123 TCGv_i64 t2 = tcg_temp_new_i64();
2124 TCGv_i64 t3 = tcg_temp_new_i64();
2125 TCGv_i64 t4 = tcg_temp_new_i64();
2126 TCGv temp, temp2;
2127
2128 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2129 tcg_gen_ext_i32_i64(t2, arg2);
2130 tcg_gen_ext_i32_i64(t3, arg3);
2131
2132 tcg_gen_mul_i64(t2, t2, t3);
2133 if (n != 0) {
2134 tcg_gen_shli_i64(t2, t2, 1);
2135 }
2136 tcg_gen_sub_i64(t4, t1, t2);
2137 /* calc v bit */
2138 tcg_gen_xor_i64(t3, t4, t1);
2139 tcg_gen_xor_i64(t2, t1, t2);
2140 tcg_gen_and_i64(t3, t3, t2);
2141 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
2142 /* We produce an overflow on the host if the mul before was
2143 (0x80000000 * 0x80000000) << 1). If this is the
2144 case, we negate the ovf. */
2145 if (n == 1) {
2146 temp = tcg_temp_new();
2147 temp2 = tcg_temp_new();
2148 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
2149 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
2150 tcg_gen_and_tl(temp, temp, temp2);
2151 tcg_gen_shli_tl(temp, temp, 31);
2152 /* negate v bit, if special condition */
2153 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
2154
2155 tcg_temp_free(temp);
2156 tcg_temp_free(temp2);
2157 }
2158 /* write back result */
2159 tcg_gen_extr_i64_i32(rl, rh, t4);
2160 /* Calc SV bit */
2161 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2162 /* Calc AV/SAV bits */
2163 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2164 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2165 /* calc SAV */
2166 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2167
2168 tcg_temp_free_i64(t1);
2169 tcg_temp_free_i64(t2);
2170 tcg_temp_free_i64(t3);
2171 tcg_temp_free_i64(t4);
2172 }
2173
2174 static inline void
2175 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
2176 uint32_t up_shift)
2177 {
2178 TCGv_i64 t1 = tcg_temp_new_i64();
2179 TCGv_i64 t2 = tcg_temp_new_i64();
2180 TCGv_i64 t3 = tcg_temp_new_i64();
2181 TCGv_i64 t4 = tcg_temp_new_i64();
2182
2183 tcg_gen_ext_i32_i64(t1, arg1);
2184 tcg_gen_ext_i32_i64(t2, arg2);
2185 tcg_gen_ext_i32_i64(t3, arg3);
2186
2187 tcg_gen_mul_i64(t2, t2, t3);
2188 /* if we shift part of the fraction out, we need to round up */
2189 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
2190 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
2191 tcg_gen_sari_i64(t3, t2, up_shift - n);
2192 tcg_gen_add_i64(t3, t3, t4);
2193
2194 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
2195
2196 tcg_temp_free_i64(t1);
2197 tcg_temp_free_i64(t2);
2198 tcg_temp_free_i64(t3);
2199 tcg_temp_free_i64(t4);
2200 }
2201
2202 static inline void
2203 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2204 TCGv arg3, uint32_t n)
2205 {
2206 TCGv_i64 r1 = tcg_temp_new_i64();
2207 TCGv temp = tcg_const_i32(n);
2208
2209 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
2210 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
2211 tcg_gen_extr_i64_i32(rl, rh, r1);
2212
2213 tcg_temp_free_i64(r1);
2214 tcg_temp_free(temp);
2215 }
2216
2217 static inline void
2218 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2219 TCGv r3, uint32_t n, uint32_t mode)
2220 {
2221 TCGv temp = tcg_const_i32(n);
2222 TCGv temp2 = tcg_temp_new();
2223 TCGv_i64 temp64 = tcg_temp_new_i64();
2224 switch (mode) {
2225 case MODE_LL:
2226 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2227 break;
2228 case MODE_LU:
2229 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2230 break;
2231 case MODE_UL:
2232 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2233 break;
2234 case MODE_UU:
2235 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2236 break;
2237 }
2238 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2239 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
2240 tcg_gen_add_tl, tcg_gen_sub_tl);
2241 tcg_temp_free(temp);
2242 tcg_temp_free(temp2);
2243 tcg_temp_free_i64(temp64);
2244 }
2245
2246 static inline void
2247 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2248 TCGv r3, uint32_t n, uint32_t mode)
2249 {
2250 TCGv temp = tcg_const_i32(n);
2251 TCGv_i64 temp64 = tcg_temp_new_i64();
2252 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2253 TCGv_i64 temp64_3 = tcg_temp_new_i64();
2254 switch (mode) {
2255 case MODE_LL:
2256 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2257 break;
2258 case MODE_LU:
2259 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2260 break;
2261 case MODE_UL:
2262 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2263 break;
2264 case MODE_UU:
2265 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2266 break;
2267 }
2268 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
2269 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2270 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2271 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2272 tcg_gen_shli_i64(temp64, temp64, 16);
2273
2274 gen_sub64_d(temp64_2, temp64_3, temp64);
2275 /* write back result */
2276 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
2277
2278 tcg_temp_free(temp);
2279 tcg_temp_free_i64(temp64);
2280 tcg_temp_free_i64(temp64_2);
2281 tcg_temp_free_i64(temp64_3);
2282 }
2283
2284 static inline void
2285 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2286 {
2287 TCGv temp = tcg_const_i32(n);
2288 TCGv temp2 = tcg_temp_new();
2289 TCGv_i64 temp64 = tcg_temp_new_i64();
2290 switch (mode) {
2291 case MODE_LL:
2292 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2293 break;
2294 case MODE_LU:
2295 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2296 break;
2297 case MODE_UL:
2298 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2299 break;
2300 case MODE_UU:
2301 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2302 break;
2303 }
2304 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2305 tcg_gen_shli_tl(temp, r1, 16);
2306 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2307
2308 tcg_temp_free(temp);
2309 tcg_temp_free(temp2);
2310 tcg_temp_free_i64(temp64);
2311 }
2312
2313 static inline void
2314 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2315 TCGv r3, uint32_t n, uint32_t mode)
2316 {
2317 TCGv temp = tcg_const_i32(n);
2318 TCGv temp2 = tcg_temp_new();
2319 TCGv temp3 = tcg_temp_new();
2320 TCGv_i64 temp64 = tcg_temp_new_i64();
2321
2322 switch (mode) {
2323 case MODE_LL:
2324 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2325 break;
2326 case MODE_LU:
2327 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2328 break;
2329 case MODE_UL:
2330 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2331 break;
2332 case MODE_UU:
2333 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2334 break;
2335 }
2336 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2337 gen_adds(ret_low, r1_low, temp);
2338 tcg_gen_mov_tl(temp, cpu_PSW_V);
2339 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2340 gen_subs(ret_high, r1_high, temp2);
2341 /* combine v bits */
2342 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2343 /* combine av bits */
2344 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2345
2346 tcg_temp_free(temp);
2347 tcg_temp_free(temp2);
2348 tcg_temp_free(temp3);
2349 tcg_temp_free_i64(temp64);
2350 }
2351
2352 static inline void
2353 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2354 TCGv r3, uint32_t n, uint32_t mode)
2355 {
2356 TCGv temp = tcg_const_i32(n);
2357 TCGv_i64 temp64 = tcg_temp_new_i64();
2358 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2359
2360 switch (mode) {
2361 case MODE_LL:
2362 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2363 break;
2364 case MODE_LU:
2365 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2366 break;
2367 case MODE_UL:
2368 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2369 break;
2370 case MODE_UU:
2371 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2372 break;
2373 }
2374 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2375 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2376 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2377 tcg_gen_shli_i64(temp64, temp64, 16);
2378 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2379
2380 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2381 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2382
2383 tcg_temp_free(temp);
2384 tcg_temp_free_i64(temp64);
2385 tcg_temp_free_i64(temp64_2);
2386 }
2387
2388 static inline void
2389 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2390 {
2391 TCGv temp = tcg_const_i32(n);
2392 TCGv temp2 = tcg_temp_new();
2393 TCGv_i64 temp64 = tcg_temp_new_i64();
2394 switch (mode) {
2395 case MODE_LL:
2396 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2397 break;
2398 case MODE_LU:
2399 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2400 break;
2401 case MODE_UL:
2402 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2403 break;
2404 case MODE_UU:
2405 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2406 break;
2407 }
2408 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2409 tcg_gen_shli_tl(temp, r1, 16);
2410 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2411
2412 tcg_temp_free(temp);
2413 tcg_temp_free(temp2);
2414 tcg_temp_free_i64(temp64);
2415 }
2416
2417 static inline void gen_abs(TCGv ret, TCGv r1)
2418 {
2419 TCGv temp = tcg_temp_new();
2420 TCGv t0 = tcg_const_i32(0);
2421
2422 tcg_gen_neg_tl(temp, r1);
2423 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
2424 /* overflow can only happen, if r1 = 0x80000000 */
2425 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2426 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2427 /* calc SV bit */
2428 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2429 /* Calc AV bit */
2430 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2431 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2432 /* calc SAV bit */
2433 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2434
2435 tcg_temp_free(temp);
2436 tcg_temp_free(t0);
2437 }
2438
2439 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2440 {
2441 TCGv temp = tcg_temp_new_i32();
2442 TCGv result = tcg_temp_new_i32();
2443
2444 tcg_gen_sub_tl(result, r1, r2);
2445 tcg_gen_sub_tl(temp, r2, r1);
2446 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2447
2448 /* calc V bit */
2449 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2450 tcg_gen_xor_tl(temp, result, r2);
2451 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2452 tcg_gen_xor_tl(temp, r1, r2);
2453 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2454 /* calc SV bit */
2455 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2456 /* Calc AV bit */
2457 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2458 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2459 /* calc SAV bit */
2460 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2461 /* write back result */
2462 tcg_gen_mov_tl(ret, result);
2463
2464 tcg_temp_free(temp);
2465 tcg_temp_free(result);
2466 }
2467
2468 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2469 {
2470 TCGv temp = tcg_const_i32(con);
2471 gen_absdif(ret, r1, temp);
2472 tcg_temp_free(temp);
2473 }
2474
2475 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2476 {
2477 TCGv temp = tcg_const_i32(con);
2478 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2479 tcg_temp_free(temp);
2480 }
2481
2482 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2483 {
2484 TCGv high = tcg_temp_new();
2485 TCGv low = tcg_temp_new();
2486
2487 tcg_gen_muls2_tl(low, high, r1, r2);
2488 tcg_gen_mov_tl(ret, low);
2489 /* calc V bit */
2490 tcg_gen_sari_tl(low, low, 31);
2491 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2492 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2493 /* calc SV bit */
2494 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2495 /* Calc AV bit */
2496 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2497 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2498 /* calc SAV bit */
2499 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2500
2501 tcg_temp_free(high);
2502 tcg_temp_free(low);
2503 }
2504
2505 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2506 {
2507 TCGv temp = tcg_const_i32(con);
2508 gen_mul_i32s(ret, r1, temp);
2509 tcg_temp_free(temp);
2510 }
2511
2512 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2513 {
2514 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2515 /* clear V bit */
2516 tcg_gen_movi_tl(cpu_PSW_V, 0);
2517 /* calc SV bit */
2518 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2519 /* Calc AV bit */
2520 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2521 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2522 /* calc SAV bit */
2523 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2524 }
2525
2526 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2527 int32_t con)
2528 {
2529 TCGv temp = tcg_const_i32(con);
2530 gen_mul_i64s(ret_low, ret_high, r1, temp);
2531 tcg_temp_free(temp);
2532 }
2533
2534 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2535 {
2536 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2537 /* clear V bit */
2538 tcg_gen_movi_tl(cpu_PSW_V, 0);
2539 /* calc SV bit */
2540 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2541 /* Calc AV bit */
2542 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2543 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2544 /* calc SAV bit */
2545 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2546 }
2547
2548 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2549 int32_t con)
2550 {
2551 TCGv temp = tcg_const_i32(con);
2552 gen_mul_i64u(ret_low, ret_high, r1, temp);
2553 tcg_temp_free(temp);
2554 }
2555
2556 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2557 {
2558 TCGv temp = tcg_const_i32(con);
2559 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2560 tcg_temp_free(temp);
2561 }
2562
2563 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2564 {
2565 TCGv temp = tcg_const_i32(con);
2566 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2567 tcg_temp_free(temp);
2568 }
2569 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2570 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2571 {
2572 TCGv temp = tcg_const_i32(con);
2573 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2574 tcg_temp_free(temp);
2575 }
2576
2577 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2578 {
2579 TCGv temp = tcg_const_i32(con);
2580 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2581 tcg_temp_free(temp);
2582 }
2583
2584 static void
2585 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2586 {
2587 TCGv temp = tcg_temp_new();
2588 TCGv_i64 temp_64 = tcg_temp_new_i64();
2589 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2590
2591 if (n == 0) {
2592 if (up_shift == 32) {
2593 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2594 } else if (up_shift == 16) {
2595 tcg_gen_ext_i32_i64(temp_64, arg1);
2596 tcg_gen_ext_i32_i64(temp2_64, arg2);
2597
2598 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2599 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2600 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2601 } else {
2602 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2603 }
2604 /* reset v bit */
2605 tcg_gen_movi_tl(cpu_PSW_V, 0);
2606 } else { /* n is expected to be 1 */
2607 tcg_gen_ext_i32_i64(temp_64, arg1);
2608 tcg_gen_ext_i32_i64(temp2_64, arg2);
2609
2610 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2611
2612 if (up_shift == 0) {
2613 tcg_gen_shli_i64(temp_64, temp_64, 1);
2614 } else {
2615 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2616 }
2617 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2618 /* overflow only occurs if r1 = r2 = 0x8000 */
2619 if (up_shift == 0) {/* result is 64 bit */
2620 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2621 0x80000000);
2622 } else { /* result is 32 bit */
2623 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2624 0x80000000);
2625 }
2626 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2627 /* calc sv overflow bit */
2628 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2629 }
2630 /* calc av overflow bit */
2631 if (up_shift == 0) {
2632 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2633 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2634 } else {
2635 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2636 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2637 }
2638 /* calc sav overflow bit */
2639 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2640 tcg_temp_free(temp);
2641 tcg_temp_free_i64(temp_64);
2642 tcg_temp_free_i64(temp2_64);
2643 }
2644
2645 static void
2646 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2647 {
2648 TCGv temp = tcg_temp_new();
2649 if (n == 0) {
2650 tcg_gen_mul_tl(ret, arg1, arg2);
2651 } else { /* n is expected to be 1 */
2652 tcg_gen_mul_tl(ret, arg1, arg2);
2653 tcg_gen_shli_tl(ret, ret, 1);
2654 /* catch special case r1 = r2 = 0x8000 */
2655 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2656 tcg_gen_sub_tl(ret, ret, temp);
2657 }
2658 /* reset v bit */
2659 tcg_gen_movi_tl(cpu_PSW_V, 0);
2660 /* calc av overflow bit */
2661 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2662 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2663 /* calc sav overflow bit */
2664 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2665
2666 tcg_temp_free(temp);
2667 }
2668
2669 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2670 {
2671 TCGv temp = tcg_temp_new();
2672 if (n == 0) {
2673 tcg_gen_mul_tl(ret, arg1, arg2);
2674 tcg_gen_addi_tl(ret, ret, 0x8000);
2675 } else {
2676 tcg_gen_mul_tl(ret, arg1, arg2);
2677 tcg_gen_shli_tl(ret, ret, 1);
2678 tcg_gen_addi_tl(ret, ret, 0x8000);
2679 /* catch special case r1 = r2 = 0x8000 */
2680 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2681 tcg_gen_muli_tl(temp, temp, 0x8001);
2682 tcg_gen_sub_tl(ret, ret, temp);
2683 }
2684 /* reset v bit */
2685 tcg_gen_movi_tl(cpu_PSW_V, 0);
2686 /* calc av overflow bit */
2687 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2688 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2689 /* calc sav overflow bit */
2690 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2691 /* cut halfword off */
2692 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2693
2694 tcg_temp_free(temp);
2695 }
2696
2697 static inline void
2698 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2699 TCGv r3)
2700 {
2701 TCGv_i64 temp64 = tcg_temp_new_i64();
2702 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2703 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2704 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2705 tcg_temp_free_i64(temp64);
2706 }
2707
2708 static inline void
2709 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2710 int32_t con)
2711 {
2712 TCGv temp = tcg_const_i32(con);
2713 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2714 tcg_temp_free(temp);
2715 }
2716
2717 static inline void
2718 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2719 TCGv r3)
2720 {
2721 TCGv_i64 temp64 = tcg_temp_new_i64();
2722 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2723 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2724 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2725 tcg_temp_free_i64(temp64);
2726 }
2727
2728 static inline void
2729 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2730 int32_t con)
2731 {
2732 TCGv temp = tcg_const_i32(con);
2733 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2734 tcg_temp_free(temp);
2735 }
2736
2737 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2738 {
2739 TCGv temp = tcg_const_i32(con);
2740 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2741 tcg_temp_free(temp);
2742 }
2743
2744 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2745 {
2746 TCGv temp = tcg_const_i32(con);
2747 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2748 tcg_temp_free(temp);
2749 }
2750
2751 static inline void
2752 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2753 TCGv r3)
2754 {
2755 TCGv_i64 temp64 = tcg_temp_new_i64();
2756 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2757 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2758 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2759 tcg_temp_free_i64(temp64);
2760 }
2761
2762 static inline void
2763 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2764 int32_t con)
2765 {
2766 TCGv temp = tcg_const_i32(con);
2767 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2768 tcg_temp_free(temp);
2769 }
2770
2771 static inline void
2772 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2773 TCGv r3)
2774 {
2775 TCGv_i64 temp64 = tcg_temp_new_i64();
2776 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2777 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2778 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2779 tcg_temp_free_i64(temp64);
2780 }
2781
2782 static inline void
2783 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2784 int32_t con)
2785 {
2786 TCGv temp = tcg_const_i32(con);
2787 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2788 tcg_temp_free(temp);
2789 }
2790
2791 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2792 {
2793 TCGv sat_neg = tcg_const_i32(low);
2794 TCGv temp = tcg_const_i32(up);
2795
2796 /* sat_neg = (arg < low ) ? low : arg; */
2797 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2798
2799 /* ret = (sat_neg > up ) ? up : sat_neg; */
2800 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2801
2802 tcg_temp_free(sat_neg);
2803 tcg_temp_free(temp);
2804 }
2805
2806 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2807 {
2808 TCGv temp = tcg_const_i32(up);
2809 /* sat_neg = (arg > up ) ? up : arg; */
2810 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2811 tcg_temp_free(temp);
2812 }
2813
2814 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2815 {
2816 if (shift_count == -32) {
2817 tcg_gen_movi_tl(ret, 0);
2818 } else if (shift_count >= 0) {
2819 tcg_gen_shli_tl(ret, r1, shift_count);
2820 } else {
2821 tcg_gen_shri_tl(ret, r1, -shift_count);
2822 }
2823 }
2824
2825 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2826 {
2827 TCGv temp_low, temp_high;
2828
2829 if (shiftcount == -16) {
2830 tcg_gen_movi_tl(ret, 0);
2831 } else {
2832 temp_high = tcg_temp_new();
2833 temp_low = tcg_temp_new();
2834
2835 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2836 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2837 gen_shi(temp_low, temp_low, shiftcount);
2838 gen_shi(ret, temp_high, shiftcount);
2839 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2840
2841 tcg_temp_free(temp_low);
2842 tcg_temp_free(temp_high);
2843 }
2844 }
2845
2846 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2847 {
2848 uint32_t msk, msk_start;
2849 TCGv temp = tcg_temp_new();
2850 TCGv temp2 = tcg_temp_new();
2851 TCGv t_0 = tcg_const_i32(0);
2852
2853 if (shift_count == 0) {
2854 /* Clear PSW.C and PSW.V */
2855 tcg_gen_movi_tl(cpu_PSW_C, 0);
2856 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2857 tcg_gen_mov_tl(ret, r1);
2858 } else if (shift_count == -32) {
2859 /* set PSW.C */
2860 tcg_gen_mov_tl(cpu_PSW_C, r1);
2861 /* fill ret completely with sign bit */
2862 tcg_gen_sari_tl(ret, r1, 31);
2863 /* clear PSW.V */
2864 tcg_gen_movi_tl(cpu_PSW_V, 0);
2865 } else if (shift_count > 0) {
2866 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2867 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2868
2869 /* calc carry */
2870 msk_start = 32 - shift_count;
2871 msk = ((1 << shift_count) - 1) << msk_start;
2872 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2873 /* calc v/sv bits */
2874 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2875 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2876 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2877 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2878 /* calc sv */
2879 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2880 /* do shift */
2881 tcg_gen_shli_tl(ret, r1, shift_count);
2882
2883 tcg_temp_free(t_max);
2884 tcg_temp_free(t_min);
2885 } else {
2886 /* clear PSW.V */
2887 tcg_gen_movi_tl(cpu_PSW_V, 0);
2888 /* calc carry */
2889 msk = (1 << -shift_count) - 1;
2890 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2891 /* do shift */
2892 tcg_gen_sari_tl(ret, r1, -shift_count);
2893 }
2894 /* calc av overflow bit */
2895 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2896 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2897 /* calc sav overflow bit */
2898 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2899
2900 tcg_temp_free(temp);
2901 tcg_temp_free(temp2);
2902 tcg_temp_free(t_0);
2903 }
2904
2905 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2906 {
2907 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2908 }
2909
2910 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2911 {
2912 TCGv temp = tcg_const_i32(con);
2913 gen_shas(ret, r1, temp);
2914 tcg_temp_free(temp);
2915 }
2916
2917 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2918 {
2919 TCGv low, high;
2920
2921 if (shift_count == 0) {
2922 tcg_gen_mov_tl(ret, r1);
2923 } else if (shift_count > 0) {
2924 low = tcg_temp_new();
2925 high = tcg_temp_new();
2926
2927 tcg_gen_andi_tl(high, r1, 0xffff0000);
2928 tcg_gen_shli_tl(low, r1, shift_count);
2929 tcg_gen_shli_tl(ret, high, shift_count);
2930 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2931
2932 tcg_temp_free(low);
2933 tcg_temp_free(high);
2934 } else {
2935 low = tcg_temp_new();
2936 high = tcg_temp_new();
2937
2938 tcg_gen_ext16s_tl(low, r1);
2939 tcg_gen_sari_tl(low, low, -shift_count);
2940 tcg_gen_sari_tl(ret, r1, -shift_count);
2941 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2942
2943 tcg_temp_free(low);
2944 tcg_temp_free(high);
2945 }
2946
2947 }
2948
2949 /* ret = {ret[30:0], (r1 cond r2)}; */
2950 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2951 {
2952 TCGv temp = tcg_temp_new();
2953 TCGv temp2 = tcg_temp_new();
2954
2955 tcg_gen_shli_tl(temp, ret, 1);
2956 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2957 tcg_gen_or_tl(ret, temp, temp2);
2958
2959 tcg_temp_free(temp);
2960 tcg_temp_free(temp2);
2961 }
2962
2963 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2964 {
2965 TCGv temp = tcg_const_i32(con);
2966 gen_sh_cond(cond, ret, r1, temp);
2967 tcg_temp_free(temp);
2968 }
2969
2970 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2971 {
2972 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2973 }
2974
2975 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2976 {
2977 TCGv temp = tcg_const_i32(con);
2978 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2979 tcg_temp_free(temp);
2980 }
2981
2982 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2983 {
2984 TCGv temp = tcg_const_i32(con);
2985 gen_helper_add_suov(ret, cpu_env, r1, temp);
2986 tcg_temp_free(temp);
2987 }
2988
2989 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2990 {
2991 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2992 }
2993
2994 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2995 {
2996 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2997 }
2998
2999 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
3000 int pos1, int pos2,
3001 void(*op1)(TCGv, TCGv, TCGv),
3002 void(*op2)(TCGv, TCGv, TCGv))
3003 {
3004 TCGv temp1, temp2;
3005
3006 temp1 = tcg_temp_new();
3007 temp2 = tcg_temp_new();
3008
3009 tcg_gen_shri_tl(temp2, r2, pos2);
3010 tcg_gen_shri_tl(temp1, r1, pos1);
3011
3012 (*op1)(temp1, temp1, temp2);
3013 (*op2)(temp1 , ret, temp1);
3014
3015 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
3016
3017 tcg_temp_free(temp1);
3018 tcg_temp_free(temp2);
3019 }
3020
3021 /* ret = r1[pos1] op1 r2[pos2]; */
3022 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
3023 int pos1, int pos2,
3024 void(*op1)(TCGv, TCGv, TCGv))
3025 {
3026 TCGv temp1, temp2;
3027
3028 temp1 = tcg_temp_new();
3029 temp2 = tcg_temp_new();
3030
3031 tcg_gen_shri_tl(temp2, r2, pos2);
3032 tcg_gen_shri_tl(temp1, r1, pos1);
3033
3034 (*op1)(ret, temp1, temp2);
3035
3036 tcg_gen_andi_tl(ret, ret, 0x1);
3037
3038 tcg_temp_free(temp1);
3039 tcg_temp_free(temp2);
3040 }
3041
3042 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
3043 void(*op)(TCGv, TCGv, TCGv))
3044 {
3045 TCGv temp = tcg_temp_new();
3046 TCGv temp2 = tcg_temp_new();
3047 /* temp = (arg1 cond arg2 )*/
3048 tcg_gen_setcond_tl(cond, temp, r1, r2);
3049 /* temp2 = ret[0]*/
3050 tcg_gen_andi_tl(temp2, ret, 0x1);
3051 /* temp = temp insn temp2 */
3052 (*op)(temp, temp, temp2);
3053 /* ret = {ret[31:1], temp} */
3054 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
3055
3056 tcg_temp_free(temp);
3057 tcg_temp_free(temp2);
3058 }
3059
3060 static inline void
3061 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
3062 void(*op)(TCGv, TCGv, TCGv))
3063 {
3064 TCGv temp = tcg_const_i32(con);
3065 gen_accumulating_cond(cond, ret, r1, temp, op);
3066 tcg_temp_free(temp);
3067 }
3068
3069 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3070 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
3071 {
3072 tcg_gen_setcond_tl(cond, ret, r1, r2);
3073 tcg_gen_neg_tl(ret, ret);
3074 }
3075
3076 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
3077 {
3078 TCGv b0 = tcg_temp_new();
3079 TCGv b1 = tcg_temp_new();
3080 TCGv b2 = tcg_temp_new();
3081 TCGv b3 = tcg_temp_new();
3082
3083 /* byte 0 */
3084 tcg_gen_andi_tl(b0, r1, 0xff);
3085 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
3086
3087 /* byte 1 */
3088 tcg_gen_andi_tl(b1, r1, 0xff00);
3089 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
3090
3091 /* byte 2 */
3092 tcg_gen_andi_tl(b2, r1, 0xff0000);
3093 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
3094
3095 /* byte 3 */
3096 tcg_gen_andi_tl(b3, r1, 0xff000000);
3097 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
3098
3099 /* combine them */
3100 tcg_gen_or_tl(ret, b0, b1);
3101 tcg_gen_or_tl(ret, ret, b2);
3102 tcg_gen_or_tl(ret, ret, b3);
3103
3104 tcg_temp_free(b0);
3105 tcg_temp_free(b1);
3106 tcg_temp_free(b2);
3107 tcg_temp_free(b3);
3108 }
3109
3110 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
3111 {
3112 TCGv h0 = tcg_temp_new();
3113 TCGv h1 = tcg_temp_new();
3114
3115 /* halfword 0 */
3116 tcg_gen_andi_tl(h0, r1, 0xffff);
3117 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
3118
3119 /* halfword 1 */
3120 tcg_gen_andi_tl(h1, r1, 0xffff0000);
3121 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
3122
3123 /* combine them */
3124 tcg_gen_or_tl(ret, h0, h1);
3125
3126 tcg_temp_free(h0);
3127 tcg_temp_free(h1);
3128 }
3129 /* mask = ((1 << width) -1) << pos;
3130 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3131 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
3132 {
3133 TCGv mask = tcg_temp_new();
3134 TCGv temp = tcg_temp_new();
3135 TCGv temp2 = tcg_temp_new();
3136
3137 tcg_gen_movi_tl(mask, 1);
3138 tcg_gen_shl_tl(mask, mask, width);
3139 tcg_gen_subi_tl(mask, mask, 1);
3140 tcg_gen_shl_tl(mask, mask, pos);
3141
3142 tcg_gen_shl_tl(temp, r2, pos);
3143 tcg_gen_and_tl(temp, temp, mask);
3144 tcg_gen_andc_tl(temp2, r1, mask);
3145 tcg_gen_or_tl(ret, temp, temp2);
3146
3147 tcg_temp_free(mask);
3148 tcg_temp_free(temp);
3149 tcg_temp_free(temp2);
3150 }
3151
3152 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
3153 {
3154 TCGv_i64 temp = tcg_temp_new_i64();
3155
3156 gen_helper_bsplit(temp, r1);
3157 tcg_gen_extr_i64_i32(rl, rh, temp);
3158
3159 tcg_temp_free_i64(temp);
3160 }
3161
3162 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
3163 {
3164 TCGv_i64 temp = tcg_temp_new_i64();
3165
3166 gen_helper_unpack(temp, r1);
3167 tcg_gen_extr_i64_i32(rl, rh, temp);
3168
3169 tcg_temp_free_i64(temp);
3170 }
3171
3172 static inline void
3173 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3174 {
3175 TCGv_i64 ret = tcg_temp_new_i64();
3176
3177 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3178 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
3179 } else {
3180 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
3181 }
3182 tcg_gen_extr_i64_i32(rl, rh, ret);
3183
3184 tcg_temp_free_i64(ret);
3185 }
3186
3187 static inline void
3188 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3189 {
3190 TCGv_i64 ret = tcg_temp_new_i64();
3191
3192 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3193 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
3194 } else {
3195 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
3196 }
3197 tcg_gen_extr_i64_i32(rl, rh, ret);
3198
3199 tcg_temp_free_i64(ret);
3200 }
3201
3202 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
3203 {
3204 TCGv temp = tcg_temp_new();
3205 /* calc AV bit */
3206 tcg_gen_add_tl(temp, arg_low, arg_low);
3207 tcg_gen_xor_tl(temp, temp, arg_low);
3208 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
3209 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
3210 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3211 /* calc SAV bit */
3212 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3213 tcg_gen_movi_tl(cpu_PSW_V, 0);
3214 tcg_temp_free(temp);
3215 }
3216
3217 static void gen_calc_usb_mulr_h(TCGv arg)
3218 {
3219 TCGv temp = tcg_temp_new();
3220 /* calc AV bit */
3221 tcg_gen_add_tl(temp, arg, arg);
3222 tcg_gen_xor_tl(temp, temp, arg);
3223 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
3224 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3225 /* calc SAV bit */
3226 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3227 /* clear V bit */
3228 tcg_gen_movi_tl(cpu_PSW_V, 0);
3229 tcg_temp_free(temp);
3230 }
3231
3232 /* helpers for generating program flow micro-ops */
3233
3234 static inline void gen_save_pc(target_ulong pc)
3235 {
3236 tcg_gen_movi_tl(cpu_PC, pc);
3237 }
3238
3239 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3240 {
3241 if (unlikely(ctx->singlestep_enabled)) {
3242 return false;
3243 }
3244
3245 #ifndef CONFIG_USER_ONLY
3246 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3247 #else
3248 return true;
3249 #endif
3250 }
3251
3252 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3253 {
3254 if (use_goto_tb(ctx, dest)) {
3255 tcg_gen_goto_tb(n);
3256 gen_save_pc(dest);
3257 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3258 } else {
3259 gen_save_pc(dest);
3260 if (ctx->singlestep_enabled) {
3261 /* raise exception debug */
3262 }
3263 tcg_gen_exit_tb(0);
3264 }
3265 }
3266
3267 static void generate_trap(DisasContext *ctx, int class, int tin)
3268 {
3269 TCGv_i32 classtemp = tcg_const_i32(class);
3270 TCGv_i32 tintemp = tcg_const_i32(tin);
3271
3272 gen_save_pc(ctx->pc);
3273 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
3274 ctx->bstate = BS_EXCP;
3275
3276 tcg_temp_free(classtemp);
3277 tcg_temp_free(tintemp);
3278 }
3279
3280 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
3281 TCGv r2, int16_t address)
3282 {
3283 TCGLabel *jumpLabel = gen_new_label();
3284 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
3285
3286 gen_goto_tb(ctx, 1, ctx->next_pc);
3287
3288 gen_set_label(jumpLabel);
3289 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
3290 }
3291
3292 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
3293 int r2, int16_t address)
3294 {
3295 TCGv temp = tcg_const_i32(r2);
3296 gen_branch_cond(ctx, cond, r1, temp, address);
3297 tcg_temp_free(temp);
3298 }
3299
3300 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
3301 {
3302 TCGLabel *l1 = gen_new_label();
3303
3304 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
3305 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
3306 gen_goto_tb(ctx, 1, ctx->pc + offset);
3307 gen_set_label(l1);
3308 gen_goto_tb(ctx, 0, ctx->next_pc);
3309 }
3310
3311 static void gen_fcall_save_ctx(DisasContext *ctx)
3312 {
3313 TCGv temp = tcg_temp_new();
3314
3315 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
3316 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
3317 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3318 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
3319
3320 tcg_temp_free(temp);
3321 }
3322
3323 static void gen_fret(DisasContext *ctx)
3324 {
3325 TCGv temp = tcg_temp_new();
3326
3327 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
3328 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
3329 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
3330 tcg_gen_mov_tl(cpu_PC, temp);
3331 tcg_gen_exit_tb(0);
3332 ctx->bstate = BS_BRANCH;
3333
3334 tcg_temp_free(temp);
3335 }
3336
3337 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
3338 int r2 , int32_t constant , int32_t offset)
3339 {
3340 TCGv temp, temp2;
3341 int n;
3342
3343 switch (opc) {
3344 /* SB-format jumps */
3345 case OPC1_16_SB_J:
3346 case OPC1_32_B_J:
3347 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3348 break;
3349 case OPC1_32_B_CALL:
3350 case OPC1_16_SB_CALL:
3351 gen_helper_1arg(call, ctx->next_pc);
3352 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3353 break;
3354 case OPC1_16_SB_JZ:
3355 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
3356 break;
3357 case OPC1_16_SB_JNZ:
3358 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
3359 break;
3360 /* SBC-format jumps */
3361 case OPC1_16_SBC_JEQ:
3362 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
3363 break;
3364 case OPC1_16_SBC_JNE:
3365 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
3366 break;
3367 /* SBRN-format jumps */
3368 case OPC1_16_SBRN_JZ_T:
3369 temp = tcg_temp_new();
3370 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3371 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3372 tcg_temp_free(temp);
3373 break;
3374 case OPC1_16_SBRN_JNZ_T:
3375 temp = tcg_temp_new();
3376 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3377 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3378 tcg_temp_free(temp);
3379 break;
3380 /* SBR-format jumps */
3381 case OPC1_16_SBR_JEQ:
3382 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
3383 offset);
3384 break;
3385 case OPC1_16_SBR_JNE:
3386 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
3387 offset);
3388 break;
3389 case OPC1_16_SBR_JNZ:
3390 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
3391 break;
3392 case OPC1_16_SBR_JNZ_A:
3393 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3394 break;
3395 case OPC1_16_SBR_JGEZ:
3396 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
3397 break;
3398 case OPC1_16_SBR_JGTZ:
3399 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
3400 break;
3401 case OPC1_16_SBR_JLEZ:
3402 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
3403 break;
3404 case OPC1_16_SBR_JLTZ:
3405 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
3406 break;
3407 case OPC1_16_SBR_JZ:
3408 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
3409 break;
3410 case OPC1_16_SBR_JZ_A:
3411 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3412 break;
3413 case OPC1_16_SBR_LOOP:
3414 gen_loop(ctx, r1, offset * 2 - 32);
3415 break;
3416 /* SR-format jumps */
3417 case OPC1_16_SR_JI:
3418 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3419 tcg_gen_exit_tb(0);
3420 break;
3421 case OPC2_32_SYS_RET:
3422 case OPC2_16_SR_RET:
3423 gen_helper_ret(cpu_env);
3424 tcg_gen_exit_tb(0);
3425 break;
3426 /* B-format */
3427 case OPC1_32_B_CALLA:
3428 gen_helper_1arg(call, ctx->next_pc);
3429 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3430 break;
3431 case OPC1_32_B_FCALL:
3432 gen_fcall_save_ctx(ctx);
3433 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3434 break;
3435 case OPC1_32_B_FCALLA:
3436 gen_fcall_save_ctx(ctx);
3437 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3438 break;
3439 case OPC1_32_B_JLA:
3440 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3441 /* fall through */
3442 case OPC1_32_B_JA:
3443 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3444 break;
3445 case OPC1_32_B_JL:
3446 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3447 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3448 break;
3449 /* BOL format */
3450 case OPCM_32_BRC_EQ_NEQ:
3451 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3452 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3453 } else {
3454 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3455 }
3456 break;
3457 case OPCM_32_BRC_GE:
3458 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3459 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3460 } else {
3461 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3462 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3463 offset);
3464 }
3465 break;
3466 case OPCM_32_BRC_JLT:
3467 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3468 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3469 } else {
3470 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3471 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3472 offset);
3473 }
3474 break;
3475 case OPCM_32_BRC_JNE:
3476 temp = tcg_temp_new();
3477 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3478 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3479 /* subi is unconditional */
3480 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3481 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3482 } else {
3483 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3484 /* addi is unconditional */
3485 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3486 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3487 }
3488 tcg_temp_free(temp);
3489 break;
3490 /* BRN format */
3491 case OPCM_32_BRN_JTT:
3492 n = MASK_OP_BRN_N(ctx->opcode);
3493
3494 temp = tcg_temp_new();
3495 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3496
3497 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3498 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3499 } else {
3500 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3501 }
3502 tcg_temp_free(temp);
3503 break;
3504 /* BRR Format */
3505 case OPCM_32_BRR_EQ_NEQ:
3506 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3507 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3508 offset);
3509 } else {
3510 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3511 offset);
3512 }
3513 break;
3514 case OPCM_32_BRR_ADDR_EQ_NEQ:
3515 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3516 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3517 offset);
3518 } else {
3519 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3520 offset);
3521 }
3522 break;
3523 case OPCM_32_BRR_GE:
3524 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3525 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3526 offset);
3527 } else {
3528 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3529 offset);
3530 }
3531 break;
3532 case OPCM_32_BRR_JLT:
3533 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3534 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3535 offset);
3536 } else {
3537 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3538 offset);
3539 }
3540 break;
3541 case OPCM_32_BRR_LOOP:
3542 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3543 gen_loop(ctx, r2, offset * 2);
3544 } else {
3545 /* OPC2_32_BRR_LOOPU */
3546 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3547 }
3548 break;
3549 case OPCM_32_BRR_JNE:
3550 temp = tcg_temp_new();
3551 temp2 = tcg_temp_new();
3552 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3553 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3554 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3555 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3556 /* subi is unconditional */
3557 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3558 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3559 } else {
3560 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3561 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3562 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3563 /* addi is unconditional */
3564 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3565 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3566 }
3567 tcg_temp_free(temp);
3568 tcg_temp_free(temp2);
3569 break;
3570 case OPCM_32_BRR_JNZ:
3571 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3572 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3573 } else {
3574 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3575 }
3576 break;
3577 default:
3578 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3579 }
3580 ctx->bstate = BS_BRANCH;
3581 }
3582
3583
3584 /*
3585 * Functions for decoding instructions
3586 */
3587
3588 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
3589 {
3590 int r1;
3591 int32_t const4;
3592 TCGv temp, temp2;
3593
3594 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3595 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3596
3597 switch (op1) {
3598 case OPC1_16_SRC_ADD:
3599 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3600 break;
3601 case OPC1_16_SRC_ADD_A15:
3602 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3603 break;
3604 case OPC1_16_SRC_ADD_15A:
3605 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3606 break;
3607 case OPC1_16_SRC_ADD_A:
3608 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3609 break;
3610 case OPC1_16_SRC_CADD:
3611 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3612 cpu_gpr_d[15]);
3613 break;
3614 case OPC1_16_SRC_CADDN:
3615 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3616 cpu_gpr_d[15]);
3617 break;
3618 case OPC1_16_SRC_CMOV:
3619 temp = tcg_const_tl(0);
3620 temp2 = tcg_const_tl(const4);
3621 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3622 temp2, cpu_gpr_d[r1]);
3623 tcg_temp_free(temp);
3624 tcg_temp_free(temp2);
3625 break;
3626 case OPC1_16_SRC_CMOVN:
3627 temp = tcg_const_tl(0);
3628 temp2 = tcg_const_tl(const4);
3629 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3630 temp2, cpu_gpr_d[r1]);
3631 tcg_temp_free(temp);
3632 tcg_temp_free(temp2);
3633 break;
3634 case OPC1_16_SRC_EQ:
3635 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3636 const4);
3637 break;
3638 case OPC1_16_SRC_LT:
3639 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3640 const4);
3641 break;
3642 case OPC1_16_SRC_MOV:
3643 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3644 break;
3645 case OPC1_16_SRC_MOV_A:
3646 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3647 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3648 break;
3649 case OPC1_16_SRC_MOV_E:
3650 if (tricore_feature(env, TRICORE_FEATURE_16)) {
3651 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3652 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3653 } else {
3654 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3655 }
3656 break;
3657 case OPC1_16_SRC_SH:
3658 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3659 break;
3660 case OPC1_16_SRC_SHA:
3661 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3662 break;
3663 default:
3664 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3665 }
3666 }
3667
3668 static void decode_srr_opc(DisasContext *ctx, int op1)
3669 {
3670 int r1, r2;
3671 TCGv temp;
3672
3673 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3674 r2 = MASK_OP_SRR_S2(ctx->opcode);
3675
3676 switch (op1) {
3677 case OPC1_16_SRR_ADD:
3678 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3679 break;
3680 case OPC1_16_SRR_ADD_A15:
3681 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3682 break;
3683 case OPC1_16_SRR_ADD_15A:
3684 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3685 break;
3686 case OPC1_16_SRR_ADD_A:
3687 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3688 break;
3689 case OPC1_16_SRR_ADDS:
3690 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3691 break;
3692 case OPC1_16_SRR_AND:
3693 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3694 break;
3695 case OPC1_16_SRR_CMOV:
3696 temp = tcg_const_tl(0);
3697 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3698 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3699 tcg_temp_free(temp);
3700 break;
3701 case OPC1_16_SRR_CMOVN:
3702 temp = tcg_const_tl(0);
3703 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3704 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3705 tcg_temp_free(temp);
3706 break;
3707 case OPC1_16_SRR_EQ:
3708 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3709 cpu_gpr_d[r2]);
3710 break;
3711 case OPC1_16_SRR_LT:
3712 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3713 cpu_gpr_d[r2]);
3714 break;
3715 case OPC1_16_SRR_MOV:
3716 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3717 break;
3718 case OPC1_16_SRR_MOV_A:
3719 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3720 break;
3721 case OPC1_16_SRR_MOV_AA:
3722 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3723 break;
3724 case OPC1_16_SRR_MOV_D:
3725 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3726 break;
3727 case OPC1_16_SRR_MUL:
3728 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3729 break;
3730 case OPC1_16_SRR_OR:
3731 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3732 break;
3733 case OPC1_16_SRR_SUB:
3734 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3735 break;
3736 case OPC1_16_SRR_SUB_A15B:
3737 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3738 break;
3739 case OPC1_16_SRR_SUB_15AB:
3740 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3741 break;
3742 case OPC1_16_SRR_SUBS:
3743 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3744 break;
3745 case OPC1_16_SRR_XOR:
3746 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3747 break;
3748 default:
3749 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3750 }
3751 }
3752
3753 static void decode_ssr_opc(DisasContext *ctx, int op1)
3754 {
3755 int r1, r2;
3756
3757 r1 = MASK_OP_SSR_S1(ctx->opcode);
3758 r2 = MASK_OP_SSR_S2(ctx->opcode);
3759
3760 switch (op1) {
3761 case OPC1_16_SSR_ST_A:
3762 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3763 break;
3764 case OPC1_16_SSR_ST_A_POSTINC:
3765 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3766 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3767 break;
3768 case OPC1_16_SSR_ST_B:
3769 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3770 break;
3771 case OPC1_16_SSR_ST_B_POSTINC:
3772 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3773 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3774 break;
3775 case OPC1_16_SSR_ST_H:
3776 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3777 break;
3778 case OPC1_16_SSR_ST_H_POSTINC:
3779 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3780 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3781 break;
3782 case OPC1_16_SSR_ST_W:
3783 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3784 break;
3785 case OPC1_16_SSR_ST_W_POSTINC:
3786 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3787 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3788 break;
3789 default:
3790 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3791 }
3792 }
3793
3794 static void decode_sc_opc(DisasContext *ctx, int op1)
3795 {
3796 int32_t const16;
3797
3798 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3799
3800 switch (op1) {
3801 case OPC1_16_SC_AND:
3802 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3803 break;
3804 case OPC1_16_SC_BISR:
3805 gen_helper_1arg(bisr, const16 & 0xff);
3806 break;
3807 case OPC1_16_SC_LD_A:
3808 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3809 break;
3810 case OPC1_16_SC_LD_W:
3811 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3812 break;
3813 case OPC1_16_SC_MOV:
3814 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3815 break;
3816 case OPC1_16_SC_OR:
3817 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3818 break;
3819 case OPC1_16_SC_ST_A:
3820 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3821 break;
3822 case OPC1_16_SC_ST_W:
3823 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3824 break;
3825 case OPC1_16_SC_SUB_A:
3826 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3827 break;
3828 default:
3829 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3830 }
3831 }
3832
3833 static void decode_slr_opc(DisasContext *ctx, int op1)
3834 {
3835 int r1, r2;
3836
3837 r1 = MASK_OP_SLR_D(ctx->opcode);
3838 r2 = MASK_OP_SLR_S2(ctx->opcode);
3839
3840 switch (op1) {
3841 /* SLR-format */
3842 case OPC1_16_SLR_LD_A:
3843 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3844 break;
3845 case OPC1_16_SLR_LD_A_POSTINC:
3846 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3847 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3848 break;
3849 case OPC1_16_SLR_LD_BU:
3850 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3851 break;
3852 case OPC1_16_SLR_LD_BU_POSTINC:
3853 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3854 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3855 break;
3856 case OPC1_16_SLR_LD_H:
3857 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3858 break;
3859 case OPC1_16_SLR_LD_H_POSTINC:
3860 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3861 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3862 break;
3863 case OPC1_16_SLR_LD_W:
3864 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3865 break;
3866 case OPC1_16_SLR_LD_W_POSTINC:
3867 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3868 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3869 break;
3870 default:
3871 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3872 }
3873 }
3874
3875 static void decode_sro_opc(DisasContext *ctx, int op1)
3876 {
3877 int r2;
3878 int32_t address;
3879
3880 r2 = MASK_OP_SRO_S2(ctx->opcode);
3881 address = MASK_OP_SRO_OFF4(ctx->opcode);
3882
3883 /* SRO-format */
3884 switch (op1) {
3885 case OPC1_16_SRO_LD_A:
3886 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3887 break;
3888 case OPC1_16_SRO_LD_BU:
3889 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3890 break;
3891 case OPC1_16_SRO_LD_H:
3892 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3893 break;
3894 case OPC1_16_SRO_LD_W:
3895 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3896 break;
3897 case OPC1_16_SRO_ST_A:
3898 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3899 break;
3900 case OPC1_16_SRO_ST_B:
3901 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3902 break;
3903 case OPC1_16_SRO_ST_H:
3904 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3905 break;
3906 case OPC1_16_SRO_ST_W:
3907 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3908 break;
3909 default:
3910 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3911 }
3912 }
3913
3914 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3915 {
3916 uint32_t op2;
3917 op2 = MASK_OP_SR_OP2(ctx->opcode);
3918
3919 switch (op2) {
3920 case OPC2_16_SR_NOP:
3921 break;
3922 case OPC2_16_SR_RET:
3923 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3924 break;
3925 case OPC2_16_SR_RFE:
3926 gen_helper_rfe(cpu_env);
3927 tcg_gen_exit_tb(0);
3928 ctx->bstate = BS_BRANCH;
3929 break;
3930 case OPC2_16_SR_DEBUG:
3931 /* raise EXCP_DEBUG */
3932 break;
3933 case OPC2_16_SR_FRET:
3934 gen_fret(ctx);
3935 break;
3936 default:
3937 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3938 }
3939 }
3940
3941 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3942 {
3943 uint32_t op2;
3944 uint32_t r1;
3945 TCGv temp;
3946
3947 r1 = MASK_OP_SR_S1D(ctx->opcode);
3948 op2 = MASK_OP_SR_OP2(ctx->opcode);
3949
3950 switch (op2) {
3951 case OPC2_16_SR_RSUB:
3952 /* overflow only if r1 = -0x80000000 */
3953 temp = tcg_const_i32(-0x80000000);
3954 /* calc V bit */
3955 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3956 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3957 /* calc SV bit */
3958 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3959 /* sub */
3960 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3961 /* calc av */
3962 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3963 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3964 /* calc sav */
3965 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3966 tcg_temp_free(temp);
3967 break;
3968 case OPC2_16_SR_SAT_B:
3969 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3970 break;
3971 case OPC2_16_SR_SAT_BU:
3972 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3973 break;
3974 case OPC2_16_SR_SAT_H:
3975 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3976 break;
3977 case OPC2_16_SR_SAT_HU:
3978 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3979 break;
3980 default:
3981 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3982 }
3983 }
3984
3985 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3986 {
3987 int op1;
3988 int r1, r2;
3989 int32_t const16;
3990 int32_t address;
3991 TCGv temp;
3992
3993 op1 = MASK_OP_MAJOR(ctx->opcode);
3994
3995 /* handle ADDSC.A opcode only being 6 bit long */
3996 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3997 op1 = OPC1_16_SRRS_ADDSC_A;
3998 }
3999
4000 switch (op1) {
4001 case OPC1_16_SRC_ADD:
4002 case OPC1_16_SRC_ADD_A15:
4003 case OPC1_16_SRC_ADD_15A:
4004 case OPC1_16_SRC_ADD_A:
4005 case OPC1_16_SRC_CADD:
4006 case OPC1_16_SRC_CADDN:
4007 case OPC1_16_SRC_CMOV:
4008 case OPC1_16_SRC_CMOVN:
4009 case OPC1_16_SRC_EQ:
4010 case OPC1_16_SRC_LT:
4011 case OPC1_16_SRC_MOV:
4012 case OPC1_16_SRC_MOV_A:
4013 case OPC1_16_SRC_MOV_E:
4014 case OPC1_16_SRC_SH:
4015 case OPC1_16_SRC_SHA:
4016 decode_src_opc(env, ctx, op1);
4017 break;
4018 /* SRR-format */
4019 case OPC1_16_SRR_ADD:
4020 case OPC1_16_SRR_ADD_A15:
4021 case OPC1_16_SRR_ADD_15A:
4022 case OPC1_16_SRR_ADD_A:
4023 case OPC1_16_SRR_ADDS:
4024 case OPC1_16_SRR_AND:
4025 case OPC1_16_SRR_CMOV:
4026 case OPC1_16_SRR_CMOVN:
4027 case OPC1_16_SRR_EQ:
4028 case OPC1_16_SRR_LT:
4029 case OPC1_16_SRR_MOV:
4030 case OPC1_16_SRR_MOV_A:
4031 case OPC1_16_SRR_MOV_AA:
4032 case OPC1_16_SRR_MOV_D:
4033 case OPC1_16_SRR_MUL:
4034 case OPC1_16_SRR_OR:
4035 case OPC1_16_SRR_SUB:
4036 case OPC1_16_SRR_SUB_A15B:
4037 case OPC1_16_SRR_SUB_15AB:
4038 case OPC1_16_SRR_SUBS:
4039 case OPC1_16_SRR_XOR:
4040 decode_srr_opc(ctx, op1);
4041 break;
4042 /* SSR-format */
4043 case OPC1_16_SSR_ST_A:
4044 case OPC1_16_SSR_ST_A_POSTINC:
4045 case OPC1_16_SSR_ST_B:
4046 case OPC1_16_SSR_ST_B_POSTINC:
4047 case OPC1_16_SSR_ST_H:
4048 case OPC1_16_SSR_ST_H_POSTINC:
4049 case OPC1_16_SSR_ST_W:
4050 case OPC1_16_SSR_ST_W_POSTINC:
4051 decode_ssr_opc(ctx, op1);
4052 break;
4053 /* SRRS-format */
4054 case OPC1_16_SRRS_ADDSC_A:
4055 r2 = MASK_OP_SRRS_S2(ctx->opcode);
4056 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
4057 const16 = MASK_OP_SRRS_N(ctx->opcode);
4058 temp = tcg_temp_new();
4059 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
4060 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
4061 tcg_temp_free(temp);
4062 break;
4063 /* SLRO-format */
4064 case OPC1_16_SLRO_LD_A:
4065 r1 = MASK_OP_SLRO_D(ctx->opcode);
4066 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4067 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4068 break;
4069 case OPC1_16_SLRO_LD_BU:
4070 r1 = MASK_OP_SLRO_D(ctx->opcode);
4071 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4072 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4073 break;
4074 case OPC1_16_SLRO_LD_H:
4075 r1 = MASK_OP_SLRO_D(ctx->opcode);
4076 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4077 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4078 break;
4079 case OPC1_16_SLRO_LD_W:
4080 r1 = MASK_OP_SLRO_D(ctx->opcode);
4081 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4082 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4083 break;
4084 /* SB-format */
4085 case OPC1_16_SB_CALL:
4086 case OPC1_16_SB_J:
4087 case OPC1_16_SB_JNZ:
4088 case OPC1_16_SB_JZ:
4089 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
4090 gen_compute_branch(ctx, op1, 0, 0, 0, address);
4091 break;
4092 /* SBC-format */
4093 case OPC1_16_SBC_JEQ:
4094 case OPC1_16_SBC_JNE:
4095 address = MASK_OP_SBC_DISP4(ctx->opcode);
4096 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
4097 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4098 break;
4099 /* SBRN-format */
4100 case OPC1_16_SBRN_JNZ_T:
4101 case OPC1_16_SBRN_JZ_T:
4102 address = MASK_OP_SBRN_DISP4(ctx->opcode);
4103 const16 = MASK_OP_SBRN_N(ctx->opcode);
4104 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4105 break;
4106 /* SBR-format */
4107 case OPC1_16_SBR_JEQ:
4108 case OPC1_16_SBR_JGEZ:
4109 case OPC1_16_SBR_JGTZ:
4110 case OPC1_16_SBR_JLEZ:
4111 case OPC1_16_SBR_JLTZ:
4112 case OPC1_16_SBR_JNE:
4113 case OPC1_16_SBR_JNZ:
4114 case OPC1_16_SBR_JNZ_A:
4115 case OPC1_16_SBR_JZ:
4116 case OPC1_16_SBR_JZ_A:
4117 case OPC1_16_SBR_LOOP:
4118 r1 = MASK_OP_SBR_S2(ctx->opcode);
4119 address = MASK_OP_SBR_DISP4(ctx->opcode);
4120 gen_compute_branch(ctx, op1, r1, 0, 0, address);
4121 break;
4122 /* SC-format */
4123 case OPC1_16_SC_AND:
4124 case OPC1_16_SC_BISR:
4125 case OPC1_16_SC_LD_A:
4126 case OPC1_16_SC_LD_W:
4127 case OPC1_16_SC_MOV:
4128 case OPC1_16_SC_OR:
4129 case OPC1_16_SC_ST_A:
4130 case OPC1_16_SC_ST_W:
4131 case OPC1_16_SC_SUB_A:
4132 decode_sc_opc(ctx, op1);
4133 break;
4134 /* SLR-format */
4135 case OPC1_16_SLR_LD_A:
4136 case OPC1_16_SLR_LD_A_POSTINC:
4137 case OPC1_16_SLR_LD_BU:
4138 case OPC1_16_SLR_LD_BU_POSTINC:
4139 case OPC1_16_SLR_LD_H:
4140 case OPC1_16_SLR_LD_H_POSTINC:
4141 case OPC1_16_SLR_LD_W:
4142 case OPC1_16_SLR_LD_W_POSTINC:
4143 decode_slr_opc(ctx, op1);
4144 break;
4145 /* SRO-format */
4146 case OPC1_16_SRO_LD_A:
4147 case OPC1_16_SRO_LD_BU:
4148 case OPC1_16_SRO_LD_H:
4149 case OPC1_16_SRO_LD_W:
4150 case OPC1_16_SRO_ST_A:
4151 case OPC1_16_SRO_ST_B:
4152 case OPC1_16_SRO_ST_H:
4153 case OPC1_16_SRO_ST_W:
4154 decode_sro_opc(ctx, op1);
4155 break;
4156 /* SSRO-format */
4157 case OPC1_16_SSRO_ST_A:
4158 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4159 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4160 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4161 break;
4162 case OPC1_16_SSRO_ST_B:
4163 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4164 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4165 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4166 break;
4167 case OPC1_16_SSRO_ST_H:
4168 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4169 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4170 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4171 break;
4172 case OPC1_16_SSRO_ST_W:
4173 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4174 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4175 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4176 break;
4177 /* SR-format */
4178 case OPCM_16_SR_SYSTEM:
4179 decode_sr_system(env, ctx);
4180 break;
4181 case OPCM_16_SR_ACCU:
4182 decode_sr_accu(env, ctx);
4183 break;
4184 case OPC1_16_SR_JI:
4185 r1 = MASK_OP_SR_S1D(ctx->opcode);
4186 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
4187 break;
4188 case OPC1_16_SR_NOT:
4189 r1 = MASK_OP_SR_S1D(ctx->opcode);
4190 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
4191 break;
4192 default:
4193 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4194 }
4195 }
4196
4197 /*
4198 * 32 bit instructions
4199 */
4200
4201 /* ABS-format */
4202 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
4203 {
4204 int32_t op2;
4205 int32_t r1;
4206 uint32_t address;
4207 TCGv temp;
4208
4209 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4210 address = MASK_OP_ABS_OFF18(ctx->opcode);
4211 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4212
4213 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4214
4215 switch (op2) {
4216 case OPC2_32_ABS_LD_A:
4217 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4218 break;
4219 case OPC2_32_ABS_LD_D:
4220 CHECK_REG_PAIR(r1);
4221 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4222 break;
4223 case OPC2_32_ABS_LD_DA:
4224 CHECK_REG_PAIR(r1);
4225 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4226 break;
4227 case OPC2_32_ABS_LD_W:
4228 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4229 break;
4230 default:
4231 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4232 }
4233
4234 tcg_temp_free(temp);
4235 }
4236
4237 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
4238 {
4239 int32_t op2;
4240 int32_t r1;
4241 uint32_t address;
4242 TCGv temp;
4243
4244 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4245 address = MASK_OP_ABS_OFF18(ctx->opcode);
4246 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4247
4248 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4249
4250 switch (op2) {
4251 case OPC2_32_ABS_LD_B:
4252 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
4253 break;
4254 case OPC2_32_ABS_LD_BU:
4255 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4256 break;
4257 case OPC2_32_ABS_LD_H:
4258 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
4259 break;
4260 case OPC2_32_ABS_LD_HU:
4261 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4262 break;
4263 default:
4264 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4265 }
4266
4267 tcg_temp_free(temp);
4268 }
4269
4270 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
4271 {
4272 int32_t op2;
4273 int32_t r1;
4274 uint32_t address;
4275 TCGv temp;
4276
4277 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4278 address = MASK_OP_ABS_OFF18(ctx->opcode);
4279 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4280
4281 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4282
4283 switch (op2) {
4284 case OPC2_32_ABS_LDMST:
4285 gen_ldmst(ctx, r1, temp);
4286 break;
4287 case OPC2_32_ABS_SWAP_W:
4288 gen_swap(ctx, r1, temp);
4289 break;
4290 default:
4291 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4292 }
4293
4294 tcg_temp_free(temp);
4295 }
4296
4297 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
4298 {
4299 uint32_t op2;
4300 int32_t off18;
4301
4302 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
4303 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4304
4305 switch (op2) {
4306 case OPC2_32_ABS_LDLCX:
4307 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
4308 break;
4309 case OPC2_32_ABS_LDUCX:
4310 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
4311 break;
4312 case OPC2_32_ABS_STLCX:
4313 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
4314 break;
4315 case OPC2_32_ABS_STUCX:
4316 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
4317 break;
4318 default:
4319 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4320 }
4321 }
4322
4323 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
4324 {
4325 int32_t op2;
4326 int32_t r1;
4327 uint32_t address;
4328 TCGv temp;
4329
4330 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4331 address = MASK_OP_ABS_OFF18(ctx->opcode);
4332 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4333
4334 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4335
4336 switch (op2) {
4337 case OPC2_32_ABS_ST_A:
4338 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4339 break;
4340 case OPC2_32_ABS_ST_D:
4341 CHECK_REG_PAIR(r1);
4342 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4343 break;
4344 case OPC2_32_ABS_ST_DA:
4345 CHECK_REG_PAIR(r1);
4346 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4347 break;
4348 case OPC2_32_ABS_ST_W:
4349 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4350 break;
4351 default:
4352 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4353 }
4354 tcg_temp_free(temp);
4355 }
4356
4357 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
4358 {
4359 int32_t op2;
4360 int32_t r1;
4361 uint32_t address;
4362 TCGv temp;
4363
4364 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4365 address = MASK_OP_ABS_OFF18(ctx->opcode);
4366 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4367
4368 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4369
4370 switch (op2) {
4371 case OPC2_32_ABS_ST_B:
4372 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4373 break;
4374 case OPC2_32_ABS_ST_H:
4375 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4376 break;
4377 default:
4378 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4379 }
4380 tcg_temp_free(temp);
4381 }
4382
4383 /* Bit-format */
4384
4385 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
4386 {
4387 uint32_t op2;
4388 int r1, r2, r3;
4389 int pos1, pos2;
4390
4391 r1 = MASK_OP_BIT_S1(ctx->opcode);
4392 r2 = MASK_OP_BIT_S2(ctx->opcode);
4393 r3 = MASK_OP_BIT_D(ctx->opcode);
4394 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4395 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4396 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4397
4398
4399 switch (op2) {
4400 case OPC2_32_BIT_AND_AND_T:
4401 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4402 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
4403 break;
4404 case OPC2_32_BIT_AND_ANDN_T:
4405 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4406 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
4407 break;
4408 case OPC2_32_BIT_AND_NOR_T:
4409 if (TCG_TARGET_HAS_andc_i32) {
4410 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4411 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
4412 } else {
4413 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4414 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
4415 }
4416 break;
4417 case OPC2_32_BIT_AND_OR_T:
4418 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4419 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4420 break;
4421 default:
4422 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4423 }
4424 }
4425
4426 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
4427 {
4428 uint32_t op2;
4429 int r1, r2, r3;
4430 int pos1, pos2;
4431 r1 = MASK_OP_BIT_S1(ctx->opcode);
4432 r2 = MASK_OP_BIT_S2(ctx->opcode);
4433 r3 = MASK_OP_BIT_D(ctx->opcode);
4434 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4435 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4436 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4437
4438 switch (op2) {
4439 case OPC2_32_BIT_AND_T:
4440 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4441 pos1, pos2, &tcg_gen_and_tl);
4442 break;
4443 case OPC2_32_BIT_ANDN_T:
4444 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4445 pos1, pos2, &tcg_gen_andc_tl);
4446 break;
4447 case OPC2_32_BIT_NOR_T:
4448 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4449 pos1, pos2, &tcg_gen_nor_tl);
4450 break;
4451 case OPC2_32_BIT_OR_T:
4452 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4453 pos1, pos2, &tcg_gen_or_tl);
4454 break;
4455 default:
4456 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4457 }
4458 }
4459
4460 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
4461 {
4462 uint32_t op2;
4463 int r1, r2, r3;
4464 int pos1, pos2;
4465 TCGv temp;
4466 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4467 r1 = MASK_OP_BIT_S1(ctx->opcode);
4468 r2 = MASK_OP_BIT_S2(ctx->opcode);
4469 r3 = MASK_OP_BIT_D(ctx->opcode);
4470 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4471 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4472
4473 temp = tcg_temp_new();
4474
4475 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4476 if (op2 == OPC2_32_BIT_INSN_T) {
4477 tcg_gen_not_tl(temp, temp);
4478 }
4479 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4480 tcg_temp_free(temp);
4481 }
4482
4483 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
4484 {
4485 uint32_t op2;
4486
4487 int r1, r2, r3;
4488 int pos1, pos2;
4489
4490 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4491 r1 = MASK_OP_BIT_S1(ctx->opcode);
4492 r2 = MASK_OP_BIT_S2(ctx->opcode);
4493 r3 = MASK_OP_BIT_D(ctx->opcode);
4494 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4495 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4496
4497 switch (op2) {
4498 case OPC2_32_BIT_NAND_T:
4499 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4500 pos1, pos2, &tcg_gen_nand_tl);
4501 break;
4502 case OPC2_32_BIT_ORN_T:
4503 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4504 pos1, pos2, &tcg_gen_orc_tl);
4505 break;
4506 case OPC2_32_BIT_XNOR_T:
4507 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4508 pos1, pos2, &tcg_gen_eqv_tl);
4509 break;
4510 case OPC2_32_BIT_XOR_T:
4511 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4512 pos1, pos2, &tcg_gen_xor_tl);
4513 break;
4514 default:
4515 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4516 }
4517 }
4518
4519 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
4520 {
4521 uint32_t op2;
4522
4523 int r1, r2, r3;
4524 int pos1, pos2;
4525
4526 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4527 r1 = MASK_OP_BIT_S1(ctx->opcode);
4528 r2 = MASK_OP_BIT_S2(ctx->opcode);
4529 r3 = MASK_OP_BIT_D(ctx->opcode);
4530 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4531 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4532
4533 switch (op2) {
4534 case OPC2_32_BIT_OR_AND_T:
4535 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4536 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4537 break;
4538 case OPC2_32_BIT_OR_ANDN_T:
4539 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4540 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4541 break;
4542 case OPC2_32_BIT_OR_NOR_T:
4543 if (TCG_TARGET_HAS_orc_i32) {
4544 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4545 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4546 } else {
4547 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4548 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4549 }
4550 break;
4551 case OPC2_32_BIT_OR_OR_T:
4552 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4553 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4554 break;
4555 default:
4556 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4557 }
4558 }
4559
4560 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
4561 {
4562 uint32_t op2;
4563 int r1, r2, r3;
4564 int pos1, pos2;
4565 TCGv temp;
4566
4567 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4568 r1 = MASK_OP_BIT_S1(ctx->opcode);
4569 r2 = MASK_OP_BIT_S2(ctx->opcode);
4570 r3 = MASK_OP_BIT_D(ctx->opcode);
4571 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4572 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4573
4574 temp = tcg_temp_new();
4575
4576 switch (op2) {
4577 case OPC2_32_BIT_SH_AND_T:
4578 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4579 pos1, pos2, &tcg_gen_and_tl);
4580 break;
4581 case OPC2_32_BIT_SH_ANDN_T:
4582 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4583 pos1, pos2, &tcg_gen_andc_tl);
4584 break;
4585 case OPC2_32_BIT_SH_NOR_T:
4586 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4587 pos1, pos2, &tcg_gen_nor_tl);
4588 break;
4589 case OPC2_32_BIT_SH_OR_T:
4590 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4591 pos1, pos2, &tcg_gen_or_tl);
4592 break;
4593 default:
4594 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4595 }
4596 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4597 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4598 tcg_temp_free(temp);
4599 }
4600
4601 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
4602 {
4603 uint32_t op2;
4604 int r1, r2, r3;
4605 int pos1, pos2;
4606 TCGv temp;
4607
4608 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4609 r1 = MASK_OP_BIT_S1(ctx->opcode);
4610 r2 = MASK_OP_BIT_S2(ctx->opcode);
4611 r3 = MASK_OP_BIT_D(ctx->opcode);
4612 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4613 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4614
4615 temp = tcg_temp_new();
4616
4617 switch (op2) {
4618 case OPC2_32_BIT_SH_NAND_T:
4619 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4620 pos1, pos2, &tcg_gen_nand_tl);
4621 break;
4622 case OPC2_32_BIT_SH_ORN_T:
4623 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4624 pos1, pos2, &tcg_gen_orc_tl);
4625 break;
4626 case OPC2_32_BIT_SH_XNOR_T:
4627 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4628 pos1, pos2, &tcg_gen_eqv_tl);
4629 break;
4630 case OPC2_32_BIT_SH_XOR_T:
4631 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4632 pos1, pos2, &tcg_gen_xor_tl);
4633 break;
4634 default:
4635 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4636 }
4637 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4638 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4639 tcg_temp_free(temp);
4640 }
4641
4642 /* BO-format */
4643
4644
4645 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
4646 DisasContext *ctx)
4647 {
4648 uint32_t op2;
4649 uint32_t off10;
4650 int32_t r1, r2;
4651 TCGv temp;
4652
4653 r1 = MASK_OP_BO_S1D(ctx->opcode);
4654 r2 = MASK_OP_BO_S2(ctx->opcode);
4655 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4656 op2 = MASK_OP_BO_OP2(ctx->opcode);
4657
4658 switch (op2) {
4659 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4660 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4661 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4662 /* instruction to access the cache */
4663 break;
4664 case OPC2_32_BO_CACHEA_WI_POSTINC:
4665 case OPC2_32_BO_CACHEA_W_POSTINC:
4666 case OPC2_32_BO_CACHEA_I_POSTINC:
4667 /* instruction to access the cache, but we still need to handle
4668 the addressing mode */
4669 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4670 break;
4671 case OPC2_32_BO_CACHEA_WI_PREINC:
4672 case OPC2_32_BO_CACHEA_W_PREINC:
4673 case OPC2_32_BO_CACHEA_I_PREINC:
4674 /* instruction to access the cache, but we still need to handle
4675 the addressing mode */
4676 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4677 break;
4678 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4679 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4680 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
4681 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4682 }
4683 break;
4684 case OPC2_32_BO_CACHEI_W_POSTINC:
4685 case OPC2_32_BO_CACHEI_WI_POSTINC:
4686 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4687 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4688 } else {
4689 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4690 }
4691 break;
4692 case OPC2_32_BO_CACHEI_W_PREINC:
4693 case OPC2_32_BO_CACHEI_WI_PREINC:
4694 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4695 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4696 } else {
4697 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4698 }
4699 break;
4700 case OPC2_32_BO_ST_A_SHORTOFF:
4701 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4702 break;
4703 case OPC2_32_BO_ST_A_POSTINC:
4704 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4705 MO_LESL);
4706 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4707 break;
4708 case OPC2_32_BO_ST_A_PREINC:
4709 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4710 break;
4711 case OPC2_32_BO_ST_B_SHORTOFF:
4712 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4713 break;
4714 case OPC2_32_BO_ST_B_POSTINC:
4715 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4716 MO_UB);
4717 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4718 break;
4719 case OPC2_32_BO_ST_B_PREINC:
4720 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4721 break;
4722 case OPC2_32_BO_ST_D_SHORTOFF:
4723 CHECK_REG_PAIR(r1);
4724 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4725 off10, ctx);
4726 break;
4727 case OPC2_32_BO_ST_D_POSTINC:
4728 CHECK_REG_PAIR(r1);
4729 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4730 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4731 break;
4732 case OPC2_32_BO_ST_D_PREINC:
4733 CHECK_REG_PAIR(r1);
4734 temp = tcg_temp_new();
4735 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4736 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4737 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4738 tcg_temp_free(temp);
4739 break;
4740 case OPC2_32_BO_ST_DA_SHORTOFF:
4741 CHECK_REG_PAIR(r1);
4742 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4743 off10, ctx);
4744 break;
4745 case OPC2_32_BO_ST_DA_POSTINC:
4746 CHECK_REG_PAIR(r1);
4747 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4748 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4749 break;
4750 case OPC2_32_BO_ST_DA_PREINC:
4751 CHECK_REG_PAIR(r1);
4752 temp = tcg_temp_new();
4753 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4754 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4755 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4756 tcg_temp_free(temp);
4757 break;
4758 case OPC2_32_BO_ST_H_SHORTOFF:
4759 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4760 break;
4761 case OPC2_32_BO_ST_H_POSTINC:
4762 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4763 MO_LEUW);
4764 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4765 break;
4766 case OPC2_32_BO_ST_H_PREINC:
4767 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4768 break;
4769 case OPC2_32_BO_ST_Q_SHORTOFF:
4770 temp = tcg_temp_new();
4771 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4772 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4773 tcg_temp_free(temp);
4774 break;
4775 case OPC2_32_BO_ST_Q_POSTINC:
4776 temp = tcg_temp_new();
4777 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4778 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4779 MO_LEUW);
4780 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4781 tcg_temp_free(temp);
4782 break;
4783 case OPC2_32_BO_ST_Q_PREINC:
4784 temp = tcg_temp_new();
4785 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4786 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4787 tcg_temp_free(temp);
4788 break;
4789 case OPC2_32_BO_ST_W_SHORTOFF:
4790 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4791 break;
4792 case OPC2_32_BO_ST_W_POSTINC:
4793 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4794 MO_LEUL);
4795 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4796 break;
4797 case OPC2_32_BO_ST_W_PREINC:
4798 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4799 break;
4800 default:
4801 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4802 }
4803 }
4804
4805 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
4806 DisasContext *ctx)
4807 {
4808 uint32_t op2;
4809 uint32_t off10;
4810 int32_t r1, r2;
4811 TCGv temp, temp2, temp3;
4812
4813 r1 = MASK_OP_BO_S1D(ctx->opcode);
4814 r2 = MASK_OP_BO_S2(ctx->opcode);
4815 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4816 op2 = MASK_OP_BO_OP2(ctx->opcode);
4817
4818 temp = tcg_temp_new();
4819 temp2 = tcg_temp_new();
4820 temp3 = tcg_const_i32(off10);
4821 CHECK_REG_PAIR(r2);
4822 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4823 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4824
4825 switch (op2) {
4826 case OPC2_32_BO_CACHEA_WI_BR:
4827 case OPC2_32_BO_CACHEA_W_BR:
4828 case OPC2_32_BO_CACHEA_I_BR:
4829 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4830 break;
4831 case OPC2_32_BO_CACHEA_WI_CIRC:
4832 case OPC2_32_BO_CACHEA_W_CIRC:
4833 case OPC2_32_BO_CACHEA_I_CIRC:
4834 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4835 break;
4836 case OPC2_32_BO_ST_A_BR:
4837 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4838 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4839 break;
4840 case OPC2_32_BO_ST_A_CIRC:
4841 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4842 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4843 break;
4844 case OPC2_32_BO_ST_B_BR:
4845 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4846 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4847 break;
4848 case OPC2_32_BO_ST_B_CIRC:
4849 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4850 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4851 break;
4852 case OPC2_32_BO_ST_D_BR:
4853 CHECK_REG_PAIR(r1);
4854 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4855 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4856 break;
4857 case OPC2_32_BO_ST_D_CIRC:
4858 CHECK_REG_PAIR(r1);
4859 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4860 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4861 tcg_gen_addi_tl(temp, temp, 4);
4862 tcg_gen_rem_tl(temp, temp, temp2);
4863 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4864 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4865 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4866 break;
4867 case OPC2_32_BO_ST_DA_BR:
4868 CHECK_REG_PAIR(r1);
4869 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4870 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4871 break;
4872 case OPC2_32_BO_ST_DA_CIRC:
4873 CHECK_REG_PAIR(r1);
4874 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4875 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4876 tcg_gen_addi_tl(temp, temp, 4);
4877 tcg_gen_rem_tl(temp, temp, temp2);
4878 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4879 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4880 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4881 break;
4882 case OPC2_32_BO_ST_H_BR:
4883 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4884 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4885 break;
4886 case OPC2_32_BO_ST_H_CIRC:
4887 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4888 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4889 break;
4890 case OPC2_32_BO_ST_Q_BR:
4891 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4892 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4893 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4894 break;
4895 case OPC2_32_BO_ST_Q_CIRC:
4896 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4897 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4898 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4899 break;
4900 case OPC2_32_BO_ST_W_BR:
4901 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4902 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4903 break;
4904 case OPC2_32_BO_ST_W_CIRC:
4905 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4906 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4907 break;
4908 default:
4909 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4910 }
4911 tcg_temp_free(temp);
4912 tcg_temp_free(temp2);
4913 tcg_temp_free(temp3);
4914 }
4915
4916 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
4917 DisasContext *ctx)
4918 {
4919 uint32_t op2;
4920 uint32_t off10;
4921 int32_t r1, r2;
4922 TCGv temp;
4923
4924 r1 = MASK_OP_BO_S1D(ctx->opcode);
4925 r2 = MASK_OP_BO_S2(ctx->opcode);
4926 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4927 op2 = MASK_OP_BO_OP2(ctx->opcode);
4928
4929 switch (op2) {
4930 case OPC2_32_BO_LD_A_SHORTOFF:
4931 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4932 break;
4933 case OPC2_32_BO_LD_A_POSTINC:
4934 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4935 MO_LEUL);
4936 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4937 break;
4938 case OPC2_32_BO_LD_A_PREINC:
4939 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4940 break;
4941 case OPC2_32_BO_LD_B_SHORTOFF:
4942 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4943 break;
4944 case OPC2_32_BO_LD_B_POSTINC:
4945 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4946 MO_SB);
4947 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4948 break;
4949 case OPC2_32_BO_LD_B_PREINC:
4950 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4951 break;
4952 case OPC2_32_BO_LD_BU_SHORTOFF:
4953 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4954 break;
4955 case OPC2_32_BO_LD_BU_POSTINC:
4956 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4957 MO_UB);
4958 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4959 break;
4960 case OPC2_32_BO_LD_BU_PREINC:
4961 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4962 break;
4963 case OPC2_32_BO_LD_D_SHORTOFF:
4964 CHECK_REG_PAIR(r1);
4965 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4966 off10, ctx);
4967 break;
4968 case OPC2_32_BO_LD_D_POSTINC:
4969 CHECK_REG_PAIR(r1);
4970 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4971 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4972 break;
4973 case OPC2_32_BO_LD_D_PREINC:
4974 CHECK_REG_PAIR(r1);
4975 temp = tcg_temp_new();
4976 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4977 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4978 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4979 tcg_temp_free(temp);
4980 break;
4981 case OPC2_32_BO_LD_DA_SHORTOFF:
4982 CHECK_REG_PAIR(r1);
4983 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4984 off10, ctx);
4985 break;
4986 case OPC2_32_BO_LD_DA_POSTINC:
4987 CHECK_REG_PAIR(r1);
4988 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4989 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4990 break;
4991 case OPC2_32_BO_LD_DA_PREINC:
4992 CHECK_REG_PAIR(r1);
4993 temp = tcg_temp_new();
4994 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4995 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4996 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4997 tcg_temp_free(temp);
4998 break;
4999 case OPC2_32_BO_LD_H_SHORTOFF:
5000 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
5001 break;
5002 case OPC2_32_BO_LD_H_POSTINC:
5003 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5004 MO_LESW);
5005 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5006 break;
5007 case OPC2_32_BO_LD_H_PREINC:
5008 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
5009 break;
5010 case OPC2_32_BO_LD_HU_SHORTOFF:
5011 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5012 break;
5013 case OPC2_32_BO_LD_HU_POSTINC:
5014 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5015 MO_LEUW);
5016 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5017 break;
5018 case OPC2_32_BO_LD_HU_PREINC:
5019 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5020 break;
5021 case OPC2_32_BO_LD_Q_SHORTOFF:
5022 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5023 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5024 break;
5025 case OPC2_32_BO_LD_Q_POSTINC:
5026 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5027 MO_LEUW);
5028 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5029 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5030 break;
5031 case OPC2_32_BO_LD_Q_PREINC:
5032 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5033 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5034 break;
5035 case OPC2_32_BO_LD_W_SHORTOFF:
5036 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
5037 break;
5038 case OPC2_32_BO_LD_W_POSTINC:
5039 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5040 MO_LEUL);
5041 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5042 break;
5043 case OPC2_32_BO_LD_W_PREINC:
5044 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
5045 break;
5046 default:
5047 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5048 }
5049 }
5050
5051 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
5052 DisasContext *ctx)
5053 {
5054 uint32_t op2;
5055 uint32_t off10;
5056 int r1, r2;
5057
5058 TCGv temp, temp2, temp3;
5059
5060 r1 = MASK_OP_BO_S1D(ctx->opcode);
5061 r2 = MASK_OP_BO_S2(ctx->opcode);
5062 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5063 op2 = MASK_OP_BO_OP2(ctx->opcode);
5064
5065 temp = tcg_temp_new();
5066 temp2 = tcg_temp_new();
5067 temp3 = tcg_const_i32(off10);
5068 CHECK_REG_PAIR(r2);
5069 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5070 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5071
5072
5073 switch (op2) {
5074 case OPC2_32_BO_LD_A_BR:
5075 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5076 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5077 break;
5078 case OPC2_32_BO_LD_A_CIRC:
5079 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5080 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5081 break;
5082 case OPC2_32_BO_LD_B_BR:
5083 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
5084 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5085 break;
5086 case OPC2_32_BO_LD_B_CIRC:
5087 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
5088 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5089 break;
5090 case OPC2_32_BO_LD_BU_BR:
5091 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
5092 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5093 break;
5094 case OPC2_32_BO_LD_BU_CIRC:
5095 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
5096 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5097 break;
5098 case OPC2_32_BO_LD_D_BR:
5099 CHECK_REG_PAIR(r1);
5100 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
5101 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5102 break;
5103 case OPC2_32_BO_LD_D_CIRC:
5104 CHECK_REG_PAIR(r1);
5105 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5106 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
5107 tcg_gen_addi_tl(temp, temp, 4);
5108 tcg_gen_rem_tl(temp, temp, temp2);
5109 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5110 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5111 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5112 break;
5113 case OPC2_32_BO_LD_DA_BR:
5114 CHECK_REG_PAIR(r1);
5115 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
5116 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5117 break;
5118 case OPC2_32_BO_LD_DA_CIRC:
5119 CHECK_REG_PAIR(r1);
5120 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5121 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
5122 tcg_gen_addi_tl(temp, temp, 4);
5123 tcg_gen_rem_tl(temp, temp, temp2);
5124 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5125 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5126 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5127 break;
5128 case OPC2_32_BO_LD_H_BR:
5129 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5130 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5131 break;
5132 case OPC2_32_BO_LD_H_CIRC:
5133 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5134 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5135 break;
5136 case OPC2_32_BO_LD_HU_BR:
5137 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5138 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5139 break;
5140 case OPC2_32_BO_LD_HU_CIRC:
5141 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5142 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5143 break;
5144 case OPC2_32_BO_LD_Q_BR:
5145 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5146 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5147 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5148 break;
5149 case OPC2_32_BO_LD_Q_CIRC:
5150 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5151 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5152 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5153 break;
5154 case OPC2_32_BO_LD_W_BR:
5155 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5156 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5157 break;
5158 case OPC2_32_BO_LD_W_CIRC:
5159 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5160 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5161 break;
5162 default:
5163 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5164 }
5165 tcg_temp_free(temp);
5166 tcg_temp_free(temp2);
5167 tcg_temp_free(temp3);
5168 }
5169
5170 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
5171 DisasContext *ctx)
5172 {
5173 uint32_t op2;
5174 uint32_t off10;
5175 int r1, r2;
5176
5177 TCGv temp, temp2;
5178
5179 r1 = MASK_OP_BO_S1D(ctx->opcode);
5180 r2 = MASK_OP_BO_S2(ctx->opcode);
5181 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5182 op2 = MASK_OP_BO_OP2(ctx->opcode);
5183
5184
5185 temp = tcg_temp_new();
5186 temp2 = tcg_temp_new();
5187
5188 switch (op2) {
5189 case OPC2_32_BO_LDLCX_SHORTOFF:
5190 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5191 gen_helper_ldlcx(cpu_env, temp);
5192 break;
5193 case OPC2_32_BO_LDMST_SHORTOFF:
5194 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5195 gen_ldmst(ctx, r1, temp);
5196 break;
5197 case OPC2_32_BO_LDMST_POSTINC:
5198 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5199 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5200 break;
5201 case OPC2_32_BO_LDMST_PREINC:
5202 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5203 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5204 break;
5205 case OPC2_32_BO_LDUCX_SHORTOFF:
5206 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5207 gen_helper_lducx(cpu_env, temp);
5208 break;
5209 case OPC2_32_BO_LEA_SHORTOFF:
5210 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
5211 break;
5212 case OPC2_32_BO_STLCX_SHORTOFF:
5213 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5214 gen_helper_stlcx(cpu_env, temp);
5215 break;
5216 case OPC2_32_BO_STUCX_SHORTOFF:
5217 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5218 gen_helper_stucx(cpu_env, temp);
5219 break;
5220 case OPC2_32_BO_SWAP_W_SHORTOFF:
5221 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5222 gen_swap(ctx, r1, temp);
5223 break;
5224 case OPC2_32_BO_SWAP_W_POSTINC:
5225 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5226 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5227 break;
5228 case OPC2_32_BO_SWAP_W_PREINC:
5229 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5230 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5231 break;
5232 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
5233 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5234 gen_cmpswap(ctx, r1, temp);
5235 break;
5236 case OPC2_32_BO_CMPSWAP_W_POSTINC:
5237 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5238 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5239 break;
5240 case OPC2_32_BO_CMPSWAP_W_PREINC:
5241 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5242 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5243 break;
5244 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
5245 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5246 gen_swapmsk(ctx, r1, temp);
5247 break;
5248 case OPC2_32_BO_SWAPMSK_W_POSTINC:
5249 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5250 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5251 break;
5252 case OPC2_32_BO_SWAPMSK_W_PREINC:
5253 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5254 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5255 break;
5256 default:
5257 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5258 }
5259 tcg_temp_free(temp);
5260 tcg_temp_free(temp2);
5261 }
5262
5263 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
5264 DisasContext *ctx)
5265 {
5266 uint32_t op2;
5267 uint32_t off10;
5268 int r1, r2;
5269
5270 TCGv temp, temp2, temp3;
5271
5272 r1 = MASK_OP_BO_S1D(ctx->opcode);
5273 r2 = MASK_OP_BO_S2(ctx->opcode);
5274 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5275 op2 = MASK_OP_BO_OP2(ctx->opcode);
5276
5277 temp = tcg_temp_new();
5278 temp2 = tcg_temp_new();
5279 temp3 = tcg_const_i32(off10);
5280 CHECK_REG_PAIR(r2);
5281 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5282 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5283
5284 switch (op2) {
5285 case OPC2_32_BO_LDMST_BR:
5286 gen_ldmst(ctx, r1, temp2);
5287 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5288 break;
5289 case OPC2_32_BO_LDMST_CIRC:
5290 gen_ldmst(ctx, r1, temp2);
5291 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5292 break;
5293 case OPC2_32_BO_SWAP_W_BR:
5294 gen_swap(ctx, r1, temp2);
5295 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5296 break;
5297 case OPC2_32_BO_SWAP_W_CIRC:
5298 gen_swap(ctx, r1, temp2);
5299 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5300 break;
5301 case OPC2_32_BO_CMPSWAP_W_BR:
5302 gen_cmpswap(ctx, r1, temp2);
5303 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5304 break;
5305 case OPC2_32_BO_CMPSWAP_W_CIRC:
5306 gen_cmpswap(ctx, r1, temp2);
5307 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5308 break;
5309 case OPC2_32_BO_SWAPMSK_W_BR:
5310 gen_swapmsk(ctx, r1, temp2);
5311 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5312 break;
5313 case OPC2_32_BO_SWAPMSK_W_CIRC:
5314 gen_swapmsk(ctx, r1, temp2);
5315 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5316 break;
5317 default:
5318 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5319 }
5320
5321 tcg_temp_free(temp);
5322 tcg_temp_free(temp2);
5323 tcg_temp_free(temp3);
5324 }
5325
5326 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
5327 {
5328 int r1, r2;
5329 int32_t address;
5330 TCGv temp;
5331
5332 r1 = MASK_OP_BOL_S1D(ctx->opcode);
5333 r2 = MASK_OP_BOL_S2(ctx->opcode);
5334 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
5335
5336 switch (op1) {
5337 case OPC1_32_BOL_LD_A_LONGOFF:
5338 temp = tcg_temp_new();
5339 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5340 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
5341 tcg_temp_free(temp);
5342 break;
5343 case OPC1_32_BOL_LD_W_LONGOFF:
5344 temp = tcg_temp_new();
5345 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5346 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
5347 tcg_temp_free(temp);
5348 break;
5349 case OPC1_32_BOL_LEA_LONGOFF:
5350 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
5351 break;
5352 case OPC1_32_BOL_ST_A_LONGOFF:
5353 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5354 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
5355 } else {
5356 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5357 }
5358 break;
5359 case OPC1_32_BOL_ST_W_LONGOFF:
5360 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
5361 break;
5362 case OPC1_32_BOL_LD_B_LONGOFF:
5363 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5364 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5365 } else {
5366 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5367 }
5368 break;
5369 case OPC1_32_BOL_LD_BU_LONGOFF:
5370 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5371 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
5372 } else {
5373 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5374 }
5375 break;
5376 case OPC1_32_BOL_LD_H_LONGOFF:
5377 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5378 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5379 } else {
5380 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5381 }
5382 break;
5383 case OPC1_32_BOL_LD_HU_LONGOFF:
5384 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5385 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
5386 } else {
5387 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5388 }
5389 break;
5390 case OPC1_32_BOL_ST_B_LONGOFF:
5391 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5392 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5393 } else {
5394 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5395 }
5396 break;
5397 case OPC1_32_BOL_ST_H_LONGOFF:
5398 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5399 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5400 } else {
5401 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5402 }
5403 break;
5404 default:
5405 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5406 }
5407 }
5408
5409 /* RC format */
5410 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5411 {
5412 uint32_t op2;
5413 int r1, r2;
5414 int32_t const9;
5415 TCGv temp;
5416
5417 r2 = MASK_OP_RC_D(ctx->opcode);
5418 r1 = MASK_OP_RC_S1(ctx->opcode);
5419 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5420 op2 = MASK_OP_RC_OP2(ctx->opcode);
5421
5422 temp = tcg_temp_new();
5423
5424 switch (op2) {
5425 case OPC2_32_RC_AND:
5426 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5427 break;
5428 case OPC2_32_RC_ANDN:
5429 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5430 break;
5431 case OPC2_32_RC_NAND:
5432 tcg_gen_movi_tl(temp, const9);
5433 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5434 break;
5435 case OPC2_32_RC_NOR:
5436 tcg_gen_movi_tl(temp, const9);
5437 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5438 break;
5439 case OPC2_32_RC_OR:
5440 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5441 break;
5442 case OPC2_32_RC_ORN:
5443 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5444 break;
5445 case OPC2_32_RC_SH:
5446 const9 = sextract32(const9, 0, 6);
5447 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5448 break;
5449 case OPC2_32_RC_SH_H:
5450 const9 = sextract32(const9, 0, 5);
5451 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5452 break;
5453 case OPC2_32_RC_SHA:
5454 const9 = sextract32(const9, 0, 6);
5455 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5456 break;
5457 case OPC2_32_RC_SHA_H:
5458 const9 = sextract32(const9, 0, 5);
5459 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5460 break;
5461 case OPC2_32_RC_SHAS:
5462 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5463 break;
5464 case OPC2_32_RC_XNOR:
5465 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5466 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5467 break;
5468 case OPC2_32_RC_XOR:
5469 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5470 break;
5471 default:
5472 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5473 }
5474 tcg_temp_free(temp);
5475 }
5476
5477 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5478 {
5479 uint32_t op2;
5480 int r1, r2;
5481 int16_t const9;
5482
5483 TCGv temp;
5484
5485 r2 = MASK_OP_RC_D(ctx->opcode);
5486 r1 = MASK_OP_RC_S1(ctx->opcode);
5487 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5488
5489 op2 = MASK_OP_RC_OP2(ctx->opcode);
5490
5491 temp = tcg_temp_new();
5492
5493 switch (op2) {
5494 case OPC2_32_RC_ABSDIF:
5495 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5496 break;
5497 case OPC2_32_RC_ABSDIFS:
5498 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5499 break;
5500 case OPC2_32_RC_ADD:
5501 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5502 break;
5503 case OPC2_32_RC_ADDC:
5504 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5505 break;
5506 case OPC2_32_RC_ADDS:
5507 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5508 break;
5509 case OPC2_32_RC_ADDS_U:
5510 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5511 break;
5512 case OPC2_32_RC_ADDX:
5513 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5514 break;
5515 case OPC2_32_RC_AND_EQ:
5516 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5517 const9, &tcg_gen_and_tl);
5518 break;
5519 case OPC2_32_RC_AND_GE:
5520 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5521 const9, &tcg_gen_and_tl);
5522 break;
5523 case OPC2_32_RC_AND_GE_U:
5524 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5525 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5526 const9, &tcg_gen_and_tl);
5527 break;
5528 case OPC2_32_RC_AND_LT:
5529 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5530 const9, &tcg_gen_and_tl);
5531 break;
5532 case OPC2_32_RC_AND_LT_U:
5533 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5534 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5535 const9, &tcg_gen_and_tl);
5536 break;
5537 case OPC2_32_RC_AND_NE:
5538 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5539 const9, &tcg_gen_and_tl);
5540 break;
5541 case OPC2_32_RC_EQ:
5542 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5543 break;
5544 case OPC2_32_RC_EQANY_B:
5545 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5546 break;
5547 case OPC2_32_RC_EQANY_H:
5548 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5549 break;
5550 case OPC2_32_RC_GE:
5551 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5552 break;
5553 case OPC2_32_RC_GE_U:
5554 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5555 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5556 break;
5557 case OPC2_32_RC_LT:
5558 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5559 break;
5560 case OPC2_32_RC_LT_U:
5561 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5562 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5563 break;
5564 case OPC2_32_RC_MAX:
5565 tcg_gen_movi_tl(temp, const9);
5566 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5567 cpu_gpr_d[r1], temp);
5568 break;
5569 case OPC2_32_RC_MAX_U:
5570 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5571 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5572 cpu_gpr_d[r1], temp);
5573 break;
5574 case OPC2_32_RC_MIN:
5575 tcg_gen_movi_tl(temp, const9);
5576 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5577 cpu_gpr_d[r1], temp);
5578 break;
5579 case OPC2_32_RC_MIN_U:
5580 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5581 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5582 cpu_gpr_d[r1], temp);
5583 break;
5584 case OPC2_32_RC_NE:
5585 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5586 break;
5587 case OPC2_32_RC_OR_EQ:
5588 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5589 const9, &tcg_gen_or_tl);
5590 break;
5591 case OPC2_32_RC_OR_GE:
5592 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5593 const9, &tcg_gen_or_tl);
5594 break;
5595 case OPC2_32_RC_OR_GE_U:
5596 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5597 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5598 const9, &tcg_gen_or_tl);
5599 break;
5600 case OPC2_32_RC_OR_LT:
5601 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5602 const9, &tcg_gen_or_tl);
5603 break;
5604 case OPC2_32_RC_OR_LT_U:
5605 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5606 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5607 const9, &tcg_gen_or_tl);
5608 break;
5609 case OPC2_32_RC_OR_NE:
5610 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5611 const9, &tcg_gen_or_tl);
5612 break;
5613 case OPC2_32_RC_RSUB:
5614 tcg_gen_movi_tl(temp, const9);
5615 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5616 break;
5617 case OPC2_32_RC_RSUBS:
5618 tcg_gen_movi_tl(temp, const9);
5619 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5620 break;
5621 case OPC2_32_RC_RSUBS_U:
5622 tcg_gen_movi_tl(temp, const9);
5623 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5624 break;
5625 case OPC2_32_RC_SH_EQ:
5626 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5627 break;
5628 case OPC2_32_RC_SH_GE:
5629 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5630 break;
5631 case OPC2_32_RC_SH_GE_U:
5632 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5633 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5634 break;
5635 case OPC2_32_RC_SH_LT:
5636 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5637 break;
5638 case OPC2_32_RC_SH_LT_U:
5639 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5640 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5641 break;
5642 case OPC2_32_RC_SH_NE:
5643 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5644 break;
5645 case OPC2_32_RC_XOR_EQ:
5646 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5647 const9, &tcg_gen_xor_tl);
5648 break;
5649 case OPC2_32_RC_XOR_GE:
5650 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5651 const9, &tcg_gen_xor_tl);
5652 break;
5653 case OPC2_32_RC_XOR_GE_U:
5654 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5655 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5656 const9, &tcg_gen_xor_tl);
5657 break;
5658 case OPC2_32_RC_XOR_LT:
5659 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5660 const9, &tcg_gen_xor_tl);
5661 break;
5662 case OPC2_32_RC_XOR_LT_U:
5663 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5664 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5665 const9, &tcg_gen_xor_tl);
5666 break;
5667 case OPC2_32_RC_XOR_NE:
5668 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5669 const9, &tcg_gen_xor_tl);
5670 break;
5671 default:
5672 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5673 }
5674 tcg_temp_free(temp);
5675 }
5676
5677 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
5678 {
5679 uint32_t op2;
5680 uint32_t const9;
5681
5682 op2 = MASK_OP_RC_OP2(ctx->opcode);
5683 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5684
5685 switch (op2) {
5686 case OPC2_32_RC_BISR:
5687 gen_helper_1arg(bisr, const9);
5688 break;
5689 case OPC2_32_RC_SYSCALL:
5690 /* TODO: Add exception generation */
5691 break;
5692 default:
5693 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5694 }
5695 }
5696
5697 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
5698 {
5699 uint32_t op2;
5700 int r1, r2;
5701 int16_t const9;
5702
5703 r2 = MASK_OP_RC_D(ctx->opcode);
5704 r1 = MASK_OP_RC_S1(ctx->opcode);
5705 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5706
5707 op2 = MASK_OP_RC_OP2(ctx->opcode);
5708
5709 switch (op2) {
5710 case OPC2_32_RC_MUL_32:
5711 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5712 break;
5713 case OPC2_32_RC_MUL_64:
5714 CHECK_REG_PAIR(r2);
5715 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5716 break;
5717 case OPC2_32_RC_MULS_32:
5718 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5719 break;
5720 case OPC2_32_RC_MUL_U_64:
5721 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5722 CHECK_REG_PAIR(r2);
5723 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5724 break;
5725 case OPC2_32_RC_MULS_U_32:
5726 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5727 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5728 break;
5729 default:
5730 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5731 }
5732 }
5733
5734 /* RCPW format */
5735 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
5736 {
5737 uint32_t op2;
5738 int r1, r2;
5739 int32_t pos, width, const4;
5740
5741 TCGv temp;
5742
5743 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5744 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5745 r2 = MASK_OP_RCPW_D(ctx->opcode);
5746 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5747 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5748 pos = MASK_OP_RCPW_POS(ctx->opcode);
5749
5750 switch (op2) {
5751 case OPC2_32_RCPW_IMASK:
5752 CHECK_REG_PAIR(r2);
5753 /* if pos + width > 31 undefined result */
5754 if (pos + width <= 31) {
5755 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5756 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5757 }
5758 break;
5759 case OPC2_32_RCPW_INSERT:
5760 /* if pos + width > 32 undefined result */
5761 if (pos + width <= 32) {
5762 temp = tcg_const_i32(const4);
5763 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5764 tcg_temp_free(temp);
5765 }
5766 break;
5767 default:
5768 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5769 }
5770 }
5771
5772 /* RCRW format */
5773
5774 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
5775 {
5776 uint32_t op2;
5777 int r1, r3, r4;
5778 int32_t width, const4;
5779
5780 TCGv temp, temp2, temp3;
5781
5782 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5783 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5784 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5785 r4 = MASK_OP_RCRW_D(ctx->opcode);
5786 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5787 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5788
5789 temp = tcg_temp_new();
5790 temp2 = tcg_temp_new();
5791
5792 switch (op2) {
5793 case OPC2_32_RCRW_IMASK:
5794 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
5795 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5796 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
5797 tcg_gen_movi_tl(temp2, const4);
5798 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
5799 break;
5800 case OPC2_32_RCRW_INSERT:
5801 temp3 = tcg_temp_new();
5802
5803 tcg_gen_movi_tl(temp, width);
5804 tcg_gen_movi_tl(temp2, const4);
5805 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
5806 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
5807
5808 tcg_temp_free(temp3);
5809 break;
5810 default:
5811 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5812 }
5813 tcg_temp_free(temp);
5814 tcg_temp_free(temp2);
5815 }
5816
5817 /* RCR format */
5818
5819 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5820 {
5821 uint32_t op2;
5822 int r1, r3, r4;
5823 int32_t const9;
5824
5825 TCGv temp, temp2;
5826
5827 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5828 r1 = MASK_OP_RCR_S1(ctx->opcode);
5829 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5830 r3 = MASK_OP_RCR_S3(ctx->opcode);
5831 r4 = MASK_OP_RCR_D(ctx->opcode);
5832
5833 switch (op2) {
5834 case OPC2_32_RCR_CADD:
5835 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5836 cpu_gpr_d[r4]);
5837 break;
5838 case OPC2_32_RCR_CADDN:
5839 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5840 cpu_gpr_d[r4]);
5841 break;
5842 case OPC2_32_RCR_SEL:
5843 temp = tcg_const_i32(0);
5844 temp2 = tcg_const_i32(const9);
5845 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5846 cpu_gpr_d[r1], temp2);
5847 tcg_temp_free(temp);
5848 tcg_temp_free(temp2);
5849 break;
5850 case OPC2_32_RCR_SELN:
5851 temp = tcg_const_i32(0);
5852 temp2 = tcg_const_i32(const9);
5853 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5854 cpu_gpr_d[r1], temp2);
5855 tcg_temp_free(temp);
5856 tcg_temp_free(temp2);
5857 break;
5858 default:
5859 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5860 }
5861 }
5862
5863 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
5864 {
5865 uint32_t op2;
5866 int r1, r3, r4;
5867 int32_t const9;
5868
5869
5870 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5871 r1 = MASK_OP_RCR_S1(ctx->opcode);
5872 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5873 r3 = MASK_OP_RCR_S3(ctx->opcode);
5874 r4 = MASK_OP_RCR_D(ctx->opcode);
5875
5876 switch (op2) {
5877 case OPC2_32_RCR_MADD_32:
5878 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5879 break;
5880 case OPC2_32_RCR_MADD_64:
5881 CHECK_REG_PAIR(r4);
5882 CHECK_REG_PAIR(r3);
5883 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5884 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5885 break;
5886 case OPC2_32_RCR_MADDS_32:
5887 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5888 break;
5889 case OPC2_32_RCR_MADDS_64:
5890 CHECK_REG_PAIR(r4);
5891 CHECK_REG_PAIR(r3);
5892 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5893 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5894 break;
5895 case OPC2_32_RCR_MADD_U_64:
5896 CHECK_REG_PAIR(r4);
5897 CHECK_REG_PAIR(r3);
5898 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5899 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5900 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5901 break;
5902 case OPC2_32_RCR_MADDS_U_32:
5903 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5904 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5905 break;
5906 case OPC2_32_RCR_MADDS_U_64:
5907 CHECK_REG_PAIR(r4);
5908 CHECK_REG_PAIR(r3);
5909 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5910 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5911 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5912 break;
5913 default:
5914 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5915 }
5916 }
5917
5918 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
5919 {
5920 uint32_t op2;
5921 int r1, r3, r4;
5922 int32_t const9;
5923
5924
5925 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5926 r1 = MASK_OP_RCR_S1(ctx->opcode);
5927 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5928 r3 = MASK_OP_RCR_S3(ctx->opcode);
5929 r4 = MASK_OP_RCR_D(ctx->opcode);
5930
5931 switch (op2) {
5932 case OPC2_32_RCR_MSUB_32:
5933 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5934 break;
5935 case OPC2_32_RCR_MSUB_64:
5936 CHECK_REG_PAIR(r4);
5937 CHECK_REG_PAIR(r3);
5938 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5939 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5940 break;
5941 case OPC2_32_RCR_MSUBS_32:
5942 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5943 break;
5944 case OPC2_32_RCR_MSUBS_64:
5945 CHECK_REG_PAIR(r4);
5946 CHECK_REG_PAIR(r3);
5947 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5948 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5949 break;
5950 case OPC2_32_RCR_MSUB_U_64:
5951 CHECK_REG_PAIR(r4);
5952 CHECK_REG_PAIR(r3);
5953 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5954 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5955 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5956 break;
5957 case OPC2_32_RCR_MSUBS_U_32:
5958 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5959 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5960 break;
5961 case OPC2_32_RCR_MSUBS_U_64:
5962 CHECK_REG_PAIR(r4);
5963 CHECK_REG_PAIR(r3);
5964 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5965 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5966 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5967 break;
5968 default:
5969 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5970 }
5971 }
5972
5973 /* RLC format */
5974
5975 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
5976 uint32_t op1)
5977 {
5978 int32_t const16;
5979 int r1, r2;
5980
5981 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5982 r1 = MASK_OP_RLC_S1(ctx->opcode);
5983 r2 = MASK_OP_RLC_D(ctx->opcode);
5984
5985 switch (op1) {
5986 case OPC1_32_RLC_ADDI:
5987 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5988 break;
5989 case OPC1_32_RLC_ADDIH:
5990 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5991 break;
5992 case OPC1_32_RLC_ADDIH_A:
5993 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5994 break;
5995 case OPC1_32_RLC_MFCR:
5996 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5997 gen_mfcr(env, cpu_gpr_d[r2], const16);
5998 break;
5999 case OPC1_32_RLC_MOV:
6000 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
6001 break;
6002 case OPC1_32_RLC_MOV_64:
6003 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6004 CHECK_REG_PAIR(r2);
6005 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
6006 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
6007 } else {
6008 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6009 }
6010 break;
6011 case OPC1_32_RLC_MOV_U:
6012 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
6013 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
6014 break;
6015 case OPC1_32_RLC_MOV_H:
6016 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
6017 break;
6018 case OPC1_32_RLC_MOVH_A:
6019 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
6020 break;
6021 case OPC1_32_RLC_MTCR:
6022 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
6023 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
6024 break;
6025 default:
6026 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6027 }
6028 }
6029
6030 /* RR format */
6031 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
6032 {
6033 uint32_t op2;
6034 int r3, r2, r1;
6035
6036 r3 = MASK_OP_RR_D(ctx->opcode);
6037 r2 = MASK_OP_RR_S2(ctx->opcode);
6038 r1 = MASK_OP_RR_S1(ctx->opcode);
6039 op2 = MASK_OP_RR_OP2(ctx->opcode);
6040
6041 switch (op2) {
6042 case OPC2_32_RR_ABS:
6043 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6044 break;
6045 case OPC2_32_RR_ABS_B:
6046 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6047 break;
6048 case OPC2_32_RR_ABS_H:
6049 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6050 break;
6051 case OPC2_32_RR_ABSDIF:
6052 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6053 break;
6054 case OPC2_32_RR_ABSDIF_B:
6055 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6056 cpu_gpr_d[r2]);
6057 break;
6058 case OPC2_32_RR_ABSDIF_H:
6059 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6060 cpu_gpr_d[r2]);
6061 break;
6062 case OPC2_32_RR_ABSDIFS:
6063 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6064 cpu_gpr_d[r2]);
6065 break;
6066 case OPC2_32_RR_ABSDIFS_H:
6067 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6068 cpu_gpr_d[r2]);
6069 break;
6070 case OPC2_32_RR_ABSS:
6071 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6072 break;
6073 case OPC2_32_RR_ABSS_H:
6074 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6075 break;
6076 case OPC2_32_RR_ADD:
6077 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6078 break;
6079 case OPC2_32_RR_ADD_B:
6080 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6081 break;
6082 case OPC2_32_RR_ADD_H:
6083 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6084 break;
6085 case OPC2_32_RR_ADDC:
6086 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6087 break;
6088 case OPC2_32_RR_ADDS:
6089 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6090 break;
6091 case OPC2_32_RR_ADDS_H:
6092 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6093 cpu_gpr_d[r2]);
6094 break;
6095 case OPC2_32_RR_ADDS_HU:
6096 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6097 cpu_gpr_d[r2]);
6098 break;
6099 case OPC2_32_RR_ADDS_U:
6100 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6101 cpu_gpr_d[r2]);
6102 break;
6103 case OPC2_32_RR_ADDX:
6104 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6105 break;
6106 case OPC2_32_RR_AND_EQ:
6107 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6108 cpu_gpr_d[r2], &tcg_gen_and_tl);
6109 break;
6110 case OPC2_32_RR_AND_GE:
6111 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6112 cpu_gpr_d[r2], &tcg_gen_and_tl);
6113 break;
6114 case OPC2_32_RR_AND_GE_U:
6115 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6116 cpu_gpr_d[r2], &tcg_gen_and_tl);
6117 break;
6118 case OPC2_32_RR_AND_LT:
6119 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6120 cpu_gpr_d[r2], &tcg_gen_and_tl);
6121 break;
6122 case OPC2_32_RR_AND_LT_U:
6123 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6124 cpu_gpr_d[r2], &tcg_gen_and_tl);
6125 break;
6126 case OPC2_32_RR_AND_NE:
6127 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6128 cpu_gpr_d[r2], &tcg_gen_and_tl);
6129 break;
6130 case OPC2_32_RR_EQ:
6131 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6132 cpu_gpr_d[r2]);
6133 break;
6134 case OPC2_32_RR_EQ_B:
6135 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6136 break;
6137 case OPC2_32_RR_EQ_H:
6138 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6139 break;
6140 case OPC2_32_RR_EQ_W:
6141 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6142 break;
6143 case OPC2_32_RR_EQANY_B:
6144 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6145 break;
6146 case OPC2_32_RR_EQANY_H:
6147 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6148 break;
6149 case OPC2_32_RR_GE:
6150 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6151 cpu_gpr_d[r2]);
6152 break;
6153 case OPC2_32_RR_GE_U:
6154 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6155 cpu_gpr_d[r2]);
6156 break;
6157 case OPC2_32_RR_LT:
6158 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6159 cpu_gpr_d[r2]);
6160 break;
6161 case OPC2_32_RR_LT_U:
6162 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6163 cpu_gpr_d[r2]);
6164 break;
6165 case OPC2_32_RR_LT_B:
6166 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6167 break;
6168 case OPC2_32_RR_LT_BU:
6169 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6170 break;
6171 case OPC2_32_RR_LT_H:
6172 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6173 break;
6174 case OPC2_32_RR_LT_HU:
6175 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6176 break;
6177 case OPC2_32_RR_LT_W:
6178 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6179 break;
6180 case OPC2_32_RR_LT_WU:
6181 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6182 break;
6183 case OPC2_32_RR_MAX:
6184 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6185 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6186 break;
6187 case OPC2_32_RR_MAX_U:
6188 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6189 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6190 break;
6191 case OPC2_32_RR_MAX_B:
6192 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6193 break;
6194 case OPC2_32_RR_MAX_BU:
6195 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6196 break;
6197 case OPC2_32_RR_MAX_H:
6198 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6199 break;
6200 case OPC2_32_RR_MAX_HU:
6201 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6202 break;
6203 case OPC2_32_RR_MIN:
6204 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6205 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6206 break;
6207 case OPC2_32_RR_MIN_U:
6208 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6209 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6210 break;
6211 case OPC2_32_RR_MIN_B:
6212 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6213 break;
6214 case OPC2_32_RR_MIN_BU:
6215 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6216 break;
6217 case OPC2_32_RR_MIN_H:
6218 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6219 break;
6220 case OPC2_32_RR_MIN_HU:
6221 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6222 break;
6223 case OPC2_32_RR_MOV:
6224 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6225 break;
6226 case OPC2_32_RR_NE:
6227 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6228 cpu_gpr_d[r2]);
6229 break;
6230 case OPC2_32_RR_OR_EQ:
6231 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6232 cpu_gpr_d[r2], &tcg_gen_or_tl);
6233 break;
6234 case OPC2_32_RR_OR_GE:
6235 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6236 cpu_gpr_d[r2], &tcg_gen_or_tl);
6237 break;
6238 case OPC2_32_RR_OR_GE_U:
6239 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6240 cpu_gpr_d[r2], &tcg_gen_or_tl);
6241 break;
6242 case OPC2_32_RR_OR_LT:
6243 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6244 cpu_gpr_d[r2], &tcg_gen_or_tl);
6245 break;
6246 case OPC2_32_RR_OR_LT_U:
6247 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6248 cpu_gpr_d[r2], &tcg_gen_or_tl);
6249 break;
6250 case OPC2_32_RR_OR_NE:
6251 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6252 cpu_gpr_d[r2], &tcg_gen_or_tl);
6253 break;
6254 case OPC2_32_RR_SAT_B:
6255 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
6256 break;
6257 case OPC2_32_RR_SAT_BU:
6258 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
6259 break;
6260 case OPC2_32_RR_SAT_H:
6261 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
6262 break;
6263 case OPC2_32_RR_SAT_HU:
6264 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
6265 break;
6266 case OPC2_32_RR_SH_EQ:
6267 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6268 cpu_gpr_d[r2]);
6269 break;
6270 case OPC2_32_RR_SH_GE:
6271 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6272 cpu_gpr_d[r2]);
6273 break;
6274 case OPC2_32_RR_SH_GE_U:
6275 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6276 cpu_gpr_d[r2]);
6277 break;
6278 case OPC2_32_RR_SH_LT:
6279 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6280 cpu_gpr_d[r2]);
6281 break;
6282 case OPC2_32_RR_SH_LT_U:
6283 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6284 cpu_gpr_d[r2]);
6285 break;
6286 case OPC2_32_RR_SH_NE:
6287 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6288 cpu_gpr_d[r2]);
6289 break;
6290 case OPC2_32_RR_SUB:
6291 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6292 break;
6293 case OPC2_32_RR_SUB_B:
6294 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6295 break;
6296 case OPC2_32_RR_SUB_H:
6297 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6298 break;
6299 case OPC2_32_RR_SUBC:
6300 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6301 break;
6302 case OPC2_32_RR_SUBS:
6303 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6304 break;
6305 case OPC2_32_RR_SUBS_U:
6306 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6307 break;
6308 case OPC2_32_RR_SUBS_H:
6309 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6310 cpu_gpr_d[r2]);
6311 break;
6312 case OPC2_32_RR_SUBS_HU:
6313 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6314 cpu_gpr_d[r2]);
6315 break;
6316 case OPC2_32_RR_SUBX:
6317 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6318 break;
6319 case OPC2_32_RR_XOR_EQ:
6320 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6321 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6322 break;
6323 case OPC2_32_RR_XOR_GE:
6324 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6325 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6326 break;
6327 case OPC2_32_RR_XOR_GE_U:
6328 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6329 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6330 break;
6331 case OPC2_32_RR_XOR_LT:
6332 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6333 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6334 break;
6335 case OPC2_32_RR_XOR_LT_U:
6336 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6337 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6338 break;
6339 case OPC2_32_RR_XOR_NE:
6340 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6341 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6342 break;
6343 default:
6344 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6345 }
6346 }
6347
6348 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
6349 {
6350 uint32_t op2;
6351 int r3, r2, r1;
6352 TCGv temp;
6353
6354 r3 = MASK_OP_RR_D(ctx->opcode);
6355 r2 = MASK_OP_RR_S2(ctx->opcode);
6356 r1 = MASK_OP_RR_S1(ctx->opcode);
6357
6358 temp = tcg_temp_new();
6359 op2 = MASK_OP_RR_OP2(ctx->opcode);
6360
6361 switch (op2) {
6362 case OPC2_32_RR_AND:
6363 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6364 break;
6365 case OPC2_32_RR_ANDN:
6366 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6367 break;
6368 case OPC2_32_RR_CLO:
6369 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6370 break;
6371 case OPC2_32_RR_CLO_H:
6372 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6373 break;
6374 case OPC2_32_RR_CLS:
6375 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6376 break;
6377 case OPC2_32_RR_CLS_H:
6378 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6379 break;
6380 case OPC2_32_RR_CLZ:
6381 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6382 break;
6383 case OPC2_32_RR_CLZ_H:
6384 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6385 break;
6386 case OPC2_32_RR_NAND:
6387 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6388 break;
6389 case OPC2_32_RR_NOR:
6390 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6391 break;
6392 case OPC2_32_RR_OR:
6393 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6394 break;
6395 case OPC2_32_RR_ORN:
6396 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6397 break;
6398 case OPC2_32_RR_SH:
6399 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6400 break;
6401 case OPC2_32_RR_SH_H:
6402 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6403 break;
6404 case OPC2_32_RR_SHA:
6405 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6406 break;
6407 case OPC2_32_RR_SHA_H:
6408 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6409 break;
6410 case OPC2_32_RR_SHAS:
6411 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6412 break;
6413 case OPC2_32_RR_XNOR:
6414 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6415 break;
6416 case OPC2_32_RR_XOR:
6417 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6418 break;
6419 default:
6420 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6421 }
6422 tcg_temp_free(temp);
6423 }
6424
6425 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
6426 {
6427 uint32_t op2, n;
6428 int r1, r2, r3;
6429 TCGv temp;
6430
6431 op2 = MASK_OP_RR_OP2(ctx->opcode);
6432 r3 = MASK_OP_RR_D(ctx->opcode);
6433 r2 = MASK_OP_RR_S2(ctx->opcode);
6434 r1 = MASK_OP_RR_S1(ctx->opcode);
6435 n = MASK_OP_RR_N(ctx->opcode);
6436
6437 switch (op2) {
6438 case OPC2_32_RR_ADD_A:
6439 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6440 break;
6441 case OPC2_32_RR_ADDSC_A:
6442 temp = tcg_temp_new();
6443 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6444 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6445 tcg_temp_free(temp);
6446 break;
6447 case OPC2_32_RR_ADDSC_AT:
6448 temp = tcg_temp_new();
6449 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6450 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6451 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6452 tcg_temp_free(temp);
6453 break;
6454 case OPC2_32_RR_EQ_A:
6455 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6456 cpu_gpr_a[r2]);
6457 break;
6458 case OPC2_32_RR_EQZ:
6459 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6460 break;
6461 case OPC2_32_RR_GE_A:
6462 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6463 cpu_gpr_a[r2]);
6464 break;
6465 case OPC2_32_RR_LT_A:
6466 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6467 cpu_gpr_a[r2]);
6468 break;
6469 case OPC2_32_RR_MOV_A:
6470 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6471 break;
6472 case OPC2_32_RR_MOV_AA:
6473 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6474 break;
6475 case OPC2_32_RR_MOV_D:
6476 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6477 break;
6478 case OPC2_32_RR_NE_A:
6479 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6480 cpu_gpr_a[r2]);
6481 break;
6482 case OPC2_32_RR_NEZ_A:
6483 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6484 break;
6485 case OPC2_32_RR_SUB_A:
6486 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6487 break;
6488 default:
6489 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6490 }
6491 }
6492
6493 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
6494 {
6495 uint32_t op2;
6496 int r1;
6497
6498 op2 = MASK_OP_RR_OP2(ctx->opcode);
6499 r1 = MASK_OP_RR_S1(ctx->opcode);
6500
6501 switch (op2) {
6502 case OPC2_32_RR_JI:
6503 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6504 break;
6505 case OPC2_32_RR_JLI:
6506 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
6507 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6508 break;
6509 case OPC2_32_RR_CALLI:
6510 gen_helper_1arg(call, ctx->next_pc);
6511 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6512 break;
6513 case OPC2_32_RR_FCALLI:
6514 gen_fcall_save_ctx(ctx);
6515 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6516 break;
6517 default:
6518 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6519 }
6520 tcg_gen_exit_tb(0);
6521 ctx->bstate = BS_BRANCH;
6522 }
6523
6524 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
6525 {
6526 uint32_t op2;
6527 int r1, r2, r3;
6528
6529 TCGv temp, temp2, temp3;
6530
6531 op2 = MASK_OP_RR_OP2(ctx->opcode);
6532 r3 = MASK_OP_RR_D(ctx->opcode);
6533 r2 = MASK_OP_RR_S2(ctx->opcode);
6534 r1 = MASK_OP_RR_S1(ctx->opcode);
6535
6536 switch (op2) {
6537 case OPC2_32_RR_BMERGE:
6538 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6539 break;
6540 case OPC2_32_RR_BSPLIT:
6541 CHECK_REG_PAIR(r3);
6542 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6543 break;
6544 case OPC2_32_RR_DVINIT_B:
6545 CHECK_REG_PAIR(r3);
6546 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6547 cpu_gpr_d[r2]);
6548 break;
6549 case OPC2_32_RR_DVINIT_BU:
6550 temp = tcg_temp_new();
6551 temp2 = tcg_temp_new();
6552 temp3 = tcg_temp_new();
6553 CHECK_REG_PAIR(r3);
6554 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6555 /* reset av */
6556 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6557 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6558 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6559 tcg_gen_neg_tl(temp, temp3);
6560 /* use cpu_PSW_AV to compare against 0 */
6561 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6562 temp, temp3);
6563 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6564 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6565 temp2, cpu_gpr_d[r2]);
6566 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6567 } else {
6568 /* overflow = (D[b] == 0) */
6569 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6570 }
6571 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6572 /* sv */
6573 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6574 /* write result */
6575 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6576 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6577
6578 tcg_temp_free(temp);
6579 tcg_temp_free(temp2);
6580 tcg_temp_free(temp3);
6581 break;
6582 case OPC2_32_RR_DVINIT_H:
6583 CHECK_REG_PAIR(r3);
6584 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6585 cpu_gpr_d[r2]);
6586 break;
6587 case OPC2_32_RR_DVINIT_HU:
6588 temp = tcg_temp_new();
6589 temp2 = tcg_temp_new();
6590 temp3 = tcg_temp_new();
6591 CHECK_REG_PAIR(r3);
6592 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6593 /* reset av */
6594 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6595 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6596 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6597 tcg_gen_neg_tl(temp, temp3);
6598 /* use cpu_PSW_AV to compare against 0 */
6599 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6600 temp, temp3);
6601 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6602 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6603 temp2, cpu_gpr_d[r2]);
6604 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6605 } else {
6606 /* overflow = (D[b] == 0) */
6607 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6608 }
6609 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6610 /* sv */
6611 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6612 /* write result */
6613 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6614 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6615 tcg_temp_free(temp);
6616 tcg_temp_free(temp2);
6617 tcg_temp_free(temp3);
6618 break;
6619 case OPC2_32_RR_DVINIT:
6620 temp = tcg_temp_new();
6621 temp2 = tcg_temp_new();
6622 CHECK_REG_PAIR(r3);
6623 /* overflow = ((D[b] == 0) ||
6624 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6625 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6626 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6627 tcg_gen_and_tl(temp, temp, temp2);
6628 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6629 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6630 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6631 /* sv */
6632 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6633 /* reset av */
6634 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6635 /* write result */
6636 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6637 /* sign extend to high reg */
6638 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6639 tcg_temp_free(temp);
6640 tcg_temp_free(temp2);
6641 break;
6642 case OPC2_32_RR_DVINIT_U:
6643 /* overflow = (D[b] == 0) */
6644 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6645 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6646 /* sv */
6647 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6648 /* reset av */
6649 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6650 /* write result */
6651 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6652 /* zero extend to high reg*/
6653 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6654 break;
6655 case OPC2_32_RR_PARITY:
6656 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6657 break;
6658 case OPC2_32_RR_UNPACK:
6659 CHECK_REG_PAIR(r3);
6660 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6661 break;
6662 case OPC2_32_RR_CRC32:
6663 if (tricore_feature(env, TRICORE_FEATURE_161)) {
6664 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6665 } else {
6666 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6667 }
6668 break;
6669 case OPC2_32_RR_DIV:
6670 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6671 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6672 cpu_gpr_d[r2]);
6673 } else {
6674 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6675 }
6676 break;
6677 case OPC2_32_RR_DIV_U:
6678 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6679 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6680 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6681 } else {
6682 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6683 }
6684 break;
6685 case OPC2_32_RR_MUL_F:
6686 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6687 break;
6688 case OPC2_32_RR_DIV_F:
6689 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6690 break;
6691 case OPC2_32_RR_CMP_F:
6692 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6693 break;
6694 case OPC2_32_RR_FTOI:
6695 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6696 break;
6697 case OPC2_32_RR_ITOF:
6698 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6699 break;
6700 default:
6701 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6702 }
6703 }
6704
6705 /* RR1 Format */
6706 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
6707 {
6708 uint32_t op2;
6709
6710 int r1, r2, r3;
6711 TCGv n;
6712 TCGv_i64 temp64;
6713
6714 r1 = MASK_OP_RR1_S1(ctx->opcode);
6715 r2 = MASK_OP_RR1_S2(ctx->opcode);
6716 r3 = MASK_OP_RR1_D(ctx->opcode);
6717 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6718 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6719
6720 switch (op2) {
6721 case OPC2_32_RR1_MUL_H_32_LL:
6722 temp64 = tcg_temp_new_i64();
6723 CHECK_REG_PAIR(r3);
6724 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6725 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6726 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6727 tcg_temp_free_i64(temp64);
6728 break;
6729 case OPC2_32_RR1_MUL_H_32_LU:
6730 temp64 = tcg_temp_new_i64();
6731 CHECK_REG_PAIR(r3);
6732 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6733 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6734 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6735 tcg_temp_free_i64(temp64);
6736 break;
6737 case OPC2_32_RR1_MUL_H_32_UL:
6738 temp64 = tcg_temp_new_i64();
6739 CHECK_REG_PAIR(r3);
6740 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6741 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6742 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6743 tcg_temp_free_i64(temp64);
6744 break;
6745 case OPC2_32_RR1_MUL_H_32_UU:
6746 temp64 = tcg_temp_new_i64();
6747 CHECK_REG_PAIR(r3);
6748 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6749 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6750 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6751 tcg_temp_free_i64(temp64);
6752 break;
6753 case OPC2_32_RR1_MULM_H_64_LL:
6754 temp64 = tcg_temp_new_i64();
6755 CHECK_REG_PAIR(r3);
6756 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6757 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6758 /* reset V bit */
6759 tcg_gen_movi_tl(cpu_PSW_V, 0);
6760 /* reset AV bit */
6761 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6762 tcg_temp_free_i64(temp64);
6763 break;
6764 case OPC2_32_RR1_MULM_H_64_LU:
6765 temp64 = tcg_temp_new_i64();
6766 CHECK_REG_PAIR(r3);
6767 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6768 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6769 /* reset V bit */
6770 tcg_gen_movi_tl(cpu_PSW_V, 0);
6771 /* reset AV bit */
6772 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6773 tcg_temp_free_i64(temp64);
6774 break;
6775 case OPC2_32_RR1_MULM_H_64_UL:
6776 temp64 = tcg_temp_new_i64();
6777 CHECK_REG_PAIR(r3);
6778 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6779 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6780 /* reset V bit */
6781 tcg_gen_movi_tl(cpu_PSW_V, 0);
6782 /* reset AV bit */
6783 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6784 tcg_temp_free_i64(temp64);
6785 break;
6786 case OPC2_32_RR1_MULM_H_64_UU:
6787 temp64 = tcg_temp_new_i64();
6788 CHECK_REG_PAIR(r3);
6789 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6790 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6791 /* reset V bit */
6792 tcg_gen_movi_tl(cpu_PSW_V, 0);
6793 /* reset AV bit */
6794 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6795 tcg_temp_free_i64(temp64);
6796
6797 break;
6798 case OPC2_32_RR1_MULR_H_16_LL:
6799 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6800 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6801 break;
6802 case OPC2_32_RR1_MULR_H_16_LU:
6803 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6804 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6805 break;
6806 case OPC2_32_RR1_MULR_H_16_UL:
6807 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6808 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6809 break;
6810 case OPC2_32_RR1_MULR_H_16_UU:
6811 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6812 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6813 break;
6814 default:
6815 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6816 }
6817 tcg_temp_free(n);
6818 }
6819
6820 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
6821 {
6822 uint32_t op2;
6823 int r1, r2, r3;
6824 uint32_t n;
6825
6826 TCGv temp, temp2;
6827
6828 r1 = MASK_OP_RR1_S1(ctx->opcode);
6829 r2 = MASK_OP_RR1_S2(ctx->opcode);
6830 r3 = MASK_OP_RR1_D(ctx->opcode);
6831 n = MASK_OP_RR1_N(ctx->opcode);
6832 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6833
6834 temp = tcg_temp_new();
6835 temp2 = tcg_temp_new();
6836
6837 switch (op2) {
6838 case OPC2_32_RR1_MUL_Q_32:
6839 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6840 break;
6841 case OPC2_32_RR1_MUL_Q_64:
6842 CHECK_REG_PAIR(r3);
6843 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6844 n, 0);
6845 break;
6846 case OPC2_32_RR1_MUL_Q_32_L:
6847 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6848 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6849 break;
6850 case OPC2_32_RR1_MUL_Q_64_L:
6851 CHECK_REG_PAIR(r3);
6852 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6853 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6854 break;
6855 case OPC2_32_RR1_MUL_Q_32_U:
6856 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6857 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6858 break;
6859 case OPC2_32_RR1_MUL_Q_64_U:
6860 CHECK_REG_PAIR(r3);
6861 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6862 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6863 break;
6864 case OPC2_32_RR1_MUL_Q_32_LL:
6865 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6866 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6867 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6868 break;
6869 case OPC2_32_RR1_MUL_Q_32_UU:
6870 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6871 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6872 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6873 break;
6874 case OPC2_32_RR1_MULR_Q_32_L:
6875 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6876 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6877 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6878 break;
6879 case OPC2_32_RR1_MULR_Q_32_U:
6880 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6881 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6882 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6883 break;
6884 default:
6885 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6886 }
6887 tcg_temp_free(temp);
6888 tcg_temp_free(temp2);
6889 }
6890
6891 /* RR2 format */
6892 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
6893 {
6894 uint32_t op2;
6895 int r1, r2, r3;
6896
6897 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6898 r1 = MASK_OP_RR2_S1(ctx->opcode);
6899 r2 = MASK_OP_RR2_S2(ctx->opcode);
6900 r3 = MASK_OP_RR2_D(ctx->opcode);
6901 switch (op2) {
6902 case OPC2_32_RR2_MUL_32:
6903 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6904 break;
6905 case OPC2_32_RR2_MUL_64:
6906 CHECK_REG_PAIR(r3);
6907 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6908 cpu_gpr_d[r2]);
6909 break;
6910 case OPC2_32_RR2_MULS_32:
6911 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6912 cpu_gpr_d[r2]);
6913 break;
6914 case OPC2_32_RR2_MUL_U_64:
6915 CHECK_REG_PAIR(r3);
6916 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6917 cpu_gpr_d[r2]);
6918 break;
6919 case OPC2_32_RR2_MULS_U_32:
6920 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6921 cpu_gpr_d[r2]);
6922 break;
6923 default:
6924 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6925 }
6926 }
6927
6928 /* RRPW format */
6929 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
6930 {
6931 uint32_t op2;
6932 int r1, r2, r3;
6933 int32_t pos, width;
6934
6935 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6936 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6937 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6938 r3 = MASK_OP_RRPW_D(ctx->opcode);
6939 pos = MASK_OP_RRPW_POS(ctx->opcode);
6940 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6941
6942 switch (op2) {
6943 case OPC2_32_RRPW_EXTR:
6944 if (pos + width <= 31) {
6945 /* optimize special cases */
6946 if ((pos == 0) && (width == 8)) {
6947 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6948 } else if ((pos == 0) && (width == 16)) {
6949 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6950 } else {
6951 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6952 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6953 }
6954 }
6955 break;
6956 case OPC2_32_RRPW_EXTR_U:
6957 if (width == 0) {
6958 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6959 } else {
6960 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6961 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6962 }
6963 break;
6964 case OPC2_32_RRPW_IMASK:
6965 CHECK_REG_PAIR(r3);
6966 if (pos + width <= 31) {
6967 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
6968 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6969 }
6970 break;
6971 case OPC2_32_RRPW_INSERT:
6972 if (pos + width <= 31) {
6973 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6974 width, pos);
6975 }
6976 break;
6977 default:
6978 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6979 }
6980 }
6981
6982 /* RRR format */
6983 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
6984 {
6985 uint32_t op2;
6986 int r1, r2, r3, r4;
6987 TCGv temp;
6988
6989 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6990 r1 = MASK_OP_RRR_S1(ctx->opcode);
6991 r2 = MASK_OP_RRR_S2(ctx->opcode);
6992 r3 = MASK_OP_RRR_S3(ctx->opcode);
6993 r4 = MASK_OP_RRR_D(ctx->opcode);
6994
6995 switch (op2) {
6996 case OPC2_32_RRR_CADD:
6997 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6998 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6999 break;
7000 case OPC2_32_RRR_CADDN:
7001 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
7002 cpu_gpr_d[r3]);
7003 break;
7004 case OPC2_32_RRR_CSUB:
7005 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
7006 cpu_gpr_d[r3]);
7007 break;
7008 case OPC2_32_RRR_CSUBN:
7009 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
7010 cpu_gpr_d[r3]);
7011 break;
7012 case OPC2_32_RRR_SEL:
7013 temp = tcg_const_i32(0);
7014 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
7015 cpu_gpr_d[r1], cpu_gpr_d[r2]);
7016 tcg_temp_free(temp);
7017 break;
7018 case OPC2_32_RRR_SELN:
7019 temp = tcg_const_i32(0);
7020 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
7021 cpu_gpr_d[r1], cpu_gpr_d[r2]);
7022 tcg_temp_free(temp);
7023 break;
7024 default:
7025 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7026 }
7027 }
7028
7029 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
7030 {
7031 uint32_t op2;
7032
7033 int r1, r2, r3, r4;
7034
7035 op2 = MASK_OP_RRR_OP2(ctx->opcode);
7036 r1 = MASK_OP_RRR_S1(ctx->opcode);
7037 r2 = MASK_OP_RRR_S2(ctx->opcode);
7038 r3 = MASK_OP_RRR_S3(ctx->opcode);
7039 r4 = MASK_OP_RRR_D(ctx->opcode);
7040
7041 switch (op2) {
7042 case OPC2_32_RRR_DVADJ:
7043 CHECK_REG_PAIR(r3);
7044 CHECK_REG_PAIR(r4);
7045 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7046 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7047 break;
7048 case OPC2_32_RRR_DVSTEP:
7049 CHECK_REG_PAIR(r3);
7050 CHECK_REG_PAIR(r4);
7051 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7052 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7053 break;
7054 case OPC2_32_RRR_DVSTEP_U:
7055 CHECK_REG_PAIR(r3);
7056 CHECK_REG_PAIR(r4);
7057 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7058 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7059 break;
7060 case OPC2_32_RRR_IXMAX:
7061 CHECK_REG_PAIR(r3);
7062 CHECK_REG_PAIR(r4);
7063 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7064 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7065 break;
7066 case OPC2_32_RRR_IXMAX_U:
7067 CHECK_REG_PAIR(r3);
7068 CHECK_REG_PAIR(r4);
7069 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7070 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7071 break;
7072 case OPC2_32_RRR_IXMIN:
7073 CHECK_REG_PAIR(r3);
7074 CHECK_REG_PAIR(r4);
7075 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7076 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7077 break;
7078 case OPC2_32_RRR_IXMIN_U:
7079 CHECK_REG_PAIR(r3);
7080 CHECK_REG_PAIR(r4);
7081 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7082 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7083 break;
7084 case OPC2_32_RRR_PACK:
7085 CHECK_REG_PAIR(r3);
7086 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
7087 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
7088 break;
7089 case OPC2_32_RRR_ADD_F:
7090 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
7091 break;
7092 case OPC2_32_RRR_SUB_F:
7093 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
7094 break;
7095 default:
7096 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7097 }
7098 }
7099
7100 /* RRR2 format */
7101 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
7102 {
7103 uint32_t op2;
7104 uint32_t r1, r2, r3, r4;
7105
7106 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
7107 r1 = MASK_OP_RRR2_S1(ctx->opcode);
7108 r2 = MASK_OP_RRR2_S2(ctx->opcode);
7109 r3 = MASK_OP_RRR2_S3(ctx->opcode);
7110 r4 = MASK_OP_RRR2_D(ctx->opcode);
7111 switch (op2) {
7112 case OPC2_32_RRR2_MADD_32:
7113 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
7114 cpu_gpr_d[r2]);
7115 break;
7116 case OPC2_32_RRR2_MADD_64:
7117 CHECK_REG_PAIR(r4);
7118 CHECK_REG_PAIR(r3);
7119 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7120 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7121 break;
7122 case OPC2_32_RRR2_MADDS_32:
7123 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7124 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7125 break;
7126 case OPC2_32_RRR2_MADDS_64:
7127 CHECK_REG_PAIR(r4);
7128 CHECK_REG_PAIR(r3);
7129 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7130 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7131 break;
7132 case OPC2_32_RRR2_MADD_U_64:
7133 CHECK_REG_PAIR(r4);
7134 CHECK_REG_PAIR(r3);
7135 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7136 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7137 break;
7138 case OPC2_32_RRR2_MADDS_U_32:
7139 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7140 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7141 break;
7142 case OPC2_32_RRR2_MADDS_U_64:
7143 CHECK_REG_PAIR(r4);
7144 CHECK_REG_PAIR(r3);
7145 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7146 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7147 break;
7148 default:
7149 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7150 }
7151 }
7152
7153 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
7154 {
7155 uint32_t op2;
7156 uint32_t r1, r2, r3, r4;
7157
7158 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
7159 r1 = MASK_OP_RRR2_S1(ctx->opcode);
7160 r2 = MASK_OP_RRR2_S2(ctx->opcode);
7161 r3 = MASK_OP_RRR2_S3(ctx->opcode);
7162 r4 = MASK_OP_RRR2_D(ctx->opcode);
7163
7164 switch (op2) {
7165 case OPC2_32_RRR2_MSUB_32:
7166 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
7167 cpu_gpr_d[r2]);
7168 break;
7169 case OPC2_32_RRR2_MSUB_64:
7170 CHECK_REG_PAIR(r4);
7171 CHECK_REG_PAIR(r3);
7172 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7173 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7174 break;
7175 case OPC2_32_RRR2_MSUBS_32:
7176 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7177 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7178 break;
7179 case OPC2_32_RRR2_MSUBS_64:
7180 CHECK_REG_PAIR(r4);
7181 CHECK_REG_PAIR(r3);
7182 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7183 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7184 break;
7185 case OPC2_32_RRR2_MSUB_U_64:
7186 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7187 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7188 break;
7189 case OPC2_32_RRR2_MSUBS_U_32:
7190 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7191 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7192 break;
7193 case OPC2_32_RRR2_MSUBS_U_64:
7194 CHECK_REG_PAIR(r4);
7195 CHECK_REG_PAIR(r3);
7196 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7197 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7198 break;
7199 default:
7200 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7201 }
7202 }
7203
7204 /* RRR1 format */
7205 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
7206 {
7207 uint32_t op2;
7208 uint32_t r1, r2, r3, r4, n;
7209
7210 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7211 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7212 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7213 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7214 r4 = MASK_OP_RRR1_D(ctx->opcode);
7215 n = MASK_OP_RRR1_N(ctx->opcode);
7216
7217 switch (op2) {
7218 case OPC2_32_RRR1_MADD_H_LL:
7219 CHECK_REG_PAIR(r4);
7220 CHECK_REG_PAIR(r3);
7221 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7222 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7223 break;
7224 case OPC2_32_RRR1_MADD_H_LU:
7225 CHECK_REG_PAIR(r4);
7226 CHECK_REG_PAIR(r3);
7227 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7228 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7229 break;
7230 case OPC2_32_RRR1_MADD_H_UL:
7231 CHECK_REG_PAIR(r4);
7232 CHECK_REG_PAIR(r3);
7233 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7234 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7235 break;
7236 case OPC2_32_RRR1_MADD_H_UU:
7237 CHECK_REG_PAIR(r4);
7238 CHECK_REG_PAIR(r3);
7239 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7240 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7241 break;
7242 case OPC2_32_RRR1_MADDS_H_LL:
7243 CHECK_REG_PAIR(r4);
7244 CHECK_REG_PAIR(r3);
7245 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7246 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7247 break;
7248 case OPC2_32_RRR1_MADDS_H_LU:
7249 CHECK_REG_PAIR(r4);
7250 CHECK_REG_PAIR(r3);
7251 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7252 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7253 break;
7254 case OPC2_32_RRR1_MADDS_H_UL:
7255 CHECK_REG_PAIR(r4);
7256 CHECK_REG_PAIR(r3);
7257 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7258 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7259 break;
7260 case OPC2_32_RRR1_MADDS_H_UU:
7261 CHECK_REG_PAIR(r4);
7262 CHECK_REG_PAIR(r3);
7263 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7264 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7265 break;
7266 case OPC2_32_RRR1_MADDM_H_LL:
7267 CHECK_REG_PAIR(r4);
7268 CHECK_REG_PAIR(r3);
7269 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7270 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7271 break;
7272 case OPC2_32_RRR1_MADDM_H_LU:
7273 CHECK_REG_PAIR(r4);
7274 CHECK_REG_PAIR(r3);
7275 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7276 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7277 break;
7278 case OPC2_32_RRR1_MADDM_H_UL:
7279 CHECK_REG_PAIR(r4);
7280 CHECK_REG_PAIR(r3);
7281 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7282 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7283 break;
7284 case OPC2_32_RRR1_MADDM_H_UU:
7285 CHECK_REG_PAIR(r4);
7286 CHECK_REG_PAIR(r3);
7287 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7288 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7289 break;
7290 case OPC2_32_RRR1_MADDMS_H_LL:
7291 CHECK_REG_PAIR(r4);
7292 CHECK_REG_PAIR(r3);
7293 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7294 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7295 break;
7296 case OPC2_32_RRR1_MADDMS_H_LU:
7297 CHECK_REG_PAIR(r4);
7298 CHECK_REG_PAIR(r3);
7299 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7300 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7301 break;
7302 case OPC2_32_RRR1_MADDMS_H_UL:
7303 CHECK_REG_PAIR(r4);
7304 CHECK_REG_PAIR(r3);
7305 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7306 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7307 break;
7308 case OPC2_32_RRR1_MADDMS_H_UU:
7309 CHECK_REG_PAIR(r4);
7310 CHECK_REG_PAIR(r3);
7311 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7312 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7313 break;
7314 case OPC2_32_RRR1_MADDR_H_LL:
7315 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7316 cpu_gpr_d[r2], n, MODE_LL);
7317 break;
7318 case OPC2_32_RRR1_MADDR_H_LU:
7319 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7320 cpu_gpr_d[r2], n, MODE_LU);
7321 break;
7322 case OPC2_32_RRR1_MADDR_H_UL:
7323 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7324 cpu_gpr_d[r2], n, MODE_UL);
7325 break;
7326 case OPC2_32_RRR1_MADDR_H_UU:
7327 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7328 cpu_gpr_d[r2], n, MODE_UU);
7329 break;
7330 case OPC2_32_RRR1_MADDRS_H_LL:
7331 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7332 cpu_gpr_d[r2], n, MODE_LL);
7333 break;
7334 case OPC2_32_RRR1_MADDRS_H_LU:
7335 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7336 cpu_gpr_d[r2], n, MODE_LU);
7337 break;
7338 case OPC2_32_RRR1_MADDRS_H_UL:
7339 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7340 cpu_gpr_d[r2], n, MODE_UL);
7341 break;
7342 case OPC2_32_RRR1_MADDRS_H_UU:
7343 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7344 cpu_gpr_d[r2], n, MODE_UU);
7345 break;
7346 default:
7347 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7348 }
7349 }
7350
7351 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
7352 {
7353 uint32_t op2;
7354 uint32_t r1, r2, r3, r4, n;
7355 TCGv temp, temp2;
7356
7357 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7358 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7359 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7360 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7361 r4 = MASK_OP_RRR1_D(ctx->opcode);
7362 n = MASK_OP_RRR1_N(ctx->opcode);
7363
7364 temp = tcg_const_i32(n);
7365 temp2 = tcg_temp_new();
7366
7367 switch (op2) {
7368 case OPC2_32_RRR1_MADD_Q_32:
7369 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7370 cpu_gpr_d[r2], n, 32, env);
7371 break;
7372 case OPC2_32_RRR1_MADD_Q_64:
7373 CHECK_REG_PAIR(r4);
7374 CHECK_REG_PAIR(r3);
7375 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7376 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7377 n, env);
7378 break;
7379 case OPC2_32_RRR1_MADD_Q_32_L:
7380 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7381 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7382 temp, n, 16, env);
7383 break;
7384 case OPC2_32_RRR1_MADD_Q_64_L:
7385 CHECK_REG_PAIR(r4);
7386 CHECK_REG_PAIR(r3);
7387 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7388 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7389 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7390 n, env);
7391 break;
7392 case OPC2_32_RRR1_MADD_Q_32_U:
7393 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7394 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7395 temp, n, 16, env);
7396 break;
7397 case OPC2_32_RRR1_MADD_Q_64_U:
7398 CHECK_REG_PAIR(r4);
7399 CHECK_REG_PAIR(r3);
7400 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7401 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7402 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7403 n, env);
7404 break;
7405 case OPC2_32_RRR1_MADD_Q_32_LL:
7406 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7407 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7408 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7409 break;
7410 case OPC2_32_RRR1_MADD_Q_64_LL:
7411 CHECK_REG_PAIR(r4);
7412 CHECK_REG_PAIR(r3);
7413 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7414 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7415 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7416 cpu_gpr_d[r3+1], temp, temp2, n);
7417 break;
7418 case OPC2_32_RRR1_MADD_Q_32_UU:
7419 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7420 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7421 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7422 break;
7423 case OPC2_32_RRR1_MADD_Q_64_UU:
7424 CHECK_REG_PAIR(r4);
7425 CHECK_REG_PAIR(r3);
7426 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7427 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7428 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7429 cpu_gpr_d[r3+1], temp, temp2, n);
7430 break;
7431 case OPC2_32_RRR1_MADDS_Q_32:
7432 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7433 cpu_gpr_d[r2], n, 32);
7434 break;
7435 case OPC2_32_RRR1_MADDS_Q_64:
7436 CHECK_REG_PAIR(r4);
7437 CHECK_REG_PAIR(r3);
7438 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7439 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7440 n);
7441 break;
7442 case OPC2_32_RRR1_MADDS_Q_32_L:
7443 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7444 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7445 temp, n, 16);
7446 break;
7447 case OPC2_32_RRR1_MADDS_Q_64_L:
7448 CHECK_REG_PAIR(r4);
7449 CHECK_REG_PAIR(r3);
7450 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7451 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7452 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7453 n);
7454 break;
7455 case OPC2_32_RRR1_MADDS_Q_32_U:
7456 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7457 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7458 temp, n, 16);
7459 break;
7460 case OPC2_32_RRR1_MADDS_Q_64_U:
7461 CHECK_REG_PAIR(r4);
7462 CHECK_REG_PAIR(r3);
7463 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7464 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7465 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7466 n);
7467 break;
7468 case OPC2_32_RRR1_MADDS_Q_32_LL:
7469 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7470 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7471 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7472 break;
7473 case OPC2_32_RRR1_MADDS_Q_64_LL:
7474 CHECK_REG_PAIR(r4);
7475 CHECK_REG_PAIR(r3);
7476 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7477 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7478 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7479 cpu_gpr_d[r3+1], temp, temp2, n);
7480 break;
7481 case OPC2_32_RRR1_MADDS_Q_32_UU:
7482 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7483 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7484 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7485 break;
7486 case OPC2_32_RRR1_MADDS_Q_64_UU:
7487 CHECK_REG_PAIR(r4);
7488 CHECK_REG_PAIR(r3);
7489 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7490 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7491 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7492 cpu_gpr_d[r3+1], temp, temp2, n);
7493 break;
7494 case OPC2_32_RRR1_MADDR_H_64_UL:
7495 CHECK_REG_PAIR(r3);
7496 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7497 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7498 break;
7499 case OPC2_32_RRR1_MADDRS_H_64_UL:
7500 CHECK_REG_PAIR(r3);
7501 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7502 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7503 break;
7504 case OPC2_32_RRR1_MADDR_Q_32_LL:
7505 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7506 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7507 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7508 break;
7509 case OPC2_32_RRR1_MADDR_Q_32_UU:
7510 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7511 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7512 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7513 break;
7514 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7515 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7516 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7517 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7518 break;
7519 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7520 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7521 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7522 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7523 break;
7524 default:
7525 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7526 }
7527 tcg_temp_free(temp);
7528 tcg_temp_free(temp2);
7529 }
7530
7531 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
7532 {
7533 uint32_t op2;
7534 uint32_t r1, r2, r3, r4, n;
7535
7536 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7537 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7538 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7539 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7540 r4 = MASK_OP_RRR1_D(ctx->opcode);
7541 n = MASK_OP_RRR1_N(ctx->opcode);
7542
7543 switch (op2) {
7544 case OPC2_32_RRR1_MADDSU_H_32_LL:
7545 CHECK_REG_PAIR(r4);
7546 CHECK_REG_PAIR(r3);
7547 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7548 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7549 break;
7550 case OPC2_32_RRR1_MADDSU_H_32_LU:
7551 CHECK_REG_PAIR(r4);
7552 CHECK_REG_PAIR(r3);
7553 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7554 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7555 break;
7556 case OPC2_32_RRR1_MADDSU_H_32_UL:
7557 CHECK_REG_PAIR(r4);
7558 CHECK_REG_PAIR(r3);
7559 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7560 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7561 break;
7562 case OPC2_32_RRR1_MADDSU_H_32_UU:
7563 CHECK_REG_PAIR(r4);
7564 CHECK_REG_PAIR(r3);
7565 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7566 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7567 break;
7568 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7569 CHECK_REG_PAIR(r4);
7570 CHECK_REG_PAIR(r3);
7571 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7572 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7573 n, MODE_LL);
7574 break;
7575 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7576 CHECK_REG_PAIR(r4);
7577 CHECK_REG_PAIR(r3);
7578 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7579 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7580 n, MODE_LU);
7581 break;
7582 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7583 CHECK_REG_PAIR(r4);
7584 CHECK_REG_PAIR(r3);
7585 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7586 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7587 n, MODE_UL);
7588 break;
7589 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7590 CHECK_REG_PAIR(r4);
7591 CHECK_REG_PAIR(r3);
7592 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7593 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7594 n, MODE_UU);
7595 break;
7596 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7597 CHECK_REG_PAIR(r4);
7598 CHECK_REG_PAIR(r3);
7599 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7600 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7601 n, MODE_LL);
7602 break;
7603 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7604 CHECK_REG_PAIR(r4);
7605 CHECK_REG_PAIR(r3);
7606 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7607 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7608 n, MODE_LU);
7609 break;
7610 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7611 CHECK_REG_PAIR(r4);
7612 CHECK_REG_PAIR(r3);
7613 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7614 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7615 n, MODE_UL);
7616 break;
7617 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7618 CHECK_REG_PAIR(r4);
7619 CHECK_REG_PAIR(r3);
7620 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7621 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7622 n, MODE_UU);
7623 break;
7624 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7625 CHECK_REG_PAIR(r4);
7626 CHECK_REG_PAIR(r3);
7627 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7628 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7629 n, MODE_LL);
7630 break;
7631 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7632 CHECK_REG_PAIR(r4);
7633 CHECK_REG_PAIR(r3);
7634 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7635 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7636 n, MODE_LU);
7637 break;
7638 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7639 CHECK_REG_PAIR(r4);
7640 CHECK_REG_PAIR(r3);
7641 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7642 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7643 n, MODE_UL);
7644 break;
7645 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7646 CHECK_REG_PAIR(r4);
7647 CHECK_REG_PAIR(r3);
7648 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7649 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7650 n, MODE_UU);
7651 break;
7652 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7653 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7654 cpu_gpr_d[r2], n, MODE_LL);
7655 break;
7656 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7657 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7658 cpu_gpr_d[r2], n, MODE_LU);
7659 break;
7660 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7661 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7662 cpu_gpr_d[r2], n, MODE_UL);
7663 break;
7664 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7665 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7666 cpu_gpr_d[r2], n, MODE_UU);
7667 break;
7668 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7669 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7670 cpu_gpr_d[r2], n, MODE_LL);
7671 break;
7672 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7673 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7674 cpu_gpr_d[r2], n, MODE_LU);
7675 break;
7676 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7677 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7678 cpu_gpr_d[r2], n, MODE_UL);
7679 break;
7680 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7681 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7682 cpu_gpr_d[r2], n, MODE_UU);
7683 break;
7684 default:
7685 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7686 }
7687 }
7688
7689 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
7690 {
7691 uint32_t op2;
7692 uint32_t r1, r2, r3, r4, n;
7693
7694 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7695 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7696 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7697 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7698 r4 = MASK_OP_RRR1_D(ctx->opcode);
7699 n = MASK_OP_RRR1_N(ctx->opcode);
7700
7701 switch (op2) {
7702 case OPC2_32_RRR1_MSUB_H_LL:
7703 CHECK_REG_PAIR(r4);
7704 CHECK_REG_PAIR(r3);
7705 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7706 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7707 break;
7708 case OPC2_32_RRR1_MSUB_H_LU:
7709 CHECK_REG_PAIR(r4);
7710 CHECK_REG_PAIR(r3);
7711 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7712 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7713 break;
7714 case OPC2_32_RRR1_MSUB_H_UL:
7715 CHECK_REG_PAIR(r4);
7716 CHECK_REG_PAIR(r3);
7717 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7718 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7719 break;
7720 case OPC2_32_RRR1_MSUB_H_UU:
7721 CHECK_REG_PAIR(r4);
7722 CHECK_REG_PAIR(r3);
7723 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7724 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7725 break;
7726 case OPC2_32_RRR1_MSUBS_H_LL:
7727 CHECK_REG_PAIR(r4);
7728 CHECK_REG_PAIR(r3);
7729 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7730 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7731 break;
7732 case OPC2_32_RRR1_MSUBS_H_LU:
7733 CHECK_REG_PAIR(r4);
7734 CHECK_REG_PAIR(r3);
7735 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7736 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7737 break;
7738 case OPC2_32_RRR1_MSUBS_H_UL:
7739 CHECK_REG_PAIR(r4);
7740 CHECK_REG_PAIR(r3);
7741 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7742 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7743 break;
7744 case OPC2_32_RRR1_MSUBS_H_UU:
7745 CHECK_REG_PAIR(r4);
7746 CHECK_REG_PAIR(r3);
7747 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7748 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7749 break;
7750 case OPC2_32_RRR1_MSUBM_H_LL:
7751 CHECK_REG_PAIR(r4);
7752 CHECK_REG_PAIR(r3);
7753 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7754 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7755 break;
7756 case OPC2_32_RRR1_MSUBM_H_LU:
7757 CHECK_REG_PAIR(r4);
7758 CHECK_REG_PAIR(r3);
7759 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7760 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7761 break;
7762 case OPC2_32_RRR1_MSUBM_H_UL:
7763 CHECK_REG_PAIR(r4);
7764 CHECK_REG_PAIR(r3);
7765 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7766 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7767 break;
7768 case OPC2_32_RRR1_MSUBM_H_UU:
7769 CHECK_REG_PAIR(r4);
7770 CHECK_REG_PAIR(r3);
7771 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7772 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7773 break;
7774 case OPC2_32_RRR1_MSUBMS_H_LL:
7775 CHECK_REG_PAIR(r4);
7776 CHECK_REG_PAIR(r3);
7777 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7778 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7779 break;
7780 case OPC2_32_RRR1_MSUBMS_H_LU:
7781 CHECK_REG_PAIR(r4);
7782 CHECK_REG_PAIR(r3);
7783 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7784 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7785 break;
7786 case OPC2_32_RRR1_MSUBMS_H_UL:
7787 CHECK_REG_PAIR(r4);
7788 CHECK_REG_PAIR(r3);
7789 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7790 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7791 break;
7792 case OPC2_32_RRR1_MSUBMS_H_UU:
7793 CHECK_REG_PAIR(r4);
7794 CHECK_REG_PAIR(r3);
7795 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7796 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7797 break;
7798 case OPC2_32_RRR1_MSUBR_H_LL:
7799 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7800 cpu_gpr_d[r2], n, MODE_LL);
7801 break;
7802 case OPC2_32_RRR1_MSUBR_H_LU:
7803 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7804 cpu_gpr_d[r2], n, MODE_LU);
7805 break;
7806 case OPC2_32_RRR1_MSUBR_H_UL:
7807 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7808 cpu_gpr_d[r2], n, MODE_UL);
7809 break;
7810 case OPC2_32_RRR1_MSUBR_H_UU:
7811 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7812 cpu_gpr_d[r2], n, MODE_UU);
7813 break;
7814 case OPC2_32_RRR1_MSUBRS_H_LL:
7815 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7816 cpu_gpr_d[r2], n, MODE_LL);
7817 break;
7818 case OPC2_32_RRR1_MSUBRS_H_LU:
7819 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7820 cpu_gpr_d[r2], n, MODE_LU);
7821 break;
7822 case OPC2_32_RRR1_MSUBRS_H_UL:
7823 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7824 cpu_gpr_d[r2], n, MODE_UL);
7825 break;
7826 case OPC2_32_RRR1_MSUBRS_H_UU:
7827 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7828 cpu_gpr_d[r2], n, MODE_UU);
7829 break;
7830 default:
7831 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7832 }
7833 }
7834
7835 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
7836 {
7837 uint32_t op2;
7838 uint32_t r1, r2, r3, r4, n;
7839 TCGv temp, temp2;
7840
7841 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7842 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7843 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7844 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7845 r4 = MASK_OP_RRR1_D(ctx->opcode);
7846 n = MASK_OP_RRR1_N(ctx->opcode);
7847
7848 temp = tcg_const_i32(n);
7849 temp2 = tcg_temp_new();
7850
7851 switch (op2) {
7852 case OPC2_32_RRR1_MSUB_Q_32:
7853 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7854 cpu_gpr_d[r2], n, 32, env);
7855 break;
7856 case OPC2_32_RRR1_MSUB_Q_64:
7857 CHECK_REG_PAIR(r4);
7858 CHECK_REG_PAIR(r3);
7859 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7860 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7861 n, env);
7862 break;
7863 case OPC2_32_RRR1_MSUB_Q_32_L:
7864 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7865 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7866 temp, n, 16, env);
7867 break;
7868 case OPC2_32_RRR1_MSUB_Q_64_L:
7869 CHECK_REG_PAIR(r4);
7870 CHECK_REG_PAIR(r3);
7871 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7872 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7873 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7874 n, env);
7875 break;
7876 case OPC2_32_RRR1_MSUB_Q_32_U:
7877 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7878 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7879 temp, n, 16, env);
7880 break;
7881 case OPC2_32_RRR1_MSUB_Q_64_U:
7882 CHECK_REG_PAIR(r4);
7883 CHECK_REG_PAIR(r3);
7884 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7885 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7886 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7887 n, env);
7888 break;
7889 case OPC2_32_RRR1_MSUB_Q_32_LL:
7890 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7891 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7892 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7893 break;
7894 case OPC2_32_RRR1_MSUB_Q_64_LL:
7895 CHECK_REG_PAIR(r4);
7896 CHECK_REG_PAIR(r3);
7897 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7898 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7899 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7900 cpu_gpr_d[r3+1], temp, temp2, n);
7901 break;
7902 case OPC2_32_RRR1_MSUB_Q_32_UU:
7903 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7904 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7905 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7906 break;
7907 case OPC2_32_RRR1_MSUB_Q_64_UU:
7908 CHECK_REG_PAIR(r4);
7909 CHECK_REG_PAIR(r3);
7910 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7911 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7912 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7913 cpu_gpr_d[r3+1], temp, temp2, n);
7914 break;
7915 case OPC2_32_RRR1_MSUBS_Q_32:
7916 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7917 cpu_gpr_d[r2], n, 32);
7918 break;
7919 case OPC2_32_RRR1_MSUBS_Q_64:
7920 CHECK_REG_PAIR(r4);
7921 CHECK_REG_PAIR(r3);
7922 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7923 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7924 n);
7925 break;
7926 case OPC2_32_RRR1_MSUBS_Q_32_L:
7927 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7928 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7929 temp, n, 16);
7930 break;
7931 case OPC2_32_RRR1_MSUBS_Q_64_L:
7932 CHECK_REG_PAIR(r4);
7933 CHECK_REG_PAIR(r3);
7934 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7935 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7936 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7937 n);
7938 break;
7939 case OPC2_32_RRR1_MSUBS_Q_32_U:
7940 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7941 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7942 temp, n, 16);
7943 break;
7944 case OPC2_32_RRR1_MSUBS_Q_64_U:
7945 CHECK_REG_PAIR(r4);
7946 CHECK_REG_PAIR(r3);
7947 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7948 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7949 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7950 n);
7951 break;
7952 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7953 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7954 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7955 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7956 break;
7957 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7958 CHECK_REG_PAIR(r4);
7959 CHECK_REG_PAIR(r3);
7960 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7961 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7962 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7963 cpu_gpr_d[r3+1], temp, temp2, n);
7964 break;
7965 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7966 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7967 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7968 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7969 break;
7970 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7971 CHECK_REG_PAIR(r4);
7972 CHECK_REG_PAIR(r3);
7973 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7974 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7975 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7976 cpu_gpr_d[r3+1], temp, temp2, n);
7977 break;
7978 case OPC2_32_RRR1_MSUBR_H_64_UL:
7979 CHECK_REG_PAIR(r3);
7980 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7981 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7982 break;
7983 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7984 CHECK_REG_PAIR(r3);
7985 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7986 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7987 break;
7988 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7989 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7990 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7991 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7992 break;
7993 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7994 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7995 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7996 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7997 break;
7998 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7999 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
8000 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
8001 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
8002 break;
8003 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
8004 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
8005 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
8006 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
8007 break;
8008 default:
8009 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8010 }
8011 tcg_temp_free(temp);
8012 tcg_temp_free(temp2);
8013 }
8014
8015 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
8016 {
8017 uint32_t op2;
8018 uint32_t r1, r2, r3, r4, n;
8019
8020 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
8021 r1 = MASK_OP_RRR1_S1(ctx->opcode);
8022 r2 = MASK_OP_RRR1_S2(ctx->opcode);
8023 r3 = MASK_OP_RRR1_S3(ctx->opcode);
8024 r4 = MASK_OP_RRR1_D(ctx->opcode);
8025 n = MASK_OP_RRR1_N(ctx->opcode);
8026
8027 switch (op2) {
8028 case OPC2_32_RRR1_MSUBAD_H_32_LL:
8029 CHECK_REG_PAIR(r4);
8030 CHECK_REG_PAIR(r3);
8031 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8032 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
8033 break;
8034 case OPC2_32_RRR1_MSUBAD_H_32_LU:
8035 CHECK_REG_PAIR(r4);
8036 CHECK_REG_PAIR(r3);
8037 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8038 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
8039 break;
8040 case OPC2_32_RRR1_MSUBAD_H_32_UL:
8041 CHECK_REG_PAIR(r4);
8042 CHECK_REG_PAIR(r3);
8043 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8044 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
8045 break;
8046 case OPC2_32_RRR1_MSUBAD_H_32_UU:
8047 CHECK_REG_PAIR(r4);
8048 CHECK_REG_PAIR(r3);
8049 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8050 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
8051 break;
8052 case OPC2_32_RRR1_MSUBADS_H_32_LL:
8053 CHECK_REG_PAIR(r4);
8054 CHECK_REG_PAIR(r3);
8055 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8056 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8057 n, MODE_LL);
8058 break;
8059 case OPC2_32_RRR1_MSUBADS_H_32_LU:
8060 CHECK_REG_PAIR(r4);
8061 CHECK_REG_PAIR(r3);
8062 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8063 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8064 n, MODE_LU);
8065 break;
8066 case OPC2_32_RRR1_MSUBADS_H_32_UL:
8067 CHECK_REG_PAIR(r4);
8068 CHECK_REG_PAIR(r3);
8069 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8070 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8071 n, MODE_UL);
8072 break;
8073 case OPC2_32_RRR1_MSUBADS_H_32_UU:
8074 CHECK_REG_PAIR(r4);
8075 CHECK_REG_PAIR(r3);
8076 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8077 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8078 n, MODE_UU);
8079 break;
8080 case OPC2_32_RRR1_MSUBADM_H_64_LL:
8081 CHECK_REG_PAIR(r4);
8082 CHECK_REG_PAIR(r3);
8083 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8084 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8085 n, MODE_LL);
8086 break;
8087 case OPC2_32_RRR1_MSUBADM_H_64_LU:
8088 CHECK_REG_PAIR(r4);
8089 CHECK_REG_PAIR(r3);
8090 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8091 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8092 n, MODE_LU);
8093 break;
8094 case OPC2_32_RRR1_MSUBADM_H_64_UL:
8095 CHECK_REG_PAIR(r4);
8096 CHECK_REG_PAIR(r3);
8097 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8098 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8099 n, MODE_UL);
8100 break;
8101 case OPC2_32_RRR1_MSUBADM_H_64_UU:
8102 CHECK_REG_PAIR(r4);
8103 CHECK_REG_PAIR(r3);
8104 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8105 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8106 n, MODE_UU);
8107 break;
8108 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
8109 CHECK_REG_PAIR(r4);
8110 CHECK_REG_PAIR(r3);
8111 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8112 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8113 n, MODE_LL);
8114 break;
8115 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
8116 CHECK_REG_PAIR(r4);
8117 CHECK_REG_PAIR(r3);
8118 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8119 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8120 n, MODE_LU);
8121 break;
8122 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
8123 CHECK_REG_PAIR(r4);
8124 CHECK_REG_PAIR(r3);
8125 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8126 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8127 n, MODE_UL);
8128 break;
8129 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
8130 CHECK_REG_PAIR(r4);
8131 CHECK_REG_PAIR(r3);
8132 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8133 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8134 n, MODE_UU);
8135 break;
8136 case OPC2_32_RRR1_MSUBADR_H_16_LL:
8137 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8138 cpu_gpr_d[r2], n, MODE_LL);
8139 break;
8140 case OPC2_32_RRR1_MSUBADR_H_16_LU:
8141 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8142 cpu_gpr_d[r2], n, MODE_LU);
8143 break;
8144 case OPC2_32_RRR1_MSUBADR_H_16_UL:
8145 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8146 cpu_gpr_d[r2], n, MODE_UL);
8147 break;
8148 case OPC2_32_RRR1_MSUBADR_H_16_UU:
8149 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8150 cpu_gpr_d[r2], n, MODE_UU);
8151 break;
8152 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
8153 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8154 cpu_gpr_d[r2], n, MODE_LL);
8155 break;
8156 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
8157 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8158 cpu_gpr_d[r2], n, MODE_LU);
8159 break;
8160 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
8161 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8162 cpu_gpr_d[r2], n, MODE_UL);
8163 break;
8164 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
8165 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8166 cpu_gpr_d[r2], n, MODE_UU);
8167 break;
8168 default:
8169 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8170 }
8171 }
8172
8173 /* RRRR format */
8174 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
8175 {
8176 uint32_t op2;
8177 int r1, r2, r3, r4;
8178 TCGv tmp_width, tmp_pos;
8179
8180 r1 = MASK_OP_RRRR_S1(ctx->opcode);
8181 r2 = MASK_OP_RRRR_S2(ctx->opcode);
8182 r3 = MASK_OP_RRRR_S3(ctx->opcode);
8183 r4 = MASK_OP_RRRR_D(ctx->opcode);
8184 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
8185
8186 tmp_pos = tcg_temp_new();
8187 tmp_width = tcg_temp_new();
8188
8189 switch (op2) {
8190 case OPC2_32_RRRR_DEXTR:
8191 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
8192 if (r1 == r2) {
8193 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
8194 } else {
8195 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
8196 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
8197 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
8198 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
8199 }
8200 break;
8201 case OPC2_32_RRRR_EXTR:
8202 case OPC2_32_RRRR_EXTR_U:
8203 CHECK_REG_PAIR(r3);
8204 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
8205 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
8206 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
8207 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
8208 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
8209 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
8210 if (op2 == OPC2_32_RRRR_EXTR) {
8211 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
8212 } else {
8213 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
8214 }
8215 break;
8216 case OPC2_32_RRRR_INSERT:
8217 CHECK_REG_PAIR(r3);
8218 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
8219 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
8220 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
8221 tmp_pos);
8222 break;
8223 default:
8224 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8225 }
8226 tcg_temp_free(tmp_pos);
8227 tcg_temp_free(tmp_width);
8228 }
8229
8230 /* RRRW format */
8231 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
8232 {
8233 uint32_t op2;
8234 int r1, r2, r3, r4;
8235 int32_t width;
8236
8237 TCGv temp, temp2;
8238
8239 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
8240 r1 = MASK_OP_RRRW_S1(ctx->opcode);
8241 r2 = MASK_OP_RRRW_S2(ctx->opcode);
8242 r3 = MASK_OP_RRRW_S3(ctx->opcode);
8243 r4 = MASK_OP_RRRW_D(ctx->opcode);
8244 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
8245
8246 temp = tcg_temp_new();
8247
8248 switch (op2) {
8249 case OPC2_32_RRRW_EXTR:
8250 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
8251 tcg_gen_addi_tl(temp, temp, width);
8252 tcg_gen_subfi_tl(temp, 32, temp);
8253 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
8254 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
8255 break;
8256 case OPC2_32_RRRW_EXTR_U:
8257 if (width == 0) {
8258 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
8259 } else {
8260 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
8261 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
8262 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
8263 }
8264 break;
8265 case OPC2_32_RRRW_IMASK:
8266 temp2 = tcg_temp_new();
8267
8268 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
8269 tcg_gen_movi_tl(temp2, (1 << width) - 1);
8270 tcg_gen_shl_tl(temp2, temp2, temp);
8271 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
8272 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
8273
8274 tcg_temp_free(temp2);
8275 break;
8276 case OPC2_32_RRRW_INSERT:
8277 temp2 = tcg_temp_new();
8278
8279 tcg_gen_movi_tl(temp, width);
8280 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
8281 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
8282
8283 tcg_temp_free(temp2);
8284 break;
8285 default:
8286 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8287 }
8288 tcg_temp_free(temp);
8289 }
8290
8291 /* SYS Format*/
8292 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
8293 {
8294 uint32_t op2;
8295 uint32_t r1;
8296 TCGLabel *l1;
8297 TCGv tmp;
8298
8299 op2 = MASK_OP_SYS_OP2(ctx->opcode);
8300 r1 = MASK_OP_SYS_S1D(ctx->opcode);
8301
8302 switch (op2) {
8303 case OPC2_32_SYS_DEBUG:
8304 /* raise EXCP_DEBUG */
8305 break;
8306 case OPC2_32_SYS_DISABLE:
8307 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
8308 break;
8309 case OPC2_32_SYS_DSYNC:
8310 break;
8311 case OPC2_32_SYS_ENABLE:
8312 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
8313 break;
8314 case OPC2_32_SYS_ISYNC:
8315 break;
8316 case OPC2_32_SYS_NOP:
8317 break;
8318 case OPC2_32_SYS_RET:
8319 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
8320 break;
8321 case OPC2_32_SYS_FRET:
8322 gen_fret(ctx);
8323 break;
8324 case OPC2_32_SYS_RFE:
8325 gen_helper_rfe(cpu_env);
8326 tcg_gen_exit_tb(0);
8327 ctx->bstate = BS_BRANCH;
8328 break;
8329 case OPC2_32_SYS_RFM:
8330 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
8331 tmp = tcg_temp_new();
8332 l1 = gen_new_label();
8333
8334 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
8335 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
8336 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
8337 gen_helper_rfm(cpu_env);
8338 gen_set_label(l1);
8339 tcg_gen_exit_tb(0);
8340 ctx->bstate = BS_BRANCH;
8341 tcg_temp_free(tmp);
8342 } else {
8343 /* generate privilege trap */
8344 }
8345 break;
8346 case OPC2_32_SYS_RSLCX:
8347 gen_helper_rslcx(cpu_env);
8348 break;
8349 case OPC2_32_SYS_SVLCX:
8350 gen_helper_svlcx(cpu_env);
8351 break;
8352 case OPC2_32_SYS_RESTORE:
8353 if (tricore_feature(env, TRICORE_FEATURE_16)) {
8354 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
8355 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
8356 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
8357 } /* else raise privilege trap */
8358 } else {
8359 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8360 }
8361 break;
8362 case OPC2_32_SYS_TRAPSV:
8363 l1 = gen_new_label();
8364 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
8365 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
8366 gen_set_label(l1);
8367 break;
8368 case OPC2_32_SYS_TRAPV:
8369 l1 = gen_new_label();
8370 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
8371 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
8372 gen_set_label(l1);
8373 break;
8374 default:
8375 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8376 }
8377 }
8378
8379 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
8380 {
8381 int op1;
8382 int32_t r1, r2, r3;
8383 int32_t address, const16;
8384 int8_t b, const4;
8385 int32_t bpos;
8386 TCGv temp, temp2, temp3;
8387
8388 op1 = MASK_OP_MAJOR(ctx->opcode);
8389
8390 /* handle JNZ.T opcode only being 7 bit long */
8391 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
8392 op1 = OPCM_32_BRN_JTT;
8393 }
8394
8395 switch (op1) {
8396 /* ABS-format */
8397 case OPCM_32_ABS_LDW:
8398 decode_abs_ldw(env, ctx);
8399 break;
8400 case OPCM_32_ABS_LDB:
8401 decode_abs_ldb(env, ctx);
8402 break;
8403 case OPCM_32_ABS_LDMST_SWAP:
8404 decode_abs_ldst_swap(env, ctx);
8405 break;
8406 case OPCM_32_ABS_LDST_CONTEXT:
8407 decode_abs_ldst_context(env, ctx);
8408 break;
8409 case OPCM_32_ABS_STORE:
8410 decode_abs_store(env, ctx);
8411 break;
8412 case OPCM_32_ABS_STOREB_H:
8413 decode_abs_storeb_h(env, ctx);
8414 break;
8415 case OPC1_32_ABS_STOREQ:
8416 address = MASK_OP_ABS_OFF18(ctx->opcode);
8417 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8418 temp = tcg_const_i32(EA_ABS_FORMAT(address));
8419 temp2 = tcg_temp_new();
8420
8421 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
8422 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
8423
8424 tcg_temp_free(temp2);
8425 tcg_temp_free(temp);
8426 break;
8427 case OPC1_32_ABS_LD_Q:
8428 address = MASK_OP_ABS_OFF18(ctx->opcode);
8429 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8430 temp = tcg_const_i32(EA_ABS_FORMAT(address));
8431
8432 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
8433 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
8434
8435 tcg_temp_free(temp);
8436 break;
8437 case OPC1_32_ABS_LEA:
8438 address = MASK_OP_ABS_OFF18(ctx->opcode);
8439 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8440 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
8441 break;
8442 /* ABSB-format */
8443 case OPC1_32_ABSB_ST_T:
8444 address = MASK_OP_ABS_OFF18(ctx->opcode);
8445 b = MASK_OP_ABSB_B(ctx->opcode);
8446 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
8447
8448 temp = tcg_const_i32(EA_ABS_FORMAT(address));
8449 temp2 = tcg_temp_new();
8450
8451 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
8452 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
8453 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
8454 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
8455
8456 tcg_temp_free(temp);
8457 tcg_temp_free(temp2);
8458 break;
8459 /* B-format */
8460 case OPC1_32_B_CALL:
8461 case OPC1_32_B_CALLA:
8462 case OPC1_32_B_FCALL:
8463 case OPC1_32_B_FCALLA:
8464 case OPC1_32_B_J:
8465 case OPC1_32_B_JA:
8466 case OPC1_32_B_JL:
8467 case OPC1_32_B_JLA:
8468 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8469 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8470 break;
8471 /* Bit-format */
8472 case OPCM_32_BIT_ANDACC:
8473 decode_bit_andacc(env, ctx);
8474 break;
8475 case OPCM_32_BIT_LOGICAL_T1:
8476 decode_bit_logical_t(env, ctx);
8477 break;
8478 case OPCM_32_BIT_INSERT:
8479 decode_bit_insert(env, ctx);
8480 break;
8481 case OPCM_32_BIT_LOGICAL_T2:
8482 decode_bit_logical_t2(env, ctx);
8483 break;
8484 case OPCM_32_BIT_ORAND:
8485 decode_bit_orand(env, ctx);
8486 break;
8487 case OPCM_32_BIT_SH_LOGIC1:
8488 decode_bit_sh_logic1(env, ctx);
8489 break;
8490 case OPCM_32_BIT_SH_LOGIC2:
8491 decode_bit_sh_logic2(env, ctx);
8492 break;
8493 /* BO Format */
8494 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8495 decode_bo_addrmode_post_pre_base(env, ctx);
8496 break;
8497 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8498 decode_bo_addrmode_bitreverse_circular(env, ctx);
8499 break;
8500 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8501 decode_bo_addrmode_ld_post_pre_base(env, ctx);
8502 break;
8503 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8504 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
8505 break;
8506 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8507 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
8508 break;
8509 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8510 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
8511 break;
8512 /* BOL-format */
8513 case OPC1_32_BOL_LD_A_LONGOFF:
8514 case OPC1_32_BOL_LD_W_LONGOFF:
8515 case OPC1_32_BOL_LEA_LONGOFF:
8516 case OPC1_32_BOL_ST_W_LONGOFF:
8517 case OPC1_32_BOL_ST_A_LONGOFF:
8518 case OPC1_32_BOL_LD_B_LONGOFF:
8519 case OPC1_32_BOL_LD_BU_LONGOFF:
8520 case OPC1_32_BOL_LD_H_LONGOFF:
8521 case OPC1_32_BOL_LD_HU_LONGOFF:
8522 case OPC1_32_BOL_ST_B_LONGOFF:
8523 case OPC1_32_BOL_ST_H_LONGOFF:
8524 decode_bol_opc(env, ctx, op1);
8525 break;
8526 /* BRC Format */
8527 case OPCM_32_BRC_EQ_NEQ:
8528 case OPCM_32_BRC_GE:
8529 case OPCM_32_BRC_JLT:
8530 case OPCM_32_BRC_JNE:
8531 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8532 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8533 r1 = MASK_OP_BRC_S1(ctx->opcode);
8534 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8535 break;
8536 /* BRN Format */
8537 case OPCM_32_BRN_JTT:
8538 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8539 r1 = MASK_OP_BRN_S1(ctx->opcode);
8540 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8541 break;
8542 /* BRR Format */
8543 case OPCM_32_BRR_EQ_NEQ:
8544 case OPCM_32_BRR_ADDR_EQ_NEQ:
8545 case OPCM_32_BRR_GE:
8546 case OPCM_32_BRR_JLT:
8547 case OPCM_32_BRR_JNE:
8548 case OPCM_32_BRR_JNZ:
8549 case OPCM_32_BRR_LOOP:
8550 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8551 r2 = MASK_OP_BRR_S2(ctx->opcode);
8552 r1 = MASK_OP_BRR_S1(ctx->opcode);
8553 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8554 break;
8555 /* RC Format */
8556 case OPCM_32_RC_LOGICAL_SHIFT:
8557 decode_rc_logical_shift(env, ctx);
8558 break;
8559 case OPCM_32_RC_ACCUMULATOR:
8560 decode_rc_accumulator(env, ctx);
8561 break;
8562 case OPCM_32_RC_SERVICEROUTINE:
8563 decode_rc_serviceroutine(env, ctx);
8564 break;
8565 case OPCM_32_RC_MUL:
8566 decode_rc_mul(env, ctx);
8567 break;
8568 /* RCPW Format */
8569 case OPCM_32_RCPW_MASK_INSERT:
8570 decode_rcpw_insert(env, ctx);
8571 break;
8572 /* RCRR Format */
8573 case OPC1_32_RCRR_INSERT:
8574 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8575 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8576 r3 = MASK_OP_RCRR_D(ctx->opcode);
8577 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8578 temp = tcg_const_i32(const16);
8579 temp2 = tcg_temp_new(); /* width*/
8580 temp3 = tcg_temp_new(); /* pos */
8581
8582 CHECK_REG_PAIR(r3);
8583
8584 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8585 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8586
8587 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8588
8589 tcg_temp_free(temp);
8590 tcg_temp_free(temp2);
8591 tcg_temp_free(temp3);
8592 break;
8593 /* RCRW Format */
8594 case OPCM_32_RCRW_MASK_INSERT:
8595 decode_rcrw_insert(env, ctx);
8596 break;
8597 /* RCR Format */
8598 case OPCM_32_RCR_COND_SELECT:
8599 decode_rcr_cond_select(env, ctx);
8600 break;
8601 case OPCM_32_RCR_MADD:
8602 decode_rcr_madd(env, ctx);
8603 break;
8604 case OPCM_32_RCR_MSUB:
8605 decode_rcr_msub(env, ctx);
8606 break;
8607 /* RLC Format */
8608 case OPC1_32_RLC_ADDI:
8609 case OPC1_32_RLC_ADDIH:
8610 case OPC1_32_RLC_ADDIH_A:
8611 case OPC1_32_RLC_MFCR:
8612 case OPC1_32_RLC_MOV:
8613 case OPC1_32_RLC_MOV_64:
8614 case OPC1_32_RLC_MOV_U:
8615 case OPC1_32_RLC_MOV_H:
8616 case OPC1_32_RLC_MOVH_A:
8617 case OPC1_32_RLC_MTCR:
8618 decode_rlc_opc(env, ctx, op1);
8619 break;
8620 /* RR Format */
8621 case OPCM_32_RR_ACCUMULATOR:
8622 decode_rr_accumulator(env, ctx);
8623 break;
8624 case OPCM_32_RR_LOGICAL_SHIFT:
8625 decode_rr_logical_shift(env, ctx);
8626 break;
8627 case OPCM_32_RR_ADDRESS:
8628 decode_rr_address(env, ctx);
8629 break;
8630 case OPCM_32_RR_IDIRECT:
8631 decode_rr_idirect(env, ctx);
8632 break;
8633 case OPCM_32_RR_DIVIDE:
8634 decode_rr_divide(env, ctx);
8635 break;
8636 /* RR1 Format */
8637 case OPCM_32_RR1_MUL:
8638 decode_rr1_mul(env, ctx);
8639 break;
8640 case OPCM_32_RR1_MULQ:
8641 decode_rr1_mulq(env, ctx);
8642 break;
8643 /* RR2 format */
8644 case OPCM_32_RR2_MUL:
8645 decode_rr2_mul(env, ctx);
8646 break;
8647 /* RRPW format */
8648 case OPCM_32_RRPW_EXTRACT_INSERT:
8649 decode_rrpw_extract_insert(env, ctx);
8650 break;
8651 case OPC1_32_RRPW_DEXTR:
8652 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8653 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8654 r3 = MASK_OP_RRPW_D(ctx->opcode);
8655 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8656 if (r1 == r2) {
8657 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
8658 } else {
8659 temp = tcg_temp_new();
8660 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
8661 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
8662 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
8663 tcg_temp_free(temp);
8664 }
8665 break;
8666 /* RRR Format */
8667 case OPCM_32_RRR_COND_SELECT:
8668 decode_rrr_cond_select(env, ctx);
8669 break;
8670 case OPCM_32_RRR_DIVIDE:
8671 decode_rrr_divide(env, ctx);
8672 break;
8673 /* RRR2 Format */
8674 case OPCM_32_RRR2_MADD:
8675 decode_rrr2_madd(env, ctx);
8676 break;
8677 case OPCM_32_RRR2_MSUB:
8678 decode_rrr2_msub(env, ctx);
8679 break;
8680 /* RRR1 format */
8681 case OPCM_32_RRR1_MADD:
8682 decode_rrr1_madd(env, ctx);
8683 break;
8684 case OPCM_32_RRR1_MADDQ_H:
8685 decode_rrr1_maddq_h(env, ctx);
8686 break;
8687 case OPCM_32_RRR1_MADDSU_H:
8688 decode_rrr1_maddsu_h(env, ctx);
8689 break;
8690 case OPCM_32_RRR1_MSUB_H:
8691 decode_rrr1_msub(env, ctx);
8692 break;
8693 case OPCM_32_RRR1_MSUB_Q:
8694 decode_rrr1_msubq_h(env, ctx);
8695 break;
8696 case OPCM_32_RRR1_MSUBAD_H:
8697 decode_rrr1_msubad_h(env, ctx);
8698 break;
8699 /* RRRR format */
8700 case OPCM_32_RRRR_EXTRACT_INSERT:
8701 decode_rrrr_extract_insert(env, ctx);
8702 break;
8703 /* RRRW format */
8704 case OPCM_32_RRRW_EXTRACT_INSERT:
8705 decode_rrrw_extract_insert(env, ctx);
8706 break;
8707 /* SYS format */
8708 case OPCM_32_SYS_INTERRUPTS:
8709 decode_sys_interrupts(env, ctx);
8710 break;
8711 case OPC1_32_SYS_RSTV:
8712 tcg_gen_movi_tl(cpu_PSW_V, 0);
8713 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8714 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8715 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8716 break;
8717 default:
8718 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8719 }
8720 }
8721
8722 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
8723 {
8724 /* 16-Bit Instruction */
8725 if ((ctx->opcode & 0x1) == 0) {
8726 ctx->next_pc = ctx->pc + 2;
8727 decode_16Bit_opc(env, ctx);
8728 /* 32-Bit Instruction */
8729 } else {
8730 ctx->next_pc = ctx->pc + 4;
8731 decode_32Bit_opc(env, ctx);
8732 }
8733 }
8734
8735 void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
8736 {
8737 TriCoreCPU *cpu = tricore_env_get_cpu(env);
8738 CPUState *cs = CPU(cpu);
8739 DisasContext ctx;
8740 target_ulong pc_start;
8741 int num_insns, max_insns;
8742
8743 num_insns = 0;
8744 max_insns = tb->cflags & CF_COUNT_MASK;
8745 if (max_insns == 0) {
8746 max_insns = CF_COUNT_MASK;
8747 }
8748 if (singlestep) {
8749 max_insns = 1;
8750 }
8751 if (max_insns > TCG_MAX_INSNS) {
8752 max_insns = TCG_MAX_INSNS;
8753 }
8754
8755 pc_start = tb->pc;
8756 ctx.pc = pc_start;
8757 ctx.saved_pc = -1;
8758 ctx.tb = tb;
8759 ctx.singlestep_enabled = cs->singlestep_enabled;
8760 ctx.bstate = BS_NONE;
8761 ctx.mem_idx = cpu_mmu_index(env, false);
8762
8763 tcg_clear_temp_count();
8764 gen_tb_start(tb);
8765 while (ctx.bstate == BS_NONE) {
8766 tcg_gen_insn_start(ctx.pc);
8767 num_insns++;
8768
8769 ctx.opcode = cpu_ldl_code(env, ctx.pc);
8770 decode_opc(env, &ctx, 0);
8771
8772 if (num_insns >= max_insns || tcg_op_buf_full()) {
8773 gen_save_pc(ctx.next_pc);
8774 tcg_gen_exit_tb(0);
8775 break;
8776 }
8777 ctx.pc = ctx.next_pc;
8778 }
8779
8780 gen_tb_end(tb, num_insns);
8781 tb->size = ctx.pc - pc_start;
8782 tb->icount = num_insns;
8783
8784 if (tcg_check_temp_count()) {
8785 printf("LEAK at %08x\n", env->PC);
8786 }
8787
8788 #ifdef DEBUG_DISAS
8789 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8790 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8791 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
8792 qemu_log("\n");
8793 }
8794 #endif
8795 }
8796
8797 void
8798 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb,
8799 target_ulong *data)
8800 {
8801 env->PC = data[0];
8802 }
8803 /*
8804 *
8805 * Initialization
8806 *
8807 */
8808
8809 void cpu_state_reset(CPUTriCoreState *env)
8810 {
8811 /* Reset Regs to Default Value */
8812 env->PSW = 0xb80;
8813 fpu_set_state(env);
8814 }
8815
8816 static void tricore_tcg_init_csfr(void)
8817 {
8818 cpu_PCXI = tcg_global_mem_new(cpu_env,
8819 offsetof(CPUTriCoreState, PCXI), "PCXI");
8820 cpu_PSW = tcg_global_mem_new(cpu_env,
8821 offsetof(CPUTriCoreState, PSW), "PSW");
8822 cpu_PC = tcg_global_mem_new(cpu_env,
8823 offsetof(CPUTriCoreState, PC), "PC");
8824 cpu_ICR = tcg_global_mem_new(cpu_env,
8825 offsetof(CPUTriCoreState, ICR), "ICR");
8826 }
8827
8828 void tricore_tcg_init(void)
8829 {
8830 int i;
8831 static int inited;
8832 if (inited) {
8833 return;
8834 }
8835 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8836 /* reg init */
8837 for (i = 0 ; i < 16 ; i++) {
8838 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8839 offsetof(CPUTriCoreState, gpr_a[i]),
8840 regnames_a[i]);
8841 }
8842 for (i = 0 ; i < 16 ; i++) {
8843 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8844 offsetof(CPUTriCoreState, gpr_d[i]),
8845 regnames_d[i]);
8846 }
8847 tricore_tcg_init_csfr();
8848 /* init PSW flag cache */
8849 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8850 offsetof(CPUTriCoreState, PSW_USB_C),
8851 "PSW_C");
8852 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8853 offsetof(CPUTriCoreState, PSW_USB_V),
8854 "PSW_V");
8855 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8856 offsetof(CPUTriCoreState, PSW_USB_SV),
8857 "PSW_SV");
8858 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8859 offsetof(CPUTriCoreState, PSW_USB_AV),
8860 "PSW_AV");
8861 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8862 offsetof(CPUTriCoreState, PSW_USB_SAV),
8863 "PSW_SAV");
8864 }
AR7 emulation for QEMU