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cpus: rename local variable to meaningful one
[qemu/ar7.git] / target-ppc / translate.c
blob618334ae51d99891f38bcf935f9b23ddf7bb4313
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip - 4);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 typedef struct opcode_t {
380 unsigned char opc1, opc2, opc3, opc4;
381 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
382 unsigned char pad[4];
383 #endif
384 opc_handler_t handler;
385 const char *oname;
386 } opcode_t;
387
388 /* Helpers for priv. check */
389 #define GEN_PRIV \
390 do { \
391 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
392 } while (0)
393
394 #if defined(CONFIG_USER_ONLY)
395 #define CHK_HV GEN_PRIV
396 #define CHK_SV GEN_PRIV
397 #define CHK_HVRM GEN_PRIV
398 #else
399 #define CHK_HV \
400 do { \
401 if (unlikely(ctx->pr || !ctx->hv)) { \
402 GEN_PRIV; \
403 } \
404 } while (0)
405 #define CHK_SV \
406 do { \
407 if (unlikely(ctx->pr)) { \
408 GEN_PRIV; \
409 } \
410 } while (0)
411 #define CHK_HVRM \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #endif
418
419 #define CHK_NONE
420
421
422 /*****************************************************************************/
423 /*** Instruction decoding ***/
424 #define EXTRACT_HELPER(name, shift, nb) \
425 static inline uint32_t name(uint32_t opcode) \
426 { \
427 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
428 }
429
430 #define EXTRACT_SHELPER(name, shift, nb) \
431 static inline int32_t name(uint32_t opcode) \
432 { \
433 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
437 static inline uint32_t name(uint32_t opcode) \
438 { \
439 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
440 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
441 }
442
443 #define EXTRACT_HELPER_DXFORM(name, \
444 d0_bits, shift_op_d0, shift_d0, \
445 d1_bits, shift_op_d1, shift_d1, \
446 d2_bits, shift_op_d2, shift_d2) \
447 static inline int16_t name(uint32_t opcode) \
448 { \
449 return \
450 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
451 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
452 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
453 }
454
455
456 /* Opcode part 1 */
457 EXTRACT_HELPER(opc1, 26, 6);
458 /* Opcode part 2 */
459 EXTRACT_HELPER(opc2, 1, 5);
460 /* Opcode part 3 */
461 EXTRACT_HELPER(opc3, 6, 5);
462 /* Opcode part 4 */
463 EXTRACT_HELPER(opc4, 16, 5);
464 /* Update Cr0 flags */
465 EXTRACT_HELPER(Rc, 0, 1);
466 /* Update Cr6 flags (Altivec) */
467 EXTRACT_HELPER(Rc21, 10, 1);
468 /* Destination */
469 EXTRACT_HELPER(rD, 21, 5);
470 /* Source */
471 EXTRACT_HELPER(rS, 21, 5);
472 /* First operand */
473 EXTRACT_HELPER(rA, 16, 5);
474 /* Second operand */
475 EXTRACT_HELPER(rB, 11, 5);
476 /* Third operand */
477 EXTRACT_HELPER(rC, 6, 5);
478 /*** Get CRn ***/
479 EXTRACT_HELPER(crfD, 23, 3);
480 EXTRACT_HELPER(crfS, 18, 3);
481 EXTRACT_HELPER(crbD, 21, 5);
482 EXTRACT_HELPER(crbA, 16, 5);
483 EXTRACT_HELPER(crbB, 11, 5);
484 /* SPR / TBL */
485 EXTRACT_HELPER(_SPR, 11, 10);
486 static inline uint32_t SPR(uint32_t opcode)
487 {
488 uint32_t sprn = _SPR(opcode);
489
490 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
491 }
492 /*** Get constants ***/
493 /* 16 bits signed immediate value */
494 EXTRACT_SHELPER(SIMM, 0, 16);
495 /* 16 bits unsigned immediate value */
496 EXTRACT_HELPER(UIMM, 0, 16);
497 /* 5 bits signed immediate value */
498 EXTRACT_HELPER(SIMM5, 16, 5);
499 /* 5 bits signed immediate value */
500 EXTRACT_HELPER(UIMM5, 16, 5);
501 /* Bit count */
502 EXTRACT_HELPER(NB, 11, 5);
503 /* Shift count */
504 EXTRACT_HELPER(SH, 11, 5);
505 /* Vector shift count */
506 EXTRACT_HELPER(VSH, 6, 4);
507 /* Mask start */
508 EXTRACT_HELPER(MB, 6, 5);
509 /* Mask end */
510 EXTRACT_HELPER(ME, 1, 5);
511 /* Trap operand */
512 EXTRACT_HELPER(TO, 21, 5);
513
514 EXTRACT_HELPER(CRM, 12, 8);
515
516 #ifndef CONFIG_USER_ONLY
517 EXTRACT_HELPER(SR, 16, 4);
518 #endif
519
520 /* mtfsf/mtfsfi */
521 EXTRACT_HELPER(FPBF, 23, 3);
522 EXTRACT_HELPER(FPIMM, 12, 4);
523 EXTRACT_HELPER(FPL, 25, 1);
524 EXTRACT_HELPER(FPFLM, 17, 8);
525 EXTRACT_HELPER(FPW, 16, 1);
526
527 /* addpcis */
528 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
529
530 /*** Jump target decoding ***/
531 /* Immediate address */
532 static inline target_ulong LI(uint32_t opcode)
533 {
534 return (opcode >> 0) & 0x03FFFFFC;
535 }
536
537 static inline uint32_t BD(uint32_t opcode)
538 {
539 return (opcode >> 0) & 0xFFFC;
540 }
541
542 EXTRACT_HELPER(BO, 21, 5);
543 EXTRACT_HELPER(BI, 16, 5);
544 /* Absolute/relative address */
545 EXTRACT_HELPER(AA, 1, 1);
546 /* Link */
547 EXTRACT_HELPER(LK, 0, 1);
548
549 /* DFP Z22-form */
550 EXTRACT_HELPER(DCM, 10, 6)
551
552 /* DFP Z23-form */
553 EXTRACT_HELPER(RMC, 9, 2)
554
555 /* Create a mask between <start> and <end> bits */
556 static inline target_ulong MASK(uint32_t start, uint32_t end)
557 {
558 target_ulong ret;
559
560 #if defined(TARGET_PPC64)
561 if (likely(start == 0)) {
562 ret = UINT64_MAX << (63 - end);
563 } else if (likely(end == 63)) {
564 ret = UINT64_MAX >> start;
565 }
566 #else
567 if (likely(start == 0)) {
568 ret = UINT32_MAX << (31 - end);
569 } else if (likely(end == 31)) {
570 ret = UINT32_MAX >> start;
571 }
572 #endif
573 else {
574 ret = (((target_ulong)(-1ULL)) >> (start)) ^
575 (((target_ulong)(-1ULL) >> (end)) >> 1);
576 if (unlikely(start > end))
577 return ~ret;
578 }
579
580 return ret;
581 }
582
583 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
585 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
586 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
587 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
588 EXTRACT_HELPER(DM, 8, 2);
589 EXTRACT_HELPER(UIM, 16, 2);
590 EXTRACT_HELPER(SHW, 8, 2);
591 EXTRACT_HELPER(SP, 19, 2);
592 /*****************************************************************************/
593 /* PowerPC instructions table */
594
595 #if defined(DO_PPC_STATISTICS)
596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
597 { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .opc4 = 0xff, \
602 .handler = { \
603 .inval1 = invl, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 .oname = stringify(name), \
608 }, \
609 .oname = stringify(name), \
610 }
611 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
612 { \
613 .opc1 = op1, \
614 .opc2 = op2, \
615 .opc3 = op3, \
616 .opc4 = 0xff, \
617 .handler = { \
618 .inval1 = invl1, \
619 .inval2 = invl2, \
620 .type = _typ, \
621 .type2 = _typ2, \
622 .handler = &gen_##name, \
623 .oname = stringify(name), \
624 }, \
625 .oname = stringify(name), \
626 }
627 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
628 { \
629 .opc1 = op1, \
630 .opc2 = op2, \
631 .opc3 = op3, \
632 .opc4 = 0xff, \
633 .handler = { \
634 .inval1 = invl, \
635 .type = _typ, \
636 .type2 = _typ2, \
637 .handler = &gen_##name, \
638 .oname = onam, \
639 }, \
640 .oname = onam, \
641 }
642 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
643 { \
644 .opc1 = op1, \
645 .opc2 = op2, \
646 .opc3 = op3, \
647 .opc4 = op4, \
648 .handler = { \
649 .inval1 = invl, \
650 .type = _typ, \
651 .type2 = _typ2, \
652 .handler = &gen_##name, \
653 .oname = stringify(name), \
654 }, \
655 .oname = stringify(name), \
656 }
657 #else
658 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
659 { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .opc4 = 0xff, \
664 .handler = { \
665 .inval1 = invl, \
666 .type = _typ, \
667 .type2 = _typ2, \
668 .handler = &gen_##name, \
669 }, \
670 .oname = stringify(name), \
671 }
672 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
673 { \
674 .opc1 = op1, \
675 .opc2 = op2, \
676 .opc3 = op3, \
677 .opc4 = 0xff, \
678 .handler = { \
679 .inval1 = invl1, \
680 .inval2 = invl2, \
681 .type = _typ, \
682 .type2 = _typ2, \
683 .handler = &gen_##name, \
684 }, \
685 .oname = stringify(name), \
686 }
687 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
688 { \
689 .opc1 = op1, \
690 .opc2 = op2, \
691 .opc3 = op3, \
692 .opc4 = 0xff, \
693 .handler = { \
694 .inval1 = invl, \
695 .type = _typ, \
696 .type2 = _typ2, \
697 .handler = &gen_##name, \
698 }, \
699 .oname = onam, \
700 }
701 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
702 { \
703 .opc1 = op1, \
704 .opc2 = op2, \
705 .opc3 = op3, \
706 .opc4 = op4, \
707 .handler = { \
708 .inval1 = invl, \
709 .type = _typ, \
710 .type2 = _typ2, \
711 .handler = &gen_##name, \
712 }, \
713 .oname = stringify(name), \
714 }
715 #endif
716
717 /* SPR load/store helpers */
718 static inline void gen_load_spr(TCGv t, int reg)
719 {
720 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
721 }
722
723 static inline void gen_store_spr(int reg, TCGv t)
724 {
725 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
726 }
727
728 /* Invalid instruction */
729 static void gen_invalid(DisasContext *ctx)
730 {
731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
732 }
733
734 static opc_handler_t invalid_handler = {
735 .inval1 = 0xFFFFFFFF,
736 .inval2 = 0xFFFFFFFF,
737 .type = PPC_NONE,
738 .type2 = PPC_NONE,
739 .handler = gen_invalid,
740 };
741
742 /*** Integer comparison ***/
743
744 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
745 {
746 TCGv t0 = tcg_temp_new();
747 TCGv_i32 t1 = tcg_temp_new_i32();
748
749 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
750
751 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
752 tcg_gen_trunc_tl_i32(t1, t0);
753 tcg_gen_shli_i32(t1, t1, CRF_LT);
754 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
755
756 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
757 tcg_gen_trunc_tl_i32(t1, t0);
758 tcg_gen_shli_i32(t1, t1, CRF_GT);
759 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
760
761 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
762 tcg_gen_trunc_tl_i32(t1, t0);
763 tcg_gen_shli_i32(t1, t1, CRF_EQ);
764 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
765
766 tcg_temp_free(t0);
767 tcg_temp_free_i32(t1);
768 }
769
770 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
771 {
772 TCGv t0 = tcg_const_tl(arg1);
773 gen_op_cmp(arg0, t0, s, crf);
774 tcg_temp_free(t0);
775 }
776
777 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
778 {
779 TCGv t0, t1;
780 t0 = tcg_temp_new();
781 t1 = tcg_temp_new();
782 if (s) {
783 tcg_gen_ext32s_tl(t0, arg0);
784 tcg_gen_ext32s_tl(t1, arg1);
785 } else {
786 tcg_gen_ext32u_tl(t0, arg0);
787 tcg_gen_ext32u_tl(t1, arg1);
788 }
789 gen_op_cmp(t0, t1, s, crf);
790 tcg_temp_free(t1);
791 tcg_temp_free(t0);
792 }
793
794 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
795 {
796 TCGv t0 = tcg_const_tl(arg1);
797 gen_op_cmp32(arg0, t0, s, crf);
798 tcg_temp_free(t0);
799 }
800
801 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
802 {
803 if (NARROW_MODE(ctx)) {
804 gen_op_cmpi32(reg, 0, 1, 0);
805 } else {
806 gen_op_cmpi(reg, 0, 1, 0);
807 }
808 }
809
810 /* cmp */
811 static void gen_cmp(DisasContext *ctx)
812 {
813 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 1, crfD(ctx->opcode));
816 } else {
817 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 1, crfD(ctx->opcode));
819 }
820 }
821
822 /* cmpi */
823 static void gen_cmpi(DisasContext *ctx)
824 {
825 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
826 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
827 1, crfD(ctx->opcode));
828 } else {
829 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
830 1, crfD(ctx->opcode));
831 }
832 }
833
834 /* cmpl */
835 static void gen_cmpl(DisasContext *ctx)
836 {
837 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
838 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
839 0, crfD(ctx->opcode));
840 } else {
841 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
842 0, crfD(ctx->opcode));
843 }
844 }
845
846 /* cmpli */
847 static void gen_cmpli(DisasContext *ctx)
848 {
849 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
850 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
851 0, crfD(ctx->opcode));
852 } else {
853 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
854 0, crfD(ctx->opcode));
855 }
856 }
857
858 /* cmprb - range comparison: isupper, isaplha, islower*/
859 static void gen_cmprb(DisasContext *ctx)
860 {
861 TCGv_i32 src1 = tcg_temp_new_i32();
862 TCGv_i32 src2 = tcg_temp_new_i32();
863 TCGv_i32 src2lo = tcg_temp_new_i32();
864 TCGv_i32 src2hi = tcg_temp_new_i32();
865 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
866
867 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
868 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
869
870 tcg_gen_andi_i32(src1, src1, 0xFF);
871 tcg_gen_ext8u_i32(src2lo, src2);
872 tcg_gen_shri_i32(src2, src2, 8);
873 tcg_gen_ext8u_i32(src2hi, src2);
874
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
876 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
877 tcg_gen_and_i32(crf, src2lo, src2hi);
878
879 if (ctx->opcode & 0x00200000) {
880 tcg_gen_shri_i32(src2, src2, 8);
881 tcg_gen_ext8u_i32(src2lo, src2);
882 tcg_gen_shri_i32(src2, src2, 8);
883 tcg_gen_ext8u_i32(src2hi, src2);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
885 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
886 tcg_gen_and_i32(src2lo, src2lo, src2hi);
887 tcg_gen_or_i32(crf, crf, src2lo);
888 }
889 tcg_gen_shli_i32(crf, crf, CRF_GT);
890 tcg_temp_free_i32(src1);
891 tcg_temp_free_i32(src2);
892 tcg_temp_free_i32(src2lo);
893 tcg_temp_free_i32(src2hi);
894 }
895
896 #if defined(TARGET_PPC64)
897 /* cmpeqb */
898 static void gen_cmpeqb(DisasContext *ctx)
899 {
900 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
901 cpu_gpr[rB(ctx->opcode)]);
902 }
903 #endif
904
905 /* isel (PowerPC 2.03 specification) */
906 static void gen_isel(DisasContext *ctx)
907 {
908 uint32_t bi = rC(ctx->opcode);
909 uint32_t mask = 0x08 >> (bi & 0x03);
910 TCGv t0 = tcg_temp_new();
911 TCGv zr;
912
913 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
914 tcg_gen_andi_tl(t0, t0, mask);
915
916 zr = tcg_const_tl(0);
917 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
918 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
919 cpu_gpr[rB(ctx->opcode)]);
920 tcg_temp_free(zr);
921 tcg_temp_free(t0);
922 }
923
924 /* cmpb: PowerPC 2.05 specification */
925 static void gen_cmpb(DisasContext *ctx)
926 {
927 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
928 cpu_gpr[rB(ctx->opcode)]);
929 }
930
931 /*** Integer arithmetic ***/
932
933 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
934 TCGv arg1, TCGv arg2, int sub)
935 {
936 TCGv t0 = tcg_temp_new();
937
938 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
939 tcg_gen_xor_tl(t0, arg1, arg2);
940 if (sub) {
941 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
942 } else {
943 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
944 }
945 tcg_temp_free(t0);
946 if (NARROW_MODE(ctx)) {
947 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
948 }
949 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
950 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
951 }
952
953 /* Common add function */
954 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
955 TCGv arg2, bool add_ca, bool compute_ca,
956 bool compute_ov, bool compute_rc0)
957 {
958 TCGv t0 = ret;
959
960 if (compute_ca || compute_ov) {
961 t0 = tcg_temp_new();
962 }
963
964 if (compute_ca) {
965 if (NARROW_MODE(ctx)) {
966 /* Caution: a non-obvious corner case of the spec is that we
967 must produce the *entire* 64-bit addition, but produce the
968 carry into bit 32. */
969 TCGv t1 = tcg_temp_new();
970 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
971 tcg_gen_add_tl(t0, arg1, arg2);
972 if (add_ca) {
973 tcg_gen_add_tl(t0, t0, cpu_ca);
974 }
975 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
976 tcg_temp_free(t1);
977 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
978 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
979 } else {
980 TCGv zero = tcg_const_tl(0);
981 if (add_ca) {
982 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
983 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
984 } else {
985 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
986 }
987 tcg_temp_free(zero);
988 }
989 } else {
990 tcg_gen_add_tl(t0, arg1, arg2);
991 if (add_ca) {
992 tcg_gen_add_tl(t0, t0, cpu_ca);
993 }
994 }
995
996 if (compute_ov) {
997 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
998 }
999 if (unlikely(compute_rc0)) {
1000 gen_set_Rc0(ctx, t0);
1001 }
1002
1003 if (!TCGV_EQUAL(t0, ret)) {
1004 tcg_gen_mov_tl(ret, t0);
1005 tcg_temp_free(t0);
1006 }
1007 }
1008 /* Add functions with two operands */
1009 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1015 }
1016 /* Add functions with one operand and one immediate */
1017 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1018 add_ca, compute_ca, compute_ov) \
1019 static void glue(gen_, name)(DisasContext *ctx) \
1020 { \
1021 TCGv t0 = tcg_const_tl(const_val); \
1022 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1023 cpu_gpr[rA(ctx->opcode)], t0, \
1024 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1025 tcg_temp_free(t0); \
1026 }
1027
1028 /* add add. addo addo. */
1029 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1030 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1031 /* addc addc. addco addco. */
1032 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1033 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1034 /* adde adde. addeo addeo. */
1035 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1036 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1037 /* addme addme. addmeo addmeo. */
1038 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1039 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1040 /* addze addze. addzeo addzeo.*/
1041 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1042 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1043 /* addi */
1044 static void gen_addi(DisasContext *ctx)
1045 {
1046 target_long simm = SIMM(ctx->opcode);
1047
1048 if (rA(ctx->opcode) == 0) {
1049 /* li case */
1050 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1051 } else {
1052 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1053 cpu_gpr[rA(ctx->opcode)], simm);
1054 }
1055 }
1056 /* addic addic.*/
1057 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1058 {
1059 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1060 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1061 c, 0, 1, 0, compute_rc0);
1062 tcg_temp_free(c);
1063 }
1064
1065 static void gen_addic(DisasContext *ctx)
1066 {
1067 gen_op_addic(ctx, 0);
1068 }
1069
1070 static void gen_addic_(DisasContext *ctx)
1071 {
1072 gen_op_addic(ctx, 1);
1073 }
1074
1075 /* addis */
1076 static void gen_addis(DisasContext *ctx)
1077 {
1078 target_long simm = SIMM(ctx->opcode);
1079
1080 if (rA(ctx->opcode) == 0) {
1081 /* lis case */
1082 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1083 } else {
1084 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], simm << 16);
1086 }
1087 }
1088
1089 /* addpcis */
1090 static void gen_addpcis(DisasContext *ctx)
1091 {
1092 target_long d = DX(ctx->opcode);
1093
1094 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1095 }
1096
1097 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1098 TCGv arg2, int sign, int compute_ov)
1099 {
1100 TCGv_i32 t0 = tcg_temp_new_i32();
1101 TCGv_i32 t1 = tcg_temp_new_i32();
1102 TCGv_i32 t2 = tcg_temp_new_i32();
1103 TCGv_i32 t3 = tcg_temp_new_i32();
1104
1105 tcg_gen_trunc_tl_i32(t0, arg1);
1106 tcg_gen_trunc_tl_i32(t1, arg2);
1107 if (sign) {
1108 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1109 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1110 tcg_gen_and_i32(t2, t2, t3);
1111 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1112 tcg_gen_or_i32(t2, t2, t3);
1113 tcg_gen_movi_i32(t3, 0);
1114 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1115 tcg_gen_div_i32(t3, t0, t1);
1116 tcg_gen_extu_i32_tl(ret, t3);
1117 } else {
1118 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1119 tcg_gen_movi_i32(t3, 0);
1120 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1121 tcg_gen_divu_i32(t3, t0, t1);
1122 tcg_gen_extu_i32_tl(ret, t3);
1123 }
1124 if (compute_ov) {
1125 tcg_gen_extu_i32_tl(cpu_ov, t2);
1126 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1127 }
1128 tcg_temp_free_i32(t0);
1129 tcg_temp_free_i32(t1);
1130 tcg_temp_free_i32(t2);
1131 tcg_temp_free_i32(t3);
1132
1133 if (unlikely(Rc(ctx->opcode) != 0))
1134 gen_set_Rc0(ctx, ret);
1135 }
1136 /* Div functions */
1137 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1138 static void glue(gen_, name)(DisasContext *ctx) \
1139 { \
1140 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1141 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1142 sign, compute_ov); \
1143 }
1144 /* divwu divwu. divwuo divwuo. */
1145 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1146 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1147 /* divw divw. divwo divwo. */
1148 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1149 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1150
1151 /* div[wd]eu[o][.] */
1152 #define GEN_DIVE(name, hlpr, compute_ov) \
1153 static void gen_##name(DisasContext *ctx) \
1154 { \
1155 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1156 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1157 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1158 tcg_temp_free_i32(t0); \
1159 if (unlikely(Rc(ctx->opcode) != 0)) { \
1160 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1161 } \
1162 }
1163
1164 GEN_DIVE(divweu, divweu, 0);
1165 GEN_DIVE(divweuo, divweu, 1);
1166 GEN_DIVE(divwe, divwe, 0);
1167 GEN_DIVE(divweo, divwe, 1);
1168
1169 #if defined(TARGET_PPC64)
1170 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1171 TCGv arg2, int sign, int compute_ov)
1172 {
1173 TCGv_i64 t0 = tcg_temp_new_i64();
1174 TCGv_i64 t1 = tcg_temp_new_i64();
1175 TCGv_i64 t2 = tcg_temp_new_i64();
1176 TCGv_i64 t3 = tcg_temp_new_i64();
1177
1178 tcg_gen_mov_i64(t0, arg1);
1179 tcg_gen_mov_i64(t1, arg2);
1180 if (sign) {
1181 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1182 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1183 tcg_gen_and_i64(t2, t2, t3);
1184 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1185 tcg_gen_or_i64(t2, t2, t3);
1186 tcg_gen_movi_i64(t3, 0);
1187 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1188 tcg_gen_div_i64(ret, t0, t1);
1189 } else {
1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1191 tcg_gen_movi_i64(t3, 0);
1192 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1193 tcg_gen_divu_i64(ret, t0, t1);
1194 }
1195 if (compute_ov) {
1196 tcg_gen_mov_tl(cpu_ov, t2);
1197 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1198 }
1199 tcg_temp_free_i64(t0);
1200 tcg_temp_free_i64(t1);
1201 tcg_temp_free_i64(t2);
1202 tcg_temp_free_i64(t3);
1203
1204 if (unlikely(Rc(ctx->opcode) != 0))
1205 gen_set_Rc0(ctx, ret);
1206 }
1207
1208 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1209 static void glue(gen_, name)(DisasContext *ctx) \
1210 { \
1211 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1212 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1213 sign, compute_ov); \
1214 }
1215 /* divwu divwu. divwuo divwuo. */
1216 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1217 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1218 /* divw divw. divwo divwo. */
1219 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1220 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1221
1222 GEN_DIVE(divdeu, divdeu, 0);
1223 GEN_DIVE(divdeuo, divdeu, 1);
1224 GEN_DIVE(divde, divde, 0);
1225 GEN_DIVE(divdeo, divde, 1);
1226 #endif
1227
1228 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1229 TCGv arg2, int sign)
1230 {
1231 TCGv_i32 t0 = tcg_temp_new_i32();
1232 TCGv_i32 t1 = tcg_temp_new_i32();
1233
1234 tcg_gen_trunc_tl_i32(t0, arg1);
1235 tcg_gen_trunc_tl_i32(t1, arg2);
1236 if (sign) {
1237 TCGv_i32 t2 = tcg_temp_new_i32();
1238 TCGv_i32 t3 = tcg_temp_new_i32();
1239 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1240 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1241 tcg_gen_and_i32(t2, t2, t3);
1242 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1243 tcg_gen_or_i32(t2, t2, t3);
1244 tcg_gen_movi_i32(t3, 0);
1245 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1246 tcg_gen_rem_i32(t3, t0, t1);
1247 tcg_gen_ext_i32_tl(ret, t3);
1248 tcg_temp_free_i32(t2);
1249 tcg_temp_free_i32(t3);
1250 } else {
1251 TCGv_i32 t2 = tcg_const_i32(1);
1252 TCGv_i32 t3 = tcg_const_i32(0);
1253 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1254 tcg_gen_remu_i32(t3, t0, t1);
1255 tcg_gen_extu_i32_tl(ret, t3);
1256 tcg_temp_free_i32(t2);
1257 tcg_temp_free_i32(t3);
1258 }
1259 tcg_temp_free_i32(t0);
1260 tcg_temp_free_i32(t1);
1261 }
1262
1263 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1264 static void glue(gen_, name)(DisasContext *ctx) \
1265 { \
1266 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1267 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1268 sign); \
1269 }
1270
1271 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1272 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1273
1274 #if defined(TARGET_PPC64)
1275 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1276 TCGv arg2, int sign)
1277 {
1278 TCGv_i64 t0 = tcg_temp_new_i64();
1279 TCGv_i64 t1 = tcg_temp_new_i64();
1280
1281 tcg_gen_mov_i64(t0, arg1);
1282 tcg_gen_mov_i64(t1, arg2);
1283 if (sign) {
1284 TCGv_i64 t2 = tcg_temp_new_i64();
1285 TCGv_i64 t3 = tcg_temp_new_i64();
1286 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1287 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1288 tcg_gen_and_i64(t2, t2, t3);
1289 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1290 tcg_gen_or_i64(t2, t2, t3);
1291 tcg_gen_movi_i64(t3, 0);
1292 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1293 tcg_gen_rem_i64(ret, t0, t1);
1294 tcg_temp_free_i64(t2);
1295 tcg_temp_free_i64(t3);
1296 } else {
1297 TCGv_i64 t2 = tcg_const_i64(1);
1298 TCGv_i64 t3 = tcg_const_i64(0);
1299 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1300 tcg_gen_remu_i64(ret, t0, t1);
1301 tcg_temp_free_i64(t2);
1302 tcg_temp_free_i64(t3);
1303 }
1304 tcg_temp_free_i64(t0);
1305 tcg_temp_free_i64(t1);
1306 }
1307
1308 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1309 static void glue(gen_, name)(DisasContext *ctx) \
1310 { \
1311 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1312 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1313 sign); \
1314 }
1315
1316 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1317 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1318 #endif
1319
1320 /* mulhw mulhw. */
1321 static void gen_mulhw(DisasContext *ctx)
1322 {
1323 TCGv_i32 t0 = tcg_temp_new_i32();
1324 TCGv_i32 t1 = tcg_temp_new_i32();
1325
1326 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1327 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1328 tcg_gen_muls2_i32(t0, t1, t0, t1);
1329 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1330 tcg_temp_free_i32(t0);
1331 tcg_temp_free_i32(t1);
1332 if (unlikely(Rc(ctx->opcode) != 0))
1333 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1334 }
1335
1336 /* mulhwu mulhwu. */
1337 static void gen_mulhwu(DisasContext *ctx)
1338 {
1339 TCGv_i32 t0 = tcg_temp_new_i32();
1340 TCGv_i32 t1 = tcg_temp_new_i32();
1341
1342 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1343 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1344 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1345 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1346 tcg_temp_free_i32(t0);
1347 tcg_temp_free_i32(t1);
1348 if (unlikely(Rc(ctx->opcode) != 0))
1349 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1350 }
1351
1352 /* mullw mullw. */
1353 static void gen_mullw(DisasContext *ctx)
1354 {
1355 #if defined(TARGET_PPC64)
1356 TCGv_i64 t0, t1;
1357 t0 = tcg_temp_new_i64();
1358 t1 = tcg_temp_new_i64();
1359 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1360 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1361 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1362 tcg_temp_free(t0);
1363 tcg_temp_free(t1);
1364 #else
1365 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1366 cpu_gpr[rB(ctx->opcode)]);
1367 #endif
1368 if (unlikely(Rc(ctx->opcode) != 0))
1369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1370 }
1371
1372 /* mullwo mullwo. */
1373 static void gen_mullwo(DisasContext *ctx)
1374 {
1375 TCGv_i32 t0 = tcg_temp_new_i32();
1376 TCGv_i32 t1 = tcg_temp_new_i32();
1377
1378 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1379 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1380 tcg_gen_muls2_i32(t0, t1, t0, t1);
1381 #if defined(TARGET_PPC64)
1382 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1383 #else
1384 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1385 #endif
1386
1387 tcg_gen_sari_i32(t0, t0, 31);
1388 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1389 tcg_gen_extu_i32_tl(cpu_ov, t0);
1390 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1391
1392 tcg_temp_free_i32(t0);
1393 tcg_temp_free_i32(t1);
1394 if (unlikely(Rc(ctx->opcode) != 0))
1395 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1396 }
1397
1398 /* mulli */
1399 static void gen_mulli(DisasContext *ctx)
1400 {
1401 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1402 SIMM(ctx->opcode));
1403 }
1404
1405 #if defined(TARGET_PPC64)
1406 /* mulhd mulhd. */
1407 static void gen_mulhd(DisasContext *ctx)
1408 {
1409 TCGv lo = tcg_temp_new();
1410 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1411 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1412 tcg_temp_free(lo);
1413 if (unlikely(Rc(ctx->opcode) != 0)) {
1414 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1415 }
1416 }
1417
1418 /* mulhdu mulhdu. */
1419 static void gen_mulhdu(DisasContext *ctx)
1420 {
1421 TCGv lo = tcg_temp_new();
1422 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1423 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1424 tcg_temp_free(lo);
1425 if (unlikely(Rc(ctx->opcode) != 0)) {
1426 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1427 }
1428 }
1429
1430 /* mulld mulld. */
1431 static void gen_mulld(DisasContext *ctx)
1432 {
1433 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1434 cpu_gpr[rB(ctx->opcode)]);
1435 if (unlikely(Rc(ctx->opcode) != 0))
1436 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1437 }
1438
1439 /* mulldo mulldo. */
1440 static void gen_mulldo(DisasContext *ctx)
1441 {
1442 TCGv_i64 t0 = tcg_temp_new_i64();
1443 TCGv_i64 t1 = tcg_temp_new_i64();
1444
1445 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1446 cpu_gpr[rB(ctx->opcode)]);
1447 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1448
1449 tcg_gen_sari_i64(t0, t0, 63);
1450 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1451 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1452
1453 tcg_temp_free_i64(t0);
1454 tcg_temp_free_i64(t1);
1455
1456 if (unlikely(Rc(ctx->opcode) != 0)) {
1457 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1458 }
1459 }
1460 #endif
1461
1462 /* Common subf function */
1463 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1464 TCGv arg2, bool add_ca, bool compute_ca,
1465 bool compute_ov, bool compute_rc0)
1466 {
1467 TCGv t0 = ret;
1468
1469 if (compute_ca || compute_ov) {
1470 t0 = tcg_temp_new();
1471 }
1472
1473 if (compute_ca) {
1474 /* dest = ~arg1 + arg2 [+ ca]. */
1475 if (NARROW_MODE(ctx)) {
1476 /* Caution: a non-obvious corner case of the spec is that we
1477 must produce the *entire* 64-bit addition, but produce the
1478 carry into bit 32. */
1479 TCGv inv1 = tcg_temp_new();
1480 TCGv t1 = tcg_temp_new();
1481 tcg_gen_not_tl(inv1, arg1);
1482 if (add_ca) {
1483 tcg_gen_add_tl(t0, arg2, cpu_ca);
1484 } else {
1485 tcg_gen_addi_tl(t0, arg2, 1);
1486 }
1487 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1488 tcg_gen_add_tl(t0, t0, inv1);
1489 tcg_temp_free(inv1);
1490 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1491 tcg_temp_free(t1);
1492 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1493 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1494 } else if (add_ca) {
1495 TCGv zero, inv1 = tcg_temp_new();
1496 tcg_gen_not_tl(inv1, arg1);
1497 zero = tcg_const_tl(0);
1498 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1499 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1500 tcg_temp_free(zero);
1501 tcg_temp_free(inv1);
1502 } else {
1503 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1504 tcg_gen_sub_tl(t0, arg2, arg1);
1505 }
1506 } else if (add_ca) {
1507 /* Since we're ignoring carry-out, we can simplify the
1508 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1509 tcg_gen_sub_tl(t0, arg2, arg1);
1510 tcg_gen_add_tl(t0, t0, cpu_ca);
1511 tcg_gen_subi_tl(t0, t0, 1);
1512 } else {
1513 tcg_gen_sub_tl(t0, arg2, arg1);
1514 }
1515
1516 if (compute_ov) {
1517 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1518 }
1519 if (unlikely(compute_rc0)) {
1520 gen_set_Rc0(ctx, t0);
1521 }
1522
1523 if (!TCGV_EQUAL(t0, ret)) {
1524 tcg_gen_mov_tl(ret, t0);
1525 tcg_temp_free(t0);
1526 }
1527 }
1528 /* Sub functions with Two operands functions */
1529 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1530 static void glue(gen_, name)(DisasContext *ctx) \
1531 { \
1532 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1533 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1534 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1535 }
1536 /* Sub functions with one operand and one immediate */
1537 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1538 add_ca, compute_ca, compute_ov) \
1539 static void glue(gen_, name)(DisasContext *ctx) \
1540 { \
1541 TCGv t0 = tcg_const_tl(const_val); \
1542 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1543 cpu_gpr[rA(ctx->opcode)], t0, \
1544 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1545 tcg_temp_free(t0); \
1546 }
1547 /* subf subf. subfo subfo. */
1548 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1549 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1550 /* subfc subfc. subfco subfco. */
1551 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1552 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1553 /* subfe subfe. subfeo subfo. */
1554 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1555 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1556 /* subfme subfme. subfmeo subfmeo. */
1557 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1558 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1559 /* subfze subfze. subfzeo subfzeo.*/
1560 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1561 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1562
1563 /* subfic */
1564 static void gen_subfic(DisasContext *ctx)
1565 {
1566 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1567 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1568 c, 0, 1, 0, 0);
1569 tcg_temp_free(c);
1570 }
1571
1572 /* neg neg. nego nego. */
1573 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1574 {
1575 TCGv zero = tcg_const_tl(0);
1576 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1577 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1578 tcg_temp_free(zero);
1579 }
1580
1581 static void gen_neg(DisasContext *ctx)
1582 {
1583 gen_op_arith_neg(ctx, 0);
1584 }
1585
1586 static void gen_nego(DisasContext *ctx)
1587 {
1588 gen_op_arith_neg(ctx, 1);
1589 }
1590
1591 /*** Integer logical ***/
1592 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1593 static void glue(gen_, name)(DisasContext *ctx) \
1594 { \
1595 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1596 cpu_gpr[rB(ctx->opcode)]); \
1597 if (unlikely(Rc(ctx->opcode) != 0)) \
1598 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1599 }
1600
1601 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1602 static void glue(gen_, name)(DisasContext *ctx) \
1603 { \
1604 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1605 if (unlikely(Rc(ctx->opcode) != 0)) \
1606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1607 }
1608
1609 /* and & and. */
1610 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1611 /* andc & andc. */
1612 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1613
1614 /* andi. */
1615 static void gen_andi_(DisasContext *ctx)
1616 {
1617 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1618 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1619 }
1620
1621 /* andis. */
1622 static void gen_andis_(DisasContext *ctx)
1623 {
1624 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1626 }
1627
1628 /* cntlzw */
1629 static void gen_cntlzw(DisasContext *ctx)
1630 {
1631 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1632 if (unlikely(Rc(ctx->opcode) != 0))
1633 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1634 }
1635
1636 /* cnttzw */
1637 static void gen_cnttzw(DisasContext *ctx)
1638 {
1639 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1640 if (unlikely(Rc(ctx->opcode) != 0)) {
1641 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1642 }
1643 }
1644
1645 /* eqv & eqv. */
1646 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1647 /* extsb & extsb. */
1648 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1649 /* extsh & extsh. */
1650 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1651 /* nand & nand. */
1652 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1653 /* nor & nor. */
1654 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1655
1656 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1657 static void gen_pause(DisasContext *ctx)
1658 {
1659 TCGv_i32 t0 = tcg_const_i32(0);
1660 tcg_gen_st_i32(t0, cpu_env,
1661 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1662 tcg_temp_free_i32(t0);
1663
1664 /* Stop translation, this gives other CPUs a chance to run */
1665 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1666 }
1667 #endif /* defined(TARGET_PPC64) */
1668
1669 /* or & or. */
1670 static void gen_or(DisasContext *ctx)
1671 {
1672 int rs, ra, rb;
1673
1674 rs = rS(ctx->opcode);
1675 ra = rA(ctx->opcode);
1676 rb = rB(ctx->opcode);
1677 /* Optimisation for mr. ri case */
1678 if (rs != ra || rs != rb) {
1679 if (rs != rb)
1680 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1681 else
1682 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1683 if (unlikely(Rc(ctx->opcode) != 0))
1684 gen_set_Rc0(ctx, cpu_gpr[ra]);
1685 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1686 gen_set_Rc0(ctx, cpu_gpr[rs]);
1687 #if defined(TARGET_PPC64)
1688 } else if (rs != 0) { /* 0 is nop */
1689 int prio = 0;
1690
1691 switch (rs) {
1692 case 1:
1693 /* Set process priority to low */
1694 prio = 2;
1695 break;
1696 case 6:
1697 /* Set process priority to medium-low */
1698 prio = 3;
1699 break;
1700 case 2:
1701 /* Set process priority to normal */
1702 prio = 4;
1703 break;
1704 #if !defined(CONFIG_USER_ONLY)
1705 case 31:
1706 if (!ctx->pr) {
1707 /* Set process priority to very low */
1708 prio = 1;
1709 }
1710 break;
1711 case 5:
1712 if (!ctx->pr) {
1713 /* Set process priority to medium-hight */
1714 prio = 5;
1715 }
1716 break;
1717 case 3:
1718 if (!ctx->pr) {
1719 /* Set process priority to high */
1720 prio = 6;
1721 }
1722 break;
1723 case 7:
1724 if (ctx->hv && !ctx->pr) {
1725 /* Set process priority to very high */
1726 prio = 7;
1727 }
1728 break;
1729 #endif
1730 default:
1731 break;
1732 }
1733 if (prio) {
1734 TCGv t0 = tcg_temp_new();
1735 gen_load_spr(t0, SPR_PPR);
1736 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1737 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1738 gen_store_spr(SPR_PPR, t0);
1739 tcg_temp_free(t0);
1740 }
1741 #if !defined(CONFIG_USER_ONLY)
1742 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1743 * CPU and the kernel hangs. This applies to all encodings other
1744 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1745 * and all currently undefined.
1746 */
1747 gen_pause(ctx);
1748 #endif
1749 #endif
1750 }
1751 }
1752 /* orc & orc. */
1753 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1754
1755 /* xor & xor. */
1756 static void gen_xor(DisasContext *ctx)
1757 {
1758 /* Optimisation for "set to zero" case */
1759 if (rS(ctx->opcode) != rB(ctx->opcode))
1760 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1761 else
1762 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766
1767 /* ori */
1768 static void gen_ori(DisasContext *ctx)
1769 {
1770 target_ulong uimm = UIMM(ctx->opcode);
1771
1772 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1773 return;
1774 }
1775 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1776 }
1777
1778 /* oris */
1779 static void gen_oris(DisasContext *ctx)
1780 {
1781 target_ulong uimm = UIMM(ctx->opcode);
1782
1783 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1784 /* NOP */
1785 return;
1786 }
1787 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1788 }
1789
1790 /* xori */
1791 static void gen_xori(DisasContext *ctx)
1792 {
1793 target_ulong uimm = UIMM(ctx->opcode);
1794
1795 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1796 /* NOP */
1797 return;
1798 }
1799 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1800 }
1801
1802 /* xoris */
1803 static void gen_xoris(DisasContext *ctx)
1804 {
1805 target_ulong uimm = UIMM(ctx->opcode);
1806
1807 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1808 /* NOP */
1809 return;
1810 }
1811 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1812 }
1813
1814 /* popcntb : PowerPC 2.03 specification */
1815 static void gen_popcntb(DisasContext *ctx)
1816 {
1817 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1818 }
1819
1820 static void gen_popcntw(DisasContext *ctx)
1821 {
1822 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1823 }
1824
1825 #if defined(TARGET_PPC64)
1826 /* popcntd: PowerPC 2.06 specification */
1827 static void gen_popcntd(DisasContext *ctx)
1828 {
1829 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1830 }
1831 #endif
1832
1833 /* prtyw: PowerPC 2.05 specification */
1834 static void gen_prtyw(DisasContext *ctx)
1835 {
1836 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1837 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1838 TCGv t0 = tcg_temp_new();
1839 tcg_gen_shri_tl(t0, rs, 16);
1840 tcg_gen_xor_tl(ra, rs, t0);
1841 tcg_gen_shri_tl(t0, ra, 8);
1842 tcg_gen_xor_tl(ra, ra, t0);
1843 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1844 tcg_temp_free(t0);
1845 }
1846
1847 #if defined(TARGET_PPC64)
1848 /* prtyd: PowerPC 2.05 specification */
1849 static void gen_prtyd(DisasContext *ctx)
1850 {
1851 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1852 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1853 TCGv t0 = tcg_temp_new();
1854 tcg_gen_shri_tl(t0, rs, 32);
1855 tcg_gen_xor_tl(ra, rs, t0);
1856 tcg_gen_shri_tl(t0, ra, 16);
1857 tcg_gen_xor_tl(ra, ra, t0);
1858 tcg_gen_shri_tl(t0, ra, 8);
1859 tcg_gen_xor_tl(ra, ra, t0);
1860 tcg_gen_andi_tl(ra, ra, 1);
1861 tcg_temp_free(t0);
1862 }
1863 #endif
1864
1865 #if defined(TARGET_PPC64)
1866 /* bpermd */
1867 static void gen_bpermd(DisasContext *ctx)
1868 {
1869 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1870 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1871 }
1872 #endif
1873
1874 #if defined(TARGET_PPC64)
1875 /* extsw & extsw. */
1876 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1877
1878 /* cntlzd */
1879 static void gen_cntlzd(DisasContext *ctx)
1880 {
1881 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1882 if (unlikely(Rc(ctx->opcode) != 0))
1883 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1884 }
1885
1886 /* cnttzd */
1887 static void gen_cnttzd(DisasContext *ctx)
1888 {
1889 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1890 if (unlikely(Rc(ctx->opcode) != 0)) {
1891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1892 }
1893 }
1894 #endif
1895
1896 /*** Integer rotate ***/
1897
1898 /* rlwimi & rlwimi. */
1899 static void gen_rlwimi(DisasContext *ctx)
1900 {
1901 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1902 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1903 uint32_t sh = SH(ctx->opcode);
1904 uint32_t mb = MB(ctx->opcode);
1905 uint32_t me = ME(ctx->opcode);
1906
1907 if (sh == (31-me) && mb <= me) {
1908 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1909 } else {
1910 target_ulong mask;
1911 TCGv t1;
1912
1913 #if defined(TARGET_PPC64)
1914 mb += 32;
1915 me += 32;
1916 #endif
1917 mask = MASK(mb, me);
1918
1919 t1 = tcg_temp_new();
1920 if (mask <= 0xffffffffu) {
1921 TCGv_i32 t0 = tcg_temp_new_i32();
1922 tcg_gen_trunc_tl_i32(t0, t_rs);
1923 tcg_gen_rotli_i32(t0, t0, sh);
1924 tcg_gen_extu_i32_tl(t1, t0);
1925 tcg_temp_free_i32(t0);
1926 } else {
1927 #if defined(TARGET_PPC64)
1928 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1929 tcg_gen_rotli_i64(t1, t1, sh);
1930 #else
1931 g_assert_not_reached();
1932 #endif
1933 }
1934
1935 tcg_gen_andi_tl(t1, t1, mask);
1936 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1937 tcg_gen_or_tl(t_ra, t_ra, t1);
1938 tcg_temp_free(t1);
1939 }
1940 if (unlikely(Rc(ctx->opcode) != 0)) {
1941 gen_set_Rc0(ctx, t_ra);
1942 }
1943 }
1944
1945 /* rlwinm & rlwinm. */
1946 static void gen_rlwinm(DisasContext *ctx)
1947 {
1948 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1949 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1950 uint32_t sh = SH(ctx->opcode);
1951 uint32_t mb = MB(ctx->opcode);
1952 uint32_t me = ME(ctx->opcode);
1953
1954 if (mb == 0 && me == (31 - sh)) {
1955 tcg_gen_shli_tl(t_ra, t_rs, sh);
1956 tcg_gen_ext32u_tl(t_ra, t_ra);
1957 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1958 tcg_gen_ext32u_tl(t_ra, t_rs);
1959 tcg_gen_shri_tl(t_ra, t_ra, mb);
1960 } else {
1961 target_ulong mask;
1962 #if defined(TARGET_PPC64)
1963 mb += 32;
1964 me += 32;
1965 #endif
1966 mask = MASK(mb, me);
1967
1968 if (mask <= 0xffffffffu) {
1969 TCGv_i32 t0 = tcg_temp_new_i32();
1970 tcg_gen_trunc_tl_i32(t0, t_rs);
1971 tcg_gen_rotli_i32(t0, t0, sh);
1972 tcg_gen_andi_i32(t0, t0, mask);
1973 tcg_gen_extu_i32_tl(t_ra, t0);
1974 tcg_temp_free_i32(t0);
1975 } else {
1976 #if defined(TARGET_PPC64)
1977 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1978 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1979 tcg_gen_andi_i64(t_ra, t_ra, mask);
1980 #else
1981 g_assert_not_reached();
1982 #endif
1983 }
1984 }
1985 if (unlikely(Rc(ctx->opcode) != 0)) {
1986 gen_set_Rc0(ctx, t_ra);
1987 }
1988 }
1989
1990 /* rlwnm & rlwnm. */
1991 static void gen_rlwnm(DisasContext *ctx)
1992 {
1993 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1994 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1995 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1996 uint32_t mb = MB(ctx->opcode);
1997 uint32_t me = ME(ctx->opcode);
1998 target_ulong mask;
1999
2000 #if defined(TARGET_PPC64)
2001 mb += 32;
2002 me += 32;
2003 #endif
2004 mask = MASK(mb, me);
2005
2006 if (mask <= 0xffffffffu) {
2007 TCGv_i32 t0 = tcg_temp_new_i32();
2008 TCGv_i32 t1 = tcg_temp_new_i32();
2009 tcg_gen_trunc_tl_i32(t0, t_rb);
2010 tcg_gen_trunc_tl_i32(t1, t_rs);
2011 tcg_gen_andi_i32(t0, t0, 0x1f);
2012 tcg_gen_rotl_i32(t1, t1, t0);
2013 tcg_gen_extu_i32_tl(t_ra, t1);
2014 tcg_temp_free_i32(t0);
2015 tcg_temp_free_i32(t1);
2016 } else {
2017 #if defined(TARGET_PPC64)
2018 TCGv_i64 t0 = tcg_temp_new_i64();
2019 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2020 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2021 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2022 tcg_temp_free_i64(t0);
2023 #else
2024 g_assert_not_reached();
2025 #endif
2026 }
2027
2028 tcg_gen_andi_tl(t_ra, t_ra, mask);
2029
2030 if (unlikely(Rc(ctx->opcode) != 0)) {
2031 gen_set_Rc0(ctx, t_ra);
2032 }
2033 }
2034
2035 #if defined(TARGET_PPC64)
2036 #define GEN_PPC64_R2(name, opc1, opc2) \
2037 static void glue(gen_, name##0)(DisasContext *ctx) \
2038 { \
2039 gen_##name(ctx, 0); \
2040 } \
2041 \
2042 static void glue(gen_, name##1)(DisasContext *ctx) \
2043 { \
2044 gen_##name(ctx, 1); \
2045 }
2046 #define GEN_PPC64_R4(name, opc1, opc2) \
2047 static void glue(gen_, name##0)(DisasContext *ctx) \
2048 { \
2049 gen_##name(ctx, 0, 0); \
2050 } \
2051 \
2052 static void glue(gen_, name##1)(DisasContext *ctx) \
2053 { \
2054 gen_##name(ctx, 0, 1); \
2055 } \
2056 \
2057 static void glue(gen_, name##2)(DisasContext *ctx) \
2058 { \
2059 gen_##name(ctx, 1, 0); \
2060 } \
2061 \
2062 static void glue(gen_, name##3)(DisasContext *ctx) \
2063 { \
2064 gen_##name(ctx, 1, 1); \
2065 }
2066
2067 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2068 {
2069 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2070 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2071
2072 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2073 tcg_gen_shli_tl(t_ra, t_rs, sh);
2074 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2075 tcg_gen_shri_tl(t_ra, t_rs, mb);
2076 } else {
2077 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2078 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2079 }
2080 if (unlikely(Rc(ctx->opcode) != 0)) {
2081 gen_set_Rc0(ctx, t_ra);
2082 }
2083 }
2084
2085 /* rldicl - rldicl. */
2086 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2087 {
2088 uint32_t sh, mb;
2089
2090 sh = SH(ctx->opcode) | (shn << 5);
2091 mb = MB(ctx->opcode) | (mbn << 5);
2092 gen_rldinm(ctx, mb, 63, sh);
2093 }
2094 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2095
2096 /* rldicr - rldicr. */
2097 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2098 {
2099 uint32_t sh, me;
2100
2101 sh = SH(ctx->opcode) | (shn << 5);
2102 me = MB(ctx->opcode) | (men << 5);
2103 gen_rldinm(ctx, 0, me, sh);
2104 }
2105 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2106
2107 /* rldic - rldic. */
2108 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2109 {
2110 uint32_t sh, mb;
2111
2112 sh = SH(ctx->opcode) | (shn << 5);
2113 mb = MB(ctx->opcode) | (mbn << 5);
2114 gen_rldinm(ctx, mb, 63 - sh, sh);
2115 }
2116 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2117
2118 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2119 {
2120 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2121 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2122 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2123 TCGv t0;
2124
2125 t0 = tcg_temp_new();
2126 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2127 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2128 tcg_temp_free(t0);
2129
2130 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2131 if (unlikely(Rc(ctx->opcode) != 0)) {
2132 gen_set_Rc0(ctx, t_ra);
2133 }
2134 }
2135
2136 /* rldcl - rldcl. */
2137 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2138 {
2139 uint32_t mb;
2140
2141 mb = MB(ctx->opcode) | (mbn << 5);
2142 gen_rldnm(ctx, mb, 63);
2143 }
2144 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2145
2146 /* rldcr - rldcr. */
2147 static inline void gen_rldcr(DisasContext *ctx, int men)
2148 {
2149 uint32_t me;
2150
2151 me = MB(ctx->opcode) | (men << 5);
2152 gen_rldnm(ctx, 0, me);
2153 }
2154 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2155
2156 /* rldimi - rldimi. */
2157 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2158 {
2159 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2160 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2161 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2162 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2163 uint32_t me = 63 - sh;
2164
2165 if (mb <= me) {
2166 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2167 } else {
2168 target_ulong mask = MASK(mb, me);
2169 TCGv t1 = tcg_temp_new();
2170
2171 tcg_gen_rotli_tl(t1, t_rs, sh);
2172 tcg_gen_andi_tl(t1, t1, mask);
2173 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2174 tcg_gen_or_tl(t_ra, t_ra, t1);
2175 tcg_temp_free(t1);
2176 }
2177 if (unlikely(Rc(ctx->opcode) != 0)) {
2178 gen_set_Rc0(ctx, t_ra);
2179 }
2180 }
2181 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2182 #endif
2183
2184 /*** Integer shift ***/
2185
2186 /* slw & slw. */
2187 static void gen_slw(DisasContext *ctx)
2188 {
2189 TCGv t0, t1;
2190
2191 t0 = tcg_temp_new();
2192 /* AND rS with a mask that is 0 when rB >= 0x20 */
2193 #if defined(TARGET_PPC64)
2194 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2195 tcg_gen_sari_tl(t0, t0, 0x3f);
2196 #else
2197 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2198 tcg_gen_sari_tl(t0, t0, 0x1f);
2199 #endif
2200 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2201 t1 = tcg_temp_new();
2202 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2203 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2204 tcg_temp_free(t1);
2205 tcg_temp_free(t0);
2206 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2207 if (unlikely(Rc(ctx->opcode) != 0))
2208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2209 }
2210
2211 /* sraw & sraw. */
2212 static void gen_sraw(DisasContext *ctx)
2213 {
2214 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2215 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2216 if (unlikely(Rc(ctx->opcode) != 0))
2217 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2218 }
2219
2220 /* srawi & srawi. */
2221 static void gen_srawi(DisasContext *ctx)
2222 {
2223 int sh = SH(ctx->opcode);
2224 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2225 TCGv src = cpu_gpr[rS(ctx->opcode)];
2226 if (sh == 0) {
2227 tcg_gen_ext32s_tl(dst, src);
2228 tcg_gen_movi_tl(cpu_ca, 0);
2229 } else {
2230 TCGv t0;
2231 tcg_gen_ext32s_tl(dst, src);
2232 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2233 t0 = tcg_temp_new();
2234 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2235 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2236 tcg_temp_free(t0);
2237 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2238 tcg_gen_sari_tl(dst, dst, sh);
2239 }
2240 if (unlikely(Rc(ctx->opcode) != 0)) {
2241 gen_set_Rc0(ctx, dst);
2242 }
2243 }
2244
2245 /* srw & srw. */
2246 static void gen_srw(DisasContext *ctx)
2247 {
2248 TCGv t0, t1;
2249
2250 t0 = tcg_temp_new();
2251 /* AND rS with a mask that is 0 when rB >= 0x20 */
2252 #if defined(TARGET_PPC64)
2253 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2254 tcg_gen_sari_tl(t0, t0, 0x3f);
2255 #else
2256 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2257 tcg_gen_sari_tl(t0, t0, 0x1f);
2258 #endif
2259 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2260 tcg_gen_ext32u_tl(t0, t0);
2261 t1 = tcg_temp_new();
2262 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2263 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2264 tcg_temp_free(t1);
2265 tcg_temp_free(t0);
2266 if (unlikely(Rc(ctx->opcode) != 0))
2267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2268 }
2269
2270 #if defined(TARGET_PPC64)
2271 /* sld & sld. */
2272 static void gen_sld(DisasContext *ctx)
2273 {
2274 TCGv t0, t1;
2275
2276 t0 = tcg_temp_new();
2277 /* AND rS with a mask that is 0 when rB >= 0x40 */
2278 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2279 tcg_gen_sari_tl(t0, t0, 0x3f);
2280 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2281 t1 = tcg_temp_new();
2282 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2283 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2284 tcg_temp_free(t1);
2285 tcg_temp_free(t0);
2286 if (unlikely(Rc(ctx->opcode) != 0))
2287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2288 }
2289
2290 /* srad & srad. */
2291 static void gen_srad(DisasContext *ctx)
2292 {
2293 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2294 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2295 if (unlikely(Rc(ctx->opcode) != 0))
2296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2297 }
2298 /* sradi & sradi. */
2299 static inline void gen_sradi(DisasContext *ctx, int n)
2300 {
2301 int sh = SH(ctx->opcode) + (n << 5);
2302 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2303 TCGv src = cpu_gpr[rS(ctx->opcode)];
2304 if (sh == 0) {
2305 tcg_gen_mov_tl(dst, src);
2306 tcg_gen_movi_tl(cpu_ca, 0);
2307 } else {
2308 TCGv t0;
2309 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2310 t0 = tcg_temp_new();
2311 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2312 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2313 tcg_temp_free(t0);
2314 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2315 tcg_gen_sari_tl(dst, src, sh);
2316 }
2317 if (unlikely(Rc(ctx->opcode) != 0)) {
2318 gen_set_Rc0(ctx, dst);
2319 }
2320 }
2321
2322 static void gen_sradi0(DisasContext *ctx)
2323 {
2324 gen_sradi(ctx, 0);
2325 }
2326
2327 static void gen_sradi1(DisasContext *ctx)
2328 {
2329 gen_sradi(ctx, 1);
2330 }
2331
2332 /* extswsli & extswsli. */
2333 static inline void gen_extswsli(DisasContext *ctx, int n)
2334 {
2335 int sh = SH(ctx->opcode) + (n << 5);
2336 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2337 TCGv src = cpu_gpr[rS(ctx->opcode)];
2338
2339 tcg_gen_ext32s_tl(dst, src);
2340 tcg_gen_shli_tl(dst, dst, sh);
2341 if (unlikely(Rc(ctx->opcode) != 0)) {
2342 gen_set_Rc0(ctx, dst);
2343 }
2344 }
2345
2346 static void gen_extswsli0(DisasContext *ctx)
2347 {
2348 gen_extswsli(ctx, 0);
2349 }
2350
2351 static void gen_extswsli1(DisasContext *ctx)
2352 {
2353 gen_extswsli(ctx, 1);
2354 }
2355
2356 /* srd & srd. */
2357 static void gen_srd(DisasContext *ctx)
2358 {
2359 TCGv t0, t1;
2360
2361 t0 = tcg_temp_new();
2362 /* AND rS with a mask that is 0 when rB >= 0x40 */
2363 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2364 tcg_gen_sari_tl(t0, t0, 0x3f);
2365 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2366 t1 = tcg_temp_new();
2367 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2368 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2369 tcg_temp_free(t1);
2370 tcg_temp_free(t0);
2371 if (unlikely(Rc(ctx->opcode) != 0))
2372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2373 }
2374 #endif
2375
2376 /*** Addressing modes ***/
2377 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2378 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2379 target_long maskl)
2380 {
2381 target_long simm = SIMM(ctx->opcode);
2382
2383 simm &= ~maskl;
2384 if (rA(ctx->opcode) == 0) {
2385 if (NARROW_MODE(ctx)) {
2386 simm = (uint32_t)simm;
2387 }
2388 tcg_gen_movi_tl(EA, simm);
2389 } else if (likely(simm != 0)) {
2390 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2391 if (NARROW_MODE(ctx)) {
2392 tcg_gen_ext32u_tl(EA, EA);
2393 }
2394 } else {
2395 if (NARROW_MODE(ctx)) {
2396 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2397 } else {
2398 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2399 }
2400 }
2401 }
2402
2403 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2404 {
2405 if (rA(ctx->opcode) == 0) {
2406 if (NARROW_MODE(ctx)) {
2407 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2408 } else {
2409 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2410 }
2411 } else {
2412 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2413 if (NARROW_MODE(ctx)) {
2414 tcg_gen_ext32u_tl(EA, EA);
2415 }
2416 }
2417 }
2418
2419 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2420 {
2421 if (rA(ctx->opcode) == 0) {
2422 tcg_gen_movi_tl(EA, 0);
2423 } else if (NARROW_MODE(ctx)) {
2424 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2425 } else {
2426 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2427 }
2428 }
2429
2430 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2431 target_long val)
2432 {
2433 tcg_gen_addi_tl(ret, arg1, val);
2434 if (NARROW_MODE(ctx)) {
2435 tcg_gen_ext32u_tl(ret, ret);
2436 }
2437 }
2438
2439 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2440 {
2441 TCGLabel *l1 = gen_new_label();
2442 TCGv t0 = tcg_temp_new();
2443 TCGv_i32 t1, t2;
2444 tcg_gen_andi_tl(t0, EA, mask);
2445 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2446 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2447 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2448 gen_update_nip(ctx, ctx->nip - 4);
2449 gen_helper_raise_exception_err(cpu_env, t1, t2);
2450 tcg_temp_free_i32(t1);
2451 tcg_temp_free_i32(t2);
2452 gen_set_label(l1);
2453 tcg_temp_free(t0);
2454 }
2455
2456 static inline void gen_align_no_le(DisasContext *ctx)
2457 {
2458 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2459 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2460 }
2461
2462 /*** Integer load ***/
2463 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2464 {
2465 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2466 }
2467
2468 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2469 {
2470 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2471 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2472 }
2473
2474 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2475 {
2476 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2477 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2478 }
2479
2480 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2481 {
2482 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2483 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2484 }
2485
2486 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2487 {
2488 TCGv tmp = tcg_temp_new();
2489 gen_qemu_ld32u(ctx, tmp, addr);
2490 tcg_gen_extu_tl_i64(val, tmp);
2491 tcg_temp_free(tmp);
2492 }
2493
2494 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2495 {
2496 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2497 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2498 }
2499
2500 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2501 {
2502 TCGv tmp = tcg_temp_new();
2503 gen_qemu_ld32s(ctx, tmp, addr);
2504 tcg_gen_ext_tl_i64(val, tmp);
2505 tcg_temp_free(tmp);
2506 }
2507
2508 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2509 {
2510 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2511 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2512 }
2513
2514 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2515 {
2516 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2517 }
2518
2519 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2520 {
2521 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2522 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2523 }
2524
2525 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2526 {
2527 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2528 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2529 }
2530
2531 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2532 {
2533 TCGv tmp = tcg_temp_new();
2534 tcg_gen_trunc_i64_tl(tmp, val);
2535 gen_qemu_st32(ctx, tmp, addr);
2536 tcg_temp_free(tmp);
2537 }
2538
2539 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2540 {
2541 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2542 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2543 }
2544
2545 #define GEN_LD(name, ldop, opc, type) \
2546 static void glue(gen_, name)(DisasContext *ctx) \
2547 { \
2548 TCGv EA; \
2549 gen_set_access_type(ctx, ACCESS_INT); \
2550 EA = tcg_temp_new(); \
2551 gen_addr_imm_index(ctx, EA, 0); \
2552 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2553 tcg_temp_free(EA); \
2554 }
2555
2556 #define GEN_LDU(name, ldop, opc, type) \
2557 static void glue(gen_, name##u)(DisasContext *ctx) \
2558 { \
2559 TCGv EA; \
2560 if (unlikely(rA(ctx->opcode) == 0 || \
2561 rA(ctx->opcode) == rD(ctx->opcode))) { \
2562 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2563 return; \
2564 } \
2565 gen_set_access_type(ctx, ACCESS_INT); \
2566 EA = tcg_temp_new(); \
2567 if (type == PPC_64B) \
2568 gen_addr_imm_index(ctx, EA, 0x03); \
2569 else \
2570 gen_addr_imm_index(ctx, EA, 0); \
2571 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2572 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2573 tcg_temp_free(EA); \
2574 }
2575
2576 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2577 static void glue(gen_, name##ux)(DisasContext *ctx) \
2578 { \
2579 TCGv EA; \
2580 if (unlikely(rA(ctx->opcode) == 0 || \
2581 rA(ctx->opcode) == rD(ctx->opcode))) { \
2582 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2583 return; \
2584 } \
2585 gen_set_access_type(ctx, ACCESS_INT); \
2586 EA = tcg_temp_new(); \
2587 gen_addr_reg_index(ctx, EA); \
2588 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2589 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2590 tcg_temp_free(EA); \
2591 }
2592
2593 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2594 static void glue(gen_, name##x)(DisasContext *ctx) \
2595 { \
2596 TCGv EA; \
2597 chk; \
2598 gen_set_access_type(ctx, ACCESS_INT); \
2599 EA = tcg_temp_new(); \
2600 gen_addr_reg_index(ctx, EA); \
2601 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2602 tcg_temp_free(EA); \
2603 }
2604
2605 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2606 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2607
2608 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2609 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2610
2611 #define GEN_LDS(name, ldop, op, type) \
2612 GEN_LD(name, ldop, op | 0x20, type); \
2613 GEN_LDU(name, ldop, op | 0x21, type); \
2614 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2615 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2616
2617 /* lbz lbzu lbzux lbzx */
2618 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2619 /* lha lhau lhaux lhax */
2620 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2621 /* lhz lhzu lhzux lhzx */
2622 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2623 /* lwz lwzu lwzux lwzx */
2624 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2625 #if defined(TARGET_PPC64)
2626 /* lwaux */
2627 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2628 /* lwax */
2629 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2630 /* ldux */
2631 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2632 /* ldx */
2633 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2634
2635 /* CI load/store variants */
2636 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2637 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2638 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2639 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2640
2641 static void gen_ld(DisasContext *ctx)
2642 {
2643 TCGv EA;
2644 if (Rc(ctx->opcode)) {
2645 if (unlikely(rA(ctx->opcode) == 0 ||
2646 rA(ctx->opcode) == rD(ctx->opcode))) {
2647 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2648 return;
2649 }
2650 }
2651 gen_set_access_type(ctx, ACCESS_INT);
2652 EA = tcg_temp_new();
2653 gen_addr_imm_index(ctx, EA, 0x03);
2654 if (ctx->opcode & 0x02) {
2655 /* lwa (lwau is undefined) */
2656 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2657 } else {
2658 /* ld - ldu */
2659 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2660 }
2661 if (Rc(ctx->opcode))
2662 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2663 tcg_temp_free(EA);
2664 }
2665
2666 /* lq */
2667 static void gen_lq(DisasContext *ctx)
2668 {
2669 int ra, rd;
2670 TCGv EA;
2671
2672 /* lq is a legal user mode instruction starting in ISA 2.07 */
2673 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2674 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2675
2676 if (!legal_in_user_mode && ctx->pr) {
2677 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2678 return;
2679 }
2680
2681 if (!le_is_supported && ctx->le_mode) {
2682 gen_align_no_le(ctx);
2683 return;
2684 }
2685 ra = rA(ctx->opcode);
2686 rd = rD(ctx->opcode);
2687 if (unlikely((rd & 1) || rd == ra)) {
2688 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2689 return;
2690 }
2691
2692 gen_set_access_type(ctx, ACCESS_INT);
2693 EA = tcg_temp_new();
2694 gen_addr_imm_index(ctx, EA, 0x0F);
2695
2696 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2697 64-bit byteswap already. */
2698 if (unlikely(ctx->le_mode)) {
2699 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2700 gen_addr_add(ctx, EA, EA, 8);
2701 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2702 } else {
2703 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2704 gen_addr_add(ctx, EA, EA, 8);
2705 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2706 }
2707 tcg_temp_free(EA);
2708 }
2709 #endif
2710
2711 /*** Integer store ***/
2712 #define GEN_ST(name, stop, opc, type) \
2713 static void glue(gen_, name)(DisasContext *ctx) \
2714 { \
2715 TCGv EA; \
2716 gen_set_access_type(ctx, ACCESS_INT); \
2717 EA = tcg_temp_new(); \
2718 gen_addr_imm_index(ctx, EA, 0); \
2719 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2720 tcg_temp_free(EA); \
2721 }
2722
2723 #define GEN_STU(name, stop, opc, type) \
2724 static void glue(gen_, stop##u)(DisasContext *ctx) \
2725 { \
2726 TCGv EA; \
2727 if (unlikely(rA(ctx->opcode) == 0)) { \
2728 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2729 return; \
2730 } \
2731 gen_set_access_type(ctx, ACCESS_INT); \
2732 EA = tcg_temp_new(); \
2733 if (type == PPC_64B) \
2734 gen_addr_imm_index(ctx, EA, 0x03); \
2735 else \
2736 gen_addr_imm_index(ctx, EA, 0); \
2737 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2739 tcg_temp_free(EA); \
2740 }
2741
2742 #define GEN_STUX(name, stop, opc2, opc3, type) \
2743 static void glue(gen_, name##ux)(DisasContext *ctx) \
2744 { \
2745 TCGv EA; \
2746 if (unlikely(rA(ctx->opcode) == 0)) { \
2747 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2748 return; \
2749 } \
2750 gen_set_access_type(ctx, ACCESS_INT); \
2751 EA = tcg_temp_new(); \
2752 gen_addr_reg_index(ctx, EA); \
2753 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2754 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2755 tcg_temp_free(EA); \
2756 }
2757
2758 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2759 static void glue(gen_, name##x)(DisasContext *ctx) \
2760 { \
2761 TCGv EA; \
2762 chk; \
2763 gen_set_access_type(ctx, ACCESS_INT); \
2764 EA = tcg_temp_new(); \
2765 gen_addr_reg_index(ctx, EA); \
2766 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2767 tcg_temp_free(EA); \
2768 }
2769 #define GEN_STX(name, stop, opc2, opc3, type) \
2770 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2771
2772 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2773 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2774
2775 #define GEN_STS(name, stop, op, type) \
2776 GEN_ST(name, stop, op | 0x20, type); \
2777 GEN_STU(name, stop, op | 0x21, type); \
2778 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2779 GEN_STX(name, stop, 0x17, op | 0x00, type)
2780
2781 /* stb stbu stbux stbx */
2782 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2783 /* sth sthu sthux sthx */
2784 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2785 /* stw stwu stwux stwx */
2786 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2787 #if defined(TARGET_PPC64)
2788 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2789 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2790 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2791 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2792 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2793 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2794
2795 static void gen_std(DisasContext *ctx)
2796 {
2797 int rs;
2798 TCGv EA;
2799
2800 rs = rS(ctx->opcode);
2801 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2802 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2803 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2804
2805 if (!(ctx->insns_flags & PPC_64BX)) {
2806 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2807 }
2808
2809 if (!legal_in_user_mode && ctx->pr) {
2810 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2811 return;
2812 }
2813
2814 if (!le_is_supported && ctx->le_mode) {
2815 gen_align_no_le(ctx);
2816 return;
2817 }
2818
2819 if (unlikely(rs & 1)) {
2820 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2821 return;
2822 }
2823 gen_set_access_type(ctx, ACCESS_INT);
2824 EA = tcg_temp_new();
2825 gen_addr_imm_index(ctx, EA, 0x03);
2826
2827 /* We only need to swap high and low halves. gen_qemu_st64 does
2828 necessary 64-bit byteswap already. */
2829 if (unlikely(ctx->le_mode)) {
2830 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2831 gen_addr_add(ctx, EA, EA, 8);
2832 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2833 } else {
2834 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2835 gen_addr_add(ctx, EA, EA, 8);
2836 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2837 }
2838 tcg_temp_free(EA);
2839 } else {
2840 /* std / stdu*/
2841 if (Rc(ctx->opcode)) {
2842 if (unlikely(rA(ctx->opcode) == 0)) {
2843 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2844 return;
2845 }
2846 }
2847 gen_set_access_type(ctx, ACCESS_INT);
2848 EA = tcg_temp_new();
2849 gen_addr_imm_index(ctx, EA, 0x03);
2850 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2851 if (Rc(ctx->opcode))
2852 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2853 tcg_temp_free(EA);
2854 }
2855 }
2856 #endif
2857 /*** Integer load and store with byte reverse ***/
2858
2859 /* lhbrx */
2860 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2861 {
2862 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2863 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2864 }
2865 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2866
2867 /* lwbrx */
2868 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2869 {
2870 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2871 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2872 }
2873 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2874
2875 #if defined(TARGET_PPC64)
2876 /* ldbrx */
2877 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2878 {
2879 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2880 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2881 }
2882 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2883 #endif /* TARGET_PPC64 */
2884
2885 /* sthbrx */
2886 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2887 {
2888 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2889 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2890 }
2891 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2892
2893 /* stwbrx */
2894 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2895 {
2896 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2897 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2898 }
2899 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2900
2901 #if defined(TARGET_PPC64)
2902 /* stdbrx */
2903 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2904 {
2905 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2906 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2907 }
2908 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2909 #endif /* TARGET_PPC64 */
2910
2911 /*** Integer load and store multiple ***/
2912
2913 /* lmw */
2914 static void gen_lmw(DisasContext *ctx)
2915 {
2916 TCGv t0;
2917 TCGv_i32 t1;
2918
2919 if (ctx->le_mode) {
2920 gen_align_no_le(ctx);
2921 return;
2922 }
2923 gen_set_access_type(ctx, ACCESS_INT);
2924 t0 = tcg_temp_new();
2925 t1 = tcg_const_i32(rD(ctx->opcode));
2926 gen_addr_imm_index(ctx, t0, 0);
2927 gen_helper_lmw(cpu_env, t0, t1);
2928 tcg_temp_free(t0);
2929 tcg_temp_free_i32(t1);
2930 }
2931
2932 /* stmw */
2933 static void gen_stmw(DisasContext *ctx)
2934 {
2935 TCGv t0;
2936 TCGv_i32 t1;
2937
2938 if (ctx->le_mode) {
2939 gen_align_no_le(ctx);
2940 return;
2941 }
2942 gen_set_access_type(ctx, ACCESS_INT);
2943 t0 = tcg_temp_new();
2944 t1 = tcg_const_i32(rS(ctx->opcode));
2945 gen_addr_imm_index(ctx, t0, 0);
2946 gen_helper_stmw(cpu_env, t0, t1);
2947 tcg_temp_free(t0);
2948 tcg_temp_free_i32(t1);
2949 }
2950
2951 /*** Integer load and store strings ***/
2952
2953 /* lswi */
2954 /* PowerPC32 specification says we must generate an exception if
2955 * rA is in the range of registers to be loaded.
2956 * In an other hand, IBM says this is valid, but rA won't be loaded.
2957 * For now, I'll follow the spec...
2958 */
2959 static void gen_lswi(DisasContext *ctx)
2960 {
2961 TCGv t0;
2962 TCGv_i32 t1, t2;
2963 int nb = NB(ctx->opcode);
2964 int start = rD(ctx->opcode);
2965 int ra = rA(ctx->opcode);
2966 int nr;
2967
2968 if (ctx->le_mode) {
2969 gen_align_no_le(ctx);
2970 return;
2971 }
2972 if (nb == 0)
2973 nb = 32;
2974 nr = (nb + 3) / 4;
2975 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2977 return;
2978 }
2979 gen_set_access_type(ctx, ACCESS_INT);
2980 t0 = tcg_temp_new();
2981 gen_addr_register(ctx, t0);
2982 t1 = tcg_const_i32(nb);
2983 t2 = tcg_const_i32(start);
2984 gen_helper_lsw(cpu_env, t0, t1, t2);
2985 tcg_temp_free(t0);
2986 tcg_temp_free_i32(t1);
2987 tcg_temp_free_i32(t2);
2988 }
2989
2990 /* lswx */
2991 static void gen_lswx(DisasContext *ctx)
2992 {
2993 TCGv t0;
2994 TCGv_i32 t1, t2, t3;
2995
2996 if (ctx->le_mode) {
2997 gen_align_no_le(ctx);
2998 return;
2999 }
3000 gen_set_access_type(ctx, ACCESS_INT);
3001 t0 = tcg_temp_new();
3002 gen_addr_reg_index(ctx, t0);
3003 t1 = tcg_const_i32(rD(ctx->opcode));
3004 t2 = tcg_const_i32(rA(ctx->opcode));
3005 t3 = tcg_const_i32(rB(ctx->opcode));
3006 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3007 tcg_temp_free(t0);
3008 tcg_temp_free_i32(t1);
3009 tcg_temp_free_i32(t2);
3010 tcg_temp_free_i32(t3);
3011 }
3012
3013 /* stswi */
3014 static void gen_stswi(DisasContext *ctx)
3015 {
3016 TCGv t0;
3017 TCGv_i32 t1, t2;
3018 int nb = NB(ctx->opcode);
3019
3020 if (ctx->le_mode) {
3021 gen_align_no_le(ctx);
3022 return;
3023 }
3024 gen_set_access_type(ctx, ACCESS_INT);
3025 t0 = tcg_temp_new();
3026 gen_addr_register(ctx, t0);
3027 if (nb == 0)
3028 nb = 32;
3029 t1 = tcg_const_i32(nb);
3030 t2 = tcg_const_i32(rS(ctx->opcode));
3031 gen_helper_stsw(cpu_env, t0, t1, t2);
3032 tcg_temp_free(t0);
3033 tcg_temp_free_i32(t1);
3034 tcg_temp_free_i32(t2);
3035 }
3036
3037 /* stswx */
3038 static void gen_stswx(DisasContext *ctx)
3039 {
3040 TCGv t0;
3041 TCGv_i32 t1, t2;
3042
3043 if (ctx->le_mode) {
3044 gen_align_no_le(ctx);
3045 return;
3046 }
3047 gen_set_access_type(ctx, ACCESS_INT);
3048 t0 = tcg_temp_new();
3049 gen_addr_reg_index(ctx, t0);
3050 t1 = tcg_temp_new_i32();
3051 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3052 tcg_gen_andi_i32(t1, t1, 0x7F);
3053 t2 = tcg_const_i32(rS(ctx->opcode));
3054 gen_helper_stsw(cpu_env, t0, t1, t2);
3055 tcg_temp_free(t0);
3056 tcg_temp_free_i32(t1);
3057 tcg_temp_free_i32(t2);
3058 }
3059
3060 /*** Memory synchronisation ***/
3061 /* eieio */
3062 static void gen_eieio(DisasContext *ctx)
3063 {
3064 }
3065
3066 #if !defined(CONFIG_USER_ONLY)
3067 static inline void gen_check_tlb_flush(DisasContext *ctx)
3068 {
3069 TCGv_i32 t;
3070 TCGLabel *l;
3071
3072 if (!ctx->lazy_tlb_flush) {
3073 return;
3074 }
3075 l = gen_new_label();
3076 t = tcg_temp_new_i32();
3077 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3078 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3079 gen_helper_check_tlb_flush(cpu_env);
3080 gen_set_label(l);
3081 tcg_temp_free_i32(t);
3082 }
3083 #else
3084 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3085 #endif
3086
3087 /* isync */
3088 static void gen_isync(DisasContext *ctx)
3089 {
3090 /*
3091 * We need to check for a pending TLB flush. This can only happen in
3092 * kernel mode however so check MSR_PR
3093 */
3094 if (!ctx->pr) {
3095 gen_check_tlb_flush(ctx);
3096 }
3097 gen_stop_exception(ctx);
3098 }
3099
3100 #define LARX(name, len, loadop) \
3101 static void gen_##name(DisasContext *ctx) \
3102 { \
3103 TCGv t0; \
3104 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3105 gen_set_access_type(ctx, ACCESS_RES); \
3106 t0 = tcg_temp_local_new(); \
3107 gen_addr_reg_index(ctx, t0); \
3108 if ((len) > 1) { \
3109 gen_check_align(ctx, t0, (len)-1); \
3110 } \
3111 gen_qemu_##loadop(ctx, gpr, t0); \
3112 tcg_gen_mov_tl(cpu_reserve, t0); \
3113 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3114 tcg_temp_free(t0); \
3115 }
3116
3117 /* lwarx */
3118 LARX(lbarx, 1, ld8u);
3119 LARX(lharx, 2, ld16u);
3120 LARX(lwarx, 4, ld32u);
3121
3122
3123 #if defined(CONFIG_USER_ONLY)
3124 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3125 int reg, int size)
3126 {
3127 TCGv t0 = tcg_temp_new();
3128
3129 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3130 tcg_gen_movi_tl(t0, (size << 5) | reg);
3131 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3132 tcg_temp_free(t0);
3133 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3134 }
3135 #else
3136 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3137 int reg, int size)
3138 {
3139 TCGLabel *l1;
3140
3141 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3142 l1 = gen_new_label();
3143 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3144 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3145 #if defined(TARGET_PPC64)
3146 if (size == 8) {
3147 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3148 } else
3149 #endif
3150 if (size == 4) {
3151 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3152 } else if (size == 2) {
3153 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3154 #if defined(TARGET_PPC64)
3155 } else if (size == 16) {
3156 TCGv gpr1, gpr2 , EA8;
3157 if (unlikely(ctx->le_mode)) {
3158 gpr1 = cpu_gpr[reg+1];
3159 gpr2 = cpu_gpr[reg];
3160 } else {
3161 gpr1 = cpu_gpr[reg];
3162 gpr2 = cpu_gpr[reg+1];
3163 }
3164 gen_qemu_st64(ctx, gpr1, EA);
3165 EA8 = tcg_temp_local_new();
3166 gen_addr_add(ctx, EA8, EA, 8);
3167 gen_qemu_st64(ctx, gpr2, EA8);
3168 tcg_temp_free(EA8);
3169 #endif
3170 } else {
3171 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3172 }
3173 gen_set_label(l1);
3174 tcg_gen_movi_tl(cpu_reserve, -1);
3175 }
3176 #endif
3177
3178 #define STCX(name, len) \
3179 static void gen_##name(DisasContext *ctx) \
3180 { \
3181 TCGv t0; \
3182 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3183 gen_inval_exception(ctx, \
3184 POWERPC_EXCP_INVAL_INVAL); \
3185 return; \
3186 } \
3187 gen_set_access_type(ctx, ACCESS_RES); \
3188 t0 = tcg_temp_local_new(); \
3189 gen_addr_reg_index(ctx, t0); \
3190 if (len > 1) { \
3191 gen_check_align(ctx, t0, (len)-1); \
3192 } \
3193 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3194 tcg_temp_free(t0); \
3195 }
3196
3197 STCX(stbcx_, 1);
3198 STCX(sthcx_, 2);
3199 STCX(stwcx_, 4);
3200
3201 #if defined(TARGET_PPC64)
3202 /* ldarx */
3203 LARX(ldarx, 8, ld64);
3204
3205 /* lqarx */
3206 static void gen_lqarx(DisasContext *ctx)
3207 {
3208 TCGv EA;
3209 int rd = rD(ctx->opcode);
3210 TCGv gpr1, gpr2;
3211
3212 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3213 (rd == rB(ctx->opcode)))) {
3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3215 return;
3216 }
3217
3218 gen_set_access_type(ctx, ACCESS_RES);
3219 EA = tcg_temp_local_new();
3220 gen_addr_reg_index(ctx, EA);
3221 gen_check_align(ctx, EA, 15);
3222 if (unlikely(ctx->le_mode)) {
3223 gpr1 = cpu_gpr[rd+1];
3224 gpr2 = cpu_gpr[rd];
3225 } else {
3226 gpr1 = cpu_gpr[rd];
3227 gpr2 = cpu_gpr[rd+1];
3228 }
3229 gen_qemu_ld64(ctx, gpr1, EA);
3230 tcg_gen_mov_tl(cpu_reserve, EA);
3231
3232 gen_addr_add(ctx, EA, EA, 8);
3233 gen_qemu_ld64(ctx, gpr2, EA);
3234
3235 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3236 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3237
3238 tcg_temp_free(EA);
3239 }
3240
3241 /* stdcx. */
3242 STCX(stdcx_, 8);
3243 STCX(stqcx_, 16);
3244 #endif /* defined(TARGET_PPC64) */
3245
3246 /* sync */
3247 static void gen_sync(DisasContext *ctx)
3248 {
3249 uint32_t l = (ctx->opcode >> 21) & 3;
3250
3251 /*
3252 * We may need to check for a pending TLB flush.
3253 *
3254 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3255 *
3256 * Additionally, this can only happen in kernel mode however so
3257 * check MSR_PR as well.
3258 */
3259 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3260 gen_check_tlb_flush(ctx);
3261 }
3262 }
3263
3264 /* wait */
3265 static void gen_wait(DisasContext *ctx)
3266 {
3267 TCGv_i32 t0 = tcg_const_i32(1);
3268 tcg_gen_st_i32(t0, cpu_env,
3269 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3270 tcg_temp_free_i32(t0);
3271 /* Stop translation, as the CPU is supposed to sleep from now */
3272 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3273 }
3274
3275 #if defined(TARGET_PPC64)
3276 static void gen_doze(DisasContext *ctx)
3277 {
3278 #if defined(CONFIG_USER_ONLY)
3279 GEN_PRIV;
3280 #else
3281 TCGv_i32 t;
3282
3283 CHK_HV;
3284 t = tcg_const_i32(PPC_PM_DOZE);
3285 gen_helper_pminsn(cpu_env, t);
3286 tcg_temp_free_i32(t);
3287 gen_stop_exception(ctx);
3288 #endif /* defined(CONFIG_USER_ONLY) */
3289 }
3290
3291 static void gen_nap(DisasContext *ctx)
3292 {
3293 #if defined(CONFIG_USER_ONLY)
3294 GEN_PRIV;
3295 #else
3296 TCGv_i32 t;
3297
3298 CHK_HV;
3299 t = tcg_const_i32(PPC_PM_NAP);
3300 gen_helper_pminsn(cpu_env, t);
3301 tcg_temp_free_i32(t);
3302 gen_stop_exception(ctx);
3303 #endif /* defined(CONFIG_USER_ONLY) */
3304 }
3305
3306 static void gen_sleep(DisasContext *ctx)
3307 {
3308 #if defined(CONFIG_USER_ONLY)
3309 GEN_PRIV;
3310 #else
3311 TCGv_i32 t;
3312
3313 CHK_HV;
3314 t = tcg_const_i32(PPC_PM_SLEEP);
3315 gen_helper_pminsn(cpu_env, t);
3316 tcg_temp_free_i32(t);
3317 gen_stop_exception(ctx);
3318 #endif /* defined(CONFIG_USER_ONLY) */
3319 }
3320
3321 static void gen_rvwinkle(DisasContext *ctx)
3322 {
3323 #if defined(CONFIG_USER_ONLY)
3324 GEN_PRIV;
3325 #else
3326 TCGv_i32 t;
3327
3328 CHK_HV;
3329 t = tcg_const_i32(PPC_PM_RVWINKLE);
3330 gen_helper_pminsn(cpu_env, t);
3331 tcg_temp_free_i32(t);
3332 gen_stop_exception(ctx);
3333 #endif /* defined(CONFIG_USER_ONLY) */
3334 }
3335 #endif /* #if defined(TARGET_PPC64) */
3336
3337 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3338 {
3339 #if defined(TARGET_PPC64)
3340 if (ctx->has_cfar)
3341 tcg_gen_movi_tl(cpu_cfar, nip);
3342 #endif
3343 }
3344
3345 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3346 {
3347 if (unlikely(ctx->singlestep_enabled)) {
3348 return false;
3349 }
3350
3351 #ifndef CONFIG_USER_ONLY
3352 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3353 #else
3354 return true;
3355 #endif
3356 }
3357
3358 /*** Branch ***/
3359 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3360 {
3361 if (NARROW_MODE(ctx)) {
3362 dest = (uint32_t) dest;
3363 }
3364 if (use_goto_tb(ctx, dest)) {
3365 tcg_gen_goto_tb(n);
3366 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3367 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3368 } else {
3369 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3370 if (unlikely(ctx->singlestep_enabled)) {
3371 if ((ctx->singlestep_enabled &
3372 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3373 (ctx->exception == POWERPC_EXCP_BRANCH ||
3374 ctx->exception == POWERPC_EXCP_TRACE)) {
3375 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3376 }
3377 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3378 gen_debug_exception(ctx);
3379 }
3380 }
3381 tcg_gen_exit_tb(0);
3382 }
3383 }
3384
3385 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3386 {
3387 if (NARROW_MODE(ctx)) {
3388 nip = (uint32_t)nip;
3389 }
3390 tcg_gen_movi_tl(cpu_lr, nip);
3391 }
3392
3393 /* b ba bl bla */
3394 static void gen_b(DisasContext *ctx)
3395 {
3396 target_ulong li, target;
3397
3398 ctx->exception = POWERPC_EXCP_BRANCH;
3399 /* sign extend LI */
3400 li = LI(ctx->opcode);
3401 li = (li ^ 0x02000000) - 0x02000000;
3402 if (likely(AA(ctx->opcode) == 0)) {
3403 target = ctx->nip + li - 4;
3404 } else {
3405 target = li;
3406 }
3407 if (LK(ctx->opcode)) {
3408 gen_setlr(ctx, ctx->nip);
3409 }
3410 gen_update_cfar(ctx, ctx->nip - 4);
3411 gen_goto_tb(ctx, 0, target);
3412 }
3413
3414 #define BCOND_IM 0
3415 #define BCOND_LR 1
3416 #define BCOND_CTR 2
3417 #define BCOND_TAR 3
3418
3419 static inline void gen_bcond(DisasContext *ctx, int type)
3420 {
3421 uint32_t bo = BO(ctx->opcode);
3422 TCGLabel *l1;
3423 TCGv target;
3424
3425 ctx->exception = POWERPC_EXCP_BRANCH;
3426 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3427 target = tcg_temp_local_new();
3428 if (type == BCOND_CTR)
3429 tcg_gen_mov_tl(target, cpu_ctr);
3430 else if (type == BCOND_TAR)
3431 gen_load_spr(target, SPR_TAR);
3432 else
3433 tcg_gen_mov_tl(target, cpu_lr);
3434 } else {
3435 TCGV_UNUSED(target);
3436 }
3437 if (LK(ctx->opcode))
3438 gen_setlr(ctx, ctx->nip);
3439 l1 = gen_new_label();
3440 if ((bo & 0x4) == 0) {
3441 /* Decrement and test CTR */
3442 TCGv temp = tcg_temp_new();
3443 if (unlikely(type == BCOND_CTR)) {
3444 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3445 return;
3446 }
3447 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3448 if (NARROW_MODE(ctx)) {
3449 tcg_gen_ext32u_tl(temp, cpu_ctr);
3450 } else {
3451 tcg_gen_mov_tl(temp, cpu_ctr);
3452 }
3453 if (bo & 0x2) {
3454 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3455 } else {
3456 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3457 }
3458 tcg_temp_free(temp);
3459 }
3460 if ((bo & 0x10) == 0) {
3461 /* Test CR */
3462 uint32_t bi = BI(ctx->opcode);
3463 uint32_t mask = 0x08 >> (bi & 0x03);
3464 TCGv_i32 temp = tcg_temp_new_i32();
3465
3466 if (bo & 0x8) {
3467 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3468 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3469 } else {
3470 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3471 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3472 }
3473 tcg_temp_free_i32(temp);
3474 }
3475 gen_update_cfar(ctx, ctx->nip - 4);
3476 if (type == BCOND_IM) {
3477 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3478 if (likely(AA(ctx->opcode) == 0)) {
3479 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3480 } else {
3481 gen_goto_tb(ctx, 0, li);
3482 }
3483 if ((bo & 0x14) != 0x14) {
3484 gen_set_label(l1);
3485 gen_goto_tb(ctx, 1, ctx->nip);
3486 }
3487 } else {
3488 if (NARROW_MODE(ctx)) {
3489 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3490 } else {
3491 tcg_gen_andi_tl(cpu_nip, target, ~3);
3492 }
3493 tcg_gen_exit_tb(0);
3494 if ((bo & 0x14) != 0x14) {
3495 gen_set_label(l1);
3496 gen_update_nip(ctx, ctx->nip);
3497 tcg_gen_exit_tb(0);
3498 }
3499 }
3500 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3501 tcg_temp_free(target);
3502 }
3503 }
3504
3505 static void gen_bc(DisasContext *ctx)
3506 {
3507 gen_bcond(ctx, BCOND_IM);
3508 }
3509
3510 static void gen_bcctr(DisasContext *ctx)
3511 {
3512 gen_bcond(ctx, BCOND_CTR);
3513 }
3514
3515 static void gen_bclr(DisasContext *ctx)
3516 {
3517 gen_bcond(ctx, BCOND_LR);
3518 }
3519
3520 static void gen_bctar(DisasContext *ctx)
3521 {
3522 gen_bcond(ctx, BCOND_TAR);
3523 }
3524
3525 /*** Condition register logical ***/
3526 #define GEN_CRLOGIC(name, tcg_op, opc) \
3527 static void glue(gen_, name)(DisasContext *ctx) \
3528 { \
3529 uint8_t bitmask; \
3530 int sh; \
3531 TCGv_i32 t0, t1; \
3532 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3533 t0 = tcg_temp_new_i32(); \
3534 if (sh > 0) \
3535 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3536 else if (sh < 0) \
3537 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3538 else \
3539 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3540 t1 = tcg_temp_new_i32(); \
3541 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3542 if (sh > 0) \
3543 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3544 else if (sh < 0) \
3545 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3546 else \
3547 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3548 tcg_op(t0, t0, t1); \
3549 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3550 tcg_gen_andi_i32(t0, t0, bitmask); \
3551 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3552 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3553 tcg_temp_free_i32(t0); \
3554 tcg_temp_free_i32(t1); \
3555 }
3556
3557 /* crand */
3558 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3559 /* crandc */
3560 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3561 /* creqv */
3562 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3563 /* crnand */
3564 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3565 /* crnor */
3566 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3567 /* cror */
3568 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3569 /* crorc */
3570 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3571 /* crxor */
3572 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3573
3574 /* mcrf */
3575 static void gen_mcrf(DisasContext *ctx)
3576 {
3577 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3578 }
3579
3580 /*** System linkage ***/
3581
3582 /* rfi (supervisor only) */
3583 static void gen_rfi(DisasContext *ctx)
3584 {
3585 #if defined(CONFIG_USER_ONLY)
3586 GEN_PRIV;
3587 #else
3588 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3589 * processors compliant with arch 2.x, we should remove it there,
3590 * but we need to fix OpenBIOS not to use it on 970 first
3591 */
3592 /* Restore CPU state */
3593 CHK_SV;
3594 gen_update_cfar(ctx, ctx->nip - 4);
3595 gen_helper_rfi(cpu_env);
3596 gen_sync_exception(ctx);
3597 #endif
3598 }
3599
3600 #if defined(TARGET_PPC64)
3601 static void gen_rfid(DisasContext *ctx)
3602 {
3603 #if defined(CONFIG_USER_ONLY)
3604 GEN_PRIV;
3605 #else
3606 /* Restore CPU state */
3607 CHK_SV;
3608 gen_update_cfar(ctx, ctx->nip - 4);
3609 gen_helper_rfid(cpu_env);
3610 gen_sync_exception(ctx);
3611 #endif
3612 }
3613
3614 static void gen_hrfid(DisasContext *ctx)
3615 {
3616 #if defined(CONFIG_USER_ONLY)
3617 GEN_PRIV;
3618 #else
3619 /* Restore CPU state */
3620 CHK_HV;
3621 gen_helper_hrfid(cpu_env);
3622 gen_sync_exception(ctx);
3623 #endif
3624 }
3625 #endif
3626
3627 /* sc */
3628 #if defined(CONFIG_USER_ONLY)
3629 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3630 #else
3631 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3632 #endif
3633 static void gen_sc(DisasContext *ctx)
3634 {
3635 uint32_t lev;
3636
3637 lev = (ctx->opcode >> 5) & 0x7F;
3638 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3639 }
3640
3641 /*** Trap ***/
3642
3643 /* Check for unconditional traps (always or never) */
3644 static bool check_unconditional_trap(DisasContext *ctx)
3645 {
3646 /* Trap never */
3647 if (TO(ctx->opcode) == 0) {
3648 return true;
3649 }
3650 /* Trap always */
3651 if (TO(ctx->opcode) == 31) {
3652 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3653 return true;
3654 }
3655 return false;
3656 }
3657
3658 /* tw */
3659 static void gen_tw(DisasContext *ctx)
3660 {
3661 TCGv_i32 t0;
3662
3663 if (check_unconditional_trap(ctx)) {
3664 return;
3665 }
3666 t0 = tcg_const_i32(TO(ctx->opcode));
3667 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3668 t0);
3669 tcg_temp_free_i32(t0);
3670 }
3671
3672 /* twi */
3673 static void gen_twi(DisasContext *ctx)
3674 {
3675 TCGv t0;
3676 TCGv_i32 t1;
3677
3678 if (check_unconditional_trap(ctx)) {
3679 return;
3680 }
3681 t0 = tcg_const_tl(SIMM(ctx->opcode));
3682 t1 = tcg_const_i32(TO(ctx->opcode));
3683 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3684 tcg_temp_free(t0);
3685 tcg_temp_free_i32(t1);
3686 }
3687
3688 #if defined(TARGET_PPC64)
3689 /* td */
3690 static void gen_td(DisasContext *ctx)
3691 {
3692 TCGv_i32 t0;
3693
3694 if (check_unconditional_trap(ctx)) {
3695 return;
3696 }
3697 t0 = tcg_const_i32(TO(ctx->opcode));
3698 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3699 t0);
3700 tcg_temp_free_i32(t0);
3701 }
3702
3703 /* tdi */
3704 static void gen_tdi(DisasContext *ctx)
3705 {
3706 TCGv t0;
3707 TCGv_i32 t1;
3708
3709 if (check_unconditional_trap(ctx)) {
3710 return;
3711 }
3712 t0 = tcg_const_tl(SIMM(ctx->opcode));
3713 t1 = tcg_const_i32(TO(ctx->opcode));
3714 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3715 tcg_temp_free(t0);
3716 tcg_temp_free_i32(t1);
3717 }
3718 #endif
3719
3720 /*** Processor control ***/
3721
3722 static void gen_read_xer(TCGv dst)
3723 {
3724 TCGv t0 = tcg_temp_new();
3725 TCGv t1 = tcg_temp_new();
3726 TCGv t2 = tcg_temp_new();
3727 tcg_gen_mov_tl(dst, cpu_xer);
3728 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3729 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3730 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3731 tcg_gen_or_tl(t0, t0, t1);
3732 tcg_gen_or_tl(dst, dst, t2);
3733 tcg_gen_or_tl(dst, dst, t0);
3734 tcg_temp_free(t0);
3735 tcg_temp_free(t1);
3736 tcg_temp_free(t2);
3737 }
3738
3739 static void gen_write_xer(TCGv src)
3740 {
3741 tcg_gen_andi_tl(cpu_xer, src,
3742 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3743 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3744 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3745 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3746 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3747 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3748 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3749 }
3750
3751 /* mcrxr */
3752 static void gen_mcrxr(DisasContext *ctx)
3753 {
3754 TCGv_i32 t0 = tcg_temp_new_i32();
3755 TCGv_i32 t1 = tcg_temp_new_i32();
3756 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3757
3758 tcg_gen_trunc_tl_i32(t0, cpu_so);
3759 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3760 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3761 tcg_gen_shli_i32(t0, t0, 3);
3762 tcg_gen_shli_i32(t1, t1, 2);
3763 tcg_gen_shli_i32(dst, dst, 1);
3764 tcg_gen_or_i32(dst, dst, t0);
3765 tcg_gen_or_i32(dst, dst, t1);
3766 tcg_temp_free_i32(t0);
3767 tcg_temp_free_i32(t1);
3768
3769 tcg_gen_movi_tl(cpu_so, 0);
3770 tcg_gen_movi_tl(cpu_ov, 0);
3771 tcg_gen_movi_tl(cpu_ca, 0);
3772 }
3773
3774 /* mfcr mfocrf */
3775 static void gen_mfcr(DisasContext *ctx)
3776 {
3777 uint32_t crm, crn;
3778
3779 if (likely(ctx->opcode & 0x00100000)) {
3780 crm = CRM(ctx->opcode);
3781 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3782 crn = ctz32 (crm);
3783 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3784 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3785 cpu_gpr[rD(ctx->opcode)], crn * 4);
3786 }
3787 } else {
3788 TCGv_i32 t0 = tcg_temp_new_i32();
3789 tcg_gen_mov_i32(t0, cpu_crf[0]);
3790 tcg_gen_shli_i32(t0, t0, 4);
3791 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3792 tcg_gen_shli_i32(t0, t0, 4);
3793 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3794 tcg_gen_shli_i32(t0, t0, 4);
3795 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3796 tcg_gen_shli_i32(t0, t0, 4);
3797 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3798 tcg_gen_shli_i32(t0, t0, 4);
3799 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3800 tcg_gen_shli_i32(t0, t0, 4);
3801 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3802 tcg_gen_shli_i32(t0, t0, 4);
3803 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3804 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3805 tcg_temp_free_i32(t0);
3806 }
3807 }
3808
3809 /* mfmsr */
3810 static void gen_mfmsr(DisasContext *ctx)
3811 {
3812 CHK_SV;
3813 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3814 }
3815
3816 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3817 {
3818 #if 0
3819 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3820 printf("ERROR: try to access SPR %d !\n", sprn);
3821 #endif
3822 }
3823 #define SPR_NOACCESS (&spr_noaccess)
3824
3825 /* mfspr */
3826 static inline void gen_op_mfspr(DisasContext *ctx)
3827 {
3828 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3829 uint32_t sprn = SPR(ctx->opcode);
3830
3831 #if defined(CONFIG_USER_ONLY)
3832 read_cb = ctx->spr_cb[sprn].uea_read;
3833 #else
3834 if (ctx->pr) {
3835 read_cb = ctx->spr_cb[sprn].uea_read;
3836 } else if (ctx->hv) {
3837 read_cb = ctx->spr_cb[sprn].hea_read;
3838 } else {
3839 read_cb = ctx->spr_cb[sprn].oea_read;
3840 }
3841 #endif
3842 if (likely(read_cb != NULL)) {
3843 if (likely(read_cb != SPR_NOACCESS)) {
3844 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3845 } else {
3846 /* Privilege exception */
3847 /* This is a hack to avoid warnings when running Linux:
3848 * this OS breaks the PowerPC virtualisation model,
3849 * allowing userland application to read the PVR
3850 */
3851 if (sprn != SPR_PVR) {
3852 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3853 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3854 if (qemu_log_separate()) {
3855 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3856 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3857 }
3858 }
3859 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3860 }
3861 } else {
3862 /* ISA 2.07 defines these as no-ops */
3863 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3864 (sprn >= 808 && sprn <= 811)) {
3865 /* This is a nop */
3866 return;
3867 }
3868 /* Not defined */
3869 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3870 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3871 if (qemu_log_separate()) {
3872 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3873 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3874 }
3875
3876 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3877 * it can generate a priv, a hv emu or a no-op
3878 */
3879 if (sprn & 0x10) {
3880 if (ctx->pr) {
3881 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3882 }
3883 } else {
3884 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3885 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3886 }
3887 }
3888 }
3889 }
3890
3891 static void gen_mfspr(DisasContext *ctx)
3892 {
3893 gen_op_mfspr(ctx);
3894 }
3895
3896 /* mftb */
3897 static void gen_mftb(DisasContext *ctx)
3898 {
3899 gen_op_mfspr(ctx);
3900 }
3901
3902 /* mtcrf mtocrf*/
3903 static void gen_mtcrf(DisasContext *ctx)
3904 {
3905 uint32_t crm, crn;
3906
3907 crm = CRM(ctx->opcode);
3908 if (likely((ctx->opcode & 0x00100000))) {
3909 if (crm && ((crm & (crm - 1)) == 0)) {
3910 TCGv_i32 temp = tcg_temp_new_i32();
3911 crn = ctz32 (crm);
3912 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3913 tcg_gen_shri_i32(temp, temp, crn * 4);
3914 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3915 tcg_temp_free_i32(temp);
3916 }
3917 } else {
3918 TCGv_i32 temp = tcg_temp_new_i32();
3919 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3920 for (crn = 0 ; crn < 8 ; crn++) {
3921 if (crm & (1 << crn)) {
3922 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3923 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3924 }
3925 }
3926 tcg_temp_free_i32(temp);
3927 }
3928 }
3929
3930 /* mtmsr */
3931 #if defined(TARGET_PPC64)
3932 static void gen_mtmsrd(DisasContext *ctx)
3933 {
3934 CHK_SV;
3935
3936 #if !defined(CONFIG_USER_ONLY)
3937 if (ctx->opcode & 0x00010000) {
3938 /* Special form that does not need any synchronisation */
3939 TCGv t0 = tcg_temp_new();
3940 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3941 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3942 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3943 tcg_temp_free(t0);
3944 } else {
3945 /* XXX: we need to update nip before the store
3946 * if we enter power saving mode, we will exit the loop
3947 * directly from ppc_store_msr
3948 */
3949 gen_update_nip(ctx, ctx->nip);
3950 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3951 /* Must stop the translation as machine state (may have) changed */
3952 /* Note that mtmsr is not always defined as context-synchronizing */
3953 gen_stop_exception(ctx);
3954 }
3955 #endif /* !defined(CONFIG_USER_ONLY) */
3956 }
3957 #endif /* defined(TARGET_PPC64) */
3958
3959 static void gen_mtmsr(DisasContext *ctx)
3960 {
3961 CHK_SV;
3962
3963 #if !defined(CONFIG_USER_ONLY)
3964 if (ctx->opcode & 0x00010000) {
3965 /* Special form that does not need any synchronisation */
3966 TCGv t0 = tcg_temp_new();
3967 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3968 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3969 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3970 tcg_temp_free(t0);
3971 } else {
3972 TCGv msr = tcg_temp_new();
3973
3974 /* XXX: we need to update nip before the store
3975 * if we enter power saving mode, we will exit the loop
3976 * directly from ppc_store_msr
3977 */
3978 gen_update_nip(ctx, ctx->nip);
3979 #if defined(TARGET_PPC64)
3980 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3981 #else
3982 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3983 #endif
3984 gen_helper_store_msr(cpu_env, msr);
3985 tcg_temp_free(msr);
3986 /* Must stop the translation as machine state (may have) changed */
3987 /* Note that mtmsr is not always defined as context-synchronizing */
3988 gen_stop_exception(ctx);
3989 }
3990 #endif
3991 }
3992
3993 /* mtspr */
3994 static void gen_mtspr(DisasContext *ctx)
3995 {
3996 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3997 uint32_t sprn = SPR(ctx->opcode);
3998
3999 #if defined(CONFIG_USER_ONLY)
4000 write_cb = ctx->spr_cb[sprn].uea_write;
4001 #else
4002 if (ctx->pr) {
4003 write_cb = ctx->spr_cb[sprn].uea_write;
4004 } else if (ctx->hv) {
4005 write_cb = ctx->spr_cb[sprn].hea_write;
4006 } else {
4007 write_cb = ctx->spr_cb[sprn].oea_write;
4008 }
4009 #endif
4010 if (likely(write_cb != NULL)) {
4011 if (likely(write_cb != SPR_NOACCESS)) {
4012 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4013 } else {
4014 /* Privilege exception */
4015 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4016 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4017 if (qemu_log_separate()) {
4018 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4019 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4020 }
4021 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4022 }
4023 } else {
4024 /* ISA 2.07 defines these as no-ops */
4025 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4026 (sprn >= 808 && sprn <= 811)) {
4027 /* This is a nop */
4028 return;
4029 }
4030
4031 /* Not defined */
4032 if (qemu_log_separate()) {
4033 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4034 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4035 }
4036 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4037 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4038
4039
4040 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4041 * it can generate a priv, a hv emu or a no-op
4042 */
4043 if (sprn & 0x10) {
4044 if (ctx->pr) {
4045 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4046 }
4047 } else {
4048 if (ctx->pr || sprn == 0) {
4049 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4050 }
4051 }
4052 }
4053 }
4054
4055 #if defined(TARGET_PPC64)
4056 /* setb */
4057 static void gen_setb(DisasContext *ctx)
4058 {
4059 TCGv_i32 t0 = tcg_temp_new_i32();
4060 TCGv_i32 t8 = tcg_temp_new_i32();
4061 TCGv_i32 tm1 = tcg_temp_new_i32();
4062 int crf = crfS(ctx->opcode);
4063
4064 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4065 tcg_gen_movi_i32(t8, 8);
4066 tcg_gen_movi_i32(tm1, -1);
4067 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4068 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4069
4070 tcg_temp_free_i32(t0);
4071 tcg_temp_free_i32(t8);
4072 tcg_temp_free_i32(tm1);
4073 }
4074 #endif
4075
4076 /*** Cache management ***/
4077
4078 /* dcbf */
4079 static void gen_dcbf(DisasContext *ctx)
4080 {
4081 /* XXX: specification says this is treated as a load by the MMU */
4082 TCGv t0;
4083 gen_set_access_type(ctx, ACCESS_CACHE);
4084 t0 = tcg_temp_new();
4085 gen_addr_reg_index(ctx, t0);
4086 gen_qemu_ld8u(ctx, t0, t0);
4087 tcg_temp_free(t0);
4088 }
4089
4090 /* dcbi (Supervisor only) */
4091 static void gen_dcbi(DisasContext *ctx)
4092 {
4093 #if defined(CONFIG_USER_ONLY)
4094 GEN_PRIV;
4095 #else
4096 TCGv EA, val;
4097
4098 CHK_SV;
4099 EA = tcg_temp_new();
4100 gen_set_access_type(ctx, ACCESS_CACHE);
4101 gen_addr_reg_index(ctx, EA);
4102 val = tcg_temp_new();
4103 /* XXX: specification says this should be treated as a store by the MMU */
4104 gen_qemu_ld8u(ctx, val, EA);
4105 gen_qemu_st8(ctx, val, EA);
4106 tcg_temp_free(val);
4107 tcg_temp_free(EA);
4108 #endif /* defined(CONFIG_USER_ONLY) */
4109 }
4110
4111 /* dcdst */
4112 static void gen_dcbst(DisasContext *ctx)
4113 {
4114 /* XXX: specification say this is treated as a load by the MMU */
4115 TCGv t0;
4116 gen_set_access_type(ctx, ACCESS_CACHE);
4117 t0 = tcg_temp_new();
4118 gen_addr_reg_index(ctx, t0);
4119 gen_qemu_ld8u(ctx, t0, t0);
4120 tcg_temp_free(t0);
4121 }
4122
4123 /* dcbt */
4124 static void gen_dcbt(DisasContext *ctx)
4125 {
4126 /* interpreted as no-op */
4127 /* XXX: specification say this is treated as a load by the MMU
4128 * but does not generate any exception
4129 */
4130 }
4131
4132 /* dcbtst */
4133 static void gen_dcbtst(DisasContext *ctx)
4134 {
4135 /* interpreted as no-op */
4136 /* XXX: specification say this is treated as a load by the MMU
4137 * but does not generate any exception
4138 */
4139 }
4140
4141 /* dcbtls */
4142 static void gen_dcbtls(DisasContext *ctx)
4143 {
4144 /* Always fails locking the cache */
4145 TCGv t0 = tcg_temp_new();
4146 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4147 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4148 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4149 tcg_temp_free(t0);
4150 }
4151
4152 /* dcbz */
4153 static void gen_dcbz(DisasContext *ctx)
4154 {
4155 TCGv tcgv_addr;
4156 TCGv_i32 tcgv_op;
4157
4158 gen_set_access_type(ctx, ACCESS_CACHE);
4159 tcgv_addr = tcg_temp_new();
4160 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4161 gen_addr_reg_index(ctx, tcgv_addr);
4162 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4163 tcg_temp_free(tcgv_addr);
4164 tcg_temp_free_i32(tcgv_op);
4165 }
4166
4167 /* dst / dstt */
4168 static void gen_dst(DisasContext *ctx)
4169 {
4170 if (rA(ctx->opcode) == 0) {
4171 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4172 } else {
4173 /* interpreted as no-op */
4174 }
4175 }
4176
4177 /* dstst /dststt */
4178 static void gen_dstst(DisasContext *ctx)
4179 {
4180 if (rA(ctx->opcode) == 0) {
4181 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4182 } else {
4183 /* interpreted as no-op */
4184 }
4185
4186 }
4187
4188 /* dss / dssall */
4189 static void gen_dss(DisasContext *ctx)
4190 {
4191 /* interpreted as no-op */
4192 }
4193
4194 /* icbi */
4195 static void gen_icbi(DisasContext *ctx)
4196 {
4197 TCGv t0;
4198 gen_set_access_type(ctx, ACCESS_CACHE);
4199 t0 = tcg_temp_new();
4200 gen_addr_reg_index(ctx, t0);
4201 gen_helper_icbi(cpu_env, t0);
4202 tcg_temp_free(t0);
4203 }
4204
4205 /* Optional: */
4206 /* dcba */
4207 static void gen_dcba(DisasContext *ctx)
4208 {
4209 /* interpreted as no-op */
4210 /* XXX: specification say this is treated as a store by the MMU
4211 * but does not generate any exception
4212 */
4213 }
4214
4215 /*** Segment register manipulation ***/
4216 /* Supervisor only: */
4217
4218 /* mfsr */
4219 static void gen_mfsr(DisasContext *ctx)
4220 {
4221 #if defined(CONFIG_USER_ONLY)
4222 GEN_PRIV;
4223 #else
4224 TCGv t0;
4225
4226 CHK_SV;
4227 t0 = tcg_const_tl(SR(ctx->opcode));
4228 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4229 tcg_temp_free(t0);
4230 #endif /* defined(CONFIG_USER_ONLY) */
4231 }
4232
4233 /* mfsrin */
4234 static void gen_mfsrin(DisasContext *ctx)
4235 {
4236 #if defined(CONFIG_USER_ONLY)
4237 GEN_PRIV;
4238 #else
4239 TCGv t0;
4240
4241 CHK_SV;
4242 t0 = tcg_temp_new();
4243 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4244 tcg_gen_andi_tl(t0, t0, 0xF);
4245 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4246 tcg_temp_free(t0);
4247 #endif /* defined(CONFIG_USER_ONLY) */
4248 }
4249
4250 /* mtsr */
4251 static void gen_mtsr(DisasContext *ctx)
4252 {
4253 #if defined(CONFIG_USER_ONLY)
4254 GEN_PRIV;
4255 #else
4256 TCGv t0;
4257
4258 CHK_SV;
4259 t0 = tcg_const_tl(SR(ctx->opcode));
4260 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4261 tcg_temp_free(t0);
4262 #endif /* defined(CONFIG_USER_ONLY) */
4263 }
4264
4265 /* mtsrin */
4266 static void gen_mtsrin(DisasContext *ctx)
4267 {
4268 #if defined(CONFIG_USER_ONLY)
4269 GEN_PRIV;
4270 #else
4271 TCGv t0;
4272 CHK_SV;
4273
4274 t0 = tcg_temp_new();
4275 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4276 tcg_gen_andi_tl(t0, t0, 0xF);
4277 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4278 tcg_temp_free(t0);
4279 #endif /* defined(CONFIG_USER_ONLY) */
4280 }
4281
4282 #if defined(TARGET_PPC64)
4283 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4284
4285 /* mfsr */
4286 static void gen_mfsr_64b(DisasContext *ctx)
4287 {
4288 #if defined(CONFIG_USER_ONLY)
4289 GEN_PRIV;
4290 #else
4291 TCGv t0;
4292
4293 CHK_SV;
4294 t0 = tcg_const_tl(SR(ctx->opcode));
4295 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4296 tcg_temp_free(t0);
4297 #endif /* defined(CONFIG_USER_ONLY) */
4298 }
4299
4300 /* mfsrin */
4301 static void gen_mfsrin_64b(DisasContext *ctx)
4302 {
4303 #if defined(CONFIG_USER_ONLY)
4304 GEN_PRIV;
4305 #else
4306 TCGv t0;
4307
4308 CHK_SV;
4309 t0 = tcg_temp_new();
4310 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4311 tcg_gen_andi_tl(t0, t0, 0xF);
4312 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4313 tcg_temp_free(t0);
4314 #endif /* defined(CONFIG_USER_ONLY) */
4315 }
4316
4317 /* mtsr */
4318 static void gen_mtsr_64b(DisasContext *ctx)
4319 {
4320 #if defined(CONFIG_USER_ONLY)
4321 GEN_PRIV;
4322 #else
4323 TCGv t0;
4324
4325 CHK_SV;
4326 t0 = tcg_const_tl(SR(ctx->opcode));
4327 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4328 tcg_temp_free(t0);
4329 #endif /* defined(CONFIG_USER_ONLY) */
4330 }
4331
4332 /* mtsrin */
4333 static void gen_mtsrin_64b(DisasContext *ctx)
4334 {
4335 #if defined(CONFIG_USER_ONLY)
4336 GEN_PRIV;
4337 #else
4338 TCGv t0;
4339
4340 CHK_SV;
4341 t0 = tcg_temp_new();
4342 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4343 tcg_gen_andi_tl(t0, t0, 0xF);
4344 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4345 tcg_temp_free(t0);
4346 #endif /* defined(CONFIG_USER_ONLY) */
4347 }
4348
4349 /* slbmte */
4350 static void gen_slbmte(DisasContext *ctx)
4351 {
4352 #if defined(CONFIG_USER_ONLY)
4353 GEN_PRIV;
4354 #else
4355 CHK_SV;
4356
4357 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4358 cpu_gpr[rS(ctx->opcode)]);
4359 #endif /* defined(CONFIG_USER_ONLY) */
4360 }
4361
4362 static void gen_slbmfee(DisasContext *ctx)
4363 {
4364 #if defined(CONFIG_USER_ONLY)
4365 GEN_PRIV;
4366 #else
4367 CHK_SV;
4368
4369 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4370 cpu_gpr[rB(ctx->opcode)]);
4371 #endif /* defined(CONFIG_USER_ONLY) */
4372 }
4373
4374 static void gen_slbmfev(DisasContext *ctx)
4375 {
4376 #if defined(CONFIG_USER_ONLY)
4377 GEN_PRIV;
4378 #else
4379 CHK_SV;
4380
4381 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4382 cpu_gpr[rB(ctx->opcode)]);
4383 #endif /* defined(CONFIG_USER_ONLY) */
4384 }
4385
4386 static void gen_slbfee_(DisasContext *ctx)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4390 #else
4391 TCGLabel *l1, *l2;
4392
4393 if (unlikely(ctx->pr)) {
4394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4395 return;
4396 }
4397 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4398 cpu_gpr[rB(ctx->opcode)]);
4399 l1 = gen_new_label();
4400 l2 = gen_new_label();
4401 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4402 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4403 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4404 tcg_gen_br(l2);
4405 gen_set_label(l1);
4406 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4407 gen_set_label(l2);
4408 #endif
4409 }
4410 #endif /* defined(TARGET_PPC64) */
4411
4412 /*** Lookaside buffer management ***/
4413 /* Optional & supervisor only: */
4414
4415 /* tlbia */
4416 static void gen_tlbia(DisasContext *ctx)
4417 {
4418 #if defined(CONFIG_USER_ONLY)
4419 GEN_PRIV;
4420 #else
4421 CHK_HV;
4422
4423 gen_helper_tlbia(cpu_env);
4424 #endif /* defined(CONFIG_USER_ONLY) */
4425 }
4426
4427 /* tlbiel */
4428 static void gen_tlbiel(DisasContext *ctx)
4429 {
4430 #if defined(CONFIG_USER_ONLY)
4431 GEN_PRIV;
4432 #else
4433 CHK_SV;
4434
4435 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4436 #endif /* defined(CONFIG_USER_ONLY) */
4437 }
4438
4439 /* tlbie */
4440 static void gen_tlbie(DisasContext *ctx)
4441 {
4442 #if defined(CONFIG_USER_ONLY)
4443 GEN_PRIV;
4444 #else
4445 CHK_HV;
4446
4447 if (NARROW_MODE(ctx)) {
4448 TCGv t0 = tcg_temp_new();
4449 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4450 gen_helper_tlbie(cpu_env, t0);
4451 tcg_temp_free(t0);
4452 } else {
4453 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4454 }
4455 #endif /* defined(CONFIG_USER_ONLY) */
4456 }
4457
4458 /* tlbsync */
4459 static void gen_tlbsync(DisasContext *ctx)
4460 {
4461 #if defined(CONFIG_USER_ONLY)
4462 GEN_PRIV;
4463 #else
4464 CHK_HV;
4465
4466 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4467 * embedded however needs to deal with tlbsync. We don't try to be
4468 * fancy and swallow the overhead of checking for both.
4469 */
4470 gen_check_tlb_flush(ctx);
4471 #endif /* defined(CONFIG_USER_ONLY) */
4472 }
4473
4474 #if defined(TARGET_PPC64)
4475 /* slbia */
4476 static void gen_slbia(DisasContext *ctx)
4477 {
4478 #if defined(CONFIG_USER_ONLY)
4479 GEN_PRIV;
4480 #else
4481 CHK_SV;
4482
4483 gen_helper_slbia(cpu_env);
4484 #endif /* defined(CONFIG_USER_ONLY) */
4485 }
4486
4487 /* slbie */
4488 static void gen_slbie(DisasContext *ctx)
4489 {
4490 #if defined(CONFIG_USER_ONLY)
4491 GEN_PRIV;
4492 #else
4493 CHK_SV;
4494
4495 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4496 #endif /* defined(CONFIG_USER_ONLY) */
4497 }
4498 #endif /* defined(TARGET_PPC64) */
4499
4500 /*** External control ***/
4501 /* Optional: */
4502
4503 /* eciwx */
4504 static void gen_eciwx(DisasContext *ctx)
4505 {
4506 TCGv t0;
4507 /* Should check EAR[E] ! */
4508 gen_set_access_type(ctx, ACCESS_EXT);
4509 t0 = tcg_temp_new();
4510 gen_addr_reg_index(ctx, t0);
4511 gen_check_align(ctx, t0, 0x03);
4512 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4513 tcg_temp_free(t0);
4514 }
4515
4516 /* ecowx */
4517 static void gen_ecowx(DisasContext *ctx)
4518 {
4519 TCGv t0;
4520 /* Should check EAR[E] ! */
4521 gen_set_access_type(ctx, ACCESS_EXT);
4522 t0 = tcg_temp_new();
4523 gen_addr_reg_index(ctx, t0);
4524 gen_check_align(ctx, t0, 0x03);
4525 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4526 tcg_temp_free(t0);
4527 }
4528
4529 /* PowerPC 601 specific instructions */
4530
4531 /* abs - abs. */
4532 static void gen_abs(DisasContext *ctx)
4533 {
4534 TCGLabel *l1 = gen_new_label();
4535 TCGLabel *l2 = gen_new_label();
4536 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4537 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4538 tcg_gen_br(l2);
4539 gen_set_label(l1);
4540 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4541 gen_set_label(l2);
4542 if (unlikely(Rc(ctx->opcode) != 0))
4543 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4544 }
4545
4546 /* abso - abso. */
4547 static void gen_abso(DisasContext *ctx)
4548 {
4549 TCGLabel *l1 = gen_new_label();
4550 TCGLabel *l2 = gen_new_label();
4551 TCGLabel *l3 = gen_new_label();
4552 /* Start with XER OV disabled, the most likely case */
4553 tcg_gen_movi_tl(cpu_ov, 0);
4554 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4555 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4556 tcg_gen_movi_tl(cpu_ov, 1);
4557 tcg_gen_movi_tl(cpu_so, 1);
4558 tcg_gen_br(l2);
4559 gen_set_label(l1);
4560 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4561 tcg_gen_br(l3);
4562 gen_set_label(l2);
4563 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4564 gen_set_label(l3);
4565 if (unlikely(Rc(ctx->opcode) != 0))
4566 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4567 }
4568
4569 /* clcs */
4570 static void gen_clcs(DisasContext *ctx)
4571 {
4572 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4573 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4574 tcg_temp_free_i32(t0);
4575 /* Rc=1 sets CR0 to an undefined state */
4576 }
4577
4578 /* div - div. */
4579 static void gen_div(DisasContext *ctx)
4580 {
4581 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4582 cpu_gpr[rB(ctx->opcode)]);
4583 if (unlikely(Rc(ctx->opcode) != 0))
4584 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4585 }
4586
4587 /* divo - divo. */
4588 static void gen_divo(DisasContext *ctx)
4589 {
4590 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4591 cpu_gpr[rB(ctx->opcode)]);
4592 if (unlikely(Rc(ctx->opcode) != 0))
4593 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4594 }
4595
4596 /* divs - divs. */
4597 static void gen_divs(DisasContext *ctx)
4598 {
4599 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4600 cpu_gpr[rB(ctx->opcode)]);
4601 if (unlikely(Rc(ctx->opcode) != 0))
4602 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4603 }
4604
4605 /* divso - divso. */
4606 static void gen_divso(DisasContext *ctx)
4607 {
4608 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4609 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4610 if (unlikely(Rc(ctx->opcode) != 0))
4611 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4612 }
4613
4614 /* doz - doz. */
4615 static void gen_doz(DisasContext *ctx)
4616 {
4617 TCGLabel *l1 = gen_new_label();
4618 TCGLabel *l2 = gen_new_label();
4619 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4620 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4621 tcg_gen_br(l2);
4622 gen_set_label(l1);
4623 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4624 gen_set_label(l2);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4627 }
4628
4629 /* dozo - dozo. */
4630 static void gen_dozo(DisasContext *ctx)
4631 {
4632 TCGLabel *l1 = gen_new_label();
4633 TCGLabel *l2 = gen_new_label();
4634 TCGv t0 = tcg_temp_new();
4635 TCGv t1 = tcg_temp_new();
4636 TCGv t2 = tcg_temp_new();
4637 /* Start with XER OV disabled, the most likely case */
4638 tcg_gen_movi_tl(cpu_ov, 0);
4639 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4640 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4641 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4642 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4643 tcg_gen_andc_tl(t1, t1, t2);
4644 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4645 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4646 tcg_gen_movi_tl(cpu_ov, 1);
4647 tcg_gen_movi_tl(cpu_so, 1);
4648 tcg_gen_br(l2);
4649 gen_set_label(l1);
4650 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4651 gen_set_label(l2);
4652 tcg_temp_free(t0);
4653 tcg_temp_free(t1);
4654 tcg_temp_free(t2);
4655 if (unlikely(Rc(ctx->opcode) != 0))
4656 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4657 }
4658
4659 /* dozi */
4660 static void gen_dozi(DisasContext *ctx)
4661 {
4662 target_long simm = SIMM(ctx->opcode);
4663 TCGLabel *l1 = gen_new_label();
4664 TCGLabel *l2 = gen_new_label();
4665 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4666 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4667 tcg_gen_br(l2);
4668 gen_set_label(l1);
4669 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4670 gen_set_label(l2);
4671 if (unlikely(Rc(ctx->opcode) != 0))
4672 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4673 }
4674
4675 /* lscbx - lscbx. */
4676 static void gen_lscbx(DisasContext *ctx)
4677 {
4678 TCGv t0 = tcg_temp_new();
4679 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4680 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4681 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4682
4683 gen_addr_reg_index(ctx, t0);
4684 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4685 tcg_temp_free_i32(t1);
4686 tcg_temp_free_i32(t2);
4687 tcg_temp_free_i32(t3);
4688 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4689 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4690 if (unlikely(Rc(ctx->opcode) != 0))
4691 gen_set_Rc0(ctx, t0);
4692 tcg_temp_free(t0);
4693 }
4694
4695 /* maskg - maskg. */
4696 static void gen_maskg(DisasContext *ctx)
4697 {
4698 TCGLabel *l1 = gen_new_label();
4699 TCGv t0 = tcg_temp_new();
4700 TCGv t1 = tcg_temp_new();
4701 TCGv t2 = tcg_temp_new();
4702 TCGv t3 = tcg_temp_new();
4703 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4704 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4705 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4706 tcg_gen_addi_tl(t2, t0, 1);
4707 tcg_gen_shr_tl(t2, t3, t2);
4708 tcg_gen_shr_tl(t3, t3, t1);
4709 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4710 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4711 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4712 gen_set_label(l1);
4713 tcg_temp_free(t0);
4714 tcg_temp_free(t1);
4715 tcg_temp_free(t2);
4716 tcg_temp_free(t3);
4717 if (unlikely(Rc(ctx->opcode) != 0))
4718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4719 }
4720
4721 /* maskir - maskir. */
4722 static void gen_maskir(DisasContext *ctx)
4723 {
4724 TCGv t0 = tcg_temp_new();
4725 TCGv t1 = tcg_temp_new();
4726 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4727 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4728 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4729 tcg_temp_free(t0);
4730 tcg_temp_free(t1);
4731 if (unlikely(Rc(ctx->opcode) != 0))
4732 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4733 }
4734
4735 /* mul - mul. */
4736 static void gen_mul(DisasContext *ctx)
4737 {
4738 TCGv_i64 t0 = tcg_temp_new_i64();
4739 TCGv_i64 t1 = tcg_temp_new_i64();
4740 TCGv t2 = tcg_temp_new();
4741 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4742 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4743 tcg_gen_mul_i64(t0, t0, t1);
4744 tcg_gen_trunc_i64_tl(t2, t0);
4745 gen_store_spr(SPR_MQ, t2);
4746 tcg_gen_shri_i64(t1, t0, 32);
4747 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4748 tcg_temp_free_i64(t0);
4749 tcg_temp_free_i64(t1);
4750 tcg_temp_free(t2);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4753 }
4754
4755 /* mulo - mulo. */
4756 static void gen_mulo(DisasContext *ctx)
4757 {
4758 TCGLabel *l1 = gen_new_label();
4759 TCGv_i64 t0 = tcg_temp_new_i64();
4760 TCGv_i64 t1 = tcg_temp_new_i64();
4761 TCGv t2 = tcg_temp_new();
4762 /* Start with XER OV disabled, the most likely case */
4763 tcg_gen_movi_tl(cpu_ov, 0);
4764 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4765 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4766 tcg_gen_mul_i64(t0, t0, t1);
4767 tcg_gen_trunc_i64_tl(t2, t0);
4768 gen_store_spr(SPR_MQ, t2);
4769 tcg_gen_shri_i64(t1, t0, 32);
4770 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4771 tcg_gen_ext32s_i64(t1, t0);
4772 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4773 tcg_gen_movi_tl(cpu_ov, 1);
4774 tcg_gen_movi_tl(cpu_so, 1);
4775 gen_set_label(l1);
4776 tcg_temp_free_i64(t0);
4777 tcg_temp_free_i64(t1);
4778 tcg_temp_free(t2);
4779 if (unlikely(Rc(ctx->opcode) != 0))
4780 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4781 }
4782
4783 /* nabs - nabs. */
4784 static void gen_nabs(DisasContext *ctx)
4785 {
4786 TCGLabel *l1 = gen_new_label();
4787 TCGLabel *l2 = gen_new_label();
4788 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4789 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4790 tcg_gen_br(l2);
4791 gen_set_label(l1);
4792 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4793 gen_set_label(l2);
4794 if (unlikely(Rc(ctx->opcode) != 0))
4795 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4796 }
4797
4798 /* nabso - nabso. */
4799 static void gen_nabso(DisasContext *ctx)
4800 {
4801 TCGLabel *l1 = gen_new_label();
4802 TCGLabel *l2 = gen_new_label();
4803 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4804 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4805 tcg_gen_br(l2);
4806 gen_set_label(l1);
4807 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4808 gen_set_label(l2);
4809 /* nabs never overflows */
4810 tcg_gen_movi_tl(cpu_ov, 0);
4811 if (unlikely(Rc(ctx->opcode) != 0))
4812 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4813 }
4814
4815 /* rlmi - rlmi. */
4816 static void gen_rlmi(DisasContext *ctx)
4817 {
4818 uint32_t mb = MB(ctx->opcode);
4819 uint32_t me = ME(ctx->opcode);
4820 TCGv t0 = tcg_temp_new();
4821 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4822 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4823 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4824 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4825 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4826 tcg_temp_free(t0);
4827 if (unlikely(Rc(ctx->opcode) != 0))
4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4829 }
4830
4831 /* rrib - rrib. */
4832 static void gen_rrib(DisasContext *ctx)
4833 {
4834 TCGv t0 = tcg_temp_new();
4835 TCGv t1 = tcg_temp_new();
4836 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4837 tcg_gen_movi_tl(t1, 0x80000000);
4838 tcg_gen_shr_tl(t1, t1, t0);
4839 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4840 tcg_gen_and_tl(t0, t0, t1);
4841 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4842 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 if (unlikely(Rc(ctx->opcode) != 0))
4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4847 }
4848
4849 /* sle - sle. */
4850 static void gen_sle(DisasContext *ctx)
4851 {
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4855 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4856 tcg_gen_subfi_tl(t1, 32, t1);
4857 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4858 tcg_gen_or_tl(t1, t0, t1);
4859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4860 gen_store_spr(SPR_MQ, t1);
4861 tcg_temp_free(t0);
4862 tcg_temp_free(t1);
4863 if (unlikely(Rc(ctx->opcode) != 0))
4864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4865 }
4866
4867 /* sleq - sleq. */
4868 static void gen_sleq(DisasContext *ctx)
4869 {
4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 TCGv t2 = tcg_temp_new();
4873 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4874 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4875 tcg_gen_shl_tl(t2, t2, t0);
4876 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4877 gen_load_spr(t1, SPR_MQ);
4878 gen_store_spr(SPR_MQ, t0);
4879 tcg_gen_and_tl(t0, t0, t2);
4880 tcg_gen_andc_tl(t1, t1, t2);
4881 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4882 tcg_temp_free(t0);
4883 tcg_temp_free(t1);
4884 tcg_temp_free(t2);
4885 if (unlikely(Rc(ctx->opcode) != 0))
4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4887 }
4888
4889 /* sliq - sliq. */
4890 static void gen_sliq(DisasContext *ctx)
4891 {
4892 int sh = SH(ctx->opcode);
4893 TCGv t0 = tcg_temp_new();
4894 TCGv t1 = tcg_temp_new();
4895 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4896 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4897 tcg_gen_or_tl(t1, t0, t1);
4898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4899 gen_store_spr(SPR_MQ, t1);
4900 tcg_temp_free(t0);
4901 tcg_temp_free(t1);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4904 }
4905
4906 /* slliq - slliq. */
4907 static void gen_slliq(DisasContext *ctx)
4908 {
4909 int sh = SH(ctx->opcode);
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_new();
4912 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4913 gen_load_spr(t1, SPR_MQ);
4914 gen_store_spr(SPR_MQ, t0);
4915 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4916 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4917 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4922 }
4923
4924 /* sllq - sllq. */
4925 static void gen_sllq(DisasContext *ctx)
4926 {
4927 TCGLabel *l1 = gen_new_label();
4928 TCGLabel *l2 = gen_new_label();
4929 TCGv t0 = tcg_temp_local_new();
4930 TCGv t1 = tcg_temp_local_new();
4931 TCGv t2 = tcg_temp_local_new();
4932 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4933 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4934 tcg_gen_shl_tl(t1, t1, t2);
4935 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4936 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4937 gen_load_spr(t0, SPR_MQ);
4938 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4939 tcg_gen_br(l2);
4940 gen_set_label(l1);
4941 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4942 gen_load_spr(t2, SPR_MQ);
4943 tcg_gen_andc_tl(t1, t2, t1);
4944 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4945 gen_set_label(l2);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 tcg_temp_free(t2);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4951 }
4952
4953 /* slq - slq. */
4954 static void gen_slq(DisasContext *ctx)
4955 {
4956 TCGLabel *l1 = gen_new_label();
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_new();
4959 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4960 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4961 tcg_gen_subfi_tl(t1, 32, t1);
4962 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4963 tcg_gen_or_tl(t1, t0, t1);
4964 gen_store_spr(SPR_MQ, t1);
4965 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4967 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4968 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4969 gen_set_label(l1);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974 }
4975
4976 /* sraiq - sraiq. */
4977 static void gen_sraiq(DisasContext *ctx)
4978 {
4979 int sh = SH(ctx->opcode);
4980 TCGLabel *l1 = gen_new_label();
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4985 tcg_gen_or_tl(t0, t0, t1);
4986 gen_store_spr(SPR_MQ, t0);
4987 tcg_gen_movi_tl(cpu_ca, 0);
4988 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4989 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4990 tcg_gen_movi_tl(cpu_ca, 1);
4991 gen_set_label(l1);
4992 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4993 tcg_temp_free(t0);
4994 tcg_temp_free(t1);
4995 if (unlikely(Rc(ctx->opcode) != 0))
4996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4997 }
4998
4999 /* sraq - sraq. */
5000 static void gen_sraq(DisasContext *ctx)
5001 {
5002 TCGLabel *l1 = gen_new_label();
5003 TCGLabel *l2 = gen_new_label();
5004 TCGv t0 = tcg_temp_new();
5005 TCGv t1 = tcg_temp_local_new();
5006 TCGv t2 = tcg_temp_local_new();
5007 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5008 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5009 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5010 tcg_gen_subfi_tl(t2, 32, t2);
5011 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5012 tcg_gen_or_tl(t0, t0, t2);
5013 gen_store_spr(SPR_MQ, t0);
5014 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5015 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5016 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5017 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5018 gen_set_label(l1);
5019 tcg_temp_free(t0);
5020 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5021 tcg_gen_movi_tl(cpu_ca, 0);
5022 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5023 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5024 tcg_gen_movi_tl(cpu_ca, 1);
5025 gen_set_label(l2);
5026 tcg_temp_free(t1);
5027 tcg_temp_free(t2);
5028 if (unlikely(Rc(ctx->opcode) != 0))
5029 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5030 }
5031
5032 /* sre - sre. */
5033 static void gen_sre(DisasContext *ctx)
5034 {
5035 TCGv t0 = tcg_temp_new();
5036 TCGv t1 = tcg_temp_new();
5037 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5039 tcg_gen_subfi_tl(t1, 32, t1);
5040 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5041 tcg_gen_or_tl(t1, t0, t1);
5042 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5043 gen_store_spr(SPR_MQ, t1);
5044 tcg_temp_free(t0);
5045 tcg_temp_free(t1);
5046 if (unlikely(Rc(ctx->opcode) != 0))
5047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5048 }
5049
5050 /* srea - srea. */
5051 static void gen_srea(DisasContext *ctx)
5052 {
5053 TCGv t0 = tcg_temp_new();
5054 TCGv t1 = tcg_temp_new();
5055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5057 gen_store_spr(SPR_MQ, t0);
5058 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5063 }
5064
5065 /* sreq */
5066 static void gen_sreq(DisasContext *ctx)
5067 {
5068 TCGv t0 = tcg_temp_new();
5069 TCGv t1 = tcg_temp_new();
5070 TCGv t2 = tcg_temp_new();
5071 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5073 tcg_gen_shr_tl(t1, t1, t0);
5074 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5075 gen_load_spr(t2, SPR_MQ);
5076 gen_store_spr(SPR_MQ, t0);
5077 tcg_gen_and_tl(t0, t0, t1);
5078 tcg_gen_andc_tl(t2, t2, t1);
5079 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5085 }
5086
5087 /* sriq */
5088 static void gen_sriq(DisasContext *ctx)
5089 {
5090 int sh = SH(ctx->opcode);
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5094 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5095 tcg_gen_or_tl(t1, t0, t1);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 gen_store_spr(SPR_MQ, t1);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5102 }
5103
5104 /* srliq */
5105 static void gen_srliq(DisasContext *ctx)
5106 {
5107 int sh = SH(ctx->opcode);
5108 TCGv t0 = tcg_temp_new();
5109 TCGv t1 = tcg_temp_new();
5110 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5111 gen_load_spr(t1, SPR_MQ);
5112 gen_store_spr(SPR_MQ, t0);
5113 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5114 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
5118 if (unlikely(Rc(ctx->opcode) != 0))
5119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5120 }
5121
5122 /* srlq */
5123 static void gen_srlq(DisasContext *ctx)
5124 {
5125 TCGLabel *l1 = gen_new_label();
5126 TCGLabel *l2 = gen_new_label();
5127 TCGv t0 = tcg_temp_local_new();
5128 TCGv t1 = tcg_temp_local_new();
5129 TCGv t2 = tcg_temp_local_new();
5130 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5132 tcg_gen_shr_tl(t2, t1, t2);
5133 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5134 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5135 gen_load_spr(t0, SPR_MQ);
5136 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5140 tcg_gen_and_tl(t0, t0, t2);
5141 gen_load_spr(t1, SPR_MQ);
5142 tcg_gen_andc_tl(t1, t1, t2);
5143 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5144 gen_set_label(l2);
5145 tcg_temp_free(t0);
5146 tcg_temp_free(t1);
5147 tcg_temp_free(t2);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5150 }
5151
5152 /* srq */
5153 static void gen_srq(DisasContext *ctx)
5154 {
5155 TCGLabel *l1 = gen_new_label();
5156 TCGv t0 = tcg_temp_new();
5157 TCGv t1 = tcg_temp_new();
5158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5159 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5160 tcg_gen_subfi_tl(t1, 32, t1);
5161 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5162 tcg_gen_or_tl(t1, t0, t1);
5163 gen_store_spr(SPR_MQ, t1);
5164 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5165 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5166 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5167 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5168 gen_set_label(l1);
5169 tcg_temp_free(t0);
5170 tcg_temp_free(t1);
5171 if (unlikely(Rc(ctx->opcode) != 0))
5172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5173 }
5174
5175 /* PowerPC 602 specific instructions */
5176
5177 /* dsa */
5178 static void gen_dsa(DisasContext *ctx)
5179 {
5180 /* XXX: TODO */
5181 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5182 }
5183
5184 /* esa */
5185 static void gen_esa(DisasContext *ctx)
5186 {
5187 /* XXX: TODO */
5188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5189 }
5190
5191 /* mfrom */
5192 static void gen_mfrom(DisasContext *ctx)
5193 {
5194 #if defined(CONFIG_USER_ONLY)
5195 GEN_PRIV;
5196 #else
5197 CHK_SV;
5198 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5199 #endif /* defined(CONFIG_USER_ONLY) */
5200 }
5201
5202 /* 602 - 603 - G2 TLB management */
5203
5204 /* tlbld */
5205 static void gen_tlbld_6xx(DisasContext *ctx)
5206 {
5207 #if defined(CONFIG_USER_ONLY)
5208 GEN_PRIV;
5209 #else
5210 CHK_SV;
5211 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5212 #endif /* defined(CONFIG_USER_ONLY) */
5213 }
5214
5215 /* tlbli */
5216 static void gen_tlbli_6xx(DisasContext *ctx)
5217 {
5218 #if defined(CONFIG_USER_ONLY)
5219 GEN_PRIV;
5220 #else
5221 CHK_SV;
5222 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5223 #endif /* defined(CONFIG_USER_ONLY) */
5224 }
5225
5226 /* 74xx TLB management */
5227
5228 /* tlbld */
5229 static void gen_tlbld_74xx(DisasContext *ctx)
5230 {
5231 #if defined(CONFIG_USER_ONLY)
5232 GEN_PRIV;
5233 #else
5234 CHK_SV;
5235 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5236 #endif /* defined(CONFIG_USER_ONLY) */
5237 }
5238
5239 /* tlbli */
5240 static void gen_tlbli_74xx(DisasContext *ctx)
5241 {
5242 #if defined(CONFIG_USER_ONLY)
5243 GEN_PRIV;
5244 #else
5245 CHK_SV;
5246 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5247 #endif /* defined(CONFIG_USER_ONLY) */
5248 }
5249
5250 /* POWER instructions not in PowerPC 601 */
5251
5252 /* clf */
5253 static void gen_clf(DisasContext *ctx)
5254 {
5255 /* Cache line flush: implemented as no-op */
5256 }
5257
5258 /* cli */
5259 static void gen_cli(DisasContext *ctx)
5260 {
5261 #if defined(CONFIG_USER_ONLY)
5262 GEN_PRIV;
5263 #else
5264 /* Cache line invalidate: privileged and treated as no-op */
5265 CHK_SV;
5266 #endif /* defined(CONFIG_USER_ONLY) */
5267 }
5268
5269 /* dclst */
5270 static void gen_dclst(DisasContext *ctx)
5271 {
5272 /* Data cache line store: treated as no-op */
5273 }
5274
5275 static void gen_mfsri(DisasContext *ctx)
5276 {
5277 #if defined(CONFIG_USER_ONLY)
5278 GEN_PRIV;
5279 #else
5280 int ra = rA(ctx->opcode);
5281 int rd = rD(ctx->opcode);
5282 TCGv t0;
5283
5284 CHK_SV;
5285 t0 = tcg_temp_new();
5286 gen_addr_reg_index(ctx, t0);
5287 tcg_gen_shri_tl(t0, t0, 28);
5288 tcg_gen_andi_tl(t0, t0, 0xF);
5289 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5290 tcg_temp_free(t0);
5291 if (ra != 0 && ra != rd)
5292 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5293 #endif /* defined(CONFIG_USER_ONLY) */
5294 }
5295
5296 static void gen_rac(DisasContext *ctx)
5297 {
5298 #if defined(CONFIG_USER_ONLY)
5299 GEN_PRIV;
5300 #else
5301 TCGv t0;
5302
5303 CHK_SV;
5304 t0 = tcg_temp_new();
5305 gen_addr_reg_index(ctx, t0);
5306 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5307 tcg_temp_free(t0);
5308 #endif /* defined(CONFIG_USER_ONLY) */
5309 }
5310
5311 static void gen_rfsvc(DisasContext *ctx)
5312 {
5313 #if defined(CONFIG_USER_ONLY)
5314 GEN_PRIV;
5315 #else
5316 CHK_SV;
5317
5318 gen_helper_rfsvc(cpu_env);
5319 gen_sync_exception(ctx);
5320 #endif /* defined(CONFIG_USER_ONLY) */
5321 }
5322
5323 /* svc is not implemented for now */
5324
5325 /* BookE specific instructions */
5326
5327 /* XXX: not implemented on 440 ? */
5328 static void gen_mfapidi(DisasContext *ctx)
5329 {
5330 /* XXX: TODO */
5331 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5332 }
5333
5334 /* XXX: not implemented on 440 ? */
5335 static void gen_tlbiva(DisasContext *ctx)
5336 {
5337 #if defined(CONFIG_USER_ONLY)
5338 GEN_PRIV;
5339 #else
5340 TCGv t0;
5341
5342 CHK_SV;
5343 t0 = tcg_temp_new();
5344 gen_addr_reg_index(ctx, t0);
5345 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5346 tcg_temp_free(t0);
5347 #endif /* defined(CONFIG_USER_ONLY) */
5348 }
5349
5350 /* All 405 MAC instructions are translated here */
5351 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5352 int ra, int rb, int rt, int Rc)
5353 {
5354 TCGv t0, t1;
5355
5356 t0 = tcg_temp_local_new();
5357 t1 = tcg_temp_local_new();
5358
5359 switch (opc3 & 0x0D) {
5360 case 0x05:
5361 /* macchw - macchw. - macchwo - macchwo. */
5362 /* macchws - macchws. - macchwso - macchwso. */
5363 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5364 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5365 /* mulchw - mulchw. */
5366 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5367 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5368 tcg_gen_ext16s_tl(t1, t1);
5369 break;
5370 case 0x04:
5371 /* macchwu - macchwu. - macchwuo - macchwuo. */
5372 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5373 /* mulchwu - mulchwu. */
5374 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5375 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5376 tcg_gen_ext16u_tl(t1, t1);
5377 break;
5378 case 0x01:
5379 /* machhw - machhw. - machhwo - machhwo. */
5380 /* machhws - machhws. - machhwso - machhwso. */
5381 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5382 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5383 /* mulhhw - mulhhw. */
5384 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5385 tcg_gen_ext16s_tl(t0, t0);
5386 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5387 tcg_gen_ext16s_tl(t1, t1);
5388 break;
5389 case 0x00:
5390 /* machhwu - machhwu. - machhwuo - machhwuo. */
5391 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5392 /* mulhhwu - mulhhwu. */
5393 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5394 tcg_gen_ext16u_tl(t0, t0);
5395 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5396 tcg_gen_ext16u_tl(t1, t1);
5397 break;
5398 case 0x0D:
5399 /* maclhw - maclhw. - maclhwo - maclhwo. */
5400 /* maclhws - maclhws. - maclhwso - maclhwso. */
5401 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5402 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5403 /* mullhw - mullhw. */
5404 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5405 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5406 break;
5407 case 0x0C:
5408 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5409 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5410 /* mullhwu - mullhwu. */
5411 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5412 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5413 break;
5414 }
5415 if (opc2 & 0x04) {
5416 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5417 tcg_gen_mul_tl(t1, t0, t1);
5418 if (opc2 & 0x02) {
5419 /* nmultiply-and-accumulate (0x0E) */
5420 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5421 } else {
5422 /* multiply-and-accumulate (0x0C) */
5423 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5424 }
5425
5426 if (opc3 & 0x12) {
5427 /* Check overflow and/or saturate */
5428 TCGLabel *l1 = gen_new_label();
5429
5430 if (opc3 & 0x10) {
5431 /* Start with XER OV disabled, the most likely case */
5432 tcg_gen_movi_tl(cpu_ov, 0);
5433 }
5434 if (opc3 & 0x01) {
5435 /* Signed */
5436 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5437 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5438 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5439 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5440 if (opc3 & 0x02) {
5441 /* Saturate */
5442 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5443 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5444 }
5445 } else {
5446 /* Unsigned */
5447 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5448 if (opc3 & 0x02) {
5449 /* Saturate */
5450 tcg_gen_movi_tl(t0, UINT32_MAX);
5451 }
5452 }
5453 if (opc3 & 0x10) {
5454 /* Check overflow */
5455 tcg_gen_movi_tl(cpu_ov, 1);
5456 tcg_gen_movi_tl(cpu_so, 1);
5457 }
5458 gen_set_label(l1);
5459 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5460 }
5461 } else {
5462 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5463 }
5464 tcg_temp_free(t0);
5465 tcg_temp_free(t1);
5466 if (unlikely(Rc) != 0) {
5467 /* Update Rc0 */
5468 gen_set_Rc0(ctx, cpu_gpr[rt]);
5469 }
5470 }
5471
5472 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5473 static void glue(gen_, name)(DisasContext *ctx) \
5474 { \
5475 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5476 rD(ctx->opcode), Rc(ctx->opcode)); \
5477 }
5478
5479 /* macchw - macchw. */
5480 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5481 /* macchwo - macchwo. */
5482 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5483 /* macchws - macchws. */
5484 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5485 /* macchwso - macchwso. */
5486 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5487 /* macchwsu - macchwsu. */
5488 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5489 /* macchwsuo - macchwsuo. */
5490 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5491 /* macchwu - macchwu. */
5492 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5493 /* macchwuo - macchwuo. */
5494 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5495 /* machhw - machhw. */
5496 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5497 /* machhwo - machhwo. */
5498 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5499 /* machhws - machhws. */
5500 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5501 /* machhwso - machhwso. */
5502 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5503 /* machhwsu - machhwsu. */
5504 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5505 /* machhwsuo - machhwsuo. */
5506 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5507 /* machhwu - machhwu. */
5508 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5509 /* machhwuo - machhwuo. */
5510 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5511 /* maclhw - maclhw. */
5512 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5513 /* maclhwo - maclhwo. */
5514 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5515 /* maclhws - maclhws. */
5516 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5517 /* maclhwso - maclhwso. */
5518 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5519 /* maclhwu - maclhwu. */
5520 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5521 /* maclhwuo - maclhwuo. */
5522 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5523 /* maclhwsu - maclhwsu. */
5524 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5525 /* maclhwsuo - maclhwsuo. */
5526 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5527 /* nmacchw - nmacchw. */
5528 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5529 /* nmacchwo - nmacchwo. */
5530 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5531 /* nmacchws - nmacchws. */
5532 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5533 /* nmacchwso - nmacchwso. */
5534 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5535 /* nmachhw - nmachhw. */
5536 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5537 /* nmachhwo - nmachhwo. */
5538 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5539 /* nmachhws - nmachhws. */
5540 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5541 /* nmachhwso - nmachhwso. */
5542 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5543 /* nmaclhw - nmaclhw. */
5544 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5545 /* nmaclhwo - nmaclhwo. */
5546 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5547 /* nmaclhws - nmaclhws. */
5548 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5549 /* nmaclhwso - nmaclhwso. */
5550 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5551
5552 /* mulchw - mulchw. */
5553 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5554 /* mulchwu - mulchwu. */
5555 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5556 /* mulhhw - mulhhw. */
5557 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5558 /* mulhhwu - mulhhwu. */
5559 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5560 /* mullhw - mullhw. */
5561 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5562 /* mullhwu - mullhwu. */
5563 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5564
5565 /* mfdcr */
5566 static void gen_mfdcr(DisasContext *ctx)
5567 {
5568 #if defined(CONFIG_USER_ONLY)
5569 GEN_PRIV;
5570 #else
5571 TCGv dcrn;
5572
5573 CHK_SV;
5574 dcrn = tcg_const_tl(SPR(ctx->opcode));
5575 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5576 tcg_temp_free(dcrn);
5577 #endif /* defined(CONFIG_USER_ONLY) */
5578 }
5579
5580 /* mtdcr */
5581 static void gen_mtdcr(DisasContext *ctx)
5582 {
5583 #if defined(CONFIG_USER_ONLY)
5584 GEN_PRIV;
5585 #else
5586 TCGv dcrn;
5587
5588 CHK_SV;
5589 dcrn = tcg_const_tl(SPR(ctx->opcode));
5590 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5591 tcg_temp_free(dcrn);
5592 #endif /* defined(CONFIG_USER_ONLY) */
5593 }
5594
5595 /* mfdcrx */
5596 /* XXX: not implemented on 440 ? */
5597 static void gen_mfdcrx(DisasContext *ctx)
5598 {
5599 #if defined(CONFIG_USER_ONLY)
5600 GEN_PRIV;
5601 #else
5602 CHK_SV;
5603 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5604 cpu_gpr[rA(ctx->opcode)]);
5605 /* Note: Rc update flag set leads to undefined state of Rc0 */
5606 #endif /* defined(CONFIG_USER_ONLY) */
5607 }
5608
5609 /* mtdcrx */
5610 /* XXX: not implemented on 440 ? */
5611 static void gen_mtdcrx(DisasContext *ctx)
5612 {
5613 #if defined(CONFIG_USER_ONLY)
5614 GEN_PRIV;
5615 #else
5616 CHK_SV;
5617 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5618 cpu_gpr[rS(ctx->opcode)]);
5619 /* Note: Rc update flag set leads to undefined state of Rc0 */
5620 #endif /* defined(CONFIG_USER_ONLY) */
5621 }
5622
5623 /* mfdcrux (PPC 460) : user-mode access to DCR */
5624 static void gen_mfdcrux(DisasContext *ctx)
5625 {
5626 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5627 cpu_gpr[rA(ctx->opcode)]);
5628 /* Note: Rc update flag set leads to undefined state of Rc0 */
5629 }
5630
5631 /* mtdcrux (PPC 460) : user-mode access to DCR */
5632 static void gen_mtdcrux(DisasContext *ctx)
5633 {
5634 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5635 cpu_gpr[rS(ctx->opcode)]);
5636 /* Note: Rc update flag set leads to undefined state of Rc0 */
5637 }
5638
5639 /* dccci */
5640 static void gen_dccci(DisasContext *ctx)
5641 {
5642 CHK_SV;
5643 /* interpreted as no-op */
5644 }
5645
5646 /* dcread */
5647 static void gen_dcread(DisasContext *ctx)
5648 {
5649 #if defined(CONFIG_USER_ONLY)
5650 GEN_PRIV;
5651 #else
5652 TCGv EA, val;
5653
5654 CHK_SV;
5655 gen_set_access_type(ctx, ACCESS_CACHE);
5656 EA = tcg_temp_new();
5657 gen_addr_reg_index(ctx, EA);
5658 val = tcg_temp_new();
5659 gen_qemu_ld32u(ctx, val, EA);
5660 tcg_temp_free(val);
5661 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5662 tcg_temp_free(EA);
5663 #endif /* defined(CONFIG_USER_ONLY) */
5664 }
5665
5666 /* icbt */
5667 static void gen_icbt_40x(DisasContext *ctx)
5668 {
5669 /* interpreted as no-op */
5670 /* XXX: specification say this is treated as a load by the MMU
5671 * but does not generate any exception
5672 */
5673 }
5674
5675 /* iccci */
5676 static void gen_iccci(DisasContext *ctx)
5677 {
5678 CHK_SV;
5679 /* interpreted as no-op */
5680 }
5681
5682 /* icread */
5683 static void gen_icread(DisasContext *ctx)
5684 {
5685 CHK_SV;
5686 /* interpreted as no-op */
5687 }
5688
5689 /* rfci (supervisor only) */
5690 static void gen_rfci_40x(DisasContext *ctx)
5691 {
5692 #if defined(CONFIG_USER_ONLY)
5693 GEN_PRIV;
5694 #else
5695 CHK_SV;
5696 /* Restore CPU state */
5697 gen_helper_40x_rfci(cpu_env);
5698 gen_sync_exception(ctx);
5699 #endif /* defined(CONFIG_USER_ONLY) */
5700 }
5701
5702 static void gen_rfci(DisasContext *ctx)
5703 {
5704 #if defined(CONFIG_USER_ONLY)
5705 GEN_PRIV;
5706 #else
5707 CHK_SV;
5708 /* Restore CPU state */
5709 gen_helper_rfci(cpu_env);
5710 gen_sync_exception(ctx);
5711 #endif /* defined(CONFIG_USER_ONLY) */
5712 }
5713
5714 /* BookE specific */
5715
5716 /* XXX: not implemented on 440 ? */
5717 static void gen_rfdi(DisasContext *ctx)
5718 {
5719 #if defined(CONFIG_USER_ONLY)
5720 GEN_PRIV;
5721 #else
5722 CHK_SV;
5723 /* Restore CPU state */
5724 gen_helper_rfdi(cpu_env);
5725 gen_sync_exception(ctx);
5726 #endif /* defined(CONFIG_USER_ONLY) */
5727 }
5728
5729 /* XXX: not implemented on 440 ? */
5730 static void gen_rfmci(DisasContext *ctx)
5731 {
5732 #if defined(CONFIG_USER_ONLY)
5733 GEN_PRIV;
5734 #else
5735 CHK_SV;
5736 /* Restore CPU state */
5737 gen_helper_rfmci(cpu_env);
5738 gen_sync_exception(ctx);
5739 #endif /* defined(CONFIG_USER_ONLY) */
5740 }
5741
5742 /* TLB management - PowerPC 405 implementation */
5743
5744 /* tlbre */
5745 static void gen_tlbre_40x(DisasContext *ctx)
5746 {
5747 #if defined(CONFIG_USER_ONLY)
5748 GEN_PRIV;
5749 #else
5750 CHK_SV;
5751 switch (rB(ctx->opcode)) {
5752 case 0:
5753 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5754 cpu_gpr[rA(ctx->opcode)]);
5755 break;
5756 case 1:
5757 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5758 cpu_gpr[rA(ctx->opcode)]);
5759 break;
5760 default:
5761 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5762 break;
5763 }
5764 #endif /* defined(CONFIG_USER_ONLY) */
5765 }
5766
5767 /* tlbsx - tlbsx. */
5768 static void gen_tlbsx_40x(DisasContext *ctx)
5769 {
5770 #if defined(CONFIG_USER_ONLY)
5771 GEN_PRIV;
5772 #else
5773 TCGv t0;
5774
5775 CHK_SV;
5776 t0 = tcg_temp_new();
5777 gen_addr_reg_index(ctx, t0);
5778 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5779 tcg_temp_free(t0);
5780 if (Rc(ctx->opcode)) {
5781 TCGLabel *l1 = gen_new_label();
5782 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5783 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5784 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5785 gen_set_label(l1);
5786 }
5787 #endif /* defined(CONFIG_USER_ONLY) */
5788 }
5789
5790 /* tlbwe */
5791 static void gen_tlbwe_40x(DisasContext *ctx)
5792 {
5793 #if defined(CONFIG_USER_ONLY)
5794 GEN_PRIV;
5795 #else
5796 CHK_SV;
5797
5798 switch (rB(ctx->opcode)) {
5799 case 0:
5800 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5801 cpu_gpr[rS(ctx->opcode)]);
5802 break;
5803 case 1:
5804 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5805 cpu_gpr[rS(ctx->opcode)]);
5806 break;
5807 default:
5808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5809 break;
5810 }
5811 #endif /* defined(CONFIG_USER_ONLY) */
5812 }
5813
5814 /* TLB management - PowerPC 440 implementation */
5815
5816 /* tlbre */
5817 static void gen_tlbre_440(DisasContext *ctx)
5818 {
5819 #if defined(CONFIG_USER_ONLY)
5820 GEN_PRIV;
5821 #else
5822 CHK_SV;
5823
5824 switch (rB(ctx->opcode)) {
5825 case 0:
5826 case 1:
5827 case 2:
5828 {
5829 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5830 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5831 t0, cpu_gpr[rA(ctx->opcode)]);
5832 tcg_temp_free_i32(t0);
5833 }
5834 break;
5835 default:
5836 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5837 break;
5838 }
5839 #endif /* defined(CONFIG_USER_ONLY) */
5840 }
5841
5842 /* tlbsx - tlbsx. */
5843 static void gen_tlbsx_440(DisasContext *ctx)
5844 {
5845 #if defined(CONFIG_USER_ONLY)
5846 GEN_PRIV;
5847 #else
5848 TCGv t0;
5849
5850 CHK_SV;
5851 t0 = tcg_temp_new();
5852 gen_addr_reg_index(ctx, t0);
5853 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5854 tcg_temp_free(t0);
5855 if (Rc(ctx->opcode)) {
5856 TCGLabel *l1 = gen_new_label();
5857 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5858 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5859 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5860 gen_set_label(l1);
5861 }
5862 #endif /* defined(CONFIG_USER_ONLY) */
5863 }
5864
5865 /* tlbwe */
5866 static void gen_tlbwe_440(DisasContext *ctx)
5867 {
5868 #if defined(CONFIG_USER_ONLY)
5869 GEN_PRIV;
5870 #else
5871 CHK_SV;
5872 switch (rB(ctx->opcode)) {
5873 case 0:
5874 case 1:
5875 case 2:
5876 {
5877 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5878 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5879 cpu_gpr[rS(ctx->opcode)]);
5880 tcg_temp_free_i32(t0);
5881 }
5882 break;
5883 default:
5884 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5885 break;
5886 }
5887 #endif /* defined(CONFIG_USER_ONLY) */
5888 }
5889
5890 /* TLB management - PowerPC BookE 2.06 implementation */
5891
5892 /* tlbre */
5893 static void gen_tlbre_booke206(DisasContext *ctx)
5894 {
5895 #if defined(CONFIG_USER_ONLY)
5896 GEN_PRIV;
5897 #else
5898 CHK_SV;
5899 gen_helper_booke206_tlbre(cpu_env);
5900 #endif /* defined(CONFIG_USER_ONLY) */
5901 }
5902
5903 /* tlbsx - tlbsx. */
5904 static void gen_tlbsx_booke206(DisasContext *ctx)
5905 {
5906 #if defined(CONFIG_USER_ONLY)
5907 GEN_PRIV;
5908 #else
5909 TCGv t0;
5910
5911 CHK_SV;
5912 if (rA(ctx->opcode)) {
5913 t0 = tcg_temp_new();
5914 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5915 } else {
5916 t0 = tcg_const_tl(0);
5917 }
5918
5919 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5920 gen_helper_booke206_tlbsx(cpu_env, t0);
5921 tcg_temp_free(t0);
5922 #endif /* defined(CONFIG_USER_ONLY) */
5923 }
5924
5925 /* tlbwe */
5926 static void gen_tlbwe_booke206(DisasContext *ctx)
5927 {
5928 #if defined(CONFIG_USER_ONLY)
5929 GEN_PRIV;
5930 #else
5931 CHK_SV;
5932 gen_helper_booke206_tlbwe(cpu_env);
5933 #endif /* defined(CONFIG_USER_ONLY) */
5934 }
5935
5936 static void gen_tlbivax_booke206(DisasContext *ctx)
5937 {
5938 #if defined(CONFIG_USER_ONLY)
5939 GEN_PRIV;
5940 #else
5941 TCGv t0;
5942
5943 CHK_SV;
5944 t0 = tcg_temp_new();
5945 gen_addr_reg_index(ctx, t0);
5946 gen_helper_booke206_tlbivax(cpu_env, t0);
5947 tcg_temp_free(t0);
5948 #endif /* defined(CONFIG_USER_ONLY) */
5949 }
5950
5951 static void gen_tlbilx_booke206(DisasContext *ctx)
5952 {
5953 #if defined(CONFIG_USER_ONLY)
5954 GEN_PRIV;
5955 #else
5956 TCGv t0;
5957
5958 CHK_SV;
5959 t0 = tcg_temp_new();
5960 gen_addr_reg_index(ctx, t0);
5961
5962 switch((ctx->opcode >> 21) & 0x3) {
5963 case 0:
5964 gen_helper_booke206_tlbilx0(cpu_env, t0);
5965 break;
5966 case 1:
5967 gen_helper_booke206_tlbilx1(cpu_env, t0);
5968 break;
5969 case 3:
5970 gen_helper_booke206_tlbilx3(cpu_env, t0);
5971 break;
5972 default:
5973 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5974 break;
5975 }
5976
5977 tcg_temp_free(t0);
5978 #endif /* defined(CONFIG_USER_ONLY) */
5979 }
5980
5981
5982 /* wrtee */
5983 static void gen_wrtee(DisasContext *ctx)
5984 {
5985 #if defined(CONFIG_USER_ONLY)
5986 GEN_PRIV;
5987 #else
5988 TCGv t0;
5989
5990 CHK_SV;
5991 t0 = tcg_temp_new();
5992 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5993 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5994 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5995 tcg_temp_free(t0);
5996 /* Stop translation to have a chance to raise an exception
5997 * if we just set msr_ee to 1
5998 */
5999 gen_stop_exception(ctx);
6000 #endif /* defined(CONFIG_USER_ONLY) */
6001 }
6002
6003 /* wrteei */
6004 static void gen_wrteei(DisasContext *ctx)
6005 {
6006 #if defined(CONFIG_USER_ONLY)
6007 GEN_PRIV;
6008 #else
6009 CHK_SV;
6010 if (ctx->opcode & 0x00008000) {
6011 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6012 /* Stop translation to have a chance to raise an exception */
6013 gen_stop_exception(ctx);
6014 } else {
6015 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6016 }
6017 #endif /* defined(CONFIG_USER_ONLY) */
6018 }
6019
6020 /* PowerPC 440 specific instructions */
6021
6022 /* dlmzb */
6023 static void gen_dlmzb(DisasContext *ctx)
6024 {
6025 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6026 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6027 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6028 tcg_temp_free_i32(t0);
6029 }
6030
6031 /* mbar replaces eieio on 440 */
6032 static void gen_mbar(DisasContext *ctx)
6033 {
6034 /* interpreted as no-op */
6035 }
6036
6037 /* msync replaces sync on 440 */
6038 static void gen_msync_4xx(DisasContext *ctx)
6039 {
6040 /* interpreted as no-op */
6041 }
6042
6043 /* icbt */
6044 static void gen_icbt_440(DisasContext *ctx)
6045 {
6046 /* interpreted as no-op */
6047 /* XXX: specification say this is treated as a load by the MMU
6048 * but does not generate any exception
6049 */
6050 }
6051
6052 /* Embedded.Processor Control */
6053
6054 static void gen_msgclr(DisasContext *ctx)
6055 {
6056 #if defined(CONFIG_USER_ONLY)
6057 GEN_PRIV;
6058 #else
6059 CHK_SV;
6060 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6061 #endif /* defined(CONFIG_USER_ONLY) */
6062 }
6063
6064 static void gen_msgsnd(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 GEN_PRIV;
6068 #else
6069 CHK_SV;
6070 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6071 #endif /* defined(CONFIG_USER_ONLY) */
6072 }
6073
6074
6075 #if defined(TARGET_PPC64)
6076 static void gen_maddld(DisasContext *ctx)
6077 {
6078 TCGv_i64 t1 = tcg_temp_new_i64();
6079
6080 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6081 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6082 tcg_temp_free_i64(t1);
6083 }
6084
6085 /* maddhd maddhdu */
6086 static void gen_maddhd_maddhdu(DisasContext *ctx)
6087 {
6088 TCGv_i64 lo = tcg_temp_new_i64();
6089 TCGv_i64 hi = tcg_temp_new_i64();
6090 TCGv_i64 t1 = tcg_temp_new_i64();
6091
6092 if (Rc(ctx->opcode)) {
6093 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6094 cpu_gpr[rB(ctx->opcode)]);
6095 tcg_gen_movi_i64(t1, 0);
6096 } else {
6097 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6098 cpu_gpr[rB(ctx->opcode)]);
6099 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6100 }
6101 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6102 cpu_gpr[rC(ctx->opcode)], t1);
6103 tcg_temp_free_i64(lo);
6104 tcg_temp_free_i64(hi);
6105 tcg_temp_free_i64(t1);
6106 }
6107 #endif /* defined(TARGET_PPC64) */
6108
6109 static void gen_tbegin(DisasContext *ctx)
6110 {
6111 if (unlikely(!ctx->tm_enabled)) {
6112 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6113 return;
6114 }
6115 gen_helper_tbegin(cpu_env);
6116 }
6117
6118 #define GEN_TM_NOOP(name) \
6119 static inline void gen_##name(DisasContext *ctx) \
6120 { \
6121 if (unlikely(!ctx->tm_enabled)) { \
6122 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6123 return; \
6124 } \
6125 /* Because tbegin always fails in QEMU, these user \
6126 * space instructions all have a simple implementation: \
6127 * \
6128 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6129 * = 0b0 || 0b00 || 0b0 \
6130 */ \
6131 tcg_gen_movi_i32(cpu_crf[0], 0); \
6132 }
6133
6134 GEN_TM_NOOP(tend);
6135 GEN_TM_NOOP(tabort);
6136 GEN_TM_NOOP(tabortwc);
6137 GEN_TM_NOOP(tabortwci);
6138 GEN_TM_NOOP(tabortdc);
6139 GEN_TM_NOOP(tabortdci);
6140 GEN_TM_NOOP(tsr);
6141
6142 static void gen_tcheck(DisasContext *ctx)
6143 {
6144 if (unlikely(!ctx->tm_enabled)) {
6145 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6146 return;
6147 }
6148 /* Because tbegin always fails, the tcheck implementation
6149 * is simple:
6150 *
6151 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6152 * = 0b1 || 0b00 || 0b0
6153 */
6154 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6155 }
6156
6157 #if defined(CONFIG_USER_ONLY)
6158 #define GEN_TM_PRIV_NOOP(name) \
6159 static inline void gen_##name(DisasContext *ctx) \
6160 { \
6161 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6162 }
6163
6164 #else
6165
6166 #define GEN_TM_PRIV_NOOP(name) \
6167 static inline void gen_##name(DisasContext *ctx) \
6168 { \
6169 CHK_SV; \
6170 if (unlikely(!ctx->tm_enabled)) { \
6171 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6172 return; \
6173 } \
6174 /* Because tbegin always fails, the implementation is \
6175 * simple: \
6176 * \
6177 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6178 * = 0b0 || 0b00 | 0b0 \
6179 */ \
6180 tcg_gen_movi_i32(cpu_crf[0], 0); \
6181 }
6182
6183 #endif
6184
6185 GEN_TM_PRIV_NOOP(treclaim);
6186 GEN_TM_PRIV_NOOP(trechkpt);
6187
6188 #include "translate/fp-impl.inc.c"
6189
6190 #include "translate/vmx-impl.inc.c"
6191
6192 #include "translate/vsx-impl.inc.c"
6193
6194 #include "translate/dfp-impl.inc.c"
6195
6196 #include "translate/spe-impl.inc.c"
6197
6198 static opcode_t opcodes[] = {
6199 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6200 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6201 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6202 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6203 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6204 #if defined(TARGET_PPC64)
6205 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6206 #endif
6207 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6208 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6209 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6210 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6211 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6212 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6213 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6214 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6215 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6216 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6217 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6218 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6219 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6220 #if defined(TARGET_PPC64)
6221 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6222 #endif
6223 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6224 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6225 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6226 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6227 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6228 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6229 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6230 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6231 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6232 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6233 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6234 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6235 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6236 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6237 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6238 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6239 #if defined(TARGET_PPC64)
6240 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6241 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6242 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6243 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6244 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6245 #endif
6246 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6247 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6248 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6249 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6250 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6251 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6252 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6253 #if defined(TARGET_PPC64)
6254 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6255 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6256 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6257 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6258 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6259 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6260 PPC_NONE, PPC2_ISA300),
6261 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6262 PPC_NONE, PPC2_ISA300),
6263 #endif
6264 #if defined(TARGET_PPC64)
6265 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6266 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6267 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6268 #endif
6269 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6270 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6271 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6272 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6273 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6274 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6275 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6276 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6277 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6278 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6279 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6280 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6281 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6282 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6283 #if defined(TARGET_PPC64)
6284 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6285 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6286 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6287 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6288 #endif
6289 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6290 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6291 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6292 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6293 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6294 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6295 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6296 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6297 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6298 #if defined(TARGET_PPC64)
6299 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6300 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6301 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6302 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6303 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6304 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6305 #endif
6306 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6307 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6308 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6309 #if defined(TARGET_PPC64)
6310 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6311 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6312 #endif
6313 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6314 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6315 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6316 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6317 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6318 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6319 #if defined(TARGET_PPC64)
6320 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6321 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6322 #endif
6323 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6324 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6325 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6326 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6327 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6328 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6329 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6330 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6331 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6332 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6333 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6334 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6335 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6336 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6337 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6338 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6339 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6340 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6341 #if defined(TARGET_PPC64)
6342 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6343 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6344 PPC_SEGMENT_64B),
6345 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6346 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6347 PPC_SEGMENT_64B),
6348 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6349 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6350 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6351 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6352 #endif
6353 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6354 /* XXX Those instructions will need to be handled differently for
6355 * different ISA versions */
6356 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6357 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6358 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6359 #if defined(TARGET_PPC64)
6360 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6361 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6362 #endif
6363 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6364 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6365 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6366 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6367 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6368 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6369 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6370 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6371 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6372 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6373 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6374 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6375 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6376 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6377 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6378 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6379 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6380 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6381 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6382 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6383 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6384 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6385 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6386 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6387 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6388 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6389 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6390 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6391 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6392 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6393 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6394 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6395 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6396 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6397 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6398 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6399 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6400 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6401 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6402 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6403 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6404 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6405 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6406 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6407 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6408 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6409 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6410 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6411 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6412 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6413 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6414 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6415 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6416 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6417 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6418 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6419 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6420 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6421 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6422 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6423 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6424 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6425 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6426 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6427 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6428 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6429 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6430 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6431 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6432 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6433 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6434 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6435 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6436 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6437 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6438 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6439 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6440 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6441 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6442 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6443 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6444 PPC_NONE, PPC2_BOOKE206),
6445 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6446 PPC_NONE, PPC2_BOOKE206),
6447 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6448 PPC_NONE, PPC2_BOOKE206),
6449 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6450 PPC_NONE, PPC2_BOOKE206),
6451 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6452 PPC_NONE, PPC2_BOOKE206),
6453 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6454 PPC_NONE, PPC2_PRCNTL),
6455 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6456 PPC_NONE, PPC2_PRCNTL),
6457 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6458 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6459 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6460 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6461 PPC_BOOKE, PPC2_BOOKE206),
6462 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6463 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6464 PPC_BOOKE, PPC2_BOOKE206),
6465 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6466 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6467 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6468 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6469 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6470 #if defined(TARGET_PPC64)
6471 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6472 PPC2_ISA300),
6473 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6474 #endif
6475
6476 #undef GEN_INT_ARITH_ADD
6477 #undef GEN_INT_ARITH_ADD_CONST
6478 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6479 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6480 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6481 add_ca, compute_ca, compute_ov) \
6482 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6483 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6484 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6485 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6486 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6487 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6488 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6489 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6490 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6491 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6492 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6493
6494 #undef GEN_INT_ARITH_DIVW
6495 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6496 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6497 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6498 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6499 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6500 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6501 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6502 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6503 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6504 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6505 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6506 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6507
6508 #if defined(TARGET_PPC64)
6509 #undef GEN_INT_ARITH_DIVD
6510 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6511 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6512 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6513 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6514 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6515 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6516
6517 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6518 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6519 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6520 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6521 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6522 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6523
6524 #undef GEN_INT_ARITH_MUL_HELPER
6525 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6526 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6527 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6528 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6529 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6530 #endif
6531
6532 #undef GEN_INT_ARITH_SUBF
6533 #undef GEN_INT_ARITH_SUBF_CONST
6534 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6535 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6536 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6537 add_ca, compute_ca, compute_ov) \
6538 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6539 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6540 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6541 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6542 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6543 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6544 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6545 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6546 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6547 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6548 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6549
6550 #undef GEN_LOGICAL1
6551 #undef GEN_LOGICAL2
6552 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6553 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6554 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6555 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6556 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6557 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6558 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6559 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6560 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6561 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6562 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6563 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6564 #if defined(TARGET_PPC64)
6565 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6566 #endif
6567
6568 #if defined(TARGET_PPC64)
6569 #undef GEN_PPC64_R2
6570 #undef GEN_PPC64_R4
6571 #define GEN_PPC64_R2(name, opc1, opc2) \
6572 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6573 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6574 PPC_64B)
6575 #define GEN_PPC64_R4(name, opc1, opc2) \
6576 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6577 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6578 PPC_64B), \
6579 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6580 PPC_64B), \
6581 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6582 PPC_64B)
6583 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6584 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6585 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6586 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6587 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6588 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6589 #endif
6590
6591 #undef GEN_LD
6592 #undef GEN_LDU
6593 #undef GEN_LDUX
6594 #undef GEN_LDX_E
6595 #undef GEN_LDS
6596 #define GEN_LD(name, ldop, opc, type) \
6597 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6598 #define GEN_LDU(name, ldop, opc, type) \
6599 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6600 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6601 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6602 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6603 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6604 #define GEN_LDS(name, ldop, op, type) \
6605 GEN_LD(name, ldop, op | 0x20, type) \
6606 GEN_LDU(name, ldop, op | 0x21, type) \
6607 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6608 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6609
6610 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6611 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6612 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6613 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6614 #if defined(TARGET_PPC64)
6615 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6616 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6617 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6618 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6619 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6620
6621 /* HV/P7 and later only */
6622 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6623 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6624 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6625 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6626 #endif
6627 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6628 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6629
6630 #undef GEN_ST
6631 #undef GEN_STU
6632 #undef GEN_STUX
6633 #undef GEN_STX_E
6634 #undef GEN_STS
6635 #define GEN_ST(name, stop, opc, type) \
6636 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6637 #define GEN_STU(name, stop, opc, type) \
6638 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6639 #define GEN_STUX(name, stop, opc2, opc3, type) \
6640 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6641 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6642 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6643 #define GEN_STS(name, stop, op, type) \
6644 GEN_ST(name, stop, op | 0x20, type) \
6645 GEN_STU(name, stop, op | 0x21, type) \
6646 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6647 GEN_STX(name, stop, 0x17, op | 0x00, type)
6648
6649 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6650 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6651 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6652 #if defined(TARGET_PPC64)
6653 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6654 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6655 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6656 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6657 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6658 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6659 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6660 #endif
6661 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6662 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6663
6664 #undef GEN_CRLOGIC
6665 #define GEN_CRLOGIC(name, tcg_op, opc) \
6666 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6667 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6668 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6669 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6670 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6671 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6672 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6673 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6674 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6675
6676 #undef GEN_MAC_HANDLER
6677 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6678 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6679 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6680 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6681 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6682 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6683 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6684 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6685 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6686 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6687 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6688 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6689 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6690 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6691 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6692 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6693 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6694 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6695 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6696 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6697 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6698 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6699 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6700 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6701 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6702 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6703 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6704 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6705 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6706 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6707 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6708 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6709 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6710 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6711 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6712 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6713 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6714 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6715 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6716 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6717 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6718 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6719 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6720 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6721
6722 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6723 PPC_NONE, PPC2_TM),
6724 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6725 PPC_NONE, PPC2_TM),
6726 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6727 PPC_NONE, PPC2_TM),
6728 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6729 PPC_NONE, PPC2_TM),
6730 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6731 PPC_NONE, PPC2_TM),
6732 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6733 PPC_NONE, PPC2_TM),
6734 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6735 PPC_NONE, PPC2_TM),
6736 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6737 PPC_NONE, PPC2_TM),
6738 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6739 PPC_NONE, PPC2_TM),
6740 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6741 PPC_NONE, PPC2_TM),
6742 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6743 PPC_NONE, PPC2_TM),
6744
6745 #include "translate/fp-ops.inc.c"
6746
6747 #include "translate/vmx-ops.inc.c"
6748
6749 #include "translate/vsx-ops.inc.c"
6750
6751 #include "translate/dfp-ops.inc.c"
6752
6753 #include "translate/spe-ops.inc.c"
6754 };
6755
6756 #include "helper_regs.h"
6757 #include "translate_init.c"
6758
6759 /*****************************************************************************/
6760 /* Misc PowerPC helpers */
6761 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6762 int flags)
6763 {
6764 #define RGPL 4
6765 #define RFPL 4
6766
6767 PowerPCCPU *cpu = POWERPC_CPU(cs);
6768 CPUPPCState *env = &cpu->env;
6769 int i;
6770
6771 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6772 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6773 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6774 cs->cpu_index);
6775 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6776 TARGET_FMT_lx " iidx %d didx %d\n",
6777 env->msr, env->spr[SPR_HID0],
6778 env->hflags, env->immu_idx, env->dmmu_idx);
6779 #if !defined(NO_TIMER_DUMP)
6780 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6781 #if !defined(CONFIG_USER_ONLY)
6782 " DECR %08" PRIu32
6783 #endif
6784 "\n",
6785 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6786 #if !defined(CONFIG_USER_ONLY)
6787 , cpu_ppc_load_decr(env)
6788 #endif
6789 );
6790 #endif
6791 for (i = 0; i < 32; i++) {
6792 if ((i & (RGPL - 1)) == 0)
6793 cpu_fprintf(f, "GPR%02d", i);
6794 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6795 if ((i & (RGPL - 1)) == (RGPL - 1))
6796 cpu_fprintf(f, "\n");
6797 }
6798 cpu_fprintf(f, "CR ");
6799 for (i = 0; i < 8; i++)
6800 cpu_fprintf(f, "%01x", env->crf[i]);
6801 cpu_fprintf(f, " [");
6802 for (i = 0; i < 8; i++) {
6803 char a = '-';
6804 if (env->crf[i] & 0x08)
6805 a = 'L';
6806 else if (env->crf[i] & 0x04)
6807 a = 'G';
6808 else if (env->crf[i] & 0x02)
6809 a = 'E';
6810 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6811 }
6812 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6813 env->reserve_addr);
6814 for (i = 0; i < 32; i++) {
6815 if ((i & (RFPL - 1)) == 0)
6816 cpu_fprintf(f, "FPR%02d", i);
6817 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6818 if ((i & (RFPL - 1)) == (RFPL - 1))
6819 cpu_fprintf(f, "\n");
6820 }
6821 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6822 #if !defined(CONFIG_USER_ONLY)
6823 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6824 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6825 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6826 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6827
6828 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6829 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6830 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6831 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6832
6833 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6834 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6835 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6836 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6837
6838 #if defined(TARGET_PPC64)
6839 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6840 env->excp_model == POWERPC_EXCP_POWER8) {
6841 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6842 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6843 }
6844 #endif
6845 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6846 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6847 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6848 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6849 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6850
6851 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6852 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6853 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6854 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6855
6856 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6857 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6858 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6859 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6860
6861 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6862 " EPR " TARGET_FMT_lx "\n",
6863 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6864 env->spr[SPR_BOOKE_EPR]);
6865
6866 /* FSL-specific */
6867 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6868 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6869 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6870 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6871
6872 /*
6873 * IVORs are left out as they are large and do not change often --
6874 * they can be read with "p $ivor0", "p $ivor1", etc.
6875 */
6876 }
6877
6878 #if defined(TARGET_PPC64)
6879 if (env->flags & POWERPC_FLAG_CFAR) {
6880 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6881 }
6882 #endif
6883
6884 switch (env->mmu_model) {
6885 case POWERPC_MMU_32B:
6886 case POWERPC_MMU_601:
6887 case POWERPC_MMU_SOFT_6xx:
6888 case POWERPC_MMU_SOFT_74xx:
6889 #if defined(TARGET_PPC64)
6890 case POWERPC_MMU_64B:
6891 case POWERPC_MMU_2_03:
6892 case POWERPC_MMU_2_06:
6893 case POWERPC_MMU_2_06a:
6894 case POWERPC_MMU_2_07:
6895 case POWERPC_MMU_2_07a:
6896 #endif
6897 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6898 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6899 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6900 break;
6901 case POWERPC_MMU_BOOKE206:
6902 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6903 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6904 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6905 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6906
6907 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6908 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6909 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6910 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6911
6912 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6913 " TLB1CFG " TARGET_FMT_lx "\n",
6914 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6915 env->spr[SPR_BOOKE_TLB1CFG]);
6916 break;
6917 default:
6918 break;
6919 }
6920 #endif
6921
6922 #undef RGPL
6923 #undef RFPL
6924 }
6925
6926 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6927 fprintf_function cpu_fprintf, int flags)
6928 {
6929 #if defined(DO_PPC_STATISTICS)
6930 PowerPCCPU *cpu = POWERPC_CPU(cs);
6931 opc_handler_t **t1, **t2, **t3, *handler;
6932 int op1, op2, op3;
6933
6934 t1 = cpu->env.opcodes;
6935 for (op1 = 0; op1 < 64; op1++) {
6936 handler = t1[op1];
6937 if (is_indirect_opcode(handler)) {
6938 t2 = ind_table(handler);
6939 for (op2 = 0; op2 < 32; op2++) {
6940 handler = t2[op2];
6941 if (is_indirect_opcode(handler)) {
6942 t3 = ind_table(handler);
6943 for (op3 = 0; op3 < 32; op3++) {
6944 handler = t3[op3];
6945 if (handler->count == 0)
6946 continue;
6947 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6948 "%016" PRIx64 " %" PRId64 "\n",
6949 op1, op2, op3, op1, (op3 << 5) | op2,
6950 handler->oname,
6951 handler->count, handler->count);
6952 }
6953 } else {
6954 if (handler->count == 0)
6955 continue;
6956 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6957 "%016" PRIx64 " %" PRId64 "\n",
6958 op1, op2, op1, op2, handler->oname,
6959 handler->count, handler->count);
6960 }
6961 }
6962 } else {
6963 if (handler->count == 0)
6964 continue;
6965 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6966 " %" PRId64 "\n",
6967 op1, op1, handler->oname,
6968 handler->count, handler->count);
6969 }
6970 }
6971 #endif
6972 }
6973
6974 /*****************************************************************************/
6975 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6976 {
6977 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6978 CPUState *cs = CPU(cpu);
6979 DisasContext ctx, *ctxp = &ctx;
6980 opc_handler_t **table, *handler;
6981 target_ulong pc_start;
6982 int num_insns;
6983 int max_insns;
6984
6985 pc_start = tb->pc;
6986 ctx.nip = pc_start;
6987 ctx.tb = tb;
6988 ctx.exception = POWERPC_EXCP_NONE;
6989 ctx.spr_cb = env->spr_cb;
6990 ctx.pr = msr_pr;
6991 ctx.mem_idx = env->dmmu_idx;
6992 ctx.dr = msr_dr;
6993 #if !defined(CONFIG_USER_ONLY)
6994 ctx.hv = msr_hv || !env->has_hv_mode;
6995 #endif
6996 ctx.insns_flags = env->insns_flags;
6997 ctx.insns_flags2 = env->insns_flags2;
6998 ctx.access_type = -1;
6999 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7000 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7001 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7002 #if defined(TARGET_PPC64)
7003 ctx.sf_mode = msr_is_64bit(env, env->msr);
7004 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7005 #endif
7006 if (env->mmu_model == POWERPC_MMU_32B ||
7007 env->mmu_model == POWERPC_MMU_601 ||
7008 (env->mmu_model & POWERPC_MMU_64B))
7009 ctx.lazy_tlb_flush = true;
7010
7011 ctx.fpu_enabled = !!msr_fp;
7012 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7013 ctx.spe_enabled = !!msr_spe;
7014 else
7015 ctx.spe_enabled = false;
7016 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7017 ctx.altivec_enabled = !!msr_vr;
7018 else
7019 ctx.altivec_enabled = false;
7020 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7021 ctx.vsx_enabled = !!msr_vsx;
7022 } else {
7023 ctx.vsx_enabled = false;
7024 }
7025 #if defined(TARGET_PPC64)
7026 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7027 ctx.tm_enabled = !!msr_tm;
7028 } else {
7029 ctx.tm_enabled = false;
7030 }
7031 #endif
7032 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7033 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7034 else
7035 ctx.singlestep_enabled = 0;
7036 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7037 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7038 if (unlikely(cs->singlestep_enabled)) {
7039 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7040 }
7041 #if defined (DO_SINGLE_STEP) && 0
7042 /* Single step trace mode */
7043 msr_se = 1;
7044 #endif
7045 num_insns = 0;
7046 max_insns = tb->cflags & CF_COUNT_MASK;
7047 if (max_insns == 0) {
7048 max_insns = CF_COUNT_MASK;
7049 }
7050 if (max_insns > TCG_MAX_INSNS) {
7051 max_insns = TCG_MAX_INSNS;
7052 }
7053
7054 gen_tb_start(tb);
7055 tcg_clear_temp_count();
7056 /* Set env in case of segfault during code fetch */
7057 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7058 tcg_gen_insn_start(ctx.nip);
7059 num_insns++;
7060
7061 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7062 gen_debug_exception(ctxp);
7063 /* The address covered by the breakpoint must be included in
7064 [tb->pc, tb->pc + tb->size) in order to for it to be
7065 properly cleared -- thus we increment the PC here so that
7066 the logic setting tb->size below does the right thing. */
7067 ctx.nip += 4;
7068 break;
7069 }
7070
7071 LOG_DISAS("----------------\n");
7072 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7073 ctx.nip, ctx.mem_idx, (int)msr_ir);
7074 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7075 gen_io_start();
7076 if (unlikely(need_byteswap(&ctx))) {
7077 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7078 } else {
7079 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7080 }
7081 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7082 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7083 opc3(ctx.opcode), opc4(ctx.opcode),
7084 ctx.le_mode ? "little" : "big");
7085 ctx.nip += 4;
7086 table = env->opcodes;
7087 handler = table[opc1(ctx.opcode)];
7088 if (is_indirect_opcode(handler)) {
7089 table = ind_table(handler);
7090 handler = table[opc2(ctx.opcode)];
7091 if (is_indirect_opcode(handler)) {
7092 table = ind_table(handler);
7093 handler = table[opc3(ctx.opcode)];
7094 if (is_indirect_opcode(handler)) {
7095 table = ind_table(handler);
7096 handler = table[opc4(ctx.opcode)];
7097 }
7098 }
7099 }
7100 /* Is opcode *REALLY* valid ? */
7101 if (unlikely(handler->handler == &gen_invalid)) {
7102 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7103 "%02x - %02x - %02x - %02x (%08x) "
7104 TARGET_FMT_lx " %d\n",
7105 opc1(ctx.opcode), opc2(ctx.opcode),
7106 opc3(ctx.opcode), opc4(ctx.opcode),
7107 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7108 } else {
7109 uint32_t inval;
7110
7111 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7112 inval = handler->inval2;
7113 } else {
7114 inval = handler->inval1;
7115 }
7116
7117 if (unlikely((ctx.opcode & inval) != 0)) {
7118 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7119 "%02x - %02x - %02x - %02x (%08x) "
7120 TARGET_FMT_lx "\n", ctx.opcode & inval,
7121 opc1(ctx.opcode), opc2(ctx.opcode),
7122 opc3(ctx.opcode), opc4(ctx.opcode),
7123 ctx.opcode, ctx.nip - 4);
7124 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7125 break;
7126 }
7127 }
7128 (*(handler->handler))(&ctx);
7129 #if defined(DO_PPC_STATISTICS)
7130 handler->count++;
7131 #endif
7132 /* Check trace mode exceptions */
7133 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7134 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7135 ctx.exception != POWERPC_SYSCALL &&
7136 ctx.exception != POWERPC_EXCP_TRAP &&
7137 ctx.exception != POWERPC_EXCP_BRANCH)) {
7138 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7139 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7140 (cs->singlestep_enabled) ||
7141 singlestep ||
7142 num_insns >= max_insns)) {
7143 /* if we reach a page boundary or are single stepping, stop
7144 * generation
7145 */
7146 break;
7147 }
7148 if (tcg_check_temp_count()) {
7149 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7150 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7151 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7152 exit(1);
7153 }
7154 }
7155 if (tb->cflags & CF_LAST_IO)
7156 gen_io_end();
7157 if (ctx.exception == POWERPC_EXCP_NONE) {
7158 gen_goto_tb(&ctx, 0, ctx.nip);
7159 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7160 if (unlikely(cs->singlestep_enabled)) {
7161 gen_debug_exception(ctxp);
7162 }
7163 /* Generate the return instruction */
7164 tcg_gen_exit_tb(0);
7165 }
7166 gen_tb_end(tb, num_insns);
7167
7168 tb->size = ctx.nip - pc_start;
7169 tb->icount = num_insns;
7170
7171 #if defined(DEBUG_DISAS)
7172 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7173 && qemu_log_in_addr_range(pc_start)) {
7174 int flags;
7175 flags = env->bfd_mach;
7176 flags |= ctx.le_mode << 16;
7177 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7178 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7179 qemu_log("\n");
7180 }
7181 #endif
7182 }
7183
7184 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7185 target_ulong *data)
7186 {
7187 env->nip = data[0];
7188 }
AR7 emulation for QEMU