ide: Update command code definitions as per ACS-2 Table B.2
[qemu/ar7.git] / hw / realview_gic.c
blobcd6a44d9d0a4506494ca2fa38a32c79bb6605509
1 /*
2 * ARM RealView Emulation Baseboard Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 #include "sysbus.h"
12 #define GIC_NIRQ 96
13 #define NCPU 1
15 /* Only a single "CPU" interface is present. */
16 static inline int
17 gic_get_current_cpu(void)
19 return 0;
22 #include "arm_gic.c"
24 typedef struct {
25 gic_state gic;
26 MemoryRegion iomem;
27 MemoryRegion container;
28 } RealViewGICState;
30 static uint64_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset,
31 unsigned size)
33 gic_state *s = (gic_state *)opaque;
34 return gic_cpu_read(s, gic_get_current_cpu(), offset);
37 static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
38 uint64_t value, unsigned size)
40 gic_state *s = (gic_state *)opaque;
41 gic_cpu_write(s, gic_get_current_cpu(), offset, value);
44 static const MemoryRegionOps realview_gic_cpu_ops = {
45 .read = realview_gic_cpu_read,
46 .write = realview_gic_cpu_write,
47 .endianness = DEVICE_NATIVE_ENDIAN,
50 static void realview_gic_map_setup(RealViewGICState *s)
52 memory_region_init(&s->container, "realview-gic-container", 0x2000);
53 memory_region_init_io(&s->iomem, &realview_gic_cpu_ops, &s->gic,
54 "realview-gic", 0x1000);
55 memory_region_add_subregion(&s->container, 0, &s->iomem);
56 memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
59 static int realview_gic_init(SysBusDevice *dev)
61 RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
63 gic_init(&s->gic);
64 realview_gic_map_setup(s);
65 sysbus_init_mmio_region(dev, &s->container);
66 return 0;
69 static void realview_gic_register_devices(void)
71 sysbus_register_dev("realview_gic", sizeof(RealViewGICState),
72 realview_gic_init);
75 device_init(realview_gic_register_devices)