hw/display/cg3.c

   1 /*
   2  * QEMU CG3 Frame buffer
   3  *
   4  * Copyright (c) 2012 Bob Breuer
   5  * Copyright (c) 2013 Mark Cave-Ayland
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "qemu/error-report.h"
  31 #include "ui/console.h"
  32 #include "hw/sysbus.h"
  33 #include "hw/loader.h"
  34 #include "qemu/log.h"
  35
  36 /* Change to 1 to enable debugging */
  37 #define DEBUG_CG3 0
  38
  39 #define CG3_ROM_FILE  "QEMU,cgthree.bin"
  40 #define FCODE_MAX_ROM_SIZE 0x10000
  41
  42 #define CG3_REG_SIZE            0x20
  43
  44 #define CG3_REG_BT458_ADDR      0x0
  45 #define CG3_REG_BT458_COLMAP    0x4
  46 #define CG3_REG_FBC_CTRL        0x10
  47 #define CG3_REG_FBC_STATUS      0x11
  48 #define CG3_REG_FBC_CURSTART    0x12
  49 #define CG3_REG_FBC_CUREND      0x13
  50 #define CG3_REG_FBC_VCTRL       0x14
  51
  52 /* Control register flags */
  53 #define CG3_CR_ENABLE_INTS      0x80
  54
  55 /* Status register flags */
  56 #define CG3_SR_PENDING_INT      0x80
  57 #define CG3_SR_1152_900_76_B    0x60
  58 #define CG3_SR_ID_COLOR         0x01
  59
  60 #define CG3_VRAM_SIZE 0x100000
  61 #define CG3_VRAM_OFFSET 0x800000
  62
  63 #define DPRINTF(fmt, ...) do { \
  64     if (DEBUG_CG3) { \
  65         printf("CG3: " fmt , ## __VA_ARGS__); \
  66     } \
  67 } while (0);
  68
  69 #define TYPE_CG3 "cgthree"
  70 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
  71
  72 typedef struct CG3State {
  73     SysBusDevice parent_obj;
  74
  75     QemuConsole *con;
  76     qemu_irq irq;
  77     hwaddr prom_addr;
  78     MemoryRegion vram_mem;
  79     MemoryRegion rom;
  80     MemoryRegion reg;
  81     uint32_t vram_size;
  82     int full_update;
  83     uint8_t regs[16];
  84     uint8_t r[256], g[256], b[256];
  85     uint16_t width, height, depth;
  86     uint8_t dac_index, dac_state;
  87 } CG3State;
  88
  89 static void cg3_update_display(void *opaque)
  90 {
  91     CG3State *s = opaque;
  92     DisplaySurface *surface = qemu_console_surface(s->con);
  93     const uint8_t *pix;
  94     uint32_t *data;
  95     uint32_t dval;
  96     int x, y, y_start;
  97     unsigned int width, height;
  98     ram_addr_t page, page_min, page_max;
  99
 100     if (surface_bits_per_pixel(surface) != 32) {
 101         return;
 102     }
 103     width = s->width;
 104     height = s->height;
 105
 106     y_start = -1;
 107     page_min = -1;
 108     page_max = 0;
 109     page = 0;
 110     pix = memory_region_get_ram_ptr(&s->vram_mem);
 111     data = (uint32_t *)surface_data(surface);
 112
 113     memory_region_sync_dirty_bitmap(&s->vram_mem);
 114     for (y = 0; y < height; y++) {
 115         int update = s->full_update;
 116
 117         page = (y * width) & TARGET_PAGE_MASK;
 118         update |= memory_region_get_dirty(&s->vram_mem, page, page + width,
 119                                           DIRTY_MEMORY_VGA);
 120         if (update) {
 121             if (y_start < 0) {
 122                 y_start = y;
 123             }
 124             if (page < page_min) {
 125                 page_min = page;
 126             }
 127             if (page > page_max) {
 128                 page_max = page;
 129             }
 130
 131             for (x = 0; x < width; x++) {
 132                 dval = *pix++;
 133                 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
 134                 *data++ = dval;
 135             }
 136         } else {
 137             if (y_start >= 0) {
 138                 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
 139                 y_start = -1;
 140             }
 141             pix += width;
 142             data += width;
 143         }
 144     }
 145     s->full_update = 0;
 146     if (y_start >= 0) {
 147         dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
 148     }
 149     if (page_max >= page_min) {
 150         memory_region_reset_dirty(&s->vram_mem,
 151                               page_min, page_max - page_min + TARGET_PAGE_SIZE,
 152                               DIRTY_MEMORY_VGA);
 153     }
 154     /* vsync interrupt? */
 155     if (s->regs[0] & CG3_CR_ENABLE_INTS) {
 156         s->regs[1] |= CG3_SR_PENDING_INT;
 157         qemu_irq_raise(s->irq);
 158     }
 159 }
 160
 161 static void cg3_invalidate_display(void *opaque)
 162 {
 163     CG3State *s = opaque;
 164
 165     memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
 166 }
 167
 168 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
 169 {
 170     CG3State *s = opaque;
 171     int val;
 172
 173     switch (addr) {
 174     case CG3_REG_BT458_ADDR:
 175     case CG3_REG_BT458_COLMAP:
 176         val = 0;
 177         break;
 178     case CG3_REG_FBC_CTRL:
 179         val = s->regs[0];
 180         break;
 181     case CG3_REG_FBC_STATUS:
 182         /* monitor ID 6, board type = 1 (color) */
 183         val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
 184         break;
 185     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
 186         val = s->regs[addr - 0x10];
 187         break;
 188     default:
 189         qemu_log_mask(LOG_UNIMP,
 190                   "cg3: Unimplemented register read "
 191                   "reg 0x%" HWADDR_PRIx " size 0x%x\n",
 192                   addr, size);
 193         val = 0;
 194         break;
 195     }
 196     DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
 197     return val;
 198 }
 199
 200 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
 201                           unsigned size)
 202 {
 203     CG3State *s = opaque;
 204     uint8_t regval;
 205     int i;
 206
 207     DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
 208             val, addr, size);
 209
 210     switch (addr) {
 211     case CG3_REG_BT458_ADDR:
 212         s->dac_index = val;
 213         s->dac_state = 0;
 214         break;
 215     case CG3_REG_BT458_COLMAP:
 216         /* This register can be written to as either a long word or a byte */
 217         if (size == 1) {
 218             val <<= 24;
 219         }
 220
 221         for (i = 0; i < size; i++) {
 222             regval = val >> 24;
 223
 224             switch (s->dac_state) {
 225             case 0:
 226                 s->r[s->dac_index] = regval;
 227                 s->dac_state++;
 228                 break;
 229             case 1:
 230                 s->g[s->dac_index] = regval;
 231                 s->dac_state++;
 232                 break;
 233             case 2:
 234                 s->b[s->dac_index] = regval;
 235                 /* Index autoincrement */
 236                 s->dac_index = (s->dac_index + 1) & 0xff;
 237             default:
 238                 s->dac_state = 0;
 239                 break;
 240             }
 241             val <<= 8;
 242         }
 243         s->full_update = 1;
 244         break;
 245     case CG3_REG_FBC_CTRL:
 246         s->regs[0] = val;
 247         break;
 248     case CG3_REG_FBC_STATUS:
 249         if (s->regs[1] & CG3_SR_PENDING_INT) {
 250             /* clear interrupt */
 251             s->regs[1] &= ~CG3_SR_PENDING_INT;
 252             qemu_irq_lower(s->irq);
 253         }
 254         break;
 255     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
 256         s->regs[addr - 0x10] = val;
 257         break;
 258     default:
 259         qemu_log_mask(LOG_UNIMP,
 260                   "cg3: Unimplemented register write "
 261                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
 262                   addr, size, val);
 263         break;
 264     }
 265 }
 266
 267 static const MemoryRegionOps cg3_reg_ops = {
 268     .read = cg3_reg_read,
 269     .write = cg3_reg_write,
 270     .endianness = DEVICE_NATIVE_ENDIAN,
 271     .valid = {
 272         .min_access_size = 1,
 273         .max_access_size = 4,
 274     },
 275 };
 276
 277 static const GraphicHwOps cg3_ops = {
 278     .invalidate = cg3_invalidate_display,
 279     .gfx_update = cg3_update_display,
 280 };
 281
 282 static void cg3_initfn(Object *obj)
 283 {
 284     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 285     CG3State *s = CG3(obj);
 286
 287     memory_region_init_ram(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE,
 288                            &error_fatal);
 289     memory_region_set_readonly(&s->rom, true);
 290     sysbus_init_mmio(sbd, &s->rom);
 291
 292     memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",
 293                           CG3_REG_SIZE);
 294     sysbus_init_mmio(sbd, &s->reg);
 295 }
 296
 297 static void cg3_realizefn(DeviceState *dev, Error **errp)
 298 {
 299     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 300     CG3State *s = CG3(dev);
 301     int ret;
 302     char *fcode_filename;
 303
 304     /* FCode ROM */
 305     vmstate_register_ram_global(&s->rom);
 306     fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
 307     if (fcode_filename) {
 308         ret = load_image_targphys(fcode_filename, s->prom_addr,
 309                                   FCODE_MAX_ROM_SIZE);
 310         g_free(fcode_filename);
 311         if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
 312             error_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
 313         }
 314     }
 315
 316     memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,
 317                            &error_fatal);
 318     memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
 319     vmstate_register_ram_global(&s->vram_mem);
 320     sysbus_init_mmio(sbd, &s->vram_mem);
 321
 322     sysbus_init_irq(sbd, &s->irq);
 323
 324     s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s);
 325     qemu_console_resize(s->con, s->width, s->height);
 326 }
 327
 328 static int vmstate_cg3_post_load(void *opaque, int version_id)
 329 {
 330     CG3State *s = opaque;
 331
 332     cg3_invalidate_display(s);
 333
 334     return 0;
 335 }
 336
 337 static const VMStateDescription vmstate_cg3 = {
 338     .name = "cg3",
 339     .version_id = 1,
 340     .minimum_version_id = 1,
 341     .post_load = vmstate_cg3_post_load,
 342     .fields = (VMStateField[]) {
 343         VMSTATE_UINT16(height, CG3State),
 344         VMSTATE_UINT16(width, CG3State),
 345         VMSTATE_UINT16(depth, CG3State),
 346         VMSTATE_BUFFER(r, CG3State),
 347         VMSTATE_BUFFER(g, CG3State),
 348         VMSTATE_BUFFER(b, CG3State),
 349         VMSTATE_UINT8(dac_index, CG3State),
 350         VMSTATE_UINT8(dac_state, CG3State),
 351         VMSTATE_END_OF_LIST()
 352     }
 353 };
 354
 355 static void cg3_reset(DeviceState *d)
 356 {
 357     CG3State *s = CG3(d);
 358
 359     /* Initialize palette */
 360     memset(s->r, 0, 256);
 361     memset(s->g, 0, 256);
 362     memset(s->b, 0, 256);
 363
 364     s->dac_state = 0;
 365     s->full_update = 1;
 366     qemu_irq_lower(s->irq);
 367 }
 368
 369 static Property cg3_properties[] = {
 370     DEFINE_PROP_UINT32("vram-size",    CG3State, vram_size, -1),
 371     DEFINE_PROP_UINT16("width",        CG3State, width,     -1),
 372     DEFINE_PROP_UINT16("height",       CG3State, height,    -1),
 373     DEFINE_PROP_UINT16("depth",        CG3State, depth,     -1),
 374     DEFINE_PROP_UINT64("prom-addr",    CG3State, prom_addr, -1),
 375     DEFINE_PROP_END_OF_LIST(),
 376 };
 377
 378 static void cg3_class_init(ObjectClass *klass, void *data)
 379 {
 380     DeviceClass *dc = DEVICE_CLASS(klass);
 381
 382     dc->realize = cg3_realizefn;
 383     dc->reset = cg3_reset;
 384     dc->vmsd = &vmstate_cg3;
 385     dc->props = cg3_properties;
 386 }
 387
 388 static const TypeInfo cg3_info = {
 389     .name          = TYPE_CG3,
 390     .parent        = TYPE_SYS_BUS_DEVICE,
 391     .instance_size = sizeof(CG3State),
 392     .instance_init = cg3_initfn,
 393     .class_init    = cg3_class_init,
 394 };
 395
 396 static void cg3_register_types(void)
 397 {
 398     type_register_static(&cg3_info);
 399 }
 400
 401 type_init(cg3_register_types)