4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "hw/arm/boot.h"
29 #include "exec/address-spaces.h"
30 #include "hw/arm/stm32f205_soc.h"
31 #include "hw/qdev-properties.h"
32 #include "sysemu/sysemu.h"
34 /* At the moment only Timer 2 to 5 are modelled */
35 static const uint32_t timer_addr
[STM_NUM_TIMERS
] = { 0x40000000, 0x40000400,
36 0x40000800, 0x40000C00 };
37 static const uint32_t usart_addr
[STM_NUM_USARTS
] = { 0x40011000, 0x40004400,
38 0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
39 static const uint32_t adc_addr
[STM_NUM_ADCS
] = { 0x40012000, 0x40012100,
41 static const uint32_t spi_addr
[STM_NUM_SPIS
] = { 0x40013000, 0x40003800,
44 static const int timer_irq
[STM_NUM_TIMERS
] = {28, 29, 30, 50};
45 static const int usart_irq
[STM_NUM_USARTS
] = {37, 38, 39, 52, 53, 71};
47 static const int spi_irq
[STM_NUM_SPIS
] = {35, 36, 51};
49 static void stm32f205_soc_initfn(Object
*obj
)
51 STM32F205State
*s
= STM32F205_SOC(obj
);
54 sysbus_init_child_obj(obj
, "armv7m", &s
->armv7m
, sizeof(s
->armv7m
),
57 sysbus_init_child_obj(obj
, "syscfg", &s
->syscfg
, sizeof(s
->syscfg
),
58 TYPE_STM32F2XX_SYSCFG
);
60 for (i
= 0; i
< STM_NUM_USARTS
; i
++) {
61 sysbus_init_child_obj(obj
, "usart[*]", &s
->usart
[i
],
62 sizeof(s
->usart
[i
]), TYPE_STM32F2XX_USART
);
65 for (i
= 0; i
< STM_NUM_TIMERS
; i
++) {
66 sysbus_init_child_obj(obj
, "timer[*]", &s
->timer
[i
],
67 sizeof(s
->timer
[i
]), TYPE_STM32F2XX_TIMER
);
70 s
->adc_irqs
= OR_IRQ(object_new(TYPE_OR_IRQ
));
72 for (i
= 0; i
< STM_NUM_ADCS
; i
++) {
73 sysbus_init_child_obj(obj
, "adc[*]", &s
->adc
[i
], sizeof(s
->adc
[i
]),
77 for (i
= 0; i
< STM_NUM_SPIS
; i
++) {
78 sysbus_init_child_obj(obj
, "spi[*]", &s
->spi
[i
], sizeof(s
->spi
[i
]),
83 static void stm32f205_soc_realize(DeviceState
*dev_soc
, Error
**errp
)
85 STM32F205State
*s
= STM32F205_SOC(dev_soc
);
86 DeviceState
*dev
, *armv7m
;
91 MemoryRegion
*system_memory
= get_system_memory();
92 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
93 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
94 MemoryRegion
*flash_alias
= g_new(MemoryRegion
, 1);
96 memory_region_init_rom(flash
, OBJECT(dev_soc
), "STM32F205.flash",
97 FLASH_SIZE
, &error_fatal
);
98 memory_region_init_alias(flash_alias
, OBJECT(dev_soc
),
99 "STM32F205.flash.alias", flash
, 0, FLASH_SIZE
);
101 memory_region_add_subregion(system_memory
, FLASH_BASE_ADDRESS
, flash
);
102 memory_region_add_subregion(system_memory
, 0, flash_alias
);
104 memory_region_init_ram(sram
, NULL
, "STM32F205.sram", SRAM_SIZE
,
106 memory_region_add_subregion(system_memory
, SRAM_BASE_ADDRESS
, sram
);
108 armv7m
= DEVICE(&s
->armv7m
);
109 qdev_prop_set_uint32(armv7m
, "num-irq", 96);
110 qdev_prop_set_string(armv7m
, "cpu-type", s
->cpu_type
);
111 qdev_prop_set_bit(armv7m
, "enable-bitband", true);
112 object_property_set_link(OBJECT(&s
->armv7m
), OBJECT(get_system_memory()),
113 "memory", &error_abort
);
114 object_property_set_bool(OBJECT(&s
->armv7m
), true, "realized", &err
);
116 error_propagate(errp
, err
);
120 /* System configuration controller */
121 dev
= DEVICE(&s
->syscfg
);
122 object_property_set_bool(OBJECT(&s
->syscfg
), true, "realized", &err
);
124 error_propagate(errp
, err
);
127 busdev
= SYS_BUS_DEVICE(dev
);
128 sysbus_mmio_map(busdev
, 0, 0x40013800);
129 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(armv7m
, 71));
131 /* Attach UART (uses USART registers) and USART controllers */
132 for (i
= 0; i
< STM_NUM_USARTS
; i
++) {
133 dev
= DEVICE(&(s
->usart
[i
]));
134 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
135 object_property_set_bool(OBJECT(&s
->usart
[i
]), true, "realized", &err
);
137 error_propagate(errp
, err
);
140 busdev
= SYS_BUS_DEVICE(dev
);
141 sysbus_mmio_map(busdev
, 0, usart_addr
[i
]);
142 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(armv7m
, usart_irq
[i
]));
146 for (i
= 0; i
< STM_NUM_TIMERS
; i
++) {
147 dev
= DEVICE(&(s
->timer
[i
]));
148 qdev_prop_set_uint64(dev
, "clock-frequency", 1000000000);
149 object_property_set_bool(OBJECT(&s
->timer
[i
]), true, "realized", &err
);
151 error_propagate(errp
, err
);
154 busdev
= SYS_BUS_DEVICE(dev
);
155 sysbus_mmio_map(busdev
, 0, timer_addr
[i
]);
156 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(armv7m
, timer_irq
[i
]));
160 object_property_set_int(OBJECT(s
->adc_irqs
), STM_NUM_ADCS
,
162 object_property_set_bool(OBJECT(s
->adc_irqs
), true, "realized", &err
);
164 error_propagate(errp
, err
);
167 qdev_connect_gpio_out(DEVICE(s
->adc_irqs
), 0,
168 qdev_get_gpio_in(armv7m
, ADC_IRQ
));
170 for (i
= 0; i
< STM_NUM_ADCS
; i
++) {
171 dev
= DEVICE(&(s
->adc
[i
]));
172 object_property_set_bool(OBJECT(&s
->adc
[i
]), true, "realized", &err
);
174 error_propagate(errp
, err
);
177 busdev
= SYS_BUS_DEVICE(dev
);
178 sysbus_mmio_map(busdev
, 0, adc_addr
[i
]);
179 sysbus_connect_irq(busdev
, 0,
180 qdev_get_gpio_in(DEVICE(s
->adc_irqs
), i
));
184 for (i
= 0; i
< STM_NUM_SPIS
; i
++) {
185 dev
= DEVICE(&(s
->spi
[i
]));
186 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized", &err
);
188 error_propagate(errp
, err
);
191 busdev
= SYS_BUS_DEVICE(dev
);
192 sysbus_mmio_map(busdev
, 0, spi_addr
[i
]);
193 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(armv7m
, spi_irq
[i
]));
197 static Property stm32f205_soc_properties
[] = {
198 DEFINE_PROP_STRING("cpu-type", STM32F205State
, cpu_type
),
199 DEFINE_PROP_END_OF_LIST(),
202 static void stm32f205_soc_class_init(ObjectClass
*klass
, void *data
)
204 DeviceClass
*dc
= DEVICE_CLASS(klass
);
206 dc
->realize
= stm32f205_soc_realize
;
207 device_class_set_props(dc
, stm32f205_soc_properties
);
210 static const TypeInfo stm32f205_soc_info
= {
211 .name
= TYPE_STM32F205_SOC
,
212 .parent
= TYPE_SYS_BUS_DEVICE
,
213 .instance_size
= sizeof(STM32F205State
),
214 .instance_init
= stm32f205_soc_initfn
,
215 .class_init
= stm32f205_soc_class_init
,
218 static void stm32f205_soc_types(void)
220 type_register_static(&stm32f205_soc_info
);
223 type_init(stm32f205_soc_types
)