target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 /* QEMU addressing/paging config */
  24 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
  25 #if defined(TARGET_RISCV64)
  26 #define TARGET_LONG_BITS 64
  27 #define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
  28 #define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
  29 #elif defined(TARGET_RISCV32)
  30 #define TARGET_LONG_BITS 32
  31 #define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
  32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
  33 #endif
  34
  35 #define TCG_GUEST_DEFAULT_MO 0
  36
  37 #define CPUArchState struct CPURISCVState
  38
  39 #include "qemu-common.h"
  40 #include "qom/cpu.h"
  41 #include "exec/cpu-defs.h"
  42 #include "fpu/softfloat.h"
  43
  44 #define TYPE_RISCV_CPU "riscv-cpu"
  45
  46 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  47 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  48 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  49
  50 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  51 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
  52 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
  53 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
  54 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
  55 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
  56 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
  57 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  58 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  59 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  60 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  61
  62 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  63 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  64
  65 #if defined(TARGET_RISCV32)
  66 #define RVXLEN RV32
  67 #elif defined(TARGET_RISCV64)
  68 #define RVXLEN RV64
  69 #endif
  70
  71 #define RV(x) ((target_ulong)1 << (x - 'A'))
  72
  73 #define RVI RV('I')
  74 #define RVE RV('E') /* E and I are mutually exclusive */
  75 #define RVM RV('M')
  76 #define RVA RV('A')
  77 #define RVF RV('F')
  78 #define RVD RV('D')
  79 #define RVC RV('C')
  80 #define RVS RV('S')
  81 #define RVU RV('U')
  82
  83 /* S extension denotes that Supervisor mode exists, however it is possible
  84    to have a core that support S mode but does not have an MMU and there
  85    is currently no bit in misa to indicate whether an MMU exists or not
  86    so a cpu features bitfield is required */
  87 enum {
  88     RISCV_FEATURE_MMU
  89 };
  90
  91 #define USER_VERSION_2_02_0 0x00020200
  92 #define PRIV_VERSION_1_09_1 0x00010901
  93 #define PRIV_VERSION_1_10_0 0x00011000
  94
  95 #define TRANSLATE_FAIL 1
  96 #define TRANSLATE_SUCCESS 0
  97 #define NB_MMU_MODES 4
  98 #define MMU_USER_IDX 3
  99
 100 #define MAX_RISCV_PMPS (16)
 101
 102 typedef struct CPURISCVState CPURISCVState;
 103
 104 #include "pmp.h"
 105
 106 struct CPURISCVState {
 107     target_ulong gpr[32];
 108     uint64_t fpr[32]; /* assume both F and D extensions */
 109     target_ulong pc;
 110     target_ulong load_res;
 111     target_ulong load_val;
 112
 113     target_ulong frm;
 114
 115     target_ulong badaddr;
 116
 117     target_ulong user_ver;
 118     target_ulong priv_ver;
 119     target_ulong misa;
 120
 121     uint32_t features;
 122
 123 #ifndef CONFIG_USER_ONLY
 124     target_ulong priv;
 125     target_ulong resetvec;
 126
 127     target_ulong mhartid;
 128     target_ulong mstatus;
 129     /*
 130      * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
 131      * by I/O threads and other vCPUs, so hold the iothread mutex before
 132      * operating on it.  CPU_INTERRUPT_HARD should be in effect iff this is
 133      * non-zero.  Use riscv_cpu_set_local_interrupt.
 134      */
 135     uint32_t mip;        /* allow atomic_read for >= 32-bit hosts */
 136     target_ulong mie;
 137     target_ulong mideleg;
 138
 139     target_ulong sptbr;  /* until: priv-1.9.1 */
 140     target_ulong satp;   /* since: priv-1.10.0 */
 141     target_ulong sbadaddr;
 142     target_ulong mbadaddr;
 143     target_ulong medeleg;
 144
 145     target_ulong stvec;
 146     target_ulong sepc;
 147     target_ulong scause;
 148
 149     target_ulong mtvec;
 150     target_ulong mepc;
 151     target_ulong mcause;
 152     target_ulong mtval;  /* since: priv-1.10.0 */
 153
 154     target_ulong scounteren;
 155     target_ulong mcounteren;
 156
 157     target_ulong sscratch;
 158     target_ulong mscratch;
 159
 160     /* temporary htif regs */
 161     uint64_t mfromhost;
 162     uint64_t mtohost;
 163     uint64_t timecmp;
 164
 165     /* physical memory protection */
 166     pmp_table_t pmp_state;
 167 #endif
 168
 169     float_status fp_status;
 170
 171     /* QEMU */
 172     CPU_COMMON
 173
 174     /* Fields from here on are preserved across CPU reset. */
 175     QEMUTimer *timer; /* Internal timer */
 176 };
 177
 178 #define RISCV_CPU_CLASS(klass) \
 179     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 180 #define RISCV_CPU(obj) \
 181     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 182 #define RISCV_CPU_GET_CLASS(obj) \
 183     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 184
 185 /**
 186  * RISCVCPUClass:
 187  * @parent_realize: The parent class' realize handler.
 188  * @parent_reset: The parent class' reset handler.
 189  *
 190  * A RISCV CPU model.
 191  */
 192 typedef struct RISCVCPUClass {
 193     /*< private >*/
 194     CPUClass parent_class;
 195     /*< public >*/
 196     DeviceRealize parent_realize;
 197     void (*parent_reset)(CPUState *cpu);
 198 } RISCVCPUClass;
 199
 200 /**
 201  * RISCVCPU:
 202  * @env: #CPURISCVState
 203  *
 204  * A RISCV CPU.
 205  */
 206 typedef struct RISCVCPU {
 207     /*< private >*/
 208     CPUState parent_obj;
 209     /*< public >*/
 210     CPURISCVState env;
 211 } RISCVCPU;
 212
 213 static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
 214 {
 215     return container_of(env, RISCVCPU, env);
 216 }
 217
 218 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 219 {
 220     return (env->misa & ext) != 0;
 221 }
 222
 223 static inline bool riscv_feature(CPURISCVState *env, int feature)
 224 {
 225     return env->features & (1ULL << feature);
 226 }
 227
 228 #include "cpu_user.h"
 229 #include "cpu_bits.h"
 230
 231 extern const char * const riscv_int_regnames[];
 232 extern const char * const riscv_fpr_regnames[];
 233 extern const char * const riscv_excp_names[];
 234 extern const char * const riscv_intr_names[];
 235
 236 #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e))
 237 #define ENV_OFFSET offsetof(RISCVCPU, env)
 238
 239 void riscv_cpu_do_interrupt(CPUState *cpu);
 240 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 241 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 242 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 243 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 244 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 245 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 246                                     MMUAccessType access_type, int mmu_idx,
 247                                     uintptr_t retaddr);
 248 int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
 249                               int rw, int mmu_idx);
 250
 251 char *riscv_isa_string(RISCVCPU *cpu);
 252 void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 253
 254 #define cpu_signal_handler cpu_riscv_signal_handler
 255 #define cpu_list riscv_cpu_list
 256 #define cpu_mmu_index riscv_cpu_mmu_index
 257
 258 void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
 259
 260 void riscv_translate_init(void);
 261 RISCVCPU *cpu_riscv_init(const char *cpu_model);
 262 int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
 263 void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
 264                                           uint32_t exception, uintptr_t pc);
 265
 266 target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
 267 void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
 268
 269 #define TB_FLAGS_MMU_MASK  3
 270 #define TB_FLAGS_FP_ENABLE MSTATUS_FS
 271
 272 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 273                                         target_ulong *cs_base, uint32_t *flags)
 274 {
 275     *pc = env->pc;
 276     *cs_base = 0;
 277 #ifdef CONFIG_USER_ONLY
 278     *flags = TB_FLAGS_FP_ENABLE;
 279 #else
 280     *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 281 #endif
 282 }
 283
 284 void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
 285         target_ulong csrno);
 286 target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
 287
 288 #ifndef CONFIG_USER_ONLY
 289 void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value);
 290 #endif
 291
 292 #include "exec/cpu-all.h"
 293
 294 #endif /* RISCV_CPU_H */