2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
28 #include "sysemu/block-backend.h"
29 #include "sysemu/blockdev.h"
30 #include "sysemu/dma.h"
31 #include "qemu/timer.h"
32 #include "qemu/bitops.h"
33 #include "hw/sd/sdhci.h"
34 #include "sdhci-internal.h"
37 /* host controller debug messages */
42 #define DPRINT_L1(fmt, args...) \
45 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
48 #define DPRINT_L2(fmt, args...) \
50 if (SDHC_DEBUG > 1) { \
51 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
54 #define ERRPRINT(fmt, args...) \
57 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
61 #define TYPE_SDHCI_BUS "sdhci-bus"
62 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
64 /* Default SD/MMC host controller features information, which will be
65 * presented in CAPABILITIES register of generic SD host controller at reset.
66 * If not stated otherwise:
67 * 0 - not supported, 1 - supported, other - prohibited.
69 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
70 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
71 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
72 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
73 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
74 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */
75 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
76 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
77 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
78 /* Maximum host controller R/W buffers size
79 * Possible values: 512, 1024, 2048 bytes */
80 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
81 /* Maximum clock frequency for SDclock in MHz
82 * value in range 10-63 MHz, 0 - not defined */
83 #define SDHC_CAPAB_BASECLKFREQ 52ul
84 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
85 /* Timeout clock frequency 1-63, 0 - not defined */
86 #define SDHC_CAPAB_TOCLKFREQ 52ul
88 /* Now check all parameters and calculate CAPABILITIES REGISTER value */
89 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
90 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
91 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
93 #error Capabilities features can have value 0 or 1 only!
96 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512
97 #define MAX_BLOCK_LENGTH 0ul
98 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
99 #define MAX_BLOCK_LENGTH 1ul
100 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
101 #define MAX_BLOCK_LENGTH 2ul
103 #error Max host controller block size can have value 512, 1024 or 2048 only!
106 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
107 SDHC_CAPAB_BASECLKFREQ > 63
108 #error SDclock frequency can have value in range 0, 10-63 only!
111 #if SDHC_CAPAB_TOCLKFREQ > 63
112 #error Timeout clock frequency can have value in range 0-63 only!
115 #define SDHC_CAPAB_REG_DEFAULT \
116 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
117 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
118 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
119 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
120 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
121 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
122 (SDHC_CAPAB_TOCLKFREQ))
124 #define MASK_TRNMOD 0x0037
125 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
127 static uint8_t sdhci_slotint(SDHCIState
*s
)
129 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
130 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
131 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
134 static inline void sdhci_update_irq(SDHCIState
*s
)
136 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
139 static void sdhci_raise_insertion_irq(void *opaque
)
141 SDHCIState
*s
= (SDHCIState
*)opaque
;
143 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
144 timer_mod(s
->insert_timer
,
145 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
147 s
->prnsts
= 0x1ff0000;
148 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
149 s
->norintsts
|= SDHC_NIS_INSERT
;
155 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
157 SDHCIState
*s
= (SDHCIState
*)dev
;
158 DPRINT_L1("Card state changed: %s!\n", level
? "insert" : "eject");
160 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
161 /* Give target some time to notice card ejection */
162 timer_mod(s
->insert_timer
,
163 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
166 s
->prnsts
= 0x1ff0000;
167 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
168 s
->norintsts
|= SDHC_NIS_INSERT
;
171 s
->prnsts
= 0x1fa0000;
172 s
->pwrcon
&= ~SDHC_POWER_ON
;
173 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
174 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
175 s
->norintsts
|= SDHC_NIS_REMOVE
;
182 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
184 SDHCIState
*s
= (SDHCIState
*)dev
;
187 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
190 s
->prnsts
|= SDHC_WRITE_PROTECT
;
194 static void sdhci_reset(SDHCIState
*s
)
196 DeviceState
*dev
= DEVICE(s
);
198 timer_del(s
->insert_timer
);
199 timer_del(s
->transfer_timer
);
200 /* Set all registers to 0. Capabilities registers are not cleared
201 * and assumed to always preserve their value, given to them during
203 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
205 /* Reset other state based on current card insertion/readonly status */
206 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
207 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
210 s
->stopped_state
= sdhc_not_stopped
;
211 s
->pending_insert_state
= false;
214 static void sdhci_poweron_reset(DeviceState
*dev
)
216 /* QOM (ie power-on) reset. This is identical to reset
217 * commanded via device register apart from handling of the
218 * 'pending insert on powerup' quirk.
220 SDHCIState
*s
= (SDHCIState
*)dev
;
224 if (s
->pending_insert_quirk
) {
225 s
->pending_insert_state
= true;
229 static void sdhci_data_transfer(void *opaque
);
231 static void sdhci_send_command(SDHCIState
*s
)
234 uint8_t response
[16];
239 request
.cmd
= s
->cmdreg
>> 8;
240 request
.arg
= s
->argument
;
241 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request
.cmd
, request
.arg
);
242 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
244 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
246 s
->rspreg
[0] = (response
[0] << 24) | (response
[1] << 16) |
247 (response
[2] << 8) | response
[3];
248 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
249 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s
->rspreg
[0]);
250 } else if (rlen
== 16) {
251 s
->rspreg
[0] = (response
[11] << 24) | (response
[12] << 16) |
252 (response
[13] << 8) | response
[14];
253 s
->rspreg
[1] = (response
[7] << 24) | (response
[8] << 16) |
254 (response
[9] << 8) | response
[10];
255 s
->rspreg
[2] = (response
[3] << 24) | (response
[4] << 16) |
256 (response
[5] << 8) | response
[6];
257 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
259 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
260 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
261 s
->rspreg
[3], s
->rspreg
[2], s
->rspreg
[1], s
->rspreg
[0]);
263 ERRPRINT("Timeout waiting for command response\n");
264 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
265 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
266 s
->norintsts
|= SDHC_NIS_ERR
;
270 if ((s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
271 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
272 s
->norintsts
|= SDHC_NIS_TRSCMP
;
276 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
277 s
->norintsts
|= SDHC_NIS_CMDCMP
;
282 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
284 sdhci_data_transfer(s
);
288 static void sdhci_end_transfer(SDHCIState
*s
)
290 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
291 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
293 uint8_t response
[16];
297 DPRINT_L1("Automatically issue CMD%d %08x\n", request
.cmd
, request
.arg
);
298 sdbus_do_command(&s
->sdbus
, &request
, response
);
299 /* Auto CMD12 response goes to the upper Response register */
300 s
->rspreg
[3] = (response
[0] << 24) | (response
[1] << 16) |
301 (response
[2] << 8) | response
[3];
304 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
305 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
306 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
308 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
309 s
->norintsts
|= SDHC_NIS_TRSCMP
;
316 * Programmed i/o data transfer
319 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
320 static void sdhci_read_block_from_card(SDHCIState
*s
)
324 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
325 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
329 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
330 s
->fifo_buffer
[index
] = sdbus_read_data(&s
->sdbus
);
333 /* New data now available for READ through Buffer Port Register */
334 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
335 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
336 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
339 /* Clear DAT line active status if that was the last block */
340 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
341 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
342 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
345 /* If stop at block gap request was set and it's not the last block of
346 * data - generate Block Event interrupt */
347 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
349 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
350 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
351 s
->norintsts
|= SDHC_EIS_BLKGAP
;
358 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
359 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
364 /* first check that a valid data exists in host controller input buffer */
365 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
366 ERRPRINT("Trying to read from empty buffer\n");
370 for (i
= 0; i
< size
; i
++) {
371 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
373 /* check if we've read all valid data (blksize bytes) from buffer */
374 if ((s
->data_count
) >= (s
->blksize
& 0x0fff)) {
375 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
377 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
378 s
->data_count
= 0; /* next buff read must start at position [0] */
380 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
384 /* if that was the last block of data */
385 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
386 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
387 /* stop at gap request */
388 (s
->stopped_state
== sdhc_gap_read
&&
389 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
390 sdhci_end_transfer(s
);
391 } else { /* if there are more data, read next block from card */
392 sdhci_read_block_from_card(s
);
401 /* Write data from host controller FIFO to card */
402 static void sdhci_write_block_to_card(SDHCIState
*s
)
406 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
407 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
408 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
414 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
415 if (s
->blkcnt
== 0) {
422 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
423 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[index
]);
426 /* Next data can be written through BUFFER DATORT register */
427 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
429 /* Finish transfer if that was the last block of data */
430 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
431 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
432 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
433 sdhci_end_transfer(s
);
434 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
435 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
438 /* Generate Block Gap Event if requested and if not the last block */
439 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
441 s
->prnsts
&= ~SDHC_DOING_WRITE
;
442 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
443 s
->norintsts
|= SDHC_EIS_BLKGAP
;
445 sdhci_end_transfer(s
);
451 /* Write @size bytes of @value data to host controller @s Buffer Data Port
453 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
457 /* Check that there is free space left in a buffer */
458 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
459 ERRPRINT("Can't write to data buffer: buffer full\n");
463 for (i
= 0; i
< size
; i
++) {
464 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
467 if (s
->data_count
>= (s
->blksize
& 0x0fff)) {
468 DPRINT_L2("write buffer filled with %u bytes of data\n",
471 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
472 if (s
->prnsts
& SDHC_DOING_WRITE
) {
473 sdhci_write_block_to_card(s
);
480 * Single DMA data transfer
483 /* Multi block SDMA transfer */
484 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
486 bool page_aligned
= false;
487 unsigned int n
, begin
;
488 const uint16_t block_size
= s
->blksize
& 0x0fff;
489 uint32_t boundary_chk
= 1 << (((s
->blksize
& 0xf000) >> 12) + 12);
490 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
492 if (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || !s
->blkcnt
) {
493 qemu_log_mask(LOG_UNIMP
, "infinite transfer is not supported\n");
497 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
498 * possible stop at page boundary if initial address is not page aligned,
499 * allow them to work properly */
500 if ((s
->sdmasysad
% boundary_chk
) == 0) {
504 if (s
->trnmod
& SDHC_TRNS_READ
) {
505 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
506 SDHC_DAT_LINE_ACTIVE
;
508 if (s
->data_count
== 0) {
509 for (n
= 0; n
< block_size
; n
++) {
510 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
513 begin
= s
->data_count
;
514 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
515 s
->data_count
= boundary_count
+ begin
;
518 s
->data_count
= block_size
;
519 boundary_count
-= block_size
- begin
;
520 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
524 dma_memory_write(&address_space_memory
, s
->sdmasysad
,
525 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
526 s
->sdmasysad
+= s
->data_count
- begin
;
527 if (s
->data_count
== block_size
) {
530 if (page_aligned
&& boundary_count
== 0) {
535 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
536 SDHC_DAT_LINE_ACTIVE
;
538 begin
= s
->data_count
;
539 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
540 s
->data_count
= boundary_count
+ begin
;
543 s
->data_count
= block_size
;
544 boundary_count
-= block_size
- begin
;
546 dma_memory_read(&address_space_memory
, s
->sdmasysad
,
547 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
548 s
->sdmasysad
+= s
->data_count
- begin
;
549 if (s
->data_count
== block_size
) {
550 for (n
= 0; n
< block_size
; n
++) {
551 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
554 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
558 if (page_aligned
&& boundary_count
== 0) {
564 if (s
->blkcnt
== 0) {
565 sdhci_end_transfer(s
);
567 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
568 s
->norintsts
|= SDHC_NIS_DMA
;
574 /* single block SDMA transfer */
575 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
578 uint32_t datacnt
= s
->blksize
& 0x0fff;
580 if (s
->trnmod
& SDHC_TRNS_READ
) {
581 for (n
= 0; n
< datacnt
; n
++) {
582 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
584 dma_memory_write(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
587 dma_memory_read(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
589 for (n
= 0; n
< datacnt
; n
++) {
590 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
595 sdhci_end_transfer(s
);
598 typedef struct ADMADescr
{
605 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
609 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
610 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
611 case SDHC_CTRL_ADMA2_32
:
612 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma2
,
614 adma2
= le64_to_cpu(adma2
);
615 /* The spec does not specify endianness of descriptor table.
616 * We currently assume that it is LE.
618 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
619 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
620 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
623 case SDHC_CTRL_ADMA1_32
:
624 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma1
,
626 adma1
= le32_to_cpu(adma1
);
627 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
628 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
630 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
631 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
636 case SDHC_CTRL_ADMA2_64
:
637 dma_memory_read(&address_space_memory
, entry_addr
,
638 (uint8_t *)(&dscr
->attr
), 1);
639 dma_memory_read(&address_space_memory
, entry_addr
+ 2,
640 (uint8_t *)(&dscr
->length
), 2);
641 dscr
->length
= le16_to_cpu(dscr
->length
);
642 dma_memory_read(&address_space_memory
, entry_addr
+ 4,
643 (uint8_t *)(&dscr
->addr
), 8);
644 dscr
->attr
= le64_to_cpu(dscr
->attr
);
645 dscr
->attr
&= 0xfffffff8;
651 /* Advanced DMA data transfer */
653 static void sdhci_do_adma(SDHCIState
*s
)
655 unsigned int n
, begin
, length
;
656 const uint16_t block_size
= s
->blksize
& 0x0fff;
660 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
661 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
663 get_adma_description(s
, &dscr
);
664 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx
", len=%d, attr=%x\n",
665 dscr
.addr
, dscr
.length
, dscr
.attr
);
667 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
668 /* Indicate that error occurred in ST_FDS state */
669 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
670 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
672 /* Generate ADMA error interrupt */
673 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
674 s
->errintsts
|= SDHC_EIS_ADMAERR
;
675 s
->norintsts
|= SDHC_NIS_ERR
;
682 length
= dscr
.length
? dscr
.length
: 65536;
684 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
685 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
687 if (s
->trnmod
& SDHC_TRNS_READ
) {
689 if (s
->data_count
== 0) {
690 for (n
= 0; n
< block_size
; n
++) {
691 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
694 begin
= s
->data_count
;
695 if ((length
+ begin
) < block_size
) {
696 s
->data_count
= length
+ begin
;
699 s
->data_count
= block_size
;
700 length
-= block_size
- begin
;
702 dma_memory_write(&address_space_memory
, dscr
.addr
,
703 &s
->fifo_buffer
[begin
],
704 s
->data_count
- begin
);
705 dscr
.addr
+= s
->data_count
- begin
;
706 if (s
->data_count
== block_size
) {
708 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
710 if (s
->blkcnt
== 0) {
718 begin
= s
->data_count
;
719 if ((length
+ begin
) < block_size
) {
720 s
->data_count
= length
+ begin
;
723 s
->data_count
= block_size
;
724 length
-= block_size
- begin
;
726 dma_memory_read(&address_space_memory
, dscr
.addr
,
727 &s
->fifo_buffer
[begin
],
728 s
->data_count
- begin
);
729 dscr
.addr
+= s
->data_count
- begin
;
730 if (s
->data_count
== block_size
) {
731 for (n
= 0; n
< block_size
; n
++) {
732 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
735 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
737 if (s
->blkcnt
== 0) {
744 s
->admasysaddr
+= dscr
.incr
;
746 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
747 s
->admasysaddr
= dscr
.addr
;
748 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64
"\n",
752 s
->admasysaddr
+= dscr
.incr
;
756 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
757 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64
"\n",
759 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
760 s
->norintsts
|= SDHC_NIS_DMA
;
766 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
767 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
768 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
769 DPRINT_L2("ADMA transfer completed\n");
770 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
771 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
773 ERRPRINT("SD/MMC host ADMA length mismatch\n");
774 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
775 SDHC_ADMAERR_STATE_ST_TFR
;
776 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
777 ERRPRINT("Set ADMA error flag\n");
778 s
->errintsts
|= SDHC_EIS_ADMAERR
;
779 s
->norintsts
|= SDHC_NIS_ERR
;
784 sdhci_end_transfer(s
);
790 /* we have unfinished business - reschedule to continue ADMA */
791 timer_mod(s
->transfer_timer
,
792 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
795 /* Perform data transfer according to controller configuration */
797 static void sdhci_data_transfer(void *opaque
)
799 SDHCIState
*s
= (SDHCIState
*)opaque
;
801 if (s
->trnmod
& SDHC_TRNS_DMA
) {
802 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
804 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
805 sdhci_sdma_transfer_single_block(s
);
807 sdhci_sdma_transfer_multi_blocks(s
);
811 case SDHC_CTRL_ADMA1_32
:
812 if (!(s
->capareg
& SDHC_CAN_DO_ADMA1
)) {
813 ERRPRINT("ADMA1 not supported\n");
819 case SDHC_CTRL_ADMA2_32
:
820 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
)) {
821 ERRPRINT("ADMA2 not supported\n");
827 case SDHC_CTRL_ADMA2_64
:
828 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
) ||
829 !(s
->capareg
& SDHC_64_BIT_BUS_SUPPORT
)) {
830 ERRPRINT("64 bit ADMA not supported\n");
837 ERRPRINT("Unsupported DMA type\n");
841 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
842 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
843 SDHC_DAT_LINE_ACTIVE
;
844 sdhci_read_block_from_card(s
);
846 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
847 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
848 sdhci_write_block_to_card(s
);
853 static bool sdhci_can_issue_command(SDHCIState
*s
)
855 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
856 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
857 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
858 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
859 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
866 /* The Buffer Data Port register must be accessed in sequential and
867 * continuous manner */
869 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
871 if ((s
->data_count
& 0x3) != byte_num
) {
872 ERRPRINT("Non-sequential access to Buffer Data Port register"
879 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
881 SDHCIState
*s
= (SDHCIState
*)opaque
;
884 switch (offset
& ~0x3) {
889 ret
= s
->blksize
| (s
->blkcnt
<< 16);
895 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
897 case SDHC_RSPREG0
... SDHC_RSPREG3
:
898 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
901 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
902 ret
= sdhci_read_dataport(s
, size
);
903 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
,
912 ret
= s
->hostctl
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
916 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
919 ret
= s
->norintsts
| (s
->errintsts
<< 16);
921 case SDHC_NORINTSTSEN
:
922 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
924 case SDHC_NORINTSIGEN
:
925 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
927 case SDHC_ACMD12ERRSTS
:
928 ret
= s
->acmd12errsts
;
939 case SDHC_ADMASYSADDR
:
940 ret
= (uint32_t)s
->admasysaddr
;
942 case SDHC_ADMASYSADDR
+ 4:
943 ret
= (uint32_t)(s
->admasysaddr
>> 32);
945 case SDHC_SLOT_INT_STATUS
:
946 ret
= (SD_HOST_SPECv2_VERS
<< 16) | sdhci_slotint(s
);
949 ERRPRINT("bad %ub read: addr[0x%04x]\n", size
, (int)offset
);
953 ret
>>= (offset
& 0x3) * 8;
954 ret
&= (1ULL << (size
* 8)) - 1;
955 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
, ret
, ret
);
959 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
961 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
964 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
966 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
967 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
968 if (s
->stopped_state
== sdhc_gap_read
) {
969 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
970 sdhci_read_block_from_card(s
);
972 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
973 sdhci_write_block_to_card(s
);
975 s
->stopped_state
= sdhc_not_stopped
;
976 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
977 if (s
->prnsts
& SDHC_DOING_READ
) {
978 s
->stopped_state
= sdhc_gap_read
;
979 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
980 s
->stopped_state
= sdhc_gap_write
;
985 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
992 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
993 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
995 case SDHC_RESET_DATA
:
997 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
998 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
999 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
1000 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
1001 s
->stopped_state
= sdhc_not_stopped
;
1002 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
1003 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
1009 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1011 SDHCIState
*s
= (SDHCIState
*)opaque
;
1012 unsigned shift
= 8 * (offset
& 0x3);
1013 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
1014 uint32_t value
= val
;
1017 switch (offset
& ~0x3) {
1019 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1020 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1021 /* Writing to last byte of sdmasysad might trigger transfer */
1022 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1023 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl
) == SDHC_CTRL_SDMA
) {
1024 if (s
->trnmod
& SDHC_TRNS_MULTI
) {
1025 sdhci_sdma_transfer_multi_blocks(s
);
1027 sdhci_sdma_transfer_single_block(s
);
1032 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1033 MASKED_WRITE(s
->blksize
, mask
, value
);
1034 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1037 /* Limit block size to the maximum buffer size */
1038 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1039 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than " \
1040 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1043 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1048 MASKED_WRITE(s
->argument
, mask
, value
);
1051 /* DMA can be enabled only if it is supported as indicated by
1052 * capabilities register */
1053 if (!(s
->capareg
& SDHC_CAN_DO_DMA
)) {
1054 value
&= ~SDHC_TRNS_DMA
;
1056 MASKED_WRITE(s
->trnmod
, mask
, value
& MASK_TRNMOD
);
1057 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1059 /* Writing to the upper byte of CMDREG triggers SD command generation */
1060 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1064 sdhci_send_command(s
);
1067 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1068 sdhci_write_dataport(s
, value
>> shift
, size
);
1072 if (!(mask
& 0xFF0000)) {
1073 sdhci_blkgap_write(s
, value
>> 16);
1075 MASKED_WRITE(s
->hostctl
, mask
, value
);
1076 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1077 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1078 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1079 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1080 s
->pwrcon
&= ~SDHC_POWER_ON
;
1084 if (!(mask
& 0xFF000000)) {
1085 sdhci_reset_write(s
, value
>> 24);
1087 MASKED_WRITE(s
->clkcon
, mask
, value
);
1088 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1089 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1090 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1092 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1095 case SDHC_NORINTSTS
:
1096 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1097 value
&= ~SDHC_NIS_CARDINT
;
1099 s
->norintsts
&= mask
| ~value
;
1100 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1102 s
->norintsts
|= SDHC_NIS_ERR
;
1104 s
->norintsts
&= ~SDHC_NIS_ERR
;
1106 sdhci_update_irq(s
);
1108 case SDHC_NORINTSTSEN
:
1109 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1110 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1111 s
->norintsts
&= s
->norintstsen
;
1112 s
->errintsts
&= s
->errintstsen
;
1114 s
->norintsts
|= SDHC_NIS_ERR
;
1116 s
->norintsts
&= ~SDHC_NIS_ERR
;
1118 /* Quirk for Raspberry Pi: pending card insert interrupt
1119 * appears when first enabled after power on */
1120 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert_state
) {
1121 assert(s
->pending_insert_quirk
);
1122 s
->norintsts
|= SDHC_NIS_INSERT
;
1123 s
->pending_insert_state
= false;
1125 sdhci_update_irq(s
);
1127 case SDHC_NORINTSIGEN
:
1128 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1129 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1130 sdhci_update_irq(s
);
1133 MASKED_WRITE(s
->admaerr
, mask
, value
);
1135 case SDHC_ADMASYSADDR
:
1136 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1137 (uint64_t)mask
)) | (uint64_t)value
;
1139 case SDHC_ADMASYSADDR
+ 4:
1140 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1141 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1144 s
->acmd12errsts
|= value
;
1145 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1146 if (s
->acmd12errsts
) {
1147 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1150 s
->norintsts
|= SDHC_NIS_ERR
;
1152 sdhci_update_irq(s
);
1155 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
1156 size
, (int)offset
, value
>> shift
, value
>> shift
);
1159 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
1160 size
, (int)offset
, value
>> shift
, value
>> shift
);
1163 static const MemoryRegionOps sdhci_mmio_ops
= {
1165 .write
= sdhci_write
,
1167 .min_access_size
= 1,
1168 .max_access_size
= 4,
1171 .endianness
= DEVICE_LITTLE_ENDIAN
,
1174 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
1176 switch (SDHC_CAPAB_BLOCKSIZE(s
->capareg
)) {
1184 hw_error("SDHC: unsupported value for maximum block size\n");
1189 /* --- qdev common --- */
1191 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
1192 /* Capabilities registers provide information on supported features
1193 * of this specific host controller implementation */ \
1194 DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
1195 DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
1197 static void sdhci_initfn(SDHCIState
*s
)
1199 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1200 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1202 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1203 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1206 static void sdhci_uninitfn(SDHCIState
*s
)
1208 timer_del(s
->insert_timer
);
1209 timer_free(s
->insert_timer
);
1210 timer_del(s
->transfer_timer
);
1211 timer_free(s
->transfer_timer
);
1213 g_free(s
->fifo_buffer
);
1214 s
->fifo_buffer
= NULL
;
1217 static bool sdhci_pending_insert_vmstate_needed(void *opaque
)
1219 SDHCIState
*s
= opaque
;
1221 return s
->pending_insert_state
;
1224 static const VMStateDescription sdhci_pending_insert_vmstate
= {
1225 .name
= "sdhci/pending-insert",
1227 .minimum_version_id
= 1,
1228 .needed
= sdhci_pending_insert_vmstate_needed
,
1229 .fields
= (VMStateField
[]) {
1230 VMSTATE_BOOL(pending_insert_state
, SDHCIState
),
1231 VMSTATE_END_OF_LIST()
1235 const VMStateDescription sdhci_vmstate
= {
1238 .minimum_version_id
= 1,
1239 .fields
= (VMStateField
[]) {
1240 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1241 VMSTATE_UINT16(blksize
, SDHCIState
),
1242 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1243 VMSTATE_UINT32(argument
, SDHCIState
),
1244 VMSTATE_UINT16(trnmod
, SDHCIState
),
1245 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1246 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1247 VMSTATE_UINT32(prnsts
, SDHCIState
),
1248 VMSTATE_UINT8(hostctl
, SDHCIState
),
1249 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1250 VMSTATE_UINT8(blkgap
, SDHCIState
),
1251 VMSTATE_UINT8(wakcon
, SDHCIState
),
1252 VMSTATE_UINT16(clkcon
, SDHCIState
),
1253 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1254 VMSTATE_UINT8(admaerr
, SDHCIState
),
1255 VMSTATE_UINT16(norintsts
, SDHCIState
),
1256 VMSTATE_UINT16(errintsts
, SDHCIState
),
1257 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1258 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1259 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1260 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1261 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1262 VMSTATE_UINT16(data_count
, SDHCIState
),
1263 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1264 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1265 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, buf_maxsz
),
1266 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1267 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1268 VMSTATE_END_OF_LIST()
1270 .subsections
= (const VMStateDescription
*[]) {
1271 &sdhci_pending_insert_vmstate
,
1276 static void sdhci_common_class_init(ObjectClass
*klass
, void *data
)
1278 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1280 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1281 dc
->vmsd
= &sdhci_vmstate
;
1282 dc
->reset
= sdhci_poweron_reset
;
1285 /* --- qdev PCI --- */
1287 static Property sdhci_pci_properties
[] = {
1288 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1289 DEFINE_PROP_END_OF_LIST(),
1292 static void sdhci_pci_realize(PCIDevice
*dev
, Error
**errp
)
1294 SDHCIState
*s
= PCI_SDHCI(dev
);
1295 dev
->config
[PCI_CLASS_PROG
] = 0x01; /* Standard Host supported DMA */
1296 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1298 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1299 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1300 s
->irq
= pci_allocate_irq(dev
);
1301 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1302 SDHC_REGISTERS_MAP_SIZE
);
1303 pci_register_bar(dev
, 0, 0, &s
->iomem
);
1306 static void sdhci_pci_exit(PCIDevice
*dev
)
1308 SDHCIState
*s
= PCI_SDHCI(dev
);
1312 static void sdhci_pci_class_init(ObjectClass
*klass
, void *data
)
1314 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1315 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1317 k
->realize
= sdhci_pci_realize
;
1318 k
->exit
= sdhci_pci_exit
;
1319 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
1320 k
->device_id
= PCI_DEVICE_ID_REDHAT_SDHCI
;
1321 k
->class_id
= PCI_CLASS_SYSTEM_SDHCI
;
1322 dc
->props
= sdhci_pci_properties
;
1324 sdhci_common_class_init(klass
, data
);
1327 static const TypeInfo sdhci_pci_info
= {
1328 .name
= TYPE_PCI_SDHCI
,
1329 .parent
= TYPE_PCI_DEVICE
,
1330 .instance_size
= sizeof(SDHCIState
),
1331 .class_init
= sdhci_pci_class_init
,
1332 .interfaces
= (InterfaceInfo
[]) {
1333 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1338 /* --- qdev SysBus --- */
1340 static Property sdhci_sysbus_properties
[] = {
1341 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1342 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert_quirk
,
1344 DEFINE_PROP_END_OF_LIST(),
1347 static void sdhci_sysbus_init(Object
*obj
)
1349 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1354 static void sdhci_sysbus_finalize(Object
*obj
)
1356 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1360 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
** errp
)
1362 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1363 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1365 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1366 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1367 sysbus_init_irq(sbd
, &s
->irq
);
1368 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1369 SDHC_REGISTERS_MAP_SIZE
);
1370 sysbus_init_mmio(sbd
, &s
->iomem
);
1373 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1375 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1377 dc
->props
= sdhci_sysbus_properties
;
1378 dc
->realize
= sdhci_sysbus_realize
;
1380 sdhci_common_class_init(klass
, data
);
1383 static const TypeInfo sdhci_sysbus_info
= {
1384 .name
= TYPE_SYSBUS_SDHCI
,
1385 .parent
= TYPE_SYS_BUS_DEVICE
,
1386 .instance_size
= sizeof(SDHCIState
),
1387 .instance_init
= sdhci_sysbus_init
,
1388 .instance_finalize
= sdhci_sysbus_finalize
,
1389 .class_init
= sdhci_sysbus_class_init
,
1392 /* --- qdev bus master --- */
1394 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1396 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1398 sbc
->set_inserted
= sdhci_set_inserted
;
1399 sbc
->set_readonly
= sdhci_set_readonly
;
1402 static const TypeInfo sdhci_bus_info
= {
1403 .name
= TYPE_SDHCI_BUS
,
1404 .parent
= TYPE_SD_BUS
,
1405 .instance_size
= sizeof(SDBus
),
1406 .class_init
= sdhci_bus_class_init
,
1409 static void sdhci_register_types(void)
1411 type_register_static(&sdhci_pci_info
);
1412 type_register_static(&sdhci_sysbus_info
);
1413 type_register_static(&sdhci_bus_info
);
1416 type_init(sdhci_register_types
)