2 * OMAP on-chip MMC/SD host emulation.
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "hw/arm/omap.h"
50 uint16_t blen_counter
;
52 uint16_t nblk_counter
;
67 static void omap_mmc_interrupts_update(struct omap_mmc_s
*s
)
69 qemu_set_irq(s
->irq
, !!(s
->status
& s
->mask
));
72 static void omap_mmc_fifolevel_update(struct omap_mmc_s
*host
)
74 if (!host
->transfer
&& !host
->fifo_len
) {
75 host
->status
&= 0xf3ff;
79 if (host
->fifo_len
> host
->af_level
&& host
->ddir
) {
81 host
->status
&= 0xfbff;
82 qemu_irq_raise(host
->dma
[1]);
84 host
->status
|= 0x0400;
86 host
->status
&= 0xfbff;
87 qemu_irq_lower(host
->dma
[1]);
90 if (host
->fifo_len
< host
->ae_level
&& !host
->ddir
) {
92 host
->status
&= 0xf7ff;
93 qemu_irq_raise(host
->dma
[0]);
95 host
->status
|= 0x0800;
97 qemu_irq_lower(host
->dma
[0]);
98 host
->status
&= 0xf7ff;
103 sd_nore
= 0, /* no response */
104 sd_r1
, /* normal response command */
105 sd_r2
, /* CID, CSD registers */
106 sd_r3
, /* OCR register */
107 sd_r6
= 6, /* Published RCA response */
111 static void omap_mmc_command(struct omap_mmc_s
*host
, int cmd
, int dir
,
112 sd_cmd_type_t type
, int busy
, sd_rsp_type_t resptype
, int init
)
114 uint32_t rspstatus
, mask
;
117 uint8_t response
[16];
119 if (init
&& cmd
== 0) {
120 host
->status
|= 0x0001;
124 if (resptype
== sd_r1
&& busy
)
127 if (type
== sd_adtc
) {
128 host
->fifo_start
= 0;
139 request
.arg
= host
->arg
;
140 request
.crc
= 0; /* FIXME */
142 rsplen
= sd_do_command(host
->card
, &request
, response
);
144 /* TODO: validate CRCs */
158 mask
= OUT_OF_RANGE
| ADDRESS_ERROR
| BLOCK_LEN_ERROR
|
159 ERASE_SEQ_ERROR
| ERASE_PARAM
| WP_VIOLATION
|
160 LOCK_UNLOCK_FAILED
| COM_CRC_ERROR
| ILLEGAL_COMMAND
|
161 CARD_ECC_FAILED
| CC_ERROR
| SD_ERROR
|
163 if (host
->sdio
& (1 << 13))
164 mask
|= AKE_SEQ_ERROR
;
165 rspstatus
= (response
[0] << 24) | (response
[1] << 16) |
166 (response
[2] << 8) | (response
[3] << 0);
184 rspstatus
= (response
[0] << 24) | (response
[1] << 16) |
185 (response
[2] << 8) | (response
[3] << 0);
186 if (rspstatus
& 0x80000000)
187 host
->status
&= 0xe000;
189 host
->status
|= 0x1000;
199 mask
= 0xe000 | AKE_SEQ_ERROR
;
200 rspstatus
= (response
[2] << 8) | (response
[3] << 0);
203 if (rspstatus
& mask
)
204 host
->status
|= 0x4000;
206 host
->status
&= 0xb000;
209 for (rsplen
= 0; rsplen
< 8; rsplen
++)
210 host
->rsp
[~rsplen
& 7] = response
[(rsplen
<< 1) | 1] |
211 (response
[(rsplen
<< 1) | 0] << 8);
214 host
->status
|= 0x0080;
216 host
->status
|= 0x0005; /* Makes it more real */
218 host
->status
|= 0x0001;
221 static void omap_mmc_transfer(struct omap_mmc_s
*host
)
230 if (host
->fifo_len
> host
->af_level
)
233 value
= sd_read_data(host
->card
);
234 host
->fifo
[(host
->fifo_start
+ host
->fifo_len
) & 31] = value
;
235 if (-- host
->blen_counter
) {
236 value
= sd_read_data(host
->card
);
237 host
->fifo
[(host
->fifo_start
+ host
->fifo_len
) & 31] |=
239 host
->blen_counter
--;
247 value
= host
->fifo
[host
->fifo_start
] & 0xff;
248 sd_write_data(host
->card
, value
);
249 if (-- host
->blen_counter
) {
250 value
= host
->fifo
[host
->fifo_start
] >> 8;
251 sd_write_data(host
->card
, value
);
252 host
->blen_counter
--;
257 host
->fifo_start
&= 31;
260 if (host
->blen_counter
== 0) {
261 host
->nblk_counter
--;
262 host
->blen_counter
= host
->blen
;
264 if (host
->nblk_counter
== 0) {
265 host
->nblk_counter
= host
->nblk
;
267 host
->status
|= 0x0008;
274 static void omap_mmc_update(void *opaque
)
276 struct omap_mmc_s
*s
= opaque
;
277 omap_mmc_transfer(s
);
278 omap_mmc_fifolevel_update(s
);
279 omap_mmc_interrupts_update(s
);
282 void omap_mmc_reset(struct omap_mmc_s
*host
)
285 memset(host
->rsp
, 0, sizeof(host
->rsp
));
296 host
->blen_counter
= 0;
298 host
->nblk_counter
= 0;
301 host
->ae_level
= 0x00;
302 host
->af_level
= 0x1f;
304 host
->cdet_wakeup
= 0;
305 host
->cdet_enable
= 0;
306 qemu_set_irq(host
->coverswitch
, host
->cdet_state
);
309 /* Since we're still using the legacy SD API the card is not plugged
310 * into any bus, and we must reset it manually. When omap_mmc is
311 * QOMified this must move into the QOM reset function.
313 device_reset(DEVICE(host
->card
));
316 static uint64_t omap_mmc_read(void *opaque
, hwaddr offset
,
320 struct omap_mmc_s
*s
= (struct omap_mmc_s
*) opaque
;
323 return omap_badwidth_read16(opaque
, offset
);
327 case 0x00: /* MMC_CMD */
330 case 0x04: /* MMC_ARGL */
331 return s
->arg
& 0x0000ffff;
333 case 0x08: /* MMC_ARGH */
336 case 0x0c: /* MMC_CON */
337 return (s
->dw
<< 15) | (s
->mode
<< 12) | (s
->enable
<< 11) |
338 (s
->be
<< 10) | s
->clkdiv
;
340 case 0x10: /* MMC_STAT */
343 case 0x14: /* MMC_IE */
346 case 0x18: /* MMC_CTO */
349 case 0x1c: /* MMC_DTO */
352 case 0x20: /* MMC_DATA */
353 /* TODO: support 8-bit access */
354 i
= s
->fifo
[s
->fifo_start
];
355 if (s
->fifo_len
== 0) {
356 printf("MMC: FIFO underrun\n");
362 omap_mmc_transfer(s
);
363 omap_mmc_fifolevel_update(s
);
364 omap_mmc_interrupts_update(s
);
367 case 0x24: /* MMC_BLEN */
368 return s
->blen_counter
;
370 case 0x28: /* MMC_NBLK */
371 return s
->nblk_counter
;
373 case 0x2c: /* MMC_BUF */
374 return (s
->rx_dma
<< 15) | (s
->af_level
<< 8) |
375 (s
->tx_dma
<< 7) | s
->ae_level
;
377 case 0x30: /* MMC_SPI */
379 case 0x34: /* MMC_SDIO */
380 return (s
->cdet_wakeup
<< 2) | (s
->cdet_enable
) | s
->sdio
;
381 case 0x38: /* MMC_SYST */
384 case 0x3c: /* MMC_REV */
387 case 0x40: /* MMC_RSP0 */
388 case 0x44: /* MMC_RSP1 */
389 case 0x48: /* MMC_RSP2 */
390 case 0x4c: /* MMC_RSP3 */
391 case 0x50: /* MMC_RSP4 */
392 case 0x54: /* MMC_RSP5 */
393 case 0x58: /* MMC_RSP6 */
394 case 0x5c: /* MMC_RSP7 */
395 return s
->rsp
[(offset
- 0x40) >> 2];
398 case 0x60: /* MMC_IOSR */
399 case 0x64: /* MMC_SYSC */
401 case 0x68: /* MMC_SYSS */
405 OMAP_BAD_REG(offset
);
409 static void omap_mmc_write(void *opaque
, hwaddr offset
,
410 uint64_t value
, unsigned size
)
413 struct omap_mmc_s
*s
= (struct omap_mmc_s
*) opaque
;
416 omap_badwidth_write16(opaque
, offset
, value
);
421 case 0x00: /* MMC_CMD */
426 for (i
= 0; i
< 8; i
++)
428 omap_mmc_command(s
, value
& 63, (value
>> 15) & 1,
429 (sd_cmd_type_t
) ((value
>> 12) & 3),
431 (sd_rsp_type_t
) ((value
>> 8) & 7),
436 case 0x04: /* MMC_ARGL */
437 s
->arg
&= 0xffff0000;
438 s
->arg
|= 0x0000ffff & value
;
441 case 0x08: /* MMC_ARGH */
442 s
->arg
&= 0x0000ffff;
443 s
->arg
|= value
<< 16;
446 case 0x0c: /* MMC_CON */
447 s
->dw
= (value
>> 15) & 1;
448 s
->mode
= (value
>> 12) & 3;
449 s
->enable
= (value
>> 11) & 1;
450 s
->be
= (value
>> 10) & 1;
451 s
->clkdiv
= (value
>> 0) & (s
->rev
>= 2 ? 0x3ff : 0xff);
453 printf("SD mode %i unimplemented!\n", s
->mode
);
455 printf("SD FIFO byte sex unimplemented!\n");
456 if (s
->dw
!= 0 && s
->lines
< 4)
457 printf("4-bit SD bus enabled\n");
462 case 0x10: /* MMC_STAT */
464 omap_mmc_interrupts_update(s
);
467 case 0x14: /* MMC_IE */
468 s
->mask
= value
& 0x7fff;
469 omap_mmc_interrupts_update(s
);
472 case 0x18: /* MMC_CTO */
473 s
->cto
= value
& 0xff;
474 if (s
->cto
> 0xfd && s
->rev
<= 1)
475 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
478 case 0x1c: /* MMC_DTO */
479 s
->dto
= value
& 0xffff;
482 case 0x20: /* MMC_DATA */
483 /* TODO: support 8-bit access */
484 if (s
->fifo_len
== 32)
486 s
->fifo
[(s
->fifo_start
+ s
->fifo_len
) & 31] = value
;
488 omap_mmc_transfer(s
);
489 omap_mmc_fifolevel_update(s
);
490 omap_mmc_interrupts_update(s
);
493 case 0x24: /* MMC_BLEN */
494 s
->blen
= (value
& 0x07ff) + 1;
495 s
->blen_counter
= s
->blen
;
498 case 0x28: /* MMC_NBLK */
499 s
->nblk
= (value
& 0x07ff) + 1;
500 s
->nblk_counter
= s
->nblk
;
501 s
->blen_counter
= s
->blen
;
504 case 0x2c: /* MMC_BUF */
505 s
->rx_dma
= (value
>> 15) & 1;
506 s
->af_level
= (value
>> 8) & 0x1f;
507 s
->tx_dma
= (value
>> 7) & 1;
508 s
->ae_level
= value
& 0x1f;
514 omap_mmc_fifolevel_update(s
);
515 omap_mmc_interrupts_update(s
);
518 /* SPI, SDIO and TEST modes unimplemented */
519 case 0x30: /* MMC_SPI (OMAP1 only) */
521 case 0x34: /* MMC_SDIO */
522 s
->sdio
= value
& (s
->rev
>= 2 ? 0xfbf3 : 0x2020);
523 s
->cdet_wakeup
= (value
>> 9) & 1;
524 s
->cdet_enable
= (value
>> 2) & 1;
526 case 0x38: /* MMC_SYST */
529 case 0x3c: /* MMC_REV */
530 case 0x40: /* MMC_RSP0 */
531 case 0x44: /* MMC_RSP1 */
532 case 0x48: /* MMC_RSP2 */
533 case 0x4c: /* MMC_RSP3 */
534 case 0x50: /* MMC_RSP4 */
535 case 0x54: /* MMC_RSP5 */
536 case 0x58: /* MMC_RSP6 */
537 case 0x5c: /* MMC_RSP7 */
542 case 0x60: /* MMC_IOSR */
544 printf("MMC: SDIO bits used!\n");
546 case 0x64: /* MMC_SYSC */
547 if (value
& (1 << 2)) /* SRTS */
550 case 0x68: /* MMC_SYSS */
555 OMAP_BAD_REG(offset
);
559 static const MemoryRegionOps omap_mmc_ops
= {
560 .read
= omap_mmc_read
,
561 .write
= omap_mmc_write
,
562 .endianness
= DEVICE_NATIVE_ENDIAN
,
565 static void omap_mmc_cover_cb(void *opaque
, int line
, int level
)
567 struct omap_mmc_s
*host
= (struct omap_mmc_s
*) opaque
;
569 if (!host
->cdet_state
&& level
) {
570 host
->status
|= 0x0002;
571 omap_mmc_interrupts_update(host
);
572 if (host
->cdet_wakeup
) {
573 /* TODO: Assert wake-up */
577 if (host
->cdet_state
!= level
) {
578 qemu_set_irq(host
->coverswitch
, level
);
579 host
->cdet_state
= level
;
583 struct omap_mmc_s
*omap_mmc_init(hwaddr base
,
584 MemoryRegion
*sysmem
,
586 qemu_irq irq
, qemu_irq dma
[], omap_clk clk
)
588 struct omap_mmc_s
*s
= g_new0(struct omap_mmc_s
, 1);
593 s
->lines
= 1; /* TODO: needs to be settable per-board */
596 memory_region_init_io(&s
->iomem
, NULL
, &omap_mmc_ops
, s
, "omap.mmc", 0x800);
597 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
599 /* Instantiate the storage */
600 s
->card
= sd_init(blk
, false);
601 if (s
->card
== NULL
) {
610 struct omap_mmc_s
*omap2_mmc_init(struct omap_target_agent_s
*ta
,
611 BlockBackend
*blk
, qemu_irq irq
, qemu_irq dma
[],
612 omap_clk fclk
, omap_clk iclk
)
614 struct omap_mmc_s
*s
= g_new0(struct omap_mmc_s
, 1);
622 memory_region_init_io(&s
->iomem
, NULL
, &omap_mmc_ops
, s
, "omap.mmc",
623 omap_l4_region_size(ta
, 0));
624 omap_l4_attach(ta
, 0, &s
->iomem
);
626 /* Instantiate the storage */
627 s
->card
= sd_init(blk
, false);
628 if (s
->card
== NULL
) {
632 s
->cdet
= qemu_allocate_irq(omap_mmc_cover_cb
, s
, 0);
633 sd_set_cb(s
->card
, NULL
, s
->cdet
);
640 void omap_mmc_handlers(struct omap_mmc_s
*s
, qemu_irq ro
, qemu_irq cover
)
643 sd_set_cb(s
->card
, ro
, s
->cdet
);
644 s
->coverswitch
= cover
;
645 qemu_set_irq(cover
, s
->cdet_state
);
647 sd_set_cb(s
->card
, ro
, cover
);
650 void omap_mmc_enable(struct omap_mmc_s
*s
, int enable
)
652 sd_enable(s
->card
, enable
);