hw/arm/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "qemu-common.h"
  32 #include "cpu.h"
  33 #include "hw/boards.h"
  34 #include "hw/irq.h"
  35 #include "hw/qdev-properties.h"
  36 #include "hw/sysbus.h"
  37 #include "migration/vmstate.h"
  38 #include "strongarm.h"
  39 #include "qemu/error-report.h"
  40 #include "hw/arm/boot.h"
  41 #include "chardev/char-fe.h"
  42 #include "chardev/char-serial.h"
  43 #include "sysemu/sysemu.h"
  44 #include "hw/ssi/ssi.h"
  45 #include "qemu/cutils.h"
  46 #include "qemu/log.h"
  47
  48 //#define DEBUG
  49
  50 /*
  51  TODO
  52  - Implement cp15, c14 ?
  53  - Implement cp15, c15 !!! (idle used in L)
  54  - Implement idle mode handling/DIM
  55  - Implement sleep mode/Wake sources
  56  - Implement reset control
  57  - Implement memory control regs
  58  - PCMCIA handling
  59  - Maybe support MBGNT/MBREQ
  60  - DMA channels
  61  - GPCLK
  62  - IrDA
  63  - MCP
  64  - Enhance UART with modem signals
  65  */
  66
  67 #ifdef DEBUG
  68 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  69 #else
  70 # define DPRINTF(format, ...) do { } while (0)
  71 #endif
  72
  73 static struct {
  74     hwaddr io_base;
  75     int irq;
  76 } sa_serial[] = {
  77     { 0x80010000, SA_PIC_UART1 },
  78     { 0x80030000, SA_PIC_UART2 },
  79     { 0x80050000, SA_PIC_UART3 },
  80     { 0, 0 }
  81 };
  82
  83 /* Interrupt Controller */
  84
  85 #define TYPE_STRONGARM_PIC "strongarm_pic"
  86 #define STRONGARM_PIC(obj) \
  87     OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
  88
  89 typedef struct StrongARMPICState {
  90     SysBusDevice parent_obj;
  91
  92     MemoryRegion iomem;
  93     qemu_irq    irq;
  94     qemu_irq    fiq;
  95
  96     uint32_t pending;
  97     uint32_t enabled;
  98     uint32_t is_fiq;
  99     uint32_t int_idle;
 100 } StrongARMPICState;
 101
 102 #define ICIP    0x00
 103 #define ICMR    0x04
 104 #define ICLR    0x08
 105 #define ICFP    0x10
 106 #define ICPR    0x20
 107 #define ICCR    0x0c
 108
 109 #define SA_PIC_SRCS     32
 110
 111
 112 static void strongarm_pic_update(void *opaque)
 113 {
 114     StrongARMPICState *s = opaque;
 115
 116     /* FIXME: reflect DIM */
 117     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 118     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 119 }
 120
 121 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 122 {
 123     StrongARMPICState *s = opaque;
 124
 125     if (level) {
 126         s->pending |= 1 << irq;
 127     } else {
 128         s->pending &= ~(1 << irq);
 129     }
 130
 131     strongarm_pic_update(s);
 132 }
 133
 134 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
 135                                        unsigned size)
 136 {
 137     StrongARMPICState *s = opaque;
 138
 139     switch (offset) {
 140     case ICIP:
 141         return s->pending & ~s->is_fiq & s->enabled;
 142     case ICMR:
 143         return s->enabled;
 144     case ICLR:
 145         return s->is_fiq;
 146     case ICCR:
 147         return s->int_idle == 0;
 148     case ICFP:
 149         return s->pending & s->is_fiq & s->enabled;
 150     case ICPR:
 151         return s->pending;
 152     default:
 153         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 154                         __func__, offset);
 155         return 0;
 156     }
 157 }
 158
 159 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
 160                                     uint64_t value, unsigned size)
 161 {
 162     StrongARMPICState *s = opaque;
 163
 164     switch (offset) {
 165     case ICMR:
 166         s->enabled = value;
 167         break;
 168     case ICLR:
 169         s->is_fiq = value;
 170         break;
 171     case ICCR:
 172         s->int_idle = (value & 1) ? 0 : ~0;
 173         break;
 174     default:
 175         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 176                         __func__, offset);
 177         break;
 178     }
 179     strongarm_pic_update(s);
 180 }
 181
 182 static const MemoryRegionOps strongarm_pic_ops = {
 183     .read = strongarm_pic_mem_read,
 184     .write = strongarm_pic_mem_write,
 185     .endianness = DEVICE_NATIVE_ENDIAN,
 186 };
 187
 188 static void strongarm_pic_initfn(Object *obj)
 189 {
 190     DeviceState *dev = DEVICE(obj);
 191     StrongARMPICState *s = STRONGARM_PIC(obj);
 192     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 193
 194     qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
 195     memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
 196                           "pic", 0x1000);
 197     sysbus_init_mmio(sbd, &s->iomem);
 198     sysbus_init_irq(sbd, &s->irq);
 199     sysbus_init_irq(sbd, &s->fiq);
 200 }
 201
 202 static int strongarm_pic_post_load(void *opaque, int version_id)
 203 {
 204     strongarm_pic_update(opaque);
 205     return 0;
 206 }
 207
 208 static VMStateDescription vmstate_strongarm_pic_regs = {
 209     .name = "strongarm_pic",
 210     .version_id = 0,
 211     .minimum_version_id = 0,
 212     .post_load = strongarm_pic_post_load,
 213     .fields = (VMStateField[]) {
 214         VMSTATE_UINT32(pending, StrongARMPICState),
 215         VMSTATE_UINT32(enabled, StrongARMPICState),
 216         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 217         VMSTATE_UINT32(int_idle, StrongARMPICState),
 218         VMSTATE_END_OF_LIST(),
 219     },
 220 };
 221
 222 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 223 {
 224     DeviceClass *dc = DEVICE_CLASS(klass);
 225
 226     dc->desc = "StrongARM PIC";
 227     dc->vmsd = &vmstate_strongarm_pic_regs;
 228 }
 229
 230 static const TypeInfo strongarm_pic_info = {
 231     .name          = TYPE_STRONGARM_PIC,
 232     .parent        = TYPE_SYS_BUS_DEVICE,
 233     .instance_size = sizeof(StrongARMPICState),
 234     .instance_init = strongarm_pic_initfn,
 235     .class_init    = strongarm_pic_class_init,
 236 };
 237
 238 /* Real-Time Clock */
 239 #define RTAR 0x00 /* RTC Alarm register */
 240 #define RCNR 0x04 /* RTC Counter register */
 241 #define RTTR 0x08 /* RTC Timer Trim register */
 242 #define RTSR 0x10 /* RTC Status register */
 243
 244 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 245 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 246 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 247 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 248
 249 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 250  * trim delete isn't emulated, so
 251  * f = 32 768 / (RTTR_trim + 1) */
 252
 253 #define TYPE_STRONGARM_RTC "strongarm-rtc"
 254 #define STRONGARM_RTC(obj) \
 255     OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
 256
 257 typedef struct StrongARMRTCState {
 258     SysBusDevice parent_obj;
 259
 260     MemoryRegion iomem;
 261     uint32_t rttr;
 262     uint32_t rtsr;
 263     uint32_t rtar;
 264     uint32_t last_rcnr;
 265     int64_t last_hz;
 266     QEMUTimer *rtc_alarm;
 267     QEMUTimer *rtc_hz;
 268     qemu_irq rtc_irq;
 269     qemu_irq rtc_hz_irq;
 270 } StrongARMRTCState;
 271
 272 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 273 {
 274     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 275     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 276 }
 277
 278 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 279 {
 280     int64_t rt = qemu_clock_get_ms(rtc_clock);
 281     s->last_rcnr += ((rt - s->last_hz) << 15) /
 282             (1000 * ((s->rttr & 0xffff) + 1));
 283     s->last_hz = rt;
 284 }
 285
 286 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 287 {
 288     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 289         timer_mod(s->rtc_hz, s->last_hz + 1000);
 290     } else {
 291         timer_del(s->rtc_hz);
 292     }
 293
 294     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 295         timer_mod(s->rtc_alarm, s->last_hz +
 296                 (((s->rtar - s->last_rcnr) * 1000 *
 297                   ((s->rttr & 0xffff) + 1)) >> 15));
 298     } else {
 299         timer_del(s->rtc_alarm);
 300     }
 301 }
 302
 303 static inline void strongarm_rtc_alarm_tick(void *opaque)
 304 {
 305     StrongARMRTCState *s = opaque;
 306     s->rtsr |= RTSR_AL;
 307     strongarm_rtc_timer_update(s);
 308     strongarm_rtc_int_update(s);
 309 }
 310
 311 static inline void strongarm_rtc_hz_tick(void *opaque)
 312 {
 313     StrongARMRTCState *s = opaque;
 314     s->rtsr |= RTSR_HZ;
 315     strongarm_rtc_timer_update(s);
 316     strongarm_rtc_int_update(s);
 317 }
 318
 319 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
 320                                    unsigned size)
 321 {
 322     StrongARMRTCState *s = opaque;
 323
 324     switch (addr) {
 325     case RTTR:
 326         return s->rttr;
 327     case RTSR:
 328         return s->rtsr;
 329     case RTAR:
 330         return s->rtar;
 331     case RCNR:
 332         return s->last_rcnr +
 333                 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 334                 (1000 * ((s->rttr & 0xffff) + 1));
 335     default:
 336         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 337         return 0;
 338     }
 339 }
 340
 341 static void strongarm_rtc_write(void *opaque, hwaddr addr,
 342                                 uint64_t value, unsigned size)
 343 {
 344     StrongARMRTCState *s = opaque;
 345     uint32_t old_rtsr;
 346
 347     switch (addr) {
 348     case RTTR:
 349         strongarm_rtc_hzupdate(s);
 350         s->rttr = value;
 351         strongarm_rtc_timer_update(s);
 352         break;
 353
 354     case RTSR:
 355         old_rtsr = s->rtsr;
 356         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 357                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 358
 359         if (s->rtsr != old_rtsr) {
 360             strongarm_rtc_timer_update(s);
 361         }
 362
 363         strongarm_rtc_int_update(s);
 364         break;
 365
 366     case RTAR:
 367         s->rtar = value;
 368         strongarm_rtc_timer_update(s);
 369         break;
 370
 371     case RCNR:
 372         strongarm_rtc_hzupdate(s);
 373         s->last_rcnr = value;
 374         strongarm_rtc_timer_update(s);
 375         break;
 376
 377     default:
 378         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 379     }
 380 }
 381
 382 static const MemoryRegionOps strongarm_rtc_ops = {
 383     .read = strongarm_rtc_read,
 384     .write = strongarm_rtc_write,
 385     .endianness = DEVICE_NATIVE_ENDIAN,
 386 };
 387
 388 static void strongarm_rtc_init(Object *obj)
 389 {
 390     StrongARMRTCState *s = STRONGARM_RTC(obj);
 391     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 392     struct tm tm;
 393
 394     s->rttr = 0x0;
 395     s->rtsr = 0;
 396
 397     qemu_get_timedate(&tm, 0);
 398
 399     s->last_rcnr = (uint32_t) mktimegm(&tm);
 400     s->last_hz = qemu_clock_get_ms(rtc_clock);
 401
 402     sysbus_init_irq(dev, &s->rtc_irq);
 403     sysbus_init_irq(dev, &s->rtc_hz_irq);
 404
 405     memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
 406                           "rtc", 0x10000);
 407     sysbus_init_mmio(dev, &s->iomem);
 408 }
 409
 410 static void strongarm_rtc_realize(DeviceState *dev, Error **errp)
 411 {
 412     StrongARMRTCState *s = STRONGARM_RTC(dev);
 413     s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
 414     s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
 415 }
 416
 417 static int strongarm_rtc_pre_save(void *opaque)
 418 {
 419     StrongARMRTCState *s = opaque;
 420
 421     strongarm_rtc_hzupdate(s);
 422
 423     return 0;
 424 }
 425
 426 static int strongarm_rtc_post_load(void *opaque, int version_id)
 427 {
 428     StrongARMRTCState *s = opaque;
 429
 430     strongarm_rtc_timer_update(s);
 431     strongarm_rtc_int_update(s);
 432
 433     return 0;
 434 }
 435
 436 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 437     .name = "strongarm-rtc",
 438     .version_id = 0,
 439     .minimum_version_id = 0,
 440     .pre_save = strongarm_rtc_pre_save,
 441     .post_load = strongarm_rtc_post_load,
 442     .fields = (VMStateField[]) {
 443         VMSTATE_UINT32(rttr, StrongARMRTCState),
 444         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 445         VMSTATE_UINT32(rtar, StrongARMRTCState),
 446         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 447         VMSTATE_INT64(last_hz, StrongARMRTCState),
 448         VMSTATE_END_OF_LIST(),
 449     },
 450 };
 451
 452 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 453 {
 454     DeviceClass *dc = DEVICE_CLASS(klass);
 455
 456     dc->desc = "StrongARM RTC Controller";
 457     dc->vmsd = &vmstate_strongarm_rtc_regs;
 458     dc->realize = strongarm_rtc_realize;
 459 }
 460
 461 static const TypeInfo strongarm_rtc_sysbus_info = {
 462     .name          = TYPE_STRONGARM_RTC,
 463     .parent        = TYPE_SYS_BUS_DEVICE,
 464     .instance_size = sizeof(StrongARMRTCState),
 465     .instance_init = strongarm_rtc_init,
 466     .class_init    = strongarm_rtc_sysbus_class_init,
 467 };
 468
 469 /* GPIO */
 470 #define GPLR 0x00
 471 #define GPDR 0x04
 472 #define GPSR 0x08
 473 #define GPCR 0x0c
 474 #define GRER 0x10
 475 #define GFER 0x14
 476 #define GEDR 0x18
 477 #define GAFR 0x1c
 478
 479 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
 480 #define STRONGARM_GPIO(obj) \
 481     OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
 482
 483 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 484 struct StrongARMGPIOInfo {
 485     SysBusDevice busdev;
 486     MemoryRegion iomem;
 487     qemu_irq handler[28];
 488     qemu_irq irqs[11];
 489     qemu_irq irqX;
 490
 491     uint32_t ilevel;
 492     uint32_t olevel;
 493     uint32_t dir;
 494     uint32_t rising;
 495     uint32_t falling;
 496     uint32_t status;
 497     uint32_t gafr;
 498
 499     uint32_t prev_level;
 500 };
 501
 502
 503 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 504 {
 505     int i;
 506     for (i = 0; i < 11; i++) {
 507         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 508     }
 509
 510     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 511 }
 512
 513 static void strongarm_gpio_set(void *opaque, int line, int level)
 514 {
 515     StrongARMGPIOInfo *s = opaque;
 516     uint32_t mask;
 517
 518     mask = 1 << line;
 519
 520     if (level) {
 521         s->status |= s->rising & mask &
 522                 ~s->ilevel & ~s->dir;
 523         s->ilevel |= mask;
 524     } else {
 525         s->status |= s->falling & mask &
 526                 s->ilevel & ~s->dir;
 527         s->ilevel &= ~mask;
 528     }
 529
 530     if (s->status & mask) {
 531         strongarm_gpio_irq_update(s);
 532     }
 533 }
 534
 535 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 536 {
 537     uint32_t level, diff;
 538     int bit;
 539
 540     level = s->olevel & s->dir;
 541
 542     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 543         bit = ctz32(diff);
 544         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 545     }
 546
 547     s->prev_level = level;
 548 }
 549
 550 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
 551                                     unsigned size)
 552 {
 553     StrongARMGPIOInfo *s = opaque;
 554
 555     switch (offset) {
 556     case GPDR:        /* GPIO Pin-Direction registers */
 557         return s->dir;
 558
 559     case GPSR:        /* GPIO Pin-Output Set registers */
 560         qemu_log_mask(LOG_GUEST_ERROR,
 561                       "strongarm GPIO: read from write only register GPSR\n");
 562         return 0;
 563
 564     case GPCR:        /* GPIO Pin-Output Clear registers */
 565         qemu_log_mask(LOG_GUEST_ERROR,
 566                       "strongarm GPIO: read from write only register GPCR\n");
 567         return 0;
 568
 569     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 570         return s->rising;
 571
 572     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 573         return s->falling;
 574
 575     case GAFR:        /* GPIO Alternate Function registers */
 576         return s->gafr;
 577
 578     case GPLR:        /* GPIO Pin-Level registers */
 579         return (s->olevel & s->dir) |
 580                (s->ilevel & ~s->dir);
 581
 582     case GEDR:        /* GPIO Edge Detect Status registers */
 583         return s->status;
 584
 585     default:
 586         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 587     }
 588
 589     return 0;
 590 }
 591
 592 static void strongarm_gpio_write(void *opaque, hwaddr offset,
 593                                  uint64_t value, unsigned size)
 594 {
 595     StrongARMGPIOInfo *s = opaque;
 596
 597     switch (offset) {
 598     case GPDR:        /* GPIO Pin-Direction registers */
 599         s->dir = value & 0x0fffffff;
 600         strongarm_gpio_handler_update(s);
 601         break;
 602
 603     case GPSR:        /* GPIO Pin-Output Set registers */
 604         s->olevel |= value & 0x0fffffff;
 605         strongarm_gpio_handler_update(s);
 606         break;
 607
 608     case GPCR:        /* GPIO Pin-Output Clear registers */
 609         s->olevel &= ~value;
 610         strongarm_gpio_handler_update(s);
 611         break;
 612
 613     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 614         s->rising = value;
 615         break;
 616
 617     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 618         s->falling = value;
 619         break;
 620
 621     case GAFR:        /* GPIO Alternate Function registers */
 622         s->gafr = value;
 623         break;
 624
 625     case GEDR:        /* GPIO Edge Detect Status registers */
 626         s->status &= ~value;
 627         strongarm_gpio_irq_update(s);
 628         break;
 629
 630     default:
 631         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 632     }
 633 }
 634
 635 static const MemoryRegionOps strongarm_gpio_ops = {
 636     .read = strongarm_gpio_read,
 637     .write = strongarm_gpio_write,
 638     .endianness = DEVICE_NATIVE_ENDIAN,
 639 };
 640
 641 static DeviceState *strongarm_gpio_init(hwaddr base,
 642                 DeviceState *pic)
 643 {
 644     DeviceState *dev;
 645     int i;
 646
 647     dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
 648     qdev_init_nofail(dev);
 649
 650     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 651     for (i = 0; i < 12; i++)
 652         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 653                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 654
 655     return dev;
 656 }
 657
 658 static void strongarm_gpio_initfn(Object *obj)
 659 {
 660     DeviceState *dev = DEVICE(obj);
 661     StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
 662     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 663     int i;
 664
 665     qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
 666     qdev_init_gpio_out(dev, s->handler, 28);
 667
 668     memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
 669                           "gpio", 0x1000);
 670
 671     sysbus_init_mmio(sbd, &s->iomem);
 672     for (i = 0; i < 11; i++) {
 673         sysbus_init_irq(sbd, &s->irqs[i]);
 674     }
 675     sysbus_init_irq(sbd, &s->irqX);
 676 }
 677
 678 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 679     .name = "strongarm-gpio",
 680     .version_id = 0,
 681     .minimum_version_id = 0,
 682     .fields = (VMStateField[]) {
 683         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 684         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 685         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 686         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 687         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 688         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 689         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 690         VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
 691         VMSTATE_END_OF_LIST(),
 692     },
 693 };
 694
 695 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 696 {
 697     DeviceClass *dc = DEVICE_CLASS(klass);
 698
 699     dc->desc = "StrongARM GPIO controller";
 700     dc->vmsd = &vmstate_strongarm_gpio_regs;
 701 }
 702
 703 static const TypeInfo strongarm_gpio_info = {
 704     .name          = TYPE_STRONGARM_GPIO,
 705     .parent        = TYPE_SYS_BUS_DEVICE,
 706     .instance_size = sizeof(StrongARMGPIOInfo),
 707     .instance_init = strongarm_gpio_initfn,
 708     .class_init    = strongarm_gpio_class_init,
 709 };
 710
 711 /* Peripheral Pin Controller */
 712 #define PPDR 0x00
 713 #define PPSR 0x04
 714 #define PPAR 0x08
 715 #define PSDR 0x0c
 716 #define PPFR 0x10
 717
 718 #define TYPE_STRONGARM_PPC "strongarm-ppc"
 719 #define STRONGARM_PPC(obj) \
 720     OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
 721
 722 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 723 struct StrongARMPPCInfo {
 724     SysBusDevice parent_obj;
 725
 726     MemoryRegion iomem;
 727     qemu_irq handler[28];
 728
 729     uint32_t ilevel;
 730     uint32_t olevel;
 731     uint32_t dir;
 732     uint32_t ppar;
 733     uint32_t psdr;
 734     uint32_t ppfr;
 735
 736     uint32_t prev_level;
 737 };
 738
 739 static void strongarm_ppc_set(void *opaque, int line, int level)
 740 {
 741     StrongARMPPCInfo *s = opaque;
 742
 743     if (level) {
 744         s->ilevel |= 1 << line;
 745     } else {
 746         s->ilevel &= ~(1 << line);
 747     }
 748 }
 749
 750 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 751 {
 752     uint32_t level, diff;
 753     int bit;
 754
 755     level = s->olevel & s->dir;
 756
 757     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 758         bit = ctz32(diff);
 759         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 760     }
 761
 762     s->prev_level = level;
 763 }
 764
 765 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
 766                                    unsigned size)
 767 {
 768     StrongARMPPCInfo *s = opaque;
 769
 770     switch (offset) {
 771     case PPDR:        /* PPC Pin Direction registers */
 772         return s->dir | ~0x3fffff;
 773
 774     case PPSR:        /* PPC Pin State registers */
 775         return (s->olevel & s->dir) |
 776                (s->ilevel & ~s->dir) |
 777                ~0x3fffff;
 778
 779     case PPAR:
 780         return s->ppar | ~0x41000;
 781
 782     case PSDR:
 783         return s->psdr;
 784
 785     case PPFR:
 786         return s->ppfr | ~0x7f001;
 787
 788     default:
 789         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 790     }
 791
 792     return 0;
 793 }
 794
 795 static void strongarm_ppc_write(void *opaque, hwaddr offset,
 796                                 uint64_t value, unsigned size)
 797 {
 798     StrongARMPPCInfo *s = opaque;
 799
 800     switch (offset) {
 801     case PPDR:        /* PPC Pin Direction registers */
 802         s->dir = value & 0x3fffff;
 803         strongarm_ppc_handler_update(s);
 804         break;
 805
 806     case PPSR:        /* PPC Pin State registers */
 807         s->olevel = value & s->dir & 0x3fffff;
 808         strongarm_ppc_handler_update(s);
 809         break;
 810
 811     case PPAR:
 812         s->ppar = value & 0x41000;
 813         break;
 814
 815     case PSDR:
 816         s->psdr = value & 0x3fffff;
 817         break;
 818
 819     case PPFR:
 820         s->ppfr = value & 0x7f001;
 821         break;
 822
 823     default:
 824         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 825     }
 826 }
 827
 828 static const MemoryRegionOps strongarm_ppc_ops = {
 829     .read = strongarm_ppc_read,
 830     .write = strongarm_ppc_write,
 831     .endianness = DEVICE_NATIVE_ENDIAN,
 832 };
 833
 834 static void strongarm_ppc_init(Object *obj)
 835 {
 836     DeviceState *dev = DEVICE(obj);
 837     StrongARMPPCInfo *s = STRONGARM_PPC(obj);
 838     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 839
 840     qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
 841     qdev_init_gpio_out(dev, s->handler, 22);
 842
 843     memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
 844                           "ppc", 0x1000);
 845
 846     sysbus_init_mmio(sbd, &s->iomem);
 847 }
 848
 849 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 850     .name = "strongarm-ppc",
 851     .version_id = 0,
 852     .minimum_version_id = 0,
 853     .fields = (VMStateField[]) {
 854         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 855         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 856         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 857         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 858         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 859         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 860         VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
 861         VMSTATE_END_OF_LIST(),
 862     },
 863 };
 864
 865 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 866 {
 867     DeviceClass *dc = DEVICE_CLASS(klass);
 868
 869     dc->desc = "StrongARM PPC controller";
 870     dc->vmsd = &vmstate_strongarm_ppc_regs;
 871 }
 872
 873 static const TypeInfo strongarm_ppc_info = {
 874     .name          = TYPE_STRONGARM_PPC,
 875     .parent        = TYPE_SYS_BUS_DEVICE,
 876     .instance_size = sizeof(StrongARMPPCInfo),
 877     .instance_init = strongarm_ppc_init,
 878     .class_init    = strongarm_ppc_class_init,
 879 };
 880
 881 /* UART Ports */
 882 #define UTCR0 0x00
 883 #define UTCR1 0x04
 884 #define UTCR2 0x08
 885 #define UTCR3 0x0c
 886 #define UTDR  0x14
 887 #define UTSR0 0x1c
 888 #define UTSR1 0x20
 889
 890 #define UTCR0_PE  (1 << 0) /* Parity enable */
 891 #define UTCR0_OES (1 << 1) /* Even parity */
 892 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 893 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 894
 895 #define UTCR3_RXE (1 << 0) /* Rx enable */
 896 #define UTCR3_TXE (1 << 1) /* Tx enable */
 897 #define UTCR3_BRK (1 << 2) /* Force Break */
 898 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 899 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 900 #define UTCR3_LBM (1 << 5) /* Loopback */
 901
 902 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 903 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 904 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 905 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 906 #define UTSR0_REB (1 << 4) /* Receiver end break */
 907 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 908
 909 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 910 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 911 #define UTSR1_PRE (1 << 3) /* Parity error */
 912 #define UTSR1_FRE (1 << 4) /* Frame error */
 913 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 914
 915 #define RX_FIFO_PRE (1 << 8)
 916 #define RX_FIFO_FRE (1 << 9)
 917 #define RX_FIFO_ROR (1 << 10)
 918
 919 #define TYPE_STRONGARM_UART "strongarm-uart"
 920 #define STRONGARM_UART(obj) \
 921     OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
 922
 923 typedef struct StrongARMUARTState {
 924     SysBusDevice parent_obj;
 925
 926     MemoryRegion iomem;
 927     CharBackend chr;
 928     qemu_irq irq;
 929
 930     uint8_t utcr0;
 931     uint16_t brd;
 932     uint8_t utcr3;
 933     uint8_t utsr0;
 934     uint8_t utsr1;
 935
 936     uint8_t tx_fifo[8];
 937     uint8_t tx_start;
 938     uint8_t tx_len;
 939     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 940     uint8_t rx_start;
 941     uint8_t rx_len;
 942
 943     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 944     bool wait_break_end;
 945     QEMUTimer *rx_timeout_timer;
 946     QEMUTimer *tx_timer;
 947 } StrongARMUARTState;
 948
 949 static void strongarm_uart_update_status(StrongARMUARTState *s)
 950 {
 951     uint16_t utsr1 = 0;
 952
 953     if (s->tx_len != 8) {
 954         utsr1 |= UTSR1_TNF;
 955     }
 956
 957     if (s->rx_len != 0) {
 958         uint16_t ent = s->rx_fifo[s->rx_start];
 959
 960         utsr1 |= UTSR1_RNE;
 961         if (ent & RX_FIFO_PRE) {
 962             s->utsr1 |= UTSR1_PRE;
 963         }
 964         if (ent & RX_FIFO_FRE) {
 965             s->utsr1 |= UTSR1_FRE;
 966         }
 967         if (ent & RX_FIFO_ROR) {
 968             s->utsr1 |= UTSR1_ROR;
 969         }
 970     }
 971
 972     s->utsr1 = utsr1;
 973 }
 974
 975 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 976 {
 977     uint16_t utsr0 = s->utsr0 &
 978             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 979     int i;
 980
 981     if ((s->utcr3 & UTCR3_TXE) &&
 982                 (s->utcr3 & UTCR3_TIE) &&
 983                 s->tx_len <= 4) {
 984         utsr0 |= UTSR0_TFS;
 985     }
 986
 987     if ((s->utcr3 & UTCR3_RXE) &&
 988                 (s->utcr3 & UTCR3_RIE) &&
 989                 s->rx_len > 4) {
 990         utsr0 |= UTSR0_RFS;
 991     }
 992
 993     for (i = 0; i < s->rx_len && i < 4; i++)
 994         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 995             utsr0 |= UTSR0_EIF;
 996             break;
 997         }
 998
 999     s->utsr0 = utsr0;
1000     qemu_set_irq(s->irq, utsr0);
1001 }
1002
1003 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
1004 {
1005     int speed, parity, data_bits, stop_bits, frame_size;
1006     QEMUSerialSetParams ssp;
1007
1008     /* Start bit. */
1009     frame_size = 1;
1010     if (s->utcr0 & UTCR0_PE) {
1011         /* Parity bit. */
1012         frame_size++;
1013         if (s->utcr0 & UTCR0_OES) {
1014             parity = 'E';
1015         } else {
1016             parity = 'O';
1017         }
1018     } else {
1019             parity = 'N';
1020     }
1021     if (s->utcr0 & UTCR0_SBS) {
1022         stop_bits = 2;
1023     } else {
1024         stop_bits = 1;
1025     }
1026
1027     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1028     frame_size += data_bits + stop_bits;
1029     speed = 3686400 / 16 / (s->brd + 1);
1030     ssp.speed = speed;
1031     ssp.parity = parity;
1032     ssp.data_bits = data_bits;
1033     ssp.stop_bits = stop_bits;
1034     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
1035     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1036
1037     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1038             speed, parity, data_bits, stop_bits);
1039 }
1040
1041 static void strongarm_uart_rx_to(void *opaque)
1042 {
1043     StrongARMUARTState *s = opaque;
1044
1045     if (s->rx_len) {
1046         s->utsr0 |= UTSR0_RID;
1047         strongarm_uart_update_int_status(s);
1048     }
1049 }
1050
1051 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1052 {
1053     if ((s->utcr3 & UTCR3_RXE) == 0) {
1054         /* rx disabled */
1055         return;
1056     }
1057
1058     if (s->wait_break_end) {
1059         s->utsr0 |= UTSR0_REB;
1060         s->wait_break_end = false;
1061     }
1062
1063     if (s->rx_len < 12) {
1064         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1065         s->rx_len++;
1066     } else
1067         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1068 }
1069
1070 static int strongarm_uart_can_receive(void *opaque)
1071 {
1072     StrongARMUARTState *s = opaque;
1073
1074     if (s->rx_len == 12) {
1075         return 0;
1076     }
1077     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1078     if (s->rx_len < 8) {
1079         return 8 - s->rx_len;
1080     }
1081     return 1;
1082 }
1083
1084 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1085 {
1086     StrongARMUARTState *s = opaque;
1087     int i;
1088
1089     for (i = 0; i < size; i++) {
1090         strongarm_uart_rx_push(s, buf[i]);
1091     }
1092
1093     /* call the timeout receive callback in 3 char transmit time */
1094     timer_mod(s->rx_timeout_timer,
1095                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1096
1097     strongarm_uart_update_status(s);
1098     strongarm_uart_update_int_status(s);
1099 }
1100
1101 static void strongarm_uart_event(void *opaque, QEMUChrEvent event)
1102 {
1103     StrongARMUARTState *s = opaque;
1104     if (event == CHR_EVENT_BREAK) {
1105         s->utsr0 |= UTSR0_RBB;
1106         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1107         s->wait_break_end = true;
1108         strongarm_uart_update_status(s);
1109         strongarm_uart_update_int_status(s);
1110     }
1111 }
1112
1113 static void strongarm_uart_tx(void *opaque)
1114 {
1115     StrongARMUARTState *s = opaque;
1116     uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1117
1118     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1119         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1120     } else if (qemu_chr_fe_backend_connected(&s->chr)) {
1121         /* XXX this blocks entire thread. Rewrite to use
1122          * qemu_chr_fe_write and background I/O callbacks */
1123         qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1);
1124     }
1125
1126     s->tx_start = (s->tx_start + 1) % 8;
1127     s->tx_len--;
1128     if (s->tx_len) {
1129         timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1130     }
1131     strongarm_uart_update_status(s);
1132     strongarm_uart_update_int_status(s);
1133 }
1134
1135 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1136                                     unsigned size)
1137 {
1138     StrongARMUARTState *s = opaque;
1139     uint16_t ret;
1140
1141     switch (addr) {
1142     case UTCR0:
1143         return s->utcr0;
1144
1145     case UTCR1:
1146         return s->brd >> 8;
1147
1148     case UTCR2:
1149         return s->brd & 0xff;
1150
1151     case UTCR3:
1152         return s->utcr3;
1153
1154     case UTDR:
1155         if (s->rx_len != 0) {
1156             ret = s->rx_fifo[s->rx_start];
1157             s->rx_start = (s->rx_start + 1) % 12;
1158             s->rx_len--;
1159             strongarm_uart_update_status(s);
1160             strongarm_uart_update_int_status(s);
1161             return ret;
1162         }
1163         return 0;
1164
1165     case UTSR0:
1166         return s->utsr0;
1167
1168     case UTSR1:
1169         return s->utsr1;
1170
1171     default:
1172         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1173         return 0;
1174     }
1175 }
1176
1177 static void strongarm_uart_write(void *opaque, hwaddr addr,
1178                                  uint64_t value, unsigned size)
1179 {
1180     StrongARMUARTState *s = opaque;
1181
1182     switch (addr) {
1183     case UTCR0:
1184         s->utcr0 = value & 0x7f;
1185         strongarm_uart_update_parameters(s);
1186         break;
1187
1188     case UTCR1:
1189         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1190         strongarm_uart_update_parameters(s);
1191         break;
1192
1193     case UTCR2:
1194         s->brd = (s->brd & 0xf00) | (value & 0xff);
1195         strongarm_uart_update_parameters(s);
1196         break;
1197
1198     case UTCR3:
1199         s->utcr3 = value & 0x3f;
1200         if ((s->utcr3 & UTCR3_RXE) == 0) {
1201             s->rx_len = 0;
1202         }
1203         if ((s->utcr3 & UTCR3_TXE) == 0) {
1204             s->tx_len = 0;
1205         }
1206         strongarm_uart_update_status(s);
1207         strongarm_uart_update_int_status(s);
1208         break;
1209
1210     case UTDR:
1211         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1212             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1213             s->tx_len++;
1214             strongarm_uart_update_status(s);
1215             strongarm_uart_update_int_status(s);
1216             if (s->tx_len == 1) {
1217                 strongarm_uart_tx(s);
1218             }
1219         }
1220         break;
1221
1222     case UTSR0:
1223         s->utsr0 = s->utsr0 & ~(value &
1224                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1225         strongarm_uart_update_int_status(s);
1226         break;
1227
1228     default:
1229         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1230     }
1231 }
1232
1233 static const MemoryRegionOps strongarm_uart_ops = {
1234     .read = strongarm_uart_read,
1235     .write = strongarm_uart_write,
1236     .endianness = DEVICE_NATIVE_ENDIAN,
1237 };
1238
1239 static void strongarm_uart_init(Object *obj)
1240 {
1241     StrongARMUARTState *s = STRONGARM_UART(obj);
1242     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1243
1244     memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
1245                           "uart", 0x10000);
1246     sysbus_init_mmio(dev, &s->iomem);
1247     sysbus_init_irq(dev, &s->irq);
1248 }
1249
1250 static void strongarm_uart_realize(DeviceState *dev, Error **errp)
1251 {
1252     StrongARMUARTState *s = STRONGARM_UART(dev);
1253
1254     s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1255                                        strongarm_uart_rx_to,
1256                                        s);
1257     s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1258     qemu_chr_fe_set_handlers(&s->chr,
1259                              strongarm_uart_can_receive,
1260                              strongarm_uart_receive,
1261                              strongarm_uart_event,
1262                              NULL, s, NULL, true);
1263 }
1264
1265 static void strongarm_uart_reset(DeviceState *dev)
1266 {
1267     StrongARMUARTState *s = STRONGARM_UART(dev);
1268
1269     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1270     s->brd = 23;    /* 9600 */
1271     /* enable send & recv - this actually violates spec */
1272     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1273
1274     s->rx_len = s->tx_len = 0;
1275
1276     strongarm_uart_update_parameters(s);
1277     strongarm_uart_update_status(s);
1278     strongarm_uart_update_int_status(s);
1279 }
1280
1281 static int strongarm_uart_post_load(void *opaque, int version_id)
1282 {
1283     StrongARMUARTState *s = opaque;
1284
1285     strongarm_uart_update_parameters(s);
1286     strongarm_uart_update_status(s);
1287     strongarm_uart_update_int_status(s);
1288
1289     /* tx and restart timer */
1290     if (s->tx_len) {
1291         strongarm_uart_tx(s);
1292     }
1293
1294     /* restart rx timeout timer */
1295     if (s->rx_len) {
1296         timer_mod(s->rx_timeout_timer,
1297                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1298     }
1299
1300     return 0;
1301 }
1302
1303 static const VMStateDescription vmstate_strongarm_uart_regs = {
1304     .name = "strongarm-uart",
1305     .version_id = 0,
1306     .minimum_version_id = 0,
1307     .post_load = strongarm_uart_post_load,
1308     .fields = (VMStateField[]) {
1309         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1310         VMSTATE_UINT16(brd, StrongARMUARTState),
1311         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1312         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1313         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1314         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1315         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1316         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1317         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1318         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1319         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1320         VMSTATE_END_OF_LIST(),
1321     },
1322 };
1323
1324 static Property strongarm_uart_properties[] = {
1325     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1326     DEFINE_PROP_END_OF_LIST(),
1327 };
1328
1329 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1330 {
1331     DeviceClass *dc = DEVICE_CLASS(klass);
1332
1333     dc->desc = "StrongARM UART controller";
1334     dc->reset = strongarm_uart_reset;
1335     dc->vmsd = &vmstate_strongarm_uart_regs;
1336     device_class_set_props(dc, strongarm_uart_properties);
1337     dc->realize = strongarm_uart_realize;
1338 }
1339
1340 static const TypeInfo strongarm_uart_info = {
1341     .name          = TYPE_STRONGARM_UART,
1342     .parent        = TYPE_SYS_BUS_DEVICE,
1343     .instance_size = sizeof(StrongARMUARTState),
1344     .instance_init = strongarm_uart_init,
1345     .class_init    = strongarm_uart_class_init,
1346 };
1347
1348 /* Synchronous Serial Ports */
1349
1350 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1351 #define STRONGARM_SSP(obj) \
1352     OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1353
1354 typedef struct StrongARMSSPState {
1355     SysBusDevice parent_obj;
1356
1357     MemoryRegion iomem;
1358     qemu_irq irq;
1359     SSIBus *bus;
1360
1361     uint16_t sscr[2];
1362     uint16_t sssr;
1363
1364     uint16_t rx_fifo[8];
1365     uint8_t rx_level;
1366     uint8_t rx_start;
1367 } StrongARMSSPState;
1368
1369 #define SSCR0 0x60 /* SSP Control register 0 */
1370 #define SSCR1 0x64 /* SSP Control register 1 */
1371 #define SSDR  0x6c /* SSP Data register */
1372 #define SSSR  0x74 /* SSP Status register */
1373
1374 /* Bitfields for above registers */
1375 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1376 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1377 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1378 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1379 #define SSCR0_SSE       (1 << 7)
1380 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1381 #define SSCR1_RIE       (1 << 0)
1382 #define SSCR1_TIE       (1 << 1)
1383 #define SSCR1_LBM       (1 << 2)
1384 #define SSSR_TNF        (1 << 2)
1385 #define SSSR_RNE        (1 << 3)
1386 #define SSSR_TFS        (1 << 5)
1387 #define SSSR_RFS        (1 << 6)
1388 #define SSSR_ROR        (1 << 7)
1389 #define SSSR_RW         0x0080
1390
1391 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1392 {
1393     int level = 0;
1394
1395     level |= (s->sssr & SSSR_ROR);
1396     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1397     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1398     qemu_set_irq(s->irq, level);
1399 }
1400
1401 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1402 {
1403     s->sssr &= ~SSSR_TFS;
1404     s->sssr &= ~SSSR_TNF;
1405     if (s->sscr[0] & SSCR0_SSE) {
1406         if (s->rx_level >= 4) {
1407             s->sssr |= SSSR_RFS;
1408         } else {
1409             s->sssr &= ~SSSR_RFS;
1410         }
1411         if (s->rx_level) {
1412             s->sssr |= SSSR_RNE;
1413         } else {
1414             s->sssr &= ~SSSR_RNE;
1415         }
1416         /* TX FIFO is never filled, so it is always in underrun
1417            condition if SSP is enabled */
1418         s->sssr |= SSSR_TFS;
1419         s->sssr |= SSSR_TNF;
1420     }
1421
1422     strongarm_ssp_int_update(s);
1423 }
1424
1425 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1426                                    unsigned size)
1427 {
1428     StrongARMSSPState *s = opaque;
1429     uint32_t retval;
1430
1431     switch (addr) {
1432     case SSCR0:
1433         return s->sscr[0];
1434     case SSCR1:
1435         return s->sscr[1];
1436     case SSSR:
1437         return s->sssr;
1438     case SSDR:
1439         if (~s->sscr[0] & SSCR0_SSE) {
1440             return 0xffffffff;
1441         }
1442         if (s->rx_level < 1) {
1443             printf("%s: SSP Rx Underrun\n", __func__);
1444             return 0xffffffff;
1445         }
1446         s->rx_level--;
1447         retval = s->rx_fifo[s->rx_start++];
1448         s->rx_start &= 0x7;
1449         strongarm_ssp_fifo_update(s);
1450         return retval;
1451     default:
1452         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1453         break;
1454     }
1455     return 0;
1456 }
1457
1458 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1459                                 uint64_t value, unsigned size)
1460 {
1461     StrongARMSSPState *s = opaque;
1462
1463     switch (addr) {
1464     case SSCR0:
1465         s->sscr[0] = value & 0xffbf;
1466         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1467             printf("%s: Wrong data size: %i bits\n", __func__,
1468                    (int)SSCR0_DSS(value));
1469         }
1470         if (!(value & SSCR0_SSE)) {
1471             s->sssr = 0;
1472             s->rx_level = 0;
1473         }
1474         strongarm_ssp_fifo_update(s);
1475         break;
1476
1477     case SSCR1:
1478         s->sscr[1] = value & 0x2f;
1479         if (value & SSCR1_LBM) {
1480             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1481         }
1482         strongarm_ssp_fifo_update(s);
1483         break;
1484
1485     case SSSR:
1486         s->sssr &= ~(value & SSSR_RW);
1487         strongarm_ssp_int_update(s);
1488         break;
1489
1490     case SSDR:
1491         if (SSCR0_UWIRE(s->sscr[0])) {
1492             value &= 0xff;
1493         } else
1494             /* Note how 32bits overflow does no harm here */
1495             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1496
1497         /* Data goes from here to the Tx FIFO and is shifted out from
1498          * there directly to the slave, no need to buffer it.
1499          */
1500         if (s->sscr[0] & SSCR0_SSE) {
1501             uint32_t readval;
1502             if (s->sscr[1] & SSCR1_LBM) {
1503                 readval = value;
1504             } else {
1505                 readval = ssi_transfer(s->bus, value);
1506             }
1507
1508             if (s->rx_level < 0x08) {
1509                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1510             } else {
1511                 s->sssr |= SSSR_ROR;
1512             }
1513         }
1514         strongarm_ssp_fifo_update(s);
1515         break;
1516
1517     default:
1518         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1519         break;
1520     }
1521 }
1522
1523 static const MemoryRegionOps strongarm_ssp_ops = {
1524     .read = strongarm_ssp_read,
1525     .write = strongarm_ssp_write,
1526     .endianness = DEVICE_NATIVE_ENDIAN,
1527 };
1528
1529 static int strongarm_ssp_post_load(void *opaque, int version_id)
1530 {
1531     StrongARMSSPState *s = opaque;
1532
1533     strongarm_ssp_fifo_update(s);
1534
1535     return 0;
1536 }
1537
1538 static void strongarm_ssp_init(Object *obj)
1539 {
1540     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1541     DeviceState *dev = DEVICE(sbd);
1542     StrongARMSSPState *s = STRONGARM_SSP(dev);
1543
1544     sysbus_init_irq(sbd, &s->irq);
1545
1546     memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s,
1547                           "ssp", 0x1000);
1548     sysbus_init_mmio(sbd, &s->iomem);
1549
1550     s->bus = ssi_create_bus(dev, "ssi");
1551 }
1552
1553 static void strongarm_ssp_reset(DeviceState *dev)
1554 {
1555     StrongARMSSPState *s = STRONGARM_SSP(dev);
1556
1557     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1558     s->rx_start = 0;
1559     s->rx_level = 0;
1560 }
1561
1562 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1563     .name = "strongarm-ssp",
1564     .version_id = 0,
1565     .minimum_version_id = 0,
1566     .post_load = strongarm_ssp_post_load,
1567     .fields = (VMStateField[]) {
1568         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1569         VMSTATE_UINT16(sssr, StrongARMSSPState),
1570         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1571         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1572         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1573         VMSTATE_END_OF_LIST(),
1574     },
1575 };
1576
1577 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1578 {
1579     DeviceClass *dc = DEVICE_CLASS(klass);
1580
1581     dc->desc = "StrongARM SSP controller";
1582     dc->reset = strongarm_ssp_reset;
1583     dc->vmsd = &vmstate_strongarm_ssp_regs;
1584 }
1585
1586 static const TypeInfo strongarm_ssp_info = {
1587     .name          = TYPE_STRONGARM_SSP,
1588     .parent        = TYPE_SYS_BUS_DEVICE,
1589     .instance_size = sizeof(StrongARMSSPState),
1590     .instance_init = strongarm_ssp_init,
1591     .class_init    = strongarm_ssp_class_init,
1592 };
1593
1594 /* Main CPU functions */
1595 StrongARMState *sa1110_init(const char *cpu_type)
1596 {
1597     StrongARMState *s;
1598     int i;
1599
1600     s = g_new0(StrongARMState, 1);
1601
1602     if (strncmp(cpu_type, "sa1110", 6)) {
1603         error_report("Machine requires a SA1110 processor.");
1604         exit(1);
1605     }
1606
1607     s->cpu = ARM_CPU(cpu_create(cpu_type));
1608
1609     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1610                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1611                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1612                     NULL);
1613
1614     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1615                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1616                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1617                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1618                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1619                     NULL);
1620
1621     sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1622                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1623
1624     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1625
1626     s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1627
1628     for (i = 0; sa_serial[i].io_base; i++) {
1629         DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1630         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
1631         qdev_init_nofail(dev);
1632         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1633                 sa_serial[i].io_base);
1634         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1635                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1636     }
1637
1638     s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1639                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1640     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1641
1642     return s;
1643 }
1644
1645 static void strongarm_register_types(void)
1646 {
1647     type_register_static(&strongarm_pic_info);
1648     type_register_static(&strongarm_rtc_sysbus_info);
1649     type_register_static(&strongarm_gpio_info);
1650     type_register_static(&strongarm_ppc_info);
1651     type_register_static(&strongarm_uart_info);
1652     type_register_static(&strongarm_ssp_info);
1653 }
1654
1655 type_init(strongarm_register_types)