hw/timer/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/sysbus.h"
  25 #include "sysemu/sysemu.h"
  26 #include "qemu/timer.h"
  27 #include "hw/ptimer.h"
  28
  29 #define D(x)
  30
  31 #define RW_TMR0_DIV   0x00
  32 #define R_TMR0_DATA   0x04
  33 #define RW_TMR0_CTRL  0x08
  34 #define RW_TMR1_DIV   0x10
  35 #define R_TMR1_DATA   0x14
  36 #define RW_TMR1_CTRL  0x18
  37 #define R_TIME        0x38
  38 #define RW_WD_CTRL    0x40
  39 #define R_WD_STAT     0x44
  40 #define RW_INTR_MASK  0x48
  41 #define RW_ACK_INTR   0x4c
  42 #define R_INTR        0x50
  43 #define R_MASKED_INTR 0x54
  44
  45 #define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
  46 #define ETRAX_TIMER(obj) \
  47     OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
  48
  49 typedef struct ETRAXTimerState {
  50     SysBusDevice parent_obj;
  51
  52     MemoryRegion mmio;
  53     qemu_irq irq;
  54     qemu_irq nmi;
  55
  56     QEMUBH *bh_t0;
  57     QEMUBH *bh_t1;
  58     QEMUBH *bh_wd;
  59     ptimer_state *ptimer_t0;
  60     ptimer_state *ptimer_t1;
  61     ptimer_state *ptimer_wd;
  62
  63     int wd_hits;
  64
  65     /* Control registers.  */
  66     uint32_t rw_tmr0_div;
  67     uint32_t r_tmr0_data;
  68     uint32_t rw_tmr0_ctrl;
  69
  70     uint32_t rw_tmr1_div;
  71     uint32_t r_tmr1_data;
  72     uint32_t rw_tmr1_ctrl;
  73
  74     uint32_t rw_wd_ctrl;
  75
  76     uint32_t rw_intr_mask;
  77     uint32_t rw_ack_intr;
  78     uint32_t r_intr;
  79     uint32_t r_masked_intr;
  80 } ETRAXTimerState;
  81
  82 static uint64_t
  83 timer_read(void *opaque, hwaddr addr, unsigned int size)
  84 {
  85     ETRAXTimerState *t = opaque;
  86     uint32_t r = 0;
  87
  88     switch (addr) {
  89     case R_TMR0_DATA:
  90         r = ptimer_get_count(t->ptimer_t0);
  91         break;
  92     case R_TMR1_DATA:
  93         r = ptimer_get_count(t->ptimer_t1);
  94         break;
  95     case R_TIME:
  96         r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
  97         break;
  98     case RW_INTR_MASK:
  99         r = t->rw_intr_mask;
 100         break;
 101     case R_MASKED_INTR:
 102         r = t->r_intr & t->rw_intr_mask;
 103         break;
 104     default:
 105         D(printf ("%s %x\n", __func__, addr));
 106         break;
 107     }
 108     return r;
 109 }
 110
 111 static void update_ctrl(ETRAXTimerState *t, int tnum)
 112 {
 113     unsigned int op;
 114     unsigned int freq;
 115     unsigned int freq_hz;
 116     unsigned int div;
 117     uint32_t ctrl;
 118
 119     ptimer_state *timer;
 120
 121     if (tnum == 0) {
 122         ctrl = t->rw_tmr0_ctrl;
 123         div = t->rw_tmr0_div;
 124         timer = t->ptimer_t0;
 125     } else {
 126         ctrl = t->rw_tmr1_ctrl;
 127         div = t->rw_tmr1_div;
 128         timer = t->ptimer_t1;
 129     }
 130
 131
 132     op = ctrl & 3;
 133     freq = ctrl >> 2;
 134     freq_hz = 32000000;
 135
 136     switch (freq)
 137     {
 138     case 0:
 139     case 1:
 140         D(printf ("extern or disabled timer clock?\n"));
 141         break;
 142     case 4: freq_hz =  29493000; break;
 143     case 5: freq_hz =  32000000; break;
 144     case 6: freq_hz =  32768000; break;
 145     case 7: freq_hz = 100000000; break;
 146     default:
 147         abort();
 148         break;
 149     }
 150
 151     D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 152     ptimer_set_freq(timer, freq_hz);
 153     ptimer_set_limit(timer, div, 0);
 154
 155     switch (op)
 156     {
 157         case 0:
 158             /* Load.  */
 159             ptimer_set_limit(timer, div, 1);
 160             break;
 161         case 1:
 162             /* Hold.  */
 163             ptimer_stop(timer);
 164             break;
 165         case 2:
 166             /* Run.  */
 167             ptimer_run(timer, 0);
 168             break;
 169         default:
 170             abort();
 171             break;
 172     }
 173 }
 174
 175 static void timer_update_irq(ETRAXTimerState *t)
 176 {
 177     t->r_intr &= ~(t->rw_ack_intr);
 178     t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 179
 180     D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 181     qemu_set_irq(t->irq, !!t->r_masked_intr);
 182 }
 183
 184 static void timer0_hit(void *opaque)
 185 {
 186     ETRAXTimerState *t = opaque;
 187     t->r_intr |= 1;
 188     timer_update_irq(t);
 189 }
 190
 191 static void timer1_hit(void *opaque)
 192 {
 193     ETRAXTimerState *t = opaque;
 194     t->r_intr |= 2;
 195     timer_update_irq(t);
 196 }
 197
 198 static void watchdog_hit(void *opaque)
 199 {
 200     ETRAXTimerState *t = opaque;
 201     if (t->wd_hits == 0) {
 202         /* real hw gives a single tick before reseting but we are
 203            a bit friendlier to compensate for our slower execution.  */
 204         ptimer_set_count(t->ptimer_wd, 10);
 205         ptimer_run(t->ptimer_wd, 1);
 206         qemu_irq_raise(t->nmi);
 207     }
 208     else
 209         qemu_system_reset_request();
 210
 211     t->wd_hits++;
 212 }
 213
 214 static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
 215 {
 216     unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 217     unsigned int wd_key = t->rw_wd_ctrl >> 9;
 218     unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 219     unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 220     unsigned int new_cmd = (value >> 8) & 1;
 221
 222     /* If the watchdog is enabled, they written key must match the
 223        complement of the previous.  */
 224     wd_key = ~wd_key & ((1 << 7) - 1);
 225
 226     if (wd_en && wd_key != new_key)
 227         return;
 228
 229     D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 230          wd_en, new_key, wd_key, new_cmd, wd_cnt));
 231
 232     if (t->wd_hits)
 233         qemu_irq_lower(t->nmi);
 234
 235     t->wd_hits = 0;
 236
 237     ptimer_set_freq(t->ptimer_wd, 760);
 238     if (wd_cnt == 0)
 239         wd_cnt = 256;
 240     ptimer_set_count(t->ptimer_wd, wd_cnt);
 241     if (new_cmd)
 242         ptimer_run(t->ptimer_wd, 1);
 243     else
 244         ptimer_stop(t->ptimer_wd);
 245
 246     t->rw_wd_ctrl = value;
 247 }
 248
 249 static void
 250 timer_write(void *opaque, hwaddr addr,
 251             uint64_t val64, unsigned int size)
 252 {
 253     ETRAXTimerState *t = opaque;
 254     uint32_t value = val64;
 255
 256     switch (addr)
 257     {
 258         case RW_TMR0_DIV:
 259             t->rw_tmr0_div = value;
 260             break;
 261         case RW_TMR0_CTRL:
 262             D(printf ("RW_TMR0_CTRL=%x\n", value));
 263             t->rw_tmr0_ctrl = value;
 264             update_ctrl(t, 0);
 265             break;
 266         case RW_TMR1_DIV:
 267             t->rw_tmr1_div = value;
 268             break;
 269         case RW_TMR1_CTRL:
 270             D(printf ("RW_TMR1_CTRL=%x\n", value));
 271             t->rw_tmr1_ctrl = value;
 272             update_ctrl(t, 1);
 273             break;
 274         case RW_INTR_MASK:
 275             D(printf ("RW_INTR_MASK=%x\n", value));
 276             t->rw_intr_mask = value;
 277             timer_update_irq(t);
 278             break;
 279         case RW_WD_CTRL:
 280             timer_watchdog_update(t, value);
 281             break;
 282         case RW_ACK_INTR:
 283             t->rw_ack_intr = value;
 284             timer_update_irq(t);
 285             t->rw_ack_intr = 0;
 286             break;
 287         default:
 288             printf ("%s " TARGET_FMT_plx " %x\n",
 289                 __func__, addr, value);
 290             break;
 291     }
 292 }
 293
 294 static const MemoryRegionOps timer_ops = {
 295     .read = timer_read,
 296     .write = timer_write,
 297     .endianness = DEVICE_LITTLE_ENDIAN,
 298     .valid = {
 299         .min_access_size = 4,
 300         .max_access_size = 4
 301     }
 302 };
 303
 304 static void etraxfs_timer_reset(void *opaque)
 305 {
 306     ETRAXTimerState *t = opaque;
 307
 308     ptimer_stop(t->ptimer_t0);
 309     ptimer_stop(t->ptimer_t1);
 310     ptimer_stop(t->ptimer_wd);
 311     t->rw_wd_ctrl = 0;
 312     t->r_intr = 0;
 313     t->rw_intr_mask = 0;
 314     qemu_irq_lower(t->irq);
 315 }
 316
 317 static int etraxfs_timer_init(SysBusDevice *dev)
 318 {
 319     ETRAXTimerState *t = ETRAX_TIMER(dev);
 320
 321     t->bh_t0 = qemu_bh_new(timer0_hit, t);
 322     t->bh_t1 = qemu_bh_new(timer1_hit, t);
 323     t->bh_wd = qemu_bh_new(watchdog_hit, t);
 324     t->ptimer_t0 = ptimer_init(t->bh_t0);
 325     t->ptimer_t1 = ptimer_init(t->bh_t1);
 326     t->ptimer_wd = ptimer_init(t->bh_wd);
 327
 328     sysbus_init_irq(dev, &t->irq);
 329     sysbus_init_irq(dev, &t->nmi);
 330
 331     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
 332                           "etraxfs-timer", 0x5c);
 333     sysbus_init_mmio(dev, &t->mmio);
 334     qemu_register_reset(etraxfs_timer_reset, t);
 335     return 0;
 336 }
 337
 338 static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
 339 {
 340     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 341
 342     sdc->init = etraxfs_timer_init;
 343 }
 344
 345 static const TypeInfo etraxfs_timer_info = {
 346     .name          = TYPE_ETRAX_FS_TIMER,
 347     .parent        = TYPE_SYS_BUS_DEVICE,
 348     .instance_size = sizeof(ETRAXTimerState),
 349     .class_init    = etraxfs_timer_class_init,
 350 };
 351
 352 static void etraxfs_timer_register_types(void)
 353 {
 354     type_register_static(&etraxfs_timer_info);
 355 }
 356
 357 type_init(etraxfs_timer_register_types)