hw/intc/puv3_intc.c

   1 /*
   2  * INTC device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #include "hw/sysbus.h"
  12
  13 #undef DEBUG_PUV3
  14 #include "hw/unicore32/puv3.h"
  15
  16 #define TYPE_PUV3_INTC "puv3_intc"
  17 #define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
  18
  19 typedef struct PUV3INTCState {
  20     SysBusDevice parent_obj;
  21
  22     MemoryRegion iomem;
  23     qemu_irq parent_irq;
  24
  25     uint32_t reg_ICMR;
  26     uint32_t reg_ICPR;
  27 } PUV3INTCState;
  28
  29 /* Update interrupt status after enabled or pending bits have been changed.  */
  30 static void puv3_intc_update(PUV3INTCState *s)
  31 {
  32     if (s->reg_ICMR & s->reg_ICPR) {
  33         qemu_irq_raise(s->parent_irq);
  34     } else {
  35         qemu_irq_lower(s->parent_irq);
  36     }
  37 }
  38
  39 /* Process a change in an external INTC input. */
  40 static void puv3_intc_handler(void *opaque, int irq, int level)
  41 {
  42     PUV3INTCState *s = opaque;
  43
  44     DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
  45     if (level) {
  46         s->reg_ICPR |= (1 << irq);
  47     } else {
  48         s->reg_ICPR &= ~(1 << irq);
  49     }
  50     puv3_intc_update(s);
  51 }
  52
  53 static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
  54         unsigned size)
  55 {
  56     PUV3INTCState *s = opaque;
  57     uint32_t ret = 0;
  58
  59     switch (offset) {
  60     case 0x04: /* INTC_ICMR */
  61         ret = s->reg_ICMR;
  62         break;
  63     case 0x0c: /* INTC_ICIP */
  64         ret = s->reg_ICPR; /* the same value with ICPR */
  65         break;
  66     default:
  67         DPRINTF("Bad offset %x\n", (int)offset);
  68     }
  69     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  70     return ret;
  71 }
  72
  73 static void puv3_intc_write(void *opaque, hwaddr offset,
  74         uint64_t value, unsigned size)
  75 {
  76     PUV3INTCState *s = opaque;
  77
  78     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  79     switch (offset) {
  80     case 0x00: /* INTC_ICLR */
  81     case 0x14: /* INTC_ICCR */
  82         break;
  83     case 0x04: /* INTC_ICMR */
  84         s->reg_ICMR = value;
  85         break;
  86     default:
  87         DPRINTF("Bad offset 0x%x\n", (int)offset);
  88         return;
  89     }
  90     puv3_intc_update(s);
  91 }
  92
  93 static const MemoryRegionOps puv3_intc_ops = {
  94     .read = puv3_intc_read,
  95     .write = puv3_intc_write,
  96     .impl = {
  97         .min_access_size = 4,
  98         .max_access_size = 4,
  99     },
 100     .endianness = DEVICE_NATIVE_ENDIAN,
 101 };
 102
 103 static int puv3_intc_init(SysBusDevice *sbd)
 104 {
 105     DeviceState *dev = DEVICE(sbd);
 106     PUV3INTCState *s = PUV3_INTC(dev);
 107
 108     qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
 109     sysbus_init_irq(sbd, &s->parent_irq);
 110
 111     s->reg_ICMR = 0;
 112     s->reg_ICPR = 0;
 113
 114     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
 115                           PUV3_REGS_OFFSET);
 116     sysbus_init_mmio(sbd, &s->iomem);
 117
 118     return 0;
 119 }
 120
 121 static void puv3_intc_class_init(ObjectClass *klass, void *data)
 122 {
 123     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 124
 125     sdc->init = puv3_intc_init;
 126 }
 127
 128 static const TypeInfo puv3_intc_info = {
 129     .name = TYPE_PUV3_INTC,
 130     .parent = TYPE_SYS_BUS_DEVICE,
 131     .instance_size = sizeof(PUV3INTCState),
 132     .class_init = puv3_intc_class_init,
 133 };
 134
 135 static void puv3_intc_register_type(void)
 136 {
 137     type_register_static(&puv3_intc_info);
 138 }
 139
 140 type_init(puv3_intc_register_type)