2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 # define LOG_DISAS(...) do { } while (0)
50 /*****************************************************************************/
51 /* Code translation helpers */
53 /* global register indexes */
54 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i64 cpu_fpr
[32];
63 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
64 static TCGv_i64 cpu_vsr
[32];
65 static TCGv_i32 cpu_crf
[8];
70 #if defined(TARGET_PPC64)
73 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
74 static TCGv cpu_reserve
;
75 static TCGv cpu_reserve_val
;
76 static TCGv cpu_fpscr
;
77 static TCGv_i32 cpu_access_type
;
79 #include "exec/gen-icount.h"
81 void ppc_translate_init(void)
85 size_t cpu_reg_names_size
;
88 cpu_reg_names_size
= sizeof(cpu_reg_names
);
90 for (i
= 0; i
< 8; i
++) {
91 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
92 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
93 offsetof(CPUPPCState
, crf
[i
]), p
);
95 cpu_reg_names_size
-= 5;
98 for (i
= 0; i
< 32; i
++) {
99 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
100 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
101 offsetof(CPUPPCState
, gpr
[i
]), p
);
102 p
+= (i
< 10) ? 3 : 4;
103 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
104 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
105 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
106 offsetof(CPUPPCState
, gprh
[i
]), p
);
107 p
+= (i
< 10) ? 4 : 5;
108 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
110 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
111 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
112 offsetof(CPUPPCState
, fpr
[i
]), p
);
113 p
+= (i
< 10) ? 4 : 5;
114 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
116 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
117 #ifdef HOST_WORDS_BIGENDIAN
118 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
119 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
124 p
+= (i
< 10) ? 6 : 7;
125 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
127 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
128 #ifdef HOST_WORDS_BIGENDIAN
129 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
130 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
135 p
+= (i
< 10) ? 6 : 7;
136 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
137 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
138 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
139 offsetof(CPUPPCState
, vsr
[i
]), p
);
140 p
+= (i
< 10) ? 5 : 6;
141 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
144 cpu_nip
= tcg_global_mem_new(cpu_env
,
145 offsetof(CPUPPCState
, nip
), "nip");
147 cpu_msr
= tcg_global_mem_new(cpu_env
,
148 offsetof(CPUPPCState
, msr
), "msr");
150 cpu_ctr
= tcg_global_mem_new(cpu_env
,
151 offsetof(CPUPPCState
, ctr
), "ctr");
153 cpu_lr
= tcg_global_mem_new(cpu_env
,
154 offsetof(CPUPPCState
, lr
), "lr");
156 #if defined(TARGET_PPC64)
157 cpu_cfar
= tcg_global_mem_new(cpu_env
,
158 offsetof(CPUPPCState
, cfar
), "cfar");
161 cpu_xer
= tcg_global_mem_new(cpu_env
,
162 offsetof(CPUPPCState
, xer
), "xer");
163 cpu_so
= tcg_global_mem_new(cpu_env
,
164 offsetof(CPUPPCState
, so
), "SO");
165 cpu_ov
= tcg_global_mem_new(cpu_env
,
166 offsetof(CPUPPCState
, ov
), "OV");
167 cpu_ca
= tcg_global_mem_new(cpu_env
,
168 offsetof(CPUPPCState
, ca
), "CA");
169 cpu_ov32
= tcg_global_mem_new(cpu_env
,
170 offsetof(CPUPPCState
, ov32
), "OV32");
171 cpu_ca32
= tcg_global_mem_new(cpu_env
,
172 offsetof(CPUPPCState
, ca32
), "CA32");
174 cpu_reserve
= tcg_global_mem_new(cpu_env
,
175 offsetof(CPUPPCState
, reserve_addr
),
177 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
178 offsetof(CPUPPCState
, reserve_val
),
181 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
182 offsetof(CPUPPCState
, fpscr
), "fpscr");
184 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
185 offsetof(CPUPPCState
, access_type
), "access_type");
188 /* internal defines */
189 struct DisasContext
{
190 struct TranslationBlock
*tb
;
194 /* Routine used to access memory */
195 bool pr
, hv
, dr
, le_mode
;
197 bool need_access_type
;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask
;
202 #if defined(TARGET_PPC64)
207 bool altivec_enabled
;
212 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled
;
214 uint64_t insns_flags
;
215 uint64_t insns_flags2
;
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext
*ctx
)
221 #if defined(TARGET_WORDS_BIGENDIAN)
224 return !ctx
->le_mode
;
228 /* True when active word size < size of target_long. */
230 # define NARROW_MODE(C) (!(C)->sf_mode)
232 # define NARROW_MODE(C) 0
235 struct opc_handler_t
{
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240 /* instruction type */
242 /* extended instruction type */
245 void (*handler
)(DisasContext
*ctx
);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
249 #if defined(DO_PPC_STATISTICS)
254 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
256 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
257 tcg_gen_movi_i32(cpu_access_type
, access_type
);
258 ctx
->access_type
= access_type
;
262 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
264 if (NARROW_MODE(ctx
)) {
267 tcg_gen_movi_tl(cpu_nip
, nip
);
270 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
277 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
278 gen_update_nip(ctx
, ctx
->nip
- 4);
280 t0
= tcg_const_i32(excp
);
281 t1
= tcg_const_i32(error
);
282 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
283 tcg_temp_free_i32(t0
);
284 tcg_temp_free_i32(t1
);
285 ctx
->exception
= (excp
);
288 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
295 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
296 gen_update_nip(ctx
, ctx
->nip
- 4);
298 t0
= tcg_const_i32(excp
);
299 gen_helper_raise_exception(cpu_env
, t0
);
300 tcg_temp_free_i32(t0
);
301 ctx
->exception
= (excp
);
304 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
309 gen_update_nip(ctx
, nip
);
310 t0
= tcg_const_i32(excp
);
311 gen_helper_raise_exception(cpu_env
, t0
);
312 tcg_temp_free_i32(t0
);
313 ctx
->exception
= (excp
);
316 static void gen_debug_exception(DisasContext
*ctx
)
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
323 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
324 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
325 gen_update_nip(ctx
, ctx
->nip
);
327 t0
= tcg_const_i32(EXCP_DEBUG
);
328 gen_helper_raise_exception(cpu_env
, t0
);
329 tcg_temp_free_i32(t0
);
332 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
338 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
340 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
343 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext
*ctx
)
352 gen_update_nip(ctx
, ctx
->nip
);
353 ctx
->exception
= POWERPC_EXCP_STOP
;
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext
*ctx
)
360 ctx
->exception
= POWERPC_EXCP_SYNC
;
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
382 typedef struct opcode_t
{
383 unsigned char opc1
, opc2
, opc3
, opc4
;
384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
385 unsigned char pad
[4];
387 opc_handler_t handler
;
391 /* Helpers for priv. check */
394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
397 #if defined(CONFIG_USER_ONLY)
398 #define CHK_HV GEN_PRIV
399 #define CHK_SV GEN_PRIV
400 #define CHK_HVRM GEN_PRIV
404 if (unlikely(ctx->pr || !ctx->hv)) { \
410 if (unlikely(ctx->pr)) { \
416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
424 /*****************************************************************************/
425 /* PowerPC instructions table */
427 #if defined(DO_PPC_STATISTICS)
428 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
438 .handler = &gen_##name, \
439 .oname = stringify(name), \
441 .oname = stringify(name), \
443 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
454 .handler = &gen_##name, \
455 .oname = stringify(name), \
457 .oname = stringify(name), \
459 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
469 .handler = &gen_##name, \
474 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
487 .oname = stringify(name), \
489 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
499 .handler = &gen_##name, \
505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
515 .handler = &gen_##name, \
517 .oname = stringify(name), \
519 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
530 .handler = &gen_##name, \
532 .oname = stringify(name), \
534 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
544 .handler = &gen_##name, \
548 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
558 .handler = &gen_##name, \
560 .oname = stringify(name), \
562 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
572 .handler = &gen_##name, \
578 /* SPR load/store helpers */
579 static inline void gen_load_spr(TCGv t
, int reg
)
581 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
584 static inline void gen_store_spr(int reg
, TCGv t
)
586 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
589 /* Invalid instruction */
590 static void gen_invalid(DisasContext
*ctx
)
592 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
595 static opc_handler_t invalid_handler
= {
596 .inval1
= 0xFFFFFFFF,
597 .inval2
= 0xFFFFFFFF,
600 .handler
= gen_invalid
,
603 /*** Integer comparison ***/
605 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
607 TCGv t0
= tcg_temp_new();
608 TCGv_i32 t1
= tcg_temp_new_i32();
610 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
612 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
613 tcg_gen_trunc_tl_i32(t1
, t0
);
614 tcg_gen_shli_i32(t1
, t1
, CRF_LT_BIT
);
615 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
617 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
618 tcg_gen_trunc_tl_i32(t1
, t0
);
619 tcg_gen_shli_i32(t1
, t1
, CRF_GT_BIT
);
620 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
622 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
623 tcg_gen_trunc_tl_i32(t1
, t0
);
624 tcg_gen_shli_i32(t1
, t1
, CRF_EQ_BIT
);
625 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
628 tcg_temp_free_i32(t1
);
631 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
633 TCGv t0
= tcg_const_tl(arg1
);
634 gen_op_cmp(arg0
, t0
, s
, crf
);
638 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
644 tcg_gen_ext32s_tl(t0
, arg0
);
645 tcg_gen_ext32s_tl(t1
, arg1
);
647 tcg_gen_ext32u_tl(t0
, arg0
);
648 tcg_gen_ext32u_tl(t1
, arg1
);
650 gen_op_cmp(t0
, t1
, s
, crf
);
655 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
657 TCGv t0
= tcg_const_tl(arg1
);
658 gen_op_cmp32(arg0
, t0
, s
, crf
);
662 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
664 if (NARROW_MODE(ctx
)) {
665 gen_op_cmpi32(reg
, 0, 1, 0);
667 gen_op_cmpi(reg
, 0, 1, 0);
672 static void gen_cmp(DisasContext
*ctx
)
674 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
675 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
676 1, crfD(ctx
->opcode
));
678 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
679 1, crfD(ctx
->opcode
));
684 static void gen_cmpi(DisasContext
*ctx
)
686 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
687 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
688 1, crfD(ctx
->opcode
));
690 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
691 1, crfD(ctx
->opcode
));
696 static void gen_cmpl(DisasContext
*ctx
)
698 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
699 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
700 0, crfD(ctx
->opcode
));
702 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
703 0, crfD(ctx
->opcode
));
708 static void gen_cmpli(DisasContext
*ctx
)
710 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
711 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
712 0, crfD(ctx
->opcode
));
714 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
715 0, crfD(ctx
->opcode
));
719 /* cmprb - range comparison: isupper, isaplha, islower*/
720 static void gen_cmprb(DisasContext
*ctx
)
722 TCGv_i32 src1
= tcg_temp_new_i32();
723 TCGv_i32 src2
= tcg_temp_new_i32();
724 TCGv_i32 src2lo
= tcg_temp_new_i32();
725 TCGv_i32 src2hi
= tcg_temp_new_i32();
726 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
728 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
729 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
731 tcg_gen_andi_i32(src1
, src1
, 0xFF);
732 tcg_gen_ext8u_i32(src2lo
, src2
);
733 tcg_gen_shri_i32(src2
, src2
, 8);
734 tcg_gen_ext8u_i32(src2hi
, src2
);
736 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
737 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
738 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
740 if (ctx
->opcode
& 0x00200000) {
741 tcg_gen_shri_i32(src2
, src2
, 8);
742 tcg_gen_ext8u_i32(src2lo
, src2
);
743 tcg_gen_shri_i32(src2
, src2
, 8);
744 tcg_gen_ext8u_i32(src2hi
, src2
);
745 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
746 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
747 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
748 tcg_gen_or_i32(crf
, crf
, src2lo
);
750 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
751 tcg_temp_free_i32(src1
);
752 tcg_temp_free_i32(src2
);
753 tcg_temp_free_i32(src2lo
);
754 tcg_temp_free_i32(src2hi
);
757 #if defined(TARGET_PPC64)
759 static void gen_cmpeqb(DisasContext
*ctx
)
761 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
762 cpu_gpr
[rB(ctx
->opcode
)]);
766 /* isel (PowerPC 2.03 specification) */
767 static void gen_isel(DisasContext
*ctx
)
769 uint32_t bi
= rC(ctx
->opcode
);
770 uint32_t mask
= 0x08 >> (bi
& 0x03);
771 TCGv t0
= tcg_temp_new();
774 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
775 tcg_gen_andi_tl(t0
, t0
, mask
);
777 zr
= tcg_const_tl(0);
778 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
779 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
780 cpu_gpr
[rB(ctx
->opcode
)]);
785 /* cmpb: PowerPC 2.05 specification */
786 static void gen_cmpb(DisasContext
*ctx
)
788 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
789 cpu_gpr
[rB(ctx
->opcode
)]);
792 /*** Integer arithmetic ***/
794 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
795 TCGv arg1
, TCGv arg2
, int sub
)
797 TCGv t0
= tcg_temp_new();
799 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
800 tcg_gen_xor_tl(t0
, arg1
, arg2
);
802 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
804 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
807 if (NARROW_MODE(ctx
)) {
808 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
809 if (is_isa300(ctx
)) {
810 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
813 if (is_isa300(ctx
)) {
814 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
816 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
818 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
821 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
822 TCGv res
, TCGv arg0
, TCGv arg1
,
827 if (!is_isa300(ctx
)) {
833 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
835 tcg_gen_xor_tl(t0
, arg0
, arg1
);
837 tcg_gen_xor_tl(t0
, t0
, res
);
838 tcg_gen_extract_tl(cpu_ca32
, t0
, 32, 1);
842 /* Common add function */
843 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
844 TCGv arg2
, bool add_ca
, bool compute_ca
,
845 bool compute_ov
, bool compute_rc0
)
849 if (compute_ca
|| compute_ov
) {
854 if (NARROW_MODE(ctx
)) {
855 /* Caution: a non-obvious corner case of the spec is that we
856 must produce the *entire* 64-bit addition, but produce the
857 carry into bit 32. */
858 TCGv t1
= tcg_temp_new();
859 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
860 tcg_gen_add_tl(t0
, arg1
, arg2
);
862 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
864 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
866 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
867 if (is_isa300(ctx
)) {
868 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
871 TCGv zero
= tcg_const_tl(0);
873 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
874 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
876 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
878 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, 0);
882 tcg_gen_add_tl(t0
, arg1
, arg2
);
884 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
889 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
891 if (unlikely(compute_rc0
)) {
892 gen_set_Rc0(ctx
, t0
);
896 tcg_gen_mov_tl(ret
, t0
);
900 /* Add functions with two operands */
901 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
902 static void glue(gen_, name)(DisasContext *ctx) \
904 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
905 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
906 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
908 /* Add functions with one operand and one immediate */
909 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
910 add_ca, compute_ca, compute_ov) \
911 static void glue(gen_, name)(DisasContext *ctx) \
913 TCGv t0 = tcg_const_tl(const_val); \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], t0, \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
920 /* add add. addo addo. */
921 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
922 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
923 /* addc addc. addco addco. */
924 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
925 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
926 /* adde adde. addeo addeo. */
927 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
928 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
929 /* addme addme. addmeo addmeo. */
930 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
931 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
932 /* addze addze. addzeo addzeo.*/
933 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
934 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
936 static void gen_addi(DisasContext
*ctx
)
938 target_long simm
= SIMM(ctx
->opcode
);
940 if (rA(ctx
->opcode
) == 0) {
942 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
944 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
945 cpu_gpr
[rA(ctx
->opcode
)], simm
);
949 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
951 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
952 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
953 c
, 0, 1, 0, compute_rc0
);
957 static void gen_addic(DisasContext
*ctx
)
959 gen_op_addic(ctx
, 0);
962 static void gen_addic_(DisasContext
*ctx
)
964 gen_op_addic(ctx
, 1);
968 static void gen_addis(DisasContext
*ctx
)
970 target_long simm
= SIMM(ctx
->opcode
);
972 if (rA(ctx
->opcode
) == 0) {
974 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
976 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
977 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
982 static void gen_addpcis(DisasContext
*ctx
)
984 target_long d
= DX(ctx
->opcode
);
986 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->nip
+ (d
<< 16));
989 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
990 TCGv arg2
, int sign
, int compute_ov
)
992 TCGv_i32 t0
= tcg_temp_new_i32();
993 TCGv_i32 t1
= tcg_temp_new_i32();
994 TCGv_i32 t2
= tcg_temp_new_i32();
995 TCGv_i32 t3
= tcg_temp_new_i32();
997 tcg_gen_trunc_tl_i32(t0
, arg1
);
998 tcg_gen_trunc_tl_i32(t1
, arg2
);
1000 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1001 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1002 tcg_gen_and_i32(t2
, t2
, t3
);
1003 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1004 tcg_gen_or_i32(t2
, t2
, t3
);
1005 tcg_gen_movi_i32(t3
, 0);
1006 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1007 tcg_gen_div_i32(t3
, t0
, t1
);
1008 tcg_gen_extu_i32_tl(ret
, t3
);
1010 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1011 tcg_gen_movi_i32(t3
, 0);
1012 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1013 tcg_gen_divu_i32(t3
, t0
, t1
);
1014 tcg_gen_extu_i32_tl(ret
, t3
);
1017 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1018 if (is_isa300(ctx
)) {
1019 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1021 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1023 tcg_temp_free_i32(t0
);
1024 tcg_temp_free_i32(t1
);
1025 tcg_temp_free_i32(t2
);
1026 tcg_temp_free_i32(t3
);
1028 if (unlikely(Rc(ctx
->opcode
) != 0))
1029 gen_set_Rc0(ctx
, ret
);
1032 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1033 static void glue(gen_, name)(DisasContext *ctx) \
1035 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1036 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1037 sign, compute_ov); \
1039 /* divwu divwu. divwuo divwuo. */
1040 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1041 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1042 /* divw divw. divwo divwo. */
1043 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1044 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1046 /* div[wd]eu[o][.] */
1047 #define GEN_DIVE(name, hlpr, compute_ov) \
1048 static void gen_##name(DisasContext *ctx) \
1050 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1051 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1052 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1053 tcg_temp_free_i32(t0); \
1054 if (unlikely(Rc(ctx->opcode) != 0)) { \
1055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1059 GEN_DIVE(divweu
, divweu
, 0);
1060 GEN_DIVE(divweuo
, divweu
, 1);
1061 GEN_DIVE(divwe
, divwe
, 0);
1062 GEN_DIVE(divweo
, divwe
, 1);
1064 #if defined(TARGET_PPC64)
1065 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1066 TCGv arg2
, int sign
, int compute_ov
)
1068 TCGv_i64 t0
= tcg_temp_new_i64();
1069 TCGv_i64 t1
= tcg_temp_new_i64();
1070 TCGv_i64 t2
= tcg_temp_new_i64();
1071 TCGv_i64 t3
= tcg_temp_new_i64();
1073 tcg_gen_mov_i64(t0
, arg1
);
1074 tcg_gen_mov_i64(t1
, arg2
);
1076 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1077 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1078 tcg_gen_and_i64(t2
, t2
, t3
);
1079 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1080 tcg_gen_or_i64(t2
, t2
, t3
);
1081 tcg_gen_movi_i64(t3
, 0);
1082 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1083 tcg_gen_div_i64(ret
, t0
, t1
);
1085 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1086 tcg_gen_movi_i64(t3
, 0);
1087 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1088 tcg_gen_divu_i64(ret
, t0
, t1
);
1091 tcg_gen_mov_tl(cpu_ov
, t2
);
1092 if (is_isa300(ctx
)) {
1093 tcg_gen_mov_tl(cpu_ov32
, t2
);
1095 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1097 tcg_temp_free_i64(t0
);
1098 tcg_temp_free_i64(t1
);
1099 tcg_temp_free_i64(t2
);
1100 tcg_temp_free_i64(t3
);
1102 if (unlikely(Rc(ctx
->opcode
) != 0))
1103 gen_set_Rc0(ctx
, ret
);
1106 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1107 static void glue(gen_, name)(DisasContext *ctx) \
1109 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1110 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1111 sign, compute_ov); \
1113 /* divdu divdu. divduo divduo. */
1114 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1115 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1116 /* divd divd. divdo divdo. */
1117 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1118 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1120 GEN_DIVE(divdeu
, divdeu
, 0);
1121 GEN_DIVE(divdeuo
, divdeu
, 1);
1122 GEN_DIVE(divde
, divde
, 0);
1123 GEN_DIVE(divdeo
, divde
, 1);
1126 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1127 TCGv arg2
, int sign
)
1129 TCGv_i32 t0
= tcg_temp_new_i32();
1130 TCGv_i32 t1
= tcg_temp_new_i32();
1132 tcg_gen_trunc_tl_i32(t0
, arg1
);
1133 tcg_gen_trunc_tl_i32(t1
, arg2
);
1135 TCGv_i32 t2
= tcg_temp_new_i32();
1136 TCGv_i32 t3
= tcg_temp_new_i32();
1137 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1138 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1139 tcg_gen_and_i32(t2
, t2
, t3
);
1140 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1141 tcg_gen_or_i32(t2
, t2
, t3
);
1142 tcg_gen_movi_i32(t3
, 0);
1143 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1144 tcg_gen_rem_i32(t3
, t0
, t1
);
1145 tcg_gen_ext_i32_tl(ret
, t3
);
1146 tcg_temp_free_i32(t2
);
1147 tcg_temp_free_i32(t3
);
1149 TCGv_i32 t2
= tcg_const_i32(1);
1150 TCGv_i32 t3
= tcg_const_i32(0);
1151 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1152 tcg_gen_remu_i32(t3
, t0
, t1
);
1153 tcg_gen_extu_i32_tl(ret
, t3
);
1154 tcg_temp_free_i32(t2
);
1155 tcg_temp_free_i32(t3
);
1157 tcg_temp_free_i32(t0
);
1158 tcg_temp_free_i32(t1
);
1161 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1162 static void glue(gen_, name)(DisasContext *ctx) \
1164 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1165 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1169 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1170 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1172 #if defined(TARGET_PPC64)
1173 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1174 TCGv arg2
, int sign
)
1176 TCGv_i64 t0
= tcg_temp_new_i64();
1177 TCGv_i64 t1
= tcg_temp_new_i64();
1179 tcg_gen_mov_i64(t0
, arg1
);
1180 tcg_gen_mov_i64(t1
, arg2
);
1182 TCGv_i64 t2
= tcg_temp_new_i64();
1183 TCGv_i64 t3
= tcg_temp_new_i64();
1184 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1185 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1186 tcg_gen_and_i64(t2
, t2
, t3
);
1187 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1188 tcg_gen_or_i64(t2
, t2
, t3
);
1189 tcg_gen_movi_i64(t3
, 0);
1190 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1191 tcg_gen_rem_i64(ret
, t0
, t1
);
1192 tcg_temp_free_i64(t2
);
1193 tcg_temp_free_i64(t3
);
1195 TCGv_i64 t2
= tcg_const_i64(1);
1196 TCGv_i64 t3
= tcg_const_i64(0);
1197 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1198 tcg_gen_remu_i64(ret
, t0
, t1
);
1199 tcg_temp_free_i64(t2
);
1200 tcg_temp_free_i64(t3
);
1202 tcg_temp_free_i64(t0
);
1203 tcg_temp_free_i64(t1
);
1206 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1207 static void glue(gen_, name)(DisasContext *ctx) \
1209 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1210 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1214 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1215 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1219 static void gen_mulhw(DisasContext
*ctx
)
1221 TCGv_i32 t0
= tcg_temp_new_i32();
1222 TCGv_i32 t1
= tcg_temp_new_i32();
1224 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1225 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1226 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1227 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1228 tcg_temp_free_i32(t0
);
1229 tcg_temp_free_i32(t1
);
1230 if (unlikely(Rc(ctx
->opcode
) != 0))
1231 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1234 /* mulhwu mulhwu. */
1235 static void gen_mulhwu(DisasContext
*ctx
)
1237 TCGv_i32 t0
= tcg_temp_new_i32();
1238 TCGv_i32 t1
= tcg_temp_new_i32();
1240 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1241 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1242 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1243 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1244 tcg_temp_free_i32(t0
);
1245 tcg_temp_free_i32(t1
);
1246 if (unlikely(Rc(ctx
->opcode
) != 0))
1247 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1251 static void gen_mullw(DisasContext
*ctx
)
1253 #if defined(TARGET_PPC64)
1255 t0
= tcg_temp_new_i64();
1256 t1
= tcg_temp_new_i64();
1257 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1258 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1259 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1263 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1264 cpu_gpr
[rB(ctx
->opcode
)]);
1266 if (unlikely(Rc(ctx
->opcode
) != 0))
1267 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1270 /* mullwo mullwo. */
1271 static void gen_mullwo(DisasContext
*ctx
)
1273 TCGv_i32 t0
= tcg_temp_new_i32();
1274 TCGv_i32 t1
= tcg_temp_new_i32();
1276 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1277 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1278 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1279 #if defined(TARGET_PPC64)
1280 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1282 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1285 tcg_gen_sari_i32(t0
, t0
, 31);
1286 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1287 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1288 if (is_isa300(ctx
)) {
1289 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1291 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1293 tcg_temp_free_i32(t0
);
1294 tcg_temp_free_i32(t1
);
1295 if (unlikely(Rc(ctx
->opcode
) != 0))
1296 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1300 static void gen_mulli(DisasContext
*ctx
)
1302 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1306 #if defined(TARGET_PPC64)
1308 static void gen_mulhd(DisasContext
*ctx
)
1310 TCGv lo
= tcg_temp_new();
1311 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1312 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1314 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1315 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1319 /* mulhdu mulhdu. */
1320 static void gen_mulhdu(DisasContext
*ctx
)
1322 TCGv lo
= tcg_temp_new();
1323 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1324 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1326 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1327 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1332 static void gen_mulld(DisasContext
*ctx
)
1334 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1335 cpu_gpr
[rB(ctx
->opcode
)]);
1336 if (unlikely(Rc(ctx
->opcode
) != 0))
1337 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1340 /* mulldo mulldo. */
1341 static void gen_mulldo(DisasContext
*ctx
)
1343 TCGv_i64 t0
= tcg_temp_new_i64();
1344 TCGv_i64 t1
= tcg_temp_new_i64();
1346 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1347 cpu_gpr
[rB(ctx
->opcode
)]);
1348 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1350 tcg_gen_sari_i64(t0
, t0
, 63);
1351 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1352 if (is_isa300(ctx
)) {
1353 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1355 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1357 tcg_temp_free_i64(t0
);
1358 tcg_temp_free_i64(t1
);
1360 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1361 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1366 /* Common subf function */
1367 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1368 TCGv arg2
, bool add_ca
, bool compute_ca
,
1369 bool compute_ov
, bool compute_rc0
)
1373 if (compute_ca
|| compute_ov
) {
1374 t0
= tcg_temp_new();
1378 /* dest = ~arg1 + arg2 [+ ca]. */
1379 if (NARROW_MODE(ctx
)) {
1380 /* Caution: a non-obvious corner case of the spec is that we
1381 must produce the *entire* 64-bit addition, but produce the
1382 carry into bit 32. */
1383 TCGv inv1
= tcg_temp_new();
1384 TCGv t1
= tcg_temp_new();
1385 tcg_gen_not_tl(inv1
, arg1
);
1387 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1389 tcg_gen_addi_tl(t0
, arg2
, 1);
1391 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1392 tcg_gen_add_tl(t0
, t0
, inv1
);
1393 tcg_temp_free(inv1
);
1394 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1396 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
1397 if (is_isa300(ctx
)) {
1398 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
1400 } else if (add_ca
) {
1401 TCGv zero
, inv1
= tcg_temp_new();
1402 tcg_gen_not_tl(inv1
, arg1
);
1403 zero
= tcg_const_tl(0);
1404 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1405 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1406 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, 0);
1407 tcg_temp_free(zero
);
1408 tcg_temp_free(inv1
);
1410 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1411 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1412 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, 1);
1414 } else if (add_ca
) {
1415 /* Since we're ignoring carry-out, we can simplify the
1416 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1417 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1418 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1419 tcg_gen_subi_tl(t0
, t0
, 1);
1421 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1425 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1427 if (unlikely(compute_rc0
)) {
1428 gen_set_Rc0(ctx
, t0
);
1432 tcg_gen_mov_tl(ret
, t0
);
1436 /* Sub functions with Two operands functions */
1437 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1438 static void glue(gen_, name)(DisasContext *ctx) \
1440 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1441 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1442 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1444 /* Sub functions with one operand and one immediate */
1445 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1446 add_ca, compute_ca, compute_ov) \
1447 static void glue(gen_, name)(DisasContext *ctx) \
1449 TCGv t0 = tcg_const_tl(const_val); \
1450 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1451 cpu_gpr[rA(ctx->opcode)], t0, \
1452 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1453 tcg_temp_free(t0); \
1455 /* subf subf. subfo subfo. */
1456 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1457 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1458 /* subfc subfc. subfco subfco. */
1459 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1460 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1461 /* subfe subfe. subfeo subfo. */
1462 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1463 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1464 /* subfme subfme. subfmeo subfmeo. */
1465 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1466 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1467 /* subfze subfze. subfzeo subfzeo.*/
1468 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1469 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1472 static void gen_subfic(DisasContext
*ctx
)
1474 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1475 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1480 /* neg neg. nego nego. */
1481 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1483 TCGv zero
= tcg_const_tl(0);
1484 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1485 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1486 tcg_temp_free(zero
);
1489 static void gen_neg(DisasContext
*ctx
)
1491 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1492 if (unlikely(Rc(ctx
->opcode
))) {
1493 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1497 static void gen_nego(DisasContext
*ctx
)
1499 gen_op_arith_neg(ctx
, 1);
1502 /*** Integer logical ***/
1503 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1504 static void glue(gen_, name)(DisasContext *ctx) \
1506 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1507 cpu_gpr[rB(ctx->opcode)]); \
1508 if (unlikely(Rc(ctx->opcode) != 0)) \
1509 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1512 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1513 static void glue(gen_, name)(DisasContext *ctx) \
1515 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1516 if (unlikely(Rc(ctx->opcode) != 0)) \
1517 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1521 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1523 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1526 static void gen_andi_(DisasContext
*ctx
)
1528 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1529 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1533 static void gen_andis_(DisasContext
*ctx
)
1535 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1536 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1540 static void gen_cntlzw(DisasContext
*ctx
)
1542 TCGv_i32 t
= tcg_temp_new_i32();
1544 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1545 tcg_gen_clzi_i32(t
, t
, 32);
1546 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1547 tcg_temp_free_i32(t
);
1549 if (unlikely(Rc(ctx
->opcode
) != 0))
1550 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1554 static void gen_cnttzw(DisasContext
*ctx
)
1556 TCGv_i32 t
= tcg_temp_new_i32();
1558 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1559 tcg_gen_ctzi_i32(t
, t
, 32);
1560 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1561 tcg_temp_free_i32(t
);
1563 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1564 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1569 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1570 /* extsb & extsb. */
1571 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1572 /* extsh & extsh. */
1573 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1575 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1577 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1579 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1580 static void gen_pause(DisasContext
*ctx
)
1582 TCGv_i32 t0
= tcg_const_i32(0);
1583 tcg_gen_st_i32(t0
, cpu_env
,
1584 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1585 tcg_temp_free_i32(t0
);
1587 /* Stop translation, this gives other CPUs a chance to run */
1588 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->nip
);
1590 #endif /* defined(TARGET_PPC64) */
1593 static void gen_or(DisasContext
*ctx
)
1597 rs
= rS(ctx
->opcode
);
1598 ra
= rA(ctx
->opcode
);
1599 rb
= rB(ctx
->opcode
);
1600 /* Optimisation for mr. ri case */
1601 if (rs
!= ra
|| rs
!= rb
) {
1603 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1605 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1606 if (unlikely(Rc(ctx
->opcode
) != 0))
1607 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1608 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1609 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1610 #if defined(TARGET_PPC64)
1611 } else if (rs
!= 0) { /* 0 is nop */
1616 /* Set process priority to low */
1620 /* Set process priority to medium-low */
1624 /* Set process priority to normal */
1627 #if !defined(CONFIG_USER_ONLY)
1630 /* Set process priority to very low */
1636 /* Set process priority to medium-hight */
1642 /* Set process priority to high */
1647 if (ctx
->hv
&& !ctx
->pr
) {
1648 /* Set process priority to very high */
1657 TCGv t0
= tcg_temp_new();
1658 gen_load_spr(t0
, SPR_PPR
);
1659 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1660 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1661 gen_store_spr(SPR_PPR
, t0
);
1664 #if !defined(CONFIG_USER_ONLY)
1665 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1666 * CPU and the kernel hangs. This applies to all encodings other
1667 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1668 * and all currently undefined.
1676 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1679 static void gen_xor(DisasContext
*ctx
)
1681 /* Optimisation for "set to zero" case */
1682 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1683 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1685 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1686 if (unlikely(Rc(ctx
->opcode
) != 0))
1687 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1691 static void gen_ori(DisasContext
*ctx
)
1693 target_ulong uimm
= UIMM(ctx
->opcode
);
1695 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1698 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1702 static void gen_oris(DisasContext
*ctx
)
1704 target_ulong uimm
= UIMM(ctx
->opcode
);
1706 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1710 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1714 static void gen_xori(DisasContext
*ctx
)
1716 target_ulong uimm
= UIMM(ctx
->opcode
);
1718 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1722 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1726 static void gen_xoris(DisasContext
*ctx
)
1728 target_ulong uimm
= UIMM(ctx
->opcode
);
1730 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1734 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1737 /* popcntb : PowerPC 2.03 specification */
1738 static void gen_popcntb(DisasContext
*ctx
)
1740 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1743 static void gen_popcntw(DisasContext
*ctx
)
1745 #if defined(TARGET_PPC64)
1746 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1748 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1752 #if defined(TARGET_PPC64)
1753 /* popcntd: PowerPC 2.06 specification */
1754 static void gen_popcntd(DisasContext
*ctx
)
1756 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1760 /* prtyw: PowerPC 2.05 specification */
1761 static void gen_prtyw(DisasContext
*ctx
)
1763 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1764 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1765 TCGv t0
= tcg_temp_new();
1766 tcg_gen_shri_tl(t0
, rs
, 16);
1767 tcg_gen_xor_tl(ra
, rs
, t0
);
1768 tcg_gen_shri_tl(t0
, ra
, 8);
1769 tcg_gen_xor_tl(ra
, ra
, t0
);
1770 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1774 #if defined(TARGET_PPC64)
1775 /* prtyd: PowerPC 2.05 specification */
1776 static void gen_prtyd(DisasContext
*ctx
)
1778 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1779 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1780 TCGv t0
= tcg_temp_new();
1781 tcg_gen_shri_tl(t0
, rs
, 32);
1782 tcg_gen_xor_tl(ra
, rs
, t0
);
1783 tcg_gen_shri_tl(t0
, ra
, 16);
1784 tcg_gen_xor_tl(ra
, ra
, t0
);
1785 tcg_gen_shri_tl(t0
, ra
, 8);
1786 tcg_gen_xor_tl(ra
, ra
, t0
);
1787 tcg_gen_andi_tl(ra
, ra
, 1);
1792 #if defined(TARGET_PPC64)
1794 static void gen_bpermd(DisasContext
*ctx
)
1796 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1797 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1801 #if defined(TARGET_PPC64)
1802 /* extsw & extsw. */
1803 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1806 static void gen_cntlzd(DisasContext
*ctx
)
1808 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1809 if (unlikely(Rc(ctx
->opcode
) != 0))
1810 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1814 static void gen_cnttzd(DisasContext
*ctx
)
1816 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1817 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1818 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1823 static void gen_darn(DisasContext
*ctx
)
1825 int l
= L(ctx
->opcode
);
1828 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
1829 } else if (l
<= 2) {
1830 /* Return 64-bit random for both CRN and RRN */
1831 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
1833 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
1838 /*** Integer rotate ***/
1840 /* rlwimi & rlwimi. */
1841 static void gen_rlwimi(DisasContext
*ctx
)
1843 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1844 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1845 uint32_t sh
= SH(ctx
->opcode
);
1846 uint32_t mb
= MB(ctx
->opcode
);
1847 uint32_t me
= ME(ctx
->opcode
);
1849 if (sh
== (31-me
) && mb
<= me
) {
1850 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1855 #if defined(TARGET_PPC64)
1859 mask
= MASK(mb
, me
);
1861 t1
= tcg_temp_new();
1862 if (mask
<= 0xffffffffu
) {
1863 TCGv_i32 t0
= tcg_temp_new_i32();
1864 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1865 tcg_gen_rotli_i32(t0
, t0
, sh
);
1866 tcg_gen_extu_i32_tl(t1
, t0
);
1867 tcg_temp_free_i32(t0
);
1869 #if defined(TARGET_PPC64)
1870 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1871 tcg_gen_rotli_i64(t1
, t1
, sh
);
1873 g_assert_not_reached();
1877 tcg_gen_andi_tl(t1
, t1
, mask
);
1878 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1879 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1882 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1883 gen_set_Rc0(ctx
, t_ra
);
1887 /* rlwinm & rlwinm. */
1888 static void gen_rlwinm(DisasContext
*ctx
)
1890 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1891 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1892 int sh
= SH(ctx
->opcode
);
1893 int mb
= MB(ctx
->opcode
);
1894 int me
= ME(ctx
->opcode
);
1895 int len
= me
- mb
+ 1;
1896 int rsh
= (32 - sh
) & 31;
1898 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
1899 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
1900 } else if (me
== 31 && rsh
+ len
<= 32) {
1901 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
1904 #if defined(TARGET_PPC64)
1908 mask
= MASK(mb
, me
);
1910 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1911 } else if (mask
<= 0xffffffffu
) {
1912 TCGv_i32 t0
= tcg_temp_new_i32();
1913 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1914 tcg_gen_rotli_i32(t0
, t0
, sh
);
1915 tcg_gen_andi_i32(t0
, t0
, mask
);
1916 tcg_gen_extu_i32_tl(t_ra
, t0
);
1917 tcg_temp_free_i32(t0
);
1919 #if defined(TARGET_PPC64)
1920 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1921 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1922 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1924 g_assert_not_reached();
1928 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1929 gen_set_Rc0(ctx
, t_ra
);
1933 /* rlwnm & rlwnm. */
1934 static void gen_rlwnm(DisasContext
*ctx
)
1936 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1937 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1938 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1939 uint32_t mb
= MB(ctx
->opcode
);
1940 uint32_t me
= ME(ctx
->opcode
);
1943 #if defined(TARGET_PPC64)
1947 mask
= MASK(mb
, me
);
1949 if (mask
<= 0xffffffffu
) {
1950 TCGv_i32 t0
= tcg_temp_new_i32();
1951 TCGv_i32 t1
= tcg_temp_new_i32();
1952 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1953 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1954 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1955 tcg_gen_rotl_i32(t1
, t1
, t0
);
1956 tcg_gen_extu_i32_tl(t_ra
, t1
);
1957 tcg_temp_free_i32(t0
);
1958 tcg_temp_free_i32(t1
);
1960 #if defined(TARGET_PPC64)
1961 TCGv_i64 t0
= tcg_temp_new_i64();
1962 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1963 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1964 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1965 tcg_temp_free_i64(t0
);
1967 g_assert_not_reached();
1971 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1973 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1974 gen_set_Rc0(ctx
, t_ra
);
1978 #if defined(TARGET_PPC64)
1979 #define GEN_PPC64_R2(name, opc1, opc2) \
1980 static void glue(gen_, name##0)(DisasContext *ctx) \
1982 gen_##name(ctx, 0); \
1985 static void glue(gen_, name##1)(DisasContext *ctx) \
1987 gen_##name(ctx, 1); \
1989 #define GEN_PPC64_R4(name, opc1, opc2) \
1990 static void glue(gen_, name##0)(DisasContext *ctx) \
1992 gen_##name(ctx, 0, 0); \
1995 static void glue(gen_, name##1)(DisasContext *ctx) \
1997 gen_##name(ctx, 0, 1); \
2000 static void glue(gen_, name##2)(DisasContext *ctx) \
2002 gen_##name(ctx, 1, 0); \
2005 static void glue(gen_, name##3)(DisasContext *ctx) \
2007 gen_##name(ctx, 1, 1); \
2010 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2012 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2013 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2014 int len
= me
- mb
+ 1;
2015 int rsh
= (64 - sh
) & 63;
2017 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2018 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2019 } else if (me
== 63 && rsh
+ len
<= 64) {
2020 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2022 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2023 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2025 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2026 gen_set_Rc0(ctx
, t_ra
);
2030 /* rldicl - rldicl. */
2031 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2035 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2036 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2037 gen_rldinm(ctx
, mb
, 63, sh
);
2039 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2041 /* rldicr - rldicr. */
2042 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2046 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2047 me
= MB(ctx
->opcode
) | (men
<< 5);
2048 gen_rldinm(ctx
, 0, me
, sh
);
2050 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2052 /* rldic - rldic. */
2053 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2057 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2058 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2059 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2061 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2063 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2065 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2066 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2067 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2070 t0
= tcg_temp_new();
2071 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2072 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2075 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2076 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2077 gen_set_Rc0(ctx
, t_ra
);
2081 /* rldcl - rldcl. */
2082 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2086 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2087 gen_rldnm(ctx
, mb
, 63);
2089 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2091 /* rldcr - rldcr. */
2092 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2096 me
= MB(ctx
->opcode
) | (men
<< 5);
2097 gen_rldnm(ctx
, 0, me
);
2099 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2101 /* rldimi - rldimi. */
2102 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2104 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2105 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2106 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2107 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2108 uint32_t me
= 63 - sh
;
2111 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2113 target_ulong mask
= MASK(mb
, me
);
2114 TCGv t1
= tcg_temp_new();
2116 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2117 tcg_gen_andi_tl(t1
, t1
, mask
);
2118 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2119 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2122 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2123 gen_set_Rc0(ctx
, t_ra
);
2126 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2129 /*** Integer shift ***/
2132 static void gen_slw(DisasContext
*ctx
)
2136 t0
= tcg_temp_new();
2137 /* AND rS with a mask that is 0 when rB >= 0x20 */
2138 #if defined(TARGET_PPC64)
2139 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2140 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2142 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2143 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2145 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2146 t1
= tcg_temp_new();
2147 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2148 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2151 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2152 if (unlikely(Rc(ctx
->opcode
) != 0))
2153 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2157 static void gen_sraw(DisasContext
*ctx
)
2159 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2160 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2161 if (unlikely(Rc(ctx
->opcode
) != 0))
2162 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2165 /* srawi & srawi. */
2166 static void gen_srawi(DisasContext
*ctx
)
2168 int sh
= SH(ctx
->opcode
);
2169 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2170 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2172 tcg_gen_ext32s_tl(dst
, src
);
2173 tcg_gen_movi_tl(cpu_ca
, 0);
2174 if (is_isa300(ctx
)) {
2175 tcg_gen_movi_tl(cpu_ca32
, 0);
2179 tcg_gen_ext32s_tl(dst
, src
);
2180 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2181 t0
= tcg_temp_new();
2182 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2183 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2185 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2186 if (is_isa300(ctx
)) {
2187 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2189 tcg_gen_sari_tl(dst
, dst
, sh
);
2191 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2192 gen_set_Rc0(ctx
, dst
);
2197 static void gen_srw(DisasContext
*ctx
)
2201 t0
= tcg_temp_new();
2202 /* AND rS with a mask that is 0 when rB >= 0x20 */
2203 #if defined(TARGET_PPC64)
2204 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2205 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2207 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2208 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2210 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2211 tcg_gen_ext32u_tl(t0
, t0
);
2212 t1
= tcg_temp_new();
2213 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2214 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2217 if (unlikely(Rc(ctx
->opcode
) != 0))
2218 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2221 #if defined(TARGET_PPC64)
2223 static void gen_sld(DisasContext
*ctx
)
2227 t0
= tcg_temp_new();
2228 /* AND rS with a mask that is 0 when rB >= 0x40 */
2229 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2230 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2231 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2232 t1
= tcg_temp_new();
2233 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2234 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2237 if (unlikely(Rc(ctx
->opcode
) != 0))
2238 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2242 static void gen_srad(DisasContext
*ctx
)
2244 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2245 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2246 if (unlikely(Rc(ctx
->opcode
) != 0))
2247 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2249 /* sradi & sradi. */
2250 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2252 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2253 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2254 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2256 tcg_gen_mov_tl(dst
, src
);
2257 tcg_gen_movi_tl(cpu_ca
, 0);
2258 if (is_isa300(ctx
)) {
2259 tcg_gen_movi_tl(cpu_ca32
, 0);
2263 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2264 t0
= tcg_temp_new();
2265 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2266 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2268 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2269 if (is_isa300(ctx
)) {
2270 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2272 tcg_gen_sari_tl(dst
, src
, sh
);
2274 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2275 gen_set_Rc0(ctx
, dst
);
2279 static void gen_sradi0(DisasContext
*ctx
)
2284 static void gen_sradi1(DisasContext
*ctx
)
2289 /* extswsli & extswsli. */
2290 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
2292 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2293 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2294 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2296 tcg_gen_ext32s_tl(dst
, src
);
2297 tcg_gen_shli_tl(dst
, dst
, sh
);
2298 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2299 gen_set_Rc0(ctx
, dst
);
2303 static void gen_extswsli0(DisasContext
*ctx
)
2305 gen_extswsli(ctx
, 0);
2308 static void gen_extswsli1(DisasContext
*ctx
)
2310 gen_extswsli(ctx
, 1);
2314 static void gen_srd(DisasContext
*ctx
)
2318 t0
= tcg_temp_new();
2319 /* AND rS with a mask that is 0 when rB >= 0x40 */
2320 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2321 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2322 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2323 t1
= tcg_temp_new();
2324 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2325 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2328 if (unlikely(Rc(ctx
->opcode
) != 0))
2329 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2333 /*** Addressing modes ***/
2334 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2335 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2338 target_long simm
= SIMM(ctx
->opcode
);
2341 if (rA(ctx
->opcode
) == 0) {
2342 if (NARROW_MODE(ctx
)) {
2343 simm
= (uint32_t)simm
;
2345 tcg_gen_movi_tl(EA
, simm
);
2346 } else if (likely(simm
!= 0)) {
2347 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2348 if (NARROW_MODE(ctx
)) {
2349 tcg_gen_ext32u_tl(EA
, EA
);
2352 if (NARROW_MODE(ctx
)) {
2353 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2355 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2360 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2362 if (rA(ctx
->opcode
) == 0) {
2363 if (NARROW_MODE(ctx
)) {
2364 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2366 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2369 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2370 if (NARROW_MODE(ctx
)) {
2371 tcg_gen_ext32u_tl(EA
, EA
);
2376 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2378 if (rA(ctx
->opcode
) == 0) {
2379 tcg_gen_movi_tl(EA
, 0);
2380 } else if (NARROW_MODE(ctx
)) {
2381 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2383 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2387 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2390 tcg_gen_addi_tl(ret
, arg1
, val
);
2391 if (NARROW_MODE(ctx
)) {
2392 tcg_gen_ext32u_tl(ret
, ret
);
2396 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2398 TCGLabel
*l1
= gen_new_label();
2399 TCGv t0
= tcg_temp_new();
2401 tcg_gen_andi_tl(t0
, EA
, mask
);
2402 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2403 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2404 t2
= tcg_const_i32(ctx
->opcode
& 0x03FF0000);
2405 gen_update_nip(ctx
, ctx
->nip
- 4);
2406 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2407 tcg_temp_free_i32(t1
);
2408 tcg_temp_free_i32(t2
);
2413 static inline void gen_align_no_le(DisasContext
*ctx
)
2415 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
2416 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
2419 /*** Integer load ***/
2420 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2421 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2423 #define GEN_QEMU_LOAD_TL(ldop, op) \
2424 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2428 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2431 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
2432 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
2433 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
2434 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
2435 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
2437 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
2438 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
2440 #define GEN_QEMU_LOAD_64(ldop, op) \
2441 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2445 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2448 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
2449 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
2450 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
2451 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
2452 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
2454 #if defined(TARGET_PPC64)
2455 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
2458 #define GEN_QEMU_STORE_TL(stop, op) \
2459 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2463 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2466 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
2467 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
2468 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
2470 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
2471 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
2473 #define GEN_QEMU_STORE_64(stop, op) \
2474 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2478 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2481 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
2482 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
2483 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
2484 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
2486 #if defined(TARGET_PPC64)
2487 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
2490 #define GEN_LD(name, ldop, opc, type) \
2491 static void glue(gen_, name)(DisasContext *ctx) \
2494 gen_set_access_type(ctx, ACCESS_INT); \
2495 EA = tcg_temp_new(); \
2496 gen_addr_imm_index(ctx, EA, 0); \
2497 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2498 tcg_temp_free(EA); \
2501 #define GEN_LDU(name, ldop, opc, type) \
2502 static void glue(gen_, name##u)(DisasContext *ctx) \
2505 if (unlikely(rA(ctx->opcode) == 0 || \
2506 rA(ctx->opcode) == rD(ctx->opcode))) { \
2507 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2510 gen_set_access_type(ctx, ACCESS_INT); \
2511 EA = tcg_temp_new(); \
2512 if (type == PPC_64B) \
2513 gen_addr_imm_index(ctx, EA, 0x03); \
2515 gen_addr_imm_index(ctx, EA, 0); \
2516 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2517 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2518 tcg_temp_free(EA); \
2521 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2522 static void glue(gen_, name##ux)(DisasContext *ctx) \
2525 if (unlikely(rA(ctx->opcode) == 0 || \
2526 rA(ctx->opcode) == rD(ctx->opcode))) { \
2527 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2530 gen_set_access_type(ctx, ACCESS_INT); \
2531 EA = tcg_temp_new(); \
2532 gen_addr_reg_index(ctx, EA); \
2533 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2534 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2535 tcg_temp_free(EA); \
2538 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2539 static void glue(gen_, name##x)(DisasContext *ctx) \
2543 gen_set_access_type(ctx, ACCESS_INT); \
2544 EA = tcg_temp_new(); \
2545 gen_addr_reg_index(ctx, EA); \
2546 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2547 tcg_temp_free(EA); \
2550 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2551 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2553 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2554 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2556 #define GEN_LDS(name, ldop, op, type) \
2557 GEN_LD(name, ldop, op | 0x20, type); \
2558 GEN_LDU(name, ldop, op | 0x21, type); \
2559 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2560 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2562 /* lbz lbzu lbzux lbzx */
2563 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2564 /* lha lhau lhaux lhax */
2565 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2566 /* lhz lhzu lhzux lhzx */
2567 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2568 /* lwz lwzu lwzux lwzx */
2569 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2570 #if defined(TARGET_PPC64)
2572 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2574 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2576 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
);
2578 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
);
2580 /* CI load/store variants */
2581 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
2582 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2583 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2584 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2586 static void gen_ld(DisasContext
*ctx
)
2589 if (Rc(ctx
->opcode
)) {
2590 if (unlikely(rA(ctx
->opcode
) == 0 ||
2591 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2592 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2596 gen_set_access_type(ctx
, ACCESS_INT
);
2597 EA
= tcg_temp_new();
2598 gen_addr_imm_index(ctx
, EA
, 0x03);
2599 if (ctx
->opcode
& 0x02) {
2600 /* lwa (lwau is undefined) */
2601 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2604 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2606 if (Rc(ctx
->opcode
))
2607 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2612 static void gen_lq(DisasContext
*ctx
)
2617 /* lq is a legal user mode instruction starting in ISA 2.07 */
2618 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2619 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2621 if (!legal_in_user_mode
&& ctx
->pr
) {
2622 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2626 if (!le_is_supported
&& ctx
->le_mode
) {
2627 gen_align_no_le(ctx
);
2630 ra
= rA(ctx
->opcode
);
2631 rd
= rD(ctx
->opcode
);
2632 if (unlikely((rd
& 1) || rd
== ra
)) {
2633 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2637 gen_set_access_type(ctx
, ACCESS_INT
);
2638 EA
= tcg_temp_new();
2639 gen_addr_imm_index(ctx
, EA
, 0x0F);
2641 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2642 necessary 64-bit byteswap already. */
2643 if (unlikely(ctx
->le_mode
)) {
2644 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
+ 1], EA
);
2645 gen_addr_add(ctx
, EA
, EA
, 8);
2646 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
], EA
);
2648 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
], EA
);
2649 gen_addr_add(ctx
, EA
, EA
, 8);
2650 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
+ 1], EA
);
2656 /*** Integer store ***/
2657 #define GEN_ST(name, stop, opc, type) \
2658 static void glue(gen_, name)(DisasContext *ctx) \
2661 gen_set_access_type(ctx, ACCESS_INT); \
2662 EA = tcg_temp_new(); \
2663 gen_addr_imm_index(ctx, EA, 0); \
2664 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2665 tcg_temp_free(EA); \
2668 #define GEN_STU(name, stop, opc, type) \
2669 static void glue(gen_, stop##u)(DisasContext *ctx) \
2672 if (unlikely(rA(ctx->opcode) == 0)) { \
2673 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2676 gen_set_access_type(ctx, ACCESS_INT); \
2677 EA = tcg_temp_new(); \
2678 if (type == PPC_64B) \
2679 gen_addr_imm_index(ctx, EA, 0x03); \
2681 gen_addr_imm_index(ctx, EA, 0); \
2682 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2684 tcg_temp_free(EA); \
2687 #define GEN_STUX(name, stop, opc2, opc3, type) \
2688 static void glue(gen_, name##ux)(DisasContext *ctx) \
2691 if (unlikely(rA(ctx->opcode) == 0)) { \
2692 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2695 gen_set_access_type(ctx, ACCESS_INT); \
2696 EA = tcg_temp_new(); \
2697 gen_addr_reg_index(ctx, EA); \
2698 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2699 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2700 tcg_temp_free(EA); \
2703 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2704 static void glue(gen_, name##x)(DisasContext *ctx) \
2708 gen_set_access_type(ctx, ACCESS_INT); \
2709 EA = tcg_temp_new(); \
2710 gen_addr_reg_index(ctx, EA); \
2711 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2712 tcg_temp_free(EA); \
2714 #define GEN_STX(name, stop, opc2, opc3, type) \
2715 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2717 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2718 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2720 #define GEN_STS(name, stop, op, type) \
2721 GEN_ST(name, stop, op | 0x20, type); \
2722 GEN_STU(name, stop, op | 0x21, type); \
2723 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2724 GEN_STX(name, stop, 0x17, op | 0x00, type)
2726 /* stb stbu stbux stbx */
2727 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2728 /* sth sthu sthux sthx */
2729 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2730 /* stw stwu stwux stwx */
2731 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2732 #if defined(TARGET_PPC64)
2733 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
);
2734 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
);
2735 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
2736 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2737 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2738 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2740 static void gen_std(DisasContext
*ctx
)
2745 rs
= rS(ctx
->opcode
);
2746 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2747 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2748 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2750 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2751 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2754 if (!legal_in_user_mode
&& ctx
->pr
) {
2755 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2759 if (!le_is_supported
&& ctx
->le_mode
) {
2760 gen_align_no_le(ctx
);
2764 if (unlikely(rs
& 1)) {
2765 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2768 gen_set_access_type(ctx
, ACCESS_INT
);
2769 EA
= tcg_temp_new();
2770 gen_addr_imm_index(ctx
, EA
, 0x03);
2772 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2773 necessary 64-bit byteswap already. */
2774 if (unlikely(ctx
->le_mode
)) {
2775 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
+ 1], EA
);
2776 gen_addr_add(ctx
, EA
, EA
, 8);
2777 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2779 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2780 gen_addr_add(ctx
, EA
, EA
, 8);
2781 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
+ 1], EA
);
2786 if (Rc(ctx
->opcode
)) {
2787 if (unlikely(rA(ctx
->opcode
) == 0)) {
2788 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2792 gen_set_access_type(ctx
, ACCESS_INT
);
2793 EA
= tcg_temp_new();
2794 gen_addr_imm_index(ctx
, EA
, 0x03);
2795 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2796 if (Rc(ctx
->opcode
))
2797 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2802 /*** Integer load and store with byte reverse ***/
2805 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2808 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2810 #if defined(TARGET_PPC64)
2812 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2814 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2815 #endif /* TARGET_PPC64 */
2818 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2820 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2822 /*** Integer load and store multiple ***/
2825 static void gen_lmw(DisasContext
*ctx
)
2831 gen_align_no_le(ctx
);
2834 gen_set_access_type(ctx
, ACCESS_INT
);
2835 t0
= tcg_temp_new();
2836 t1
= tcg_const_i32(rD(ctx
->opcode
));
2837 gen_addr_imm_index(ctx
, t0
, 0);
2838 gen_helper_lmw(cpu_env
, t0
, t1
);
2840 tcg_temp_free_i32(t1
);
2844 static void gen_stmw(DisasContext
*ctx
)
2850 gen_align_no_le(ctx
);
2853 gen_set_access_type(ctx
, ACCESS_INT
);
2854 t0
= tcg_temp_new();
2855 t1
= tcg_const_i32(rS(ctx
->opcode
));
2856 gen_addr_imm_index(ctx
, t0
, 0);
2857 gen_helper_stmw(cpu_env
, t0
, t1
);
2859 tcg_temp_free_i32(t1
);
2862 /*** Integer load and store strings ***/
2865 /* PowerPC32 specification says we must generate an exception if
2866 * rA is in the range of registers to be loaded.
2867 * In an other hand, IBM says this is valid, but rA won't be loaded.
2868 * For now, I'll follow the spec...
2870 static void gen_lswi(DisasContext
*ctx
)
2874 int nb
= NB(ctx
->opcode
);
2875 int start
= rD(ctx
->opcode
);
2876 int ra
= rA(ctx
->opcode
);
2880 gen_align_no_le(ctx
);
2885 nr
= DIV_ROUND_UP(nb
, 4);
2886 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2887 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2890 gen_set_access_type(ctx
, ACCESS_INT
);
2891 t0
= tcg_temp_new();
2892 gen_addr_register(ctx
, t0
);
2893 t1
= tcg_const_i32(nb
);
2894 t2
= tcg_const_i32(start
);
2895 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2897 tcg_temp_free_i32(t1
);
2898 tcg_temp_free_i32(t2
);
2902 static void gen_lswx(DisasContext
*ctx
)
2905 TCGv_i32 t1
, t2
, t3
;
2908 gen_align_no_le(ctx
);
2911 gen_set_access_type(ctx
, ACCESS_INT
);
2912 t0
= tcg_temp_new();
2913 gen_addr_reg_index(ctx
, t0
);
2914 t1
= tcg_const_i32(rD(ctx
->opcode
));
2915 t2
= tcg_const_i32(rA(ctx
->opcode
));
2916 t3
= tcg_const_i32(rB(ctx
->opcode
));
2917 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2919 tcg_temp_free_i32(t1
);
2920 tcg_temp_free_i32(t2
);
2921 tcg_temp_free_i32(t3
);
2925 static void gen_stswi(DisasContext
*ctx
)
2929 int nb
= NB(ctx
->opcode
);
2932 gen_align_no_le(ctx
);
2935 gen_set_access_type(ctx
, ACCESS_INT
);
2936 t0
= tcg_temp_new();
2937 gen_addr_register(ctx
, t0
);
2940 t1
= tcg_const_i32(nb
);
2941 t2
= tcg_const_i32(rS(ctx
->opcode
));
2942 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2944 tcg_temp_free_i32(t1
);
2945 tcg_temp_free_i32(t2
);
2949 static void gen_stswx(DisasContext
*ctx
)
2955 gen_align_no_le(ctx
);
2958 gen_set_access_type(ctx
, ACCESS_INT
);
2959 t0
= tcg_temp_new();
2960 gen_addr_reg_index(ctx
, t0
);
2961 t1
= tcg_temp_new_i32();
2962 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
2963 tcg_gen_andi_i32(t1
, t1
, 0x7F);
2964 t2
= tcg_const_i32(rS(ctx
->opcode
));
2965 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2967 tcg_temp_free_i32(t1
);
2968 tcg_temp_free_i32(t2
);
2971 /*** Memory synchronisation ***/
2973 static void gen_eieio(DisasContext
*ctx
)
2975 tcg_gen_mb(TCG_MO_LD_ST
| TCG_BAR_SC
);
2978 #if !defined(CONFIG_USER_ONLY)
2979 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
2984 if (!ctx
->lazy_tlb_flush
) {
2987 l
= gen_new_label();
2988 t
= tcg_temp_new_i32();
2989 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
2990 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
2992 gen_helper_check_tlb_flush_global(cpu_env
);
2994 gen_helper_check_tlb_flush_local(cpu_env
);
2997 tcg_temp_free_i32(t
);
3000 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3004 static void gen_isync(DisasContext
*ctx
)
3007 * We need to check for a pending TLB flush. This can only happen in
3008 * kernel mode however so check MSR_PR
3011 gen_check_tlb_flush(ctx
, false);
3013 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3014 gen_stop_exception(ctx
);
3017 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3019 #define LARX(name, memop) \
3020 static void gen_##name(DisasContext *ctx) \
3023 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3024 int len = MEMOP_GET_SIZE(memop); \
3025 gen_set_access_type(ctx, ACCESS_RES); \
3026 t0 = tcg_temp_local_new(); \
3027 gen_addr_reg_index(ctx, t0); \
3029 gen_check_align(ctx, t0, (len)-1); \
3031 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3032 tcg_gen_mov_tl(cpu_reserve, t0); \
3033 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3034 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
3035 tcg_temp_free(t0); \
3039 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3040 LARX(lharx
, DEF_MEMOP(MO_UW
))
3041 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3043 #define LD_ATOMIC(name, memop, tp, op, eop) \
3044 static void gen_##name(DisasContext *ctx) \
3046 int len = MEMOP_GET_SIZE(memop); \
3047 uint32_t gpr_FC = FC(ctx->opcode); \
3048 TCGv EA = tcg_temp_local_new(); \
3051 gen_addr_register(ctx, EA); \
3053 gen_check_align(ctx, EA, len - 1); \
3055 t0 = tcg_temp_new_##tp(); \
3056 t1 = tcg_temp_new_##tp(); \
3057 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3060 case 0: /* Fetch and add */ \
3061 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3063 case 1: /* Fetch and xor */ \
3064 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3066 case 2: /* Fetch and or */ \
3067 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3069 case 3: /* Fetch and 'and' */ \
3070 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3072 case 8: /* Swap */ \
3073 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3075 case 4: /* Fetch and max unsigned */ \
3076 case 5: /* Fetch and max signed */ \
3077 case 6: /* Fetch and min unsigned */ \
3078 case 7: /* Fetch and min signed */ \
3079 case 16: /* compare and swap not equal */ \
3080 case 24: /* Fetch and increment bounded */ \
3081 case 25: /* Fetch and increment equal */ \
3082 case 28: /* Fetch and decrement bounded */ \
3086 /* invoke data storage error handler */ \
3087 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3089 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3090 tcg_temp_free_##tp(t0); \
3091 tcg_temp_free_##tp(t1); \
3092 tcg_temp_free(EA); \
3095 LD_ATOMIC(lwat
, DEF_MEMOP(MO_UL
), i32
, trunc_tl_i32
, extu_i32_tl
)
3096 #if defined(TARGET_PPC64)
3097 LD_ATOMIC(ldat
, DEF_MEMOP(MO_Q
), i64
, mov_i64
, mov_i64
)
3100 #define ST_ATOMIC(name, memop, tp, op) \
3101 static void gen_##name(DisasContext *ctx) \
3103 int len = MEMOP_GET_SIZE(memop); \
3104 uint32_t gpr_FC = FC(ctx->opcode); \
3105 TCGv EA = tcg_temp_local_new(); \
3108 gen_addr_register(ctx, EA); \
3110 gen_check_align(ctx, EA, len - 1); \
3112 t0 = tcg_temp_new_##tp(); \
3113 t1 = tcg_temp_new_##tp(); \
3114 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3117 case 0: /* add and Store */ \
3118 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3120 case 1: /* xor and Store */ \
3121 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3123 case 2: /* Or and Store */ \
3124 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3126 case 3: /* 'and' and Store */ \
3127 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3129 case 4: /* Store max unsigned */ \
3130 case 5: /* Store max signed */ \
3131 case 6: /* Store min unsigned */ \
3132 case 7: /* Store min signed */ \
3133 case 24: /* Store twin */ \
3137 /* invoke data storage error handler */ \
3138 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3140 tcg_temp_free_##tp(t0); \
3141 tcg_temp_free_##tp(t1); \
3142 tcg_temp_free(EA); \
3145 ST_ATOMIC(stwat
, DEF_MEMOP(MO_UL
), i32
, trunc_tl_i32
)
3146 #if defined(TARGET_PPC64)
3147 ST_ATOMIC(stdat
, DEF_MEMOP(MO_Q
), i64
, mov_i64
)
3150 #if defined(CONFIG_USER_ONLY)
3151 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3154 TCGv t0
= tcg_temp_new();
3156 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3157 tcg_gen_movi_tl(t0
, (MEMOP_GET_SIZE(memop
) << 5) | reg
);
3158 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3160 gen_exception_err(ctx
, POWERPC_EXCP_STCX
, 0);
3163 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3166 TCGLabel
*l1
= gen_new_label();
3167 TCGLabel
*l2
= gen_new_label();
3170 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3172 t0
= tcg_temp_new();
3173 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
3174 cpu_gpr
[reg
], ctx
->mem_idx
,
3175 DEF_MEMOP(memop
) | MO_ALIGN
);
3176 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
3177 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
3178 tcg_gen_or_tl(t0
, t0
, cpu_so
);
3179 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
3185 /* Address mismatch implies failure. But we still need to provide the
3186 memory barrier semantics of the instruction. */
3187 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3188 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3191 tcg_gen_movi_tl(cpu_reserve
, -1);
3195 #define STCX(name, memop) \
3196 static void gen_##name(DisasContext *ctx) \
3199 int len = MEMOP_GET_SIZE(memop); \
3200 gen_set_access_type(ctx, ACCESS_RES); \
3201 t0 = tcg_temp_local_new(); \
3202 gen_addr_reg_index(ctx, t0); \
3204 gen_check_align(ctx, t0, (len) - 1); \
3206 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3207 tcg_temp_free(t0); \
3210 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
3211 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
3212 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
3214 #if defined(TARGET_PPC64)
3216 LARX(ldarx
, DEF_MEMOP(MO_Q
))
3218 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
3221 static void gen_lqarx(DisasContext
*ctx
)
3224 int rd
= rD(ctx
->opcode
);
3227 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3228 (rd
== rB(ctx
->opcode
)))) {
3229 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3233 gen_set_access_type(ctx
, ACCESS_RES
);
3234 EA
= tcg_temp_local_new();
3235 gen_addr_reg_index(ctx
, EA
);
3236 gen_check_align(ctx
, EA
, 15);
3237 if (unlikely(ctx
->le_mode
)) {
3238 gpr1
= cpu_gpr
[rd
+1];
3242 gpr2
= cpu_gpr
[rd
+1];
3244 tcg_gen_qemu_ld_i64(gpr1
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3245 tcg_gen_mov_tl(cpu_reserve
, EA
);
3246 gen_addr_add(ctx
, EA
, EA
, 8);
3247 tcg_gen_qemu_ld_i64(gpr2
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3249 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3250 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3255 static void gen_stqcx_(DisasContext
*ctx
)
3258 int reg
= rS(ctx
->opcode
);
3260 #if !defined(CONFIG_USER_ONLY)
3265 if (unlikely((rD(ctx
->opcode
) & 1))) {
3266 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3269 gen_set_access_type(ctx
, ACCESS_RES
);
3270 EA
= tcg_temp_local_new();
3271 gen_addr_reg_index(ctx
, EA
);
3273 gen_check_align(ctx
, EA
, (len
) - 1);
3276 #if defined(CONFIG_USER_ONLY)
3277 gen_conditional_store(ctx
, EA
, reg
, 16);
3279 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3280 l1
= gen_new_label();
3281 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3282 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
3284 if (unlikely(ctx
->le_mode
)) {
3285 gpr1
= cpu_gpr
[reg
+ 1];
3286 gpr2
= cpu_gpr
[reg
];
3288 gpr1
= cpu_gpr
[reg
];
3289 gpr2
= cpu_gpr
[reg
+ 1];
3291 tcg_gen_qemu_st_tl(gpr1
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3292 gen_addr_add(ctx
, EA
, EA
, 8);
3293 tcg_gen_qemu_st_tl(gpr2
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3296 tcg_gen_movi_tl(cpu_reserve
, -1);
3301 #endif /* defined(TARGET_PPC64) */
3304 static void gen_sync(DisasContext
*ctx
)
3306 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3309 * We may need to check for a pending TLB flush.
3311 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3313 * Additionally, this can only happen in kernel mode however so
3314 * check MSR_PR as well.
3316 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3317 gen_check_tlb_flush(ctx
, true);
3319 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3323 static void gen_wait(DisasContext
*ctx
)
3325 TCGv_i32 t0
= tcg_const_i32(1);
3326 tcg_gen_st_i32(t0
, cpu_env
,
3327 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3328 tcg_temp_free_i32(t0
);
3329 /* Stop translation, as the CPU is supposed to sleep from now */
3330 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->nip
);
3333 #if defined(TARGET_PPC64)
3334 static void gen_doze(DisasContext
*ctx
)
3336 #if defined(CONFIG_USER_ONLY)
3342 t
= tcg_const_i32(PPC_PM_DOZE
);
3343 gen_helper_pminsn(cpu_env
, t
);
3344 tcg_temp_free_i32(t
);
3345 gen_stop_exception(ctx
);
3346 #endif /* defined(CONFIG_USER_ONLY) */
3349 static void gen_nap(DisasContext
*ctx
)
3351 #if defined(CONFIG_USER_ONLY)
3357 t
= tcg_const_i32(PPC_PM_NAP
);
3358 gen_helper_pminsn(cpu_env
, t
);
3359 tcg_temp_free_i32(t
);
3360 gen_stop_exception(ctx
);
3361 #endif /* defined(CONFIG_USER_ONLY) */
3364 static void gen_stop(DisasContext
*ctx
)
3369 static void gen_sleep(DisasContext
*ctx
)
3371 #if defined(CONFIG_USER_ONLY)
3377 t
= tcg_const_i32(PPC_PM_SLEEP
);
3378 gen_helper_pminsn(cpu_env
, t
);
3379 tcg_temp_free_i32(t
);
3380 gen_stop_exception(ctx
);
3381 #endif /* defined(CONFIG_USER_ONLY) */
3384 static void gen_rvwinkle(DisasContext
*ctx
)
3386 #if defined(CONFIG_USER_ONLY)
3392 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3393 gen_helper_pminsn(cpu_env
, t
);
3394 tcg_temp_free_i32(t
);
3395 gen_stop_exception(ctx
);
3396 #endif /* defined(CONFIG_USER_ONLY) */
3398 #endif /* #if defined(TARGET_PPC64) */
3400 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3402 #if defined(TARGET_PPC64)
3404 tcg_gen_movi_tl(cpu_cfar
, nip
);
3408 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3410 if (unlikely(ctx
->singlestep_enabled
)) {
3414 #ifndef CONFIG_USER_ONLY
3415 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3422 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3424 if (NARROW_MODE(ctx
)) {
3425 dest
= (uint32_t) dest
;
3427 if (use_goto_tb(ctx
, dest
)) {
3429 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3430 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3432 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3433 if (unlikely(ctx
->singlestep_enabled
)) {
3434 if ((ctx
->singlestep_enabled
&
3435 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3436 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3437 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3438 gen_exception_nip(ctx
, POWERPC_EXCP_TRACE
, dest
);
3440 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3441 gen_debug_exception(ctx
);
3448 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3450 if (NARROW_MODE(ctx
)) {
3451 nip
= (uint32_t)nip
;
3453 tcg_gen_movi_tl(cpu_lr
, nip
);
3457 static void gen_b(DisasContext
*ctx
)
3459 target_ulong li
, target
;
3461 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3462 /* sign extend LI */
3463 li
= LI(ctx
->opcode
);
3464 li
= (li
^ 0x02000000) - 0x02000000;
3465 if (likely(AA(ctx
->opcode
) == 0)) {
3466 target
= ctx
->nip
+ li
- 4;
3470 if (LK(ctx
->opcode
)) {
3471 gen_setlr(ctx
, ctx
->nip
);
3473 gen_update_cfar(ctx
, ctx
->nip
- 4);
3474 gen_goto_tb(ctx
, 0, target
);
3482 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3484 uint32_t bo
= BO(ctx
->opcode
);
3488 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3489 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3490 target
= tcg_temp_local_new();
3491 if (type
== BCOND_CTR
)
3492 tcg_gen_mov_tl(target
, cpu_ctr
);
3493 else if (type
== BCOND_TAR
)
3494 gen_load_spr(target
, SPR_TAR
);
3496 tcg_gen_mov_tl(target
, cpu_lr
);
3498 TCGV_UNUSED(target
);
3500 if (LK(ctx
->opcode
))
3501 gen_setlr(ctx
, ctx
->nip
);
3502 l1
= gen_new_label();
3503 if ((bo
& 0x4) == 0) {
3504 /* Decrement and test CTR */
3505 TCGv temp
= tcg_temp_new();
3506 if (unlikely(type
== BCOND_CTR
)) {
3507 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3510 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3511 if (NARROW_MODE(ctx
)) {
3512 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3514 tcg_gen_mov_tl(temp
, cpu_ctr
);
3517 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3519 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3521 tcg_temp_free(temp
);
3523 if ((bo
& 0x10) == 0) {
3525 uint32_t bi
= BI(ctx
->opcode
);
3526 uint32_t mask
= 0x08 >> (bi
& 0x03);
3527 TCGv_i32 temp
= tcg_temp_new_i32();
3530 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3531 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3533 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3534 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3536 tcg_temp_free_i32(temp
);
3538 gen_update_cfar(ctx
, ctx
->nip
- 4);
3539 if (type
== BCOND_IM
) {
3540 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3541 if (likely(AA(ctx
->opcode
) == 0)) {
3542 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3544 gen_goto_tb(ctx
, 0, li
);
3546 if ((bo
& 0x14) != 0x14) {
3548 gen_goto_tb(ctx
, 1, ctx
->nip
);
3551 if (NARROW_MODE(ctx
)) {
3552 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3554 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3557 if ((bo
& 0x14) != 0x14) {
3559 gen_update_nip(ctx
, ctx
->nip
);
3563 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3564 tcg_temp_free(target
);
3568 static void gen_bc(DisasContext
*ctx
)
3570 gen_bcond(ctx
, BCOND_IM
);
3573 static void gen_bcctr(DisasContext
*ctx
)
3575 gen_bcond(ctx
, BCOND_CTR
);
3578 static void gen_bclr(DisasContext
*ctx
)
3580 gen_bcond(ctx
, BCOND_LR
);
3583 static void gen_bctar(DisasContext
*ctx
)
3585 gen_bcond(ctx
, BCOND_TAR
);
3588 /*** Condition register logical ***/
3589 #define GEN_CRLOGIC(name, tcg_op, opc) \
3590 static void glue(gen_, name)(DisasContext *ctx) \
3595 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3596 t0 = tcg_temp_new_i32(); \
3598 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3600 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3602 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3603 t1 = tcg_temp_new_i32(); \
3604 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3606 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3608 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3610 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3611 tcg_op(t0, t0, t1); \
3612 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3613 tcg_gen_andi_i32(t0, t0, bitmask); \
3614 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3615 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3616 tcg_temp_free_i32(t0); \
3617 tcg_temp_free_i32(t1); \
3621 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3623 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3625 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3627 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3629 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3631 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3633 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3635 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3638 static void gen_mcrf(DisasContext
*ctx
)
3640 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3643 /*** System linkage ***/
3645 /* rfi (supervisor only) */
3646 static void gen_rfi(DisasContext
*ctx
)
3648 #if defined(CONFIG_USER_ONLY)
3651 /* This instruction doesn't exist anymore on 64-bit server
3652 * processors compliant with arch 2.x
3654 if (ctx
->insns_flags
& PPC_SEGMENT_64B
) {
3655 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3658 /* Restore CPU state */
3660 gen_update_cfar(ctx
, ctx
->nip
- 4);
3661 gen_helper_rfi(cpu_env
);
3662 gen_sync_exception(ctx
);
3666 #if defined(TARGET_PPC64)
3667 static void gen_rfid(DisasContext
*ctx
)
3669 #if defined(CONFIG_USER_ONLY)
3672 /* Restore CPU state */
3674 gen_update_cfar(ctx
, ctx
->nip
- 4);
3675 gen_helper_rfid(cpu_env
);
3676 gen_sync_exception(ctx
);
3680 static void gen_hrfid(DisasContext
*ctx
)
3682 #if defined(CONFIG_USER_ONLY)
3685 /* Restore CPU state */
3687 gen_helper_hrfid(cpu_env
);
3688 gen_sync_exception(ctx
);
3694 #if defined(CONFIG_USER_ONLY)
3695 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3697 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3699 static void gen_sc(DisasContext
*ctx
)
3703 lev
= (ctx
->opcode
>> 5) & 0x7F;
3704 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3709 /* Check for unconditional traps (always or never) */
3710 static bool check_unconditional_trap(DisasContext
*ctx
)
3713 if (TO(ctx
->opcode
) == 0) {
3717 if (TO(ctx
->opcode
) == 31) {
3718 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
3725 static void gen_tw(DisasContext
*ctx
)
3729 if (check_unconditional_trap(ctx
)) {
3732 t0
= tcg_const_i32(TO(ctx
->opcode
));
3733 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3735 tcg_temp_free_i32(t0
);
3739 static void gen_twi(DisasContext
*ctx
)
3744 if (check_unconditional_trap(ctx
)) {
3747 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3748 t1
= tcg_const_i32(TO(ctx
->opcode
));
3749 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3751 tcg_temp_free_i32(t1
);
3754 #if defined(TARGET_PPC64)
3756 static void gen_td(DisasContext
*ctx
)
3760 if (check_unconditional_trap(ctx
)) {
3763 t0
= tcg_const_i32(TO(ctx
->opcode
));
3764 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3766 tcg_temp_free_i32(t0
);
3770 static void gen_tdi(DisasContext
*ctx
)
3775 if (check_unconditional_trap(ctx
)) {
3778 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3779 t1
= tcg_const_i32(TO(ctx
->opcode
));
3780 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3782 tcg_temp_free_i32(t1
);
3786 /*** Processor control ***/
3788 static void gen_read_xer(DisasContext
*ctx
, TCGv dst
)
3790 TCGv t0
= tcg_temp_new();
3791 TCGv t1
= tcg_temp_new();
3792 TCGv t2
= tcg_temp_new();
3793 tcg_gen_mov_tl(dst
, cpu_xer
);
3794 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3795 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3796 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3797 tcg_gen_or_tl(t0
, t0
, t1
);
3798 tcg_gen_or_tl(dst
, dst
, t2
);
3799 tcg_gen_or_tl(dst
, dst
, t0
);
3800 if (is_isa300(ctx
)) {
3801 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
3802 tcg_gen_or_tl(dst
, dst
, t0
);
3803 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
3804 tcg_gen_or_tl(dst
, dst
, t0
);
3811 static void gen_write_xer(TCGv src
)
3813 /* Write all flags, while reading back check for isa300 */
3814 tcg_gen_andi_tl(cpu_xer
, src
,
3816 (1u << XER_OV
) | (1u << XER_OV32
) |
3817 (1u << XER_CA
) | (1u << XER_CA32
)));
3818 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
3819 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
3820 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
3821 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
3822 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
3826 static void gen_mcrxr(DisasContext
*ctx
)
3828 TCGv_i32 t0
= tcg_temp_new_i32();
3829 TCGv_i32 t1
= tcg_temp_new_i32();
3830 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3832 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3833 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3834 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3835 tcg_gen_shli_i32(t0
, t0
, 3);
3836 tcg_gen_shli_i32(t1
, t1
, 2);
3837 tcg_gen_shli_i32(dst
, dst
, 1);
3838 tcg_gen_or_i32(dst
, dst
, t0
);
3839 tcg_gen_or_i32(dst
, dst
, t1
);
3840 tcg_temp_free_i32(t0
);
3841 tcg_temp_free_i32(t1
);
3843 tcg_gen_movi_tl(cpu_so
, 0);
3844 tcg_gen_movi_tl(cpu_ov
, 0);
3845 tcg_gen_movi_tl(cpu_ca
, 0);
3850 static void gen_mcrxrx(DisasContext
*ctx
)
3852 TCGv t0
= tcg_temp_new();
3853 TCGv t1
= tcg_temp_new();
3854 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3856 /* copy OV and OV32 */
3857 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
3858 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
3859 tcg_gen_shli_tl(t0
, t0
, 2);
3860 /* copy CA and CA32 */
3861 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
3862 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
3863 tcg_gen_or_tl(t0
, t0
, t1
);
3864 tcg_gen_trunc_tl_i32(dst
, t0
);
3871 static void gen_mfcr(DisasContext
*ctx
)
3875 if (likely(ctx
->opcode
& 0x00100000)) {
3876 crm
= CRM(ctx
->opcode
);
3877 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3879 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3880 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3881 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3884 TCGv_i32 t0
= tcg_temp_new_i32();
3885 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3886 tcg_gen_shli_i32(t0
, t0
, 4);
3887 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3888 tcg_gen_shli_i32(t0
, t0
, 4);
3889 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3890 tcg_gen_shli_i32(t0
, t0
, 4);
3891 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3892 tcg_gen_shli_i32(t0
, t0
, 4);
3893 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3894 tcg_gen_shli_i32(t0
, t0
, 4);
3895 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3896 tcg_gen_shli_i32(t0
, t0
, 4);
3897 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3898 tcg_gen_shli_i32(t0
, t0
, 4);
3899 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3900 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3901 tcg_temp_free_i32(t0
);
3906 static void gen_mfmsr(DisasContext
*ctx
)
3909 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3912 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
3915 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3916 printf("ERROR: try to access SPR %d !\n", sprn
);
3919 #define SPR_NOACCESS (&spr_noaccess)
3922 static inline void gen_op_mfspr(DisasContext
*ctx
)
3924 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
3925 uint32_t sprn
= SPR(ctx
->opcode
);
3927 #if defined(CONFIG_USER_ONLY)
3928 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3931 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3932 } else if (ctx
->hv
) {
3933 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3935 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3938 if (likely(read_cb
!= NULL
)) {
3939 if (likely(read_cb
!= SPR_NOACCESS
)) {
3940 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3942 /* Privilege exception */
3943 /* This is a hack to avoid warnings when running Linux:
3944 * this OS breaks the PowerPC virtualisation model,
3945 * allowing userland application to read the PVR
3947 if (sprn
!= SPR_PVR
) {
3948 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
3949 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3950 if (qemu_log_separate()) {
3951 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3952 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3955 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3958 /* ISA 2.07 defines these as no-ops */
3959 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
3960 (sprn
>= 808 && sprn
<= 811)) {
3965 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
3966 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3967 if (qemu_log_separate()) {
3968 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3969 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3972 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3973 * it can generate a priv, a hv emu or a no-op
3977 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3980 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
3981 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3987 static void gen_mfspr(DisasContext
*ctx
)
3993 static void gen_mftb(DisasContext
*ctx
)
3999 static void gen_mtcrf(DisasContext
*ctx
)
4003 crm
= CRM(ctx
->opcode
);
4004 if (likely((ctx
->opcode
& 0x00100000))) {
4005 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4006 TCGv_i32 temp
= tcg_temp_new_i32();
4008 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4009 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4010 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4011 tcg_temp_free_i32(temp
);
4014 TCGv_i32 temp
= tcg_temp_new_i32();
4015 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4016 for (crn
= 0 ; crn
< 8 ; crn
++) {
4017 if (crm
& (1 << crn
)) {
4018 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4019 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4022 tcg_temp_free_i32(temp
);
4027 #if defined(TARGET_PPC64)
4028 static void gen_mtmsrd(DisasContext
*ctx
)
4032 #if !defined(CONFIG_USER_ONLY)
4033 if (ctx
->opcode
& 0x00010000) {
4034 /* Special form that does not need any synchronisation */
4035 TCGv t0
= tcg_temp_new();
4036 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4037 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4038 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4041 /* XXX: we need to update nip before the store
4042 * if we enter power saving mode, we will exit the loop
4043 * directly from ppc_store_msr
4045 gen_update_nip(ctx
, ctx
->nip
);
4046 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4047 /* Must stop the translation as machine state (may have) changed */
4048 /* Note that mtmsr is not always defined as context-synchronizing */
4049 gen_stop_exception(ctx
);
4051 #endif /* !defined(CONFIG_USER_ONLY) */
4053 #endif /* defined(TARGET_PPC64) */
4055 static void gen_mtmsr(DisasContext
*ctx
)
4059 #if !defined(CONFIG_USER_ONLY)
4060 if (ctx
->opcode
& 0x00010000) {
4061 /* Special form that does not need any synchronisation */
4062 TCGv t0
= tcg_temp_new();
4063 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4064 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4065 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4068 TCGv msr
= tcg_temp_new();
4070 /* XXX: we need to update nip before the store
4071 * if we enter power saving mode, we will exit the loop
4072 * directly from ppc_store_msr
4074 gen_update_nip(ctx
, ctx
->nip
);
4075 #if defined(TARGET_PPC64)
4076 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4078 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4080 gen_helper_store_msr(cpu_env
, msr
);
4082 /* Must stop the translation as machine state (may have) changed */
4083 /* Note that mtmsr is not always defined as context-synchronizing */
4084 gen_stop_exception(ctx
);
4090 static void gen_mtspr(DisasContext
*ctx
)
4092 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4093 uint32_t sprn
= SPR(ctx
->opcode
);
4095 #if defined(CONFIG_USER_ONLY)
4096 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4099 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4100 } else if (ctx
->hv
) {
4101 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4103 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4106 if (likely(write_cb
!= NULL
)) {
4107 if (likely(write_cb
!= SPR_NOACCESS
)) {
4108 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4110 /* Privilege exception */
4111 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
4112 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4113 if (qemu_log_separate()) {
4114 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4115 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4117 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4120 /* ISA 2.07 defines these as no-ops */
4121 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4122 (sprn
>= 808 && sprn
<= 811)) {
4128 if (qemu_log_separate()) {
4129 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4130 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4132 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
4133 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4136 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4137 * it can generate a priv, a hv emu or a no-op
4141 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4144 if (ctx
->pr
|| sprn
== 0) {
4145 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4151 #if defined(TARGET_PPC64)
4153 static void gen_setb(DisasContext
*ctx
)
4155 TCGv_i32 t0
= tcg_temp_new_i32();
4156 TCGv_i32 t8
= tcg_temp_new_i32();
4157 TCGv_i32 tm1
= tcg_temp_new_i32();
4158 int crf
= crfS(ctx
->opcode
);
4160 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
4161 tcg_gen_movi_i32(t8
, 8);
4162 tcg_gen_movi_i32(tm1
, -1);
4163 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
4164 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4166 tcg_temp_free_i32(t0
);
4167 tcg_temp_free_i32(t8
);
4168 tcg_temp_free_i32(tm1
);
4172 /*** Cache management ***/
4175 static void gen_dcbf(DisasContext
*ctx
)
4177 /* XXX: specification says this is treated as a load by the MMU */
4179 gen_set_access_type(ctx
, ACCESS_CACHE
);
4180 t0
= tcg_temp_new();
4181 gen_addr_reg_index(ctx
, t0
);
4182 gen_qemu_ld8u(ctx
, t0
, t0
);
4186 /* dcbi (Supervisor only) */
4187 static void gen_dcbi(DisasContext
*ctx
)
4189 #if defined(CONFIG_USER_ONLY)
4195 EA
= tcg_temp_new();
4196 gen_set_access_type(ctx
, ACCESS_CACHE
);
4197 gen_addr_reg_index(ctx
, EA
);
4198 val
= tcg_temp_new();
4199 /* XXX: specification says this should be treated as a store by the MMU */
4200 gen_qemu_ld8u(ctx
, val
, EA
);
4201 gen_qemu_st8(ctx
, val
, EA
);
4204 #endif /* defined(CONFIG_USER_ONLY) */
4208 static void gen_dcbst(DisasContext
*ctx
)
4210 /* XXX: specification say this is treated as a load by the MMU */
4212 gen_set_access_type(ctx
, ACCESS_CACHE
);
4213 t0
= tcg_temp_new();
4214 gen_addr_reg_index(ctx
, t0
);
4215 gen_qemu_ld8u(ctx
, t0
, t0
);
4220 static void gen_dcbt(DisasContext
*ctx
)
4222 /* interpreted as no-op */
4223 /* XXX: specification say this is treated as a load by the MMU
4224 * but does not generate any exception
4229 static void gen_dcbtst(DisasContext
*ctx
)
4231 /* interpreted as no-op */
4232 /* XXX: specification say this is treated as a load by the MMU
4233 * but does not generate any exception
4238 static void gen_dcbtls(DisasContext
*ctx
)
4240 /* Always fails locking the cache */
4241 TCGv t0
= tcg_temp_new();
4242 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4243 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4244 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4249 static void gen_dcbz(DisasContext
*ctx
)
4254 gen_set_access_type(ctx
, ACCESS_CACHE
);
4255 tcgv_addr
= tcg_temp_new();
4256 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4257 gen_addr_reg_index(ctx
, tcgv_addr
);
4258 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
4259 tcg_temp_free(tcgv_addr
);
4260 tcg_temp_free_i32(tcgv_op
);
4264 static void gen_dst(DisasContext
*ctx
)
4266 if (rA(ctx
->opcode
) == 0) {
4267 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4269 /* interpreted as no-op */
4274 static void gen_dstst(DisasContext
*ctx
)
4276 if (rA(ctx
->opcode
) == 0) {
4277 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4279 /* interpreted as no-op */
4285 static void gen_dss(DisasContext
*ctx
)
4287 /* interpreted as no-op */
4291 static void gen_icbi(DisasContext
*ctx
)
4294 gen_set_access_type(ctx
, ACCESS_CACHE
);
4295 t0
= tcg_temp_new();
4296 gen_addr_reg_index(ctx
, t0
);
4297 gen_helper_icbi(cpu_env
, t0
);
4303 static void gen_dcba(DisasContext
*ctx
)
4305 /* interpreted as no-op */
4306 /* XXX: specification say this is treated as a store by the MMU
4307 * but does not generate any exception
4311 /*** Segment register manipulation ***/
4312 /* Supervisor only: */
4315 static void gen_mfsr(DisasContext
*ctx
)
4317 #if defined(CONFIG_USER_ONLY)
4323 t0
= tcg_const_tl(SR(ctx
->opcode
));
4324 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4326 #endif /* defined(CONFIG_USER_ONLY) */
4330 static void gen_mfsrin(DisasContext
*ctx
)
4332 #if defined(CONFIG_USER_ONLY)
4338 t0
= tcg_temp_new();
4339 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4340 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4342 #endif /* defined(CONFIG_USER_ONLY) */
4346 static void gen_mtsr(DisasContext
*ctx
)
4348 #if defined(CONFIG_USER_ONLY)
4354 t0
= tcg_const_tl(SR(ctx
->opcode
));
4355 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4357 #endif /* defined(CONFIG_USER_ONLY) */
4361 static void gen_mtsrin(DisasContext
*ctx
)
4363 #if defined(CONFIG_USER_ONLY)
4369 t0
= tcg_temp_new();
4370 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4371 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4373 #endif /* defined(CONFIG_USER_ONLY) */
4376 #if defined(TARGET_PPC64)
4377 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4380 static void gen_mfsr_64b(DisasContext
*ctx
)
4382 #if defined(CONFIG_USER_ONLY)
4388 t0
= tcg_const_tl(SR(ctx
->opcode
));
4389 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4391 #endif /* defined(CONFIG_USER_ONLY) */
4395 static void gen_mfsrin_64b(DisasContext
*ctx
)
4397 #if defined(CONFIG_USER_ONLY)
4403 t0
= tcg_temp_new();
4404 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4405 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4407 #endif /* defined(CONFIG_USER_ONLY) */
4411 static void gen_mtsr_64b(DisasContext
*ctx
)
4413 #if defined(CONFIG_USER_ONLY)
4419 t0
= tcg_const_tl(SR(ctx
->opcode
));
4420 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4422 #endif /* defined(CONFIG_USER_ONLY) */
4426 static void gen_mtsrin_64b(DisasContext
*ctx
)
4428 #if defined(CONFIG_USER_ONLY)
4434 t0
= tcg_temp_new();
4435 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4436 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4438 #endif /* defined(CONFIG_USER_ONLY) */
4442 static void gen_slbmte(DisasContext
*ctx
)
4444 #if defined(CONFIG_USER_ONLY)
4449 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4450 cpu_gpr
[rS(ctx
->opcode
)]);
4451 #endif /* defined(CONFIG_USER_ONLY) */
4454 static void gen_slbmfee(DisasContext
*ctx
)
4456 #if defined(CONFIG_USER_ONLY)
4461 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4462 cpu_gpr
[rB(ctx
->opcode
)]);
4463 #endif /* defined(CONFIG_USER_ONLY) */
4466 static void gen_slbmfev(DisasContext
*ctx
)
4468 #if defined(CONFIG_USER_ONLY)
4473 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4474 cpu_gpr
[rB(ctx
->opcode
)]);
4475 #endif /* defined(CONFIG_USER_ONLY) */
4478 static void gen_slbfee_(DisasContext
*ctx
)
4480 #if defined(CONFIG_USER_ONLY)
4481 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4485 if (unlikely(ctx
->pr
)) {
4486 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4489 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4490 cpu_gpr
[rB(ctx
->opcode
)]);
4491 l1
= gen_new_label();
4492 l2
= gen_new_label();
4493 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4494 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4495 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4498 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4502 #endif /* defined(TARGET_PPC64) */
4504 /*** Lookaside buffer management ***/
4505 /* Optional & supervisor only: */
4508 static void gen_tlbia(DisasContext
*ctx
)
4510 #if defined(CONFIG_USER_ONLY)
4515 gen_helper_tlbia(cpu_env
);
4516 #endif /* defined(CONFIG_USER_ONLY) */
4520 static void gen_tlbiel(DisasContext
*ctx
)
4522 #if defined(CONFIG_USER_ONLY)
4527 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4528 #endif /* defined(CONFIG_USER_ONLY) */
4532 static void gen_tlbie(DisasContext
*ctx
)
4534 #if defined(CONFIG_USER_ONLY)
4540 CHK_SV
; /* If gtse is set then tblie is supervisor privileged */
4542 CHK_HV
; /* Else hypervisor privileged */
4545 if (NARROW_MODE(ctx
)) {
4546 TCGv t0
= tcg_temp_new();
4547 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4548 gen_helper_tlbie(cpu_env
, t0
);
4551 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4553 t1
= tcg_temp_new_i32();
4554 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4555 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
4556 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4557 tcg_temp_free_i32(t1
);
4558 #endif /* defined(CONFIG_USER_ONLY) */
4562 static void gen_tlbsync(DisasContext
*ctx
)
4564 #if defined(CONFIG_USER_ONLY)
4569 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4570 if (ctx
->insns_flags
& PPC_BOOKE
) {
4571 gen_check_tlb_flush(ctx
, true);
4573 #endif /* defined(CONFIG_USER_ONLY) */
4576 #if defined(TARGET_PPC64)
4578 static void gen_slbia(DisasContext
*ctx
)
4580 #if defined(CONFIG_USER_ONLY)
4585 gen_helper_slbia(cpu_env
);
4586 #endif /* defined(CONFIG_USER_ONLY) */
4590 static void gen_slbie(DisasContext
*ctx
)
4592 #if defined(CONFIG_USER_ONLY)
4597 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4598 #endif /* defined(CONFIG_USER_ONLY) */
4602 static void gen_slbieg(DisasContext
*ctx
)
4604 #if defined(CONFIG_USER_ONLY)
4609 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4610 #endif /* defined(CONFIG_USER_ONLY) */
4614 static void gen_slbsync(DisasContext
*ctx
)
4616 #if defined(CONFIG_USER_ONLY)
4620 gen_check_tlb_flush(ctx
, true);
4621 #endif /* defined(CONFIG_USER_ONLY) */
4624 #endif /* defined(TARGET_PPC64) */
4626 /*** External control ***/
4630 static void gen_eciwx(DisasContext
*ctx
)
4633 /* Should check EAR[E] ! */
4634 gen_set_access_type(ctx
, ACCESS_EXT
);
4635 t0
= tcg_temp_new();
4636 gen_addr_reg_index(ctx
, t0
);
4637 gen_check_align(ctx
, t0
, 0x03);
4638 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4643 static void gen_ecowx(DisasContext
*ctx
)
4646 /* Should check EAR[E] ! */
4647 gen_set_access_type(ctx
, ACCESS_EXT
);
4648 t0
= tcg_temp_new();
4649 gen_addr_reg_index(ctx
, t0
);
4650 gen_check_align(ctx
, t0
, 0x03);
4651 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4655 /* PowerPC 601 specific instructions */
4658 static void gen_abs(DisasContext
*ctx
)
4660 TCGLabel
*l1
= gen_new_label();
4661 TCGLabel
*l2
= gen_new_label();
4662 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4663 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4666 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4668 if (unlikely(Rc(ctx
->opcode
) != 0))
4669 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4673 static void gen_abso(DisasContext
*ctx
)
4675 TCGLabel
*l1
= gen_new_label();
4676 TCGLabel
*l2
= gen_new_label();
4677 TCGLabel
*l3
= gen_new_label();
4678 /* Start with XER OV disabled, the most likely case */
4679 tcg_gen_movi_tl(cpu_ov
, 0);
4680 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4681 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4682 tcg_gen_movi_tl(cpu_ov
, 1);
4683 tcg_gen_movi_tl(cpu_so
, 1);
4686 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4689 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4691 if (unlikely(Rc(ctx
->opcode
) != 0))
4692 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4696 static void gen_clcs(DisasContext
*ctx
)
4698 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4699 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4700 tcg_temp_free_i32(t0
);
4701 /* Rc=1 sets CR0 to an undefined state */
4705 static void gen_div(DisasContext
*ctx
)
4707 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4708 cpu_gpr
[rB(ctx
->opcode
)]);
4709 if (unlikely(Rc(ctx
->opcode
) != 0))
4710 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4714 static void gen_divo(DisasContext
*ctx
)
4716 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4717 cpu_gpr
[rB(ctx
->opcode
)]);
4718 if (unlikely(Rc(ctx
->opcode
) != 0))
4719 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4723 static void gen_divs(DisasContext
*ctx
)
4725 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4726 cpu_gpr
[rB(ctx
->opcode
)]);
4727 if (unlikely(Rc(ctx
->opcode
) != 0))
4728 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4731 /* divso - divso. */
4732 static void gen_divso(DisasContext
*ctx
)
4734 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4735 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4736 if (unlikely(Rc(ctx
->opcode
) != 0))
4737 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4741 static void gen_doz(DisasContext
*ctx
)
4743 TCGLabel
*l1
= gen_new_label();
4744 TCGLabel
*l2
= gen_new_label();
4745 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4746 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4749 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4751 if (unlikely(Rc(ctx
->opcode
) != 0))
4752 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4756 static void gen_dozo(DisasContext
*ctx
)
4758 TCGLabel
*l1
= gen_new_label();
4759 TCGLabel
*l2
= gen_new_label();
4760 TCGv t0
= tcg_temp_new();
4761 TCGv t1
= tcg_temp_new();
4762 TCGv t2
= tcg_temp_new();
4763 /* Start with XER OV disabled, the most likely case */
4764 tcg_gen_movi_tl(cpu_ov
, 0);
4765 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4766 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4767 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4768 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4769 tcg_gen_andc_tl(t1
, t1
, t2
);
4770 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4771 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4772 tcg_gen_movi_tl(cpu_ov
, 1);
4773 tcg_gen_movi_tl(cpu_so
, 1);
4776 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4781 if (unlikely(Rc(ctx
->opcode
) != 0))
4782 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4786 static void gen_dozi(DisasContext
*ctx
)
4788 target_long simm
= SIMM(ctx
->opcode
);
4789 TCGLabel
*l1
= gen_new_label();
4790 TCGLabel
*l2
= gen_new_label();
4791 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4792 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4795 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4797 if (unlikely(Rc(ctx
->opcode
) != 0))
4798 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4801 /* lscbx - lscbx. */
4802 static void gen_lscbx(DisasContext
*ctx
)
4804 TCGv t0
= tcg_temp_new();
4805 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4806 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4807 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4809 gen_addr_reg_index(ctx
, t0
);
4810 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4811 tcg_temp_free_i32(t1
);
4812 tcg_temp_free_i32(t2
);
4813 tcg_temp_free_i32(t3
);
4814 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4815 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4816 if (unlikely(Rc(ctx
->opcode
) != 0))
4817 gen_set_Rc0(ctx
, t0
);
4821 /* maskg - maskg. */
4822 static void gen_maskg(DisasContext
*ctx
)
4824 TCGLabel
*l1
= gen_new_label();
4825 TCGv t0
= tcg_temp_new();
4826 TCGv t1
= tcg_temp_new();
4827 TCGv t2
= tcg_temp_new();
4828 TCGv t3
= tcg_temp_new();
4829 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4830 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4831 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4832 tcg_gen_addi_tl(t2
, t0
, 1);
4833 tcg_gen_shr_tl(t2
, t3
, t2
);
4834 tcg_gen_shr_tl(t3
, t3
, t1
);
4835 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4836 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4837 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4843 if (unlikely(Rc(ctx
->opcode
) != 0))
4844 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4847 /* maskir - maskir. */
4848 static void gen_maskir(DisasContext
*ctx
)
4850 TCGv t0
= tcg_temp_new();
4851 TCGv t1
= tcg_temp_new();
4852 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4853 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4854 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4857 if (unlikely(Rc(ctx
->opcode
) != 0))
4858 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4862 static void gen_mul(DisasContext
*ctx
)
4864 TCGv_i64 t0
= tcg_temp_new_i64();
4865 TCGv_i64 t1
= tcg_temp_new_i64();
4866 TCGv t2
= tcg_temp_new();
4867 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4868 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4869 tcg_gen_mul_i64(t0
, t0
, t1
);
4870 tcg_gen_trunc_i64_tl(t2
, t0
);
4871 gen_store_spr(SPR_MQ
, t2
);
4872 tcg_gen_shri_i64(t1
, t0
, 32);
4873 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4874 tcg_temp_free_i64(t0
);
4875 tcg_temp_free_i64(t1
);
4877 if (unlikely(Rc(ctx
->opcode
) != 0))
4878 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4882 static void gen_mulo(DisasContext
*ctx
)
4884 TCGLabel
*l1
= gen_new_label();
4885 TCGv_i64 t0
= tcg_temp_new_i64();
4886 TCGv_i64 t1
= tcg_temp_new_i64();
4887 TCGv t2
= tcg_temp_new();
4888 /* Start with XER OV disabled, the most likely case */
4889 tcg_gen_movi_tl(cpu_ov
, 0);
4890 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4891 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4892 tcg_gen_mul_i64(t0
, t0
, t1
);
4893 tcg_gen_trunc_i64_tl(t2
, t0
);
4894 gen_store_spr(SPR_MQ
, t2
);
4895 tcg_gen_shri_i64(t1
, t0
, 32);
4896 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4897 tcg_gen_ext32s_i64(t1
, t0
);
4898 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4899 tcg_gen_movi_tl(cpu_ov
, 1);
4900 tcg_gen_movi_tl(cpu_so
, 1);
4902 tcg_temp_free_i64(t0
);
4903 tcg_temp_free_i64(t1
);
4905 if (unlikely(Rc(ctx
->opcode
) != 0))
4906 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4910 static void gen_nabs(DisasContext
*ctx
)
4912 TCGLabel
*l1
= gen_new_label();
4913 TCGLabel
*l2
= gen_new_label();
4914 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4915 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4918 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4920 if (unlikely(Rc(ctx
->opcode
) != 0))
4921 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4924 /* nabso - nabso. */
4925 static void gen_nabso(DisasContext
*ctx
)
4927 TCGLabel
*l1
= gen_new_label();
4928 TCGLabel
*l2
= gen_new_label();
4929 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4930 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4933 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4935 /* nabs never overflows */
4936 tcg_gen_movi_tl(cpu_ov
, 0);
4937 if (unlikely(Rc(ctx
->opcode
) != 0))
4938 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4942 static void gen_rlmi(DisasContext
*ctx
)
4944 uint32_t mb
= MB(ctx
->opcode
);
4945 uint32_t me
= ME(ctx
->opcode
);
4946 TCGv t0
= tcg_temp_new();
4947 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4948 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4949 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4950 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4951 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4953 if (unlikely(Rc(ctx
->opcode
) != 0))
4954 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4958 static void gen_rrib(DisasContext
*ctx
)
4960 TCGv t0
= tcg_temp_new();
4961 TCGv t1
= tcg_temp_new();
4962 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4963 tcg_gen_movi_tl(t1
, 0x80000000);
4964 tcg_gen_shr_tl(t1
, t1
, t0
);
4965 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4966 tcg_gen_and_tl(t0
, t0
, t1
);
4967 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4968 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4971 if (unlikely(Rc(ctx
->opcode
) != 0))
4972 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4976 static void gen_sle(DisasContext
*ctx
)
4978 TCGv t0
= tcg_temp_new();
4979 TCGv t1
= tcg_temp_new();
4980 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4981 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4982 tcg_gen_subfi_tl(t1
, 32, t1
);
4983 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4984 tcg_gen_or_tl(t1
, t0
, t1
);
4985 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4986 gen_store_spr(SPR_MQ
, t1
);
4989 if (unlikely(Rc(ctx
->opcode
) != 0))
4990 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4994 static void gen_sleq(DisasContext
*ctx
)
4996 TCGv t0
= tcg_temp_new();
4997 TCGv t1
= tcg_temp_new();
4998 TCGv t2
= tcg_temp_new();
4999 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5000 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5001 tcg_gen_shl_tl(t2
, t2
, t0
);
5002 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5003 gen_load_spr(t1
, SPR_MQ
);
5004 gen_store_spr(SPR_MQ
, t0
);
5005 tcg_gen_and_tl(t0
, t0
, t2
);
5006 tcg_gen_andc_tl(t1
, t1
, t2
);
5007 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5011 if (unlikely(Rc(ctx
->opcode
) != 0))
5012 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5016 static void gen_sliq(DisasContext
*ctx
)
5018 int sh
= SH(ctx
->opcode
);
5019 TCGv t0
= tcg_temp_new();
5020 TCGv t1
= tcg_temp_new();
5021 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5022 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5023 tcg_gen_or_tl(t1
, t0
, t1
);
5024 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5025 gen_store_spr(SPR_MQ
, t1
);
5028 if (unlikely(Rc(ctx
->opcode
) != 0))
5029 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5032 /* slliq - slliq. */
5033 static void gen_slliq(DisasContext
*ctx
)
5035 int sh
= SH(ctx
->opcode
);
5036 TCGv t0
= tcg_temp_new();
5037 TCGv t1
= tcg_temp_new();
5038 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5039 gen_load_spr(t1
, SPR_MQ
);
5040 gen_store_spr(SPR_MQ
, t0
);
5041 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5042 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5043 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5046 if (unlikely(Rc(ctx
->opcode
) != 0))
5047 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5051 static void gen_sllq(DisasContext
*ctx
)
5053 TCGLabel
*l1
= gen_new_label();
5054 TCGLabel
*l2
= gen_new_label();
5055 TCGv t0
= tcg_temp_local_new();
5056 TCGv t1
= tcg_temp_local_new();
5057 TCGv t2
= tcg_temp_local_new();
5058 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5059 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5060 tcg_gen_shl_tl(t1
, t1
, t2
);
5061 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5062 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5063 gen_load_spr(t0
, SPR_MQ
);
5064 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5067 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5068 gen_load_spr(t2
, SPR_MQ
);
5069 tcg_gen_andc_tl(t1
, t2
, t1
);
5070 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5075 if (unlikely(Rc(ctx
->opcode
) != 0))
5076 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5080 static void gen_slq(DisasContext
*ctx
)
5082 TCGLabel
*l1
= gen_new_label();
5083 TCGv t0
= tcg_temp_new();
5084 TCGv t1
= tcg_temp_new();
5085 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5086 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5087 tcg_gen_subfi_tl(t1
, 32, t1
);
5088 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5089 tcg_gen_or_tl(t1
, t0
, t1
);
5090 gen_store_spr(SPR_MQ
, t1
);
5091 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5092 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5093 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5094 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5098 if (unlikely(Rc(ctx
->opcode
) != 0))
5099 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5102 /* sraiq - sraiq. */
5103 static void gen_sraiq(DisasContext
*ctx
)
5105 int sh
= SH(ctx
->opcode
);
5106 TCGLabel
*l1
= gen_new_label();
5107 TCGv t0
= tcg_temp_new();
5108 TCGv t1
= tcg_temp_new();
5109 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5110 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5111 tcg_gen_or_tl(t0
, t0
, t1
);
5112 gen_store_spr(SPR_MQ
, t0
);
5113 tcg_gen_movi_tl(cpu_ca
, 0);
5114 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5115 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5116 tcg_gen_movi_tl(cpu_ca
, 1);
5118 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5121 if (unlikely(Rc(ctx
->opcode
) != 0))
5122 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5126 static void gen_sraq(DisasContext
*ctx
)
5128 TCGLabel
*l1
= gen_new_label();
5129 TCGLabel
*l2
= gen_new_label();
5130 TCGv t0
= tcg_temp_new();
5131 TCGv t1
= tcg_temp_local_new();
5132 TCGv t2
= tcg_temp_local_new();
5133 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5134 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5135 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5136 tcg_gen_subfi_tl(t2
, 32, t2
);
5137 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5138 tcg_gen_or_tl(t0
, t0
, t2
);
5139 gen_store_spr(SPR_MQ
, t0
);
5140 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5141 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5142 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5143 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5146 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5147 tcg_gen_movi_tl(cpu_ca
, 0);
5148 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5149 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5150 tcg_gen_movi_tl(cpu_ca
, 1);
5154 if (unlikely(Rc(ctx
->opcode
) != 0))
5155 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5159 static void gen_sre(DisasContext
*ctx
)
5161 TCGv t0
= tcg_temp_new();
5162 TCGv t1
= tcg_temp_new();
5163 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5164 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5165 tcg_gen_subfi_tl(t1
, 32, t1
);
5166 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5167 tcg_gen_or_tl(t1
, t0
, t1
);
5168 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5169 gen_store_spr(SPR_MQ
, t1
);
5172 if (unlikely(Rc(ctx
->opcode
) != 0))
5173 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5177 static void gen_srea(DisasContext
*ctx
)
5179 TCGv t0
= tcg_temp_new();
5180 TCGv t1
= tcg_temp_new();
5181 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5182 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5183 gen_store_spr(SPR_MQ
, t0
);
5184 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5187 if (unlikely(Rc(ctx
->opcode
) != 0))
5188 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5192 static void gen_sreq(DisasContext
*ctx
)
5194 TCGv t0
= tcg_temp_new();
5195 TCGv t1
= tcg_temp_new();
5196 TCGv t2
= tcg_temp_new();
5197 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5198 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5199 tcg_gen_shr_tl(t1
, t1
, t0
);
5200 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5201 gen_load_spr(t2
, SPR_MQ
);
5202 gen_store_spr(SPR_MQ
, t0
);
5203 tcg_gen_and_tl(t0
, t0
, t1
);
5204 tcg_gen_andc_tl(t2
, t2
, t1
);
5205 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5209 if (unlikely(Rc(ctx
->opcode
) != 0))
5210 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5214 static void gen_sriq(DisasContext
*ctx
)
5216 int sh
= SH(ctx
->opcode
);
5217 TCGv t0
= tcg_temp_new();
5218 TCGv t1
= tcg_temp_new();
5219 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5220 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5221 tcg_gen_or_tl(t1
, t0
, t1
);
5222 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5223 gen_store_spr(SPR_MQ
, t1
);
5226 if (unlikely(Rc(ctx
->opcode
) != 0))
5227 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5231 static void gen_srliq(DisasContext
*ctx
)
5233 int sh
= SH(ctx
->opcode
);
5234 TCGv t0
= tcg_temp_new();
5235 TCGv t1
= tcg_temp_new();
5236 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5237 gen_load_spr(t1
, SPR_MQ
);
5238 gen_store_spr(SPR_MQ
, t0
);
5239 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5240 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5241 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5244 if (unlikely(Rc(ctx
->opcode
) != 0))
5245 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5249 static void gen_srlq(DisasContext
*ctx
)
5251 TCGLabel
*l1
= gen_new_label();
5252 TCGLabel
*l2
= gen_new_label();
5253 TCGv t0
= tcg_temp_local_new();
5254 TCGv t1
= tcg_temp_local_new();
5255 TCGv t2
= tcg_temp_local_new();
5256 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5257 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5258 tcg_gen_shr_tl(t2
, t1
, t2
);
5259 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5260 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5261 gen_load_spr(t0
, SPR_MQ
);
5262 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5265 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5266 tcg_gen_and_tl(t0
, t0
, t2
);
5267 gen_load_spr(t1
, SPR_MQ
);
5268 tcg_gen_andc_tl(t1
, t1
, t2
);
5269 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5274 if (unlikely(Rc(ctx
->opcode
) != 0))
5275 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5279 static void gen_srq(DisasContext
*ctx
)
5281 TCGLabel
*l1
= gen_new_label();
5282 TCGv t0
= tcg_temp_new();
5283 TCGv t1
= tcg_temp_new();
5284 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5285 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5286 tcg_gen_subfi_tl(t1
, 32, t1
);
5287 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5288 tcg_gen_or_tl(t1
, t0
, t1
);
5289 gen_store_spr(SPR_MQ
, t1
);
5290 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5291 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5292 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5293 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5297 if (unlikely(Rc(ctx
->opcode
) != 0))
5298 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5301 /* PowerPC 602 specific instructions */
5304 static void gen_dsa(DisasContext
*ctx
)
5307 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5311 static void gen_esa(DisasContext
*ctx
)
5314 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5318 static void gen_mfrom(DisasContext
*ctx
)
5320 #if defined(CONFIG_USER_ONLY)
5324 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5325 #endif /* defined(CONFIG_USER_ONLY) */
5328 /* 602 - 603 - G2 TLB management */
5331 static void gen_tlbld_6xx(DisasContext
*ctx
)
5333 #if defined(CONFIG_USER_ONLY)
5337 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5338 #endif /* defined(CONFIG_USER_ONLY) */
5342 static void gen_tlbli_6xx(DisasContext
*ctx
)
5344 #if defined(CONFIG_USER_ONLY)
5348 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5349 #endif /* defined(CONFIG_USER_ONLY) */
5352 /* 74xx TLB management */
5355 static void gen_tlbld_74xx(DisasContext
*ctx
)
5357 #if defined(CONFIG_USER_ONLY)
5361 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5362 #endif /* defined(CONFIG_USER_ONLY) */
5366 static void gen_tlbli_74xx(DisasContext
*ctx
)
5368 #if defined(CONFIG_USER_ONLY)
5372 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5373 #endif /* defined(CONFIG_USER_ONLY) */
5376 /* POWER instructions not in PowerPC 601 */
5379 static void gen_clf(DisasContext
*ctx
)
5381 /* Cache line flush: implemented as no-op */
5385 static void gen_cli(DisasContext
*ctx
)
5387 #if defined(CONFIG_USER_ONLY)
5390 /* Cache line invalidate: privileged and treated as no-op */
5392 #endif /* defined(CONFIG_USER_ONLY) */
5396 static void gen_dclst(DisasContext
*ctx
)
5398 /* Data cache line store: treated as no-op */
5401 static void gen_mfsri(DisasContext
*ctx
)
5403 #if defined(CONFIG_USER_ONLY)
5406 int ra
= rA(ctx
->opcode
);
5407 int rd
= rD(ctx
->opcode
);
5411 t0
= tcg_temp_new();
5412 gen_addr_reg_index(ctx
, t0
);
5413 tcg_gen_extract_tl(t0
, t0
, 28, 4);
5414 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5416 if (ra
!= 0 && ra
!= rd
)
5417 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5418 #endif /* defined(CONFIG_USER_ONLY) */
5421 static void gen_rac(DisasContext
*ctx
)
5423 #if defined(CONFIG_USER_ONLY)
5429 t0
= tcg_temp_new();
5430 gen_addr_reg_index(ctx
, t0
);
5431 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5433 #endif /* defined(CONFIG_USER_ONLY) */
5436 static void gen_rfsvc(DisasContext
*ctx
)
5438 #if defined(CONFIG_USER_ONLY)
5443 gen_helper_rfsvc(cpu_env
);
5444 gen_sync_exception(ctx
);
5445 #endif /* defined(CONFIG_USER_ONLY) */
5448 /* svc is not implemented for now */
5450 /* BookE specific instructions */
5452 /* XXX: not implemented on 440 ? */
5453 static void gen_mfapidi(DisasContext
*ctx
)
5456 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5459 /* XXX: not implemented on 440 ? */
5460 static void gen_tlbiva(DisasContext
*ctx
)
5462 #if defined(CONFIG_USER_ONLY)
5468 t0
= tcg_temp_new();
5469 gen_addr_reg_index(ctx
, t0
);
5470 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5472 #endif /* defined(CONFIG_USER_ONLY) */
5475 /* All 405 MAC instructions are translated here */
5476 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5477 int ra
, int rb
, int rt
, int Rc
)
5481 t0
= tcg_temp_local_new();
5482 t1
= tcg_temp_local_new();
5484 switch (opc3
& 0x0D) {
5486 /* macchw - macchw. - macchwo - macchwo. */
5487 /* macchws - macchws. - macchwso - macchwso. */
5488 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5489 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5490 /* mulchw - mulchw. */
5491 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5492 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5493 tcg_gen_ext16s_tl(t1
, t1
);
5496 /* macchwu - macchwu. - macchwuo - macchwuo. */
5497 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5498 /* mulchwu - mulchwu. */
5499 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5500 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5501 tcg_gen_ext16u_tl(t1
, t1
);
5504 /* machhw - machhw. - machhwo - machhwo. */
5505 /* machhws - machhws. - machhwso - machhwso. */
5506 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5507 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5508 /* mulhhw - mulhhw. */
5509 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5510 tcg_gen_ext16s_tl(t0
, t0
);
5511 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5512 tcg_gen_ext16s_tl(t1
, t1
);
5515 /* machhwu - machhwu. - machhwuo - machhwuo. */
5516 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5517 /* mulhhwu - mulhhwu. */
5518 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5519 tcg_gen_ext16u_tl(t0
, t0
);
5520 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5521 tcg_gen_ext16u_tl(t1
, t1
);
5524 /* maclhw - maclhw. - maclhwo - maclhwo. */
5525 /* maclhws - maclhws. - maclhwso - maclhwso. */
5526 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5527 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5528 /* mullhw - mullhw. */
5529 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5530 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5533 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5534 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5535 /* mullhwu - mullhwu. */
5536 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5537 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5541 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5542 tcg_gen_mul_tl(t1
, t0
, t1
);
5544 /* nmultiply-and-accumulate (0x0E) */
5545 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5547 /* multiply-and-accumulate (0x0C) */
5548 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5552 /* Check overflow and/or saturate */
5553 TCGLabel
*l1
= gen_new_label();
5556 /* Start with XER OV disabled, the most likely case */
5557 tcg_gen_movi_tl(cpu_ov
, 0);
5561 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5562 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5563 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5564 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5567 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5568 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5572 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5575 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5579 /* Check overflow */
5580 tcg_gen_movi_tl(cpu_ov
, 1);
5581 tcg_gen_movi_tl(cpu_so
, 1);
5584 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5587 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5591 if (unlikely(Rc
) != 0) {
5593 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5597 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5598 static void glue(gen_, name)(DisasContext *ctx) \
5600 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5601 rD(ctx->opcode), Rc(ctx->opcode)); \
5604 /* macchw - macchw. */
5605 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5606 /* macchwo - macchwo. */
5607 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5608 /* macchws - macchws. */
5609 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5610 /* macchwso - macchwso. */
5611 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5612 /* macchwsu - macchwsu. */
5613 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5614 /* macchwsuo - macchwsuo. */
5615 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5616 /* macchwu - macchwu. */
5617 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5618 /* macchwuo - macchwuo. */
5619 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5620 /* machhw - machhw. */
5621 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5622 /* machhwo - machhwo. */
5623 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5624 /* machhws - machhws. */
5625 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5626 /* machhwso - machhwso. */
5627 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5628 /* machhwsu - machhwsu. */
5629 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5630 /* machhwsuo - machhwsuo. */
5631 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5632 /* machhwu - machhwu. */
5633 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5634 /* machhwuo - machhwuo. */
5635 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5636 /* maclhw - maclhw. */
5637 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5638 /* maclhwo - maclhwo. */
5639 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5640 /* maclhws - maclhws. */
5641 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5642 /* maclhwso - maclhwso. */
5643 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5644 /* maclhwu - maclhwu. */
5645 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5646 /* maclhwuo - maclhwuo. */
5647 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5648 /* maclhwsu - maclhwsu. */
5649 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5650 /* maclhwsuo - maclhwsuo. */
5651 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5652 /* nmacchw - nmacchw. */
5653 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5654 /* nmacchwo - nmacchwo. */
5655 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5656 /* nmacchws - nmacchws. */
5657 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5658 /* nmacchwso - nmacchwso. */
5659 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5660 /* nmachhw - nmachhw. */
5661 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5662 /* nmachhwo - nmachhwo. */
5663 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5664 /* nmachhws - nmachhws. */
5665 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5666 /* nmachhwso - nmachhwso. */
5667 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5668 /* nmaclhw - nmaclhw. */
5669 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5670 /* nmaclhwo - nmaclhwo. */
5671 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5672 /* nmaclhws - nmaclhws. */
5673 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5674 /* nmaclhwso - nmaclhwso. */
5675 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5677 /* mulchw - mulchw. */
5678 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5679 /* mulchwu - mulchwu. */
5680 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5681 /* mulhhw - mulhhw. */
5682 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5683 /* mulhhwu - mulhhwu. */
5684 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5685 /* mullhw - mullhw. */
5686 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5687 /* mullhwu - mullhwu. */
5688 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5691 static void gen_mfdcr(DisasContext
*ctx
)
5693 #if defined(CONFIG_USER_ONLY)
5699 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5700 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5701 tcg_temp_free(dcrn
);
5702 #endif /* defined(CONFIG_USER_ONLY) */
5706 static void gen_mtdcr(DisasContext
*ctx
)
5708 #if defined(CONFIG_USER_ONLY)
5714 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5715 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5716 tcg_temp_free(dcrn
);
5717 #endif /* defined(CONFIG_USER_ONLY) */
5721 /* XXX: not implemented on 440 ? */
5722 static void gen_mfdcrx(DisasContext
*ctx
)
5724 #if defined(CONFIG_USER_ONLY)
5728 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5729 cpu_gpr
[rA(ctx
->opcode
)]);
5730 /* Note: Rc update flag set leads to undefined state of Rc0 */
5731 #endif /* defined(CONFIG_USER_ONLY) */
5735 /* XXX: not implemented on 440 ? */
5736 static void gen_mtdcrx(DisasContext
*ctx
)
5738 #if defined(CONFIG_USER_ONLY)
5742 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5743 cpu_gpr
[rS(ctx
->opcode
)]);
5744 /* Note: Rc update flag set leads to undefined state of Rc0 */
5745 #endif /* defined(CONFIG_USER_ONLY) */
5748 /* mfdcrux (PPC 460) : user-mode access to DCR */
5749 static void gen_mfdcrux(DisasContext
*ctx
)
5751 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5752 cpu_gpr
[rA(ctx
->opcode
)]);
5753 /* Note: Rc update flag set leads to undefined state of Rc0 */
5756 /* mtdcrux (PPC 460) : user-mode access to DCR */
5757 static void gen_mtdcrux(DisasContext
*ctx
)
5759 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5760 cpu_gpr
[rS(ctx
->opcode
)]);
5761 /* Note: Rc update flag set leads to undefined state of Rc0 */
5765 static void gen_dccci(DisasContext
*ctx
)
5768 /* interpreted as no-op */
5772 static void gen_dcread(DisasContext
*ctx
)
5774 #if defined(CONFIG_USER_ONLY)
5780 gen_set_access_type(ctx
, ACCESS_CACHE
);
5781 EA
= tcg_temp_new();
5782 gen_addr_reg_index(ctx
, EA
);
5783 val
= tcg_temp_new();
5784 gen_qemu_ld32u(ctx
, val
, EA
);
5786 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5788 #endif /* defined(CONFIG_USER_ONLY) */
5792 static void gen_icbt_40x(DisasContext
*ctx
)
5794 /* interpreted as no-op */
5795 /* XXX: specification say this is treated as a load by the MMU
5796 * but does not generate any exception
5801 static void gen_iccci(DisasContext
*ctx
)
5804 /* interpreted as no-op */
5808 static void gen_icread(DisasContext
*ctx
)
5811 /* interpreted as no-op */
5814 /* rfci (supervisor only) */
5815 static void gen_rfci_40x(DisasContext
*ctx
)
5817 #if defined(CONFIG_USER_ONLY)
5821 /* Restore CPU state */
5822 gen_helper_40x_rfci(cpu_env
);
5823 gen_sync_exception(ctx
);
5824 #endif /* defined(CONFIG_USER_ONLY) */
5827 static void gen_rfci(DisasContext
*ctx
)
5829 #if defined(CONFIG_USER_ONLY)
5833 /* Restore CPU state */
5834 gen_helper_rfci(cpu_env
);
5835 gen_sync_exception(ctx
);
5836 #endif /* defined(CONFIG_USER_ONLY) */
5839 /* BookE specific */
5841 /* XXX: not implemented on 440 ? */
5842 static void gen_rfdi(DisasContext
*ctx
)
5844 #if defined(CONFIG_USER_ONLY)
5848 /* Restore CPU state */
5849 gen_helper_rfdi(cpu_env
);
5850 gen_sync_exception(ctx
);
5851 #endif /* defined(CONFIG_USER_ONLY) */
5854 /* XXX: not implemented on 440 ? */
5855 static void gen_rfmci(DisasContext
*ctx
)
5857 #if defined(CONFIG_USER_ONLY)
5861 /* Restore CPU state */
5862 gen_helper_rfmci(cpu_env
);
5863 gen_sync_exception(ctx
);
5864 #endif /* defined(CONFIG_USER_ONLY) */
5867 /* TLB management - PowerPC 405 implementation */
5870 static void gen_tlbre_40x(DisasContext
*ctx
)
5872 #if defined(CONFIG_USER_ONLY)
5876 switch (rB(ctx
->opcode
)) {
5878 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5879 cpu_gpr
[rA(ctx
->opcode
)]);
5882 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5883 cpu_gpr
[rA(ctx
->opcode
)]);
5886 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5889 #endif /* defined(CONFIG_USER_ONLY) */
5892 /* tlbsx - tlbsx. */
5893 static void gen_tlbsx_40x(DisasContext
*ctx
)
5895 #if defined(CONFIG_USER_ONLY)
5901 t0
= tcg_temp_new();
5902 gen_addr_reg_index(ctx
, t0
);
5903 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5905 if (Rc(ctx
->opcode
)) {
5906 TCGLabel
*l1
= gen_new_label();
5907 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5908 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5909 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5912 #endif /* defined(CONFIG_USER_ONLY) */
5916 static void gen_tlbwe_40x(DisasContext
*ctx
)
5918 #if defined(CONFIG_USER_ONLY)
5923 switch (rB(ctx
->opcode
)) {
5925 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5926 cpu_gpr
[rS(ctx
->opcode
)]);
5929 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5930 cpu_gpr
[rS(ctx
->opcode
)]);
5933 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5936 #endif /* defined(CONFIG_USER_ONLY) */
5939 /* TLB management - PowerPC 440 implementation */
5942 static void gen_tlbre_440(DisasContext
*ctx
)
5944 #if defined(CONFIG_USER_ONLY)
5949 switch (rB(ctx
->opcode
)) {
5954 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5955 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5956 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5957 tcg_temp_free_i32(t0
);
5961 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5964 #endif /* defined(CONFIG_USER_ONLY) */
5967 /* tlbsx - tlbsx. */
5968 static void gen_tlbsx_440(DisasContext
*ctx
)
5970 #if defined(CONFIG_USER_ONLY)
5976 t0
= tcg_temp_new();
5977 gen_addr_reg_index(ctx
, t0
);
5978 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5980 if (Rc(ctx
->opcode
)) {
5981 TCGLabel
*l1
= gen_new_label();
5982 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5983 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5984 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5987 #endif /* defined(CONFIG_USER_ONLY) */
5991 static void gen_tlbwe_440(DisasContext
*ctx
)
5993 #if defined(CONFIG_USER_ONLY)
5997 switch (rB(ctx
->opcode
)) {
6002 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6003 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6004 cpu_gpr
[rS(ctx
->opcode
)]);
6005 tcg_temp_free_i32(t0
);
6009 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6012 #endif /* defined(CONFIG_USER_ONLY) */
6015 /* TLB management - PowerPC BookE 2.06 implementation */
6018 static void gen_tlbre_booke206(DisasContext
*ctx
)
6020 #if defined(CONFIG_USER_ONLY)
6024 gen_helper_booke206_tlbre(cpu_env
);
6025 #endif /* defined(CONFIG_USER_ONLY) */
6028 /* tlbsx - tlbsx. */
6029 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6031 #if defined(CONFIG_USER_ONLY)
6037 if (rA(ctx
->opcode
)) {
6038 t0
= tcg_temp_new();
6039 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6041 t0
= tcg_const_tl(0);
6044 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6045 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6047 #endif /* defined(CONFIG_USER_ONLY) */
6051 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6053 #if defined(CONFIG_USER_ONLY)
6057 gen_helper_booke206_tlbwe(cpu_env
);
6058 #endif /* defined(CONFIG_USER_ONLY) */
6061 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6063 #if defined(CONFIG_USER_ONLY)
6069 t0
= tcg_temp_new();
6070 gen_addr_reg_index(ctx
, t0
);
6071 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6073 #endif /* defined(CONFIG_USER_ONLY) */
6076 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6078 #if defined(CONFIG_USER_ONLY)
6084 t0
= tcg_temp_new();
6085 gen_addr_reg_index(ctx
, t0
);
6087 switch((ctx
->opcode
>> 21) & 0x3) {
6089 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6092 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6095 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6098 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6103 #endif /* defined(CONFIG_USER_ONLY) */
6108 static void gen_wrtee(DisasContext
*ctx
)
6110 #if defined(CONFIG_USER_ONLY)
6116 t0
= tcg_temp_new();
6117 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6118 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6119 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6121 /* Stop translation to have a chance to raise an exception
6122 * if we just set msr_ee to 1
6124 gen_stop_exception(ctx
);
6125 #endif /* defined(CONFIG_USER_ONLY) */
6129 static void gen_wrteei(DisasContext
*ctx
)
6131 #if defined(CONFIG_USER_ONLY)
6135 if (ctx
->opcode
& 0x00008000) {
6136 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6137 /* Stop translation to have a chance to raise an exception */
6138 gen_stop_exception(ctx
);
6140 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6142 #endif /* defined(CONFIG_USER_ONLY) */
6145 /* PowerPC 440 specific instructions */
6148 static void gen_dlmzb(DisasContext
*ctx
)
6150 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6151 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6152 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6153 tcg_temp_free_i32(t0
);
6156 /* mbar replaces eieio on 440 */
6157 static void gen_mbar(DisasContext
*ctx
)
6159 /* interpreted as no-op */
6162 /* msync replaces sync on 440 */
6163 static void gen_msync_4xx(DisasContext
*ctx
)
6165 /* interpreted as no-op */
6169 static void gen_icbt_440(DisasContext
*ctx
)
6171 /* interpreted as no-op */
6172 /* XXX: specification say this is treated as a load by the MMU
6173 * but does not generate any exception
6177 /* Embedded.Processor Control */
6179 static void gen_msgclr(DisasContext
*ctx
)
6181 #if defined(CONFIG_USER_ONLY)
6185 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6186 #endif /* defined(CONFIG_USER_ONLY) */
6189 static void gen_msgsnd(DisasContext
*ctx
)
6191 #if defined(CONFIG_USER_ONLY)
6195 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6196 #endif /* defined(CONFIG_USER_ONLY) */
6200 #if defined(TARGET_PPC64)
6201 static void gen_maddld(DisasContext
*ctx
)
6203 TCGv_i64 t1
= tcg_temp_new_i64();
6205 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6206 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6207 tcg_temp_free_i64(t1
);
6210 /* maddhd maddhdu */
6211 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6213 TCGv_i64 lo
= tcg_temp_new_i64();
6214 TCGv_i64 hi
= tcg_temp_new_i64();
6215 TCGv_i64 t1
= tcg_temp_new_i64();
6217 if (Rc(ctx
->opcode
)) {
6218 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6219 cpu_gpr
[rB(ctx
->opcode
)]);
6220 tcg_gen_movi_i64(t1
, 0);
6222 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6223 cpu_gpr
[rB(ctx
->opcode
)]);
6224 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6226 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6227 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6228 tcg_temp_free_i64(lo
);
6229 tcg_temp_free_i64(hi
);
6230 tcg_temp_free_i64(t1
);
6232 #endif /* defined(TARGET_PPC64) */
6234 static void gen_tbegin(DisasContext
*ctx
)
6236 if (unlikely(!ctx
->tm_enabled
)) {
6237 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6240 gen_helper_tbegin(cpu_env
);
6243 #define GEN_TM_NOOP(name) \
6244 static inline void gen_##name(DisasContext *ctx) \
6246 if (unlikely(!ctx->tm_enabled)) { \
6247 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6250 /* Because tbegin always fails in QEMU, these user \
6251 * space instructions all have a simple implementation: \
6253 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6254 * = 0b0 || 0b00 || 0b0 \
6256 tcg_gen_movi_i32(cpu_crf[0], 0); \
6260 GEN_TM_NOOP(tabort
);
6261 GEN_TM_NOOP(tabortwc
);
6262 GEN_TM_NOOP(tabortwci
);
6263 GEN_TM_NOOP(tabortdc
);
6264 GEN_TM_NOOP(tabortdci
);
6266 static inline void gen_cp_abort(DisasContext
*ctx
)
6271 #define GEN_CP_PASTE_NOOP(name) \
6272 static inline void gen_##name(DisasContext *ctx) \
6274 /* Generate invalid exception until \
6275 * we have an implementation of the copy \
6281 GEN_CP_PASTE_NOOP(copy
)
6282 GEN_CP_PASTE_NOOP(paste
)
6284 static void gen_tcheck(DisasContext
*ctx
)
6286 if (unlikely(!ctx
->tm_enabled
)) {
6287 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6290 /* Because tbegin always fails, the tcheck implementation
6293 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6294 * = 0b1 || 0b00 || 0b0
6296 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6299 #if defined(CONFIG_USER_ONLY)
6300 #define GEN_TM_PRIV_NOOP(name) \
6301 static inline void gen_##name(DisasContext *ctx) \
6303 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6308 #define GEN_TM_PRIV_NOOP(name) \
6309 static inline void gen_##name(DisasContext *ctx) \
6312 if (unlikely(!ctx->tm_enabled)) { \
6313 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6316 /* Because tbegin always fails, the implementation is \
6319 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6320 * = 0b0 || 0b00 | 0b0 \
6322 tcg_gen_movi_i32(cpu_crf[0], 0); \
6327 GEN_TM_PRIV_NOOP(treclaim
);
6328 GEN_TM_PRIV_NOOP(trechkpt
);
6330 #include "translate/fp-impl.inc.c"
6332 #include "translate/vmx-impl.inc.c"
6334 #include "translate/vsx-impl.inc.c"
6336 #include "translate/dfp-impl.inc.c"
6338 #include "translate/spe-impl.inc.c"
6340 /* Handles lfdp, lxsd, lxssp */
6341 static void gen_dform39(DisasContext
*ctx
)
6343 switch (ctx
->opcode
& 0x3) {
6345 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6346 return gen_lfdp(ctx
);
6350 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6351 return gen_lxsd(ctx
);
6355 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6356 return gen_lxssp(ctx
);
6360 return gen_invalid(ctx
);
6363 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6364 static void gen_dform3D(DisasContext
*ctx
)
6366 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
6367 switch (ctx
->opcode
& 0x7) {
6369 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6370 return gen_lxv(ctx
);
6374 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6375 return gen_stxv(ctx
);
6379 } else { /* DS-FORM */
6380 switch (ctx
->opcode
& 0x3) {
6382 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6383 return gen_stfdp(ctx
);
6387 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6388 return gen_stxsd(ctx
);
6391 case 3: /* stxssp */
6392 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6393 return gen_stxssp(ctx
);
6398 return gen_invalid(ctx
);
6401 static opcode_t opcodes
[] = {
6402 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6403 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6404 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6405 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER
),
6406 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6407 #if defined(TARGET_PPC64)
6408 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6410 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6411 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6412 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6413 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6414 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6415 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6416 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6417 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6418 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6419 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6420 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6421 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6422 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6423 #if defined(TARGET_PPC64)
6424 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6426 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
6427 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
6428 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6429 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6430 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6431 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
6432 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6433 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
6434 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6435 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
6436 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
6437 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
6438 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6439 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6440 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6441 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6442 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
6443 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
6444 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6445 #if defined(TARGET_PPC64)
6446 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
6447 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
6448 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6449 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
6450 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6451 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
6453 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6454 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6455 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6456 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
6457 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
6458 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
6459 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
6460 #if defined(TARGET_PPC64)
6461 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
6462 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
6463 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
6464 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
6465 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
6466 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6467 PPC_NONE
, PPC2_ISA300
),
6468 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6469 PPC_NONE
, PPC2_ISA300
),
6471 #if defined(TARGET_PPC64)
6472 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6473 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
6474 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6476 /* handles lfdp, lxsd, lxssp */
6477 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6478 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6479 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6480 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6481 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6482 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
6483 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
6484 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
6485 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
6486 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
6487 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
6488 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6489 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6490 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
6491 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6492 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6493 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6494 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6495 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
6496 #if defined(TARGET_PPC64)
6497 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6498 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6499 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
6500 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6501 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
6502 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6504 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
6505 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
6506 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
6507 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6508 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6509 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
6510 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
6511 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
6512 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
6513 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
6514 #if defined(TARGET_PPC64)
6515 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
6516 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6517 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6518 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6519 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6520 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6521 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
6523 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
6524 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
6525 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6526 #if defined(TARGET_PPC64)
6527 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
6528 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6530 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
6531 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
6532 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
6533 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
6534 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
6535 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
6536 #if defined(TARGET_PPC64)
6537 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
6538 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
6539 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
6541 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
6542 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
6543 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
6544 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
6545 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
6546 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
6547 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
6548 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
6549 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
6550 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
6551 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
6552 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
6553 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
6554 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
6555 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
6556 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
6557 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
6558 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
6559 #if defined(TARGET_PPC64)
6560 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
6561 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6563 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
6564 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6566 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
6567 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
6568 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
6569 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
6571 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
6572 /* XXX Those instructions will need to be handled differently for
6573 * different ISA versions */
6574 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
6575 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
6576 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6577 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6578 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
6579 #if defined(TARGET_PPC64)
6580 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
6581 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
6582 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
6583 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6585 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
6586 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
6587 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
6588 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
6589 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
6590 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
6591 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
6592 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
6593 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
6594 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
6595 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
6596 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6597 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
6598 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
6599 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
6600 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
6601 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
6602 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
6603 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
6604 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6605 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
6606 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
6607 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
6608 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
6609 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
6610 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
6611 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
6612 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
6613 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
6614 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
6615 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
6616 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
6617 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
6618 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
6619 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
6620 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
6621 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
6622 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
6623 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
6624 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
6625 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
6626 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
6627 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
6628 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
6629 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
6630 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
6631 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
6632 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
6633 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
6634 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6635 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6636 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
6637 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
6638 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6639 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6640 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
6641 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
6642 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
6643 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
6644 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
6645 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
6646 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
6647 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
6648 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
6649 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
6650 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
6651 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
6652 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
6653 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
6654 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
6655 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
6656 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
6657 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
6658 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
6659 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
6660 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
6661 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
6662 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
6663 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
6664 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
6665 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6666 PPC_NONE
, PPC2_BOOKE206
),
6667 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6668 PPC_NONE
, PPC2_BOOKE206
),
6669 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6670 PPC_NONE
, PPC2_BOOKE206
),
6671 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6672 PPC_NONE
, PPC2_BOOKE206
),
6673 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6674 PPC_NONE
, PPC2_BOOKE206
),
6675 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6676 PPC_NONE
, PPC2_PRCNTL
),
6677 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6678 PPC_NONE
, PPC2_PRCNTL
),
6679 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
6680 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
6681 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
6682 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
6683 PPC_BOOKE
, PPC2_BOOKE206
),
6684 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
6685 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6686 PPC_BOOKE
, PPC2_BOOKE206
),
6687 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
6688 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
6689 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
6690 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
6691 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
6692 #if defined(TARGET_PPC64)
6693 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
6695 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6698 #undef GEN_INT_ARITH_ADD
6699 #undef GEN_INT_ARITH_ADD_CONST
6700 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6701 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6702 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6703 add_ca, compute_ca, compute_ov) \
6704 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6705 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
6706 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
6707 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
6708 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
6709 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
6710 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
6711 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
6712 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
6713 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
6714 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
6716 #undef GEN_INT_ARITH_DIVW
6717 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6718 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6719 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
6720 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
6721 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
6722 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
6723 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6724 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6725 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6726 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6727 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6728 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6730 #if defined(TARGET_PPC64)
6731 #undef GEN_INT_ARITH_DIVD
6732 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6733 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6734 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
6735 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
6736 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
6737 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
6739 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6740 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6741 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6742 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6743 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6744 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6746 #undef GEN_INT_ARITH_MUL_HELPER
6747 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6748 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6749 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
6750 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
6751 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
6754 #undef GEN_INT_ARITH_SUBF
6755 #undef GEN_INT_ARITH_SUBF_CONST
6756 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6757 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6758 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6759 add_ca, compute_ca, compute_ov) \
6760 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6761 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
6762 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
6763 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
6764 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
6765 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
6766 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
6767 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
6768 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
6769 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
6770 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
6774 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6775 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6776 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6777 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6778 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
6779 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
6780 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
6781 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
6782 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
6783 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
6784 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
6785 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
6786 #if defined(TARGET_PPC64)
6787 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
6790 #if defined(TARGET_PPC64)
6793 #define GEN_PPC64_R2(name, opc1, opc2) \
6794 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6795 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6797 #define GEN_PPC64_R4(name, opc1, opc2) \
6798 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6799 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6801 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6803 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6805 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
6806 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
6807 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
6808 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
6809 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
6810 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
6818 #define GEN_LD(name, ldop, opc, type) \
6819 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6820 #define GEN_LDU(name, ldop, opc, type) \
6821 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6822 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6823 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6824 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6825 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6826 #define GEN_LDS(name, ldop, op, type) \
6827 GEN_LD(name, ldop, op | 0x20, type) \
6828 GEN_LDU(name, ldop, op | 0x21, type) \
6829 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6830 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6832 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
6833 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
6834 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
6835 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
6836 #if defined(TARGET_PPC64)
6837 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
6838 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
6839 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
)
6840 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
)
6841 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
6843 /* HV/P7 and later only */
6844 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
6845 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
6846 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
6847 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
6849 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
6850 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
6857 #define GEN_ST(name, stop, opc, type) \
6858 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6859 #define GEN_STU(name, stop, opc, type) \
6860 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6861 #define GEN_STUX(name, stop, opc2, opc3, type) \
6862 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6863 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6864 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6865 #define GEN_STS(name, stop, op, type) \
6866 GEN_ST(name, stop, op | 0x20, type) \
6867 GEN_STU(name, stop, op | 0x21, type) \
6868 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6869 GEN_STX(name, stop, 0x17, op | 0x00, type)
6871 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
6872 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
6873 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
6874 #if defined(TARGET_PPC64)
6875 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
)
6876 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
)
6877 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
6878 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
6879 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
6880 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
6881 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
6883 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
6884 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
6887 #define GEN_CRLOGIC(name, tcg_op, opc) \
6888 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6889 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
6890 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
6891 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
6892 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
6893 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
6894 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
6895 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
6896 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
6898 #undef GEN_MAC_HANDLER
6899 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6900 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6901 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
6902 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
6903 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
6904 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
6905 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
6906 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
6907 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
6908 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
6909 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
6910 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
6911 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
6912 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
6913 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
6914 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
6915 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
6916 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
6917 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
6918 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
6919 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
6920 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
6921 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
6922 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
6923 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
6924 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
6925 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
6926 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
6927 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
6928 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
6929 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
6930 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
6931 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
6932 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
6933 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
6934 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
6935 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
6936 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
6937 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
6938 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
6939 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
6940 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
6941 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
6942 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
6944 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6946 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6948 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6950 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6952 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6954 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6956 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6958 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6960 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6962 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6964 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6967 #include "translate/fp-ops.inc.c"
6969 #include "translate/vmx-ops.inc.c"
6971 #include "translate/vsx-ops.inc.c"
6973 #include "translate/dfp-ops.inc.c"
6975 #include "translate/spe-ops.inc.c"
6978 #include "helper_regs.h"
6979 #include "translate_init.c"
6981 /*****************************************************************************/
6982 /* Misc PowerPC helpers */
6983 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
6989 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
6990 CPUPPCState
*env
= &cpu
->env
;
6993 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
6994 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
6995 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
6997 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
6998 TARGET_FMT_lx
" iidx %d didx %d\n",
6999 env
->msr
, env
->spr
[SPR_HID0
],
7000 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7001 #if !defined(NO_TIMER_DUMP)
7002 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7003 #if !defined(CONFIG_USER_ONLY)
7007 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7008 #if !defined(CONFIG_USER_ONLY)
7009 , cpu_ppc_load_decr(env
)
7013 for (i
= 0; i
< 32; i
++) {
7014 if ((i
& (RGPL
- 1)) == 0)
7015 cpu_fprintf(f
, "GPR%02d", i
);
7016 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7017 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
7018 cpu_fprintf(f
, "\n");
7020 cpu_fprintf(f
, "CR ");
7021 for (i
= 0; i
< 8; i
++)
7022 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
7023 cpu_fprintf(f
, " [");
7024 for (i
= 0; i
< 8; i
++) {
7026 if (env
->crf
[i
] & 0x08)
7028 else if (env
->crf
[i
] & 0x04)
7030 else if (env
->crf
[i
] & 0x02)
7032 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7034 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7036 for (i
= 0; i
< 32; i
++) {
7037 if ((i
& (RFPL
- 1)) == 0)
7038 cpu_fprintf(f
, "FPR%02d", i
);
7039 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
7040 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
7041 cpu_fprintf(f
, "\n");
7043 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7044 #if !defined(CONFIG_USER_ONLY)
7045 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7046 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7047 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7048 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7050 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7051 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7052 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7053 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7055 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7056 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7057 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7058 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7060 #if defined(TARGET_PPC64)
7061 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7062 env
->excp_model
== POWERPC_EXCP_POWER8
) {
7063 cpu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7064 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7067 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7068 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7069 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7070 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7071 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7073 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7074 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7075 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7076 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7078 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7079 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7080 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7081 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7083 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7084 " EPR " TARGET_FMT_lx
"\n",
7085 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7086 env
->spr
[SPR_BOOKE_EPR
]);
7089 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7090 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7091 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7092 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7095 * IVORs are left out as they are large and do not change often --
7096 * they can be read with "p $ivor0", "p $ivor1", etc.
7100 #if defined(TARGET_PPC64)
7101 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7102 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7106 if (env
->spr_cb
[SPR_LPCR
].name
)
7107 cpu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7109 switch (POWERPC_MMU_VER(env
->mmu_model
)) {
7110 case POWERPC_MMU_32B
:
7111 case POWERPC_MMU_601
:
7112 case POWERPC_MMU_SOFT_6xx
:
7113 case POWERPC_MMU_SOFT_74xx
:
7114 #if defined(TARGET_PPC64)
7115 case POWERPC_MMU_VER_64B
:
7116 case POWERPC_MMU_VER_2_03
:
7117 case POWERPC_MMU_VER_2_06
:
7118 case POWERPC_MMU_VER_2_07
:
7119 case POWERPC_MMU_VER_3_00
:
7121 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7122 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7124 cpu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7125 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7127 case POWERPC_MMU_BOOKE206
:
7128 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7129 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7130 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7131 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7133 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7134 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7135 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7136 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7138 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7139 " TLB1CFG " TARGET_FMT_lx
"\n",
7140 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7141 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7152 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
7153 fprintf_function cpu_fprintf
, int flags
)
7155 #if defined(DO_PPC_STATISTICS)
7156 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7157 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7160 t1
= cpu
->env
.opcodes
;
7161 for (op1
= 0; op1
< 64; op1
++) {
7163 if (is_indirect_opcode(handler
)) {
7164 t2
= ind_table(handler
);
7165 for (op2
= 0; op2
< 32; op2
++) {
7167 if (is_indirect_opcode(handler
)) {
7168 t3
= ind_table(handler
);
7169 for (op3
= 0; op3
< 32; op3
++) {
7171 if (handler
->count
== 0)
7173 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
7174 "%016" PRIx64
" %" PRId64
"\n",
7175 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7177 handler
->count
, handler
->count
);
7180 if (handler
->count
== 0)
7182 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
7183 "%016" PRIx64
" %" PRId64
"\n",
7184 op1
, op2
, op1
, op2
, handler
->oname
,
7185 handler
->count
, handler
->count
);
7189 if (handler
->count
== 0)
7191 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
7193 op1
, op1
, handler
->oname
,
7194 handler
->count
, handler
->count
);
7200 /*****************************************************************************/
7201 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
7203 CPUPPCState
*env
= cs
->env_ptr
;
7204 DisasContext ctx
, *ctxp
= &ctx
;
7205 opc_handler_t
**table
, *handler
;
7206 target_ulong pc_start
;
7213 ctx
.exception
= POWERPC_EXCP_NONE
;
7214 ctx
.spr_cb
= env
->spr_cb
;
7216 ctx
.mem_idx
= env
->dmmu_idx
;
7218 #if !defined(CONFIG_USER_ONLY)
7219 ctx
.hv
= msr_hv
|| !env
->has_hv_mode
;
7221 ctx
.insns_flags
= env
->insns_flags
;
7222 ctx
.insns_flags2
= env
->insns_flags2
;
7223 ctx
.access_type
= -1;
7224 ctx
.need_access_type
= !(env
->mmu_model
& POWERPC_MMU_64B
);
7225 ctx
.le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7226 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
7227 #if defined(TARGET_PPC64)
7228 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
7229 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7231 if (env
->mmu_model
== POWERPC_MMU_32B
||
7232 env
->mmu_model
== POWERPC_MMU_601
||
7233 (env
->mmu_model
& POWERPC_MMU_64B
))
7234 ctx
.lazy_tlb_flush
= true;
7236 ctx
.fpu_enabled
= !!msr_fp
;
7237 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
7238 ctx
.spe_enabled
= !!msr_spe
;
7240 ctx
.spe_enabled
= false;
7241 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
7242 ctx
.altivec_enabled
= !!msr_vr
;
7244 ctx
.altivec_enabled
= false;
7245 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7246 ctx
.vsx_enabled
= !!msr_vsx
;
7248 ctx
.vsx_enabled
= false;
7250 #if defined(TARGET_PPC64)
7251 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7252 ctx
.tm_enabled
= !!msr_tm
;
7254 ctx
.tm_enabled
= false;
7257 ctx
.gtse
= !!(env
->spr
[SPR_LPCR
] & LPCR_GTSE
);
7258 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
7259 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
7261 ctx
.singlestep_enabled
= 0;
7262 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
7263 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
7264 if (unlikely(cs
->singlestep_enabled
)) {
7265 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7267 #if defined (DO_SINGLE_STEP) && 0
7268 /* Single step trace mode */
7272 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
7273 if (max_insns
== 0) {
7274 max_insns
= CF_COUNT_MASK
;
7276 if (max_insns
> TCG_MAX_INSNS
) {
7277 max_insns
= TCG_MAX_INSNS
;
7281 tcg_clear_temp_count();
7282 /* Set env in case of segfault during code fetch */
7283 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
7284 tcg_gen_insn_start(ctx
.nip
);
7287 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
7288 gen_debug_exception(ctxp
);
7289 /* The address covered by the breakpoint must be included in
7290 [tb->pc, tb->pc + tb->size) in order to for it to be
7291 properly cleared -- thus we increment the PC here so that
7292 the logic setting tb->size below does the right thing. */
7297 LOG_DISAS("----------------\n");
7298 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7299 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
7300 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
))
7302 if (unlikely(need_byteswap(&ctx
))) {
7303 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
7305 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
7307 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7308 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7309 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7310 ctx
.le_mode
? "little" : "big");
7312 table
= env
->opcodes
;
7313 handler
= table
[opc1(ctx
.opcode
)];
7314 if (is_indirect_opcode(handler
)) {
7315 table
= ind_table(handler
);
7316 handler
= table
[opc2(ctx
.opcode
)];
7317 if (is_indirect_opcode(handler
)) {
7318 table
= ind_table(handler
);
7319 handler
= table
[opc3(ctx
.opcode
)];
7320 if (is_indirect_opcode(handler
)) {
7321 table
= ind_table(handler
);
7322 handler
= table
[opc4(ctx
.opcode
)];
7326 /* Is opcode *REALLY* valid ? */
7327 if (unlikely(handler
->handler
== &gen_invalid
)) {
7328 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
7329 "%02x - %02x - %02x - %02x (%08x) "
7330 TARGET_FMT_lx
" %d\n",
7331 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7332 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7333 ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
7337 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
7338 inval
= handler
->inval2
;
7340 inval
= handler
->inval1
;
7343 if (unlikely((ctx
.opcode
& inval
) != 0)) {
7344 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
7345 "%02x - %02x - %02x - %02x (%08x) "
7346 TARGET_FMT_lx
"\n", ctx
.opcode
& inval
,
7347 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7348 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7349 ctx
.opcode
, ctx
.nip
- 4);
7350 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
7354 (*(handler
->handler
))(&ctx
);
7355 #if defined(DO_PPC_STATISTICS)
7358 /* Check trace mode exceptions */
7359 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
7360 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
7361 ctx
.exception
!= POWERPC_SYSCALL
&&
7362 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
7363 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
7364 gen_exception_nip(ctxp
, POWERPC_EXCP_TRACE
, ctx
.nip
);
7365 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
7366 (cs
->singlestep_enabled
) ||
7368 num_insns
>= max_insns
)) {
7369 /* if we reach a page boundary or are single stepping, stop
7374 if (tcg_check_temp_count()) {
7375 fprintf(stderr
, "Opcode %02x %02x %02x %02x (%08x) leaked "
7376 "temporaries\n", opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7377 opc3(ctx
.opcode
), opc4(ctx
.opcode
), ctx
.opcode
);
7381 if (tb_cflags(tb
) & CF_LAST_IO
)
7383 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
7384 gen_goto_tb(&ctx
, 0, ctx
.nip
);
7385 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
7386 if (unlikely(cs
->singlestep_enabled
)) {
7387 gen_debug_exception(ctxp
);
7389 /* Generate the return instruction */
7392 gen_tb_end(tb
, num_insns
);
7394 tb
->size
= ctx
.nip
- pc_start
;
7395 tb
->icount
= num_insns
;
7397 #if defined(DEBUG_DISAS)
7398 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
7399 && qemu_log_in_addr_range(pc_start
)) {
7401 flags
= env
->bfd_mach
;
7402 flags
|= ctx
.le_mode
<< 16;
7404 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7405 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, flags
);
7412 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,