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target-ppc: Bug Fix: rlwnm
[qemu/ar7.git] / target-ppc / translate.c
blobbe7d40bbf8be45e5729962dc66c3c057a8c5d47c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define PPC_DEBUG_DISAS
39 //#define DO_PPC_STATISTICS
40
41 #ifdef PPC_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DISAS(...) do { } while (0)
45 #endif
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 + 10*4 + 22*5 /* SPE GPRh */
53 + 10*4 + 22*5 /* FPR */
54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 10*5 + 22*6 /* VSR */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 static TCGv cpu_gprh[32];
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i64 cpu_vsr[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
71 static TCGv cpu_reserve;
72 static TCGv cpu_fpscr;
73 static TCGv_i32 cpu_access_type;
74
75 #include "exec/gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 size_t cpu_reg_names_size;
82 static int done_init = 0;
83
84 if (done_init)
85 return;
86
87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
171
172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, reserve_addr),
174 "reserve_addr");
175
176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
178
179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
180 offsetof(CPUPPCState, access_type), "access_type");
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 TCGMemOp default_tcg_memop_mask;
197 #if defined(TARGET_PPC64)
198 int sf_mode;
199 int has_cfar;
200 #endif
201 int fpu_enabled;
202 int altivec_enabled;
203 int vsx_enabled;
204 int spe_enabled;
205 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
206 int singlestep_enabled;
207 uint64_t insns_flags;
208 uint64_t insns_flags2;
209 } DisasContext;
210
211 /* Return true iff byteswap is needed in a scalar memop */
212 static inline bool need_byteswap(const DisasContext *ctx)
213 {
214 #if defined(TARGET_WORDS_BIGENDIAN)
215 return ctx->le_mode;
216 #else
217 return !ctx->le_mode;
218 #endif
219 }
220
221 /* True when active word size < size of target_long. */
222 #ifdef TARGET_PPC64
223 # define NARROW_MODE(C) (!(C)->sf_mode)
224 #else
225 # define NARROW_MODE(C) 0
226 #endif
227
228 struct opc_handler_t {
229 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
230 uint32_t inval1;
231 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
232 uint32_t inval2;
233 /* instruction type */
234 uint64_t type;
235 /* extended instruction type */
236 uint64_t type2;
237 /* handler */
238 void (*handler)(DisasContext *ctx);
239 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
240 const char *oname;
241 #endif
242 #if defined(DO_PPC_STATISTICS)
243 uint64_t count;
244 #endif
245 };
246
247 static inline void gen_reset_fpstatus(void)
248 {
249 gen_helper_reset_fpstatus(cpu_env);
250 }
251
252 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
253 {
254 TCGv_i32 t0 = tcg_temp_new_i32();
255
256 if (set_fprf != 0) {
257 /* This case might be optimized later */
258 tcg_gen_movi_i32(t0, 1);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 if (unlikely(set_rc)) {
261 tcg_gen_mov_i32(cpu_crf[1], t0);
262 }
263 gen_helper_float_check_status(cpu_env);
264 } else if (unlikely(set_rc)) {
265 /* We always need to compute fpcc */
266 tcg_gen_movi_i32(t0, 0);
267 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
268 tcg_gen_mov_i32(cpu_crf[1], t0);
269 }
270
271 tcg_temp_free_i32(t0);
272 }
273
274 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
275 {
276 if (ctx->access_type != access_type) {
277 tcg_gen_movi_i32(cpu_access_type, access_type);
278 ctx->access_type = access_type;
279 }
280 }
281
282 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
283 {
284 if (NARROW_MODE(ctx)) {
285 nip = (uint32_t)nip;
286 }
287 tcg_gen_movi_tl(cpu_nip, nip);
288 }
289
290 void gen_update_current_nip(void *opaque)
291 {
292 DisasContext *ctx = opaque;
293
294 tcg_gen_movi_tl(cpu_nip, ctx->nip);
295 }
296
297 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
298 {
299 TCGv_i32 t0, t1;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
304 t1 = tcg_const_i32(error);
305 gen_helper_raise_exception_err(cpu_env, t0, t1);
306 tcg_temp_free_i32(t0);
307 tcg_temp_free_i32(t1);
308 ctx->exception = (excp);
309 }
310
311 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
312 {
313 TCGv_i32 t0;
314 if (ctx->exception == POWERPC_EXCP_NONE) {
315 gen_update_nip(ctx, ctx->nip);
316 }
317 t0 = tcg_const_i32(excp);
318 gen_helper_raise_exception(cpu_env, t0);
319 tcg_temp_free_i32(t0);
320 ctx->exception = (excp);
321 }
322
323 static inline void gen_debug_exception(DisasContext *ctx)
324 {
325 TCGv_i32 t0;
326
327 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
328 (ctx->exception != POWERPC_EXCP_SYNC)) {
329 gen_update_nip(ctx, ctx->nip);
330 }
331 t0 = tcg_const_i32(EXCP_DEBUG);
332 gen_helper_raise_exception(cpu_env, t0);
333 tcg_temp_free_i32(t0);
334 }
335
336 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
337 {
338 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
339 }
340
341 /* Stop translation */
342 static inline void gen_stop_exception(DisasContext *ctx)
343 {
344 gen_update_nip(ctx, ctx->nip);
345 ctx->exception = POWERPC_EXCP_STOP;
346 }
347
348 /* No need to update nip here, as execution flow will change */
349 static inline void gen_sync_exception(DisasContext *ctx)
350 {
351 ctx->exception = POWERPC_EXCP_SYNC;
352 }
353
354 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
355 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
356
357 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
358 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
359
360 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
361 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
362
363 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
364 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
365
366 typedef struct opcode_t {
367 unsigned char opc1, opc2, opc3;
368 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
369 unsigned char pad[5];
370 #else
371 unsigned char pad[1];
372 #endif
373 opc_handler_t handler;
374 const char *oname;
375 } opcode_t;
376
377 /*****************************************************************************/
378 /*** Instruction decoding ***/
379 #define EXTRACT_HELPER(name, shift, nb) \
380 static inline uint32_t name(uint32_t opcode) \
381 { \
382 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
383 }
384
385 #define EXTRACT_SHELPER(name, shift, nb) \
386 static inline int32_t name(uint32_t opcode) \
387 { \
388 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
389 }
390
391 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
392 static inline uint32_t name(uint32_t opcode) \
393 { \
394 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
395 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
396 }
397 /* Opcode part 1 */
398 EXTRACT_HELPER(opc1, 26, 6);
399 /* Opcode part 2 */
400 EXTRACT_HELPER(opc2, 1, 5);
401 /* Opcode part 3 */
402 EXTRACT_HELPER(opc3, 6, 5);
403 /* Update Cr0 flags */
404 EXTRACT_HELPER(Rc, 0, 1);
405 /* Update Cr6 flags (Altivec) */
406 EXTRACT_HELPER(Rc21, 10, 1);
407 /* Destination */
408 EXTRACT_HELPER(rD, 21, 5);
409 /* Source */
410 EXTRACT_HELPER(rS, 21, 5);
411 /* First operand */
412 EXTRACT_HELPER(rA, 16, 5);
413 /* Second operand */
414 EXTRACT_HELPER(rB, 11, 5);
415 /* Third operand */
416 EXTRACT_HELPER(rC, 6, 5);
417 /*** Get CRn ***/
418 EXTRACT_HELPER(crfD, 23, 3);
419 EXTRACT_HELPER(crfS, 18, 3);
420 EXTRACT_HELPER(crbD, 21, 5);
421 EXTRACT_HELPER(crbA, 16, 5);
422 EXTRACT_HELPER(crbB, 11, 5);
423 /* SPR / TBL */
424 EXTRACT_HELPER(_SPR, 11, 10);
425 static inline uint32_t SPR(uint32_t opcode)
426 {
427 uint32_t sprn = _SPR(opcode);
428
429 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
430 }
431 /*** Get constants ***/
432 /* 16 bits signed immediate value */
433 EXTRACT_SHELPER(SIMM, 0, 16);
434 /* 16 bits unsigned immediate value */
435 EXTRACT_HELPER(UIMM, 0, 16);
436 /* 5 bits signed immediate value */
437 EXTRACT_HELPER(SIMM5, 16, 5);
438 /* 5 bits signed immediate value */
439 EXTRACT_HELPER(UIMM5, 16, 5);
440 /* Bit count */
441 EXTRACT_HELPER(NB, 11, 5);
442 /* Shift count */
443 EXTRACT_HELPER(SH, 11, 5);
444 /* Vector shift count */
445 EXTRACT_HELPER(VSH, 6, 4);
446 /* Mask start */
447 EXTRACT_HELPER(MB, 6, 5);
448 /* Mask end */
449 EXTRACT_HELPER(ME, 1, 5);
450 /* Trap operand */
451 EXTRACT_HELPER(TO, 21, 5);
452
453 EXTRACT_HELPER(CRM, 12, 8);
454 EXTRACT_HELPER(SR, 16, 4);
455
456 /* mtfsf/mtfsfi */
457 EXTRACT_HELPER(FPBF, 23, 3);
458 EXTRACT_HELPER(FPIMM, 12, 4);
459 EXTRACT_HELPER(FPL, 25, 1);
460 EXTRACT_HELPER(FPFLM, 17, 8);
461 EXTRACT_HELPER(FPW, 16, 1);
462
463 /*** Jump target decoding ***/
464 /* Immediate address */
465 static inline target_ulong LI(uint32_t opcode)
466 {
467 return (opcode >> 0) & 0x03FFFFFC;
468 }
469
470 static inline uint32_t BD(uint32_t opcode)
471 {
472 return (opcode >> 0) & 0xFFFC;
473 }
474
475 EXTRACT_HELPER(BO, 21, 5);
476 EXTRACT_HELPER(BI, 16, 5);
477 /* Absolute/relative address */
478 EXTRACT_HELPER(AA, 1, 1);
479 /* Link */
480 EXTRACT_HELPER(LK, 0, 1);
481
482 /* DFP Z22-form */
483 EXTRACT_HELPER(DCM, 10, 6)
484
485 /* DFP Z23-form */
486 EXTRACT_HELPER(RMC, 9, 2)
487
488 /* Create a mask between <start> and <end> bits */
489 static inline target_ulong MASK(uint32_t start, uint32_t end)
490 {
491 target_ulong ret;
492
493 #if defined(TARGET_PPC64)
494 if (likely(start == 0)) {
495 ret = UINT64_MAX << (63 - end);
496 } else if (likely(end == 63)) {
497 ret = UINT64_MAX >> start;
498 }
499 #else
500 if (likely(start == 0)) {
501 ret = UINT32_MAX << (31 - end);
502 } else if (likely(end == 31)) {
503 ret = UINT32_MAX >> start;
504 }
505 #endif
506 else {
507 ret = (((target_ulong)(-1ULL)) >> (start)) ^
508 (((target_ulong)(-1ULL) >> (end)) >> 1);
509 if (unlikely(start > end))
510 return ~ret;
511 }
512
513 return ret;
514 }
515
516 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
517 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
518 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
519 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
520 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
521 EXTRACT_HELPER(DM, 8, 2);
522 EXTRACT_HELPER(UIM, 16, 2);
523 EXTRACT_HELPER(SHW, 8, 2);
524 EXTRACT_HELPER(SP, 19, 2);
525 /*****************************************************************************/
526 /* PowerPC instructions table */
527
528 #if defined(DO_PPC_STATISTICS)
529 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
530 { \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
534 .pad = { 0, }, \
535 .handler = { \
536 .inval1 = invl, \
537 .type = _typ, \
538 .type2 = _typ2, \
539 .handler = &gen_##name, \
540 .oname = stringify(name), \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 .oname = stringify(name), \
557 }, \
558 .oname = stringify(name), \
559 }
560 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
561 { \
562 .opc1 = op1, \
563 .opc2 = op2, \
564 .opc3 = op3, \
565 .pad = { 0, }, \
566 .handler = { \
567 .inval1 = invl, \
568 .type = _typ, \
569 .type2 = _typ2, \
570 .handler = &gen_##name, \
571 .oname = onam, \
572 }, \
573 .oname = onam, \
574 }
575 #else
576 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
577 { \
578 .opc1 = op1, \
579 .opc2 = op2, \
580 .opc3 = op3, \
581 .pad = { 0, }, \
582 .handler = { \
583 .inval1 = invl, \
584 .type = _typ, \
585 .type2 = _typ2, \
586 .handler = &gen_##name, \
587 }, \
588 .oname = stringify(name), \
589 }
590 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
591 { \
592 .opc1 = op1, \
593 .opc2 = op2, \
594 .opc3 = op3, \
595 .pad = { 0, }, \
596 .handler = { \
597 .inval1 = invl1, \
598 .inval2 = invl2, \
599 .type = _typ, \
600 .type2 = _typ2, \
601 .handler = &gen_##name, \
602 }, \
603 .oname = stringify(name), \
604 }
605 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
606 { \
607 .opc1 = op1, \
608 .opc2 = op2, \
609 .opc3 = op3, \
610 .pad = { 0, }, \
611 .handler = { \
612 .inval1 = invl, \
613 .type = _typ, \
614 .type2 = _typ2, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618 }
619 #endif
620
621 /* SPR load/store helpers */
622 static inline void gen_load_spr(TCGv t, int reg)
623 {
624 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
625 }
626
627 static inline void gen_store_spr(int reg, TCGv t)
628 {
629 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
630 }
631
632 /* Invalid instruction */
633 static void gen_invalid(DisasContext *ctx)
634 {
635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
636 }
637
638 static opc_handler_t invalid_handler = {
639 .inval1 = 0xFFFFFFFF,
640 .inval2 = 0xFFFFFFFF,
641 .type = PPC_NONE,
642 .type2 = PPC_NONE,
643 .handler = gen_invalid,
644 };
645
646 #if defined(TARGET_PPC64)
647 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
648 /* so the function is wrapped in the standard 64-bit ifdef in order to */
649 /* avoid compiler warnings in 32-bit implementations. */
650 static bool is_user_mode(DisasContext *ctx)
651 {
652 #if defined(CONFIG_USER_ONLY)
653 return true;
654 #else
655 return ctx->mem_idx == 0;
656 #endif
657 }
658 #endif
659
660 /*** Integer comparison ***/
661
662 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
663 {
664 TCGv t0 = tcg_temp_new();
665 TCGv_i32 t1 = tcg_temp_new_i32();
666
667 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
668
669 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
670 tcg_gen_trunc_tl_i32(t1, t0);
671 tcg_gen_shli_i32(t1, t1, CRF_LT);
672 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
673
674 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
675 tcg_gen_trunc_tl_i32(t1, t0);
676 tcg_gen_shli_i32(t1, t1, CRF_GT);
677 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
678
679 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
680 tcg_gen_trunc_tl_i32(t1, t0);
681 tcg_gen_shli_i32(t1, t1, CRF_EQ);
682 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
683
684 tcg_temp_free(t0);
685 tcg_temp_free_i32(t1);
686 }
687
688 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
689 {
690 TCGv t0 = tcg_const_tl(arg1);
691 gen_op_cmp(arg0, t0, s, crf);
692 tcg_temp_free(t0);
693 }
694
695 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
696 {
697 TCGv t0, t1;
698 t0 = tcg_temp_new();
699 t1 = tcg_temp_new();
700 if (s) {
701 tcg_gen_ext32s_tl(t0, arg0);
702 tcg_gen_ext32s_tl(t1, arg1);
703 } else {
704 tcg_gen_ext32u_tl(t0, arg0);
705 tcg_gen_ext32u_tl(t1, arg1);
706 }
707 gen_op_cmp(t0, t1, s, crf);
708 tcg_temp_free(t1);
709 tcg_temp_free(t0);
710 }
711
712 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
713 {
714 TCGv t0 = tcg_const_tl(arg1);
715 gen_op_cmp32(arg0, t0, s, crf);
716 tcg_temp_free(t0);
717 }
718
719 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
720 {
721 if (NARROW_MODE(ctx)) {
722 gen_op_cmpi32(reg, 0, 1, 0);
723 } else {
724 gen_op_cmpi(reg, 0, 1, 0);
725 }
726 }
727
728 /* cmp */
729 static void gen_cmp(DisasContext *ctx)
730 {
731 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
732 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
733 1, crfD(ctx->opcode));
734 } else {
735 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 1, crfD(ctx->opcode));
737 }
738 }
739
740 /* cmpi */
741 static void gen_cmpi(DisasContext *ctx)
742 {
743 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
744 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
745 1, crfD(ctx->opcode));
746 } else {
747 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
748 1, crfD(ctx->opcode));
749 }
750 }
751
752 /* cmpl */
753 static void gen_cmpl(DisasContext *ctx)
754 {
755 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
756 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
757 0, crfD(ctx->opcode));
758 } else {
759 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
760 0, crfD(ctx->opcode));
761 }
762 }
763
764 /* cmpli */
765 static void gen_cmpli(DisasContext *ctx)
766 {
767 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
768 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
769 0, crfD(ctx->opcode));
770 } else {
771 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
772 0, crfD(ctx->opcode));
773 }
774 }
775
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext *ctx)
778 {
779 int l1, l2;
780 uint32_t bi = rC(ctx->opcode);
781 uint32_t mask;
782 TCGv_i32 t0;
783
784 l1 = gen_new_label();
785 l2 = gen_new_label();
786
787 mask = 1 << (3 - (bi & 0x03));
788 t0 = tcg_temp_new_i32();
789 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
790 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
791 if (rA(ctx->opcode) == 0)
792 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
793 else
794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
795 tcg_gen_br(l2);
796 gen_set_label(l1);
797 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
798 gen_set_label(l2);
799 tcg_temp_free_i32(t0);
800 }
801
802 /* cmpb: PowerPC 2.05 specification */
803 static void gen_cmpb(DisasContext *ctx)
804 {
805 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
806 cpu_gpr[rB(ctx->opcode)]);
807 }
808
809 /*** Integer arithmetic ***/
810
811 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
812 TCGv arg1, TCGv arg2, int sub)
813 {
814 TCGv t0 = tcg_temp_new();
815
816 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
817 tcg_gen_xor_tl(t0, arg1, arg2);
818 if (sub) {
819 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
820 } else {
821 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
822 }
823 tcg_temp_free(t0);
824 if (NARROW_MODE(ctx)) {
825 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
826 }
827 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
829 }
830
831 /* Common add function */
832 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
833 TCGv arg2, bool add_ca, bool compute_ca,
834 bool compute_ov, bool compute_rc0)
835 {
836 TCGv t0 = ret;
837
838 if (compute_ca || compute_ov) {
839 t0 = tcg_temp_new();
840 }
841
842 if (compute_ca) {
843 if (NARROW_MODE(ctx)) {
844 /* Caution: a non-obvious corner case of the spec is that we
845 must produce the *entire* 64-bit addition, but produce the
846 carry into bit 32. */
847 TCGv t1 = tcg_temp_new();
848 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
849 tcg_gen_add_tl(t0, arg1, arg2);
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, cpu_ca);
852 }
853 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
854 tcg_temp_free(t1);
855 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
856 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
857 } else {
858 TCGv zero = tcg_const_tl(0);
859 if (add_ca) {
860 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
861 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
862 } else {
863 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
864 }
865 tcg_temp_free(zero);
866 }
867 } else {
868 tcg_gen_add_tl(t0, arg1, arg2);
869 if (add_ca) {
870 tcg_gen_add_tl(t0, t0, cpu_ca);
871 }
872 }
873
874 if (compute_ov) {
875 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
876 }
877 if (unlikely(compute_rc0)) {
878 gen_set_Rc0(ctx, t0);
879 }
880
881 if (!TCGV_EQUAL(t0, ret)) {
882 tcg_gen_mov_tl(ret, t0);
883 tcg_temp_free(t0);
884 }
885 }
886 /* Add functions with two operands */
887 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
888 static void glue(gen_, name)(DisasContext *ctx) \
889 { \
890 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
891 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
892 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
893 }
894 /* Add functions with one operand and one immediate */
895 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
896 add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 TCGv t0 = tcg_const_tl(const_val); \
900 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
901 cpu_gpr[rA(ctx->opcode)], t0, \
902 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
903 tcg_temp_free(t0); \
904 }
905
906 /* add add. addo addo. */
907 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
908 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
909 /* addc addc. addco addco. */
910 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
911 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
912 /* adde adde. addeo addeo. */
913 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
914 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
915 /* addme addme. addmeo addmeo. */
916 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
917 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
918 /* addze addze. addzeo addzeo.*/
919 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
920 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
921 /* addi */
922 static void gen_addi(DisasContext *ctx)
923 {
924 target_long simm = SIMM(ctx->opcode);
925
926 if (rA(ctx->opcode) == 0) {
927 /* li case */
928 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
929 } else {
930 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
931 cpu_gpr[rA(ctx->opcode)], simm);
932 }
933 }
934 /* addic addic.*/
935 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
936 {
937 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
938 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
939 c, 0, 1, 0, compute_rc0);
940 tcg_temp_free(c);
941 }
942
943 static void gen_addic(DisasContext *ctx)
944 {
945 gen_op_addic(ctx, 0);
946 }
947
948 static void gen_addic_(DisasContext *ctx)
949 {
950 gen_op_addic(ctx, 1);
951 }
952
953 /* addis */
954 static void gen_addis(DisasContext *ctx)
955 {
956 target_long simm = SIMM(ctx->opcode);
957
958 if (rA(ctx->opcode) == 0) {
959 /* lis case */
960 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
961 } else {
962 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
963 cpu_gpr[rA(ctx->opcode)], simm << 16);
964 }
965 }
966
967 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
968 TCGv arg2, int sign, int compute_ov)
969 {
970 int l1 = gen_new_label();
971 int l2 = gen_new_label();
972 TCGv_i32 t0 = tcg_temp_local_new_i32();
973 TCGv_i32 t1 = tcg_temp_local_new_i32();
974
975 tcg_gen_trunc_tl_i32(t0, arg1);
976 tcg_gen_trunc_tl_i32(t1, arg2);
977 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
978 if (sign) {
979 int l3 = gen_new_label();
980 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
981 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
982 gen_set_label(l3);
983 tcg_gen_div_i32(t0, t0, t1);
984 } else {
985 tcg_gen_divu_i32(t0, t0, t1);
986 }
987 if (compute_ov) {
988 tcg_gen_movi_tl(cpu_ov, 0);
989 }
990 tcg_gen_br(l2);
991 gen_set_label(l1);
992 if (sign) {
993 tcg_gen_sari_i32(t0, t0, 31);
994 } else {
995 tcg_gen_movi_i32(t0, 0);
996 }
997 if (compute_ov) {
998 tcg_gen_movi_tl(cpu_ov, 1);
999 tcg_gen_movi_tl(cpu_so, 1);
1000 }
1001 gen_set_label(l2);
1002 tcg_gen_extu_i32_tl(ret, t0);
1003 tcg_temp_free_i32(t0);
1004 tcg_temp_free_i32(t1);
1005 if (unlikely(Rc(ctx->opcode) != 0))
1006 gen_set_Rc0(ctx, ret);
1007 }
1008 /* Div functions */
1009 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 sign, compute_ov); \
1015 }
1016 /* divwu divwu. divwuo divwuo. */
1017 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1018 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1019 /* divw divw. divwo divwo. */
1020 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1021 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1022
1023 /* div[wd]eu[o][.] */
1024 #define GEN_DIVE(name, hlpr, compute_ov) \
1025 static void gen_##name(DisasContext *ctx) \
1026 { \
1027 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1028 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1030 tcg_temp_free_i32(t0); \
1031 if (unlikely(Rc(ctx->opcode) != 0)) { \
1032 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1033 } \
1034 }
1035
1036 GEN_DIVE(divweu, divweu, 0);
1037 GEN_DIVE(divweuo, divweu, 1);
1038 GEN_DIVE(divwe, divwe, 0);
1039 GEN_DIVE(divweo, divwe, 1);
1040
1041 #if defined(TARGET_PPC64)
1042 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1043 TCGv arg2, int sign, int compute_ov)
1044 {
1045 int l1 = gen_new_label();
1046 int l2 = gen_new_label();
1047
1048 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1049 if (sign) {
1050 int l3 = gen_new_label();
1051 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1052 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1053 gen_set_label(l3);
1054 tcg_gen_div_i64(ret, arg1, arg2);
1055 } else {
1056 tcg_gen_divu_i64(ret, arg1, arg2);
1057 }
1058 if (compute_ov) {
1059 tcg_gen_movi_tl(cpu_ov, 0);
1060 }
1061 tcg_gen_br(l2);
1062 gen_set_label(l1);
1063 if (sign) {
1064 tcg_gen_sari_i64(ret, arg1, 63);
1065 } else {
1066 tcg_gen_movi_i64(ret, 0);
1067 }
1068 if (compute_ov) {
1069 tcg_gen_movi_tl(cpu_ov, 1);
1070 tcg_gen_movi_tl(cpu_so, 1);
1071 }
1072 gen_set_label(l2);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, ret);
1075 }
1076 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1077 static void glue(gen_, name)(DisasContext *ctx) \
1078 { \
1079 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1080 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1081 sign, compute_ov); \
1082 }
1083 /* divwu divwu. divwuo divwuo. */
1084 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1085 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1086 /* divw divw. divwo divwo. */
1087 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1088 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1089
1090 GEN_DIVE(divdeu, divdeu, 0);
1091 GEN_DIVE(divdeuo, divdeu, 1);
1092 GEN_DIVE(divde, divde, 0);
1093 GEN_DIVE(divdeo, divde, 1);
1094 #endif
1095
1096 /* mulhw mulhw. */
1097 static void gen_mulhw(DisasContext *ctx)
1098 {
1099 TCGv_i32 t0 = tcg_temp_new_i32();
1100 TCGv_i32 t1 = tcg_temp_new_i32();
1101
1102 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1103 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1104 tcg_gen_muls2_i32(t0, t1, t0, t1);
1105 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1106 tcg_temp_free_i32(t0);
1107 tcg_temp_free_i32(t1);
1108 if (unlikely(Rc(ctx->opcode) != 0))
1109 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1110 }
1111
1112 /* mulhwu mulhwu. */
1113 static void gen_mulhwu(DisasContext *ctx)
1114 {
1115 TCGv_i32 t0 = tcg_temp_new_i32();
1116 TCGv_i32 t1 = tcg_temp_new_i32();
1117
1118 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1119 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1120 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1121 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1122 tcg_temp_free_i32(t0);
1123 tcg_temp_free_i32(t1);
1124 if (unlikely(Rc(ctx->opcode) != 0))
1125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1126 }
1127
1128 /* mullw mullw. */
1129 static void gen_mullw(DisasContext *ctx)
1130 {
1131 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1132 cpu_gpr[rB(ctx->opcode)]);
1133 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1134 if (unlikely(Rc(ctx->opcode) != 0))
1135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1136 }
1137
1138 /* mullwo mullwo. */
1139 static void gen_mullwo(DisasContext *ctx)
1140 {
1141 TCGv_i32 t0 = tcg_temp_new_i32();
1142 TCGv_i32 t1 = tcg_temp_new_i32();
1143
1144 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1145 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1146 tcg_gen_muls2_i32(t0, t1, t0, t1);
1147 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1148
1149 tcg_gen_sari_i32(t0, t0, 31);
1150 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1151 tcg_gen_extu_i32_tl(cpu_ov, t0);
1152 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1153
1154 tcg_temp_free_i32(t0);
1155 tcg_temp_free_i32(t1);
1156 if (unlikely(Rc(ctx->opcode) != 0))
1157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1158 }
1159
1160 /* mulli */
1161 static void gen_mulli(DisasContext *ctx)
1162 {
1163 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1164 SIMM(ctx->opcode));
1165 }
1166
1167 #if defined(TARGET_PPC64)
1168 /* mulhd mulhd. */
1169 static void gen_mulhd(DisasContext *ctx)
1170 {
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178 }
1179
1180 /* mulhdu mulhdu. */
1181 static void gen_mulhdu(DisasContext *ctx)
1182 {
1183 TCGv lo = tcg_temp_new();
1184 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1185 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1186 tcg_temp_free(lo);
1187 if (unlikely(Rc(ctx->opcode) != 0)) {
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189 }
1190 }
1191
1192 /* mulld mulld. */
1193 static void gen_mulld(DisasContext *ctx)
1194 {
1195 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 if (unlikely(Rc(ctx->opcode) != 0))
1198 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1199 }
1200
1201 /* mulldo mulldo. */
1202 static void gen_mulldo(DisasContext *ctx)
1203 {
1204 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209 }
1210 #endif
1211
1212 /* Common subf function */
1213 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
1216 {
1217 TCGv t0 = ret;
1218
1219 if (compute_ca || compute_ov) {
1220 t0 = tcg_temp_new();
1221 }
1222
1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
1229 TCGv inv1 = tcg_temp_new();
1230 TCGv t1 = tcg_temp_new();
1231 tcg_gen_not_tl(inv1, arg1);
1232 if (add_ca) {
1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
1234 } else {
1235 tcg_gen_addi_tl(t0, arg2, 1);
1236 }
1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1238 tcg_gen_add_tl(t0, t0, inv1);
1239 tcg_temp_free(inv1);
1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1244 } else if (add_ca) {
1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1250 tcg_temp_free(zero);
1251 tcg_temp_free(inv1);
1252 } else {
1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1254 tcg_gen_sub_tl(t0, arg2, arg1);
1255 }
1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
1262 } else {
1263 tcg_gen_sub_tl(t0, arg2, arg1);
1264 }
1265
1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
1269 if (unlikely(compute_rc0)) {
1270 gen_set_Rc0(ctx, t0);
1271 }
1272
1273 if (!TCGV_EQUAL(t0, ret)) {
1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
1276 }
1277 }
1278 /* Sub functions with Two operands functions */
1279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1280 static void glue(gen_, name)(DisasContext *ctx) \
1281 { \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1285 }
1286 /* Sub functions with one operand and one immediate */
1287 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
1289 static void glue(gen_, name)(DisasContext *ctx) \
1290 { \
1291 TCGv t0 = tcg_const_tl(const_val); \
1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1295 tcg_temp_free(t0); \
1296 }
1297 /* subf subf. subfo subfo. */
1298 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300 /* subfc subfc. subfco subfco. */
1301 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303 /* subfe subfe. subfeo subfo. */
1304 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306 /* subfme subfme. subfmeo subfmeo. */
1307 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309 /* subfze subfze. subfzeo subfzeo.*/
1310 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1312
1313 /* subfic */
1314 static void gen_subfic(DisasContext *ctx)
1315 {
1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
1320 }
1321
1322 /* neg neg. nego nego. */
1323 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324 {
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329 }
1330
1331 static void gen_neg(DisasContext *ctx)
1332 {
1333 gen_op_arith_neg(ctx, 0);
1334 }
1335
1336 static void gen_nego(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 1);
1339 }
1340
1341 /*** Integer logical ***/
1342 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1343 static void glue(gen_, name)(DisasContext *ctx) \
1344 { \
1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
1347 if (unlikely(Rc(ctx->opcode) != 0)) \
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1349 }
1350
1351 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1352 static void glue(gen_, name)(DisasContext *ctx) \
1353 { \
1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1355 if (unlikely(Rc(ctx->opcode) != 0)) \
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1357 }
1358
1359 /* and & and. */
1360 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1361 /* andc & andc. */
1362 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1363
1364 /* andi. */
1365 static void gen_andi_(DisasContext *ctx)
1366 {
1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1369 }
1370
1371 /* andis. */
1372 static void gen_andis_(DisasContext *ctx)
1373 {
1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* cntlzw */
1379 static void gen_cntlzw(DisasContext *ctx)
1380 {
1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385 /* eqv & eqv. */
1386 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1387 /* extsb & extsb. */
1388 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1389 /* extsh & extsh. */
1390 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1391 /* nand & nand. */
1392 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1393 /* nor & nor. */
1394 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1395
1396 /* or & or. */
1397 static void gen_or(DisasContext *ctx)
1398 {
1399 int rs, ra, rb;
1400
1401 rs = rS(ctx->opcode);
1402 ra = rA(ctx->opcode);
1403 rb = rB(ctx->opcode);
1404 /* Optimisation for mr. ri case */
1405 if (rs != ra || rs != rb) {
1406 if (rs != rb)
1407 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1408 else
1409 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1410 if (unlikely(Rc(ctx->opcode) != 0))
1411 gen_set_Rc0(ctx, cpu_gpr[ra]);
1412 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1413 gen_set_Rc0(ctx, cpu_gpr[rs]);
1414 #if defined(TARGET_PPC64)
1415 } else {
1416 int prio = 0;
1417
1418 switch (rs) {
1419 case 1:
1420 /* Set process priority to low */
1421 prio = 2;
1422 break;
1423 case 6:
1424 /* Set process priority to medium-low */
1425 prio = 3;
1426 break;
1427 case 2:
1428 /* Set process priority to normal */
1429 prio = 4;
1430 break;
1431 #if !defined(CONFIG_USER_ONLY)
1432 case 31:
1433 if (ctx->mem_idx > 0) {
1434 /* Set process priority to very low */
1435 prio = 1;
1436 }
1437 break;
1438 case 5:
1439 if (ctx->mem_idx > 0) {
1440 /* Set process priority to medium-hight */
1441 prio = 5;
1442 }
1443 break;
1444 case 3:
1445 if (ctx->mem_idx > 0) {
1446 /* Set process priority to high */
1447 prio = 6;
1448 }
1449 break;
1450 case 7:
1451 if (ctx->mem_idx > 1) {
1452 /* Set process priority to very high */
1453 prio = 7;
1454 }
1455 break;
1456 #endif
1457 default:
1458 /* nop */
1459 break;
1460 }
1461 if (prio) {
1462 TCGv t0 = tcg_temp_new();
1463 gen_load_spr(t0, SPR_PPR);
1464 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1465 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1466 gen_store_spr(SPR_PPR, t0);
1467 tcg_temp_free(t0);
1468 }
1469 #endif
1470 }
1471 }
1472 /* orc & orc. */
1473 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1474
1475 /* xor & xor. */
1476 static void gen_xor(DisasContext *ctx)
1477 {
1478 /* Optimisation for "set to zero" case */
1479 if (rS(ctx->opcode) != rB(ctx->opcode))
1480 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1481 else
1482 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485 }
1486
1487 /* ori */
1488 static void gen_ori(DisasContext *ctx)
1489 {
1490 target_ulong uimm = UIMM(ctx->opcode);
1491
1492 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1493 /* NOP */
1494 /* XXX: should handle special NOPs for POWER series */
1495 return;
1496 }
1497 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1498 }
1499
1500 /* oris */
1501 static void gen_oris(DisasContext *ctx)
1502 {
1503 target_ulong uimm = UIMM(ctx->opcode);
1504
1505 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1506 /* NOP */
1507 return;
1508 }
1509 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1510 }
1511
1512 /* xori */
1513 static void gen_xori(DisasContext *ctx)
1514 {
1515 target_ulong uimm = UIMM(ctx->opcode);
1516
1517 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1518 /* NOP */
1519 return;
1520 }
1521 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1522 }
1523
1524 /* xoris */
1525 static void gen_xoris(DisasContext *ctx)
1526 {
1527 target_ulong uimm = UIMM(ctx->opcode);
1528
1529 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1530 /* NOP */
1531 return;
1532 }
1533 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1534 }
1535
1536 /* popcntb : PowerPC 2.03 specification */
1537 static void gen_popcntb(DisasContext *ctx)
1538 {
1539 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1540 }
1541
1542 static void gen_popcntw(DisasContext *ctx)
1543 {
1544 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 }
1546
1547 #if defined(TARGET_PPC64)
1548 /* popcntd: PowerPC 2.06 specification */
1549 static void gen_popcntd(DisasContext *ctx)
1550 {
1551 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1552 }
1553 #endif
1554
1555 /* prtyw: PowerPC 2.05 specification */
1556 static void gen_prtyw(DisasContext *ctx)
1557 {
1558 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1559 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1560 TCGv t0 = tcg_temp_new();
1561 tcg_gen_shri_tl(t0, rs, 16);
1562 tcg_gen_xor_tl(ra, rs, t0);
1563 tcg_gen_shri_tl(t0, ra, 8);
1564 tcg_gen_xor_tl(ra, ra, t0);
1565 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1566 tcg_temp_free(t0);
1567 }
1568
1569 #if defined(TARGET_PPC64)
1570 /* prtyd: PowerPC 2.05 specification */
1571 static void gen_prtyd(DisasContext *ctx)
1572 {
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 32);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 16);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_shri_tl(t0, ra, 8);
1581 tcg_gen_xor_tl(ra, ra, t0);
1582 tcg_gen_andi_tl(ra, ra, 1);
1583 tcg_temp_free(t0);
1584 }
1585 #endif
1586
1587 #if defined(TARGET_PPC64)
1588 /* bpermd */
1589 static void gen_bpermd(DisasContext *ctx)
1590 {
1591 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1592 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1593 }
1594 #endif
1595
1596 #if defined(TARGET_PPC64)
1597 /* extsw & extsw. */
1598 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1599
1600 /* cntlzd */
1601 static void gen_cntlzd(DisasContext *ctx)
1602 {
1603 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1604 if (unlikely(Rc(ctx->opcode) != 0))
1605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1606 }
1607 #endif
1608
1609 /*** Integer rotate ***/
1610
1611 /* rlwimi & rlwimi. */
1612 static void gen_rlwimi(DisasContext *ctx)
1613 {
1614 uint32_t mb, me, sh;
1615
1616 mb = MB(ctx->opcode);
1617 me = ME(ctx->opcode);
1618 sh = SH(ctx->opcode);
1619 if (likely(sh == 0 && mb == 0 && me == 31)) {
1620 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1621 } else {
1622 target_ulong mask;
1623 TCGv t1;
1624 TCGv t0 = tcg_temp_new();
1625 #if defined(TARGET_PPC64)
1626 TCGv_i32 t2 = tcg_temp_new_i32();
1627 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1628 tcg_gen_rotli_i32(t2, t2, sh);
1629 tcg_gen_extu_i32_i64(t0, t2);
1630 tcg_temp_free_i32(t2);
1631 #else
1632 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1633 #endif
1634 #if defined(TARGET_PPC64)
1635 mb += 32;
1636 me += 32;
1637 #endif
1638 mask = MASK(mb, me);
1639 t1 = tcg_temp_new();
1640 tcg_gen_andi_tl(t0, t0, mask);
1641 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1642 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1643 tcg_temp_free(t0);
1644 tcg_temp_free(t1);
1645 }
1646 if (unlikely(Rc(ctx->opcode) != 0))
1647 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1648 }
1649
1650 /* rlwinm & rlwinm. */
1651 static void gen_rlwinm(DisasContext *ctx)
1652 {
1653 uint32_t mb, me, sh;
1654
1655 sh = SH(ctx->opcode);
1656 mb = MB(ctx->opcode);
1657 me = ME(ctx->opcode);
1658
1659 if (likely(mb == 0 && me == (31 - sh))) {
1660 if (likely(sh == 0)) {
1661 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1662 } else {
1663 TCGv t0 = tcg_temp_new();
1664 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1665 tcg_gen_shli_tl(t0, t0, sh);
1666 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1667 tcg_temp_free(t0);
1668 }
1669 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1670 TCGv t0 = tcg_temp_new();
1671 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_shri_tl(t0, t0, mb);
1673 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1674 tcg_temp_free(t0);
1675 } else {
1676 TCGv t0 = tcg_temp_new();
1677 #if defined(TARGET_PPC64)
1678 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1679 cpu_gpr[rS(ctx->opcode)], 32, 32);
1680 tcg_gen_rotli_i64(t0, t0, sh);
1681 #else
1682 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1683 #endif
1684 #if defined(TARGET_PPC64)
1685 mb += 32;
1686 me += 32;
1687 #endif
1688 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1689 tcg_temp_free(t0);
1690 }
1691 if (unlikely(Rc(ctx->opcode) != 0))
1692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1693 }
1694
1695 /* rlwnm & rlwnm. */
1696 static void gen_rlwnm(DisasContext *ctx)
1697 {
1698 uint32_t mb, me;
1699 TCGv t0;
1700 #if defined(TARGET_PPC64)
1701 TCGv t1;
1702 #endif
1703
1704 mb = MB(ctx->opcode);
1705 me = ME(ctx->opcode);
1706 t0 = tcg_temp_new();
1707 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1708 #if defined(TARGET_PPC64)
1709 t1 = tcg_temp_new_i64();
1710 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1711 cpu_gpr[rS(ctx->opcode)], 32, 32);
1712 tcg_gen_rotl_i64(t0, t1, t0);
1713 tcg_temp_free_i64(t1);
1714 #else
1715 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1716 #endif
1717 if (unlikely(mb != 0 || me != 31)) {
1718 #if defined(TARGET_PPC64)
1719 mb += 32;
1720 me += 32;
1721 #endif
1722 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1723 } else {
1724 #if defined(TARGET_PPC64)
1725 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1726 #endif
1727 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1728 }
1729 tcg_temp_free(t0);
1730 if (unlikely(Rc(ctx->opcode) != 0))
1731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1732 }
1733
1734 #if defined(TARGET_PPC64)
1735 #define GEN_PPC64_R2(name, opc1, opc2) \
1736 static void glue(gen_, name##0)(DisasContext *ctx) \
1737 { \
1738 gen_##name(ctx, 0); \
1739 } \
1740 \
1741 static void glue(gen_, name##1)(DisasContext *ctx) \
1742 { \
1743 gen_##name(ctx, 1); \
1744 }
1745 #define GEN_PPC64_R4(name, opc1, opc2) \
1746 static void glue(gen_, name##0)(DisasContext *ctx) \
1747 { \
1748 gen_##name(ctx, 0, 0); \
1749 } \
1750 \
1751 static void glue(gen_, name##1)(DisasContext *ctx) \
1752 { \
1753 gen_##name(ctx, 0, 1); \
1754 } \
1755 \
1756 static void glue(gen_, name##2)(DisasContext *ctx) \
1757 { \
1758 gen_##name(ctx, 1, 0); \
1759 } \
1760 \
1761 static void glue(gen_, name##3)(DisasContext *ctx) \
1762 { \
1763 gen_##name(ctx, 1, 1); \
1764 }
1765
1766 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1767 uint32_t sh)
1768 {
1769 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1770 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1771 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1772 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1773 } else {
1774 TCGv t0 = tcg_temp_new();
1775 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1776 if (likely(mb == 0 && me == 63)) {
1777 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1778 } else {
1779 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1780 }
1781 tcg_temp_free(t0);
1782 }
1783 if (unlikely(Rc(ctx->opcode) != 0))
1784 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1785 }
1786 /* rldicl - rldicl. */
1787 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1788 {
1789 uint32_t sh, mb;
1790
1791 sh = SH(ctx->opcode) | (shn << 5);
1792 mb = MB(ctx->opcode) | (mbn << 5);
1793 gen_rldinm(ctx, mb, 63, sh);
1794 }
1795 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1796 /* rldicr - rldicr. */
1797 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1798 {
1799 uint32_t sh, me;
1800
1801 sh = SH(ctx->opcode) | (shn << 5);
1802 me = MB(ctx->opcode) | (men << 5);
1803 gen_rldinm(ctx, 0, me, sh);
1804 }
1805 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1806 /* rldic - rldic. */
1807 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1808 {
1809 uint32_t sh, mb;
1810
1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
1813 gen_rldinm(ctx, mb, 63 - sh, sh);
1814 }
1815 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1816
1817 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1818 {
1819 TCGv t0;
1820
1821 t0 = tcg_temp_new();
1822 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1823 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1824 if (unlikely(mb != 0 || me != 63)) {
1825 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1826 } else {
1827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1828 }
1829 tcg_temp_free(t0);
1830 if (unlikely(Rc(ctx->opcode) != 0))
1831 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1832 }
1833
1834 /* rldcl - rldcl. */
1835 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1836 {
1837 uint32_t mb;
1838
1839 mb = MB(ctx->opcode) | (mbn << 5);
1840 gen_rldnm(ctx, mb, 63);
1841 }
1842 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1843 /* rldcr - rldcr. */
1844 static inline void gen_rldcr(DisasContext *ctx, int men)
1845 {
1846 uint32_t me;
1847
1848 me = MB(ctx->opcode) | (men << 5);
1849 gen_rldnm(ctx, 0, me);
1850 }
1851 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1852 /* rldimi - rldimi. */
1853 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1854 {
1855 uint32_t sh, mb, me;
1856
1857 sh = SH(ctx->opcode) | (shn << 5);
1858 mb = MB(ctx->opcode) | (mbn << 5);
1859 me = 63 - sh;
1860 if (unlikely(sh == 0 && mb == 0)) {
1861 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1862 } else {
1863 TCGv t0, t1;
1864 target_ulong mask;
1865
1866 t0 = tcg_temp_new();
1867 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1868 t1 = tcg_temp_new();
1869 mask = MASK(mb, me);
1870 tcg_gen_andi_tl(t0, t0, mask);
1871 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1872 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1873 tcg_temp_free(t0);
1874 tcg_temp_free(t1);
1875 }
1876 if (unlikely(Rc(ctx->opcode) != 0))
1877 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1878 }
1879 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1880 #endif
1881
1882 /*** Integer shift ***/
1883
1884 /* slw & slw. */
1885 static void gen_slw(DisasContext *ctx)
1886 {
1887 TCGv t0, t1;
1888
1889 t0 = tcg_temp_new();
1890 /* AND rS with a mask that is 0 when rB >= 0x20 */
1891 #if defined(TARGET_PPC64)
1892 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1893 tcg_gen_sari_tl(t0, t0, 0x3f);
1894 #else
1895 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1896 tcg_gen_sari_tl(t0, t0, 0x1f);
1897 #endif
1898 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1899 t1 = tcg_temp_new();
1900 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1901 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1902 tcg_temp_free(t1);
1903 tcg_temp_free(t0);
1904 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1905 if (unlikely(Rc(ctx->opcode) != 0))
1906 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1907 }
1908
1909 /* sraw & sraw. */
1910 static void gen_sraw(DisasContext *ctx)
1911 {
1912 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1913 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1914 if (unlikely(Rc(ctx->opcode) != 0))
1915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1916 }
1917
1918 /* srawi & srawi. */
1919 static void gen_srawi(DisasContext *ctx)
1920 {
1921 int sh = SH(ctx->opcode);
1922 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1923 TCGv src = cpu_gpr[rS(ctx->opcode)];
1924 if (sh == 0) {
1925 tcg_gen_mov_tl(dst, src);
1926 tcg_gen_movi_tl(cpu_ca, 0);
1927 } else {
1928 TCGv t0;
1929 tcg_gen_ext32s_tl(dst, src);
1930 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1931 t0 = tcg_temp_new();
1932 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1933 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1934 tcg_temp_free(t0);
1935 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1936 tcg_gen_sari_tl(dst, dst, sh);
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, dst);
1940 }
1941 }
1942
1943 /* srw & srw. */
1944 static void gen_srw(DisasContext *ctx)
1945 {
1946 TCGv t0, t1;
1947
1948 t0 = tcg_temp_new();
1949 /* AND rS with a mask that is 0 when rB >= 0x20 */
1950 #if defined(TARGET_PPC64)
1951 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1952 tcg_gen_sari_tl(t0, t0, 0x3f);
1953 #else
1954 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1955 tcg_gen_sari_tl(t0, t0, 0x1f);
1956 #endif
1957 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1958 tcg_gen_ext32u_tl(t0, t0);
1959 t1 = tcg_temp_new();
1960 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1961 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1962 tcg_temp_free(t1);
1963 tcg_temp_free(t0);
1964 if (unlikely(Rc(ctx->opcode) != 0))
1965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966 }
1967
1968 #if defined(TARGET_PPC64)
1969 /* sld & sld. */
1970 static void gen_sld(DisasContext *ctx)
1971 {
1972 TCGv t0, t1;
1973
1974 t0 = tcg_temp_new();
1975 /* AND rS with a mask that is 0 when rB >= 0x40 */
1976 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1977 tcg_gen_sari_tl(t0, t0, 0x3f);
1978 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1979 t1 = tcg_temp_new();
1980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1981 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1982 tcg_temp_free(t1);
1983 tcg_temp_free(t0);
1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986 }
1987
1988 /* srad & srad. */
1989 static void gen_srad(DisasContext *ctx)
1990 {
1991 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1992 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995 }
1996 /* sradi & sradi. */
1997 static inline void gen_sradi(DisasContext *ctx, int n)
1998 {
1999 int sh = SH(ctx->opcode) + (n << 5);
2000 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2001 TCGv src = cpu_gpr[rS(ctx->opcode)];
2002 if (sh == 0) {
2003 tcg_gen_mov_tl(dst, src);
2004 tcg_gen_movi_tl(cpu_ca, 0);
2005 } else {
2006 TCGv t0;
2007 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2008 t0 = tcg_temp_new();
2009 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2010 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2011 tcg_temp_free(t0);
2012 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2013 tcg_gen_sari_tl(dst, src, sh);
2014 }
2015 if (unlikely(Rc(ctx->opcode) != 0)) {
2016 gen_set_Rc0(ctx, dst);
2017 }
2018 }
2019
2020 static void gen_sradi0(DisasContext *ctx)
2021 {
2022 gen_sradi(ctx, 0);
2023 }
2024
2025 static void gen_sradi1(DisasContext *ctx)
2026 {
2027 gen_sradi(ctx, 1);
2028 }
2029
2030 /* srd & srd. */
2031 static void gen_srd(DisasContext *ctx)
2032 {
2033 TCGv t0, t1;
2034
2035 t0 = tcg_temp_new();
2036 /* AND rS with a mask that is 0 when rB >= 0x40 */
2037 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2038 tcg_gen_sari_tl(t0, t0, 0x3f);
2039 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2040 t1 = tcg_temp_new();
2041 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2042 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2043 tcg_temp_free(t1);
2044 tcg_temp_free(t0);
2045 if (unlikely(Rc(ctx->opcode) != 0))
2046 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2047 }
2048 #endif
2049
2050 /*** Floating-Point arithmetic ***/
2051 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2052 static void gen_f##name(DisasContext *ctx) \
2053 { \
2054 if (unlikely(!ctx->fpu_enabled)) { \
2055 gen_exception(ctx, POWERPC_EXCP_FPU); \
2056 return; \
2057 } \
2058 /* NIP cannot be restored if the memory exception comes from an helper */ \
2059 gen_update_nip(ctx, ctx->nip - 4); \
2060 gen_reset_fpstatus(); \
2061 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2062 cpu_fpr[rA(ctx->opcode)], \
2063 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2064 if (isfloat) { \
2065 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2066 cpu_fpr[rD(ctx->opcode)]); \
2067 } \
2068 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2069 Rc(ctx->opcode) != 0); \
2070 }
2071
2072 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2073 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2074 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2075
2076 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2077 static void gen_f##name(DisasContext *ctx) \
2078 { \
2079 if (unlikely(!ctx->fpu_enabled)) { \
2080 gen_exception(ctx, POWERPC_EXCP_FPU); \
2081 return; \
2082 } \
2083 /* NIP cannot be restored if the memory exception comes from an helper */ \
2084 gen_update_nip(ctx, ctx->nip - 4); \
2085 gen_reset_fpstatus(); \
2086 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2087 cpu_fpr[rA(ctx->opcode)], \
2088 cpu_fpr[rB(ctx->opcode)]); \
2089 if (isfloat) { \
2090 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2091 cpu_fpr[rD(ctx->opcode)]); \
2092 } \
2093 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2094 set_fprf, Rc(ctx->opcode) != 0); \
2095 }
2096 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2097 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2098 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2099
2100 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2101 static void gen_f##name(DisasContext *ctx) \
2102 { \
2103 if (unlikely(!ctx->fpu_enabled)) { \
2104 gen_exception(ctx, POWERPC_EXCP_FPU); \
2105 return; \
2106 } \
2107 /* NIP cannot be restored if the memory exception comes from an helper */ \
2108 gen_update_nip(ctx, ctx->nip - 4); \
2109 gen_reset_fpstatus(); \
2110 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2111 cpu_fpr[rA(ctx->opcode)], \
2112 cpu_fpr[rC(ctx->opcode)]); \
2113 if (isfloat) { \
2114 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2115 cpu_fpr[rD(ctx->opcode)]); \
2116 } \
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2118 set_fprf, Rc(ctx->opcode) != 0); \
2119 }
2120 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2121 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2123
2124 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2125 static void gen_f##name(DisasContext *ctx) \
2126 { \
2127 if (unlikely(!ctx->fpu_enabled)) { \
2128 gen_exception(ctx, POWERPC_EXCP_FPU); \
2129 return; \
2130 } \
2131 /* NIP cannot be restored if the memory exception comes from an helper */ \
2132 gen_update_nip(ctx, ctx->nip - 4); \
2133 gen_reset_fpstatus(); \
2134 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2135 cpu_fpr[rB(ctx->opcode)]); \
2136 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2137 set_fprf, Rc(ctx->opcode) != 0); \
2138 }
2139
2140 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2141 static void gen_f##name(DisasContext *ctx) \
2142 { \
2143 if (unlikely(!ctx->fpu_enabled)) { \
2144 gen_exception(ctx, POWERPC_EXCP_FPU); \
2145 return; \
2146 } \
2147 /* NIP cannot be restored if the memory exception comes from an helper */ \
2148 gen_update_nip(ctx, ctx->nip - 4); \
2149 gen_reset_fpstatus(); \
2150 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2151 cpu_fpr[rB(ctx->opcode)]); \
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2153 set_fprf, Rc(ctx->opcode) != 0); \
2154 }
2155
2156 /* fadd - fadds */
2157 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2158 /* fdiv - fdivs */
2159 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2160 /* fmul - fmuls */
2161 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2162
2163 /* fre */
2164 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2165
2166 /* fres */
2167 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2168
2169 /* frsqrte */
2170 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2171
2172 /* frsqrtes */
2173 static void gen_frsqrtes(DisasContext *ctx)
2174 {
2175 if (unlikely(!ctx->fpu_enabled)) {
2176 gen_exception(ctx, POWERPC_EXCP_FPU);
2177 return;
2178 }
2179 /* NIP cannot be restored if the memory exception comes from an helper */
2180 gen_update_nip(ctx, ctx->nip - 4);
2181 gen_reset_fpstatus();
2182 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2183 cpu_fpr[rB(ctx->opcode)]);
2184 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2185 cpu_fpr[rD(ctx->opcode)]);
2186 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2187 }
2188
2189 /* fsel */
2190 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2191 /* fsub - fsubs */
2192 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2193 /* Optional: */
2194
2195 /* fsqrt */
2196 static void gen_fsqrt(DisasContext *ctx)
2197 {
2198 if (unlikely(!ctx->fpu_enabled)) {
2199 gen_exception(ctx, POWERPC_EXCP_FPU);
2200 return;
2201 }
2202 /* NIP cannot be restored if the memory exception comes from an helper */
2203 gen_update_nip(ctx, ctx->nip - 4);
2204 gen_reset_fpstatus();
2205 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2206 cpu_fpr[rB(ctx->opcode)]);
2207 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2208 }
2209
2210 static void gen_fsqrts(DisasContext *ctx)
2211 {
2212 if (unlikely(!ctx->fpu_enabled)) {
2213 gen_exception(ctx, POWERPC_EXCP_FPU);
2214 return;
2215 }
2216 /* NIP cannot be restored if the memory exception comes from an helper */
2217 gen_update_nip(ctx, ctx->nip - 4);
2218 gen_reset_fpstatus();
2219 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2220 cpu_fpr[rB(ctx->opcode)]);
2221 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2222 cpu_fpr[rD(ctx->opcode)]);
2223 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2224 }
2225
2226 /*** Floating-Point multiply-and-add ***/
2227 /* fmadd - fmadds */
2228 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2229 /* fmsub - fmsubs */
2230 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2231 /* fnmadd - fnmadds */
2232 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2233 /* fnmsub - fnmsubs */
2234 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2235
2236 /*** Floating-Point round & convert ***/
2237 /* fctiw */
2238 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2239 /* fctiwu */
2240 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2241 /* fctiwz */
2242 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2243 /* fctiwuz */
2244 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2245 /* frsp */
2246 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2247 #if defined(TARGET_PPC64)
2248 /* fcfid */
2249 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2250 /* fcfids */
2251 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2252 /* fcfidu */
2253 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2254 /* fcfidus */
2255 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2256 /* fctid */
2257 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2258 /* fctidu */
2259 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2260 /* fctidz */
2261 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2262 /* fctidu */
2263 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2264 #endif
2265
2266 /* frin */
2267 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2268 /* friz */
2269 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2270 /* frip */
2271 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2272 /* frim */
2273 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2274
2275 static void gen_ftdiv(DisasContext *ctx)
2276 {
2277 if (unlikely(!ctx->fpu_enabled)) {
2278 gen_exception(ctx, POWERPC_EXCP_FPU);
2279 return;
2280 }
2281 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2282 cpu_fpr[rB(ctx->opcode)]);
2283 }
2284
2285 static void gen_ftsqrt(DisasContext *ctx)
2286 {
2287 if (unlikely(!ctx->fpu_enabled)) {
2288 gen_exception(ctx, POWERPC_EXCP_FPU);
2289 return;
2290 }
2291 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2292 }
2293
2294
2295
2296 /*** Floating-Point compare ***/
2297
2298 /* fcmpo */
2299 static void gen_fcmpo(DisasContext *ctx)
2300 {
2301 TCGv_i32 crf;
2302 if (unlikely(!ctx->fpu_enabled)) {
2303 gen_exception(ctx, POWERPC_EXCP_FPU);
2304 return;
2305 }
2306 /* NIP cannot be restored if the memory exception comes from an helper */
2307 gen_update_nip(ctx, ctx->nip - 4);
2308 gen_reset_fpstatus();
2309 crf = tcg_const_i32(crfD(ctx->opcode));
2310 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2311 cpu_fpr[rB(ctx->opcode)], crf);
2312 tcg_temp_free_i32(crf);
2313 gen_helper_float_check_status(cpu_env);
2314 }
2315
2316 /* fcmpu */
2317 static void gen_fcmpu(DisasContext *ctx)
2318 {
2319 TCGv_i32 crf;
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 /* NIP cannot be restored if the memory exception comes from an helper */
2325 gen_update_nip(ctx, ctx->nip - 4);
2326 gen_reset_fpstatus();
2327 crf = tcg_const_i32(crfD(ctx->opcode));
2328 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2329 cpu_fpr[rB(ctx->opcode)], crf);
2330 tcg_temp_free_i32(crf);
2331 gen_helper_float_check_status(cpu_env);
2332 }
2333
2334 /*** Floating-point move ***/
2335 /* fabs */
2336 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2337 static void gen_fabs(DisasContext *ctx)
2338 {
2339 if (unlikely(!ctx->fpu_enabled)) {
2340 gen_exception(ctx, POWERPC_EXCP_FPU);
2341 return;
2342 }
2343 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2344 ~(1ULL << 63));
2345 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2346 }
2347
2348 /* fmr - fmr. */
2349 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2350 static void gen_fmr(DisasContext *ctx)
2351 {
2352 if (unlikely(!ctx->fpu_enabled)) {
2353 gen_exception(ctx, POWERPC_EXCP_FPU);
2354 return;
2355 }
2356 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2357 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2358 }
2359
2360 /* fnabs */
2361 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2362 static void gen_fnabs(DisasContext *ctx)
2363 {
2364 if (unlikely(!ctx->fpu_enabled)) {
2365 gen_exception(ctx, POWERPC_EXCP_FPU);
2366 return;
2367 }
2368 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2369 1ULL << 63);
2370 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2371 }
2372
2373 /* fneg */
2374 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2375 static void gen_fneg(DisasContext *ctx)
2376 {
2377 if (unlikely(!ctx->fpu_enabled)) {
2378 gen_exception(ctx, POWERPC_EXCP_FPU);
2379 return;
2380 }
2381 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2382 1ULL << 63);
2383 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2384 }
2385
2386 /* fcpsgn: PowerPC 2.05 specification */
2387 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2388 static void gen_fcpsgn(DisasContext *ctx)
2389 {
2390 if (unlikely(!ctx->fpu_enabled)) {
2391 gen_exception(ctx, POWERPC_EXCP_FPU);
2392 return;
2393 }
2394 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2395 cpu_fpr[rB(ctx->opcode)], 0, 63);
2396 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2397 }
2398
2399 static void gen_fmrgew(DisasContext *ctx)
2400 {
2401 TCGv_i64 b0;
2402 if (unlikely(!ctx->fpu_enabled)) {
2403 gen_exception(ctx, POWERPC_EXCP_FPU);
2404 return;
2405 }
2406 b0 = tcg_temp_new_i64();
2407 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2408 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2409 b0, 0, 32);
2410 tcg_temp_free_i64(b0);
2411 }
2412
2413 static void gen_fmrgow(DisasContext *ctx)
2414 {
2415 if (unlikely(!ctx->fpu_enabled)) {
2416 gen_exception(ctx, POWERPC_EXCP_FPU);
2417 return;
2418 }
2419 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2420 cpu_fpr[rB(ctx->opcode)],
2421 cpu_fpr[rA(ctx->opcode)],
2422 32, 32);
2423 }
2424
2425 /*** Floating-Point status & ctrl register ***/
2426
2427 /* mcrfs */
2428 static void gen_mcrfs(DisasContext *ctx)
2429 {
2430 TCGv tmp = tcg_temp_new();
2431 int bfa;
2432
2433 if (unlikely(!ctx->fpu_enabled)) {
2434 gen_exception(ctx, POWERPC_EXCP_FPU);
2435 return;
2436 }
2437 bfa = 4 * (7 - crfS(ctx->opcode));
2438 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2439 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2440 tcg_temp_free(tmp);
2441 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2442 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2443 }
2444
2445 /* mffs */
2446 static void gen_mffs(DisasContext *ctx)
2447 {
2448 if (unlikely(!ctx->fpu_enabled)) {
2449 gen_exception(ctx, POWERPC_EXCP_FPU);
2450 return;
2451 }
2452 gen_reset_fpstatus();
2453 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2454 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2455 }
2456
2457 /* mtfsb0 */
2458 static void gen_mtfsb0(DisasContext *ctx)
2459 {
2460 uint8_t crb;
2461
2462 if (unlikely(!ctx->fpu_enabled)) {
2463 gen_exception(ctx, POWERPC_EXCP_FPU);
2464 return;
2465 }
2466 crb = 31 - crbD(ctx->opcode);
2467 gen_reset_fpstatus();
2468 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2469 TCGv_i32 t0;
2470 /* NIP cannot be restored if the memory exception comes from an helper */
2471 gen_update_nip(ctx, ctx->nip - 4);
2472 t0 = tcg_const_i32(crb);
2473 gen_helper_fpscr_clrbit(cpu_env, t0);
2474 tcg_temp_free_i32(t0);
2475 }
2476 if (unlikely(Rc(ctx->opcode) != 0)) {
2477 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2478 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2479 }
2480 }
2481
2482 /* mtfsb1 */
2483 static void gen_mtfsb1(DisasContext *ctx)
2484 {
2485 uint8_t crb;
2486
2487 if (unlikely(!ctx->fpu_enabled)) {
2488 gen_exception(ctx, POWERPC_EXCP_FPU);
2489 return;
2490 }
2491 crb = 31 - crbD(ctx->opcode);
2492 gen_reset_fpstatus();
2493 /* XXX: we pretend we can only do IEEE floating-point computations */
2494 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2495 TCGv_i32 t0;
2496 /* NIP cannot be restored if the memory exception comes from an helper */
2497 gen_update_nip(ctx, ctx->nip - 4);
2498 t0 = tcg_const_i32(crb);
2499 gen_helper_fpscr_setbit(cpu_env, t0);
2500 tcg_temp_free_i32(t0);
2501 }
2502 if (unlikely(Rc(ctx->opcode) != 0)) {
2503 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2504 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2505 }
2506 /* We can raise a differed exception */
2507 gen_helper_float_check_status(cpu_env);
2508 }
2509
2510 /* mtfsf */
2511 static void gen_mtfsf(DisasContext *ctx)
2512 {
2513 TCGv_i32 t0;
2514 int flm, l, w;
2515
2516 if (unlikely(!ctx->fpu_enabled)) {
2517 gen_exception(ctx, POWERPC_EXCP_FPU);
2518 return;
2519 }
2520 flm = FPFLM(ctx->opcode);
2521 l = FPL(ctx->opcode);
2522 w = FPW(ctx->opcode);
2523 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2524 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2525 return;
2526 }
2527 /* NIP cannot be restored if the memory exception comes from an helper */
2528 gen_update_nip(ctx, ctx->nip - 4);
2529 gen_reset_fpstatus();
2530 if (l) {
2531 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2532 } else {
2533 t0 = tcg_const_i32(flm << (w * 8));
2534 }
2535 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2536 tcg_temp_free_i32(t0);
2537 if (unlikely(Rc(ctx->opcode) != 0)) {
2538 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2539 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2540 }
2541 /* We can raise a differed exception */
2542 gen_helper_float_check_status(cpu_env);
2543 }
2544
2545 /* mtfsfi */
2546 static void gen_mtfsfi(DisasContext *ctx)
2547 {
2548 int bf, sh, w;
2549 TCGv_i64 t0;
2550 TCGv_i32 t1;
2551
2552 if (unlikely(!ctx->fpu_enabled)) {
2553 gen_exception(ctx, POWERPC_EXCP_FPU);
2554 return;
2555 }
2556 w = FPW(ctx->opcode);
2557 bf = FPBF(ctx->opcode);
2558 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2559 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2560 return;
2561 }
2562 sh = (8 * w) + 7 - bf;
2563 /* NIP cannot be restored if the memory exception comes from an helper */
2564 gen_update_nip(ctx, ctx->nip - 4);
2565 gen_reset_fpstatus();
2566 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2567 t1 = tcg_const_i32(1 << sh);
2568 gen_helper_store_fpscr(cpu_env, t0, t1);
2569 tcg_temp_free_i64(t0);
2570 tcg_temp_free_i32(t1);
2571 if (unlikely(Rc(ctx->opcode) != 0)) {
2572 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2573 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2574 }
2575 /* We can raise a differed exception */
2576 gen_helper_float_check_status(cpu_env);
2577 }
2578
2579 /*** Addressing modes ***/
2580 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2581 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2582 target_long maskl)
2583 {
2584 target_long simm = SIMM(ctx->opcode);
2585
2586 simm &= ~maskl;
2587 if (rA(ctx->opcode) == 0) {
2588 if (NARROW_MODE(ctx)) {
2589 simm = (uint32_t)simm;
2590 }
2591 tcg_gen_movi_tl(EA, simm);
2592 } else if (likely(simm != 0)) {
2593 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2594 if (NARROW_MODE(ctx)) {
2595 tcg_gen_ext32u_tl(EA, EA);
2596 }
2597 } else {
2598 if (NARROW_MODE(ctx)) {
2599 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2600 } else {
2601 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2602 }
2603 }
2604 }
2605
2606 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2607 {
2608 if (rA(ctx->opcode) == 0) {
2609 if (NARROW_MODE(ctx)) {
2610 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2611 } else {
2612 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2613 }
2614 } else {
2615 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2616 if (NARROW_MODE(ctx)) {
2617 tcg_gen_ext32u_tl(EA, EA);
2618 }
2619 }
2620 }
2621
2622 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2623 {
2624 if (rA(ctx->opcode) == 0) {
2625 tcg_gen_movi_tl(EA, 0);
2626 } else if (NARROW_MODE(ctx)) {
2627 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2628 } else {
2629 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2630 }
2631 }
2632
2633 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2634 target_long val)
2635 {
2636 tcg_gen_addi_tl(ret, arg1, val);
2637 if (NARROW_MODE(ctx)) {
2638 tcg_gen_ext32u_tl(ret, ret);
2639 }
2640 }
2641
2642 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2643 {
2644 int l1 = gen_new_label();
2645 TCGv t0 = tcg_temp_new();
2646 TCGv_i32 t1, t2;
2647 /* NIP cannot be restored if the memory exception comes from an helper */
2648 gen_update_nip(ctx, ctx->nip - 4);
2649 tcg_gen_andi_tl(t0, EA, mask);
2650 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2651 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2652 t2 = tcg_const_i32(0);
2653 gen_helper_raise_exception_err(cpu_env, t1, t2);
2654 tcg_temp_free_i32(t1);
2655 tcg_temp_free_i32(t2);
2656 gen_set_label(l1);
2657 tcg_temp_free(t0);
2658 }
2659
2660 /*** Integer load ***/
2661 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2662 {
2663 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2664 }
2665
2666 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2667 {
2668 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2669 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2670 }
2671
2672 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2673 {
2674 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2675 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2676 }
2677
2678 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2679 {
2680 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2681 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2682 }
2683
2684 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2685 {
2686 TCGv tmp = tcg_temp_new();
2687 gen_qemu_ld32u(ctx, tmp, addr);
2688 tcg_gen_extu_tl_i64(val, tmp);
2689 tcg_temp_free(tmp);
2690 }
2691
2692 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2693 {
2694 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2695 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2696 }
2697
2698 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2699 {
2700 TCGv tmp = tcg_temp_new();
2701 gen_qemu_ld32s(ctx, tmp, addr);
2702 tcg_gen_ext_tl_i64(val, tmp);
2703 tcg_temp_free(tmp);
2704 }
2705
2706 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2707 {
2708 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2709 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2710 }
2711
2712 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2713 {
2714 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2715 }
2716
2717 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2718 {
2719 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2720 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2721 }
2722
2723 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2724 {
2725 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2726 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2727 }
2728
2729 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2730 {
2731 TCGv tmp = tcg_temp_new();
2732 tcg_gen_trunc_i64_tl(tmp, val);
2733 gen_qemu_st32(ctx, tmp, addr);
2734 tcg_temp_free(tmp);
2735 }
2736
2737 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2738 {
2739 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2740 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2741 }
2742
2743 #define GEN_LD(name, ldop, opc, type) \
2744 static void glue(gen_, name)(DisasContext *ctx) \
2745 { \
2746 TCGv EA; \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_imm_index(ctx, EA, 0); \
2750 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2751 tcg_temp_free(EA); \
2752 }
2753
2754 #define GEN_LDU(name, ldop, opc, type) \
2755 static void glue(gen_, name##u)(DisasContext *ctx) \
2756 { \
2757 TCGv EA; \
2758 if (unlikely(rA(ctx->opcode) == 0 || \
2759 rA(ctx->opcode) == rD(ctx->opcode))) { \
2760 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2761 return; \
2762 } \
2763 gen_set_access_type(ctx, ACCESS_INT); \
2764 EA = tcg_temp_new(); \
2765 if (type == PPC_64B) \
2766 gen_addr_imm_index(ctx, EA, 0x03); \
2767 else \
2768 gen_addr_imm_index(ctx, EA, 0); \
2769 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2771 tcg_temp_free(EA); \
2772 }
2773
2774 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2775 static void glue(gen_, name##ux)(DisasContext *ctx) \
2776 { \
2777 TCGv EA; \
2778 if (unlikely(rA(ctx->opcode) == 0 || \
2779 rA(ctx->opcode) == rD(ctx->opcode))) { \
2780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2781 return; \
2782 } \
2783 gen_set_access_type(ctx, ACCESS_INT); \
2784 EA = tcg_temp_new(); \
2785 gen_addr_reg_index(ctx, EA); \
2786 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2788 tcg_temp_free(EA); \
2789 }
2790
2791 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2792 static void glue(gen_, name##x)(DisasContext *ctx) \
2793 { \
2794 TCGv EA; \
2795 gen_set_access_type(ctx, ACCESS_INT); \
2796 EA = tcg_temp_new(); \
2797 gen_addr_reg_index(ctx, EA); \
2798 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2799 tcg_temp_free(EA); \
2800 }
2801 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2802 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2803
2804 #define GEN_LDS(name, ldop, op, type) \
2805 GEN_LD(name, ldop, op | 0x20, type); \
2806 GEN_LDU(name, ldop, op | 0x21, type); \
2807 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2808 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2809
2810 /* lbz lbzu lbzux lbzx */
2811 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2812 /* lha lhau lhaux lhax */
2813 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2814 /* lhz lhzu lhzux lhzx */
2815 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2816 /* lwz lwzu lwzux lwzx */
2817 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2818 #if defined(TARGET_PPC64)
2819 /* lwaux */
2820 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2821 /* lwax */
2822 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2823 /* ldux */
2824 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2825 /* ldx */
2826 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2827
2828 static void gen_ld(DisasContext *ctx)
2829 {
2830 TCGv EA;
2831 if (Rc(ctx->opcode)) {
2832 if (unlikely(rA(ctx->opcode) == 0 ||
2833 rA(ctx->opcode) == rD(ctx->opcode))) {
2834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2835 return;
2836 }
2837 }
2838 gen_set_access_type(ctx, ACCESS_INT);
2839 EA = tcg_temp_new();
2840 gen_addr_imm_index(ctx, EA, 0x03);
2841 if (ctx->opcode & 0x02) {
2842 /* lwa (lwau is undefined) */
2843 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2844 } else {
2845 /* ld - ldu */
2846 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2847 }
2848 if (Rc(ctx->opcode))
2849 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2850 tcg_temp_free(EA);
2851 }
2852
2853 /* lq */
2854 static void gen_lq(DisasContext *ctx)
2855 {
2856 int ra, rd;
2857 TCGv EA;
2858
2859 /* lq is a legal user mode instruction starting in ISA 2.07 */
2860 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2861 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2862
2863 if (!legal_in_user_mode && is_user_mode(ctx)) {
2864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2865 return;
2866 }
2867
2868 if (!le_is_supported && ctx->le_mode) {
2869 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2870 return;
2871 }
2872
2873 ra = rA(ctx->opcode);
2874 rd = rD(ctx->opcode);
2875 if (unlikely((rd & 1) || rd == ra)) {
2876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2877 return;
2878 }
2879
2880 gen_set_access_type(ctx, ACCESS_INT);
2881 EA = tcg_temp_new();
2882 gen_addr_imm_index(ctx, EA, 0x0F);
2883
2884 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2885 64-bit byteswap already. */
2886 if (unlikely(ctx->le_mode)) {
2887 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2888 gen_addr_add(ctx, EA, EA, 8);
2889 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2890 } else {
2891 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2892 gen_addr_add(ctx, EA, EA, 8);
2893 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2894 }
2895 tcg_temp_free(EA);
2896 }
2897 #endif
2898
2899 /*** Integer store ***/
2900 #define GEN_ST(name, stop, opc, type) \
2901 static void glue(gen_, name)(DisasContext *ctx) \
2902 { \
2903 TCGv EA; \
2904 gen_set_access_type(ctx, ACCESS_INT); \
2905 EA = tcg_temp_new(); \
2906 gen_addr_imm_index(ctx, EA, 0); \
2907 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2908 tcg_temp_free(EA); \
2909 }
2910
2911 #define GEN_STU(name, stop, opc, type) \
2912 static void glue(gen_, stop##u)(DisasContext *ctx) \
2913 { \
2914 TCGv EA; \
2915 if (unlikely(rA(ctx->opcode) == 0)) { \
2916 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2917 return; \
2918 } \
2919 gen_set_access_type(ctx, ACCESS_INT); \
2920 EA = tcg_temp_new(); \
2921 if (type == PPC_64B) \
2922 gen_addr_imm_index(ctx, EA, 0x03); \
2923 else \
2924 gen_addr_imm_index(ctx, EA, 0); \
2925 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2926 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2927 tcg_temp_free(EA); \
2928 }
2929
2930 #define GEN_STUX(name, stop, opc2, opc3, type) \
2931 static void glue(gen_, name##ux)(DisasContext *ctx) \
2932 { \
2933 TCGv EA; \
2934 if (unlikely(rA(ctx->opcode) == 0)) { \
2935 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2936 return; \
2937 } \
2938 gen_set_access_type(ctx, ACCESS_INT); \
2939 EA = tcg_temp_new(); \
2940 gen_addr_reg_index(ctx, EA); \
2941 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2942 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2943 tcg_temp_free(EA); \
2944 }
2945
2946 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2947 static void glue(gen_, name##x)(DisasContext *ctx) \
2948 { \
2949 TCGv EA; \
2950 gen_set_access_type(ctx, ACCESS_INT); \
2951 EA = tcg_temp_new(); \
2952 gen_addr_reg_index(ctx, EA); \
2953 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2954 tcg_temp_free(EA); \
2955 }
2956 #define GEN_STX(name, stop, opc2, opc3, type) \
2957 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2958
2959 #define GEN_STS(name, stop, op, type) \
2960 GEN_ST(name, stop, op | 0x20, type); \
2961 GEN_STU(name, stop, op | 0x21, type); \
2962 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2963 GEN_STX(name, stop, 0x17, op | 0x00, type)
2964
2965 /* stb stbu stbux stbx */
2966 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2967 /* sth sthu sthux sthx */
2968 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2969 /* stw stwu stwux stwx */
2970 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2971 #if defined(TARGET_PPC64)
2972 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2973 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2974
2975 static void gen_std(DisasContext *ctx)
2976 {
2977 int rs;
2978 TCGv EA;
2979
2980 rs = rS(ctx->opcode);
2981 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2982
2983 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2984 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2985
2986 if (!legal_in_user_mode && is_user_mode(ctx)) {
2987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2988 return;
2989 }
2990
2991 if (!le_is_supported && ctx->le_mode) {
2992 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2993 return;
2994 }
2995
2996 if (unlikely(rs & 1)) {
2997 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2998 return;
2999 }
3000 gen_set_access_type(ctx, ACCESS_INT);
3001 EA = tcg_temp_new();
3002 gen_addr_imm_index(ctx, EA, 0x03);
3003
3004 /* We only need to swap high and low halves. gen_qemu_st64 does
3005 necessary 64-bit byteswap already. */
3006 if (unlikely(ctx->le_mode)) {
3007 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3008 gen_addr_add(ctx, EA, EA, 8);
3009 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3010 } else {
3011 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3012 gen_addr_add(ctx, EA, EA, 8);
3013 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3014 }
3015 tcg_temp_free(EA);
3016 } else {
3017 /* std / stdu*/
3018 if (Rc(ctx->opcode)) {
3019 if (unlikely(rA(ctx->opcode) == 0)) {
3020 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3021 return;
3022 }
3023 }
3024 gen_set_access_type(ctx, ACCESS_INT);
3025 EA = tcg_temp_new();
3026 gen_addr_imm_index(ctx, EA, 0x03);
3027 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3028 if (Rc(ctx->opcode))
3029 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3030 tcg_temp_free(EA);
3031 }
3032 }
3033 #endif
3034 /*** Integer load and store with byte reverse ***/
3035
3036 /* lhbrx */
3037 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3038 {
3039 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3040 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3041 }
3042 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3043
3044 /* lwbrx */
3045 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3046 {
3047 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3048 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3049 }
3050 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3051
3052 #if defined(TARGET_PPC64)
3053 /* ldbrx */
3054 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3055 {
3056 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3057 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3058 }
3059 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3060 #endif /* TARGET_PPC64 */
3061
3062 /* sthbrx */
3063 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3064 {
3065 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3066 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3067 }
3068 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3069
3070 /* stwbrx */
3071 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3072 {
3073 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3074 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3075 }
3076 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3077
3078 #if defined(TARGET_PPC64)
3079 /* stdbrx */
3080 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3081 {
3082 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3083 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3084 }
3085 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3086 #endif /* TARGET_PPC64 */
3087
3088 /*** Integer load and store multiple ***/
3089
3090 /* lmw */
3091 static void gen_lmw(DisasContext *ctx)
3092 {
3093 TCGv t0;
3094 TCGv_i32 t1;
3095 gen_set_access_type(ctx, ACCESS_INT);
3096 /* NIP cannot be restored if the memory exception comes from an helper */
3097 gen_update_nip(ctx, ctx->nip - 4);
3098 t0 = tcg_temp_new();
3099 t1 = tcg_const_i32(rD(ctx->opcode));
3100 gen_addr_imm_index(ctx, t0, 0);
3101 gen_helper_lmw(cpu_env, t0, t1);
3102 tcg_temp_free(t0);
3103 tcg_temp_free_i32(t1);
3104 }
3105
3106 /* stmw */
3107 static void gen_stmw(DisasContext *ctx)
3108 {
3109 TCGv t0;
3110 TCGv_i32 t1;
3111 gen_set_access_type(ctx, ACCESS_INT);
3112 /* NIP cannot be restored if the memory exception comes from an helper */
3113 gen_update_nip(ctx, ctx->nip - 4);
3114 t0 = tcg_temp_new();
3115 t1 = tcg_const_i32(rS(ctx->opcode));
3116 gen_addr_imm_index(ctx, t0, 0);
3117 gen_helper_stmw(cpu_env, t0, t1);
3118 tcg_temp_free(t0);
3119 tcg_temp_free_i32(t1);
3120 }
3121
3122 /*** Integer load and store strings ***/
3123
3124 /* lswi */
3125 /* PowerPC32 specification says we must generate an exception if
3126 * rA is in the range of registers to be loaded.
3127 * In an other hand, IBM says this is valid, but rA won't be loaded.
3128 * For now, I'll follow the spec...
3129 */
3130 static void gen_lswi(DisasContext *ctx)
3131 {
3132 TCGv t0;
3133 TCGv_i32 t1, t2;
3134 int nb = NB(ctx->opcode);
3135 int start = rD(ctx->opcode);
3136 int ra = rA(ctx->opcode);
3137 int nr;
3138
3139 if (nb == 0)
3140 nb = 32;
3141 nr = nb / 4;
3142 if (unlikely(((start + nr) > 32 &&
3143 start <= ra && (start + nr - 32) > ra) ||
3144 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3145 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3146 return;
3147 }
3148 gen_set_access_type(ctx, ACCESS_INT);
3149 /* NIP cannot be restored if the memory exception comes from an helper */
3150 gen_update_nip(ctx, ctx->nip - 4);
3151 t0 = tcg_temp_new();
3152 gen_addr_register(ctx, t0);
3153 t1 = tcg_const_i32(nb);
3154 t2 = tcg_const_i32(start);
3155 gen_helper_lsw(cpu_env, t0, t1, t2);
3156 tcg_temp_free(t0);
3157 tcg_temp_free_i32(t1);
3158 tcg_temp_free_i32(t2);
3159 }
3160
3161 /* lswx */
3162 static void gen_lswx(DisasContext *ctx)
3163 {
3164 TCGv t0;
3165 TCGv_i32 t1, t2, t3;
3166 gen_set_access_type(ctx, ACCESS_INT);
3167 /* NIP cannot be restored if the memory exception comes from an helper */
3168 gen_update_nip(ctx, ctx->nip - 4);
3169 t0 = tcg_temp_new();
3170 gen_addr_reg_index(ctx, t0);
3171 t1 = tcg_const_i32(rD(ctx->opcode));
3172 t2 = tcg_const_i32(rA(ctx->opcode));
3173 t3 = tcg_const_i32(rB(ctx->opcode));
3174 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3175 tcg_temp_free(t0);
3176 tcg_temp_free_i32(t1);
3177 tcg_temp_free_i32(t2);
3178 tcg_temp_free_i32(t3);
3179 }
3180
3181 /* stswi */
3182 static void gen_stswi(DisasContext *ctx)
3183 {
3184 TCGv t0;
3185 TCGv_i32 t1, t2;
3186 int nb = NB(ctx->opcode);
3187 gen_set_access_type(ctx, ACCESS_INT);
3188 /* NIP cannot be restored if the memory exception comes from an helper */
3189 gen_update_nip(ctx, ctx->nip - 4);
3190 t0 = tcg_temp_new();
3191 gen_addr_register(ctx, t0);
3192 if (nb == 0)
3193 nb = 32;
3194 t1 = tcg_const_i32(nb);
3195 t2 = tcg_const_i32(rS(ctx->opcode));
3196 gen_helper_stsw(cpu_env, t0, t1, t2);
3197 tcg_temp_free(t0);
3198 tcg_temp_free_i32(t1);
3199 tcg_temp_free_i32(t2);
3200 }
3201
3202 /* stswx */
3203 static void gen_stswx(DisasContext *ctx)
3204 {
3205 TCGv t0;
3206 TCGv_i32 t1, t2;
3207 gen_set_access_type(ctx, ACCESS_INT);
3208 /* NIP cannot be restored if the memory exception comes from an helper */
3209 gen_update_nip(ctx, ctx->nip - 4);
3210 t0 = tcg_temp_new();
3211 gen_addr_reg_index(ctx, t0);
3212 t1 = tcg_temp_new_i32();
3213 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3214 tcg_gen_andi_i32(t1, t1, 0x7F);
3215 t2 = tcg_const_i32(rS(ctx->opcode));
3216 gen_helper_stsw(cpu_env, t0, t1, t2);
3217 tcg_temp_free(t0);
3218 tcg_temp_free_i32(t1);
3219 tcg_temp_free_i32(t2);
3220 }
3221
3222 /*** Memory synchronisation ***/
3223 /* eieio */
3224 static void gen_eieio(DisasContext *ctx)
3225 {
3226 }
3227
3228 /* isync */
3229 static void gen_isync(DisasContext *ctx)
3230 {
3231 gen_stop_exception(ctx);
3232 }
3233
3234 #define LARX(name, len, loadop) \
3235 static void gen_##name(DisasContext *ctx) \
3236 { \
3237 TCGv t0; \
3238 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3239 gen_set_access_type(ctx, ACCESS_RES); \
3240 t0 = tcg_temp_local_new(); \
3241 gen_addr_reg_index(ctx, t0); \
3242 if ((len) > 1) { \
3243 gen_check_align(ctx, t0, (len)-1); \
3244 } \
3245 gen_qemu_##loadop(ctx, gpr, t0); \
3246 tcg_gen_mov_tl(cpu_reserve, t0); \
3247 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3248 tcg_temp_free(t0); \
3249 }
3250
3251 /* lwarx */
3252 LARX(lbarx, 1, ld8u);
3253 LARX(lharx, 2, ld16u);
3254 LARX(lwarx, 4, ld32u);
3255
3256
3257 #if defined(CONFIG_USER_ONLY)
3258 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3259 int reg, int size)
3260 {
3261 TCGv t0 = tcg_temp_new();
3262 uint32_t save_exception = ctx->exception;
3263
3264 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3265 tcg_gen_movi_tl(t0, (size << 5) | reg);
3266 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3267 tcg_temp_free(t0);
3268 gen_update_nip(ctx, ctx->nip-4);
3269 ctx->exception = POWERPC_EXCP_BRANCH;
3270 gen_exception(ctx, POWERPC_EXCP_STCX);
3271 ctx->exception = save_exception;
3272 }
3273 #else
3274 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3275 int reg, int size)
3276 {
3277 int l1;
3278
3279 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3280 l1 = gen_new_label();
3281 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3282 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3283 #if defined(TARGET_PPC64)
3284 if (size == 8) {
3285 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3286 } else
3287 #endif
3288 if (size == 4) {
3289 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3290 } else if (size == 2) {
3291 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3292 #if defined(TARGET_PPC64)
3293 } else if (size == 16) {
3294 TCGv gpr1, gpr2 , EA8;
3295 if (unlikely(ctx->le_mode)) {
3296 gpr1 = cpu_gpr[reg+1];
3297 gpr2 = cpu_gpr[reg];
3298 } else {
3299 gpr1 = cpu_gpr[reg];
3300 gpr2 = cpu_gpr[reg+1];
3301 }
3302 gen_qemu_st64(ctx, gpr1, EA);
3303 EA8 = tcg_temp_local_new();
3304 gen_addr_add(ctx, EA8, EA, 8);
3305 gen_qemu_st64(ctx, gpr2, EA8);
3306 tcg_temp_free(EA8);
3307 #endif
3308 } else {
3309 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3310 }
3311 gen_set_label(l1);
3312 tcg_gen_movi_tl(cpu_reserve, -1);
3313 }
3314 #endif
3315
3316 #define STCX(name, len) \
3317 static void gen_##name(DisasContext *ctx) \
3318 { \
3319 TCGv t0; \
3320 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3321 gen_inval_exception(ctx, \
3322 POWERPC_EXCP_INVAL_INVAL); \
3323 return; \
3324 } \
3325 gen_set_access_type(ctx, ACCESS_RES); \
3326 t0 = tcg_temp_local_new(); \
3327 gen_addr_reg_index(ctx, t0); \
3328 if (len > 1) { \
3329 gen_check_align(ctx, t0, (len)-1); \
3330 } \
3331 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3332 tcg_temp_free(t0); \
3333 }
3334
3335 STCX(stbcx_, 1);
3336 STCX(sthcx_, 2);
3337 STCX(stwcx_, 4);
3338
3339 #if defined(TARGET_PPC64)
3340 /* ldarx */
3341 LARX(ldarx, 8, ld64);
3342
3343 /* lqarx */
3344 static void gen_lqarx(DisasContext *ctx)
3345 {
3346 TCGv EA;
3347 int rd = rD(ctx->opcode);
3348 TCGv gpr1, gpr2;
3349
3350 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3351 (rd == rB(ctx->opcode)))) {
3352 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3353 return;
3354 }
3355
3356 gen_set_access_type(ctx, ACCESS_RES);
3357 EA = tcg_temp_local_new();
3358 gen_addr_reg_index(ctx, EA);
3359 gen_check_align(ctx, EA, 15);
3360 if (unlikely(ctx->le_mode)) {
3361 gpr1 = cpu_gpr[rd+1];
3362 gpr2 = cpu_gpr[rd];
3363 } else {
3364 gpr1 = cpu_gpr[rd];
3365 gpr2 = cpu_gpr[rd+1];
3366 }
3367 gen_qemu_ld64(ctx, gpr1, EA);
3368 tcg_gen_mov_tl(cpu_reserve, EA);
3369
3370 gen_addr_add(ctx, EA, EA, 8);
3371 gen_qemu_ld64(ctx, gpr2, EA);
3372
3373 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3374 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3375
3376 tcg_temp_free(EA);
3377 }
3378
3379 /* stdcx. */
3380 STCX(stdcx_, 8);
3381 STCX(stqcx_, 16);
3382 #endif /* defined(TARGET_PPC64) */
3383
3384 /* sync */
3385 static void gen_sync(DisasContext *ctx)
3386 {
3387 }
3388
3389 /* wait */
3390 static void gen_wait(DisasContext *ctx)
3391 {
3392 TCGv_i32 t0 = tcg_temp_new_i32();
3393 tcg_gen_st_i32(t0, cpu_env,
3394 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3395 tcg_temp_free_i32(t0);
3396 /* Stop translation, as the CPU is supposed to sleep from now */
3397 gen_exception_err(ctx, EXCP_HLT, 1);
3398 }
3399
3400 /*** Floating-point load ***/
3401 #define GEN_LDF(name, ldop, opc, type) \
3402 static void glue(gen_, name)(DisasContext *ctx) \
3403 { \
3404 TCGv EA; \
3405 if (unlikely(!ctx->fpu_enabled)) { \
3406 gen_exception(ctx, POWERPC_EXCP_FPU); \
3407 return; \
3408 } \
3409 gen_set_access_type(ctx, ACCESS_FLOAT); \
3410 EA = tcg_temp_new(); \
3411 gen_addr_imm_index(ctx, EA, 0); \
3412 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3413 tcg_temp_free(EA); \
3414 }
3415
3416 #define GEN_LDUF(name, ldop, opc, type) \
3417 static void glue(gen_, name##u)(DisasContext *ctx) \
3418 { \
3419 TCGv EA; \
3420 if (unlikely(!ctx->fpu_enabled)) { \
3421 gen_exception(ctx, POWERPC_EXCP_FPU); \
3422 return; \
3423 } \
3424 if (unlikely(rA(ctx->opcode) == 0)) { \
3425 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3426 return; \
3427 } \
3428 gen_set_access_type(ctx, ACCESS_FLOAT); \
3429 EA = tcg_temp_new(); \
3430 gen_addr_imm_index(ctx, EA, 0); \
3431 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3432 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3433 tcg_temp_free(EA); \
3434 }
3435
3436 #define GEN_LDUXF(name, ldop, opc, type) \
3437 static void glue(gen_, name##ux)(DisasContext *ctx) \
3438 { \
3439 TCGv EA; \
3440 if (unlikely(!ctx->fpu_enabled)) { \
3441 gen_exception(ctx, POWERPC_EXCP_FPU); \
3442 return; \
3443 } \
3444 if (unlikely(rA(ctx->opcode) == 0)) { \
3445 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3446 return; \
3447 } \
3448 gen_set_access_type(ctx, ACCESS_FLOAT); \
3449 EA = tcg_temp_new(); \
3450 gen_addr_reg_index(ctx, EA); \
3451 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3452 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3453 tcg_temp_free(EA); \
3454 }
3455
3456 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3457 static void glue(gen_, name##x)(DisasContext *ctx) \
3458 { \
3459 TCGv EA; \
3460 if (unlikely(!ctx->fpu_enabled)) { \
3461 gen_exception(ctx, POWERPC_EXCP_FPU); \
3462 return; \
3463 } \
3464 gen_set_access_type(ctx, ACCESS_FLOAT); \
3465 EA = tcg_temp_new(); \
3466 gen_addr_reg_index(ctx, EA); \
3467 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3468 tcg_temp_free(EA); \
3469 }
3470
3471 #define GEN_LDFS(name, ldop, op, type) \
3472 GEN_LDF(name, ldop, op | 0x20, type); \
3473 GEN_LDUF(name, ldop, op | 0x21, type); \
3474 GEN_LDUXF(name, ldop, op | 0x01, type); \
3475 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3476
3477 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3478 {
3479 TCGv t0 = tcg_temp_new();
3480 TCGv_i32 t1 = tcg_temp_new_i32();
3481 gen_qemu_ld32u(ctx, t0, arg2);
3482 tcg_gen_trunc_tl_i32(t1, t0);
3483 tcg_temp_free(t0);
3484 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3485 tcg_temp_free_i32(t1);
3486 }
3487
3488 /* lfd lfdu lfdux lfdx */
3489 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3490 /* lfs lfsu lfsux lfsx */
3491 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3492
3493 /* lfdp */
3494 static void gen_lfdp(DisasContext *ctx)
3495 {
3496 TCGv EA;
3497 if (unlikely(!ctx->fpu_enabled)) {
3498 gen_exception(ctx, POWERPC_EXCP_FPU);
3499 return;
3500 }
3501 gen_set_access_type(ctx, ACCESS_FLOAT);
3502 EA = tcg_temp_new();
3503 gen_addr_imm_index(ctx, EA, 0);
3504 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3505 64-bit byteswap already. */
3506 if (unlikely(ctx->le_mode)) {
3507 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3508 tcg_gen_addi_tl(EA, EA, 8);
3509 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3510 } else {
3511 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3512 tcg_gen_addi_tl(EA, EA, 8);
3513 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3514 }
3515 tcg_temp_free(EA);
3516 }
3517
3518 /* lfdpx */
3519 static void gen_lfdpx(DisasContext *ctx)
3520 {
3521 TCGv EA;
3522 if (unlikely(!ctx->fpu_enabled)) {
3523 gen_exception(ctx, POWERPC_EXCP_FPU);
3524 return;
3525 }
3526 gen_set_access_type(ctx, ACCESS_FLOAT);
3527 EA = tcg_temp_new();
3528 gen_addr_reg_index(ctx, EA);
3529 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3530 64-bit byteswap already. */
3531 if (unlikely(ctx->le_mode)) {
3532 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3533 tcg_gen_addi_tl(EA, EA, 8);
3534 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3535 } else {
3536 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3537 tcg_gen_addi_tl(EA, EA, 8);
3538 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3539 }
3540 tcg_temp_free(EA);
3541 }
3542
3543 /* lfiwax */
3544 static void gen_lfiwax(DisasContext *ctx)
3545 {
3546 TCGv EA;
3547 TCGv t0;
3548 if (unlikely(!ctx->fpu_enabled)) {
3549 gen_exception(ctx, POWERPC_EXCP_FPU);
3550 return;
3551 }
3552 gen_set_access_type(ctx, ACCESS_FLOAT);
3553 EA = tcg_temp_new();
3554 t0 = tcg_temp_new();
3555 gen_addr_reg_index(ctx, EA);
3556 gen_qemu_ld32s(ctx, t0, EA);
3557 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3558 tcg_temp_free(EA);
3559 tcg_temp_free(t0);
3560 }
3561
3562 /* lfiwzx */
3563 static void gen_lfiwzx(DisasContext *ctx)
3564 {
3565 TCGv EA;
3566 if (unlikely(!ctx->fpu_enabled)) {
3567 gen_exception(ctx, POWERPC_EXCP_FPU);
3568 return;
3569 }
3570 gen_set_access_type(ctx, ACCESS_FLOAT);
3571 EA = tcg_temp_new();
3572 gen_addr_reg_index(ctx, EA);
3573 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3574 tcg_temp_free(EA);
3575 }
3576 /*** Floating-point store ***/
3577 #define GEN_STF(name, stop, opc, type) \
3578 static void glue(gen_, name)(DisasContext *ctx) \
3579 { \
3580 TCGv EA; \
3581 if (unlikely(!ctx->fpu_enabled)) { \
3582 gen_exception(ctx, POWERPC_EXCP_FPU); \
3583 return; \
3584 } \
3585 gen_set_access_type(ctx, ACCESS_FLOAT); \
3586 EA = tcg_temp_new(); \
3587 gen_addr_imm_index(ctx, EA, 0); \
3588 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3589 tcg_temp_free(EA); \
3590 }
3591
3592 #define GEN_STUF(name, stop, opc, type) \
3593 static void glue(gen_, name##u)(DisasContext *ctx) \
3594 { \
3595 TCGv EA; \
3596 if (unlikely(!ctx->fpu_enabled)) { \
3597 gen_exception(ctx, POWERPC_EXCP_FPU); \
3598 return; \
3599 } \
3600 if (unlikely(rA(ctx->opcode) == 0)) { \
3601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3602 return; \
3603 } \
3604 gen_set_access_type(ctx, ACCESS_FLOAT); \
3605 EA = tcg_temp_new(); \
3606 gen_addr_imm_index(ctx, EA, 0); \
3607 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3608 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3609 tcg_temp_free(EA); \
3610 }
3611
3612 #define GEN_STUXF(name, stop, opc, type) \
3613 static void glue(gen_, name##ux)(DisasContext *ctx) \
3614 { \
3615 TCGv EA; \
3616 if (unlikely(!ctx->fpu_enabled)) { \
3617 gen_exception(ctx, POWERPC_EXCP_FPU); \
3618 return; \
3619 } \
3620 if (unlikely(rA(ctx->opcode) == 0)) { \
3621 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3622 return; \
3623 } \
3624 gen_set_access_type(ctx, ACCESS_FLOAT); \
3625 EA = tcg_temp_new(); \
3626 gen_addr_reg_index(ctx, EA); \
3627 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3628 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3629 tcg_temp_free(EA); \
3630 }
3631
3632 #define GEN_STXF(name, stop, opc2, opc3, type) \
3633 static void glue(gen_, name##x)(DisasContext *ctx) \
3634 { \
3635 TCGv EA; \
3636 if (unlikely(!ctx->fpu_enabled)) { \
3637 gen_exception(ctx, POWERPC_EXCP_FPU); \
3638 return; \
3639 } \
3640 gen_set_access_type(ctx, ACCESS_FLOAT); \
3641 EA = tcg_temp_new(); \
3642 gen_addr_reg_index(ctx, EA); \
3643 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3644 tcg_temp_free(EA); \
3645 }
3646
3647 #define GEN_STFS(name, stop, op, type) \
3648 GEN_STF(name, stop, op | 0x20, type); \
3649 GEN_STUF(name, stop, op | 0x21, type); \
3650 GEN_STUXF(name, stop, op | 0x01, type); \
3651 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3652
3653 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3654 {
3655 TCGv_i32 t0 = tcg_temp_new_i32();
3656 TCGv t1 = tcg_temp_new();
3657 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3658 tcg_gen_extu_i32_tl(t1, t0);
3659 tcg_temp_free_i32(t0);
3660 gen_qemu_st32(ctx, t1, arg2);
3661 tcg_temp_free(t1);
3662 }
3663
3664 /* stfd stfdu stfdux stfdx */
3665 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3666 /* stfs stfsu stfsux stfsx */
3667 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3668
3669 /* stfdp */
3670 static void gen_stfdp(DisasContext *ctx)
3671 {
3672 TCGv EA;
3673 if (unlikely(!ctx->fpu_enabled)) {
3674 gen_exception(ctx, POWERPC_EXCP_FPU);
3675 return;
3676 }
3677 gen_set_access_type(ctx, ACCESS_FLOAT);
3678 EA = tcg_temp_new();
3679 gen_addr_imm_index(ctx, EA, 0);
3680 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3681 64-bit byteswap already. */
3682 if (unlikely(ctx->le_mode)) {
3683 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3684 tcg_gen_addi_tl(EA, EA, 8);
3685 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3686 } else {
3687 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3688 tcg_gen_addi_tl(EA, EA, 8);
3689 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3690 }
3691 tcg_temp_free(EA);
3692 }
3693
3694 /* stfdpx */
3695 static void gen_stfdpx(DisasContext *ctx)
3696 {
3697 TCGv EA;
3698 if (unlikely(!ctx->fpu_enabled)) {
3699 gen_exception(ctx, POWERPC_EXCP_FPU);
3700 return;
3701 }
3702 gen_set_access_type(ctx, ACCESS_FLOAT);
3703 EA = tcg_temp_new();
3704 gen_addr_reg_index(ctx, EA);
3705 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3706 64-bit byteswap already. */
3707 if (unlikely(ctx->le_mode)) {
3708 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3709 tcg_gen_addi_tl(EA, EA, 8);
3710 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3711 } else {
3712 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3713 tcg_gen_addi_tl(EA, EA, 8);
3714 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3715 }
3716 tcg_temp_free(EA);
3717 }
3718
3719 /* Optional: */
3720 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3721 {
3722 TCGv t0 = tcg_temp_new();
3723 tcg_gen_trunc_i64_tl(t0, arg1),
3724 gen_qemu_st32(ctx, t0, arg2);
3725 tcg_temp_free(t0);
3726 }
3727 /* stfiwx */
3728 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3729
3730 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3731 {
3732 #if defined(TARGET_PPC64)
3733 if (ctx->has_cfar)
3734 tcg_gen_movi_tl(cpu_cfar, nip);
3735 #endif
3736 }
3737
3738 /*** Branch ***/
3739 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3740 {
3741 TranslationBlock *tb;
3742 tb = ctx->tb;
3743 if (NARROW_MODE(ctx)) {
3744 dest = (uint32_t) dest;
3745 }
3746 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3747 likely(!ctx->singlestep_enabled)) {
3748 tcg_gen_goto_tb(n);
3749 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3750 tcg_gen_exit_tb((uintptr_t)tb + n);
3751 } else {
3752 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3753 if (unlikely(ctx->singlestep_enabled)) {
3754 if ((ctx->singlestep_enabled &
3755 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3756 (ctx->exception == POWERPC_EXCP_BRANCH ||
3757 ctx->exception == POWERPC_EXCP_TRACE)) {
3758 target_ulong tmp = ctx->nip;
3759 ctx->nip = dest;
3760 gen_exception(ctx, POWERPC_EXCP_TRACE);
3761 ctx->nip = tmp;
3762 }
3763 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3764 gen_debug_exception(ctx);
3765 }
3766 }
3767 tcg_gen_exit_tb(0);
3768 }
3769 }
3770
3771 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3772 {
3773 if (NARROW_MODE(ctx)) {
3774 nip = (uint32_t)nip;
3775 }
3776 tcg_gen_movi_tl(cpu_lr, nip);
3777 }
3778
3779 /* b ba bl bla */
3780 static void gen_b(DisasContext *ctx)
3781 {
3782 target_ulong li, target;
3783
3784 ctx->exception = POWERPC_EXCP_BRANCH;
3785 /* sign extend LI */
3786 li = LI(ctx->opcode);
3787 li = (li ^ 0x02000000) - 0x02000000;
3788 if (likely(AA(ctx->opcode) == 0)) {
3789 target = ctx->nip + li - 4;
3790 } else {
3791 target = li;
3792 }
3793 if (LK(ctx->opcode)) {
3794 gen_setlr(ctx, ctx->nip);
3795 }
3796 gen_update_cfar(ctx, ctx->nip);
3797 gen_goto_tb(ctx, 0, target);
3798 }
3799
3800 #define BCOND_IM 0
3801 #define BCOND_LR 1
3802 #define BCOND_CTR 2
3803 #define BCOND_TAR 3
3804
3805 static inline void gen_bcond(DisasContext *ctx, int type)
3806 {
3807 uint32_t bo = BO(ctx->opcode);
3808 int l1;
3809 TCGv target;
3810
3811 ctx->exception = POWERPC_EXCP_BRANCH;
3812 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3813 target = tcg_temp_local_new();
3814 if (type == BCOND_CTR)
3815 tcg_gen_mov_tl(target, cpu_ctr);
3816 else if (type == BCOND_TAR)
3817 gen_load_spr(target, SPR_TAR);
3818 else
3819 tcg_gen_mov_tl(target, cpu_lr);
3820 } else {
3821 TCGV_UNUSED(target);
3822 }
3823 if (LK(ctx->opcode))
3824 gen_setlr(ctx, ctx->nip);
3825 l1 = gen_new_label();
3826 if ((bo & 0x4) == 0) {
3827 /* Decrement and test CTR */
3828 TCGv temp = tcg_temp_new();
3829 if (unlikely(type == BCOND_CTR)) {
3830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3831 return;
3832 }
3833 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3834 if (NARROW_MODE(ctx)) {
3835 tcg_gen_ext32u_tl(temp, cpu_ctr);
3836 } else {
3837 tcg_gen_mov_tl(temp, cpu_ctr);
3838 }
3839 if (bo & 0x2) {
3840 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3841 } else {
3842 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3843 }
3844 tcg_temp_free(temp);
3845 }
3846 if ((bo & 0x10) == 0) {
3847 /* Test CR */
3848 uint32_t bi = BI(ctx->opcode);
3849 uint32_t mask = 1 << (3 - (bi & 0x03));
3850 TCGv_i32 temp = tcg_temp_new_i32();
3851
3852 if (bo & 0x8) {
3853 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3854 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3855 } else {
3856 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3857 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3858 }
3859 tcg_temp_free_i32(temp);
3860 }
3861 gen_update_cfar(ctx, ctx->nip);
3862 if (type == BCOND_IM) {
3863 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3864 if (likely(AA(ctx->opcode) == 0)) {
3865 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3866 } else {
3867 gen_goto_tb(ctx, 0, li);
3868 }
3869 gen_set_label(l1);
3870 gen_goto_tb(ctx, 1, ctx->nip);
3871 } else {
3872 if (NARROW_MODE(ctx)) {
3873 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3874 } else {
3875 tcg_gen_andi_tl(cpu_nip, target, ~3);
3876 }
3877 tcg_gen_exit_tb(0);
3878 gen_set_label(l1);
3879 gen_update_nip(ctx, ctx->nip);
3880 tcg_gen_exit_tb(0);
3881 }
3882 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3883 tcg_temp_free(target);
3884 }
3885 }
3886
3887 static void gen_bc(DisasContext *ctx)
3888 {
3889 gen_bcond(ctx, BCOND_IM);
3890 }
3891
3892 static void gen_bcctr(DisasContext *ctx)
3893 {
3894 gen_bcond(ctx, BCOND_CTR);
3895 }
3896
3897 static void gen_bclr(DisasContext *ctx)
3898 {
3899 gen_bcond(ctx, BCOND_LR);
3900 }
3901
3902 static void gen_bctar(DisasContext *ctx)
3903 {
3904 gen_bcond(ctx, BCOND_TAR);
3905 }
3906
3907 /*** Condition register logical ***/
3908 #define GEN_CRLOGIC(name, tcg_op, opc) \
3909 static void glue(gen_, name)(DisasContext *ctx) \
3910 { \
3911 uint8_t bitmask; \
3912 int sh; \
3913 TCGv_i32 t0, t1; \
3914 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3915 t0 = tcg_temp_new_i32(); \
3916 if (sh > 0) \
3917 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3918 else if (sh < 0) \
3919 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3920 else \
3921 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3922 t1 = tcg_temp_new_i32(); \
3923 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3924 if (sh > 0) \
3925 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3926 else if (sh < 0) \
3927 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3928 else \
3929 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3930 tcg_op(t0, t0, t1); \
3931 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3932 tcg_gen_andi_i32(t0, t0, bitmask); \
3933 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3934 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3935 tcg_temp_free_i32(t0); \
3936 tcg_temp_free_i32(t1); \
3937 }
3938
3939 /* crand */
3940 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3941 /* crandc */
3942 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3943 /* creqv */
3944 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3945 /* crnand */
3946 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3947 /* crnor */
3948 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3949 /* cror */
3950 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3951 /* crorc */
3952 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3953 /* crxor */
3954 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3955
3956 /* mcrf */
3957 static void gen_mcrf(DisasContext *ctx)
3958 {
3959 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3960 }
3961
3962 /*** System linkage ***/
3963
3964 /* rfi (mem_idx only) */
3965 static void gen_rfi(DisasContext *ctx)
3966 {
3967 #if defined(CONFIG_USER_ONLY)
3968 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3969 #else
3970 /* Restore CPU state */
3971 if (unlikely(!ctx->mem_idx)) {
3972 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3973 return;
3974 }
3975 gen_update_cfar(ctx, ctx->nip);
3976 gen_helper_rfi(cpu_env);
3977 gen_sync_exception(ctx);
3978 #endif
3979 }
3980
3981 #if defined(TARGET_PPC64)
3982 static void gen_rfid(DisasContext *ctx)
3983 {
3984 #if defined(CONFIG_USER_ONLY)
3985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3986 #else
3987 /* Restore CPU state */
3988 if (unlikely(!ctx->mem_idx)) {
3989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3990 return;
3991 }
3992 gen_update_cfar(ctx, ctx->nip);
3993 gen_helper_rfid(cpu_env);
3994 gen_sync_exception(ctx);
3995 #endif
3996 }
3997
3998 static void gen_hrfid(DisasContext *ctx)
3999 {
4000 #if defined(CONFIG_USER_ONLY)
4001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4002 #else
4003 /* Restore CPU state */
4004 if (unlikely(ctx->mem_idx <= 1)) {
4005 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4006 return;
4007 }
4008 gen_helper_hrfid(cpu_env);
4009 gen_sync_exception(ctx);
4010 #endif
4011 }
4012 #endif
4013
4014 /* sc */
4015 #if defined(CONFIG_USER_ONLY)
4016 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4017 #else
4018 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4019 #endif
4020 static void gen_sc(DisasContext *ctx)
4021 {
4022 uint32_t lev;
4023
4024 lev = (ctx->opcode >> 5) & 0x7F;
4025 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4026 }
4027
4028 /*** Trap ***/
4029
4030 /* tw */
4031 static void gen_tw(DisasContext *ctx)
4032 {
4033 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4034 /* Update the nip since this might generate a trap exception */
4035 gen_update_nip(ctx, ctx->nip);
4036 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4037 t0);
4038 tcg_temp_free_i32(t0);
4039 }
4040
4041 /* twi */
4042 static void gen_twi(DisasContext *ctx)
4043 {
4044 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4045 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4046 /* Update the nip since this might generate a trap exception */
4047 gen_update_nip(ctx, ctx->nip);
4048 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4049 tcg_temp_free(t0);
4050 tcg_temp_free_i32(t1);
4051 }
4052
4053 #if defined(TARGET_PPC64)
4054 /* td */
4055 static void gen_td(DisasContext *ctx)
4056 {
4057 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4058 /* Update the nip since this might generate a trap exception */
4059 gen_update_nip(ctx, ctx->nip);
4060 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4061 t0);
4062 tcg_temp_free_i32(t0);
4063 }
4064
4065 /* tdi */
4066 static void gen_tdi(DisasContext *ctx)
4067 {
4068 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4069 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4070 /* Update the nip since this might generate a trap exception */
4071 gen_update_nip(ctx, ctx->nip);
4072 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4073 tcg_temp_free(t0);
4074 tcg_temp_free_i32(t1);
4075 }
4076 #endif
4077
4078 /*** Processor control ***/
4079
4080 static void gen_read_xer(TCGv dst)
4081 {
4082 TCGv t0 = tcg_temp_new();
4083 TCGv t1 = tcg_temp_new();
4084 TCGv t2 = tcg_temp_new();
4085 tcg_gen_mov_tl(dst, cpu_xer);
4086 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4087 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4088 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4089 tcg_gen_or_tl(t0, t0, t1);
4090 tcg_gen_or_tl(dst, dst, t2);
4091 tcg_gen_or_tl(dst, dst, t0);
4092 tcg_temp_free(t0);
4093 tcg_temp_free(t1);
4094 tcg_temp_free(t2);
4095 }
4096
4097 static void gen_write_xer(TCGv src)
4098 {
4099 tcg_gen_andi_tl(cpu_xer, src,
4100 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4101 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4102 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4103 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4104 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4105 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4106 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4107 }
4108
4109 /* mcrxr */
4110 static void gen_mcrxr(DisasContext *ctx)
4111 {
4112 TCGv_i32 t0 = tcg_temp_new_i32();
4113 TCGv_i32 t1 = tcg_temp_new_i32();
4114 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4115
4116 tcg_gen_trunc_tl_i32(t0, cpu_so);
4117 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4118 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4119 tcg_gen_shli_i32(t0, t0, 3);
4120 tcg_gen_shli_i32(t1, t1, 2);
4121 tcg_gen_shli_i32(dst, dst, 1);
4122 tcg_gen_or_i32(dst, dst, t0);
4123 tcg_gen_or_i32(dst, dst, t1);
4124 tcg_temp_free_i32(t0);
4125 tcg_temp_free_i32(t1);
4126
4127 tcg_gen_movi_tl(cpu_so, 0);
4128 tcg_gen_movi_tl(cpu_ov, 0);
4129 tcg_gen_movi_tl(cpu_ca, 0);
4130 }
4131
4132 /* mfcr mfocrf */
4133 static void gen_mfcr(DisasContext *ctx)
4134 {
4135 uint32_t crm, crn;
4136
4137 if (likely(ctx->opcode & 0x00100000)) {
4138 crm = CRM(ctx->opcode);
4139 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4140 crn = ctz32 (crm);
4141 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4142 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4143 cpu_gpr[rD(ctx->opcode)], crn * 4);
4144 }
4145 } else {
4146 TCGv_i32 t0 = tcg_temp_new_i32();
4147 tcg_gen_mov_i32(t0, cpu_crf[0]);
4148 tcg_gen_shli_i32(t0, t0, 4);
4149 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4150 tcg_gen_shli_i32(t0, t0, 4);
4151 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4152 tcg_gen_shli_i32(t0, t0, 4);
4153 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4154 tcg_gen_shli_i32(t0, t0, 4);
4155 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4156 tcg_gen_shli_i32(t0, t0, 4);
4157 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4158 tcg_gen_shli_i32(t0, t0, 4);
4159 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4160 tcg_gen_shli_i32(t0, t0, 4);
4161 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4162 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4163 tcg_temp_free_i32(t0);
4164 }
4165 }
4166
4167 /* mfmsr */
4168 static void gen_mfmsr(DisasContext *ctx)
4169 {
4170 #if defined(CONFIG_USER_ONLY)
4171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4172 #else
4173 if (unlikely(!ctx->mem_idx)) {
4174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4175 return;
4176 }
4177 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4178 #endif
4179 }
4180
4181 static void spr_noaccess(void *opaque, int gprn, int sprn)
4182 {
4183 #if 0
4184 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4185 printf("ERROR: try to access SPR %d !\n", sprn);
4186 #endif
4187 }
4188 #define SPR_NOACCESS (&spr_noaccess)
4189
4190 /* mfspr */
4191 static inline void gen_op_mfspr(DisasContext *ctx)
4192 {
4193 void (*read_cb)(void *opaque, int gprn, int sprn);
4194 uint32_t sprn = SPR(ctx->opcode);
4195
4196 #if !defined(CONFIG_USER_ONLY)
4197 if (ctx->mem_idx == 2)
4198 read_cb = ctx->spr_cb[sprn].hea_read;
4199 else if (ctx->mem_idx)
4200 read_cb = ctx->spr_cb[sprn].oea_read;
4201 else
4202 #endif
4203 read_cb = ctx->spr_cb[sprn].uea_read;
4204 if (likely(read_cb != NULL)) {
4205 if (likely(read_cb != SPR_NOACCESS)) {
4206 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4207 } else {
4208 /* Privilege exception */
4209 /* This is a hack to avoid warnings when running Linux:
4210 * this OS breaks the PowerPC virtualisation model,
4211 * allowing userland application to read the PVR
4212 */
4213 if (sprn != SPR_PVR) {
4214 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4215 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4216 printf("Trying to read privileged spr %d (0x%03x) at "
4217 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4218 }
4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4220 }
4221 } else {
4222 /* Not defined */
4223 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4224 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4225 printf("Trying to read invalid spr %d (0x%03x) at "
4226 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4227 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4228 }
4229 }
4230
4231 static void gen_mfspr(DisasContext *ctx)
4232 {
4233 gen_op_mfspr(ctx);
4234 }
4235
4236 /* mftb */
4237 static void gen_mftb(DisasContext *ctx)
4238 {
4239 gen_op_mfspr(ctx);
4240 }
4241
4242 /* mtcrf mtocrf*/
4243 static void gen_mtcrf(DisasContext *ctx)
4244 {
4245 uint32_t crm, crn;
4246
4247 crm = CRM(ctx->opcode);
4248 if (likely((ctx->opcode & 0x00100000))) {
4249 if (crm && ((crm & (crm - 1)) == 0)) {
4250 TCGv_i32 temp = tcg_temp_new_i32();
4251 crn = ctz32 (crm);
4252 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4253 tcg_gen_shri_i32(temp, temp, crn * 4);
4254 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4255 tcg_temp_free_i32(temp);
4256 }
4257 } else {
4258 TCGv_i32 temp = tcg_temp_new_i32();
4259 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4260 for (crn = 0 ; crn < 8 ; crn++) {
4261 if (crm & (1 << crn)) {
4262 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4263 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4264 }
4265 }
4266 tcg_temp_free_i32(temp);
4267 }
4268 }
4269
4270 /* mtmsr */
4271 #if defined(TARGET_PPC64)
4272 static void gen_mtmsrd(DisasContext *ctx)
4273 {
4274 #if defined(CONFIG_USER_ONLY)
4275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4276 #else
4277 if (unlikely(!ctx->mem_idx)) {
4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4279 return;
4280 }
4281 if (ctx->opcode & 0x00010000) {
4282 /* Special form that does not need any synchronisation */
4283 TCGv t0 = tcg_temp_new();
4284 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4285 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4286 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4287 tcg_temp_free(t0);
4288 } else {
4289 /* XXX: we need to update nip before the store
4290 * if we enter power saving mode, we will exit the loop
4291 * directly from ppc_store_msr
4292 */
4293 gen_update_nip(ctx, ctx->nip);
4294 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4295 /* Must stop the translation as machine state (may have) changed */
4296 /* Note that mtmsr is not always defined as context-synchronizing */
4297 gen_stop_exception(ctx);
4298 }
4299 #endif
4300 }
4301 #endif
4302
4303 static void gen_mtmsr(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 #else
4308 if (unlikely(!ctx->mem_idx)) {
4309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4310 return;
4311 }
4312 if (ctx->opcode & 0x00010000) {
4313 /* Special form that does not need any synchronisation */
4314 TCGv t0 = tcg_temp_new();
4315 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4316 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4317 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4318 tcg_temp_free(t0);
4319 } else {
4320 TCGv msr = tcg_temp_new();
4321
4322 /* XXX: we need to update nip before the store
4323 * if we enter power saving mode, we will exit the loop
4324 * directly from ppc_store_msr
4325 */
4326 gen_update_nip(ctx, ctx->nip);
4327 #if defined(TARGET_PPC64)
4328 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4329 #else
4330 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4331 #endif
4332 gen_helper_store_msr(cpu_env, msr);
4333 tcg_temp_free(msr);
4334 /* Must stop the translation as machine state (may have) changed */
4335 /* Note that mtmsr is not always defined as context-synchronizing */
4336 gen_stop_exception(ctx);
4337 }
4338 #endif
4339 }
4340
4341 /* mtspr */
4342 static void gen_mtspr(DisasContext *ctx)
4343 {
4344 void (*write_cb)(void *opaque, int sprn, int gprn);
4345 uint32_t sprn = SPR(ctx->opcode);
4346
4347 #if !defined(CONFIG_USER_ONLY)
4348 if (ctx->mem_idx == 2)
4349 write_cb = ctx->spr_cb[sprn].hea_write;
4350 else if (ctx->mem_idx)
4351 write_cb = ctx->spr_cb[sprn].oea_write;
4352 else
4353 #endif
4354 write_cb = ctx->spr_cb[sprn].uea_write;
4355 if (likely(write_cb != NULL)) {
4356 if (likely(write_cb != SPR_NOACCESS)) {
4357 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4358 } else {
4359 /* Privilege exception */
4360 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4361 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4362 printf("Trying to write privileged spr %d (0x%03x) at "
4363 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4365 }
4366 } else {
4367 /* Not defined */
4368 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4369 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4370 printf("Trying to write invalid spr %d (0x%03x) at "
4371 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4372 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4373 }
4374 }
4375
4376 /*** Cache management ***/
4377
4378 /* dcbf */
4379 static void gen_dcbf(DisasContext *ctx)
4380 {
4381 /* XXX: specification says this is treated as a load by the MMU */
4382 TCGv t0;
4383 gen_set_access_type(ctx, ACCESS_CACHE);
4384 t0 = tcg_temp_new();
4385 gen_addr_reg_index(ctx, t0);
4386 gen_qemu_ld8u(ctx, t0, t0);
4387 tcg_temp_free(t0);
4388 }
4389
4390 /* dcbi (Supervisor only) */
4391 static void gen_dcbi(DisasContext *ctx)
4392 {
4393 #if defined(CONFIG_USER_ONLY)
4394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4395 #else
4396 TCGv EA, val;
4397 if (unlikely(!ctx->mem_idx)) {
4398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4399 return;
4400 }
4401 EA = tcg_temp_new();
4402 gen_set_access_type(ctx, ACCESS_CACHE);
4403 gen_addr_reg_index(ctx, EA);
4404 val = tcg_temp_new();
4405 /* XXX: specification says this should be treated as a store by the MMU */
4406 gen_qemu_ld8u(ctx, val, EA);
4407 gen_qemu_st8(ctx, val, EA);
4408 tcg_temp_free(val);
4409 tcg_temp_free(EA);
4410 #endif
4411 }
4412
4413 /* dcdst */
4414 static void gen_dcbst(DisasContext *ctx)
4415 {
4416 /* XXX: specification say this is treated as a load by the MMU */
4417 TCGv t0;
4418 gen_set_access_type(ctx, ACCESS_CACHE);
4419 t0 = tcg_temp_new();
4420 gen_addr_reg_index(ctx, t0);
4421 gen_qemu_ld8u(ctx, t0, t0);
4422 tcg_temp_free(t0);
4423 }
4424
4425 /* dcbt */
4426 static void gen_dcbt(DisasContext *ctx)
4427 {
4428 /* interpreted as no-op */
4429 /* XXX: specification say this is treated as a load by the MMU
4430 * but does not generate any exception
4431 */
4432 }
4433
4434 /* dcbtst */
4435 static void gen_dcbtst(DisasContext *ctx)
4436 {
4437 /* interpreted as no-op */
4438 /* XXX: specification say this is treated as a load by the MMU
4439 * but does not generate any exception
4440 */
4441 }
4442
4443 /* dcbtls */
4444 static void gen_dcbtls(DisasContext *ctx)
4445 {
4446 /* Always fails locking the cache */
4447 TCGv t0 = tcg_temp_new();
4448 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4449 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4450 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4451 tcg_temp_free(t0);
4452 }
4453
4454 /* dcbz */
4455 static void gen_dcbz(DisasContext *ctx)
4456 {
4457 TCGv tcgv_addr;
4458 TCGv_i32 tcgv_is_dcbzl;
4459 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4460
4461 gen_set_access_type(ctx, ACCESS_CACHE);
4462 /* NIP cannot be restored if the memory exception comes from an helper */
4463 gen_update_nip(ctx, ctx->nip - 4);
4464 tcgv_addr = tcg_temp_new();
4465 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4466
4467 gen_addr_reg_index(ctx, tcgv_addr);
4468 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4469
4470 tcg_temp_free(tcgv_addr);
4471 tcg_temp_free_i32(tcgv_is_dcbzl);
4472 }
4473
4474 /* dst / dstt */
4475 static void gen_dst(DisasContext *ctx)
4476 {
4477 if (rA(ctx->opcode) == 0) {
4478 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4479 } else {
4480 /* interpreted as no-op */
4481 }
4482 }
4483
4484 /* dstst /dststt */
4485 static void gen_dstst(DisasContext *ctx)
4486 {
4487 if (rA(ctx->opcode) == 0) {
4488 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4489 } else {
4490 /* interpreted as no-op */
4491 }
4492
4493 }
4494
4495 /* dss / dssall */
4496 static void gen_dss(DisasContext *ctx)
4497 {
4498 /* interpreted as no-op */
4499 }
4500
4501 /* icbi */
4502 static void gen_icbi(DisasContext *ctx)
4503 {
4504 TCGv t0;
4505 gen_set_access_type(ctx, ACCESS_CACHE);
4506 /* NIP cannot be restored if the memory exception comes from an helper */
4507 gen_update_nip(ctx, ctx->nip - 4);
4508 t0 = tcg_temp_new();
4509 gen_addr_reg_index(ctx, t0);
4510 gen_helper_icbi(cpu_env, t0);
4511 tcg_temp_free(t0);
4512 }
4513
4514 /* Optional: */
4515 /* dcba */
4516 static void gen_dcba(DisasContext *ctx)
4517 {
4518 /* interpreted as no-op */
4519 /* XXX: specification say this is treated as a store by the MMU
4520 * but does not generate any exception
4521 */
4522 }
4523
4524 /*** Segment register manipulation ***/
4525 /* Supervisor only: */
4526
4527 /* mfsr */
4528 static void gen_mfsr(DisasContext *ctx)
4529 {
4530 #if defined(CONFIG_USER_ONLY)
4531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4532 #else
4533 TCGv t0;
4534 if (unlikely(!ctx->mem_idx)) {
4535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4536 return;
4537 }
4538 t0 = tcg_const_tl(SR(ctx->opcode));
4539 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4540 tcg_temp_free(t0);
4541 #endif
4542 }
4543
4544 /* mfsrin */
4545 static void gen_mfsrin(DisasContext *ctx)
4546 {
4547 #if defined(CONFIG_USER_ONLY)
4548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4549 #else
4550 TCGv t0;
4551 if (unlikely(!ctx->mem_idx)) {
4552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4553 return;
4554 }
4555 t0 = tcg_temp_new();
4556 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4557 tcg_gen_andi_tl(t0, t0, 0xF);
4558 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4559 tcg_temp_free(t0);
4560 #endif
4561 }
4562
4563 /* mtsr */
4564 static void gen_mtsr(DisasContext *ctx)
4565 {
4566 #if defined(CONFIG_USER_ONLY)
4567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4568 #else
4569 TCGv t0;
4570 if (unlikely(!ctx->mem_idx)) {
4571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4572 return;
4573 }
4574 t0 = tcg_const_tl(SR(ctx->opcode));
4575 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4576 tcg_temp_free(t0);
4577 #endif
4578 }
4579
4580 /* mtsrin */
4581 static void gen_mtsrin(DisasContext *ctx)
4582 {
4583 #if defined(CONFIG_USER_ONLY)
4584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4585 #else
4586 TCGv t0;
4587 if (unlikely(!ctx->mem_idx)) {
4588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4589 return;
4590 }
4591 t0 = tcg_temp_new();
4592 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4593 tcg_gen_andi_tl(t0, t0, 0xF);
4594 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4595 tcg_temp_free(t0);
4596 #endif
4597 }
4598
4599 #if defined(TARGET_PPC64)
4600 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4601
4602 /* mfsr */
4603 static void gen_mfsr_64b(DisasContext *ctx)
4604 {
4605 #if defined(CONFIG_USER_ONLY)
4606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4607 #else
4608 TCGv t0;
4609 if (unlikely(!ctx->mem_idx)) {
4610 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4611 return;
4612 }
4613 t0 = tcg_const_tl(SR(ctx->opcode));
4614 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4615 tcg_temp_free(t0);
4616 #endif
4617 }
4618
4619 /* mfsrin */
4620 static void gen_mfsrin_64b(DisasContext *ctx)
4621 {
4622 #if defined(CONFIG_USER_ONLY)
4623 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4624 #else
4625 TCGv t0;
4626 if (unlikely(!ctx->mem_idx)) {
4627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4628 return;
4629 }
4630 t0 = tcg_temp_new();
4631 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4632 tcg_gen_andi_tl(t0, t0, 0xF);
4633 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4634 tcg_temp_free(t0);
4635 #endif
4636 }
4637
4638 /* mtsr */
4639 static void gen_mtsr_64b(DisasContext *ctx)
4640 {
4641 #if defined(CONFIG_USER_ONLY)
4642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4643 #else
4644 TCGv t0;
4645 if (unlikely(!ctx->mem_idx)) {
4646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4647 return;
4648 }
4649 t0 = tcg_const_tl(SR(ctx->opcode));
4650 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4651 tcg_temp_free(t0);
4652 #endif
4653 }
4654
4655 /* mtsrin */
4656 static void gen_mtsrin_64b(DisasContext *ctx)
4657 {
4658 #if defined(CONFIG_USER_ONLY)
4659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4660 #else
4661 TCGv t0;
4662 if (unlikely(!ctx->mem_idx)) {
4663 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4664 return;
4665 }
4666 t0 = tcg_temp_new();
4667 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4668 tcg_gen_andi_tl(t0, t0, 0xF);
4669 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4670 tcg_temp_free(t0);
4671 #endif
4672 }
4673
4674 /* slbmte */
4675 static void gen_slbmte(DisasContext *ctx)
4676 {
4677 #if defined(CONFIG_USER_ONLY)
4678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4679 #else
4680 if (unlikely(!ctx->mem_idx)) {
4681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4682 return;
4683 }
4684 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4685 cpu_gpr[rS(ctx->opcode)]);
4686 #endif
4687 }
4688
4689 static void gen_slbmfee(DisasContext *ctx)
4690 {
4691 #if defined(CONFIG_USER_ONLY)
4692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4693 #else
4694 if (unlikely(!ctx->mem_idx)) {
4695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4696 return;
4697 }
4698 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4699 cpu_gpr[rB(ctx->opcode)]);
4700 #endif
4701 }
4702
4703 static void gen_slbmfev(DisasContext *ctx)
4704 {
4705 #if defined(CONFIG_USER_ONLY)
4706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4707 #else
4708 if (unlikely(!ctx->mem_idx)) {
4709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4710 return;
4711 }
4712 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4713 cpu_gpr[rB(ctx->opcode)]);
4714 #endif
4715 }
4716 #endif /* defined(TARGET_PPC64) */
4717
4718 /*** Lookaside buffer management ***/
4719 /* Optional & mem_idx only: */
4720
4721 /* tlbia */
4722 static void gen_tlbia(DisasContext *ctx)
4723 {
4724 #if defined(CONFIG_USER_ONLY)
4725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4726 #else
4727 if (unlikely(!ctx->mem_idx)) {
4728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4729 return;
4730 }
4731 gen_helper_tlbia(cpu_env);
4732 #endif
4733 }
4734
4735 /* tlbiel */
4736 static void gen_tlbiel(DisasContext *ctx)
4737 {
4738 #if defined(CONFIG_USER_ONLY)
4739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4740 #else
4741 if (unlikely(!ctx->mem_idx)) {
4742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4743 return;
4744 }
4745 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4746 #endif
4747 }
4748
4749 /* tlbie */
4750 static void gen_tlbie(DisasContext *ctx)
4751 {
4752 #if defined(CONFIG_USER_ONLY)
4753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4754 #else
4755 if (unlikely(!ctx->mem_idx)) {
4756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4757 return;
4758 }
4759 if (NARROW_MODE(ctx)) {
4760 TCGv t0 = tcg_temp_new();
4761 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4762 gen_helper_tlbie(cpu_env, t0);
4763 tcg_temp_free(t0);
4764 } else {
4765 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4766 }
4767 #endif
4768 }
4769
4770 /* tlbsync */
4771 static void gen_tlbsync(DisasContext *ctx)
4772 {
4773 #if defined(CONFIG_USER_ONLY)
4774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4775 #else
4776 if (unlikely(!ctx->mem_idx)) {
4777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4778 return;
4779 }
4780 /* This has no effect: it should ensure that all previous
4781 * tlbie have completed
4782 */
4783 gen_stop_exception(ctx);
4784 #endif
4785 }
4786
4787 #if defined(TARGET_PPC64)
4788 /* slbia */
4789 static void gen_slbia(DisasContext *ctx)
4790 {
4791 #if defined(CONFIG_USER_ONLY)
4792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4793 #else
4794 if (unlikely(!ctx->mem_idx)) {
4795 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4796 return;
4797 }
4798 gen_helper_slbia(cpu_env);
4799 #endif
4800 }
4801
4802 /* slbie */
4803 static void gen_slbie(DisasContext *ctx)
4804 {
4805 #if defined(CONFIG_USER_ONLY)
4806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4807 #else
4808 if (unlikely(!ctx->mem_idx)) {
4809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4810 return;
4811 }
4812 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4813 #endif
4814 }
4815 #endif
4816
4817 /*** External control ***/
4818 /* Optional: */
4819
4820 /* eciwx */
4821 static void gen_eciwx(DisasContext *ctx)
4822 {
4823 TCGv t0;
4824 /* Should check EAR[E] ! */
4825 gen_set_access_type(ctx, ACCESS_EXT);
4826 t0 = tcg_temp_new();
4827 gen_addr_reg_index(ctx, t0);
4828 gen_check_align(ctx, t0, 0x03);
4829 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4830 tcg_temp_free(t0);
4831 }
4832
4833 /* ecowx */
4834 static void gen_ecowx(DisasContext *ctx)
4835 {
4836 TCGv t0;
4837 /* Should check EAR[E] ! */
4838 gen_set_access_type(ctx, ACCESS_EXT);
4839 t0 = tcg_temp_new();
4840 gen_addr_reg_index(ctx, t0);
4841 gen_check_align(ctx, t0, 0x03);
4842 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4843 tcg_temp_free(t0);
4844 }
4845
4846 /* PowerPC 601 specific instructions */
4847
4848 /* abs - abs. */
4849 static void gen_abs(DisasContext *ctx)
4850 {
4851 int l1 = gen_new_label();
4852 int l2 = gen_new_label();
4853 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4854 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4855 tcg_gen_br(l2);
4856 gen_set_label(l1);
4857 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4858 gen_set_label(l2);
4859 if (unlikely(Rc(ctx->opcode) != 0))
4860 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4861 }
4862
4863 /* abso - abso. */
4864 static void gen_abso(DisasContext *ctx)
4865 {
4866 int l1 = gen_new_label();
4867 int l2 = gen_new_label();
4868 int l3 = gen_new_label();
4869 /* Start with XER OV disabled, the most likely case */
4870 tcg_gen_movi_tl(cpu_ov, 0);
4871 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4872 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4873 tcg_gen_movi_tl(cpu_ov, 1);
4874 tcg_gen_movi_tl(cpu_so, 1);
4875 tcg_gen_br(l2);
4876 gen_set_label(l1);
4877 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4878 tcg_gen_br(l3);
4879 gen_set_label(l2);
4880 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4881 gen_set_label(l3);
4882 if (unlikely(Rc(ctx->opcode) != 0))
4883 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4884 }
4885
4886 /* clcs */
4887 static void gen_clcs(DisasContext *ctx)
4888 {
4889 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4890 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4891 tcg_temp_free_i32(t0);
4892 /* Rc=1 sets CR0 to an undefined state */
4893 }
4894
4895 /* div - div. */
4896 static void gen_div(DisasContext *ctx)
4897 {
4898 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4899 cpu_gpr[rB(ctx->opcode)]);
4900 if (unlikely(Rc(ctx->opcode) != 0))
4901 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4902 }
4903
4904 /* divo - divo. */
4905 static void gen_divo(DisasContext *ctx)
4906 {
4907 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4908 cpu_gpr[rB(ctx->opcode)]);
4909 if (unlikely(Rc(ctx->opcode) != 0))
4910 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4911 }
4912
4913 /* divs - divs. */
4914 static void gen_divs(DisasContext *ctx)
4915 {
4916 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4917 cpu_gpr[rB(ctx->opcode)]);
4918 if (unlikely(Rc(ctx->opcode) != 0))
4919 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4920 }
4921
4922 /* divso - divso. */
4923 static void gen_divso(DisasContext *ctx)
4924 {
4925 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4926 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4927 if (unlikely(Rc(ctx->opcode) != 0))
4928 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4929 }
4930
4931 /* doz - doz. */
4932 static void gen_doz(DisasContext *ctx)
4933 {
4934 int l1 = gen_new_label();
4935 int l2 = gen_new_label();
4936 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4937 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4938 tcg_gen_br(l2);
4939 gen_set_label(l1);
4940 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4941 gen_set_label(l2);
4942 if (unlikely(Rc(ctx->opcode) != 0))
4943 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4944 }
4945
4946 /* dozo - dozo. */
4947 static void gen_dozo(DisasContext *ctx)
4948 {
4949 int l1 = gen_new_label();
4950 int l2 = gen_new_label();
4951 TCGv t0 = tcg_temp_new();
4952 TCGv t1 = tcg_temp_new();
4953 TCGv t2 = tcg_temp_new();
4954 /* Start with XER OV disabled, the most likely case */
4955 tcg_gen_movi_tl(cpu_ov, 0);
4956 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4957 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4958 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4959 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4960 tcg_gen_andc_tl(t1, t1, t2);
4961 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4962 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4963 tcg_gen_movi_tl(cpu_ov, 1);
4964 tcg_gen_movi_tl(cpu_so, 1);
4965 tcg_gen_br(l2);
4966 gen_set_label(l1);
4967 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4968 gen_set_label(l2);
4969 tcg_temp_free(t0);
4970 tcg_temp_free(t1);
4971 tcg_temp_free(t2);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4974 }
4975
4976 /* dozi */
4977 static void gen_dozi(DisasContext *ctx)
4978 {
4979 target_long simm = SIMM(ctx->opcode);
4980 int l1 = gen_new_label();
4981 int l2 = gen_new_label();
4982 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4983 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4984 tcg_gen_br(l2);
4985 gen_set_label(l1);
4986 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4987 gen_set_label(l2);
4988 if (unlikely(Rc(ctx->opcode) != 0))
4989 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4990 }
4991
4992 /* lscbx - lscbx. */
4993 static void gen_lscbx(DisasContext *ctx)
4994 {
4995 TCGv t0 = tcg_temp_new();
4996 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4997 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4998 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4999
5000 gen_addr_reg_index(ctx, t0);
5001 /* NIP cannot be restored if the memory exception comes from an helper */
5002 gen_update_nip(ctx, ctx->nip - 4);
5003 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5004 tcg_temp_free_i32(t1);
5005 tcg_temp_free_i32(t2);
5006 tcg_temp_free_i32(t3);
5007 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5008 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5009 if (unlikely(Rc(ctx->opcode) != 0))
5010 gen_set_Rc0(ctx, t0);
5011 tcg_temp_free(t0);
5012 }
5013
5014 /* maskg - maskg. */
5015 static void gen_maskg(DisasContext *ctx)
5016 {
5017 int l1 = gen_new_label();
5018 TCGv t0 = tcg_temp_new();
5019 TCGv t1 = tcg_temp_new();
5020 TCGv t2 = tcg_temp_new();
5021 TCGv t3 = tcg_temp_new();
5022 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5023 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5024 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5025 tcg_gen_addi_tl(t2, t0, 1);
5026 tcg_gen_shr_tl(t2, t3, t2);
5027 tcg_gen_shr_tl(t3, t3, t1);
5028 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5029 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5030 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5031 gen_set_label(l1);
5032 tcg_temp_free(t0);
5033 tcg_temp_free(t1);
5034 tcg_temp_free(t2);
5035 tcg_temp_free(t3);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* maskir - maskir. */
5041 static void gen_maskir(DisasContext *ctx)
5042 {
5043 TCGv t0 = tcg_temp_new();
5044 TCGv t1 = tcg_temp_new();
5045 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5046 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5047 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5048 tcg_temp_free(t0);
5049 tcg_temp_free(t1);
5050 if (unlikely(Rc(ctx->opcode) != 0))
5051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5052 }
5053
5054 /* mul - mul. */
5055 static void gen_mul(DisasContext *ctx)
5056 {
5057 TCGv_i64 t0 = tcg_temp_new_i64();
5058 TCGv_i64 t1 = tcg_temp_new_i64();
5059 TCGv t2 = tcg_temp_new();
5060 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5061 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5062 tcg_gen_mul_i64(t0, t0, t1);
5063 tcg_gen_trunc_i64_tl(t2, t0);
5064 gen_store_spr(SPR_MQ, t2);
5065 tcg_gen_shri_i64(t1, t0, 32);
5066 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5067 tcg_temp_free_i64(t0);
5068 tcg_temp_free_i64(t1);
5069 tcg_temp_free(t2);
5070 if (unlikely(Rc(ctx->opcode) != 0))
5071 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5072 }
5073
5074 /* mulo - mulo. */
5075 static void gen_mulo(DisasContext *ctx)
5076 {
5077 int l1 = gen_new_label();
5078 TCGv_i64 t0 = tcg_temp_new_i64();
5079 TCGv_i64 t1 = tcg_temp_new_i64();
5080 TCGv t2 = tcg_temp_new();
5081 /* Start with XER OV disabled, the most likely case */
5082 tcg_gen_movi_tl(cpu_ov, 0);
5083 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5084 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5085 tcg_gen_mul_i64(t0, t0, t1);
5086 tcg_gen_trunc_i64_tl(t2, t0);
5087 gen_store_spr(SPR_MQ, t2);
5088 tcg_gen_shri_i64(t1, t0, 32);
5089 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5090 tcg_gen_ext32s_i64(t1, t0);
5091 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5092 tcg_gen_movi_tl(cpu_ov, 1);
5093 tcg_gen_movi_tl(cpu_so, 1);
5094 gen_set_label(l1);
5095 tcg_temp_free_i64(t0);
5096 tcg_temp_free_i64(t1);
5097 tcg_temp_free(t2);
5098 if (unlikely(Rc(ctx->opcode) != 0))
5099 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5100 }
5101
5102 /* nabs - nabs. */
5103 static void gen_nabs(DisasContext *ctx)
5104 {
5105 int l1 = gen_new_label();
5106 int l2 = gen_new_label();
5107 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5108 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5109 tcg_gen_br(l2);
5110 gen_set_label(l1);
5111 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5112 gen_set_label(l2);
5113 if (unlikely(Rc(ctx->opcode) != 0))
5114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5115 }
5116
5117 /* nabso - nabso. */
5118 static void gen_nabso(DisasContext *ctx)
5119 {
5120 int l1 = gen_new_label();
5121 int l2 = gen_new_label();
5122 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5123 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5124 tcg_gen_br(l2);
5125 gen_set_label(l1);
5126 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5127 gen_set_label(l2);
5128 /* nabs never overflows */
5129 tcg_gen_movi_tl(cpu_ov, 0);
5130 if (unlikely(Rc(ctx->opcode) != 0))
5131 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5132 }
5133
5134 /* rlmi - rlmi. */
5135 static void gen_rlmi(DisasContext *ctx)
5136 {
5137 uint32_t mb = MB(ctx->opcode);
5138 uint32_t me = ME(ctx->opcode);
5139 TCGv t0 = tcg_temp_new();
5140 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5141 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5142 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5143 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5144 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5145 tcg_temp_free(t0);
5146 if (unlikely(Rc(ctx->opcode) != 0))
5147 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5148 }
5149
5150 /* rrib - rrib. */
5151 static void gen_rrib(DisasContext *ctx)
5152 {
5153 TCGv t0 = tcg_temp_new();
5154 TCGv t1 = tcg_temp_new();
5155 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5156 tcg_gen_movi_tl(t1, 0x80000000);
5157 tcg_gen_shr_tl(t1, t1, t0);
5158 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5159 tcg_gen_and_tl(t0, t0, t1);
5160 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5161 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5162 tcg_temp_free(t0);
5163 tcg_temp_free(t1);
5164 if (unlikely(Rc(ctx->opcode) != 0))
5165 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5166 }
5167
5168 /* sle - sle. */
5169 static void gen_sle(DisasContext *ctx)
5170 {
5171 TCGv t0 = tcg_temp_new();
5172 TCGv t1 = tcg_temp_new();
5173 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5174 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5175 tcg_gen_subfi_tl(t1, 32, t1);
5176 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5177 tcg_gen_or_tl(t1, t0, t1);
5178 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5179 gen_store_spr(SPR_MQ, t1);
5180 tcg_temp_free(t0);
5181 tcg_temp_free(t1);
5182 if (unlikely(Rc(ctx->opcode) != 0))
5183 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5184 }
5185
5186 /* sleq - sleq. */
5187 static void gen_sleq(DisasContext *ctx)
5188 {
5189 TCGv t0 = tcg_temp_new();
5190 TCGv t1 = tcg_temp_new();
5191 TCGv t2 = tcg_temp_new();
5192 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5193 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5194 tcg_gen_shl_tl(t2, t2, t0);
5195 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5196 gen_load_spr(t1, SPR_MQ);
5197 gen_store_spr(SPR_MQ, t0);
5198 tcg_gen_and_tl(t0, t0, t2);
5199 tcg_gen_andc_tl(t1, t1, t2);
5200 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5201 tcg_temp_free(t0);
5202 tcg_temp_free(t1);
5203 tcg_temp_free(t2);
5204 if (unlikely(Rc(ctx->opcode) != 0))
5205 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5206 }
5207
5208 /* sliq - sliq. */
5209 static void gen_sliq(DisasContext *ctx)
5210 {
5211 int sh = SH(ctx->opcode);
5212 TCGv t0 = tcg_temp_new();
5213 TCGv t1 = tcg_temp_new();
5214 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5215 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5216 tcg_gen_or_tl(t1, t0, t1);
5217 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5218 gen_store_spr(SPR_MQ, t1);
5219 tcg_temp_free(t0);
5220 tcg_temp_free(t1);
5221 if (unlikely(Rc(ctx->opcode) != 0))
5222 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5223 }
5224
5225 /* slliq - slliq. */
5226 static void gen_slliq(DisasContext *ctx)
5227 {
5228 int sh = SH(ctx->opcode);
5229 TCGv t0 = tcg_temp_new();
5230 TCGv t1 = tcg_temp_new();
5231 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5232 gen_load_spr(t1, SPR_MQ);
5233 gen_store_spr(SPR_MQ, t0);
5234 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5235 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5236 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5237 tcg_temp_free(t0);
5238 tcg_temp_free(t1);
5239 if (unlikely(Rc(ctx->opcode) != 0))
5240 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5241 }
5242
5243 /* sllq - sllq. */
5244 static void gen_sllq(DisasContext *ctx)
5245 {
5246 int l1 = gen_new_label();
5247 int l2 = gen_new_label();
5248 TCGv t0 = tcg_temp_local_new();
5249 TCGv t1 = tcg_temp_local_new();
5250 TCGv t2 = tcg_temp_local_new();
5251 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5252 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5253 tcg_gen_shl_tl(t1, t1, t2);
5254 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5255 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5256 gen_load_spr(t0, SPR_MQ);
5257 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5258 tcg_gen_br(l2);
5259 gen_set_label(l1);
5260 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5261 gen_load_spr(t2, SPR_MQ);
5262 tcg_gen_andc_tl(t1, t2, t1);
5263 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5264 gen_set_label(l2);
5265 tcg_temp_free(t0);
5266 tcg_temp_free(t1);
5267 tcg_temp_free(t2);
5268 if (unlikely(Rc(ctx->opcode) != 0))
5269 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5270 }
5271
5272 /* slq - slq. */
5273 static void gen_slq(DisasContext *ctx)
5274 {
5275 int l1 = gen_new_label();
5276 TCGv t0 = tcg_temp_new();
5277 TCGv t1 = tcg_temp_new();
5278 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5279 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5280 tcg_gen_subfi_tl(t1, 32, t1);
5281 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5282 tcg_gen_or_tl(t1, t0, t1);
5283 gen_store_spr(SPR_MQ, t1);
5284 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5285 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5286 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5287 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5288 gen_set_label(l1);
5289 tcg_temp_free(t0);
5290 tcg_temp_free(t1);
5291 if (unlikely(Rc(ctx->opcode) != 0))
5292 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5293 }
5294
5295 /* sraiq - sraiq. */
5296 static void gen_sraiq(DisasContext *ctx)
5297 {
5298 int sh = SH(ctx->opcode);
5299 int l1 = gen_new_label();
5300 TCGv t0 = tcg_temp_new();
5301 TCGv t1 = tcg_temp_new();
5302 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5303 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5304 tcg_gen_or_tl(t0, t0, t1);
5305 gen_store_spr(SPR_MQ, t0);
5306 tcg_gen_movi_tl(cpu_ca, 0);
5307 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5308 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5309 tcg_gen_movi_tl(cpu_ca, 1);
5310 gen_set_label(l1);
5311 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5312 tcg_temp_free(t0);
5313 tcg_temp_free(t1);
5314 if (unlikely(Rc(ctx->opcode) != 0))
5315 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5316 }
5317
5318 /* sraq - sraq. */
5319 static void gen_sraq(DisasContext *ctx)
5320 {
5321 int l1 = gen_new_label();
5322 int l2 = gen_new_label();
5323 TCGv t0 = tcg_temp_new();
5324 TCGv t1 = tcg_temp_local_new();
5325 TCGv t2 = tcg_temp_local_new();
5326 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5327 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5328 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5329 tcg_gen_subfi_tl(t2, 32, t2);
5330 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5331 tcg_gen_or_tl(t0, t0, t2);
5332 gen_store_spr(SPR_MQ, t0);
5333 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5334 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5335 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5336 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5337 gen_set_label(l1);
5338 tcg_temp_free(t0);
5339 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5340 tcg_gen_movi_tl(cpu_ca, 0);
5341 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5342 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5343 tcg_gen_movi_tl(cpu_ca, 1);
5344 gen_set_label(l2);
5345 tcg_temp_free(t1);
5346 tcg_temp_free(t2);
5347 if (unlikely(Rc(ctx->opcode) != 0))
5348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5349 }
5350
5351 /* sre - sre. */
5352 static void gen_sre(DisasContext *ctx)
5353 {
5354 TCGv t0 = tcg_temp_new();
5355 TCGv t1 = tcg_temp_new();
5356 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5357 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5358 tcg_gen_subfi_tl(t1, 32, t1);
5359 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5360 tcg_gen_or_tl(t1, t0, t1);
5361 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5362 gen_store_spr(SPR_MQ, t1);
5363 tcg_temp_free(t0);
5364 tcg_temp_free(t1);
5365 if (unlikely(Rc(ctx->opcode) != 0))
5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5367 }
5368
5369 /* srea - srea. */
5370 static void gen_srea(DisasContext *ctx)
5371 {
5372 TCGv t0 = tcg_temp_new();
5373 TCGv t1 = tcg_temp_new();
5374 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5375 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5376 gen_store_spr(SPR_MQ, t0);
5377 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5378 tcg_temp_free(t0);
5379 tcg_temp_free(t1);
5380 if (unlikely(Rc(ctx->opcode) != 0))
5381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5382 }
5383
5384 /* sreq */
5385 static void gen_sreq(DisasContext *ctx)
5386 {
5387 TCGv t0 = tcg_temp_new();
5388 TCGv t1 = tcg_temp_new();
5389 TCGv t2 = tcg_temp_new();
5390 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5391 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5392 tcg_gen_shr_tl(t1, t1, t0);
5393 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5394 gen_load_spr(t2, SPR_MQ);
5395 gen_store_spr(SPR_MQ, t0);
5396 tcg_gen_and_tl(t0, t0, t1);
5397 tcg_gen_andc_tl(t2, t2, t1);
5398 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5399 tcg_temp_free(t0);
5400 tcg_temp_free(t1);
5401 tcg_temp_free(t2);
5402 if (unlikely(Rc(ctx->opcode) != 0))
5403 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5404 }
5405
5406 /* sriq */
5407 static void gen_sriq(DisasContext *ctx)
5408 {
5409 int sh = SH(ctx->opcode);
5410 TCGv t0 = tcg_temp_new();
5411 TCGv t1 = tcg_temp_new();
5412 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5413 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5414 tcg_gen_or_tl(t1, t0, t1);
5415 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5416 gen_store_spr(SPR_MQ, t1);
5417 tcg_temp_free(t0);
5418 tcg_temp_free(t1);
5419 if (unlikely(Rc(ctx->opcode) != 0))
5420 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5421 }
5422
5423 /* srliq */
5424 static void gen_srliq(DisasContext *ctx)
5425 {
5426 int sh = SH(ctx->opcode);
5427 TCGv t0 = tcg_temp_new();
5428 TCGv t1 = tcg_temp_new();
5429 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5430 gen_load_spr(t1, SPR_MQ);
5431 gen_store_spr(SPR_MQ, t0);
5432 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5433 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5434 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5435 tcg_temp_free(t0);
5436 tcg_temp_free(t1);
5437 if (unlikely(Rc(ctx->opcode) != 0))
5438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5439 }
5440
5441 /* srlq */
5442 static void gen_srlq(DisasContext *ctx)
5443 {
5444 int l1 = gen_new_label();
5445 int l2 = gen_new_label();
5446 TCGv t0 = tcg_temp_local_new();
5447 TCGv t1 = tcg_temp_local_new();
5448 TCGv t2 = tcg_temp_local_new();
5449 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5450 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5451 tcg_gen_shr_tl(t2, t1, t2);
5452 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5453 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5454 gen_load_spr(t0, SPR_MQ);
5455 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5456 tcg_gen_br(l2);
5457 gen_set_label(l1);
5458 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5459 tcg_gen_and_tl(t0, t0, t2);
5460 gen_load_spr(t1, SPR_MQ);
5461 tcg_gen_andc_tl(t1, t1, t2);
5462 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5463 gen_set_label(l2);
5464 tcg_temp_free(t0);
5465 tcg_temp_free(t1);
5466 tcg_temp_free(t2);
5467 if (unlikely(Rc(ctx->opcode) != 0))
5468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5469 }
5470
5471 /* srq */
5472 static void gen_srq(DisasContext *ctx)
5473 {
5474 int l1 = gen_new_label();
5475 TCGv t0 = tcg_temp_new();
5476 TCGv t1 = tcg_temp_new();
5477 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5478 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5479 tcg_gen_subfi_tl(t1, 32, t1);
5480 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5481 tcg_gen_or_tl(t1, t0, t1);
5482 gen_store_spr(SPR_MQ, t1);
5483 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5484 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5485 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5486 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5487 gen_set_label(l1);
5488 tcg_temp_free(t0);
5489 tcg_temp_free(t1);
5490 if (unlikely(Rc(ctx->opcode) != 0))
5491 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5492 }
5493
5494 /* PowerPC 602 specific instructions */
5495
5496 /* dsa */
5497 static void gen_dsa(DisasContext *ctx)
5498 {
5499 /* XXX: TODO */
5500 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5501 }
5502
5503 /* esa */
5504 static void gen_esa(DisasContext *ctx)
5505 {
5506 /* XXX: TODO */
5507 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5508 }
5509
5510 /* mfrom */
5511 static void gen_mfrom(DisasContext *ctx)
5512 {
5513 #if defined(CONFIG_USER_ONLY)
5514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5515 #else
5516 if (unlikely(!ctx->mem_idx)) {
5517 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5518 return;
5519 }
5520 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5521 #endif
5522 }
5523
5524 /* 602 - 603 - G2 TLB management */
5525
5526 /* tlbld */
5527 static void gen_tlbld_6xx(DisasContext *ctx)
5528 {
5529 #if defined(CONFIG_USER_ONLY)
5530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5531 #else
5532 if (unlikely(!ctx->mem_idx)) {
5533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5534 return;
5535 }
5536 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5537 #endif
5538 }
5539
5540 /* tlbli */
5541 static void gen_tlbli_6xx(DisasContext *ctx)
5542 {
5543 #if defined(CONFIG_USER_ONLY)
5544 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5545 #else
5546 if (unlikely(!ctx->mem_idx)) {
5547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5548 return;
5549 }
5550 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5551 #endif
5552 }
5553
5554 /* 74xx TLB management */
5555
5556 /* tlbld */
5557 static void gen_tlbld_74xx(DisasContext *ctx)
5558 {
5559 #if defined(CONFIG_USER_ONLY)
5560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5561 #else
5562 if (unlikely(!ctx->mem_idx)) {
5563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5564 return;
5565 }
5566 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5567 #endif
5568 }
5569
5570 /* tlbli */
5571 static void gen_tlbli_74xx(DisasContext *ctx)
5572 {
5573 #if defined(CONFIG_USER_ONLY)
5574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5575 #else
5576 if (unlikely(!ctx->mem_idx)) {
5577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5578 return;
5579 }
5580 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5581 #endif
5582 }
5583
5584 /* POWER instructions not in PowerPC 601 */
5585
5586 /* clf */
5587 static void gen_clf(DisasContext *ctx)
5588 {
5589 /* Cache line flush: implemented as no-op */
5590 }
5591
5592 /* cli */
5593 static void gen_cli(DisasContext *ctx)
5594 {
5595 /* Cache line invalidate: privileged and treated as no-op */
5596 #if defined(CONFIG_USER_ONLY)
5597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5598 #else
5599 if (unlikely(!ctx->mem_idx)) {
5600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5601 return;
5602 }
5603 #endif
5604 }
5605
5606 /* dclst */
5607 static void gen_dclst(DisasContext *ctx)
5608 {
5609 /* Data cache line store: treated as no-op */
5610 }
5611
5612 static void gen_mfsri(DisasContext *ctx)
5613 {
5614 #if defined(CONFIG_USER_ONLY)
5615 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5616 #else
5617 int ra = rA(ctx->opcode);
5618 int rd = rD(ctx->opcode);
5619 TCGv t0;
5620 if (unlikely(!ctx->mem_idx)) {
5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5622 return;
5623 }
5624 t0 = tcg_temp_new();
5625 gen_addr_reg_index(ctx, t0);
5626 tcg_gen_shri_tl(t0, t0, 28);
5627 tcg_gen_andi_tl(t0, t0, 0xF);
5628 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5629 tcg_temp_free(t0);
5630 if (ra != 0 && ra != rd)
5631 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5632 #endif
5633 }
5634
5635 static void gen_rac(DisasContext *ctx)
5636 {
5637 #if defined(CONFIG_USER_ONLY)
5638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5639 #else
5640 TCGv t0;
5641 if (unlikely(!ctx->mem_idx)) {
5642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5643 return;
5644 }
5645 t0 = tcg_temp_new();
5646 gen_addr_reg_index(ctx, t0);
5647 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5648 tcg_temp_free(t0);
5649 #endif
5650 }
5651
5652 static void gen_rfsvc(DisasContext *ctx)
5653 {
5654 #if defined(CONFIG_USER_ONLY)
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5656 #else
5657 if (unlikely(!ctx->mem_idx)) {
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5659 return;
5660 }
5661 gen_helper_rfsvc(cpu_env);
5662 gen_sync_exception(ctx);
5663 #endif
5664 }
5665
5666 /* svc is not implemented for now */
5667
5668 /* POWER2 specific instructions */
5669 /* Quad manipulation (load/store two floats at a time) */
5670
5671 /* lfq */
5672 static void gen_lfq(DisasContext *ctx)
5673 {
5674 int rd = rD(ctx->opcode);
5675 TCGv t0;
5676 gen_set_access_type(ctx, ACCESS_FLOAT);
5677 t0 = tcg_temp_new();
5678 gen_addr_imm_index(ctx, t0, 0);
5679 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5680 gen_addr_add(ctx, t0, t0, 8);
5681 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5682 tcg_temp_free(t0);
5683 }
5684
5685 /* lfqu */
5686 static void gen_lfqu(DisasContext *ctx)
5687 {
5688 int ra = rA(ctx->opcode);
5689 int rd = rD(ctx->opcode);
5690 TCGv t0, t1;
5691 gen_set_access_type(ctx, ACCESS_FLOAT);
5692 t0 = tcg_temp_new();
5693 t1 = tcg_temp_new();
5694 gen_addr_imm_index(ctx, t0, 0);
5695 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5696 gen_addr_add(ctx, t1, t0, 8);
5697 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5698 if (ra != 0)
5699 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5700 tcg_temp_free(t0);
5701 tcg_temp_free(t1);
5702 }
5703
5704 /* lfqux */
5705 static void gen_lfqux(DisasContext *ctx)
5706 {
5707 int ra = rA(ctx->opcode);
5708 int rd = rD(ctx->opcode);
5709 gen_set_access_type(ctx, ACCESS_FLOAT);
5710 TCGv t0, t1;
5711 t0 = tcg_temp_new();
5712 gen_addr_reg_index(ctx, t0);
5713 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5714 t1 = tcg_temp_new();
5715 gen_addr_add(ctx, t1, t0, 8);
5716 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5717 tcg_temp_free(t1);
5718 if (ra != 0)
5719 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5720 tcg_temp_free(t0);
5721 }
5722
5723 /* lfqx */
5724 static void gen_lfqx(DisasContext *ctx)
5725 {
5726 int rd = rD(ctx->opcode);
5727 TCGv t0;
5728 gen_set_access_type(ctx, ACCESS_FLOAT);
5729 t0 = tcg_temp_new();
5730 gen_addr_reg_index(ctx, t0);
5731 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5732 gen_addr_add(ctx, t0, t0, 8);
5733 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5734 tcg_temp_free(t0);
5735 }
5736
5737 /* stfq */
5738 static void gen_stfq(DisasContext *ctx)
5739 {
5740 int rd = rD(ctx->opcode);
5741 TCGv t0;
5742 gen_set_access_type(ctx, ACCESS_FLOAT);
5743 t0 = tcg_temp_new();
5744 gen_addr_imm_index(ctx, t0, 0);
5745 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5746 gen_addr_add(ctx, t0, t0, 8);
5747 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5748 tcg_temp_free(t0);
5749 }
5750
5751 /* stfqu */
5752 static void gen_stfqu(DisasContext *ctx)
5753 {
5754 int ra = rA(ctx->opcode);
5755 int rd = rD(ctx->opcode);
5756 TCGv t0, t1;
5757 gen_set_access_type(ctx, ACCESS_FLOAT);
5758 t0 = tcg_temp_new();
5759 gen_addr_imm_index(ctx, t0, 0);
5760 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5761 t1 = tcg_temp_new();
5762 gen_addr_add(ctx, t1, t0, 8);
5763 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5764 tcg_temp_free(t1);
5765 if (ra != 0)
5766 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5767 tcg_temp_free(t0);
5768 }
5769
5770 /* stfqux */
5771 static void gen_stfqux(DisasContext *ctx)
5772 {
5773 int ra = rA(ctx->opcode);
5774 int rd = rD(ctx->opcode);
5775 TCGv t0, t1;
5776 gen_set_access_type(ctx, ACCESS_FLOAT);
5777 t0 = tcg_temp_new();
5778 gen_addr_reg_index(ctx, t0);
5779 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5780 t1 = tcg_temp_new();
5781 gen_addr_add(ctx, t1, t0, 8);
5782 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5783 tcg_temp_free(t1);
5784 if (ra != 0)
5785 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5786 tcg_temp_free(t0);
5787 }
5788
5789 /* stfqx */
5790 static void gen_stfqx(DisasContext *ctx)
5791 {
5792 int rd = rD(ctx->opcode);
5793 TCGv t0;
5794 gen_set_access_type(ctx, ACCESS_FLOAT);
5795 t0 = tcg_temp_new();
5796 gen_addr_reg_index(ctx, t0);
5797 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5798 gen_addr_add(ctx, t0, t0, 8);
5799 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5800 tcg_temp_free(t0);
5801 }
5802
5803 /* BookE specific instructions */
5804
5805 /* XXX: not implemented on 440 ? */
5806 static void gen_mfapidi(DisasContext *ctx)
5807 {
5808 /* XXX: TODO */
5809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5810 }
5811
5812 /* XXX: not implemented on 440 ? */
5813 static void gen_tlbiva(DisasContext *ctx)
5814 {
5815 #if defined(CONFIG_USER_ONLY)
5816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5817 #else
5818 TCGv t0;
5819 if (unlikely(!ctx->mem_idx)) {
5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5821 return;
5822 }
5823 t0 = tcg_temp_new();
5824 gen_addr_reg_index(ctx, t0);
5825 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5826 tcg_temp_free(t0);
5827 #endif
5828 }
5829
5830 /* All 405 MAC instructions are translated here */
5831 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5832 int ra, int rb, int rt, int Rc)
5833 {
5834 TCGv t0, t1;
5835
5836 t0 = tcg_temp_local_new();
5837 t1 = tcg_temp_local_new();
5838
5839 switch (opc3 & 0x0D) {
5840 case 0x05:
5841 /* macchw - macchw. - macchwo - macchwo. */
5842 /* macchws - macchws. - macchwso - macchwso. */
5843 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5844 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5845 /* mulchw - mulchw. */
5846 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5847 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5848 tcg_gen_ext16s_tl(t1, t1);
5849 break;
5850 case 0x04:
5851 /* macchwu - macchwu. - macchwuo - macchwuo. */
5852 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5853 /* mulchwu - mulchwu. */
5854 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5855 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5856 tcg_gen_ext16u_tl(t1, t1);
5857 break;
5858 case 0x01:
5859 /* machhw - machhw. - machhwo - machhwo. */
5860 /* machhws - machhws. - machhwso - machhwso. */
5861 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5862 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5863 /* mulhhw - mulhhw. */
5864 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5865 tcg_gen_ext16s_tl(t0, t0);
5866 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5867 tcg_gen_ext16s_tl(t1, t1);
5868 break;
5869 case 0x00:
5870 /* machhwu - machhwu. - machhwuo - machhwuo. */
5871 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5872 /* mulhhwu - mulhhwu. */
5873 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5874 tcg_gen_ext16u_tl(t0, t0);
5875 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5876 tcg_gen_ext16u_tl(t1, t1);
5877 break;
5878 case 0x0D:
5879 /* maclhw - maclhw. - maclhwo - maclhwo. */
5880 /* maclhws - maclhws. - maclhwso - maclhwso. */
5881 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5882 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5883 /* mullhw - mullhw. */
5884 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5885 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5886 break;
5887 case 0x0C:
5888 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5889 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5890 /* mullhwu - mullhwu. */
5891 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5892 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5893 break;
5894 }
5895 if (opc2 & 0x04) {
5896 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5897 tcg_gen_mul_tl(t1, t0, t1);
5898 if (opc2 & 0x02) {
5899 /* nmultiply-and-accumulate (0x0E) */
5900 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5901 } else {
5902 /* multiply-and-accumulate (0x0C) */
5903 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5904 }
5905
5906 if (opc3 & 0x12) {
5907 /* Check overflow and/or saturate */
5908 int l1 = gen_new_label();
5909
5910 if (opc3 & 0x10) {
5911 /* Start with XER OV disabled, the most likely case */
5912 tcg_gen_movi_tl(cpu_ov, 0);
5913 }
5914 if (opc3 & 0x01) {
5915 /* Signed */
5916 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5917 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5918 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5919 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5920 if (opc3 & 0x02) {
5921 /* Saturate */
5922 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5923 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5924 }
5925 } else {
5926 /* Unsigned */
5927 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5928 if (opc3 & 0x02) {
5929 /* Saturate */
5930 tcg_gen_movi_tl(t0, UINT32_MAX);
5931 }
5932 }
5933 if (opc3 & 0x10) {
5934 /* Check overflow */
5935 tcg_gen_movi_tl(cpu_ov, 1);
5936 tcg_gen_movi_tl(cpu_so, 1);
5937 }
5938 gen_set_label(l1);
5939 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5940 }
5941 } else {
5942 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5943 }
5944 tcg_temp_free(t0);
5945 tcg_temp_free(t1);
5946 if (unlikely(Rc) != 0) {
5947 /* Update Rc0 */
5948 gen_set_Rc0(ctx, cpu_gpr[rt]);
5949 }
5950 }
5951
5952 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5953 static void glue(gen_, name)(DisasContext *ctx) \
5954 { \
5955 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5956 rD(ctx->opcode), Rc(ctx->opcode)); \
5957 }
5958
5959 /* macchw - macchw. */
5960 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5961 /* macchwo - macchwo. */
5962 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5963 /* macchws - macchws. */
5964 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5965 /* macchwso - macchwso. */
5966 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5967 /* macchwsu - macchwsu. */
5968 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5969 /* macchwsuo - macchwsuo. */
5970 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5971 /* macchwu - macchwu. */
5972 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5973 /* macchwuo - macchwuo. */
5974 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5975 /* machhw - machhw. */
5976 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5977 /* machhwo - machhwo. */
5978 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5979 /* machhws - machhws. */
5980 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5981 /* machhwso - machhwso. */
5982 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5983 /* machhwsu - machhwsu. */
5984 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5985 /* machhwsuo - machhwsuo. */
5986 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5987 /* machhwu - machhwu. */
5988 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5989 /* machhwuo - machhwuo. */
5990 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5991 /* maclhw - maclhw. */
5992 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5993 /* maclhwo - maclhwo. */
5994 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5995 /* maclhws - maclhws. */
5996 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5997 /* maclhwso - maclhwso. */
5998 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5999 /* maclhwu - maclhwu. */
6000 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6001 /* maclhwuo - maclhwuo. */
6002 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6003 /* maclhwsu - maclhwsu. */
6004 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6005 /* maclhwsuo - maclhwsuo. */
6006 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6007 /* nmacchw - nmacchw. */
6008 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6009 /* nmacchwo - nmacchwo. */
6010 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6011 /* nmacchws - nmacchws. */
6012 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6013 /* nmacchwso - nmacchwso. */
6014 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6015 /* nmachhw - nmachhw. */
6016 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6017 /* nmachhwo - nmachhwo. */
6018 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6019 /* nmachhws - nmachhws. */
6020 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6021 /* nmachhwso - nmachhwso. */
6022 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6023 /* nmaclhw - nmaclhw. */
6024 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6025 /* nmaclhwo - nmaclhwo. */
6026 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6027 /* nmaclhws - nmaclhws. */
6028 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6029 /* nmaclhwso - nmaclhwso. */
6030 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6031
6032 /* mulchw - mulchw. */
6033 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6034 /* mulchwu - mulchwu. */
6035 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6036 /* mulhhw - mulhhw. */
6037 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6038 /* mulhhwu - mulhhwu. */
6039 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6040 /* mullhw - mullhw. */
6041 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6042 /* mullhwu - mullhwu. */
6043 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6044
6045 /* mfdcr */
6046 static void gen_mfdcr(DisasContext *ctx)
6047 {
6048 #if defined(CONFIG_USER_ONLY)
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6050 #else
6051 TCGv dcrn;
6052 if (unlikely(!ctx->mem_idx)) {
6053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6054 return;
6055 }
6056 /* NIP cannot be restored if the memory exception comes from an helper */
6057 gen_update_nip(ctx, ctx->nip - 4);
6058 dcrn = tcg_const_tl(SPR(ctx->opcode));
6059 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6060 tcg_temp_free(dcrn);
6061 #endif
6062 }
6063
6064 /* mtdcr */
6065 static void gen_mtdcr(DisasContext *ctx)
6066 {
6067 #if defined(CONFIG_USER_ONLY)
6068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6069 #else
6070 TCGv dcrn;
6071 if (unlikely(!ctx->mem_idx)) {
6072 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6073 return;
6074 }
6075 /* NIP cannot be restored if the memory exception comes from an helper */
6076 gen_update_nip(ctx, ctx->nip - 4);
6077 dcrn = tcg_const_tl(SPR(ctx->opcode));
6078 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6079 tcg_temp_free(dcrn);
6080 #endif
6081 }
6082
6083 /* mfdcrx */
6084 /* XXX: not implemented on 440 ? */
6085 static void gen_mfdcrx(DisasContext *ctx)
6086 {
6087 #if defined(CONFIG_USER_ONLY)
6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6089 #else
6090 if (unlikely(!ctx->mem_idx)) {
6091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6092 return;
6093 }
6094 /* NIP cannot be restored if the memory exception comes from an helper */
6095 gen_update_nip(ctx, ctx->nip - 4);
6096 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6097 cpu_gpr[rA(ctx->opcode)]);
6098 /* Note: Rc update flag set leads to undefined state of Rc0 */
6099 #endif
6100 }
6101
6102 /* mtdcrx */
6103 /* XXX: not implemented on 440 ? */
6104 static void gen_mtdcrx(DisasContext *ctx)
6105 {
6106 #if defined(CONFIG_USER_ONLY)
6107 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6108 #else
6109 if (unlikely(!ctx->mem_idx)) {
6110 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6111 return;
6112 }
6113 /* NIP cannot be restored if the memory exception comes from an helper */
6114 gen_update_nip(ctx, ctx->nip - 4);
6115 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6116 cpu_gpr[rS(ctx->opcode)]);
6117 /* Note: Rc update flag set leads to undefined state of Rc0 */
6118 #endif
6119 }
6120
6121 /* mfdcrux (PPC 460) : user-mode access to DCR */
6122 static void gen_mfdcrux(DisasContext *ctx)
6123 {
6124 /* NIP cannot be restored if the memory exception comes from an helper */
6125 gen_update_nip(ctx, ctx->nip - 4);
6126 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6127 cpu_gpr[rA(ctx->opcode)]);
6128 /* Note: Rc update flag set leads to undefined state of Rc0 */
6129 }
6130
6131 /* mtdcrux (PPC 460) : user-mode access to DCR */
6132 static void gen_mtdcrux(DisasContext *ctx)
6133 {
6134 /* NIP cannot be restored if the memory exception comes from an helper */
6135 gen_update_nip(ctx, ctx->nip - 4);
6136 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6137 cpu_gpr[rS(ctx->opcode)]);
6138 /* Note: Rc update flag set leads to undefined state of Rc0 */
6139 }
6140
6141 /* dccci */
6142 static void gen_dccci(DisasContext *ctx)
6143 {
6144 #if defined(CONFIG_USER_ONLY)
6145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6146 #else
6147 if (unlikely(!ctx->mem_idx)) {
6148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6149 return;
6150 }
6151 /* interpreted as no-op */
6152 #endif
6153 }
6154
6155 /* dcread */
6156 static void gen_dcread(DisasContext *ctx)
6157 {
6158 #if defined(CONFIG_USER_ONLY)
6159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6160 #else
6161 TCGv EA, val;
6162 if (unlikely(!ctx->mem_idx)) {
6163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6164 return;
6165 }
6166 gen_set_access_type(ctx, ACCESS_CACHE);
6167 EA = tcg_temp_new();
6168 gen_addr_reg_index(ctx, EA);
6169 val = tcg_temp_new();
6170 gen_qemu_ld32u(ctx, val, EA);
6171 tcg_temp_free(val);
6172 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6173 tcg_temp_free(EA);
6174 #endif
6175 }
6176
6177 /* icbt */
6178 static void gen_icbt_40x(DisasContext *ctx)
6179 {
6180 /* interpreted as no-op */
6181 /* XXX: specification say this is treated as a load by the MMU
6182 * but does not generate any exception
6183 */
6184 }
6185
6186 /* iccci */
6187 static void gen_iccci(DisasContext *ctx)
6188 {
6189 #if defined(CONFIG_USER_ONLY)
6190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6191 #else
6192 if (unlikely(!ctx->mem_idx)) {
6193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6194 return;
6195 }
6196 /* interpreted as no-op */
6197 #endif
6198 }
6199
6200 /* icread */
6201 static void gen_icread(DisasContext *ctx)
6202 {
6203 #if defined(CONFIG_USER_ONLY)
6204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6205 #else
6206 if (unlikely(!ctx->mem_idx)) {
6207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6208 return;
6209 }
6210 /* interpreted as no-op */
6211 #endif
6212 }
6213
6214 /* rfci (mem_idx only) */
6215 static void gen_rfci_40x(DisasContext *ctx)
6216 {
6217 #if defined(CONFIG_USER_ONLY)
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6219 #else
6220 if (unlikely(!ctx->mem_idx)) {
6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6222 return;
6223 }
6224 /* Restore CPU state */
6225 gen_helper_40x_rfci(cpu_env);
6226 gen_sync_exception(ctx);
6227 #endif
6228 }
6229
6230 static void gen_rfci(DisasContext *ctx)
6231 {
6232 #if defined(CONFIG_USER_ONLY)
6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6234 #else
6235 if (unlikely(!ctx->mem_idx)) {
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 return;
6238 }
6239 /* Restore CPU state */
6240 gen_helper_rfci(cpu_env);
6241 gen_sync_exception(ctx);
6242 #endif
6243 }
6244
6245 /* BookE specific */
6246
6247 /* XXX: not implemented on 440 ? */
6248 static void gen_rfdi(DisasContext *ctx)
6249 {
6250 #if defined(CONFIG_USER_ONLY)
6251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6252 #else
6253 if (unlikely(!ctx->mem_idx)) {
6254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6255 return;
6256 }
6257 /* Restore CPU state */
6258 gen_helper_rfdi(cpu_env);
6259 gen_sync_exception(ctx);
6260 #endif
6261 }
6262
6263 /* XXX: not implemented on 440 ? */
6264 static void gen_rfmci(DisasContext *ctx)
6265 {
6266 #if defined(CONFIG_USER_ONLY)
6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6268 #else
6269 if (unlikely(!ctx->mem_idx)) {
6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6271 return;
6272 }
6273 /* Restore CPU state */
6274 gen_helper_rfmci(cpu_env);
6275 gen_sync_exception(ctx);
6276 #endif
6277 }
6278
6279 /* TLB management - PowerPC 405 implementation */
6280
6281 /* tlbre */
6282 static void gen_tlbre_40x(DisasContext *ctx)
6283 {
6284 #if defined(CONFIG_USER_ONLY)
6285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6286 #else
6287 if (unlikely(!ctx->mem_idx)) {
6288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6289 return;
6290 }
6291 switch (rB(ctx->opcode)) {
6292 case 0:
6293 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6294 cpu_gpr[rA(ctx->opcode)]);
6295 break;
6296 case 1:
6297 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6298 cpu_gpr[rA(ctx->opcode)]);
6299 break;
6300 default:
6301 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6302 break;
6303 }
6304 #endif
6305 }
6306
6307 /* tlbsx - tlbsx. */
6308 static void gen_tlbsx_40x(DisasContext *ctx)
6309 {
6310 #if defined(CONFIG_USER_ONLY)
6311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6312 #else
6313 TCGv t0;
6314 if (unlikely(!ctx->mem_idx)) {
6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6316 return;
6317 }
6318 t0 = tcg_temp_new();
6319 gen_addr_reg_index(ctx, t0);
6320 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6321 tcg_temp_free(t0);
6322 if (Rc(ctx->opcode)) {
6323 int l1 = gen_new_label();
6324 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6325 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6326 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6327 gen_set_label(l1);
6328 }
6329 #endif
6330 }
6331
6332 /* tlbwe */
6333 static void gen_tlbwe_40x(DisasContext *ctx)
6334 {
6335 #if defined(CONFIG_USER_ONLY)
6336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6337 #else
6338 if (unlikely(!ctx->mem_idx)) {
6339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6340 return;
6341 }
6342 switch (rB(ctx->opcode)) {
6343 case 0:
6344 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6345 cpu_gpr[rS(ctx->opcode)]);
6346 break;
6347 case 1:
6348 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6349 cpu_gpr[rS(ctx->opcode)]);
6350 break;
6351 default:
6352 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6353 break;
6354 }
6355 #endif
6356 }
6357
6358 /* TLB management - PowerPC 440 implementation */
6359
6360 /* tlbre */
6361 static void gen_tlbre_440(DisasContext *ctx)
6362 {
6363 #if defined(CONFIG_USER_ONLY)
6364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6365 #else
6366 if (unlikely(!ctx->mem_idx)) {
6367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6368 return;
6369 }
6370 switch (rB(ctx->opcode)) {
6371 case 0:
6372 case 1:
6373 case 2:
6374 {
6375 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6376 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6377 t0, cpu_gpr[rA(ctx->opcode)]);
6378 tcg_temp_free_i32(t0);
6379 }
6380 break;
6381 default:
6382 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6383 break;
6384 }
6385 #endif
6386 }
6387
6388 /* tlbsx - tlbsx. */
6389 static void gen_tlbsx_440(DisasContext *ctx)
6390 {
6391 #if defined(CONFIG_USER_ONLY)
6392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6393 #else
6394 TCGv t0;
6395 if (unlikely(!ctx->mem_idx)) {
6396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6397 return;
6398 }
6399 t0 = tcg_temp_new();
6400 gen_addr_reg_index(ctx, t0);
6401 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6402 tcg_temp_free(t0);
6403 if (Rc(ctx->opcode)) {
6404 int l1 = gen_new_label();
6405 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6406 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6407 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6408 gen_set_label(l1);
6409 }
6410 #endif
6411 }
6412
6413 /* tlbwe */
6414 static void gen_tlbwe_440(DisasContext *ctx)
6415 {
6416 #if defined(CONFIG_USER_ONLY)
6417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6418 #else
6419 if (unlikely(!ctx->mem_idx)) {
6420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6421 return;
6422 }
6423 switch (rB(ctx->opcode)) {
6424 case 0:
6425 case 1:
6426 case 2:
6427 {
6428 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6429 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6430 cpu_gpr[rS(ctx->opcode)]);
6431 tcg_temp_free_i32(t0);
6432 }
6433 break;
6434 default:
6435 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6436 break;
6437 }
6438 #endif
6439 }
6440
6441 /* TLB management - PowerPC BookE 2.06 implementation */
6442
6443 /* tlbre */
6444 static void gen_tlbre_booke206(DisasContext *ctx)
6445 {
6446 #if defined(CONFIG_USER_ONLY)
6447 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6448 #else
6449 if (unlikely(!ctx->mem_idx)) {
6450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6451 return;
6452 }
6453
6454 gen_helper_booke206_tlbre(cpu_env);
6455 #endif
6456 }
6457
6458 /* tlbsx - tlbsx. */
6459 static void gen_tlbsx_booke206(DisasContext *ctx)
6460 {
6461 #if defined(CONFIG_USER_ONLY)
6462 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6463 #else
6464 TCGv t0;
6465 if (unlikely(!ctx->mem_idx)) {
6466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6467 return;
6468 }
6469
6470 if (rA(ctx->opcode)) {
6471 t0 = tcg_temp_new();
6472 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6473 } else {
6474 t0 = tcg_const_tl(0);
6475 }
6476
6477 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6478 gen_helper_booke206_tlbsx(cpu_env, t0);
6479 tcg_temp_free(t0);
6480 #endif
6481 }
6482
6483 /* tlbwe */
6484 static void gen_tlbwe_booke206(DisasContext *ctx)
6485 {
6486 #if defined(CONFIG_USER_ONLY)
6487 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6488 #else
6489 if (unlikely(!ctx->mem_idx)) {
6490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6491 return;
6492 }
6493 gen_update_nip(ctx, ctx->nip - 4);
6494 gen_helper_booke206_tlbwe(cpu_env);
6495 #endif
6496 }
6497
6498 static void gen_tlbivax_booke206(DisasContext *ctx)
6499 {
6500 #if defined(CONFIG_USER_ONLY)
6501 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6502 #else
6503 TCGv t0;
6504 if (unlikely(!ctx->mem_idx)) {
6505 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6506 return;
6507 }
6508
6509 t0 = tcg_temp_new();
6510 gen_addr_reg_index(ctx, t0);
6511
6512 gen_helper_booke206_tlbivax(cpu_env, t0);
6513 tcg_temp_free(t0);
6514 #endif
6515 }
6516
6517 static void gen_tlbilx_booke206(DisasContext *ctx)
6518 {
6519 #if defined(CONFIG_USER_ONLY)
6520 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6521 #else
6522 TCGv t0;
6523 if (unlikely(!ctx->mem_idx)) {
6524 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6525 return;
6526 }
6527
6528 t0 = tcg_temp_new();
6529 gen_addr_reg_index(ctx, t0);
6530
6531 switch((ctx->opcode >> 21) & 0x3) {
6532 case 0:
6533 gen_helper_booke206_tlbilx0(cpu_env, t0);
6534 break;
6535 case 1:
6536 gen_helper_booke206_tlbilx1(cpu_env, t0);
6537 break;
6538 case 3:
6539 gen_helper_booke206_tlbilx3(cpu_env, t0);
6540 break;
6541 default:
6542 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6543 break;
6544 }
6545
6546 tcg_temp_free(t0);
6547 #endif
6548 }
6549
6550
6551 /* wrtee */
6552 static void gen_wrtee(DisasContext *ctx)
6553 {
6554 #if defined(CONFIG_USER_ONLY)
6555 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6556 #else
6557 TCGv t0;
6558 if (unlikely(!ctx->mem_idx)) {
6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6560 return;
6561 }
6562 t0 = tcg_temp_new();
6563 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6564 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6565 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6566 tcg_temp_free(t0);
6567 /* Stop translation to have a chance to raise an exception
6568 * if we just set msr_ee to 1
6569 */
6570 gen_stop_exception(ctx);
6571 #endif
6572 }
6573
6574 /* wrteei */
6575 static void gen_wrteei(DisasContext *ctx)
6576 {
6577 #if defined(CONFIG_USER_ONLY)
6578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6579 #else
6580 if (unlikely(!ctx->mem_idx)) {
6581 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6582 return;
6583 }
6584 if (ctx->opcode & 0x00008000) {
6585 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6586 /* Stop translation to have a chance to raise an exception */
6587 gen_stop_exception(ctx);
6588 } else {
6589 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6590 }
6591 #endif
6592 }
6593
6594 /* PowerPC 440 specific instructions */
6595
6596 /* dlmzb */
6597 static void gen_dlmzb(DisasContext *ctx)
6598 {
6599 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6600 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6601 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6602 tcg_temp_free_i32(t0);
6603 }
6604
6605 /* mbar replaces eieio on 440 */
6606 static void gen_mbar(DisasContext *ctx)
6607 {
6608 /* interpreted as no-op */
6609 }
6610
6611 /* msync replaces sync on 440 */
6612 static void gen_msync_4xx(DisasContext *ctx)
6613 {
6614 /* interpreted as no-op */
6615 }
6616
6617 /* icbt */
6618 static void gen_icbt_440(DisasContext *ctx)
6619 {
6620 /* interpreted as no-op */
6621 /* XXX: specification say this is treated as a load by the MMU
6622 * but does not generate any exception
6623 */
6624 }
6625
6626 /* Embedded.Processor Control */
6627
6628 static void gen_msgclr(DisasContext *ctx)
6629 {
6630 #if defined(CONFIG_USER_ONLY)
6631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6632 #else
6633 if (unlikely(ctx->mem_idx == 0)) {
6634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6635 return;
6636 }
6637
6638 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6639 #endif
6640 }
6641
6642 static void gen_msgsnd(DisasContext *ctx)
6643 {
6644 #if defined(CONFIG_USER_ONLY)
6645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6646 #else
6647 if (unlikely(ctx->mem_idx == 0)) {
6648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6649 return;
6650 }
6651
6652 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6653 #endif
6654 }
6655
6656 /*** Altivec vector extension ***/
6657 /* Altivec registers moves */
6658
6659 static inline TCGv_ptr gen_avr_ptr(int reg)
6660 {
6661 TCGv_ptr r = tcg_temp_new_ptr();
6662 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6663 return r;
6664 }
6665
6666 #define GEN_VR_LDX(name, opc2, opc3) \
6667 static void glue(gen_, name)(DisasContext *ctx) \
6668 { \
6669 TCGv EA; \
6670 if (unlikely(!ctx->altivec_enabled)) { \
6671 gen_exception(ctx, POWERPC_EXCP_VPU); \
6672 return; \
6673 } \
6674 gen_set_access_type(ctx, ACCESS_INT); \
6675 EA = tcg_temp_new(); \
6676 gen_addr_reg_index(ctx, EA); \
6677 tcg_gen_andi_tl(EA, EA, ~0xf); \
6678 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6679 64-bit byteswap already. */ \
6680 if (ctx->le_mode) { \
6681 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6682 tcg_gen_addi_tl(EA, EA, 8); \
6683 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6684 } else { \
6685 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6686 tcg_gen_addi_tl(EA, EA, 8); \
6687 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6688 } \
6689 tcg_temp_free(EA); \
6690 }
6691
6692 #define GEN_VR_STX(name, opc2, opc3) \
6693 static void gen_st##name(DisasContext *ctx) \
6694 { \
6695 TCGv EA; \
6696 if (unlikely(!ctx->altivec_enabled)) { \
6697 gen_exception(ctx, POWERPC_EXCP_VPU); \
6698 return; \
6699 } \
6700 gen_set_access_type(ctx, ACCESS_INT); \
6701 EA = tcg_temp_new(); \
6702 gen_addr_reg_index(ctx, EA); \
6703 tcg_gen_andi_tl(EA, EA, ~0xf); \
6704 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6705 64-bit byteswap already. */ \
6706 if (ctx->le_mode) { \
6707 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6708 tcg_gen_addi_tl(EA, EA, 8); \
6709 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6710 } else { \
6711 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6712 tcg_gen_addi_tl(EA, EA, 8); \
6713 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6714 } \
6715 tcg_temp_free(EA); \
6716 }
6717
6718 #define GEN_VR_LVE(name, opc2, opc3) \
6719 static void gen_lve##name(DisasContext *ctx) \
6720 { \
6721 TCGv EA; \
6722 TCGv_ptr rs; \
6723 if (unlikely(!ctx->altivec_enabled)) { \
6724 gen_exception(ctx, POWERPC_EXCP_VPU); \
6725 return; \
6726 } \
6727 gen_set_access_type(ctx, ACCESS_INT); \
6728 EA = tcg_temp_new(); \
6729 gen_addr_reg_index(ctx, EA); \
6730 rs = gen_avr_ptr(rS(ctx->opcode)); \
6731 gen_helper_lve##name(cpu_env, rs, EA); \
6732 tcg_temp_free(EA); \
6733 tcg_temp_free_ptr(rs); \
6734 }
6735
6736 #define GEN_VR_STVE(name, opc2, opc3) \
6737 static void gen_stve##name(DisasContext *ctx) \
6738 { \
6739 TCGv EA; \
6740 TCGv_ptr rs; \
6741 if (unlikely(!ctx->altivec_enabled)) { \
6742 gen_exception(ctx, POWERPC_EXCP_VPU); \
6743 return; \
6744 } \
6745 gen_set_access_type(ctx, ACCESS_INT); \
6746 EA = tcg_temp_new(); \
6747 gen_addr_reg_index(ctx, EA); \
6748 rs = gen_avr_ptr(rS(ctx->opcode)); \
6749 gen_helper_stve##name(cpu_env, rs, EA); \
6750 tcg_temp_free(EA); \
6751 tcg_temp_free_ptr(rs); \
6752 }
6753
6754 GEN_VR_LDX(lvx, 0x07, 0x03);
6755 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6756 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6757
6758 GEN_VR_LVE(bx, 0x07, 0x00);
6759 GEN_VR_LVE(hx, 0x07, 0x01);
6760 GEN_VR_LVE(wx, 0x07, 0x02);
6761
6762 GEN_VR_STX(svx, 0x07, 0x07);
6763 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6764 GEN_VR_STX(svxl, 0x07, 0x0F);
6765
6766 GEN_VR_STVE(bx, 0x07, 0x04);
6767 GEN_VR_STVE(hx, 0x07, 0x05);
6768 GEN_VR_STVE(wx, 0x07, 0x06);
6769
6770 static void gen_lvsl(DisasContext *ctx)
6771 {
6772 TCGv_ptr rd;
6773 TCGv EA;
6774 if (unlikely(!ctx->altivec_enabled)) {
6775 gen_exception(ctx, POWERPC_EXCP_VPU);
6776 return;
6777 }
6778 EA = tcg_temp_new();
6779 gen_addr_reg_index(ctx, EA);
6780 rd = gen_avr_ptr(rD(ctx->opcode));
6781 gen_helper_lvsl(rd, EA);
6782 tcg_temp_free(EA);
6783 tcg_temp_free_ptr(rd);
6784 }
6785
6786 static void gen_lvsr(DisasContext *ctx)
6787 {
6788 TCGv_ptr rd;
6789 TCGv EA;
6790 if (unlikely(!ctx->altivec_enabled)) {
6791 gen_exception(ctx, POWERPC_EXCP_VPU);
6792 return;
6793 }
6794 EA = tcg_temp_new();
6795 gen_addr_reg_index(ctx, EA);
6796 rd = gen_avr_ptr(rD(ctx->opcode));
6797 gen_helper_lvsr(rd, EA);
6798 tcg_temp_free(EA);
6799 tcg_temp_free_ptr(rd);
6800 }
6801
6802 static void gen_mfvscr(DisasContext *ctx)
6803 {
6804 TCGv_i32 t;
6805 if (unlikely(!ctx->altivec_enabled)) {
6806 gen_exception(ctx, POWERPC_EXCP_VPU);
6807 return;
6808 }
6809 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6810 t = tcg_temp_new_i32();
6811 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6812 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6813 tcg_temp_free_i32(t);
6814 }
6815
6816 static void gen_mtvscr(DisasContext *ctx)
6817 {
6818 TCGv_ptr p;
6819 if (unlikely(!ctx->altivec_enabled)) {
6820 gen_exception(ctx, POWERPC_EXCP_VPU);
6821 return;
6822 }
6823 p = gen_avr_ptr(rD(ctx->opcode));
6824 gen_helper_mtvscr(cpu_env, p);
6825 tcg_temp_free_ptr(p);
6826 }
6827
6828 /* Logical operations */
6829 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6830 static void glue(gen_, name)(DisasContext *ctx) \
6831 { \
6832 if (unlikely(!ctx->altivec_enabled)) { \
6833 gen_exception(ctx, POWERPC_EXCP_VPU); \
6834 return; \
6835 } \
6836 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6837 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6838 }
6839
6840 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6841 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6842 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6843 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6844 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6845 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6846 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6847 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6848
6849 #define GEN_VXFORM(name, opc2, opc3) \
6850 static void glue(gen_, name)(DisasContext *ctx) \
6851 { \
6852 TCGv_ptr ra, rb, rd; \
6853 if (unlikely(!ctx->altivec_enabled)) { \
6854 gen_exception(ctx, POWERPC_EXCP_VPU); \
6855 return; \
6856 } \
6857 ra = gen_avr_ptr(rA(ctx->opcode)); \
6858 rb = gen_avr_ptr(rB(ctx->opcode)); \
6859 rd = gen_avr_ptr(rD(ctx->opcode)); \
6860 gen_helper_##name (rd, ra, rb); \
6861 tcg_temp_free_ptr(ra); \
6862 tcg_temp_free_ptr(rb); \
6863 tcg_temp_free_ptr(rd); \
6864 }
6865
6866 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6867 static void glue(gen_, name)(DisasContext *ctx) \
6868 { \
6869 TCGv_ptr ra, rb, rd; \
6870 if (unlikely(!ctx->altivec_enabled)) { \
6871 gen_exception(ctx, POWERPC_EXCP_VPU); \
6872 return; \
6873 } \
6874 ra = gen_avr_ptr(rA(ctx->opcode)); \
6875 rb = gen_avr_ptr(rB(ctx->opcode)); \
6876 rd = gen_avr_ptr(rD(ctx->opcode)); \
6877 gen_helper_##name(cpu_env, rd, ra, rb); \
6878 tcg_temp_free_ptr(ra); \
6879 tcg_temp_free_ptr(rb); \
6880 tcg_temp_free_ptr(rd); \
6881 }
6882
6883 #define GEN_VXFORM3(name, opc2, opc3) \
6884 static void glue(gen_, name)(DisasContext *ctx) \
6885 { \
6886 TCGv_ptr ra, rb, rc, rd; \
6887 if (unlikely(!ctx->altivec_enabled)) { \
6888 gen_exception(ctx, POWERPC_EXCP_VPU); \
6889 return; \
6890 } \
6891 ra = gen_avr_ptr(rA(ctx->opcode)); \
6892 rb = gen_avr_ptr(rB(ctx->opcode)); \
6893 rc = gen_avr_ptr(rC(ctx->opcode)); \
6894 rd = gen_avr_ptr(rD(ctx->opcode)); \
6895 gen_helper_##name(rd, ra, rb, rc); \
6896 tcg_temp_free_ptr(ra); \
6897 tcg_temp_free_ptr(rb); \
6898 tcg_temp_free_ptr(rc); \
6899 tcg_temp_free_ptr(rd); \
6900 }
6901
6902 /*
6903 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6904 * an opcode bit. In general, these pairs come from different
6905 * versions of the ISA, so we must also support a pair of flags for
6906 * each instruction.
6907 */
6908 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6909 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6910 { \
6911 if ((Rc(ctx->opcode) == 0) && \
6912 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6913 gen_##name0(ctx); \
6914 } else if ((Rc(ctx->opcode) == 1) && \
6915 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6916 gen_##name1(ctx); \
6917 } else { \
6918 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6919 } \
6920 }
6921
6922 GEN_VXFORM(vaddubm, 0, 0);
6923 GEN_VXFORM(vadduhm, 0, 1);
6924 GEN_VXFORM(vadduwm, 0, 2);
6925 GEN_VXFORM(vaddudm, 0, 3);
6926 GEN_VXFORM(vsububm, 0, 16);
6927 GEN_VXFORM(vsubuhm, 0, 17);
6928 GEN_VXFORM(vsubuwm, 0, 18);
6929 GEN_VXFORM(vsubudm, 0, 19);
6930 GEN_VXFORM(vmaxub, 1, 0);
6931 GEN_VXFORM(vmaxuh, 1, 1);
6932 GEN_VXFORM(vmaxuw, 1, 2);
6933 GEN_VXFORM(vmaxud, 1, 3);
6934 GEN_VXFORM(vmaxsb, 1, 4);
6935 GEN_VXFORM(vmaxsh, 1, 5);
6936 GEN_VXFORM(vmaxsw, 1, 6);
6937 GEN_VXFORM(vmaxsd, 1, 7);
6938 GEN_VXFORM(vminub, 1, 8);
6939 GEN_VXFORM(vminuh, 1, 9);
6940 GEN_VXFORM(vminuw, 1, 10);
6941 GEN_VXFORM(vminud, 1, 11);
6942 GEN_VXFORM(vminsb, 1, 12);
6943 GEN_VXFORM(vminsh, 1, 13);
6944 GEN_VXFORM(vminsw, 1, 14);
6945 GEN_VXFORM(vminsd, 1, 15);
6946 GEN_VXFORM(vavgub, 1, 16);
6947 GEN_VXFORM(vavguh, 1, 17);
6948 GEN_VXFORM(vavguw, 1, 18);
6949 GEN_VXFORM(vavgsb, 1, 20);
6950 GEN_VXFORM(vavgsh, 1, 21);
6951 GEN_VXFORM(vavgsw, 1, 22);
6952 GEN_VXFORM(vmrghb, 6, 0);
6953 GEN_VXFORM(vmrghh, 6, 1);
6954 GEN_VXFORM(vmrghw, 6, 2);
6955 GEN_VXFORM(vmrglb, 6, 4);
6956 GEN_VXFORM(vmrglh, 6, 5);
6957 GEN_VXFORM(vmrglw, 6, 6);
6958
6959 static void gen_vmrgew(DisasContext *ctx)
6960 {
6961 TCGv_i64 tmp;
6962 int VT, VA, VB;
6963 if (unlikely(!ctx->altivec_enabled)) {
6964 gen_exception(ctx, POWERPC_EXCP_VPU);
6965 return;
6966 }
6967 VT = rD(ctx->opcode);
6968 VA = rA(ctx->opcode);
6969 VB = rB(ctx->opcode);
6970 tmp = tcg_temp_new_i64();
6971 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
6972 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
6973 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
6974 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
6975 tcg_temp_free_i64(tmp);
6976 }
6977
6978 static void gen_vmrgow(DisasContext *ctx)
6979 {
6980 int VT, VA, VB;
6981 if (unlikely(!ctx->altivec_enabled)) {
6982 gen_exception(ctx, POWERPC_EXCP_VPU);
6983 return;
6984 }
6985 VT = rD(ctx->opcode);
6986 VA = rA(ctx->opcode);
6987 VB = rB(ctx->opcode);
6988
6989 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
6990 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
6991 }
6992
6993 GEN_VXFORM(vmuloub, 4, 0);
6994 GEN_VXFORM(vmulouh, 4, 1);
6995 GEN_VXFORM(vmulouw, 4, 2);
6996 GEN_VXFORM(vmuluwm, 4, 2);
6997 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
6998 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
6999 GEN_VXFORM(vmulosb, 4, 4);
7000 GEN_VXFORM(vmulosh, 4, 5);
7001 GEN_VXFORM(vmulosw, 4, 6);
7002 GEN_VXFORM(vmuleub, 4, 8);
7003 GEN_VXFORM(vmuleuh, 4, 9);
7004 GEN_VXFORM(vmuleuw, 4, 10);
7005 GEN_VXFORM(vmulesb, 4, 12);
7006 GEN_VXFORM(vmulesh, 4, 13);
7007 GEN_VXFORM(vmulesw, 4, 14);
7008 GEN_VXFORM(vslb, 2, 4);
7009 GEN_VXFORM(vslh, 2, 5);
7010 GEN_VXFORM(vslw, 2, 6);
7011 GEN_VXFORM(vsld, 2, 23);
7012 GEN_VXFORM(vsrb, 2, 8);
7013 GEN_VXFORM(vsrh, 2, 9);
7014 GEN_VXFORM(vsrw, 2, 10);
7015 GEN_VXFORM(vsrd, 2, 27);
7016 GEN_VXFORM(vsrab, 2, 12);
7017 GEN_VXFORM(vsrah, 2, 13);
7018 GEN_VXFORM(vsraw, 2, 14);
7019 GEN_VXFORM(vsrad, 2, 15);
7020 GEN_VXFORM(vslo, 6, 16);
7021 GEN_VXFORM(vsro, 6, 17);
7022 GEN_VXFORM(vaddcuw, 0, 6);
7023 GEN_VXFORM(vsubcuw, 0, 22);
7024 GEN_VXFORM_ENV(vaddubs, 0, 8);
7025 GEN_VXFORM_ENV(vadduhs, 0, 9);
7026 GEN_VXFORM_ENV(vadduws, 0, 10);
7027 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7028 GEN_VXFORM_ENV(vaddshs, 0, 13);
7029 GEN_VXFORM_ENV(vaddsws, 0, 14);
7030 GEN_VXFORM_ENV(vsububs, 0, 24);
7031 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7032 GEN_VXFORM_ENV(vsubuws, 0, 26);
7033 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7034 GEN_VXFORM_ENV(vsubshs, 0, 29);
7035 GEN_VXFORM_ENV(vsubsws, 0, 30);
7036 GEN_VXFORM(vadduqm, 0, 4);
7037 GEN_VXFORM(vaddcuq, 0, 5);
7038 GEN_VXFORM3(vaddeuqm, 30, 0);
7039 GEN_VXFORM3(vaddecuq, 30, 0);
7040 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7041 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7042 GEN_VXFORM(vsubuqm, 0, 20);
7043 GEN_VXFORM(vsubcuq, 0, 21);
7044 GEN_VXFORM3(vsubeuqm, 31, 0);
7045 GEN_VXFORM3(vsubecuq, 31, 0);
7046 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7047 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7048 GEN_VXFORM(vrlb, 2, 0);
7049 GEN_VXFORM(vrlh, 2, 1);
7050 GEN_VXFORM(vrlw, 2, 2);
7051 GEN_VXFORM(vrld, 2, 3);
7052 GEN_VXFORM(vsl, 2, 7);
7053 GEN_VXFORM(vsr, 2, 11);
7054 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7055 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7056 GEN_VXFORM_ENV(vpkudum, 7, 17);
7057 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7058 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7059 GEN_VXFORM_ENV(vpkudus, 7, 19);
7060 GEN_VXFORM_ENV(vpkshus, 7, 4);
7061 GEN_VXFORM_ENV(vpkswus, 7, 5);
7062 GEN_VXFORM_ENV(vpksdus, 7, 21);
7063 GEN_VXFORM_ENV(vpkshss, 7, 6);
7064 GEN_VXFORM_ENV(vpkswss, 7, 7);
7065 GEN_VXFORM_ENV(vpksdss, 7, 23);
7066 GEN_VXFORM(vpkpx, 7, 12);
7067 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7068 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7069 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7070 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7071 GEN_VXFORM_ENV(vsumsws, 4, 30);
7072 GEN_VXFORM_ENV(vaddfp, 5, 0);
7073 GEN_VXFORM_ENV(vsubfp, 5, 1);
7074 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7075 GEN_VXFORM_ENV(vminfp, 5, 17);
7076
7077 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7078 static void glue(gen_, name)(DisasContext *ctx) \
7079 { \
7080 TCGv_ptr ra, rb, rd; \
7081 if (unlikely(!ctx->altivec_enabled)) { \
7082 gen_exception(ctx, POWERPC_EXCP_VPU); \
7083 return; \
7084 } \
7085 ra = gen_avr_ptr(rA(ctx->opcode)); \
7086 rb = gen_avr_ptr(rB(ctx->opcode)); \
7087 rd = gen_avr_ptr(rD(ctx->opcode)); \
7088 gen_helper_##opname(cpu_env, rd, ra, rb); \
7089 tcg_temp_free_ptr(ra); \
7090 tcg_temp_free_ptr(rb); \
7091 tcg_temp_free_ptr(rd); \
7092 }
7093
7094 #define GEN_VXRFORM(name, opc2, opc3) \
7095 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7096 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7097
7098 /*
7099 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7100 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7101 * come from different versions of the ISA, so we must also support a
7102 * pair of flags for each instruction.
7103 */
7104 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7105 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7106 { \
7107 if ((Rc(ctx->opcode) == 0) && \
7108 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7109 if (Rc21(ctx->opcode) == 0) { \
7110 gen_##name0(ctx); \
7111 } else { \
7112 gen_##name0##_(ctx); \
7113 } \
7114 } else if ((Rc(ctx->opcode) == 1) && \
7115 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7116 if (Rc21(ctx->opcode) == 0) { \
7117 gen_##name1(ctx); \
7118 } else { \
7119 gen_##name1##_(ctx); \
7120 } \
7121 } else { \
7122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7123 } \
7124 }
7125
7126 GEN_VXRFORM(vcmpequb, 3, 0)
7127 GEN_VXRFORM(vcmpequh, 3, 1)
7128 GEN_VXRFORM(vcmpequw, 3, 2)
7129 GEN_VXRFORM(vcmpequd, 3, 3)
7130 GEN_VXRFORM(vcmpgtsb, 3, 12)
7131 GEN_VXRFORM(vcmpgtsh, 3, 13)
7132 GEN_VXRFORM(vcmpgtsw, 3, 14)
7133 GEN_VXRFORM(vcmpgtsd, 3, 15)
7134 GEN_VXRFORM(vcmpgtub, 3, 8)
7135 GEN_VXRFORM(vcmpgtuh, 3, 9)
7136 GEN_VXRFORM(vcmpgtuw, 3, 10)
7137 GEN_VXRFORM(vcmpgtud, 3, 11)
7138 GEN_VXRFORM(vcmpeqfp, 3, 3)
7139 GEN_VXRFORM(vcmpgefp, 3, 7)
7140 GEN_VXRFORM(vcmpgtfp, 3, 11)
7141 GEN_VXRFORM(vcmpbfp, 3, 15)
7142
7143 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7144 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7145 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7146 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7147 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7148 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7149
7150 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7151 static void glue(gen_, name)(DisasContext *ctx) \
7152 { \
7153 TCGv_ptr rd; \
7154 TCGv_i32 simm; \
7155 if (unlikely(!ctx->altivec_enabled)) { \
7156 gen_exception(ctx, POWERPC_EXCP_VPU); \
7157 return; \
7158 } \
7159 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7160 rd = gen_avr_ptr(rD(ctx->opcode)); \
7161 gen_helper_##name (rd, simm); \
7162 tcg_temp_free_i32(simm); \
7163 tcg_temp_free_ptr(rd); \
7164 }
7165
7166 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7167 GEN_VXFORM_SIMM(vspltish, 6, 13);
7168 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7169
7170 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7171 static void glue(gen_, name)(DisasContext *ctx) \
7172 { \
7173 TCGv_ptr rb, rd; \
7174 if (unlikely(!ctx->altivec_enabled)) { \
7175 gen_exception(ctx, POWERPC_EXCP_VPU); \
7176 return; \
7177 } \
7178 rb = gen_avr_ptr(rB(ctx->opcode)); \
7179 rd = gen_avr_ptr(rD(ctx->opcode)); \
7180 gen_helper_##name (rd, rb); \
7181 tcg_temp_free_ptr(rb); \
7182 tcg_temp_free_ptr(rd); \
7183 }
7184
7185 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7186 static void glue(gen_, name)(DisasContext *ctx) \
7187 { \
7188 TCGv_ptr rb, rd; \
7189 \
7190 if (unlikely(!ctx->altivec_enabled)) { \
7191 gen_exception(ctx, POWERPC_EXCP_VPU); \
7192 return; \
7193 } \
7194 rb = gen_avr_ptr(rB(ctx->opcode)); \
7195 rd = gen_avr_ptr(rD(ctx->opcode)); \
7196 gen_helper_##name(cpu_env, rd, rb); \
7197 tcg_temp_free_ptr(rb); \
7198 tcg_temp_free_ptr(rd); \
7199 }
7200
7201 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7202 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7203 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7204 GEN_VXFORM_NOA(vupklsb, 7, 10);
7205 GEN_VXFORM_NOA(vupklsh, 7, 11);
7206 GEN_VXFORM_NOA(vupklsw, 7, 27);
7207 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7208 GEN_VXFORM_NOA(vupklpx, 7, 15);
7209 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7210 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7211 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7212 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7213 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7214 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7215 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7216 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7217
7218 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7219 static void glue(gen_, name)(DisasContext *ctx) \
7220 { \
7221 TCGv_ptr rd; \
7222 TCGv_i32 simm; \
7223 if (unlikely(!ctx->altivec_enabled)) { \
7224 gen_exception(ctx, POWERPC_EXCP_VPU); \
7225 return; \
7226 } \
7227 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7228 rd = gen_avr_ptr(rD(ctx->opcode)); \
7229 gen_helper_##name (rd, simm); \
7230 tcg_temp_free_i32(simm); \
7231 tcg_temp_free_ptr(rd); \
7232 }
7233
7234 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7235 static void glue(gen_, name)(DisasContext *ctx) \
7236 { \
7237 TCGv_ptr rb, rd; \
7238 TCGv_i32 uimm; \
7239 if (unlikely(!ctx->altivec_enabled)) { \
7240 gen_exception(ctx, POWERPC_EXCP_VPU); \
7241 return; \
7242 } \
7243 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7244 rb = gen_avr_ptr(rB(ctx->opcode)); \
7245 rd = gen_avr_ptr(rD(ctx->opcode)); \
7246 gen_helper_##name (rd, rb, uimm); \
7247 tcg_temp_free_i32(uimm); \
7248 tcg_temp_free_ptr(rb); \
7249 tcg_temp_free_ptr(rd); \
7250 }
7251
7252 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7253 static void glue(gen_, name)(DisasContext *ctx) \
7254 { \
7255 TCGv_ptr rb, rd; \
7256 TCGv_i32 uimm; \
7257 \
7258 if (unlikely(!ctx->altivec_enabled)) { \
7259 gen_exception(ctx, POWERPC_EXCP_VPU); \
7260 return; \
7261 } \
7262 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7263 rb = gen_avr_ptr(rB(ctx->opcode)); \
7264 rd = gen_avr_ptr(rD(ctx->opcode)); \
7265 gen_helper_##name(cpu_env, rd, rb, uimm); \
7266 tcg_temp_free_i32(uimm); \
7267 tcg_temp_free_ptr(rb); \
7268 tcg_temp_free_ptr(rd); \
7269 }
7270
7271 GEN_VXFORM_UIMM(vspltb, 6, 8);
7272 GEN_VXFORM_UIMM(vsplth, 6, 9);
7273 GEN_VXFORM_UIMM(vspltw, 6, 10);
7274 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7275 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7276 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7277 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7278
7279 static void gen_vsldoi(DisasContext *ctx)
7280 {
7281 TCGv_ptr ra, rb, rd;
7282 TCGv_i32 sh;
7283 if (unlikely(!ctx->altivec_enabled)) {
7284 gen_exception(ctx, POWERPC_EXCP_VPU);
7285 return;
7286 }
7287 ra = gen_avr_ptr(rA(ctx->opcode));
7288 rb = gen_avr_ptr(rB(ctx->opcode));
7289 rd = gen_avr_ptr(rD(ctx->opcode));
7290 sh = tcg_const_i32(VSH(ctx->opcode));
7291 gen_helper_vsldoi (rd, ra, rb, sh);
7292 tcg_temp_free_ptr(ra);
7293 tcg_temp_free_ptr(rb);
7294 tcg_temp_free_ptr(rd);
7295 tcg_temp_free_i32(sh);
7296 }
7297
7298 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7299 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7300 { \
7301 TCGv_ptr ra, rb, rc, rd; \
7302 if (unlikely(!ctx->altivec_enabled)) { \
7303 gen_exception(ctx, POWERPC_EXCP_VPU); \
7304 return; \
7305 } \
7306 ra = gen_avr_ptr(rA(ctx->opcode)); \
7307 rb = gen_avr_ptr(rB(ctx->opcode)); \
7308 rc = gen_avr_ptr(rC(ctx->opcode)); \
7309 rd = gen_avr_ptr(rD(ctx->opcode)); \
7310 if (Rc(ctx->opcode)) { \
7311 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7312 } else { \
7313 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7314 } \
7315 tcg_temp_free_ptr(ra); \
7316 tcg_temp_free_ptr(rb); \
7317 tcg_temp_free_ptr(rc); \
7318 tcg_temp_free_ptr(rd); \
7319 }
7320
7321 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7322
7323 static void gen_vmladduhm(DisasContext *ctx)
7324 {
7325 TCGv_ptr ra, rb, rc, rd;
7326 if (unlikely(!ctx->altivec_enabled)) {
7327 gen_exception(ctx, POWERPC_EXCP_VPU);
7328 return;
7329 }
7330 ra = gen_avr_ptr(rA(ctx->opcode));
7331 rb = gen_avr_ptr(rB(ctx->opcode));
7332 rc = gen_avr_ptr(rC(ctx->opcode));
7333 rd = gen_avr_ptr(rD(ctx->opcode));
7334 gen_helper_vmladduhm(rd, ra, rb, rc);
7335 tcg_temp_free_ptr(ra);
7336 tcg_temp_free_ptr(rb);
7337 tcg_temp_free_ptr(rc);
7338 tcg_temp_free_ptr(rd);
7339 }
7340
7341 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7342 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7343 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7344 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7345 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7346
7347 GEN_VXFORM_NOA(vclzb, 1, 28)
7348 GEN_VXFORM_NOA(vclzh, 1, 29)
7349 GEN_VXFORM_NOA(vclzw, 1, 30)
7350 GEN_VXFORM_NOA(vclzd, 1, 31)
7351 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7352 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7353 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7354 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7355 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7356 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7357 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7358 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7359 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7360 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7361 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7362 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7363 GEN_VXFORM(vbpermq, 6, 21);
7364 GEN_VXFORM_NOA(vgbbd, 6, 20);
7365 GEN_VXFORM(vpmsumb, 4, 16)
7366 GEN_VXFORM(vpmsumh, 4, 17)
7367 GEN_VXFORM(vpmsumw, 4, 18)
7368 GEN_VXFORM(vpmsumd, 4, 19)
7369
7370 #define GEN_BCD(op) \
7371 static void gen_##op(DisasContext *ctx) \
7372 { \
7373 TCGv_ptr ra, rb, rd; \
7374 TCGv_i32 ps; \
7375 \
7376 if (unlikely(!ctx->altivec_enabled)) { \
7377 gen_exception(ctx, POWERPC_EXCP_VPU); \
7378 return; \
7379 } \
7380 \
7381 ra = gen_avr_ptr(rA(ctx->opcode)); \
7382 rb = gen_avr_ptr(rB(ctx->opcode)); \
7383 rd = gen_avr_ptr(rD(ctx->opcode)); \
7384 \
7385 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7386 \
7387 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7388 \
7389 tcg_temp_free_ptr(ra); \
7390 tcg_temp_free_ptr(rb); \
7391 tcg_temp_free_ptr(rd); \
7392 tcg_temp_free_i32(ps); \
7393 }
7394
7395 GEN_BCD(bcdadd)
7396 GEN_BCD(bcdsub)
7397
7398 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7399 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7400 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7401 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7402 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7403 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7404 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7405 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7406
7407 static void gen_vsbox(DisasContext *ctx)
7408 {
7409 TCGv_ptr ra, rd;
7410 if (unlikely(!ctx->altivec_enabled)) {
7411 gen_exception(ctx, POWERPC_EXCP_VPU);
7412 return;
7413 }
7414 ra = gen_avr_ptr(rA(ctx->opcode));
7415 rd = gen_avr_ptr(rD(ctx->opcode));
7416 gen_helper_vsbox(rd, ra);
7417 tcg_temp_free_ptr(ra);
7418 tcg_temp_free_ptr(rd);
7419 }
7420
7421 GEN_VXFORM(vcipher, 4, 20)
7422 GEN_VXFORM(vcipherlast, 4, 20)
7423 GEN_VXFORM(vncipher, 4, 21)
7424 GEN_VXFORM(vncipherlast, 4, 21)
7425
7426 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7427 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7428 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7429 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7430
7431 #define VSHASIGMA(op) \
7432 static void gen_##op(DisasContext *ctx) \
7433 { \
7434 TCGv_ptr ra, rd; \
7435 TCGv_i32 st_six; \
7436 if (unlikely(!ctx->altivec_enabled)) { \
7437 gen_exception(ctx, POWERPC_EXCP_VPU); \
7438 return; \
7439 } \
7440 ra = gen_avr_ptr(rA(ctx->opcode)); \
7441 rd = gen_avr_ptr(rD(ctx->opcode)); \
7442 st_six = tcg_const_i32(rB(ctx->opcode)); \
7443 gen_helper_##op(rd, ra, st_six); \
7444 tcg_temp_free_ptr(ra); \
7445 tcg_temp_free_ptr(rd); \
7446 tcg_temp_free_i32(st_six); \
7447 }
7448
7449 VSHASIGMA(vshasigmaw)
7450 VSHASIGMA(vshasigmad)
7451
7452 GEN_VXFORM3(vpermxor, 22, 0xFF)
7453 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7454 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7455
7456 /*** VSX extension ***/
7457
7458 static inline TCGv_i64 cpu_vsrh(int n)
7459 {
7460 if (n < 32) {
7461 return cpu_fpr[n];
7462 } else {
7463 return cpu_avrh[n-32];
7464 }
7465 }
7466
7467 static inline TCGv_i64 cpu_vsrl(int n)
7468 {
7469 if (n < 32) {
7470 return cpu_vsr[n];
7471 } else {
7472 return cpu_avrl[n-32];
7473 }
7474 }
7475
7476 #define VSX_LOAD_SCALAR(name, operation) \
7477 static void gen_##name(DisasContext *ctx) \
7478 { \
7479 TCGv EA; \
7480 if (unlikely(!ctx->vsx_enabled)) { \
7481 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7482 return; \
7483 } \
7484 gen_set_access_type(ctx, ACCESS_INT); \
7485 EA = tcg_temp_new(); \
7486 gen_addr_reg_index(ctx, EA); \
7487 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7488 /* NOTE: cpu_vsrl is undefined */ \
7489 tcg_temp_free(EA); \
7490 }
7491
7492 VSX_LOAD_SCALAR(lxsdx, ld64)
7493 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7494 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7495 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7496
7497 static void gen_lxvd2x(DisasContext *ctx)
7498 {
7499 TCGv EA;
7500 if (unlikely(!ctx->vsx_enabled)) {
7501 gen_exception(ctx, POWERPC_EXCP_VSXU);
7502 return;
7503 }
7504 gen_set_access_type(ctx, ACCESS_INT);
7505 EA = tcg_temp_new();
7506 gen_addr_reg_index(ctx, EA);
7507 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7508 tcg_gen_addi_tl(EA, EA, 8);
7509 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7510 tcg_temp_free(EA);
7511 }
7512
7513 static void gen_lxvdsx(DisasContext *ctx)
7514 {
7515 TCGv EA;
7516 if (unlikely(!ctx->vsx_enabled)) {
7517 gen_exception(ctx, POWERPC_EXCP_VSXU);
7518 return;
7519 }
7520 gen_set_access_type(ctx, ACCESS_INT);
7521 EA = tcg_temp_new();
7522 gen_addr_reg_index(ctx, EA);
7523 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7524 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7525 tcg_temp_free(EA);
7526 }
7527
7528 static void gen_lxvw4x(DisasContext *ctx)
7529 {
7530 TCGv EA;
7531 TCGv_i64 tmp;
7532 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7533 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7534 if (unlikely(!ctx->vsx_enabled)) {
7535 gen_exception(ctx, POWERPC_EXCP_VSXU);
7536 return;
7537 }
7538 gen_set_access_type(ctx, ACCESS_INT);
7539 EA = tcg_temp_new();
7540 tmp = tcg_temp_new_i64();
7541
7542 gen_addr_reg_index(ctx, EA);
7543 gen_qemu_ld32u_i64(ctx, tmp, EA);
7544 tcg_gen_addi_tl(EA, EA, 4);
7545 gen_qemu_ld32u_i64(ctx, xth, EA);
7546 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7547
7548 tcg_gen_addi_tl(EA, EA, 4);
7549 gen_qemu_ld32u_i64(ctx, tmp, EA);
7550 tcg_gen_addi_tl(EA, EA, 4);
7551 gen_qemu_ld32u_i64(ctx, xtl, EA);
7552 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7553
7554 tcg_temp_free(EA);
7555 tcg_temp_free_i64(tmp);
7556 }
7557
7558 #define VSX_STORE_SCALAR(name, operation) \
7559 static void gen_##name(DisasContext *ctx) \
7560 { \
7561 TCGv EA; \
7562 if (unlikely(!ctx->vsx_enabled)) { \
7563 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7564 return; \
7565 } \
7566 gen_set_access_type(ctx, ACCESS_INT); \
7567 EA = tcg_temp_new(); \
7568 gen_addr_reg_index(ctx, EA); \
7569 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7570 tcg_temp_free(EA); \
7571 }
7572
7573 VSX_STORE_SCALAR(stxsdx, st64)
7574 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7575 VSX_STORE_SCALAR(stxsspx, st32fs)
7576
7577 static void gen_stxvd2x(DisasContext *ctx)
7578 {
7579 TCGv EA;
7580 if (unlikely(!ctx->vsx_enabled)) {
7581 gen_exception(ctx, POWERPC_EXCP_VSXU);
7582 return;
7583 }
7584 gen_set_access_type(ctx, ACCESS_INT);
7585 EA = tcg_temp_new();
7586 gen_addr_reg_index(ctx, EA);
7587 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7588 tcg_gen_addi_tl(EA, EA, 8);
7589 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7590 tcg_temp_free(EA);
7591 }
7592
7593 static void gen_stxvw4x(DisasContext *ctx)
7594 {
7595 TCGv_i64 tmp;
7596 TCGv EA;
7597 if (unlikely(!ctx->vsx_enabled)) {
7598 gen_exception(ctx, POWERPC_EXCP_VSXU);
7599 return;
7600 }
7601 gen_set_access_type(ctx, ACCESS_INT);
7602 EA = tcg_temp_new();
7603 gen_addr_reg_index(ctx, EA);
7604 tmp = tcg_temp_new_i64();
7605
7606 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7607 gen_qemu_st32_i64(ctx, tmp, EA);
7608 tcg_gen_addi_tl(EA, EA, 4);
7609 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7610
7611 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7612 tcg_gen_addi_tl(EA, EA, 4);
7613 gen_qemu_st32_i64(ctx, tmp, EA);
7614 tcg_gen_addi_tl(EA, EA, 4);
7615 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7616
7617 tcg_temp_free(EA);
7618 tcg_temp_free_i64(tmp);
7619 }
7620
7621 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7622 static void gen_##name(DisasContext *ctx) \
7623 { \
7624 if (xS(ctx->opcode) < 32) { \
7625 if (unlikely(!ctx->fpu_enabled)) { \
7626 gen_exception(ctx, POWERPC_EXCP_FPU); \
7627 return; \
7628 } \
7629 } else { \
7630 if (unlikely(!ctx->altivec_enabled)) { \
7631 gen_exception(ctx, POWERPC_EXCP_VPU); \
7632 return; \
7633 } \
7634 } \
7635 TCGv_i64 tmp = tcg_temp_new_i64(); \
7636 tcg_gen_##tcgop1(tmp, source); \
7637 tcg_gen_##tcgop2(target, tmp); \
7638 tcg_temp_free_i64(tmp); \
7639 }
7640
7641
7642 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7643 cpu_vsrh(xS(ctx->opcode)))
7644 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7645 cpu_gpr[rA(ctx->opcode)])
7646 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7647 cpu_gpr[rA(ctx->opcode)])
7648
7649 #if defined(TARGET_PPC64)
7650 #define MV_VSRD(name, target, source) \
7651 static void gen_##name(DisasContext *ctx) \
7652 { \
7653 if (xS(ctx->opcode) < 32) { \
7654 if (unlikely(!ctx->fpu_enabled)) { \
7655 gen_exception(ctx, POWERPC_EXCP_FPU); \
7656 return; \
7657 } \
7658 } else { \
7659 if (unlikely(!ctx->altivec_enabled)) { \
7660 gen_exception(ctx, POWERPC_EXCP_VPU); \
7661 return; \
7662 } \
7663 } \
7664 tcg_gen_mov_i64(target, source); \
7665 }
7666
7667 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7668 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7669
7670 #endif
7671
7672 static void gen_xxpermdi(DisasContext *ctx)
7673 {
7674 if (unlikely(!ctx->vsx_enabled)) {
7675 gen_exception(ctx, POWERPC_EXCP_VSXU);
7676 return;
7677 }
7678
7679 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7680 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7681 TCGv_i64 xh, xl;
7682
7683 xh = tcg_temp_new_i64();
7684 xl = tcg_temp_new_i64();
7685
7686 if ((DM(ctx->opcode) & 2) == 0) {
7687 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7688 } else {
7689 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7690 }
7691 if ((DM(ctx->opcode) & 1) == 0) {
7692 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7693 } else {
7694 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7695 }
7696
7697 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7698 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7699
7700 tcg_temp_free_i64(xh);
7701 tcg_temp_free_i64(xl);
7702 } else {
7703 if ((DM(ctx->opcode) & 2) == 0) {
7704 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7705 } else {
7706 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7707 }
7708 if ((DM(ctx->opcode) & 1) == 0) {
7709 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7710 } else {
7711 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7712 }
7713 }
7714 }
7715
7716 #define OP_ABS 1
7717 #define OP_NABS 2
7718 #define OP_NEG 3
7719 #define OP_CPSGN 4
7720 #define SGN_MASK_DP 0x8000000000000000ull
7721 #define SGN_MASK_SP 0x8000000080000000ull
7722
7723 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7724 static void glue(gen_, name)(DisasContext * ctx) \
7725 { \
7726 TCGv_i64 xb, sgm; \
7727 if (unlikely(!ctx->vsx_enabled)) { \
7728 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7729 return; \
7730 } \
7731 xb = tcg_temp_new_i64(); \
7732 sgm = tcg_temp_new_i64(); \
7733 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7734 tcg_gen_movi_i64(sgm, sgn_mask); \
7735 switch (op) { \
7736 case OP_ABS: { \
7737 tcg_gen_andc_i64(xb, xb, sgm); \
7738 break; \
7739 } \
7740 case OP_NABS: { \
7741 tcg_gen_or_i64(xb, xb, sgm); \
7742 break; \
7743 } \
7744 case OP_NEG: { \
7745 tcg_gen_xor_i64(xb, xb, sgm); \
7746 break; \
7747 } \
7748 case OP_CPSGN: { \
7749 TCGv_i64 xa = tcg_temp_new_i64(); \
7750 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7751 tcg_gen_and_i64(xa, xa, sgm); \
7752 tcg_gen_andc_i64(xb, xb, sgm); \
7753 tcg_gen_or_i64(xb, xb, xa); \
7754 tcg_temp_free_i64(xa); \
7755 break; \
7756 } \
7757 } \
7758 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7759 tcg_temp_free_i64(xb); \
7760 tcg_temp_free_i64(sgm); \
7761 }
7762
7763 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7764 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7765 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7766 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7767
7768 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7769 static void glue(gen_, name)(DisasContext * ctx) \
7770 { \
7771 TCGv_i64 xbh, xbl, sgm; \
7772 if (unlikely(!ctx->vsx_enabled)) { \
7773 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7774 return; \
7775 } \
7776 xbh = tcg_temp_new_i64(); \
7777 xbl = tcg_temp_new_i64(); \
7778 sgm = tcg_temp_new_i64(); \
7779 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7780 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7781 tcg_gen_movi_i64(sgm, sgn_mask); \
7782 switch (op) { \
7783 case OP_ABS: { \
7784 tcg_gen_andc_i64(xbh, xbh, sgm); \
7785 tcg_gen_andc_i64(xbl, xbl, sgm); \
7786 break; \
7787 } \
7788 case OP_NABS: { \
7789 tcg_gen_or_i64(xbh, xbh, sgm); \
7790 tcg_gen_or_i64(xbl, xbl, sgm); \
7791 break; \
7792 } \
7793 case OP_NEG: { \
7794 tcg_gen_xor_i64(xbh, xbh, sgm); \
7795 tcg_gen_xor_i64(xbl, xbl, sgm); \
7796 break; \
7797 } \
7798 case OP_CPSGN: { \
7799 TCGv_i64 xah = tcg_temp_new_i64(); \
7800 TCGv_i64 xal = tcg_temp_new_i64(); \
7801 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7802 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7803 tcg_gen_and_i64(xah, xah, sgm); \
7804 tcg_gen_and_i64(xal, xal, sgm); \
7805 tcg_gen_andc_i64(xbh, xbh, sgm); \
7806 tcg_gen_andc_i64(xbl, xbl, sgm); \
7807 tcg_gen_or_i64(xbh, xbh, xah); \
7808 tcg_gen_or_i64(xbl, xbl, xal); \
7809 tcg_temp_free_i64(xah); \
7810 tcg_temp_free_i64(xal); \
7811 break; \
7812 } \
7813 } \
7814 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7815 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7816 tcg_temp_free_i64(xbh); \
7817 tcg_temp_free_i64(xbl); \
7818 tcg_temp_free_i64(sgm); \
7819 }
7820
7821 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7822 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7823 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7824 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7825 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7826 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7827 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7828 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7829
7830 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7831 static void gen_##name(DisasContext * ctx) \
7832 { \
7833 TCGv_i32 opc; \
7834 if (unlikely(!ctx->vsx_enabled)) { \
7835 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7836 return; \
7837 } \
7838 /* NIP cannot be restored if the memory exception comes from an helper */ \
7839 gen_update_nip(ctx, ctx->nip - 4); \
7840 opc = tcg_const_i32(ctx->opcode); \
7841 gen_helper_##name(cpu_env, opc); \
7842 tcg_temp_free_i32(opc); \
7843 }
7844
7845 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7846 static void gen_##name(DisasContext * ctx) \
7847 { \
7848 if (unlikely(!ctx->vsx_enabled)) { \
7849 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7850 return; \
7851 } \
7852 /* NIP cannot be restored if the exception comes */ \
7853 /* from a helper. */ \
7854 gen_update_nip(ctx, ctx->nip - 4); \
7855 \
7856 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7857 cpu_vsrh(xB(ctx->opcode))); \
7858 }
7859
7860 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7861 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7862 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7863 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7864 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7865 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7866 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7867 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7868 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7869 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7870 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7871 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7872 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7873 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7874 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7875 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7876 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7877 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7878 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7879 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7880 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7881 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7882 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7883 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7884 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7885 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7886 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7887 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7888 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7889 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7891 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7895 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7896 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7897
7898 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7899 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7900 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7901 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7902 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7903 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7904 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7905 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7906 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7907 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7908 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7909 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7910 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7911 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7912 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7913 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7914 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7915
7916 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7917 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7918 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7919 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7920 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7921 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7922 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7923 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7924 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7925 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7926 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7927 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7928 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7929 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7930 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7931 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7932 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7933 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7934 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7935 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7952
7953 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7989
7990 #define VSX_LOGICAL(name, tcg_op) \
7991 static void glue(gen_, name)(DisasContext * ctx) \
7992 { \
7993 if (unlikely(!ctx->vsx_enabled)) { \
7994 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7995 return; \
7996 } \
7997 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7998 cpu_vsrh(xB(ctx->opcode))); \
7999 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8000 cpu_vsrl(xB(ctx->opcode))); \
8001 }
8002
8003 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8004 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8005 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8006 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8007 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8008 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8009 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8010 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8011
8012 #define VSX_XXMRG(name, high) \
8013 static void glue(gen_, name)(DisasContext * ctx) \
8014 { \
8015 TCGv_i64 a0, a1, b0, b1; \
8016 if (unlikely(!ctx->vsx_enabled)) { \
8017 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8018 return; \
8019 } \
8020 a0 = tcg_temp_new_i64(); \
8021 a1 = tcg_temp_new_i64(); \
8022 b0 = tcg_temp_new_i64(); \
8023 b1 = tcg_temp_new_i64(); \
8024 if (high) { \
8025 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8026 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8027 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8028 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8029 } else { \
8030 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8031 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8032 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8033 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8034 } \
8035 tcg_gen_shri_i64(a0, a0, 32); \
8036 tcg_gen_shri_i64(b0, b0, 32); \
8037 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8038 b0, a0, 32, 32); \
8039 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8040 b1, a1, 32, 32); \
8041 tcg_temp_free_i64(a0); \
8042 tcg_temp_free_i64(a1); \
8043 tcg_temp_free_i64(b0); \
8044 tcg_temp_free_i64(b1); \
8045 }
8046
8047 VSX_XXMRG(xxmrghw, 1)
8048 VSX_XXMRG(xxmrglw, 0)
8049
8050 static void gen_xxsel(DisasContext * ctx)
8051 {
8052 TCGv_i64 a, b, c;
8053 if (unlikely(!ctx->vsx_enabled)) {
8054 gen_exception(ctx, POWERPC_EXCP_VSXU);
8055 return;
8056 }
8057 a = tcg_temp_new_i64();
8058 b = tcg_temp_new_i64();
8059 c = tcg_temp_new_i64();
8060
8061 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8062 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8063 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8064
8065 tcg_gen_and_i64(b, b, c);
8066 tcg_gen_andc_i64(a, a, c);
8067 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8068
8069 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8070 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8071 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8072
8073 tcg_gen_and_i64(b, b, c);
8074 tcg_gen_andc_i64(a, a, c);
8075 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8076
8077 tcg_temp_free_i64(a);
8078 tcg_temp_free_i64(b);
8079 tcg_temp_free_i64(c);
8080 }
8081
8082 static void gen_xxspltw(DisasContext *ctx)
8083 {
8084 TCGv_i64 b, b2;
8085 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8086 cpu_vsrl(xB(ctx->opcode)) :
8087 cpu_vsrh(xB(ctx->opcode));
8088
8089 if (unlikely(!ctx->vsx_enabled)) {
8090 gen_exception(ctx, POWERPC_EXCP_VSXU);
8091 return;
8092 }
8093
8094 b = tcg_temp_new_i64();
8095 b2 = tcg_temp_new_i64();
8096
8097 if (UIM(ctx->opcode) & 1) {
8098 tcg_gen_ext32u_i64(b, vsr);
8099 } else {
8100 tcg_gen_shri_i64(b, vsr, 32);
8101 }
8102
8103 tcg_gen_shli_i64(b2, b, 32);
8104 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8105 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8106
8107 tcg_temp_free_i64(b);
8108 tcg_temp_free_i64(b2);
8109 }
8110
8111 static void gen_xxsldwi(DisasContext *ctx)
8112 {
8113 TCGv_i64 xth, xtl;
8114 if (unlikely(!ctx->vsx_enabled)) {
8115 gen_exception(ctx, POWERPC_EXCP_VSXU);
8116 return;
8117 }
8118 xth = tcg_temp_new_i64();
8119 xtl = tcg_temp_new_i64();
8120
8121 switch (SHW(ctx->opcode)) {
8122 case 0: {
8123 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8124 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8125 break;
8126 }
8127 case 1: {
8128 TCGv_i64 t0 = tcg_temp_new_i64();
8129 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8130 tcg_gen_shli_i64(xth, xth, 32);
8131 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8132 tcg_gen_shri_i64(t0, t0, 32);
8133 tcg_gen_or_i64(xth, xth, t0);
8134 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8135 tcg_gen_shli_i64(xtl, xtl, 32);
8136 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8137 tcg_gen_shri_i64(t0, t0, 32);
8138 tcg_gen_or_i64(xtl, xtl, t0);
8139 tcg_temp_free_i64(t0);
8140 break;
8141 }
8142 case 2: {
8143 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8144 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8145 break;
8146 }
8147 case 3: {
8148 TCGv_i64 t0 = tcg_temp_new_i64();
8149 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8150 tcg_gen_shli_i64(xth, xth, 32);
8151 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8152 tcg_gen_shri_i64(t0, t0, 32);
8153 tcg_gen_or_i64(xth, xth, t0);
8154 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8155 tcg_gen_shli_i64(xtl, xtl, 32);
8156 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8157 tcg_gen_shri_i64(t0, t0, 32);
8158 tcg_gen_or_i64(xtl, xtl, t0);
8159 tcg_temp_free_i64(t0);
8160 break;
8161 }
8162 }
8163
8164 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8165 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8166
8167 tcg_temp_free_i64(xth);
8168 tcg_temp_free_i64(xtl);
8169 }
8170
8171 /*** Decimal Floating Point ***/
8172
8173 static inline TCGv_ptr gen_fprp_ptr(int reg)
8174 {
8175 TCGv_ptr r = tcg_temp_new_ptr();
8176 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8177 return r;
8178 }
8179
8180 #if defined(TARGET_PPC64)
8181 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8182 {
8183 TCGv_i32 tmp = tcg_temp_new_i32();
8184 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8185 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8186 tcg_temp_free_i32(tmp);
8187 }
8188 #else
8189 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8190 {
8191 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8192 }
8193 #endif
8194
8195 #define GEN_DFP_T_A_B_Rc(name) \
8196 static void gen_##name(DisasContext *ctx) \
8197 { \
8198 TCGv_ptr rd, ra, rb; \
8199 if (unlikely(!ctx->fpu_enabled)) { \
8200 gen_exception(ctx, POWERPC_EXCP_FPU); \
8201 return; \
8202 } \
8203 gen_update_nip(ctx, ctx->nip - 4); \
8204 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8205 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8206 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8207 gen_helper_##name(cpu_env, rd, ra, rb); \
8208 if (unlikely(Rc(ctx->opcode) != 0)) { \
8209 gen_set_cr6_from_fpscr(ctx); \
8210 } \
8211 tcg_temp_free_ptr(rd); \
8212 tcg_temp_free_ptr(ra); \
8213 tcg_temp_free_ptr(rb); \
8214 }
8215
8216 #define GEN_DFP_BF_A_B(name) \
8217 static void gen_##name(DisasContext *ctx) \
8218 { \
8219 TCGv_ptr ra, rb; \
8220 if (unlikely(!ctx->fpu_enabled)) { \
8221 gen_exception(ctx, POWERPC_EXCP_FPU); \
8222 return; \
8223 } \
8224 gen_update_nip(ctx, ctx->nip - 4); \
8225 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8226 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8227 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8228 cpu_env, ra, rb); \
8229 tcg_temp_free_ptr(ra); \
8230 tcg_temp_free_ptr(rb); \
8231 }
8232
8233 #define GEN_DFP_BF_A_DCM(name) \
8234 static void gen_##name(DisasContext *ctx) \
8235 { \
8236 TCGv_ptr ra; \
8237 TCGv_i32 dcm; \
8238 if (unlikely(!ctx->fpu_enabled)) { \
8239 gen_exception(ctx, POWERPC_EXCP_FPU); \
8240 return; \
8241 } \
8242 gen_update_nip(ctx, ctx->nip - 4); \
8243 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8244 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8245 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8246 cpu_env, ra, dcm); \
8247 tcg_temp_free_ptr(ra); \
8248 tcg_temp_free_i32(dcm); \
8249 }
8250
8251 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8252 static void gen_##name(DisasContext *ctx) \
8253 { \
8254 TCGv_ptr rt, rb; \
8255 TCGv_i32 u32_1, u32_2; \
8256 if (unlikely(!ctx->fpu_enabled)) { \
8257 gen_exception(ctx, POWERPC_EXCP_FPU); \
8258 return; \
8259 } \
8260 gen_update_nip(ctx, ctx->nip - 4); \
8261 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8262 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8263 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8264 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8265 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8266 if (unlikely(Rc(ctx->opcode) != 0)) { \
8267 gen_set_cr6_from_fpscr(ctx); \
8268 } \
8269 tcg_temp_free_ptr(rt); \
8270 tcg_temp_free_ptr(rb); \
8271 tcg_temp_free_i32(u32_1); \
8272 tcg_temp_free_i32(u32_2); \
8273 }
8274
8275 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8276 static void gen_##name(DisasContext *ctx) \
8277 { \
8278 TCGv_ptr rt, ra, rb; \
8279 TCGv_i32 i32; \
8280 if (unlikely(!ctx->fpu_enabled)) { \
8281 gen_exception(ctx, POWERPC_EXCP_FPU); \
8282 return; \
8283 } \
8284 gen_update_nip(ctx, ctx->nip - 4); \
8285 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8286 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8287 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8288 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8289 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8290 if (unlikely(Rc(ctx->opcode) != 0)) { \
8291 gen_set_cr6_from_fpscr(ctx); \
8292 } \
8293 tcg_temp_free_ptr(rt); \
8294 tcg_temp_free_ptr(rb); \
8295 tcg_temp_free_ptr(ra); \
8296 tcg_temp_free_i32(i32); \
8297 }
8298
8299 #define GEN_DFP_T_B_Rc(name) \
8300 static void gen_##name(DisasContext *ctx) \
8301 { \
8302 TCGv_ptr rt, rb; \
8303 if (unlikely(!ctx->fpu_enabled)) { \
8304 gen_exception(ctx, POWERPC_EXCP_FPU); \
8305 return; \
8306 } \
8307 gen_update_nip(ctx, ctx->nip - 4); \
8308 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8309 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8310 gen_helper_##name(cpu_env, rt, rb); \
8311 if (unlikely(Rc(ctx->opcode) != 0)) { \
8312 gen_set_cr6_from_fpscr(ctx); \
8313 } \
8314 tcg_temp_free_ptr(rt); \
8315 tcg_temp_free_ptr(rb); \
8316 }
8317
8318 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8319 static void gen_##name(DisasContext *ctx) \
8320 { \
8321 TCGv_ptr rt, rs; \
8322 TCGv_i32 i32; \
8323 if (unlikely(!ctx->fpu_enabled)) { \
8324 gen_exception(ctx, POWERPC_EXCP_FPU); \
8325 return; \
8326 } \
8327 gen_update_nip(ctx, ctx->nip - 4); \
8328 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8329 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8330 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8331 gen_helper_##name(cpu_env, rt, rs, i32); \
8332 if (unlikely(Rc(ctx->opcode) != 0)) { \
8333 gen_set_cr6_from_fpscr(ctx); \
8334 } \
8335 tcg_temp_free_ptr(rt); \
8336 tcg_temp_free_ptr(rs); \
8337 tcg_temp_free_i32(i32); \
8338 }
8339
8340 GEN_DFP_T_A_B_Rc(dadd)
8341 GEN_DFP_T_A_B_Rc(daddq)
8342 GEN_DFP_T_A_B_Rc(dsub)
8343 GEN_DFP_T_A_B_Rc(dsubq)
8344 GEN_DFP_T_A_B_Rc(dmul)
8345 GEN_DFP_T_A_B_Rc(dmulq)
8346 GEN_DFP_T_A_B_Rc(ddiv)
8347 GEN_DFP_T_A_B_Rc(ddivq)
8348 GEN_DFP_BF_A_B(dcmpu)
8349 GEN_DFP_BF_A_B(dcmpuq)
8350 GEN_DFP_BF_A_B(dcmpo)
8351 GEN_DFP_BF_A_B(dcmpoq)
8352 GEN_DFP_BF_A_DCM(dtstdc)
8353 GEN_DFP_BF_A_DCM(dtstdcq)
8354 GEN_DFP_BF_A_DCM(dtstdg)
8355 GEN_DFP_BF_A_DCM(dtstdgq)
8356 GEN_DFP_BF_A_B(dtstex)
8357 GEN_DFP_BF_A_B(dtstexq)
8358 GEN_DFP_BF_A_B(dtstsf)
8359 GEN_DFP_BF_A_B(dtstsfq)
8360 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8361 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8362 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8363 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8364 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8365 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8366 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8367 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8368 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8369 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8370 GEN_DFP_T_B_Rc(dctdp)
8371 GEN_DFP_T_B_Rc(dctqpq)
8372 GEN_DFP_T_B_Rc(drsp)
8373 GEN_DFP_T_B_Rc(drdpq)
8374 GEN_DFP_T_B_Rc(dcffix)
8375 GEN_DFP_T_B_Rc(dcffixq)
8376 GEN_DFP_T_B_Rc(dctfix)
8377 GEN_DFP_T_B_Rc(dctfixq)
8378 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8379 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8380 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8381 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8382 GEN_DFP_T_B_Rc(dxex)
8383 GEN_DFP_T_B_Rc(dxexq)
8384 GEN_DFP_T_A_B_Rc(diex)
8385 GEN_DFP_T_A_B_Rc(diexq)
8386 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8387 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8388 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8389 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8390
8391 /*** SPE extension ***/
8392 /* Register moves */
8393
8394 static inline void gen_evmra(DisasContext *ctx)
8395 {
8396
8397 if (unlikely(!ctx->spe_enabled)) {
8398 gen_exception(ctx, POWERPC_EXCP_SPEU);
8399 return;
8400 }
8401
8402 TCGv_i64 tmp = tcg_temp_new_i64();
8403
8404 /* tmp := rA_lo + rA_hi << 32 */
8405 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8406
8407 /* spe_acc := tmp */
8408 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8409 tcg_temp_free_i64(tmp);
8410
8411 /* rD := rA */
8412 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8413 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8414 }
8415
8416 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8417 {
8418 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8419 }
8420
8421 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8422 {
8423 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8424 }
8425
8426 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8427 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8428 { \
8429 if (Rc(ctx->opcode)) \
8430 gen_##name1(ctx); \
8431 else \
8432 gen_##name0(ctx); \
8433 }
8434
8435 /* Handler for undefined SPE opcodes */
8436 static inline void gen_speundef(DisasContext *ctx)
8437 {
8438 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8439 }
8440
8441 /* SPE logic */
8442 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8443 static inline void gen_##name(DisasContext *ctx) \
8444 { \
8445 if (unlikely(!ctx->spe_enabled)) { \
8446 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8447 return; \
8448 } \
8449 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8450 cpu_gpr[rB(ctx->opcode)]); \
8451 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8452 cpu_gprh[rB(ctx->opcode)]); \
8453 }
8454
8455 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8456 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8457 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8458 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8459 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8460 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8461 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8462 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8463
8464 /* SPE logic immediate */
8465 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8466 static inline void gen_##name(DisasContext *ctx) \
8467 { \
8468 TCGv_i32 t0; \
8469 if (unlikely(!ctx->spe_enabled)) { \
8470 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8471 return; \
8472 } \
8473 t0 = tcg_temp_new_i32(); \
8474 \
8475 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8476 tcg_opi(t0, t0, rB(ctx->opcode)); \
8477 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8478 \
8479 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8480 tcg_opi(t0, t0, rB(ctx->opcode)); \
8481 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8482 \
8483 tcg_temp_free_i32(t0); \
8484 }
8485 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8486 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8487 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8488 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8489
8490 /* SPE arithmetic */
8491 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8492 static inline void gen_##name(DisasContext *ctx) \
8493 { \
8494 TCGv_i32 t0; \
8495 if (unlikely(!ctx->spe_enabled)) { \
8496 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8497 return; \
8498 } \
8499 t0 = tcg_temp_new_i32(); \
8500 \
8501 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8502 tcg_op(t0, t0); \
8503 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8504 \
8505 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8506 tcg_op(t0, t0); \
8507 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8508 \
8509 tcg_temp_free_i32(t0); \
8510 }
8511
8512 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8513 {
8514 int l1 = gen_new_label();
8515 int l2 = gen_new_label();
8516
8517 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8518 tcg_gen_neg_i32(ret, arg1);
8519 tcg_gen_br(l2);
8520 gen_set_label(l1);
8521 tcg_gen_mov_i32(ret, arg1);
8522 gen_set_label(l2);
8523 }
8524 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8525 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8526 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8527 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8528 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8529 {
8530 tcg_gen_addi_i32(ret, arg1, 0x8000);
8531 tcg_gen_ext16u_i32(ret, ret);
8532 }
8533 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8534 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8535 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8536
8537 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8538 static inline void gen_##name(DisasContext *ctx) \
8539 { \
8540 TCGv_i32 t0, t1; \
8541 if (unlikely(!ctx->spe_enabled)) { \
8542 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8543 return; \
8544 } \
8545 t0 = tcg_temp_new_i32(); \
8546 t1 = tcg_temp_new_i32(); \
8547 \
8548 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8549 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8550 tcg_op(t0, t0, t1); \
8551 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8552 \
8553 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8554 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8555 tcg_op(t0, t0, t1); \
8556 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8557 \
8558 tcg_temp_free_i32(t0); \
8559 tcg_temp_free_i32(t1); \
8560 }
8561
8562 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8563 {
8564 TCGv_i32 t0;
8565 int l1, l2;
8566
8567 l1 = gen_new_label();
8568 l2 = gen_new_label();
8569 t0 = tcg_temp_local_new_i32();
8570 /* No error here: 6 bits are used */
8571 tcg_gen_andi_i32(t0, arg2, 0x3F);
8572 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8573 tcg_gen_shr_i32(ret, arg1, t0);
8574 tcg_gen_br(l2);
8575 gen_set_label(l1);
8576 tcg_gen_movi_i32(ret, 0);
8577 gen_set_label(l2);
8578 tcg_temp_free_i32(t0);
8579 }
8580 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8581 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8582 {
8583 TCGv_i32 t0;
8584 int l1, l2;
8585
8586 l1 = gen_new_label();
8587 l2 = gen_new_label();
8588 t0 = tcg_temp_local_new_i32();
8589 /* No error here: 6 bits are used */
8590 tcg_gen_andi_i32(t0, arg2, 0x3F);
8591 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8592 tcg_gen_sar_i32(ret, arg1, t0);
8593 tcg_gen_br(l2);
8594 gen_set_label(l1);
8595 tcg_gen_movi_i32(ret, 0);
8596 gen_set_label(l2);
8597 tcg_temp_free_i32(t0);
8598 }
8599 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8600 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8601 {
8602 TCGv_i32 t0;
8603 int l1, l2;
8604
8605 l1 = gen_new_label();
8606 l2 = gen_new_label();
8607 t0 = tcg_temp_local_new_i32();
8608 /* No error here: 6 bits are used */
8609 tcg_gen_andi_i32(t0, arg2, 0x3F);
8610 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8611 tcg_gen_shl_i32(ret, arg1, t0);
8612 tcg_gen_br(l2);
8613 gen_set_label(l1);
8614 tcg_gen_movi_i32(ret, 0);
8615 gen_set_label(l2);
8616 tcg_temp_free_i32(t0);
8617 }
8618 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8619 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8620 {
8621 TCGv_i32 t0 = tcg_temp_new_i32();
8622 tcg_gen_andi_i32(t0, arg2, 0x1F);
8623 tcg_gen_rotl_i32(ret, arg1, t0);
8624 tcg_temp_free_i32(t0);
8625 }
8626 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8627 static inline void gen_evmergehi(DisasContext *ctx)
8628 {
8629 if (unlikely(!ctx->spe_enabled)) {
8630 gen_exception(ctx, POWERPC_EXCP_SPEU);
8631 return;
8632 }
8633 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8634 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8635 }
8636 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8637 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8638 {
8639 tcg_gen_sub_i32(ret, arg2, arg1);
8640 }
8641 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8642
8643 /* SPE arithmetic immediate */
8644 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8645 static inline void gen_##name(DisasContext *ctx) \
8646 { \
8647 TCGv_i32 t0; \
8648 if (unlikely(!ctx->spe_enabled)) { \
8649 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8650 return; \
8651 } \
8652 t0 = tcg_temp_new_i32(); \
8653 \
8654 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8655 tcg_op(t0, t0, rA(ctx->opcode)); \
8656 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8657 \
8658 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8659 tcg_op(t0, t0, rA(ctx->opcode)); \
8660 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8661 \
8662 tcg_temp_free_i32(t0); \
8663 }
8664 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8665 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8666
8667 /* SPE comparison */
8668 #define GEN_SPEOP_COMP(name, tcg_cond) \
8669 static inline void gen_##name(DisasContext *ctx) \
8670 { \
8671 if (unlikely(!ctx->spe_enabled)) { \
8672 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8673 return; \
8674 } \
8675 int l1 = gen_new_label(); \
8676 int l2 = gen_new_label(); \
8677 int l3 = gen_new_label(); \
8678 int l4 = gen_new_label(); \
8679 \
8680 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8681 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8682 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8683 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8684 \
8685 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8686 cpu_gpr[rB(ctx->opcode)], l1); \
8687 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8688 tcg_gen_br(l2); \
8689 gen_set_label(l1); \
8690 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8691 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8692 gen_set_label(l2); \
8693 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8694 cpu_gprh[rB(ctx->opcode)], l3); \
8695 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8696 ~(CRF_CH | CRF_CH_AND_CL)); \
8697 tcg_gen_br(l4); \
8698 gen_set_label(l3); \
8699 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8700 CRF_CH | CRF_CH_OR_CL); \
8701 gen_set_label(l4); \
8702 }
8703 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8704 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8705 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8706 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8707 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8708
8709 /* SPE misc */
8710 static inline void gen_brinc(DisasContext *ctx)
8711 {
8712 /* Note: brinc is usable even if SPE is disabled */
8713 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8714 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8715 }
8716 static inline void gen_evmergelo(DisasContext *ctx)
8717 {
8718 if (unlikely(!ctx->spe_enabled)) {
8719 gen_exception(ctx, POWERPC_EXCP_SPEU);
8720 return;
8721 }
8722 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8723 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8724 }
8725 static inline void gen_evmergehilo(DisasContext *ctx)
8726 {
8727 if (unlikely(!ctx->spe_enabled)) {
8728 gen_exception(ctx, POWERPC_EXCP_SPEU);
8729 return;
8730 }
8731 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8732 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8733 }
8734 static inline void gen_evmergelohi(DisasContext *ctx)
8735 {
8736 if (unlikely(!ctx->spe_enabled)) {
8737 gen_exception(ctx, POWERPC_EXCP_SPEU);
8738 return;
8739 }
8740 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8741 TCGv tmp = tcg_temp_new();
8742 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8743 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8744 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8745 tcg_temp_free(tmp);
8746 } else {
8747 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8748 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8749 }
8750 }
8751 static inline void gen_evsplati(DisasContext *ctx)
8752 {
8753 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8754
8755 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8756 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8757 }
8758 static inline void gen_evsplatfi(DisasContext *ctx)
8759 {
8760 uint64_t imm = rA(ctx->opcode) << 27;
8761
8762 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8763 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8764 }
8765
8766 static inline void gen_evsel(DisasContext *ctx)
8767 {
8768 int l1 = gen_new_label();
8769 int l2 = gen_new_label();
8770 int l3 = gen_new_label();
8771 int l4 = gen_new_label();
8772 TCGv_i32 t0 = tcg_temp_local_new_i32();
8773 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8774 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8775 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8776 tcg_gen_br(l2);
8777 gen_set_label(l1);
8778 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8779 gen_set_label(l2);
8780 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8781 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8782 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8783 tcg_gen_br(l4);
8784 gen_set_label(l3);
8785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8786 gen_set_label(l4);
8787 tcg_temp_free_i32(t0);
8788 }
8789
8790 static void gen_evsel0(DisasContext *ctx)
8791 {
8792 gen_evsel(ctx);
8793 }
8794
8795 static void gen_evsel1(DisasContext *ctx)
8796 {
8797 gen_evsel(ctx);
8798 }
8799
8800 static void gen_evsel2(DisasContext *ctx)
8801 {
8802 gen_evsel(ctx);
8803 }
8804
8805 static void gen_evsel3(DisasContext *ctx)
8806 {
8807 gen_evsel(ctx);
8808 }
8809
8810 /* Multiply */
8811
8812 static inline void gen_evmwumi(DisasContext *ctx)
8813 {
8814 TCGv_i64 t0, t1;
8815
8816 if (unlikely(!ctx->spe_enabled)) {
8817 gen_exception(ctx, POWERPC_EXCP_SPEU);
8818 return;
8819 }
8820
8821 t0 = tcg_temp_new_i64();
8822 t1 = tcg_temp_new_i64();
8823
8824 /* t0 := rA; t1 := rB */
8825 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8826 tcg_gen_ext32u_i64(t0, t0);
8827 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8828 tcg_gen_ext32u_i64(t1, t1);
8829
8830 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8831
8832 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8833
8834 tcg_temp_free_i64(t0);
8835 tcg_temp_free_i64(t1);
8836 }
8837
8838 static inline void gen_evmwumia(DisasContext *ctx)
8839 {
8840 TCGv_i64 tmp;
8841
8842 if (unlikely(!ctx->spe_enabled)) {
8843 gen_exception(ctx, POWERPC_EXCP_SPEU);
8844 return;
8845 }
8846
8847 gen_evmwumi(ctx); /* rD := rA * rB */
8848
8849 tmp = tcg_temp_new_i64();
8850
8851 /* acc := rD */
8852 gen_load_gpr64(tmp, rD(ctx->opcode));
8853 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8854 tcg_temp_free_i64(tmp);
8855 }
8856
8857 static inline void gen_evmwumiaa(DisasContext *ctx)
8858 {
8859 TCGv_i64 acc;
8860 TCGv_i64 tmp;
8861
8862 if (unlikely(!ctx->spe_enabled)) {
8863 gen_exception(ctx, POWERPC_EXCP_SPEU);
8864 return;
8865 }
8866
8867 gen_evmwumi(ctx); /* rD := rA * rB */
8868
8869 acc = tcg_temp_new_i64();
8870 tmp = tcg_temp_new_i64();
8871
8872 /* tmp := rD */
8873 gen_load_gpr64(tmp, rD(ctx->opcode));
8874
8875 /* Load acc */
8876 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8877
8878 /* acc := tmp + acc */
8879 tcg_gen_add_i64(acc, acc, tmp);
8880
8881 /* Store acc */
8882 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8883
8884 /* rD := acc */
8885 gen_store_gpr64(rD(ctx->opcode), acc);
8886
8887 tcg_temp_free_i64(acc);
8888 tcg_temp_free_i64(tmp);
8889 }
8890
8891 static inline void gen_evmwsmi(DisasContext *ctx)
8892 {
8893 TCGv_i64 t0, t1;
8894
8895 if (unlikely(!ctx->spe_enabled)) {
8896 gen_exception(ctx, POWERPC_EXCP_SPEU);
8897 return;
8898 }
8899
8900 t0 = tcg_temp_new_i64();
8901 t1 = tcg_temp_new_i64();
8902
8903 /* t0 := rA; t1 := rB */
8904 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8905 tcg_gen_ext32s_i64(t0, t0);
8906 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8907 tcg_gen_ext32s_i64(t1, t1);
8908
8909 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8910
8911 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8912
8913 tcg_temp_free_i64(t0);
8914 tcg_temp_free_i64(t1);
8915 }
8916
8917 static inline void gen_evmwsmia(DisasContext *ctx)
8918 {
8919 TCGv_i64 tmp;
8920
8921 gen_evmwsmi(ctx); /* rD := rA * rB */
8922
8923 tmp = tcg_temp_new_i64();
8924
8925 /* acc := rD */
8926 gen_load_gpr64(tmp, rD(ctx->opcode));
8927 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8928
8929 tcg_temp_free_i64(tmp);
8930 }
8931
8932 static inline void gen_evmwsmiaa(DisasContext *ctx)
8933 {
8934 TCGv_i64 acc = tcg_temp_new_i64();
8935 TCGv_i64 tmp = tcg_temp_new_i64();
8936
8937 gen_evmwsmi(ctx); /* rD := rA * rB */
8938
8939 acc = tcg_temp_new_i64();
8940 tmp = tcg_temp_new_i64();
8941
8942 /* tmp := rD */
8943 gen_load_gpr64(tmp, rD(ctx->opcode));
8944
8945 /* Load acc */
8946 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8947
8948 /* acc := tmp + acc */
8949 tcg_gen_add_i64(acc, acc, tmp);
8950
8951 /* Store acc */
8952 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8953
8954 /* rD := acc */
8955 gen_store_gpr64(rD(ctx->opcode), acc);
8956
8957 tcg_temp_free_i64(acc);
8958 tcg_temp_free_i64(tmp);
8959 }
8960
8961 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8962 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8963 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8964 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8965 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8966 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8967 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8968 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8969 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8970 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8971 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8972 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8973 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8974 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8975 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8976 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8977 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8978 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8979 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8980 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8981 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8982 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8983 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8984 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8985 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8986 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8987 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8988 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8989 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8990
8991 /* SPE load and stores */
8992 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8993 {
8994 target_ulong uimm = rB(ctx->opcode);
8995
8996 if (rA(ctx->opcode) == 0) {
8997 tcg_gen_movi_tl(EA, uimm << sh);
8998 } else {
8999 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9000 if (NARROW_MODE(ctx)) {
9001 tcg_gen_ext32u_tl(EA, EA);
9002 }
9003 }
9004 }
9005
9006 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9007 {
9008 TCGv_i64 t0 = tcg_temp_new_i64();
9009 gen_qemu_ld64(ctx, t0, addr);
9010 gen_store_gpr64(rD(ctx->opcode), t0);
9011 tcg_temp_free_i64(t0);
9012 }
9013
9014 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9015 {
9016 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9017 gen_addr_add(ctx, addr, addr, 4);
9018 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9019 }
9020
9021 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9022 {
9023 TCGv t0 = tcg_temp_new();
9024 gen_qemu_ld16u(ctx, t0, addr);
9025 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9026 gen_addr_add(ctx, addr, addr, 2);
9027 gen_qemu_ld16u(ctx, t0, addr);
9028 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9029 gen_addr_add(ctx, addr, addr, 2);
9030 gen_qemu_ld16u(ctx, t0, addr);
9031 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9032 gen_addr_add(ctx, addr, addr, 2);
9033 gen_qemu_ld16u(ctx, t0, addr);
9034 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9035 tcg_temp_free(t0);
9036 }
9037
9038 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9039 {
9040 TCGv t0 = tcg_temp_new();
9041 gen_qemu_ld16u(ctx, t0, addr);
9042 tcg_gen_shli_tl(t0, t0, 16);
9043 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9044 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9045 tcg_temp_free(t0);
9046 }
9047
9048 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9049 {
9050 TCGv t0 = tcg_temp_new();
9051 gen_qemu_ld16u(ctx, t0, addr);
9052 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9053 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9054 tcg_temp_free(t0);
9055 }
9056
9057 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9058 {
9059 TCGv t0 = tcg_temp_new();
9060 gen_qemu_ld16s(ctx, t0, addr);
9061 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9062 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9063 tcg_temp_free(t0);
9064 }
9065
9066 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9067 {
9068 TCGv t0 = tcg_temp_new();
9069 gen_qemu_ld16u(ctx, t0, addr);
9070 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9071 gen_addr_add(ctx, addr, addr, 2);
9072 gen_qemu_ld16u(ctx, t0, addr);
9073 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9074 tcg_temp_free(t0);
9075 }
9076
9077 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9078 {
9079 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9080 gen_addr_add(ctx, addr, addr, 2);
9081 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9082 }
9083
9084 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9085 {
9086 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9087 gen_addr_add(ctx, addr, addr, 2);
9088 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9089 }
9090
9091 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9092 {
9093 TCGv t0 = tcg_temp_new();
9094 gen_qemu_ld32u(ctx, t0, addr);
9095 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9096 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9097 tcg_temp_free(t0);
9098 }
9099
9100 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9101 {
9102 TCGv t0 = tcg_temp_new();
9103 gen_qemu_ld16u(ctx, t0, addr);
9104 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9105 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9106 gen_addr_add(ctx, addr, addr, 2);
9107 gen_qemu_ld16u(ctx, t0, addr);
9108 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9109 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9110 tcg_temp_free(t0);
9111 }
9112
9113 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9114 {
9115 TCGv_i64 t0 = tcg_temp_new_i64();
9116 gen_load_gpr64(t0, rS(ctx->opcode));
9117 gen_qemu_st64(ctx, t0, addr);
9118 tcg_temp_free_i64(t0);
9119 }
9120
9121 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9122 {
9123 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9124 gen_addr_add(ctx, addr, addr, 4);
9125 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9126 }
9127
9128 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9129 {
9130 TCGv t0 = tcg_temp_new();
9131 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9132 gen_qemu_st16(ctx, t0, addr);
9133 gen_addr_add(ctx, addr, addr, 2);
9134 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9135 gen_addr_add(ctx, addr, addr, 2);
9136 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9137 gen_qemu_st16(ctx, t0, addr);
9138 tcg_temp_free(t0);
9139 gen_addr_add(ctx, addr, addr, 2);
9140 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9141 }
9142
9143 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9144 {
9145 TCGv t0 = tcg_temp_new();
9146 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9147 gen_qemu_st16(ctx, t0, addr);
9148 gen_addr_add(ctx, addr, addr, 2);
9149 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9150 gen_qemu_st16(ctx, t0, addr);
9151 tcg_temp_free(t0);
9152 }
9153
9154 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9155 {
9156 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9157 gen_addr_add(ctx, addr, addr, 2);
9158 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9159 }
9160
9161 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9162 {
9163 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9164 }
9165
9166 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9167 {
9168 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9169 }
9170
9171 #define GEN_SPEOP_LDST(name, opc2, sh) \
9172 static void glue(gen_, name)(DisasContext *ctx) \
9173 { \
9174 TCGv t0; \
9175 if (unlikely(!ctx->spe_enabled)) { \
9176 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9177 return; \
9178 } \
9179 gen_set_access_type(ctx, ACCESS_INT); \
9180 t0 = tcg_temp_new(); \
9181 if (Rc(ctx->opcode)) { \
9182 gen_addr_spe_imm_index(ctx, t0, sh); \
9183 } else { \
9184 gen_addr_reg_index(ctx, t0); \
9185 } \
9186 gen_op_##name(ctx, t0); \
9187 tcg_temp_free(t0); \
9188 }
9189
9190 GEN_SPEOP_LDST(evldd, 0x00, 3);
9191 GEN_SPEOP_LDST(evldw, 0x01, 3);
9192 GEN_SPEOP_LDST(evldh, 0x02, 3);
9193 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9194 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9195 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9196 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9197 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9198 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9199 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9200 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9201
9202 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9203 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9204 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9205 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9206 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9207 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9208 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9209
9210 /* Multiply and add - TODO */
9211 #if 0
9212 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9213 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9214 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9215 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9216 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9217 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9218 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9219 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9220 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9221 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9222 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9223 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9224
9225 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9226 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9227 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9228 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9229 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9230 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9231 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9232 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9233 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9234 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9235 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9236 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9237
9238 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9239 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9240 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9241 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9242 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9243
9244 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9245 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9246 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9247 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9248 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9249 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9250 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9251 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9252 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9253 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9254 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9255 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9256
9257 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9258 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9259 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9260 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9261
9262 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9263 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9264 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9265 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9266 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9267 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9268 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9269 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9270 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9271 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9272 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9273 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274
9275 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9276 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280 #endif
9281
9282 /*** SPE floating-point extension ***/
9283 #define GEN_SPEFPUOP_CONV_32_32(name) \
9284 static inline void gen_##name(DisasContext *ctx) \
9285 { \
9286 TCGv_i32 t0 = tcg_temp_new_i32(); \
9287 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9288 gen_helper_##name(t0, cpu_env, t0); \
9289 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9290 tcg_temp_free_i32(t0); \
9291 }
9292 #define GEN_SPEFPUOP_CONV_32_64(name) \
9293 static inline void gen_##name(DisasContext *ctx) \
9294 { \
9295 TCGv_i64 t0 = tcg_temp_new_i64(); \
9296 TCGv_i32 t1 = tcg_temp_new_i32(); \
9297 gen_load_gpr64(t0, rB(ctx->opcode)); \
9298 gen_helper_##name(t1, cpu_env, t0); \
9299 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9300 tcg_temp_free_i64(t0); \
9301 tcg_temp_free_i32(t1); \
9302 }
9303 #define GEN_SPEFPUOP_CONV_64_32(name) \
9304 static inline void gen_##name(DisasContext *ctx) \
9305 { \
9306 TCGv_i64 t0 = tcg_temp_new_i64(); \
9307 TCGv_i32 t1 = tcg_temp_new_i32(); \
9308 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9309 gen_helper_##name(t0, cpu_env, t1); \
9310 gen_store_gpr64(rD(ctx->opcode), t0); \
9311 tcg_temp_free_i64(t0); \
9312 tcg_temp_free_i32(t1); \
9313 }
9314 #define GEN_SPEFPUOP_CONV_64_64(name) \
9315 static inline void gen_##name(DisasContext *ctx) \
9316 { \
9317 TCGv_i64 t0 = tcg_temp_new_i64(); \
9318 gen_load_gpr64(t0, rB(ctx->opcode)); \
9319 gen_helper_##name(t0, cpu_env, t0); \
9320 gen_store_gpr64(rD(ctx->opcode), t0); \
9321 tcg_temp_free_i64(t0); \
9322 }
9323 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9324 static inline void gen_##name(DisasContext *ctx) \
9325 { \
9326 TCGv_i32 t0, t1; \
9327 if (unlikely(!ctx->spe_enabled)) { \
9328 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9329 return; \
9330 } \
9331 t0 = tcg_temp_new_i32(); \
9332 t1 = tcg_temp_new_i32(); \
9333 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9334 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9335 gen_helper_##name(t0, cpu_env, t0, t1); \
9336 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9337 \
9338 tcg_temp_free_i32(t0); \
9339 tcg_temp_free_i32(t1); \
9340 }
9341 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9342 static inline void gen_##name(DisasContext *ctx) \
9343 { \
9344 TCGv_i64 t0, t1; \
9345 if (unlikely(!ctx->spe_enabled)) { \
9346 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9347 return; \
9348 } \
9349 t0 = tcg_temp_new_i64(); \
9350 t1 = tcg_temp_new_i64(); \
9351 gen_load_gpr64(t0, rA(ctx->opcode)); \
9352 gen_load_gpr64(t1, rB(ctx->opcode)); \
9353 gen_helper_##name(t0, cpu_env, t0, t1); \
9354 gen_store_gpr64(rD(ctx->opcode), t0); \
9355 tcg_temp_free_i64(t0); \
9356 tcg_temp_free_i64(t1); \
9357 }
9358 #define GEN_SPEFPUOP_COMP_32(name) \
9359 static inline void gen_##name(DisasContext *ctx) \
9360 { \
9361 TCGv_i32 t0, t1; \
9362 if (unlikely(!ctx->spe_enabled)) { \
9363 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9364 return; \
9365 } \
9366 t0 = tcg_temp_new_i32(); \
9367 t1 = tcg_temp_new_i32(); \
9368 \
9369 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9370 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9371 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9372 \
9373 tcg_temp_free_i32(t0); \
9374 tcg_temp_free_i32(t1); \
9375 }
9376 #define GEN_SPEFPUOP_COMP_64(name) \
9377 static inline void gen_##name(DisasContext *ctx) \
9378 { \
9379 TCGv_i64 t0, t1; \
9380 if (unlikely(!ctx->spe_enabled)) { \
9381 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9382 return; \
9383 } \
9384 t0 = tcg_temp_new_i64(); \
9385 t1 = tcg_temp_new_i64(); \
9386 gen_load_gpr64(t0, rA(ctx->opcode)); \
9387 gen_load_gpr64(t1, rB(ctx->opcode)); \
9388 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9389 tcg_temp_free_i64(t0); \
9390 tcg_temp_free_i64(t1); \
9391 }
9392
9393 /* Single precision floating-point vectors operations */
9394 /* Arithmetic */
9395 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9396 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9397 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9398 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9399 static inline void gen_evfsabs(DisasContext *ctx)
9400 {
9401 if (unlikely(!ctx->spe_enabled)) {
9402 gen_exception(ctx, POWERPC_EXCP_SPEU);
9403 return;
9404 }
9405 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9406 ~0x80000000);
9407 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9408 ~0x80000000);
9409 }
9410 static inline void gen_evfsnabs(DisasContext *ctx)
9411 {
9412 if (unlikely(!ctx->spe_enabled)) {
9413 gen_exception(ctx, POWERPC_EXCP_SPEU);
9414 return;
9415 }
9416 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9417 0x80000000);
9418 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9419 0x80000000);
9420 }
9421 static inline void gen_evfsneg(DisasContext *ctx)
9422 {
9423 if (unlikely(!ctx->spe_enabled)) {
9424 gen_exception(ctx, POWERPC_EXCP_SPEU);
9425 return;
9426 }
9427 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9428 0x80000000);
9429 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9430 0x80000000);
9431 }
9432
9433 /* Conversion */
9434 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9435 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9436 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9437 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9438 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9439 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9440 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9441 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9442 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9443 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9444
9445 /* Comparison */
9446 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9447 GEN_SPEFPUOP_COMP_64(evfscmplt);
9448 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9449 GEN_SPEFPUOP_COMP_64(evfststgt);
9450 GEN_SPEFPUOP_COMP_64(evfststlt);
9451 GEN_SPEFPUOP_COMP_64(evfststeq);
9452
9453 /* Opcodes definitions */
9454 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9455 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9456 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9457 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9458 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9459 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9460 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9461 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9462 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9463 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9464 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9465 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9466 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9467 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9468
9469 /* Single precision floating-point operations */
9470 /* Arithmetic */
9471 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9472 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9473 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9474 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9475 static inline void gen_efsabs(DisasContext *ctx)
9476 {
9477 if (unlikely(!ctx->spe_enabled)) {
9478 gen_exception(ctx, POWERPC_EXCP_SPEU);
9479 return;
9480 }
9481 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9482 }
9483 static inline void gen_efsnabs(DisasContext *ctx)
9484 {
9485 if (unlikely(!ctx->spe_enabled)) {
9486 gen_exception(ctx, POWERPC_EXCP_SPEU);
9487 return;
9488 }
9489 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9490 }
9491 static inline void gen_efsneg(DisasContext *ctx)
9492 {
9493 if (unlikely(!ctx->spe_enabled)) {
9494 gen_exception(ctx, POWERPC_EXCP_SPEU);
9495 return;
9496 }
9497 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9498 }
9499
9500 /* Conversion */
9501 GEN_SPEFPUOP_CONV_32_32(efscfui);
9502 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9503 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9504 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9505 GEN_SPEFPUOP_CONV_32_32(efsctui);
9506 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9507 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9508 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9509 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9510 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9511 GEN_SPEFPUOP_CONV_32_64(efscfd);
9512
9513 /* Comparison */
9514 GEN_SPEFPUOP_COMP_32(efscmpgt);
9515 GEN_SPEFPUOP_COMP_32(efscmplt);
9516 GEN_SPEFPUOP_COMP_32(efscmpeq);
9517 GEN_SPEFPUOP_COMP_32(efststgt);
9518 GEN_SPEFPUOP_COMP_32(efststlt);
9519 GEN_SPEFPUOP_COMP_32(efststeq);
9520
9521 /* Opcodes definitions */
9522 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9523 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9524 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9526 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9527 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9528 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9529 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9530 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9531 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9532 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9533 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9534 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9535 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9536
9537 /* Double precision floating-point operations */
9538 /* Arithmetic */
9539 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9540 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9541 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9542 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9543 static inline void gen_efdabs(DisasContext *ctx)
9544 {
9545 if (unlikely(!ctx->spe_enabled)) {
9546 gen_exception(ctx, POWERPC_EXCP_SPEU);
9547 return;
9548 }
9549 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9550 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9551 ~0x80000000);
9552 }
9553 static inline void gen_efdnabs(DisasContext *ctx)
9554 {
9555 if (unlikely(!ctx->spe_enabled)) {
9556 gen_exception(ctx, POWERPC_EXCP_SPEU);
9557 return;
9558 }
9559 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9560 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9561 0x80000000);
9562 }
9563 static inline void gen_efdneg(DisasContext *ctx)
9564 {
9565 if (unlikely(!ctx->spe_enabled)) {
9566 gen_exception(ctx, POWERPC_EXCP_SPEU);
9567 return;
9568 }
9569 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9570 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9571 0x80000000);
9572 }
9573
9574 /* Conversion */
9575 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9576 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9577 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9578 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9579 GEN_SPEFPUOP_CONV_32_64(efdctui);
9580 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9581 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9582 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9583 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9584 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9585 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9586 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9587 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9588 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9589 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9590
9591 /* Comparison */
9592 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9593 GEN_SPEFPUOP_COMP_64(efdcmplt);
9594 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9595 GEN_SPEFPUOP_COMP_64(efdtstgt);
9596 GEN_SPEFPUOP_COMP_64(efdtstlt);
9597 GEN_SPEFPUOP_COMP_64(efdtsteq);
9598
9599 /* Opcodes definitions */
9600 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9601 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9602 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9603 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9604 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9605 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9606 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9607 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9608 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9609 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9610 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9611 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9612 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9613 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9614 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9615 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9616
9617 static opcode_t opcodes[] = {
9618 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9619 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9620 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9621 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9622 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9623 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9624 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9625 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9626 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9627 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9628 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9629 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9630 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9631 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9632 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9633 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9634 #if defined(TARGET_PPC64)
9635 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9636 #endif
9637 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9638 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9639 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9640 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9641 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9642 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9643 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9644 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9645 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9646 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9647 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9648 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9649 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9650 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9651 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9652 #if defined(TARGET_PPC64)
9653 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9654 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9655 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9656 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9657 #endif
9658 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9659 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9660 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9661 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9662 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9663 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9664 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9665 #if defined(TARGET_PPC64)
9666 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9667 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9668 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9669 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9670 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9671 #endif
9672 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9673 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9674 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9675 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9676 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9677 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9678 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9679 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9680 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9681 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9682 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9683 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9684 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9685 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9686 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9687 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9688 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9689 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9690 #if defined(TARGET_PPC64)
9691 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9692 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9693 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9694 #endif
9695 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9696 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9697 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9698 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9699 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9700 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9701 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9702 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9703 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9704 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9705 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9706 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9707 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9708 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9709 #if defined(TARGET_PPC64)
9710 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9711 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9712 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9713 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9714 #endif
9715 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9716 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9717 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9718 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9719 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9720 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9721 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9722 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9723 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9724 #if defined(TARGET_PPC64)
9725 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9726 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9727 #endif
9728 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9729 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9730 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9731 #if defined(TARGET_PPC64)
9732 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9733 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9734 #endif
9735 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9736 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9737 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9738 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9739 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9740 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9741 #if defined(TARGET_PPC64)
9742 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9743 #endif
9744 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9745 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9746 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9747 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9748 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9749 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9750 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9751 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9752 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9753 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9754 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9755 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9756 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9757 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9758 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9759 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9760 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9761 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9762 #if defined(TARGET_PPC64)
9763 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9764 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9765 PPC_SEGMENT_64B),
9766 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9767 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9768 PPC_SEGMENT_64B),
9769 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9770 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9771 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9772 #endif
9773 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9774 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9775 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9776 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9777 #if defined(TARGET_PPC64)
9778 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9779 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9780 #endif
9781 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9782 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9783 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9784 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9785 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9786 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9787 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9788 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9789 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9790 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9791 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9792 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9793 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9794 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9795 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9796 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9797 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9798 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9799 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9800 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9801 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9802 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9803 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9804 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9805 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9806 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9807 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9808 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9809 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9810 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9811 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9812 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9813 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9814 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9815 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9816 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9817 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9818 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9819 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9820 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9821 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9822 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9823 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9824 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9825 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9826 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9827 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9828 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9829 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9830 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9831 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9832 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9833 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9834 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9835 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9836 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9837 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9838 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9839 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9840 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9841 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9842 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9843 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9844 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9845 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9846 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9847 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9848 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9849 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9850 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9851 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9852 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9853 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9854 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9855 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9856 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9857 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9858 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9859 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9860 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9861 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9862 PPC_NONE, PPC2_BOOKE206),
9863 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9864 PPC_NONE, PPC2_BOOKE206),
9865 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9866 PPC_NONE, PPC2_BOOKE206),
9867 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9868 PPC_NONE, PPC2_BOOKE206),
9869 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9870 PPC_NONE, PPC2_BOOKE206),
9871 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9872 PPC_NONE, PPC2_PRCNTL),
9873 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9874 PPC_NONE, PPC2_PRCNTL),
9875 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9876 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9877 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9878 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9879 PPC_BOOKE, PPC2_BOOKE206),
9880 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9881 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9882 PPC_BOOKE, PPC2_BOOKE206),
9883 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9884 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9885 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9886 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9887 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9888 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9889 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9890 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9891 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9892
9893 #undef GEN_INT_ARITH_ADD
9894 #undef GEN_INT_ARITH_ADD_CONST
9895 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9896 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9897 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9898 add_ca, compute_ca, compute_ov) \
9899 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9900 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9901 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9902 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9903 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9904 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9905 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9906 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9907 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9908 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9909 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9910
9911 #undef GEN_INT_ARITH_DIVW
9912 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9913 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9914 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9915 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9916 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9917 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9918 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9919 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9920 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9921 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9922
9923 #if defined(TARGET_PPC64)
9924 #undef GEN_INT_ARITH_DIVD
9925 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9926 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9927 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9928 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9929 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9930 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9931
9932 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9933 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9934 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9935 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9936
9937 #undef GEN_INT_ARITH_MUL_HELPER
9938 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9939 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9940 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9941 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9942 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9943 #endif
9944
9945 #undef GEN_INT_ARITH_SUBF
9946 #undef GEN_INT_ARITH_SUBF_CONST
9947 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9948 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9949 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9950 add_ca, compute_ca, compute_ov) \
9951 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9952 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9953 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9954 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9955 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9956 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9957 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9958 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9959 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9960 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9961 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9962
9963 #undef GEN_LOGICAL1
9964 #undef GEN_LOGICAL2
9965 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9966 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9967 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9968 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9969 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9970 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9971 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9972 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9973 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9974 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9975 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9976 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9977 #if defined(TARGET_PPC64)
9978 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9979 #endif
9980
9981 #if defined(TARGET_PPC64)
9982 #undef GEN_PPC64_R2
9983 #undef GEN_PPC64_R4
9984 #define GEN_PPC64_R2(name, opc1, opc2) \
9985 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9986 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9987 PPC_64B)
9988 #define GEN_PPC64_R4(name, opc1, opc2) \
9989 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9990 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9991 PPC_64B), \
9992 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9993 PPC_64B), \
9994 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9995 PPC_64B)
9996 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9997 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9998 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9999 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10000 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10001 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10002 #endif
10003
10004 #undef _GEN_FLOAT_ACB
10005 #undef GEN_FLOAT_ACB
10006 #undef _GEN_FLOAT_AB
10007 #undef GEN_FLOAT_AB
10008 #undef _GEN_FLOAT_AC
10009 #undef GEN_FLOAT_AC
10010 #undef GEN_FLOAT_B
10011 #undef GEN_FLOAT_BS
10012 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10013 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10014 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10015 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10016 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10017 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10018 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10019 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10020 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10021 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10022 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10023 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10024 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10025 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10026 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10027 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10028 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10029 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10030 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10031
10032 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10033 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10034 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10035 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10036 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10037 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10038 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10039 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10040 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10041 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10042 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10043 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10044 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10045 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10046 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10047 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10048 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10049 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10050 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10051 #if defined(TARGET_PPC64)
10052 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10053 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10054 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10055 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10056 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10057 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10058 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10059 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10060 #endif
10061 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10062 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10063 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10064 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10065
10066 #undef GEN_LD
10067 #undef GEN_LDU
10068 #undef GEN_LDUX
10069 #undef GEN_LDX_E
10070 #undef GEN_LDS
10071 #define GEN_LD(name, ldop, opc, type) \
10072 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10073 #define GEN_LDU(name, ldop, opc, type) \
10074 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10075 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10076 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10077 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10078 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10079 #define GEN_LDS(name, ldop, op, type) \
10080 GEN_LD(name, ldop, op | 0x20, type) \
10081 GEN_LDU(name, ldop, op | 0x21, type) \
10082 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10083 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10084
10085 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10086 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10087 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10088 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10089 #if defined(TARGET_PPC64)
10090 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10091 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10092 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10093 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10094 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10095 #endif
10096 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10097 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10098
10099 #undef GEN_ST
10100 #undef GEN_STU
10101 #undef GEN_STUX
10102 #undef GEN_STX_E
10103 #undef GEN_STS
10104 #define GEN_ST(name, stop, opc, type) \
10105 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10106 #define GEN_STU(name, stop, opc, type) \
10107 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10108 #define GEN_STUX(name, stop, opc2, opc3, type) \
10109 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10110 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10111 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10112 #define GEN_STS(name, stop, op, type) \
10113 GEN_ST(name, stop, op | 0x20, type) \
10114 GEN_STU(name, stop, op | 0x21, type) \
10115 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10116 GEN_STX(name, stop, 0x17, op | 0x00, type)
10117
10118 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10119 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10120 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10121 #if defined(TARGET_PPC64)
10122 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10123 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10124 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10125 #endif
10126 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10127 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10128
10129 #undef GEN_LDF
10130 #undef GEN_LDUF
10131 #undef GEN_LDUXF
10132 #undef GEN_LDXF
10133 #undef GEN_LDFS
10134 #define GEN_LDF(name, ldop, opc, type) \
10135 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10136 #define GEN_LDUF(name, ldop, opc, type) \
10137 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10138 #define GEN_LDUXF(name, ldop, opc, type) \
10139 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10140 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10141 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10142 #define GEN_LDFS(name, ldop, op, type) \
10143 GEN_LDF(name, ldop, op | 0x20, type) \
10144 GEN_LDUF(name, ldop, op | 0x21, type) \
10145 GEN_LDUXF(name, ldop, op | 0x01, type) \
10146 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10147
10148 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10149 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10150 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10151 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10152 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10153 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10154
10155 #undef GEN_STF
10156 #undef GEN_STUF
10157 #undef GEN_STUXF
10158 #undef GEN_STXF
10159 #undef GEN_STFS
10160 #define GEN_STF(name, stop, opc, type) \
10161 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10162 #define GEN_STUF(name, stop, opc, type) \
10163 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10164 #define GEN_STUXF(name, stop, opc, type) \
10165 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10166 #define GEN_STXF(name, stop, opc2, opc3, type) \
10167 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10168 #define GEN_STFS(name, stop, op, type) \
10169 GEN_STF(name, stop, op | 0x20, type) \
10170 GEN_STUF(name, stop, op | 0x21, type) \
10171 GEN_STUXF(name, stop, op | 0x01, type) \
10172 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10173
10174 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10175 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10176 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10177 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10178 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10179
10180 #undef GEN_CRLOGIC
10181 #define GEN_CRLOGIC(name, tcg_op, opc) \
10182 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10183 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10184 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10185 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10186 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10187 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10188 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10189 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10190 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10191
10192 #undef GEN_MAC_HANDLER
10193 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10194 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10195 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10196 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10197 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10198 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10199 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10200 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10201 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10202 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10203 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10204 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10205 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10206 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10207 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10208 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10209 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10210 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10211 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10212 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10213 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10214 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10215 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10216 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10217 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10218 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10219 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10220 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10221 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10222 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10223 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10224 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10225 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10226 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10227 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10228 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10229 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10230 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10231 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10232 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10233 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10234 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10235 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10236 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10237
10238 #undef GEN_VR_LDX
10239 #undef GEN_VR_STX
10240 #undef GEN_VR_LVE
10241 #undef GEN_VR_STVE
10242 #define GEN_VR_LDX(name, opc2, opc3) \
10243 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10244 #define GEN_VR_STX(name, opc2, opc3) \
10245 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10246 #define GEN_VR_LVE(name, opc2, opc3) \
10247 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10248 #define GEN_VR_STVE(name, opc2, opc3) \
10249 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10250 GEN_VR_LDX(lvx, 0x07, 0x03),
10251 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10252 GEN_VR_LVE(bx, 0x07, 0x00),
10253 GEN_VR_LVE(hx, 0x07, 0x01),
10254 GEN_VR_LVE(wx, 0x07, 0x02),
10255 GEN_VR_STX(svx, 0x07, 0x07),
10256 GEN_VR_STX(svxl, 0x07, 0x0F),
10257 GEN_VR_STVE(bx, 0x07, 0x04),
10258 GEN_VR_STVE(hx, 0x07, 0x05),
10259 GEN_VR_STVE(wx, 0x07, 0x06),
10260
10261 #undef GEN_VX_LOGICAL
10262 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10263 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10264
10265 #undef GEN_VX_LOGICAL_207
10266 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10267 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10268
10269 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10270 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10271 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10272 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10273 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10274 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10275 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10276 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10277
10278 #undef GEN_VXFORM
10279 #define GEN_VXFORM(name, opc2, opc3) \
10280 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10281
10282 #undef GEN_VXFORM_207
10283 #define GEN_VXFORM_207(name, opc2, opc3) \
10284 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10285
10286 #undef GEN_VXFORM_DUAL
10287 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10288 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10289
10290 #undef GEN_VXRFORM_DUAL
10291 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10292 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10293 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10294
10295 GEN_VXFORM(vaddubm, 0, 0),
10296 GEN_VXFORM(vadduhm, 0, 1),
10297 GEN_VXFORM(vadduwm, 0, 2),
10298 GEN_VXFORM_207(vaddudm, 0, 3),
10299 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10300 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10301 GEN_VXFORM(vsubuwm, 0, 18),
10302 GEN_VXFORM_207(vsubudm, 0, 19),
10303 GEN_VXFORM(vmaxub, 1, 0),
10304 GEN_VXFORM(vmaxuh, 1, 1),
10305 GEN_VXFORM(vmaxuw, 1, 2),
10306 GEN_VXFORM_207(vmaxud, 1, 3),
10307 GEN_VXFORM(vmaxsb, 1, 4),
10308 GEN_VXFORM(vmaxsh, 1, 5),
10309 GEN_VXFORM(vmaxsw, 1, 6),
10310 GEN_VXFORM_207(vmaxsd, 1, 7),
10311 GEN_VXFORM(vminub, 1, 8),
10312 GEN_VXFORM(vminuh, 1, 9),
10313 GEN_VXFORM(vminuw, 1, 10),
10314 GEN_VXFORM_207(vminud, 1, 11),
10315 GEN_VXFORM(vminsb, 1, 12),
10316 GEN_VXFORM(vminsh, 1, 13),
10317 GEN_VXFORM(vminsw, 1, 14),
10318 GEN_VXFORM_207(vminsd, 1, 15),
10319 GEN_VXFORM(vavgub, 1, 16),
10320 GEN_VXFORM(vavguh, 1, 17),
10321 GEN_VXFORM(vavguw, 1, 18),
10322 GEN_VXFORM(vavgsb, 1, 20),
10323 GEN_VXFORM(vavgsh, 1, 21),
10324 GEN_VXFORM(vavgsw, 1, 22),
10325 GEN_VXFORM(vmrghb, 6, 0),
10326 GEN_VXFORM(vmrghh, 6, 1),
10327 GEN_VXFORM(vmrghw, 6, 2),
10328 GEN_VXFORM(vmrglb, 6, 4),
10329 GEN_VXFORM(vmrglh, 6, 5),
10330 GEN_VXFORM(vmrglw, 6, 6),
10331 GEN_VXFORM_207(vmrgew, 6, 30),
10332 GEN_VXFORM_207(vmrgow, 6, 26),
10333 GEN_VXFORM(vmuloub, 4, 0),
10334 GEN_VXFORM(vmulouh, 4, 1),
10335 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10336 GEN_VXFORM(vmulosb, 4, 4),
10337 GEN_VXFORM(vmulosh, 4, 5),
10338 GEN_VXFORM_207(vmulosw, 4, 6),
10339 GEN_VXFORM(vmuleub, 4, 8),
10340 GEN_VXFORM(vmuleuh, 4, 9),
10341 GEN_VXFORM_207(vmuleuw, 4, 10),
10342 GEN_VXFORM(vmulesb, 4, 12),
10343 GEN_VXFORM(vmulesh, 4, 13),
10344 GEN_VXFORM_207(vmulesw, 4, 14),
10345 GEN_VXFORM(vslb, 2, 4),
10346 GEN_VXFORM(vslh, 2, 5),
10347 GEN_VXFORM(vslw, 2, 6),
10348 GEN_VXFORM_207(vsld, 2, 23),
10349 GEN_VXFORM(vsrb, 2, 8),
10350 GEN_VXFORM(vsrh, 2, 9),
10351 GEN_VXFORM(vsrw, 2, 10),
10352 GEN_VXFORM_207(vsrd, 2, 27),
10353 GEN_VXFORM(vsrab, 2, 12),
10354 GEN_VXFORM(vsrah, 2, 13),
10355 GEN_VXFORM(vsraw, 2, 14),
10356 GEN_VXFORM_207(vsrad, 2, 15),
10357 GEN_VXFORM(vslo, 6, 16),
10358 GEN_VXFORM(vsro, 6, 17),
10359 GEN_VXFORM(vaddcuw, 0, 6),
10360 GEN_VXFORM(vsubcuw, 0, 22),
10361 GEN_VXFORM(vaddubs, 0, 8),
10362 GEN_VXFORM(vadduhs, 0, 9),
10363 GEN_VXFORM(vadduws, 0, 10),
10364 GEN_VXFORM(vaddsbs, 0, 12),
10365 GEN_VXFORM(vaddshs, 0, 13),
10366 GEN_VXFORM(vaddsws, 0, 14),
10367 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10368 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10369 GEN_VXFORM(vsubuws, 0, 26),
10370 GEN_VXFORM(vsubsbs, 0, 28),
10371 GEN_VXFORM(vsubshs, 0, 29),
10372 GEN_VXFORM(vsubsws, 0, 30),
10373 GEN_VXFORM_207(vadduqm, 0, 4),
10374 GEN_VXFORM_207(vaddcuq, 0, 5),
10375 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10376 GEN_VXFORM_207(vsubuqm, 0, 20),
10377 GEN_VXFORM_207(vsubcuq, 0, 21),
10378 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10379 GEN_VXFORM(vrlb, 2, 0),
10380 GEN_VXFORM(vrlh, 2, 1),
10381 GEN_VXFORM(vrlw, 2, 2),
10382 GEN_VXFORM_207(vrld, 2, 3),
10383 GEN_VXFORM(vsl, 2, 7),
10384 GEN_VXFORM(vsr, 2, 11),
10385 GEN_VXFORM(vpkuhum, 7, 0),
10386 GEN_VXFORM(vpkuwum, 7, 1),
10387 GEN_VXFORM_207(vpkudum, 7, 17),
10388 GEN_VXFORM(vpkuhus, 7, 2),
10389 GEN_VXFORM(vpkuwus, 7, 3),
10390 GEN_VXFORM_207(vpkudus, 7, 19),
10391 GEN_VXFORM(vpkshus, 7, 4),
10392 GEN_VXFORM(vpkswus, 7, 5),
10393 GEN_VXFORM_207(vpksdus, 7, 21),
10394 GEN_VXFORM(vpkshss, 7, 6),
10395 GEN_VXFORM(vpkswss, 7, 7),
10396 GEN_VXFORM_207(vpksdss, 7, 23),
10397 GEN_VXFORM(vpkpx, 7, 12),
10398 GEN_VXFORM(vsum4ubs, 4, 24),
10399 GEN_VXFORM(vsum4sbs, 4, 28),
10400 GEN_VXFORM(vsum4shs, 4, 25),
10401 GEN_VXFORM(vsum2sws, 4, 26),
10402 GEN_VXFORM(vsumsws, 4, 30),
10403 GEN_VXFORM(vaddfp, 5, 0),
10404 GEN_VXFORM(vsubfp, 5, 1),
10405 GEN_VXFORM(vmaxfp, 5, 16),
10406 GEN_VXFORM(vminfp, 5, 17),
10407
10408 #undef GEN_VXRFORM1
10409 #undef GEN_VXRFORM
10410 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10411 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10412 #define GEN_VXRFORM(name, opc2, opc3) \
10413 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10414 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10415 GEN_VXRFORM(vcmpequb, 3, 0)
10416 GEN_VXRFORM(vcmpequh, 3, 1)
10417 GEN_VXRFORM(vcmpequw, 3, 2)
10418 GEN_VXRFORM(vcmpgtsb, 3, 12)
10419 GEN_VXRFORM(vcmpgtsh, 3, 13)
10420 GEN_VXRFORM(vcmpgtsw, 3, 14)
10421 GEN_VXRFORM(vcmpgtub, 3, 8)
10422 GEN_VXRFORM(vcmpgtuh, 3, 9)
10423 GEN_VXRFORM(vcmpgtuw, 3, 10)
10424 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10425 GEN_VXRFORM(vcmpgefp, 3, 7)
10426 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10427 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10428
10429 #undef GEN_VXFORM_SIMM
10430 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10431 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10432 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10433 GEN_VXFORM_SIMM(vspltish, 6, 13),
10434 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10435
10436 #undef GEN_VXFORM_NOA
10437 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10438 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10439 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10440 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10441 GEN_VXFORM_207(vupkhsw, 7, 25),
10442 GEN_VXFORM_NOA(vupklsb, 7, 10),
10443 GEN_VXFORM_NOA(vupklsh, 7, 11),
10444 GEN_VXFORM_207(vupklsw, 7, 27),
10445 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10446 GEN_VXFORM_NOA(vupklpx, 7, 15),
10447 GEN_VXFORM_NOA(vrefp, 5, 4),
10448 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10449 GEN_VXFORM_NOA(vexptefp, 5, 6),
10450 GEN_VXFORM_NOA(vlogefp, 5, 7),
10451 GEN_VXFORM_NOA(vrfim, 5, 8),
10452 GEN_VXFORM_NOA(vrfin, 5, 9),
10453 GEN_VXFORM_NOA(vrfip, 5, 10),
10454 GEN_VXFORM_NOA(vrfiz, 5, 11),
10455
10456 #undef GEN_VXFORM_UIMM
10457 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10458 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10459 GEN_VXFORM_UIMM(vspltb, 6, 8),
10460 GEN_VXFORM_UIMM(vsplth, 6, 9),
10461 GEN_VXFORM_UIMM(vspltw, 6, 10),
10462 GEN_VXFORM_UIMM(vcfux, 5, 12),
10463 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10464 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10465 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10466
10467 #undef GEN_VAFORM_PAIRED
10468 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10469 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10470 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10471 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10472 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10473 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10474 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10475 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10476
10477 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10478 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10479 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10480 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10481
10482 GEN_VXFORM_207(vbpermq, 6, 21),
10483 GEN_VXFORM_207(vgbbd, 6, 20),
10484 GEN_VXFORM_207(vpmsumb, 4, 16),
10485 GEN_VXFORM_207(vpmsumh, 4, 17),
10486 GEN_VXFORM_207(vpmsumw, 4, 18),
10487 GEN_VXFORM_207(vpmsumd, 4, 19),
10488
10489 GEN_VXFORM_207(vsbox, 4, 23),
10490
10491 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10492 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10493
10494 GEN_VXFORM_207(vshasigmaw, 1, 26),
10495 GEN_VXFORM_207(vshasigmad, 1, 27),
10496
10497 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10498
10499 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10500 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10501 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10502 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10503 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10504 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10505 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10506
10507 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10508 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10509 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10510 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10511 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10512
10513 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10514 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10515 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10516 #if defined(TARGET_PPC64)
10517 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10518 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10519 #endif
10520
10521 #undef GEN_XX2FORM
10522 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10523 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10524 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10525
10526 #undef GEN_XX3FORM
10527 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10528 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10529 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10530 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10531 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10532
10533 #undef GEN_XX3_RC_FORM
10534 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10535 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10536 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10537 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10538 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10539 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10540 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10541 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10542 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10543
10544 #undef GEN_XX3FORM_DM
10545 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10546 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10547 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10548 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10549 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10550 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10551 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10552 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10553 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10554 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10555 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10556 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10557 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10558 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10559 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10560 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10561 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10562
10563 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10564 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10565 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10566 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10567
10568 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10569 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10570 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10571 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10572 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10573 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10574 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10575 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10576
10577 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10578 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10579 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10580 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10581 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10582 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10583 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10584 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10585 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10586 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10587 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10588 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10589 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10590 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10591 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10592 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10593 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10594 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10595 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10596 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10597 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10598 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10599 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10600 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10601 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10602 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10603 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10604 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10605 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10606 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10607 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10608 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10609 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10610 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10611 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10612 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10613
10614 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10615 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10616 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10617 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10618 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10619 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10620 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10621 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10622 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10623 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10624 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10625 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10626 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10627 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10628 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10629 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10630 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10631 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10632
10633 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10634 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10635 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10636 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10637 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10638 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10639 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10640 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10641 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10642 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10643 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10644 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10645 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10646 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10647 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10648 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10649 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10650 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10651 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10652 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10653 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10654 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10655 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10656 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10657 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10658 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10659 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10660 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10661 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10662 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10663 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10664 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10665 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10666 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10667 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10668 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10669
10670 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10671 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10672 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10673 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10674 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10675 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10676 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10677 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10678 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10679 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10680 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10681 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10682 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10683 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10684 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10685 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10686 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10687 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10688 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10689 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10690 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10691 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10692 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10693 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10694 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10695 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10696 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10697 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10698 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10699 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10700 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10701 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10702 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10703 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10704 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10705 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10706
10707 #undef VSX_LOGICAL
10708 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10709 GEN_XX3FORM(name, opc2, opc3, fl2)
10710
10711 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10712 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10713 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10714 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10715 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10716 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10717 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10718 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10719 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10720 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10721 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10722 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10723
10724 #define GEN_XXSEL_ROW(opc3) \
10725 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10726 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10727 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10728 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10729 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10730 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10731 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10732 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10733
10734 GEN_XXSEL_ROW(0x00)
10735 GEN_XXSEL_ROW(0x01)
10736 GEN_XXSEL_ROW(0x02)
10737 GEN_XXSEL_ROW(0x03)
10738 GEN_XXSEL_ROW(0x04)
10739 GEN_XXSEL_ROW(0x05)
10740 GEN_XXSEL_ROW(0x06)
10741 GEN_XXSEL_ROW(0x07)
10742 GEN_XXSEL_ROW(0x08)
10743 GEN_XXSEL_ROW(0x09)
10744 GEN_XXSEL_ROW(0x0A)
10745 GEN_XXSEL_ROW(0x0B)
10746 GEN_XXSEL_ROW(0x0C)
10747 GEN_XXSEL_ROW(0x0D)
10748 GEN_XXSEL_ROW(0x0E)
10749 GEN_XXSEL_ROW(0x0F)
10750 GEN_XXSEL_ROW(0x10)
10751 GEN_XXSEL_ROW(0x11)
10752 GEN_XXSEL_ROW(0x12)
10753 GEN_XXSEL_ROW(0x13)
10754 GEN_XXSEL_ROW(0x14)
10755 GEN_XXSEL_ROW(0x15)
10756 GEN_XXSEL_ROW(0x16)
10757 GEN_XXSEL_ROW(0x17)
10758 GEN_XXSEL_ROW(0x18)
10759 GEN_XXSEL_ROW(0x19)
10760 GEN_XXSEL_ROW(0x1A)
10761 GEN_XXSEL_ROW(0x1B)
10762 GEN_XXSEL_ROW(0x1C)
10763 GEN_XXSEL_ROW(0x1D)
10764 GEN_XXSEL_ROW(0x1E)
10765 GEN_XXSEL_ROW(0x1F)
10766
10767 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10768
10769 #undef GEN_DFP_T_A_B_Rc
10770 #undef GEN_DFP_BF_A_B
10771 #undef GEN_DFP_BF_A_DCM
10772 #undef GEN_DFP_T_B_U32_U32_Rc
10773 #undef GEN_DFP_T_A_B_I32_Rc
10774 #undef GEN_DFP_T_B_Rc
10775 #undef GEN_DFP_T_FPR_I32_Rc
10776
10777 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10778 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10779
10780 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10781 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10782 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10783
10784 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10785 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10786 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10787 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10788 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10789
10790 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10791 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10792
10793 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10794 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10795 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10796
10797 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10798 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10799 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10800 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10801 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10802
10803 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10804 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10805
10806 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10807 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10808
10809 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10810 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10811
10812 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10813 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10814
10815 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10816 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10817
10818 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10819 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10820
10821 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10822 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10823
10824 #define GEN_DFP_BF_A_B(name, op1, op2) \
10825 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10826
10827 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10828 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10829
10830 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10831 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10832
10833 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10834 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10835
10836 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10837 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10838
10839 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10840 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10841
10842 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10843 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10844
10845 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10846 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10847
10848 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10849 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10850
10851 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10852 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10853
10854 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10855 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10856
10857 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10858 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10859
10860 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10861 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10862
10863 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10864 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10865
10866 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10867 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10868
10869 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10870 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10871
10872 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10873 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10874
10875 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10876 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10877
10878 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10879 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10880 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10881 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10882 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10883 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10884 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10885 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10886 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10887 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10888 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10889 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10890 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10891 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10892 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10893 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10894 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10895 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10896 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10897 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10898 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10899 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10900 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10901 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10902 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10903 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10904 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10905 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10906 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10907 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10908 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10909 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
10910 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10911 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
10912 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10913 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
10914 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10915 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
10916 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10917 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
10918 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10919 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
10920 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10921 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
10922 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10923 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
10924 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10925 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10926 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10927 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10928
10929 #undef GEN_SPE
10930 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10931 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10932 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10933 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10934 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10935 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10936 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10937 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10938 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10939 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10940 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10941 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10942 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10943 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10944 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10945 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10946 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10947 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10948 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10949 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10950 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10951 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10952 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10953 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10954 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10955 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10956 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10957 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10958 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10959 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10960 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10961
10962 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10963 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10964 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10965 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10966 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10967 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10968 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10969 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10970 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10971 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10972 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10973 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10974 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10975 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10976
10977 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10978 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10979 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10980 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10981 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10982 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10983 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10984 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10985 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10986 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10987 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10988 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10989 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10990 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10991
10992 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10993 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10994 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10995 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10996 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10997 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10998 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10999 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11000 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11001 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11002 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11003 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11004 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11005 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11006 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11007 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11008
11009 #undef GEN_SPEOP_LDST
11010 #define GEN_SPEOP_LDST(name, opc2, sh) \
11011 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11012 GEN_SPEOP_LDST(evldd, 0x00, 3),
11013 GEN_SPEOP_LDST(evldw, 0x01, 3),
11014 GEN_SPEOP_LDST(evldh, 0x02, 3),
11015 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11016 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11017 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11018 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11019 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11020 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11021 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11022 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11023
11024 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11025 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11026 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11027 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11028 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11029 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11030 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11031 };
11032
11033 #include "helper_regs.h"
11034 #include "translate_init.c"
11035
11036 /*****************************************************************************/
11037 /* Misc PowerPC helpers */
11038 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11039 int flags)
11040 {
11041 #define RGPL 4
11042 #define RFPL 4
11043
11044 PowerPCCPU *cpu = POWERPC_CPU(cs);
11045 CPUPPCState *env = &cpu->env;
11046 int i;
11047
11048 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11049 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11050 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11051 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11052 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11053 env->hflags, env->mmu_idx);
11054 #if !defined(NO_TIMER_DUMP)
11055 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11056 #if !defined(CONFIG_USER_ONLY)
11057 " DECR %08" PRIu32
11058 #endif
11059 "\n",
11060 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11061 #if !defined(CONFIG_USER_ONLY)
11062 , cpu_ppc_load_decr(env)
11063 #endif
11064 );
11065 #endif
11066 for (i = 0; i < 32; i++) {
11067 if ((i & (RGPL - 1)) == 0)
11068 cpu_fprintf(f, "GPR%02d", i);
11069 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11070 if ((i & (RGPL - 1)) == (RGPL - 1))
11071 cpu_fprintf(f, "\n");
11072 }
11073 cpu_fprintf(f, "CR ");
11074 for (i = 0; i < 8; i++)
11075 cpu_fprintf(f, "%01x", env->crf[i]);
11076 cpu_fprintf(f, " [");
11077 for (i = 0; i < 8; i++) {
11078 char a = '-';
11079 if (env->crf[i] & 0x08)
11080 a = 'L';
11081 else if (env->crf[i] & 0x04)
11082 a = 'G';
11083 else if (env->crf[i] & 0x02)
11084 a = 'E';
11085 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11086 }
11087 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11088 env->reserve_addr);
11089 for (i = 0; i < 32; i++) {
11090 if ((i & (RFPL - 1)) == 0)
11091 cpu_fprintf(f, "FPR%02d", i);
11092 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11093 if ((i & (RFPL - 1)) == (RFPL - 1))
11094 cpu_fprintf(f, "\n");
11095 }
11096 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11097 #if !defined(CONFIG_USER_ONLY)
11098 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11099 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11100 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11101 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11102
11103 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11104 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11105 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11106 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11107
11108 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11109 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11110 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11111 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11112
11113 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11114 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11115 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11116 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11117 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11118
11119 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11120 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11121 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11122 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11123
11124 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11125 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11126 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11127 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11128
11129 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11130 " EPR " TARGET_FMT_lx "\n",
11131 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11132 env->spr[SPR_BOOKE_EPR]);
11133
11134 /* FSL-specific */
11135 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11136 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11137 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11138 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11139
11140 /*
11141 * IVORs are left out as they are large and do not change often --
11142 * they can be read with "p $ivor0", "p $ivor1", etc.
11143 */
11144 }
11145
11146 #if defined(TARGET_PPC64)
11147 if (env->flags & POWERPC_FLAG_CFAR) {
11148 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11149 }
11150 #endif
11151
11152 switch (env->mmu_model) {
11153 case POWERPC_MMU_32B:
11154 case POWERPC_MMU_601:
11155 case POWERPC_MMU_SOFT_6xx:
11156 case POWERPC_MMU_SOFT_74xx:
11157 #if defined(TARGET_PPC64)
11158 case POWERPC_MMU_64B:
11159 case POWERPC_MMU_2_06:
11160 case POWERPC_MMU_2_06a:
11161 case POWERPC_MMU_2_06d:
11162 #endif
11163 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11164 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11165 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11166 break;
11167 case POWERPC_MMU_BOOKE206:
11168 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11169 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11170 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11171 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11172
11173 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11174 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11175 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11176 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11177
11178 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11179 " TLB1CFG " TARGET_FMT_lx "\n",
11180 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11181 env->spr[SPR_BOOKE_TLB1CFG]);
11182 break;
11183 default:
11184 break;
11185 }
11186 #endif
11187
11188 #undef RGPL
11189 #undef RFPL
11190 }
11191
11192 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11193 fprintf_function cpu_fprintf, int flags)
11194 {
11195 #if defined(DO_PPC_STATISTICS)
11196 PowerPCCPU *cpu = POWERPC_CPU(cs);
11197 opc_handler_t **t1, **t2, **t3, *handler;
11198 int op1, op2, op3;
11199
11200 t1 = cpu->env.opcodes;
11201 for (op1 = 0; op1 < 64; op1++) {
11202 handler = t1[op1];
11203 if (is_indirect_opcode(handler)) {
11204 t2 = ind_table(handler);
11205 for (op2 = 0; op2 < 32; op2++) {
11206 handler = t2[op2];
11207 if (is_indirect_opcode(handler)) {
11208 t3 = ind_table(handler);
11209 for (op3 = 0; op3 < 32; op3++) {
11210 handler = t3[op3];
11211 if (handler->count == 0)
11212 continue;
11213 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11214 "%016" PRIx64 " %" PRId64 "\n",
11215 op1, op2, op3, op1, (op3 << 5) | op2,
11216 handler->oname,
11217 handler->count, handler->count);
11218 }
11219 } else {
11220 if (handler->count == 0)
11221 continue;
11222 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11223 "%016" PRIx64 " %" PRId64 "\n",
11224 op1, op2, op1, op2, handler->oname,
11225 handler->count, handler->count);
11226 }
11227 }
11228 } else {
11229 if (handler->count == 0)
11230 continue;
11231 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11232 " %" PRId64 "\n",
11233 op1, op1, handler->oname,
11234 handler->count, handler->count);
11235 }
11236 }
11237 #endif
11238 }
11239
11240 /*****************************************************************************/
11241 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11242 TranslationBlock *tb,
11243 bool search_pc)
11244 {
11245 CPUState *cs = CPU(cpu);
11246 CPUPPCState *env = &cpu->env;
11247 DisasContext ctx, *ctxp = &ctx;
11248 opc_handler_t **table, *handler;
11249 target_ulong pc_start;
11250 uint16_t *gen_opc_end;
11251 CPUBreakpoint *bp;
11252 int j, lj = -1;
11253 int num_insns;
11254 int max_insns;
11255
11256 pc_start = tb->pc;
11257 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11258 ctx.nip = pc_start;
11259 ctx.tb = tb;
11260 ctx.exception = POWERPC_EXCP_NONE;
11261 ctx.spr_cb = env->spr_cb;
11262 ctx.mem_idx = env->mmu_idx;
11263 ctx.insns_flags = env->insns_flags;
11264 ctx.insns_flags2 = env->insns_flags2;
11265 ctx.access_type = -1;
11266 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11267 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11268 #if defined(TARGET_PPC64)
11269 ctx.sf_mode = msr_is_64bit(env, env->msr);
11270 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11271 #endif
11272 ctx.fpu_enabled = msr_fp;
11273 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11274 ctx.spe_enabled = msr_spe;
11275 else
11276 ctx.spe_enabled = 0;
11277 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11278 ctx.altivec_enabled = msr_vr;
11279 else
11280 ctx.altivec_enabled = 0;
11281 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11282 ctx.vsx_enabled = msr_vsx;
11283 } else {
11284 ctx.vsx_enabled = 0;
11285 }
11286 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11287 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11288 else
11289 ctx.singlestep_enabled = 0;
11290 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11291 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11292 if (unlikely(cs->singlestep_enabled)) {
11293 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11294 }
11295 #if defined (DO_SINGLE_STEP) && 0
11296 /* Single step trace mode */
11297 msr_se = 1;
11298 #endif
11299 num_insns = 0;
11300 max_insns = tb->cflags & CF_COUNT_MASK;
11301 if (max_insns == 0)
11302 max_insns = CF_COUNT_MASK;
11303
11304 gen_tb_start();
11305 tcg_clear_temp_count();
11306 /* Set env in case of segfault during code fetch */
11307 while (ctx.exception == POWERPC_EXCP_NONE
11308 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11309 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11310 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11311 if (bp->pc == ctx.nip) {
11312 gen_debug_exception(ctxp);
11313 break;
11314 }
11315 }
11316 }
11317 if (unlikely(search_pc)) {
11318 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11319 if (lj < j) {
11320 lj++;
11321 while (lj < j)
11322 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11323 }
11324 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11325 tcg_ctx.gen_opc_instr_start[lj] = 1;
11326 tcg_ctx.gen_opc_icount[lj] = num_insns;
11327 }
11328 LOG_DISAS("----------------\n");
11329 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11330 ctx.nip, ctx.mem_idx, (int)msr_ir);
11331 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11332 gen_io_start();
11333 if (unlikely(need_byteswap(&ctx))) {
11334 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11335 } else {
11336 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11337 }
11338 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11339 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11340 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11341 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11342 tcg_gen_debug_insn_start(ctx.nip);
11343 }
11344 ctx.nip += 4;
11345 table = env->opcodes;
11346 num_insns++;
11347 handler = table[opc1(ctx.opcode)];
11348 if (is_indirect_opcode(handler)) {
11349 table = ind_table(handler);
11350 handler = table[opc2(ctx.opcode)];
11351 if (is_indirect_opcode(handler)) {
11352 table = ind_table(handler);
11353 handler = table[opc3(ctx.opcode)];
11354 }
11355 }
11356 /* Is opcode *REALLY* valid ? */
11357 if (unlikely(handler->handler == &gen_invalid)) {
11358 if (qemu_log_enabled()) {
11359 qemu_log("invalid/unsupported opcode: "
11360 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11361 opc1(ctx.opcode), opc2(ctx.opcode),
11362 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11363 }
11364 } else {
11365 uint32_t inval;
11366
11367 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11368 inval = handler->inval2;
11369 } else {
11370 inval = handler->inval1;
11371 }
11372
11373 if (unlikely((ctx.opcode & inval) != 0)) {
11374 if (qemu_log_enabled()) {
11375 qemu_log("invalid bits: %08x for opcode: "
11376 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11377 ctx.opcode & inval, opc1(ctx.opcode),
11378 opc2(ctx.opcode), opc3(ctx.opcode),
11379 ctx.opcode, ctx.nip - 4);
11380 }
11381 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11382 break;
11383 }
11384 }
11385 (*(handler->handler))(&ctx);
11386 #if defined(DO_PPC_STATISTICS)
11387 handler->count++;
11388 #endif
11389 /* Check trace mode exceptions */
11390 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11391 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11392 ctx.exception != POWERPC_SYSCALL &&
11393 ctx.exception != POWERPC_EXCP_TRAP &&
11394 ctx.exception != POWERPC_EXCP_BRANCH)) {
11395 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11396 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11397 (cs->singlestep_enabled) ||
11398 singlestep ||
11399 num_insns >= max_insns)) {
11400 /* if we reach a page boundary or are single stepping, stop
11401 * generation
11402 */
11403 break;
11404 }
11405 if (tcg_check_temp_count()) {
11406 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11407 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11408 ctx.opcode);
11409 exit(1);
11410 }
11411 }
11412 if (tb->cflags & CF_LAST_IO)
11413 gen_io_end();
11414 if (ctx.exception == POWERPC_EXCP_NONE) {
11415 gen_goto_tb(&ctx, 0, ctx.nip);
11416 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11417 if (unlikely(cs->singlestep_enabled)) {
11418 gen_debug_exception(ctxp);
11419 }
11420 /* Generate the return instruction */
11421 tcg_gen_exit_tb(0);
11422 }
11423 gen_tb_end(tb, num_insns);
11424 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11425 if (unlikely(search_pc)) {
11426 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11427 lj++;
11428 while (lj <= j)
11429 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11430 } else {
11431 tb->size = ctx.nip - pc_start;
11432 tb->icount = num_insns;
11433 }
11434 #if defined(DEBUG_DISAS)
11435 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11436 int flags;
11437 flags = env->bfd_mach;
11438 flags |= ctx.le_mode << 16;
11439 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11440 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11441 qemu_log("\n");
11442 }
11443 #endif
11444 }
11445
11446 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11447 {
11448 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11449 }
11450
11451 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11452 {
11453 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11454 }
11455
11456 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11457 {
11458 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11459 }
AR7 emulation for QEMU