virtio-net: use the backend cross-endian capabilities
[qemu/ar7.git] / hw / pci-host / apb.c
blob75dee50bc34bedb7ed4f998bdcf43d77a2c465c6
1 /*
2 * QEMU Ultrasparc APB PCI host
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2012,2013 Artyom Tarasenko
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
26 /* XXX This file and most of its contents are somewhat misnamed. The
27 Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
28 the secondary PCI bridge. */
30 #include "qemu/osdep.h"
31 #include "hw/sysbus.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/pci/pci_bridge.h"
35 #include "hw/pci/pci_bus.h"
36 #include "hw/pci-host/apb.h"
37 #include "sysemu/sysemu.h"
38 #include "exec/address-spaces.h"
40 /* debug APB */
41 //#define DEBUG_APB
43 #ifdef DEBUG_APB
44 #define APB_DPRINTF(fmt, ...) \
45 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
46 #else
47 #define APB_DPRINTF(fmt, ...)
48 #endif
50 /* debug IOMMU */
51 //#define DEBUG_IOMMU
53 #ifdef DEBUG_IOMMU
54 #define IOMMU_DPRINTF(fmt, ...) \
55 do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
56 #else
57 #define IOMMU_DPRINTF(fmt, ...)
58 #endif
61 * Chipset docs:
62 * PBM: "UltraSPARC IIi User's Manual",
63 * http://www.sun.com/processors/manuals/805-0087.pdf
65 * APB: "Advanced PCI Bridge (APB) User's Manual",
66 * http://www.sun.com/processors/manuals/805-1251.pdf
69 #define PBM_PCI_IMR_MASK 0x7fffffff
70 #define PBM_PCI_IMR_ENABLED 0x80000000
72 #define POR (1U << 31)
73 #define SOFT_POR (1U << 30)
74 #define SOFT_XIR (1U << 29)
75 #define BTN_POR (1U << 28)
76 #define BTN_XIR (1U << 27)
77 #define RESET_MASK 0xf8000000
78 #define RESET_WCMASK 0x98000000
79 #define RESET_WMASK 0x60000000
81 #define MAX_IVEC 0x40
82 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
84 #define IOMMU_PAGE_SIZE_8K (1ULL << 13)
85 #define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
86 #define IOMMU_PAGE_SIZE_64K (1ULL << 16)
87 #define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
89 #define IOMMU_NREGS 3
91 #define IOMMU_CTRL 0x0
92 #define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
93 #define IOMMU_CTRL_MMU_EN (1ULL)
95 #define IOMMU_CTRL_TSB_SHIFT 16
97 #define IOMMU_BASE 0x8
98 #define IOMMU_FLUSH 0x10
100 #define IOMMU_TTE_DATA_V (1ULL << 63)
101 #define IOMMU_TTE_DATA_SIZE (1ULL << 61)
102 #define IOMMU_TTE_DATA_W (1ULL << 1)
104 #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
105 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
107 #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
108 #define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
109 #define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
110 #define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
111 #define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
112 #define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
113 #define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
114 #define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
116 #define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
117 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
118 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
119 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
120 #define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
121 #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
123 typedef struct IOMMUState {
124 AddressSpace iommu_as;
125 MemoryRegion iommu;
127 uint64_t regs[IOMMU_NREGS];
128 } IOMMUState;
130 #define TYPE_APB "pbm"
132 #define APB_DEVICE(obj) \
133 OBJECT_CHECK(APBState, (obj), TYPE_APB)
135 typedef struct APBState {
136 PCIHostState parent_obj;
138 MemoryRegion apb_config;
139 MemoryRegion pci_config;
140 MemoryRegion pci_mmio;
141 MemoryRegion pci_ioport;
142 uint64_t pci_irq_in;
143 IOMMUState iommu;
144 uint32_t pci_control[16];
145 uint32_t pci_irq_map[8];
146 uint32_t pci_err_irq_map[4];
147 uint32_t obio_irq_map[32];
148 qemu_irq *pbm_irqs;
149 qemu_irq *ivec_irqs;
150 unsigned int irq_request;
151 uint32_t reset_control;
152 unsigned int nr_resets;
153 } APBState;
155 static inline void pbm_set_request(APBState *s, unsigned int irq_num)
157 APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
159 s->irq_request = irq_num;
160 qemu_set_irq(s->ivec_irqs[irq_num], 1);
163 static inline void pbm_check_irqs(APBState *s)
166 unsigned int i;
168 /* Previous request is not acknowledged, resubmit */
169 if (s->irq_request != NO_IRQ_REQUEST) {
170 pbm_set_request(s, s->irq_request);
171 return;
173 /* no request pending */
174 if (s->pci_irq_in == 0ULL) {
175 return;
177 for (i = 0; i < 32; i++) {
178 if (s->pci_irq_in & (1ULL << i)) {
179 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
180 pbm_set_request(s, i);
181 return;
185 for (i = 32; i < 64; i++) {
186 if (s->pci_irq_in & (1ULL << i)) {
187 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
188 pbm_set_request(s, i);
189 break;
195 static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
197 APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
198 qemu_set_irq(s->ivec_irqs[irq_num], 0);
199 s->irq_request = NO_IRQ_REQUEST;
202 static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
204 IOMMUState *is = opaque;
206 return &is->iommu_as;
209 /* Called from RCU critical section */
210 static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr,
211 bool is_write)
213 IOMMUState *is = container_of(iommu, IOMMUState, iommu);
214 hwaddr baseaddr, offset;
215 uint64_t tte;
216 uint32_t tsbsize;
217 IOMMUTLBEntry ret = {
218 .target_as = &address_space_memory,
219 .iova = 0,
220 .translated_addr = 0,
221 .addr_mask = ~(hwaddr)0,
222 .perm = IOMMU_NONE,
225 if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
226 /* IOMMU disabled, passthrough using standard 8K page */
227 ret.iova = addr & IOMMU_PAGE_MASK_8K;
228 ret.translated_addr = addr;
229 ret.addr_mask = IOMMU_PAGE_MASK_8K;
230 ret.perm = IOMMU_RW;
232 return ret;
235 baseaddr = is->regs[IOMMU_BASE >> 3];
236 tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
238 if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
239 /* 64K */
240 switch (tsbsize) {
241 case 0:
242 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
243 break;
244 case 1:
245 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
246 break;
247 case 2:
248 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
249 break;
250 case 3:
251 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
252 break;
253 case 4:
254 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
255 break;
256 case 5:
257 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
258 break;
259 default:
260 /* Not implemented, error */
261 return ret;
263 } else {
264 /* 8K */
265 switch (tsbsize) {
266 case 0:
267 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
268 break;
269 case 1:
270 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
271 break;
272 case 2:
273 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
274 break;
275 case 3:
276 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
277 break;
278 case 4:
279 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
280 break;
281 case 5:
282 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
283 break;
284 case 6:
285 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
286 break;
287 case 7:
288 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
289 break;
293 tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
294 MEMTXATTRS_UNSPECIFIED, NULL);
296 if (!(tte & IOMMU_TTE_DATA_V)) {
297 /* Invalid mapping */
298 return ret;
301 if (tte & IOMMU_TTE_DATA_W) {
302 /* Writeable */
303 ret.perm = IOMMU_RW;
304 } else {
305 ret.perm = IOMMU_RO;
308 /* Extract phys */
309 if (tte & IOMMU_TTE_DATA_SIZE) {
310 /* 64K */
311 ret.iova = addr & IOMMU_PAGE_MASK_64K;
312 ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
313 ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
314 } else {
315 /* 8K */
316 ret.iova = addr & IOMMU_PAGE_MASK_8K;
317 ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
318 ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
321 return ret;
324 static MemoryRegionIOMMUOps pbm_iommu_ops = {
325 .translate = pbm_translate_iommu,
328 static void iommu_config_write(void *opaque, hwaddr addr,
329 uint64_t val, unsigned size)
331 IOMMUState *is = opaque;
333 IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
334 " size: %d\n", addr, val, size);
336 switch (addr) {
337 case IOMMU_CTRL:
338 if (size == 4) {
339 is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
340 is->regs[IOMMU_CTRL >> 3] |= val << 32;
341 } else {
342 is->regs[IOMMU_CTRL >> 3] = val;
344 break;
345 case IOMMU_CTRL + 0x4:
346 is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
347 is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
348 break;
349 case IOMMU_BASE:
350 if (size == 4) {
351 is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
352 is->regs[IOMMU_BASE >> 3] |= val << 32;
353 } else {
354 is->regs[IOMMU_BASE >> 3] = val;
356 break;
357 case IOMMU_BASE + 0x4:
358 is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
359 is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
360 break;
361 case IOMMU_FLUSH:
362 case IOMMU_FLUSH + 0x4:
363 break;
364 default:
365 qemu_log_mask(LOG_UNIMP,
366 "apb iommu: Unimplemented register write "
367 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
368 addr, size, val);
369 break;
373 static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
375 IOMMUState *is = opaque;
376 uint64_t val;
378 switch (addr) {
379 case IOMMU_CTRL:
380 if (size == 4) {
381 val = is->regs[IOMMU_CTRL >> 3] >> 32;
382 } else {
383 val = is->regs[IOMMU_CTRL >> 3];
385 break;
386 case IOMMU_CTRL + 0x4:
387 val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
388 break;
389 case IOMMU_BASE:
390 if (size == 4) {
391 val = is->regs[IOMMU_BASE >> 3] >> 32;
392 } else {
393 val = is->regs[IOMMU_BASE >> 3];
395 break;
396 case IOMMU_BASE + 0x4:
397 val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
398 break;
399 case IOMMU_FLUSH:
400 case IOMMU_FLUSH + 0x4:
401 val = 0;
402 break;
403 default:
404 qemu_log_mask(LOG_UNIMP,
405 "apb iommu: Unimplemented register read "
406 "reg 0x%" HWADDR_PRIx " size 0x%x\n",
407 addr, size);
408 val = 0;
409 break;
412 IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
413 " size: %d\n", addr, val, size);
415 return val;
418 static void apb_config_writel (void *opaque, hwaddr addr,
419 uint64_t val, unsigned size)
421 APBState *s = opaque;
422 IOMMUState *is = &s->iommu;
424 APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
426 switch (addr & 0xffff) {
427 case 0x30 ... 0x4f: /* DMA error registers */
428 /* XXX: not implemented yet */
429 break;
430 case 0x200 ... 0x217: /* IOMMU */
431 iommu_config_write(is, (addr & 0x1f), val, size);
432 break;
433 case 0xc00 ... 0xc3f: /* PCI interrupt control */
434 if (addr & 4) {
435 unsigned int ino = (addr & 0x3f) >> 3;
436 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
437 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
438 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
439 pbm_clear_request(s, ino);
441 pbm_check_irqs(s);
443 break;
444 case 0x1000 ... 0x107f: /* OBIO interrupt control */
445 if (addr & 4) {
446 unsigned int ino = ((addr & 0xff) >> 3);
447 s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
448 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
449 if ((s->irq_request == (ino | 0x20))
450 && !(val & ~PBM_PCI_IMR_MASK)) {
451 pbm_clear_request(s, ino | 0x20);
453 pbm_check_irqs(s);
455 break;
456 case 0x1400 ... 0x14ff: /* PCI interrupt clear */
457 if (addr & 4) {
458 unsigned int ino = (addr & 0xff) >> 5;
459 if ((s->irq_request / 4) == ino) {
460 pbm_clear_request(s, s->irq_request);
461 pbm_check_irqs(s);
464 break;
465 case 0x1800 ... 0x1860: /* OBIO interrupt clear */
466 if (addr & 4) {
467 unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
468 if (s->irq_request == ino) {
469 pbm_clear_request(s, ino);
470 pbm_check_irqs(s);
473 break;
474 case 0x2000 ... 0x202f: /* PCI control */
475 s->pci_control[(addr & 0x3f) >> 2] = val;
476 break;
477 case 0xf020 ... 0xf027: /* Reset control */
478 if (addr & 4) {
479 val &= RESET_MASK;
480 s->reset_control &= ~(val & RESET_WCMASK);
481 s->reset_control |= val & RESET_WMASK;
482 if (val & SOFT_POR) {
483 s->nr_resets = 0;
484 qemu_system_reset_request();
485 } else if (val & SOFT_XIR) {
486 qemu_system_reset_request();
489 break;
490 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
491 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
492 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
493 case 0xf000 ... 0xf01f: /* FFB config, memory control */
494 /* we don't care */
495 default:
496 break;
500 static uint64_t apb_config_readl (void *opaque,
501 hwaddr addr, unsigned size)
503 APBState *s = opaque;
504 IOMMUState *is = &s->iommu;
505 uint32_t val;
507 switch (addr & 0xffff) {
508 case 0x30 ... 0x4f: /* DMA error registers */
509 val = 0;
510 /* XXX: not implemented yet */
511 break;
512 case 0x200 ... 0x217: /* IOMMU */
513 val = iommu_config_read(is, (addr & 0x1f), size);
514 break;
515 case 0xc00 ... 0xc3f: /* PCI interrupt control */
516 if (addr & 4) {
517 val = s->pci_irq_map[(addr & 0x3f) >> 3];
518 } else {
519 val = 0;
521 break;
522 case 0x1000 ... 0x107f: /* OBIO interrupt control */
523 if (addr & 4) {
524 val = s->obio_irq_map[(addr & 0xff) >> 3];
525 } else {
526 val = 0;
528 break;
529 case 0x1080 ... 0x108f: /* PCI bus error */
530 if (addr & 4) {
531 val = s->pci_err_irq_map[(addr & 0xf) >> 3];
532 } else {
533 val = 0;
535 break;
536 case 0x2000 ... 0x202f: /* PCI control */
537 val = s->pci_control[(addr & 0x3f) >> 2];
538 break;
539 case 0xf020 ... 0xf027: /* Reset control */
540 if (addr & 4) {
541 val = s->reset_control;
542 } else {
543 val = 0;
545 break;
546 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
547 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
548 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
549 case 0xf000 ... 0xf01f: /* FFB config, memory control */
550 /* we don't care */
551 default:
552 val = 0;
553 break;
555 APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
557 return val;
560 static const MemoryRegionOps apb_config_ops = {
561 .read = apb_config_readl,
562 .write = apb_config_writel,
563 .endianness = DEVICE_NATIVE_ENDIAN,
566 static void apb_pci_config_write(void *opaque, hwaddr addr,
567 uint64_t val, unsigned size)
569 APBState *s = opaque;
570 PCIHostState *phb = PCI_HOST_BRIDGE(s);
572 val = qemu_bswap_len(val, size);
573 APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
574 pci_data_write(phb->bus, addr, val, size);
577 static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
578 unsigned size)
580 uint32_t ret;
581 APBState *s = opaque;
582 PCIHostState *phb = PCI_HOST_BRIDGE(s);
584 ret = pci_data_read(phb->bus, addr, size);
585 ret = qemu_bswap_len(ret, size);
586 APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
587 return ret;
590 /* The APB host has an IRQ line for each IRQ line of each slot. */
591 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
593 return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
596 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
598 int bus_offset;
599 if (pci_dev->devfn & 1)
600 bus_offset = 16;
601 else
602 bus_offset = 0;
603 return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
606 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
608 APBState *s = opaque;
610 APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
611 /* PCI IRQ map onto the first 32 INO. */
612 if (irq_num < 32) {
613 if (level) {
614 s->pci_irq_in |= 1ULL << irq_num;
615 if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
616 pbm_set_request(s, irq_num);
618 } else {
619 s->pci_irq_in &= ~(1ULL << irq_num);
621 } else {
622 /* OBIO IRQ map onto the next 32 INO. */
623 if (level) {
624 APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
625 s->pci_irq_in |= 1ULL << irq_num;
626 if ((s->irq_request == NO_IRQ_REQUEST)
627 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
628 pbm_set_request(s, irq_num);
630 } else {
631 s->pci_irq_in &= ~(1ULL << irq_num);
636 static int apb_pci_bridge_initfn(PCIDevice *dev)
638 int rc;
640 rc = pci_bridge_initfn(dev, TYPE_PCI_BUS);
641 if (rc < 0) {
642 return rc;
646 * command register:
647 * According to PCI bridge spec, after reset
648 * bus master bit is off
649 * memory space enable bit is off
650 * According to manual (805-1251.pdf).
651 * the reset value should be zero unless the boot pin is tied high
652 * (which is true) and thus it should be PCI_COMMAND_MEMORY.
654 pci_set_word(dev->config + PCI_COMMAND,
655 PCI_COMMAND_MEMORY);
656 pci_set_word(dev->config + PCI_STATUS,
657 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
658 PCI_STATUS_DEVSEL_MEDIUM);
659 return 0;
662 PCIBus *pci_apb_init(hwaddr special_base,
663 hwaddr mem_base,
664 qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
665 qemu_irq **pbm_irqs)
667 DeviceState *dev;
668 SysBusDevice *s;
669 PCIHostState *phb;
670 APBState *d;
671 IOMMUState *is;
672 PCIDevice *pci_dev;
673 PCIBridge *br;
675 /* Ultrasparc PBM main bus */
676 dev = qdev_create(NULL, TYPE_APB);
677 qdev_init_nofail(dev);
678 s = SYS_BUS_DEVICE(dev);
679 /* apb_config */
680 sysbus_mmio_map(s, 0, special_base);
681 /* PCI configuration space */
682 sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
683 /* pci_ioport */
684 sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
685 d = APB_DEVICE(dev);
687 memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
688 memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
690 phb = PCI_HOST_BRIDGE(dev);
691 phb->bus = pci_register_bus(DEVICE(phb), "pci",
692 pci_apb_set_irq, pci_pbm_map_irq, d,
693 &d->pci_mmio,
694 get_system_io(),
695 0, 32, TYPE_PCI_BUS);
697 *pbm_irqs = d->pbm_irqs;
698 d->ivec_irqs = ivec_irqs;
700 pci_create_simple(phb->bus, 0, "pbm-pci");
702 /* APB IOMMU */
703 is = &d->iommu;
704 memset(is, 0, sizeof(IOMMUState));
706 memory_region_init_iommu(&is->iommu, OBJECT(dev), &pbm_iommu_ops,
707 "iommu-apb", UINT64_MAX);
708 address_space_init(&is->iommu_as, &is->iommu, "pbm-as");
709 pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
711 /* APB secondary busses */
712 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
713 "pbm-bridge");
714 br = PCI_BRIDGE(pci_dev);
715 pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
716 pci_apb_map_irq);
717 qdev_init_nofail(&pci_dev->qdev);
718 *bus2 = pci_bridge_get_sec_bus(br);
720 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
721 "pbm-bridge");
722 br = PCI_BRIDGE(pci_dev);
723 pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
724 pci_apb_map_irq);
725 qdev_init_nofail(&pci_dev->qdev);
726 *bus3 = pci_bridge_get_sec_bus(br);
728 return phb->bus;
731 static void pci_pbm_reset(DeviceState *d)
733 unsigned int i;
734 APBState *s = APB_DEVICE(d);
736 for (i = 0; i < 8; i++) {
737 s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
739 for (i = 0; i < 32; i++) {
740 s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
743 s->irq_request = NO_IRQ_REQUEST;
744 s->pci_irq_in = 0ULL;
746 if (s->nr_resets++ == 0) {
747 /* Power on reset */
748 s->reset_control = POR;
752 static const MemoryRegionOps pci_config_ops = {
753 .read = apb_pci_config_read,
754 .write = apb_pci_config_write,
755 .endianness = DEVICE_NATIVE_ENDIAN,
758 static int pci_pbm_init_device(SysBusDevice *dev)
760 APBState *s;
761 unsigned int i;
763 s = APB_DEVICE(dev);
764 for (i = 0; i < 8; i++) {
765 s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
767 for (i = 0; i < 2; i++) {
768 s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
770 for (i = 0; i < 32; i++) {
771 s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
773 s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
774 s->irq_request = NO_IRQ_REQUEST;
775 s->pci_irq_in = 0ULL;
777 /* apb_config */
778 memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
779 "apb-config", 0x10000);
780 /* at region 0 */
781 sysbus_init_mmio(dev, &s->apb_config);
783 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
784 "apb-pci-config", 0x1000000);
785 /* at region 1 */
786 sysbus_init_mmio(dev, &s->pci_config);
788 /* pci_ioport */
789 memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
790 get_system_io(), 0, 0x10000);
791 /* at region 2 */
792 sysbus_init_mmio(dev, &s->pci_ioport);
794 return 0;
797 static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
799 pci_set_word(d->config + PCI_COMMAND,
800 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
801 pci_set_word(d->config + PCI_STATUS,
802 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
803 PCI_STATUS_DEVSEL_MEDIUM);
806 static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
808 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
809 DeviceClass *dc = DEVICE_CLASS(klass);
811 k->realize = pbm_pci_host_realize;
812 k->vendor_id = PCI_VENDOR_ID_SUN;
813 k->device_id = PCI_DEVICE_ID_SUN_SABRE;
814 k->class_id = PCI_CLASS_BRIDGE_HOST;
816 * PCI-facing part of the host bridge, not usable without the
817 * host-facing part, which can't be device_add'ed, yet.
819 dc->cannot_instantiate_with_device_add_yet = true;
822 static const TypeInfo pbm_pci_host_info = {
823 .name = "pbm-pci",
824 .parent = TYPE_PCI_DEVICE,
825 .instance_size = sizeof(PCIDevice),
826 .class_init = pbm_pci_host_class_init,
829 static void pbm_host_class_init(ObjectClass *klass, void *data)
831 DeviceClass *dc = DEVICE_CLASS(klass);
832 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
834 k->init = pci_pbm_init_device;
835 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
836 dc->reset = pci_pbm_reset;
839 static const TypeInfo pbm_host_info = {
840 .name = TYPE_APB,
841 .parent = TYPE_PCI_HOST_BRIDGE,
842 .instance_size = sizeof(APBState),
843 .class_init = pbm_host_class_init,
846 static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
848 DeviceClass *dc = DEVICE_CLASS(klass);
849 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
851 k->init = apb_pci_bridge_initfn;
852 k->exit = pci_bridge_exitfn;
853 k->vendor_id = PCI_VENDOR_ID_SUN;
854 k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
855 k->revision = 0x11;
856 k->config_write = pci_bridge_write_config;
857 k->is_bridge = 1;
858 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
859 dc->reset = pci_bridge_reset;
860 dc->vmsd = &vmstate_pci_device;
863 static const TypeInfo pbm_pci_bridge_info = {
864 .name = "pbm-bridge",
865 .parent = TYPE_PCI_BRIDGE,
866 .class_init = pbm_pci_bridge_class_init,
869 static void pbm_register_types(void)
871 type_register_static(&pbm_host_info);
872 type_register_static(&pbm_pci_host_info);
873 type_register_static(&pbm_pci_bridge_info);
876 type_init(pbm_register_types)