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docs/system: Convert qemu-cpu-models.texi to rST
[qemu/ar7.git] / target / arm / cpu.c
blob3623ecefbd9c2bb2755b759e4c40389a6e2f295b
1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
28 #include "cpu.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
35 #endif
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
39 #include "kvm_arm.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
42
43 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
44 {
45 ARMCPU *cpu = ARM_CPU(cs);
46 CPUARMState *env = &cpu->env;
47
48 if (is_a64(env)) {
49 env->pc = value;
50 env->thumb = 0;
51 } else {
52 env->regs[15] = value & ~1;
53 env->thumb = value & 1;
54 }
55 }
56
57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
58 {
59 ARMCPU *cpu = ARM_CPU(cs);
60 CPUARMState *env = &cpu->env;
61
62 /*
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
65 */
66 if (is_a64(env)) {
67 env->pc = tb->pc;
68 } else {
69 env->regs[15] = tb->pc;
70 }
71 }
72
73 static bool arm_cpu_has_work(CPUState *cs)
74 {
75 ARMCPU *cpu = ARM_CPU(cs);
76
77 return (cpu->power_state != PSCI_OFF)
78 && cs->interrupt_request &
79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB);
82 }
83
84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
85 void *opaque)
86 {
87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
88
89 entry->hook = hook;
90 entry->opaque = opaque;
91
92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
93 }
94
95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
96 void *opaque)
97 {
98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
99
100 entry->hook = hook;
101 entry->opaque = opaque;
102
103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
104 }
105
106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
107 {
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo *ri = value;
110 ARMCPU *cpu = opaque;
111
112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
113 return;
114 }
115
116 if (ri->resetfn) {
117 ri->resetfn(&cpu->env, ri);
118 return;
119 }
120
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
125 */
126 if (!ri->fieldoffset) {
127 return;
128 }
129
130 if (cpreg_field_is_64bit(ri)) {
131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
132 } else {
133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
134 }
135 }
136
137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
138 {
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
143 */
144 ARMCPRegInfo *ri = value;
145 ARMCPU *cpu = opaque;
146 uint64_t oldvalue, newvalue;
147
148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
149 return;
150 }
151
152 oldvalue = read_raw_cp_reg(&cpu->env, ri);
153 cp_reg_reset(key, value, opaque);
154 newvalue = read_raw_cp_reg(&cpu->env, ri);
155 assert(oldvalue == newvalue);
156 }
157
158 /* CPUClass::reset() */
159 static void arm_cpu_reset(CPUState *s)
160 {
161 ARMCPU *cpu = ARM_CPU(s);
162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
163 CPUARMState *env = &cpu->env;
164
165 acc->parent_reset(s);
166
167 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
168
169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
171
172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
176
177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
178 s->halted = cpu->start_powered_off;
179
180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
182 }
183
184 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
185 /* 64 bit CPUs always start in 64 bit mode */
186 env->aarch64 = 1;
187 #if defined(CONFIG_USER_ONLY)
188 env->pstate = PSTATE_MODE_EL0t;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
191 /* Enable all PAC keys. */
192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
193 SCTLR_EnDA | SCTLR_EnDB);
194 /* and to the FP/Neon instructions */
195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
196 /* and to the SVE instructions */
197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
198 /* with maximum vector length */
199 env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
200 cpu->sve_max_vq - 1 : 0;
201 /*
202 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
203 * turning on both here will produce smaller code and otherwise
204 * make no difference to the user-level emulation.
205 */
206 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
207 #else
208 /* Reset into the highest available EL */
209 if (arm_feature(env, ARM_FEATURE_EL3)) {
210 env->pstate = PSTATE_MODE_EL3h;
211 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
212 env->pstate = PSTATE_MODE_EL2h;
213 } else {
214 env->pstate = PSTATE_MODE_EL1h;
215 }
216 env->pc = cpu->rvbar;
217 #endif
218 } else {
219 #if defined(CONFIG_USER_ONLY)
220 /* Userspace expects access to cp10 and cp11 for FP/Neon */
221 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
222 #endif
223 }
224
225 #if defined(CONFIG_USER_ONLY)
226 env->uncached_cpsr = ARM_CPU_MODE_USR;
227 /* For user mode we must enable access to coprocessors */
228 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
229 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
230 env->cp15.c15_cpar = 3;
231 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
232 env->cp15.c15_cpar = 1;
233 }
234 #else
235
236 /*
237 * If the highest available EL is EL2, AArch32 will start in Hyp
238 * mode; otherwise it starts in SVC. Note that if we start in
239 * AArch64 then these values in the uncached_cpsr will be ignored.
240 */
241 if (arm_feature(env, ARM_FEATURE_EL2) &&
242 !arm_feature(env, ARM_FEATURE_EL3)) {
243 env->uncached_cpsr = ARM_CPU_MODE_HYP;
244 } else {
245 env->uncached_cpsr = ARM_CPU_MODE_SVC;
246 }
247 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
248
249 if (arm_feature(env, ARM_FEATURE_M)) {
250 uint32_t initial_msp; /* Loaded from 0x0 */
251 uint32_t initial_pc; /* Loaded from 0x4 */
252 uint8_t *rom;
253 uint32_t vecbase;
254
255 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
256 env->v7m.secure = true;
257 } else {
258 /* This bit resets to 0 if security is supported, but 1 if
259 * it is not. The bit is not present in v7M, but we set it
260 * here so we can avoid having to make checks on it conditional
261 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
262 */
263 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
264 /*
265 * Set NSACR to indicate "NS access permitted to everything";
266 * this avoids having to have all the tests of it being
267 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
268 * v8.1M the guest-visible value of NSACR in a CPU without the
269 * Security Extension is 0xcff.
270 */
271 env->v7m.nsacr = 0xcff;
272 }
273
274 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
275 * that it resets to 1, so QEMU always does that rather than making
276 * it dependent on CPU model. In v8M it is RES1.
277 */
278 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
279 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
280 if (arm_feature(env, ARM_FEATURE_V8)) {
281 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
282 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
283 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
284 }
285 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
286 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
287 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
288 }
289
290 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
291 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
292 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
293 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
294 }
295 /* Unlike A/R profile, M profile defines the reset LR value */
296 env->regs[14] = 0xffffffff;
297
298 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
299
300 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
301 vecbase = env->v7m.vecbase[env->v7m.secure];
302 rom = rom_ptr(vecbase, 8);
303 if (rom) {
304 /* Address zero is covered by ROM which hasn't yet been
305 * copied into physical memory.
306 */
307 initial_msp = ldl_p(rom);
308 initial_pc = ldl_p(rom + 4);
309 } else {
310 /* Address zero not covered by a ROM blob, or the ROM blob
311 * is in non-modifiable memory and this is a second reset after
312 * it got copied into memory. In the latter case, rom_ptr
313 * will return a NULL pointer and we should use ldl_phys instead.
314 */
315 initial_msp = ldl_phys(s->as, vecbase);
316 initial_pc = ldl_phys(s->as, vecbase + 4);
317 }
318
319 env->regs[13] = initial_msp & 0xFFFFFFFC;
320 env->regs[15] = initial_pc & ~1;
321 env->thumb = initial_pc & 1;
322 }
323
324 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
325 * executing as AArch32 then check if highvecs are enabled and
326 * adjust the PC accordingly.
327 */
328 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
329 env->regs[15] = 0xFFFF0000;
330 }
331
332 /* M profile requires that reset clears the exclusive monitor;
333 * A profile does not, but clearing it makes more sense than having it
334 * set with an exclusive access on address zero.
335 */
336 arm_clear_exclusive(env);
337
338 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
339 #endif
340
341 if (arm_feature(env, ARM_FEATURE_PMSA)) {
342 if (cpu->pmsav7_dregion > 0) {
343 if (arm_feature(env, ARM_FEATURE_V8)) {
344 memset(env->pmsav8.rbar[M_REG_NS], 0,
345 sizeof(*env->pmsav8.rbar[M_REG_NS])
346 * cpu->pmsav7_dregion);
347 memset(env->pmsav8.rlar[M_REG_NS], 0,
348 sizeof(*env->pmsav8.rlar[M_REG_NS])
349 * cpu->pmsav7_dregion);
350 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
351 memset(env->pmsav8.rbar[M_REG_S], 0,
352 sizeof(*env->pmsav8.rbar[M_REG_S])
353 * cpu->pmsav7_dregion);
354 memset(env->pmsav8.rlar[M_REG_S], 0,
355 sizeof(*env->pmsav8.rlar[M_REG_S])
356 * cpu->pmsav7_dregion);
357 }
358 } else if (arm_feature(env, ARM_FEATURE_V7)) {
359 memset(env->pmsav7.drbar, 0,
360 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
361 memset(env->pmsav7.drsr, 0,
362 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
363 memset(env->pmsav7.dracr, 0,
364 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
365 }
366 }
367 env->pmsav7.rnr[M_REG_NS] = 0;
368 env->pmsav7.rnr[M_REG_S] = 0;
369 env->pmsav8.mair0[M_REG_NS] = 0;
370 env->pmsav8.mair0[M_REG_S] = 0;
371 env->pmsav8.mair1[M_REG_NS] = 0;
372 env->pmsav8.mair1[M_REG_S] = 0;
373 }
374
375 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
376 if (cpu->sau_sregion > 0) {
377 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
378 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
379 }
380 env->sau.rnr = 0;
381 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
382 * the Cortex-M33 does.
383 */
384 env->sau.ctrl = 0;
385 }
386
387 set_flush_to_zero(1, &env->vfp.standard_fp_status);
388 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
389 set_default_nan_mode(1, &env->vfp.standard_fp_status);
390 set_float_detect_tininess(float_tininess_before_rounding,
391 &env->vfp.fp_status);
392 set_float_detect_tininess(float_tininess_before_rounding,
393 &env->vfp.standard_fp_status);
394 set_float_detect_tininess(float_tininess_before_rounding,
395 &env->vfp.fp_status_f16);
396 #ifndef CONFIG_USER_ONLY
397 if (kvm_enabled()) {
398 kvm_arm_reset_vcpu(cpu);
399 }
400 #endif
401
402 hw_breakpoint_update_all(cpu);
403 hw_watchpoint_update_all(cpu);
404 arm_rebuild_hflags(env);
405 }
406
407 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
408 unsigned int target_el,
409 unsigned int cur_el, bool secure,
410 uint64_t hcr_el2)
411 {
412 CPUARMState *env = cs->env_ptr;
413 bool pstate_unmasked;
414 bool unmasked = false;
415
416 /*
417 * Don't take exceptions if they target a lower EL.
418 * This check should catch any exceptions that would not be taken
419 * but left pending.
420 */
421 if (cur_el > target_el) {
422 return false;
423 }
424
425 switch (excp_idx) {
426 case EXCP_FIQ:
427 pstate_unmasked = !(env->daif & PSTATE_F);
428 break;
429
430 case EXCP_IRQ:
431 pstate_unmasked = !(env->daif & PSTATE_I);
432 break;
433
434 case EXCP_VFIQ:
435 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
436 /* VFIQs are only taken when hypervized and non-secure. */
437 return false;
438 }
439 return !(env->daif & PSTATE_F);
440 case EXCP_VIRQ:
441 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
442 /* VIRQs are only taken when hypervized and non-secure. */
443 return false;
444 }
445 return !(env->daif & PSTATE_I);
446 default:
447 g_assert_not_reached();
448 }
449
450 /*
451 * Use the target EL, current execution state and SCR/HCR settings to
452 * determine whether the corresponding CPSR bit is used to mask the
453 * interrupt.
454 */
455 if ((target_el > cur_el) && (target_el != 1)) {
456 /* Exceptions targeting a higher EL may not be maskable */
457 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
458 /*
459 * 64-bit masking rules are simple: exceptions to EL3
460 * can't be masked, and exceptions to EL2 can only be
461 * masked from Secure state. The HCR and SCR settings
462 * don't affect the masking logic, only the interrupt routing.
463 */
464 if (target_el == 3 || !secure) {
465 unmasked = true;
466 }
467 } else {
468 /*
469 * The old 32-bit-only environment has a more complicated
470 * masking setup. HCR and SCR bits not only affect interrupt
471 * routing but also change the behaviour of masking.
472 */
473 bool hcr, scr;
474
475 switch (excp_idx) {
476 case EXCP_FIQ:
477 /*
478 * If FIQs are routed to EL3 or EL2 then there are cases where
479 * we override the CPSR.F in determining if the exception is
480 * masked or not. If neither of these are set then we fall back
481 * to the CPSR.F setting otherwise we further assess the state
482 * below.
483 */
484 hcr = hcr_el2 & HCR_FMO;
485 scr = (env->cp15.scr_el3 & SCR_FIQ);
486
487 /*
488 * When EL3 is 32-bit, the SCR.FW bit controls whether the
489 * CPSR.F bit masks FIQ interrupts when taken in non-secure
490 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
491 * when non-secure but only when FIQs are only routed to EL3.
492 */
493 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
494 break;
495 case EXCP_IRQ:
496 /*
497 * When EL3 execution state is 32-bit, if HCR.IMO is set then
498 * we may override the CPSR.I masking when in non-secure state.
499 * The SCR.IRQ setting has already been taken into consideration
500 * when setting the target EL, so it does not have a further
501 * affect here.
502 */
503 hcr = hcr_el2 & HCR_IMO;
504 scr = false;
505 break;
506 default:
507 g_assert_not_reached();
508 }
509
510 if ((scr || hcr) && !secure) {
511 unmasked = true;
512 }
513 }
514 }
515
516 /*
517 * The PSTATE bits only mask the interrupt if we have not overriden the
518 * ability above.
519 */
520 return unmasked || pstate_unmasked;
521 }
522
523 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
524 {
525 CPUClass *cc = CPU_GET_CLASS(cs);
526 CPUARMState *env = cs->env_ptr;
527 uint32_t cur_el = arm_current_el(env);
528 bool secure = arm_is_secure(env);
529 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
530 uint32_t target_el;
531 uint32_t excp_idx;
532
533 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
534
535 if (interrupt_request & CPU_INTERRUPT_FIQ) {
536 excp_idx = EXCP_FIQ;
537 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
538 if (arm_excp_unmasked(cs, excp_idx, target_el,
539 cur_el, secure, hcr_el2)) {
540 goto found;
541 }
542 }
543 if (interrupt_request & CPU_INTERRUPT_HARD) {
544 excp_idx = EXCP_IRQ;
545 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
546 if (arm_excp_unmasked(cs, excp_idx, target_el,
547 cur_el, secure, hcr_el2)) {
548 goto found;
549 }
550 }
551 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
552 excp_idx = EXCP_VIRQ;
553 target_el = 1;
554 if (arm_excp_unmasked(cs, excp_idx, target_el,
555 cur_el, secure, hcr_el2)) {
556 goto found;
557 }
558 }
559 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
560 excp_idx = EXCP_VFIQ;
561 target_el = 1;
562 if (arm_excp_unmasked(cs, excp_idx, target_el,
563 cur_el, secure, hcr_el2)) {
564 goto found;
565 }
566 }
567 return false;
568
569 found:
570 cs->exception_index = excp_idx;
571 env->exception.target_el = target_el;
572 cc->do_interrupt(cs);
573 return true;
574 }
575
576 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
577 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
578 {
579 CPUClass *cc = CPU_GET_CLASS(cs);
580 ARMCPU *cpu = ARM_CPU(cs);
581 CPUARMState *env = &cpu->env;
582 bool ret = false;
583
584 /* ARMv7-M interrupt masking works differently than -A or -R.
585 * There is no FIQ/IRQ distinction. Instead of I and F bits
586 * masking FIQ and IRQ interrupts, an exception is taken only
587 * if it is higher priority than the current execution priority
588 * (which depends on state like BASEPRI, FAULTMASK and the
589 * currently active exception).
590 */
591 if (interrupt_request & CPU_INTERRUPT_HARD
592 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
593 cs->exception_index = EXCP_IRQ;
594 cc->do_interrupt(cs);
595 ret = true;
596 }
597 return ret;
598 }
599 #endif
600
601 void arm_cpu_update_virq(ARMCPU *cpu)
602 {
603 /*
604 * Update the interrupt level for VIRQ, which is the logical OR of
605 * the HCR_EL2.VI bit and the input line level from the GIC.
606 */
607 CPUARMState *env = &cpu->env;
608 CPUState *cs = CPU(cpu);
609
610 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
611 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
612
613 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
614 if (new_state) {
615 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
616 } else {
617 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
618 }
619 }
620 }
621
622 void arm_cpu_update_vfiq(ARMCPU *cpu)
623 {
624 /*
625 * Update the interrupt level for VFIQ, which is the logical OR of
626 * the HCR_EL2.VF bit and the input line level from the GIC.
627 */
628 CPUARMState *env = &cpu->env;
629 CPUState *cs = CPU(cpu);
630
631 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
632 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
633
634 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
635 if (new_state) {
636 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
637 } else {
638 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
639 }
640 }
641 }
642
643 #ifndef CONFIG_USER_ONLY
644 static void arm_cpu_set_irq(void *opaque, int irq, int level)
645 {
646 ARMCPU *cpu = opaque;
647 CPUARMState *env = &cpu->env;
648 CPUState *cs = CPU(cpu);
649 static const int mask[] = {
650 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
651 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
652 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
653 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
654 };
655
656 if (level) {
657 env->irq_line_state |= mask[irq];
658 } else {
659 env->irq_line_state &= ~mask[irq];
660 }
661
662 switch (irq) {
663 case ARM_CPU_VIRQ:
664 assert(arm_feature(env, ARM_FEATURE_EL2));
665 arm_cpu_update_virq(cpu);
666 break;
667 case ARM_CPU_VFIQ:
668 assert(arm_feature(env, ARM_FEATURE_EL2));
669 arm_cpu_update_vfiq(cpu);
670 break;
671 case ARM_CPU_IRQ:
672 case ARM_CPU_FIQ:
673 if (level) {
674 cpu_interrupt(cs, mask[irq]);
675 } else {
676 cpu_reset_interrupt(cs, mask[irq]);
677 }
678 break;
679 default:
680 g_assert_not_reached();
681 }
682 }
683
684 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
685 {
686 #ifdef CONFIG_KVM
687 ARMCPU *cpu = opaque;
688 CPUARMState *env = &cpu->env;
689 CPUState *cs = CPU(cpu);
690 uint32_t linestate_bit;
691 int irq_id;
692
693 switch (irq) {
694 case ARM_CPU_IRQ:
695 irq_id = KVM_ARM_IRQ_CPU_IRQ;
696 linestate_bit = CPU_INTERRUPT_HARD;
697 break;
698 case ARM_CPU_FIQ:
699 irq_id = KVM_ARM_IRQ_CPU_FIQ;
700 linestate_bit = CPU_INTERRUPT_FIQ;
701 break;
702 default:
703 g_assert_not_reached();
704 }
705
706 if (level) {
707 env->irq_line_state |= linestate_bit;
708 } else {
709 env->irq_line_state &= ~linestate_bit;
710 }
711 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
712 #endif
713 }
714
715 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
716 {
717 ARMCPU *cpu = ARM_CPU(cs);
718 CPUARMState *env = &cpu->env;
719
720 cpu_synchronize_state(cs);
721 return arm_cpu_data_is_big_endian(env);
722 }
723
724 #endif
725
726 static inline void set_feature(CPUARMState *env, int feature)
727 {
728 env->features |= 1ULL << feature;
729 }
730
731 static inline void unset_feature(CPUARMState *env, int feature)
732 {
733 env->features &= ~(1ULL << feature);
734 }
735
736 static int
737 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
738 {
739 return print_insn_arm(pc | 1, info);
740 }
741
742 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
743 {
744 ARMCPU *ac = ARM_CPU(cpu);
745 CPUARMState *env = &ac->env;
746 bool sctlr_b;
747
748 if (is_a64(env)) {
749 /* We might not be compiled with the A64 disassembler
750 * because it needs a C++ compiler. Leave print_insn
751 * unset in this case to use the caller default behaviour.
752 */
753 #if defined(CONFIG_ARM_A64_DIS)
754 info->print_insn = print_insn_arm_a64;
755 #endif
756 info->cap_arch = CS_ARCH_ARM64;
757 info->cap_insn_unit = 4;
758 info->cap_insn_split = 4;
759 } else {
760 int cap_mode;
761 if (env->thumb) {
762 info->print_insn = print_insn_thumb1;
763 info->cap_insn_unit = 2;
764 info->cap_insn_split = 4;
765 cap_mode = CS_MODE_THUMB;
766 } else {
767 info->print_insn = print_insn_arm;
768 info->cap_insn_unit = 4;
769 info->cap_insn_split = 4;
770 cap_mode = CS_MODE_ARM;
771 }
772 if (arm_feature(env, ARM_FEATURE_V8)) {
773 cap_mode |= CS_MODE_V8;
774 }
775 if (arm_feature(env, ARM_FEATURE_M)) {
776 cap_mode |= CS_MODE_MCLASS;
777 }
778 info->cap_arch = CS_ARCH_ARM;
779 info->cap_mode = cap_mode;
780 }
781
782 sctlr_b = arm_sctlr_b(env);
783 if (bswap_code(sctlr_b)) {
784 #ifdef TARGET_WORDS_BIGENDIAN
785 info->endian = BFD_ENDIAN_LITTLE;
786 #else
787 info->endian = BFD_ENDIAN_BIG;
788 #endif
789 }
790 info->flags &= ~INSN_ARM_BE32;
791 #ifndef CONFIG_USER_ONLY
792 if (sctlr_b) {
793 info->flags |= INSN_ARM_BE32;
794 }
795 #endif
796 }
797
798 #ifdef TARGET_AARCH64
799
800 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
801 {
802 ARMCPU *cpu = ARM_CPU(cs);
803 CPUARMState *env = &cpu->env;
804 uint32_t psr = pstate_read(env);
805 int i;
806 int el = arm_current_el(env);
807 const char *ns_status;
808
809 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
810 for (i = 0; i < 32; i++) {
811 if (i == 31) {
812 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
813 } else {
814 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
815 (i + 2) % 3 ? " " : "\n");
816 }
817 }
818
819 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
820 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
821 } else {
822 ns_status = "";
823 }
824 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
825 psr,
826 psr & PSTATE_N ? 'N' : '-',
827 psr & PSTATE_Z ? 'Z' : '-',
828 psr & PSTATE_C ? 'C' : '-',
829 psr & PSTATE_V ? 'V' : '-',
830 ns_status,
831 el,
832 psr & PSTATE_SP ? 'h' : 't');
833
834 if (cpu_isar_feature(aa64_bti, cpu)) {
835 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
836 }
837 if (!(flags & CPU_DUMP_FPU)) {
838 qemu_fprintf(f, "\n");
839 return;
840 }
841 if (fp_exception_el(env, el) != 0) {
842 qemu_fprintf(f, " FPU disabled\n");
843 return;
844 }
845 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
846 vfp_get_fpcr(env), vfp_get_fpsr(env));
847
848 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
849 int j, zcr_len = sve_zcr_len_for_el(env, el);
850
851 for (i = 0; i <= FFR_PRED_NUM; i++) {
852 bool eol;
853 if (i == FFR_PRED_NUM) {
854 qemu_fprintf(f, "FFR=");
855 /* It's last, so end the line. */
856 eol = true;
857 } else {
858 qemu_fprintf(f, "P%02d=", i);
859 switch (zcr_len) {
860 case 0:
861 eol = i % 8 == 7;
862 break;
863 case 1:
864 eol = i % 6 == 5;
865 break;
866 case 2:
867 case 3:
868 eol = i % 3 == 2;
869 break;
870 default:
871 /* More than one quadword per predicate. */
872 eol = true;
873 break;
874 }
875 }
876 for (j = zcr_len / 4; j >= 0; j--) {
877 int digits;
878 if (j * 4 + 4 <= zcr_len + 1) {
879 digits = 16;
880 } else {
881 digits = (zcr_len % 4 + 1) * 4;
882 }
883 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
884 env->vfp.pregs[i].p[j],
885 j ? ":" : eol ? "\n" : " ");
886 }
887 }
888
889 for (i = 0; i < 32; i++) {
890 if (zcr_len == 0) {
891 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
892 i, env->vfp.zregs[i].d[1],
893 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
894 } else if (zcr_len == 1) {
895 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
896 ":%016" PRIx64 ":%016" PRIx64 "\n",
897 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
898 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
899 } else {
900 for (j = zcr_len; j >= 0; j--) {
901 bool odd = (zcr_len - j) % 2 != 0;
902 if (j == zcr_len) {
903 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
904 } else if (!odd) {
905 if (j > 0) {
906 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
907 } else {
908 qemu_fprintf(f, " [%x]=", j);
909 }
910 }
911 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
912 env->vfp.zregs[i].d[j * 2 + 1],
913 env->vfp.zregs[i].d[j * 2],
914 odd || j == 0 ? "\n" : ":");
915 }
916 }
917 }
918 } else {
919 for (i = 0; i < 32; i++) {
920 uint64_t *q = aa64_vfp_qreg(env, i);
921 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
922 i, q[1], q[0], (i & 1 ? "\n" : " "));
923 }
924 }
925 }
926
927 #else
928
929 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
930 {
931 g_assert_not_reached();
932 }
933
934 #endif
935
936 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
937 {
938 ARMCPU *cpu = ARM_CPU(cs);
939 CPUARMState *env = &cpu->env;
940 int i;
941
942 if (is_a64(env)) {
943 aarch64_cpu_dump_state(cs, f, flags);
944 return;
945 }
946
947 for (i = 0; i < 16; i++) {
948 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
949 if ((i % 4) == 3) {
950 qemu_fprintf(f, "\n");
951 } else {
952 qemu_fprintf(f, " ");
953 }
954 }
955
956 if (arm_feature(env, ARM_FEATURE_M)) {
957 uint32_t xpsr = xpsr_read(env);
958 const char *mode;
959 const char *ns_status = "";
960
961 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
962 ns_status = env->v7m.secure ? "S " : "NS ";
963 }
964
965 if (xpsr & XPSR_EXCP) {
966 mode = "handler";
967 } else {
968 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
969 mode = "unpriv-thread";
970 } else {
971 mode = "priv-thread";
972 }
973 }
974
975 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
976 xpsr,
977 xpsr & XPSR_N ? 'N' : '-',
978 xpsr & XPSR_Z ? 'Z' : '-',
979 xpsr & XPSR_C ? 'C' : '-',
980 xpsr & XPSR_V ? 'V' : '-',
981 xpsr & XPSR_T ? 'T' : 'A',
982 ns_status,
983 mode);
984 } else {
985 uint32_t psr = cpsr_read(env);
986 const char *ns_status = "";
987
988 if (arm_feature(env, ARM_FEATURE_EL3) &&
989 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
990 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
991 }
992
993 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
994 psr,
995 psr & CPSR_N ? 'N' : '-',
996 psr & CPSR_Z ? 'Z' : '-',
997 psr & CPSR_C ? 'C' : '-',
998 psr & CPSR_V ? 'V' : '-',
999 psr & CPSR_T ? 'T' : 'A',
1000 ns_status,
1001 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1002 }
1003
1004 if (flags & CPU_DUMP_FPU) {
1005 int numvfpregs = 0;
1006 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1007 numvfpregs = 32;
1008 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1009 numvfpregs = 16;
1010 }
1011 for (i = 0; i < numvfpregs; i++) {
1012 uint64_t v = *aa32_vfp_dreg(env, i);
1013 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1014 i * 2, (uint32_t)v,
1015 i * 2 + 1, (uint32_t)(v >> 32),
1016 i, v);
1017 }
1018 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1019 }
1020 }
1021
1022 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
1023 {
1024 uint32_t Aff1 = idx / clustersz;
1025 uint32_t Aff0 = idx % clustersz;
1026 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1027 }
1028
1029 static void cpreg_hashtable_data_destroy(gpointer data)
1030 {
1031 /*
1032 * Destroy function for cpu->cp_regs hashtable data entries.
1033 * We must free the name string because it was g_strdup()ed in
1034 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1035 * from r->name because we know we definitely allocated it.
1036 */
1037 ARMCPRegInfo *r = data;
1038
1039 g_free((void *)r->name);
1040 g_free(r);
1041 }
1042
1043 static void arm_cpu_initfn(Object *obj)
1044 {
1045 ARMCPU *cpu = ARM_CPU(obj);
1046
1047 cpu_set_cpustate_pointers(cpu);
1048 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
1049 g_free, cpreg_hashtable_data_destroy);
1050
1051 QLIST_INIT(&cpu->pre_el_change_hooks);
1052 QLIST_INIT(&cpu->el_change_hooks);
1053
1054 #ifndef CONFIG_USER_ONLY
1055 /* Our inbound IRQ and FIQ lines */
1056 if (kvm_enabled()) {
1057 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1058 * the same interface as non-KVM CPUs.
1059 */
1060 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
1061 } else {
1062 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
1063 }
1064
1065 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1066 ARRAY_SIZE(cpu->gt_timer_outputs));
1067
1068 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1069 "gicv3-maintenance-interrupt", 1);
1070 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1071 "pmu-interrupt", 1);
1072 #endif
1073
1074 /* DTB consumers generally don't in fact care what the 'compatible'
1075 * string is, so always provide some string and trust that a hypothetical
1076 * picky DTB consumer will also provide a helpful error message.
1077 */
1078 cpu->dtb_compatible = "qemu,unknown";
1079 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
1080 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1081
1082 if (tcg_enabled()) {
1083 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
1084 }
1085 }
1086
1087 static Property arm_cpu_gt_cntfrq_property =
1088 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
1089 NANOSECONDS_PER_SECOND / GTIMER_SCALE);
1090
1091 static Property arm_cpu_reset_cbar_property =
1092 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1093
1094 static Property arm_cpu_reset_hivecs_property =
1095 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1096
1097 static Property arm_cpu_rvbar_property =
1098 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
1099
1100 #ifndef CONFIG_USER_ONLY
1101 static Property arm_cpu_has_el2_property =
1102 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1103
1104 static Property arm_cpu_has_el3_property =
1105 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1106 #endif
1107
1108 static Property arm_cpu_cfgend_property =
1109 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1110
1111 static Property arm_cpu_has_vfp_property =
1112 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1113
1114 static Property arm_cpu_has_neon_property =
1115 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1116
1117 static Property arm_cpu_has_dsp_property =
1118 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1119
1120 static Property arm_cpu_has_mpu_property =
1121 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1122
1123 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1124 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1125 * the right value for that particular CPU type, and we don't want
1126 * to override that with an incorrect constant value.
1127 */
1128 static Property arm_cpu_pmsav7_dregion_property =
1129 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1130 pmsav7_dregion,
1131 qdev_prop_uint32, uint32_t);
1132
1133 static bool arm_get_pmu(Object *obj, Error **errp)
1134 {
1135 ARMCPU *cpu = ARM_CPU(obj);
1136
1137 return cpu->has_pmu;
1138 }
1139
1140 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1141 {
1142 ARMCPU *cpu = ARM_CPU(obj);
1143
1144 if (value) {
1145 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
1146 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1147 return;
1148 }
1149 set_feature(&cpu->env, ARM_FEATURE_PMU);
1150 } else {
1151 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1152 }
1153 cpu->has_pmu = value;
1154 }
1155
1156 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
1157 void *opaque, Error **errp)
1158 {
1159 ARMCPU *cpu = ARM_CPU(obj);
1160
1161 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1162 }
1163
1164 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
1165 void *opaque, Error **errp)
1166 {
1167 ARMCPU *cpu = ARM_CPU(obj);
1168
1169 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1170 }
1171
1172 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1173 {
1174 /*
1175 * The exact approach to calculating guest ticks is:
1176 *
1177 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1178 * NANOSECONDS_PER_SECOND);
1179 *
1180 * We don't do that. Rather we intentionally use integer division
1181 * truncation below and in the caller for the conversion of host monotonic
1182 * time to guest ticks to provide the exact inverse for the semantics of
1183 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1184 * it loses precision when representing frequencies where
1185 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1186 * provide an exact inverse leads to scheduling timers with negative
1187 * periods, which in turn leads to sticky behaviour in the guest.
1188 *
1189 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1190 * cannot become zero.
1191 */
1192 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1193 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1194 }
1195
1196 void arm_cpu_post_init(Object *obj)
1197 {
1198 ARMCPU *cpu = ARM_CPU(obj);
1199
1200 /* M profile implies PMSA. We have to do this here rather than
1201 * in realize with the other feature-implication checks because
1202 * we look at the PMSA bit to see if we should add some properties.
1203 */
1204 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1205 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1206 }
1207
1208 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1209 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1210 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1211 }
1212
1213 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1214 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1215 }
1216
1217 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1218 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
1219 }
1220
1221 #ifndef CONFIG_USER_ONLY
1222 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1223 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1224 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1225 */
1226 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1227
1228 object_property_add_link(obj, "secure-memory",
1229 TYPE_MEMORY_REGION,
1230 (Object **)&cpu->secure_memory,
1231 qdev_prop_allow_set_link_before_realize,
1232 OBJ_PROP_LINK_STRONG,
1233 &error_abort);
1234 }
1235
1236 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1237 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1238 }
1239 #endif
1240
1241 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1242 cpu->has_pmu = true;
1243 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
1244 &error_abort);
1245 }
1246
1247 /*
1248 * Allow user to turn off VFP and Neon support, but only for TCG --
1249 * KVM does not currently allow us to lie to the guest about its
1250 * ID/feature registers, so the guest always sees what the host has.
1251 */
1252 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
1253 ? cpu_isar_feature(aa64_fp_simd, cpu)
1254 : cpu_isar_feature(aa32_vfp, cpu)) {
1255 cpu->has_vfp = true;
1256 if (!kvm_enabled()) {
1257 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1258 }
1259 }
1260
1261 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1262 cpu->has_neon = true;
1263 if (!kvm_enabled()) {
1264 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1265 }
1266 }
1267
1268 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1269 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1270 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1271 }
1272
1273 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1274 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1275 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1276 qdev_property_add_static(DEVICE(obj),
1277 &arm_cpu_pmsav7_dregion_property);
1278 }
1279 }
1280
1281 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1282 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1283 qdev_prop_allow_set_link_before_realize,
1284 OBJ_PROP_LINK_STRONG,
1285 &error_abort);
1286 /*
1287 * M profile: initial value of the Secure VTOR. We can't just use
1288 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1289 * the property to be set after realize.
1290 */
1291 object_property_add(obj, "init-svtor", "uint32",
1292 arm_get_init_svtor, arm_set_init_svtor,
1293 NULL, NULL, &error_abort);
1294 }
1295
1296 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1297
1298 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1299 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1300 }
1301 }
1302
1303 static void arm_cpu_finalizefn(Object *obj)
1304 {
1305 ARMCPU *cpu = ARM_CPU(obj);
1306 ARMELChangeHook *hook, *next;
1307
1308 g_hash_table_destroy(cpu->cp_regs);
1309
1310 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1311 QLIST_REMOVE(hook, node);
1312 g_free(hook);
1313 }
1314 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1315 QLIST_REMOVE(hook, node);
1316 g_free(hook);
1317 }
1318 #ifndef CONFIG_USER_ONLY
1319 if (cpu->pmu_timer) {
1320 timer_del(cpu->pmu_timer);
1321 timer_deinit(cpu->pmu_timer);
1322 timer_free(cpu->pmu_timer);
1323 }
1324 #endif
1325 }
1326
1327 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1328 {
1329 Error *local_err = NULL;
1330
1331 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1332 arm_cpu_sve_finalize(cpu, &local_err);
1333 if (local_err != NULL) {
1334 error_propagate(errp, local_err);
1335 return;
1336 }
1337 }
1338 }
1339
1340 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1341 {
1342 CPUState *cs = CPU(dev);
1343 ARMCPU *cpu = ARM_CPU(dev);
1344 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1345 CPUARMState *env = &cpu->env;
1346 int pagebits;
1347 Error *local_err = NULL;
1348 bool no_aa32 = false;
1349
1350 /* If we needed to query the host kernel for the CPU features
1351 * then it's possible that might have failed in the initfn, but
1352 * this is the first point where we can report it.
1353 */
1354 if (cpu->host_cpu_probe_failed) {
1355 if (!kvm_enabled()) {
1356 error_setg(errp, "The 'host' CPU type can only be used with KVM");
1357 } else {
1358 error_setg(errp, "Failed to retrieve host CPU features");
1359 }
1360 return;
1361 }
1362
1363 #ifndef CONFIG_USER_ONLY
1364 /* The NVIC and M-profile CPU are two halves of a single piece of
1365 * hardware; trying to use one without the other is a command line
1366 * error and will result in segfaults if not caught here.
1367 */
1368 if (arm_feature(env, ARM_FEATURE_M)) {
1369 if (!env->nvic) {
1370 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1371 return;
1372 }
1373 } else {
1374 if (env->nvic) {
1375 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1376 return;
1377 }
1378 }
1379
1380 {
1381 uint64_t scale;
1382
1383 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1384 if (!cpu->gt_cntfrq_hz) {
1385 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
1386 cpu->gt_cntfrq_hz);
1387 return;
1388 }
1389 scale = gt_cntfrq_period_ns(cpu);
1390 } else {
1391 scale = GTIMER_SCALE;
1392 }
1393
1394 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1395 arm_gt_ptimer_cb, cpu);
1396 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1397 arm_gt_vtimer_cb, cpu);
1398 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1399 arm_gt_htimer_cb, cpu);
1400 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1401 arm_gt_stimer_cb, cpu);
1402 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1403 arm_gt_hvtimer_cb, cpu);
1404 }
1405 #endif
1406
1407 cpu_exec_realizefn(cs, &local_err);
1408 if (local_err != NULL) {
1409 error_propagate(errp, local_err);
1410 return;
1411 }
1412
1413 arm_cpu_finalize_features(cpu, &local_err);
1414 if (local_err != NULL) {
1415 error_propagate(errp, local_err);
1416 return;
1417 }
1418
1419 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1420 cpu->has_vfp != cpu->has_neon) {
1421 /*
1422 * This is an architectural requirement for AArch64; AArch32 is
1423 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1424 */
1425 error_setg(errp,
1426 "AArch64 CPUs must have both VFP and Neon or neither");
1427 return;
1428 }
1429
1430 if (!cpu->has_vfp) {
1431 uint64_t t;
1432 uint32_t u;
1433
1434 t = cpu->isar.id_aa64isar1;
1435 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1436 cpu->isar.id_aa64isar1 = t;
1437
1438 t = cpu->isar.id_aa64pfr0;
1439 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1440 cpu->isar.id_aa64pfr0 = t;
1441
1442 u = cpu->isar.id_isar6;
1443 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1444 cpu->isar.id_isar6 = u;
1445
1446 u = cpu->isar.mvfr0;
1447 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1448 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1449 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1450 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1451 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1452 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1453 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1454 cpu->isar.mvfr0 = u;
1455
1456 u = cpu->isar.mvfr1;
1457 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1458 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1459 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1460 cpu->isar.mvfr1 = u;
1461
1462 u = cpu->isar.mvfr2;
1463 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1464 cpu->isar.mvfr2 = u;
1465 }
1466
1467 if (!cpu->has_neon) {
1468 uint64_t t;
1469 uint32_t u;
1470
1471 unset_feature(env, ARM_FEATURE_NEON);
1472
1473 t = cpu->isar.id_aa64isar0;
1474 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1475 cpu->isar.id_aa64isar0 = t;
1476
1477 t = cpu->isar.id_aa64isar1;
1478 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1479 cpu->isar.id_aa64isar1 = t;
1480
1481 t = cpu->isar.id_aa64pfr0;
1482 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1483 cpu->isar.id_aa64pfr0 = t;
1484
1485 u = cpu->isar.id_isar5;
1486 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1487 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1488 cpu->isar.id_isar5 = u;
1489
1490 u = cpu->isar.id_isar6;
1491 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1492 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1493 cpu->isar.id_isar6 = u;
1494
1495 u = cpu->isar.mvfr1;
1496 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1497 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1498 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1499 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1500 cpu->isar.mvfr1 = u;
1501
1502 u = cpu->isar.mvfr2;
1503 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1504 cpu->isar.mvfr2 = u;
1505 }
1506
1507 if (!cpu->has_neon && !cpu->has_vfp) {
1508 uint64_t t;
1509 uint32_t u;
1510
1511 t = cpu->isar.id_aa64isar0;
1512 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1513 cpu->isar.id_aa64isar0 = t;
1514
1515 t = cpu->isar.id_aa64isar1;
1516 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1517 cpu->isar.id_aa64isar1 = t;
1518
1519 u = cpu->isar.mvfr0;
1520 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1521 cpu->isar.mvfr0 = u;
1522
1523 /* Despite the name, this field covers both VFP and Neon */
1524 u = cpu->isar.mvfr1;
1525 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1526 cpu->isar.mvfr1 = u;
1527 }
1528
1529 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1530 uint32_t u;
1531
1532 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1533
1534 u = cpu->isar.id_isar1;
1535 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1536 cpu->isar.id_isar1 = u;
1537
1538 u = cpu->isar.id_isar2;
1539 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1540 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1541 cpu->isar.id_isar2 = u;
1542
1543 u = cpu->isar.id_isar3;
1544 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1545 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1546 cpu->isar.id_isar3 = u;
1547 }
1548
1549 /* Some features automatically imply others: */
1550 if (arm_feature(env, ARM_FEATURE_V8)) {
1551 if (arm_feature(env, ARM_FEATURE_M)) {
1552 set_feature(env, ARM_FEATURE_V7);
1553 } else {
1554 set_feature(env, ARM_FEATURE_V7VE);
1555 }
1556 }
1557
1558 /*
1559 * There exist AArch64 cpus without AArch32 support. When KVM
1560 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1561 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1562 * As a general principle, we also do not make ID register
1563 * consistency checks anywhere unless using TCG, because only
1564 * for TCG would a consistency-check failure be a QEMU bug.
1565 */
1566 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1567 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1568 }
1569
1570 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1571 /* v7 Virtualization Extensions. In real hardware this implies
1572 * EL2 and also the presence of the Security Extensions.
1573 * For QEMU, for backwards-compatibility we implement some
1574 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1575 * include the various other features that V7VE implies.
1576 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1577 * Security Extensions is ARM_FEATURE_EL3.
1578 */
1579 assert(!tcg_enabled() || no_aa32 ||
1580 cpu_isar_feature(aa32_arm_div, cpu));
1581 set_feature(env, ARM_FEATURE_LPAE);
1582 set_feature(env, ARM_FEATURE_V7);
1583 }
1584 if (arm_feature(env, ARM_FEATURE_V7)) {
1585 set_feature(env, ARM_FEATURE_VAPA);
1586 set_feature(env, ARM_FEATURE_THUMB2);
1587 set_feature(env, ARM_FEATURE_MPIDR);
1588 if (!arm_feature(env, ARM_FEATURE_M)) {
1589 set_feature(env, ARM_FEATURE_V6K);
1590 } else {
1591 set_feature(env, ARM_FEATURE_V6);
1592 }
1593
1594 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1595 * non-EL3 configs. This is needed by some legacy boards.
1596 */
1597 set_feature(env, ARM_FEATURE_VBAR);
1598 }
1599 if (arm_feature(env, ARM_FEATURE_V6K)) {
1600 set_feature(env, ARM_FEATURE_V6);
1601 set_feature(env, ARM_FEATURE_MVFR);
1602 }
1603 if (arm_feature(env, ARM_FEATURE_V6)) {
1604 set_feature(env, ARM_FEATURE_V5);
1605 if (!arm_feature(env, ARM_FEATURE_M)) {
1606 assert(!tcg_enabled() || no_aa32 ||
1607 cpu_isar_feature(aa32_jazelle, cpu));
1608 set_feature(env, ARM_FEATURE_AUXCR);
1609 }
1610 }
1611 if (arm_feature(env, ARM_FEATURE_V5)) {
1612 set_feature(env, ARM_FEATURE_V4T);
1613 }
1614 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1615 set_feature(env, ARM_FEATURE_V7MP);
1616 set_feature(env, ARM_FEATURE_PXN);
1617 }
1618 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1619 set_feature(env, ARM_FEATURE_CBAR);
1620 }
1621 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1622 !arm_feature(env, ARM_FEATURE_M)) {
1623 set_feature(env, ARM_FEATURE_THUMB_DSP);
1624 }
1625
1626 /*
1627 * We rely on no XScale CPU having VFP so we can use the same bits in the
1628 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1629 */
1630 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
1631 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
1632 !arm_feature(env, ARM_FEATURE_XSCALE));
1633
1634 if (arm_feature(env, ARM_FEATURE_V7) &&
1635 !arm_feature(env, ARM_FEATURE_M) &&
1636 !arm_feature(env, ARM_FEATURE_PMSA)) {
1637 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1638 * can use 4K pages.
1639 */
1640 pagebits = 12;
1641 } else {
1642 /* For CPUs which might have tiny 1K pages, or which have an
1643 * MPU and might have small region sizes, stick with 1K pages.
1644 */
1645 pagebits = 10;
1646 }
1647 if (!set_preferred_target_page_bits(pagebits)) {
1648 /* This can only ever happen for hotplugging a CPU, or if
1649 * the board code incorrectly creates a CPU which it has
1650 * promised via minimum_page_size that it will not.
1651 */
1652 error_setg(errp, "This CPU requires a smaller page size than the "
1653 "system is using");
1654 return;
1655 }
1656
1657 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1658 * We don't support setting cluster ID ([16..23]) (known as Aff2
1659 * in later ARM ARM versions), or any of the higher affinity level fields,
1660 * so these bits always RAZ.
1661 */
1662 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1663 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1664 ARM_DEFAULT_CPUS_PER_CLUSTER);
1665 }
1666
1667 if (cpu->reset_hivecs) {
1668 cpu->reset_sctlr |= (1 << 13);
1669 }
1670
1671 if (cpu->cfgend) {
1672 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1673 cpu->reset_sctlr |= SCTLR_EE;
1674 } else {
1675 cpu->reset_sctlr |= SCTLR_B;
1676 }
1677 }
1678
1679 if (!cpu->has_el3) {
1680 /* If the has_el3 CPU property is disabled then we need to disable the
1681 * feature.
1682 */
1683 unset_feature(env, ARM_FEATURE_EL3);
1684
1685 /* Disable the security extension feature bits in the processor feature
1686 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1687 */
1688 cpu->id_pfr1 &= ~0xf0;
1689 cpu->isar.id_aa64pfr0 &= ~0xf000;
1690 }
1691
1692 if (!cpu->has_el2) {
1693 unset_feature(env, ARM_FEATURE_EL2);
1694 }
1695
1696 if (!cpu->has_pmu) {
1697 unset_feature(env, ARM_FEATURE_PMU);
1698 }
1699 if (arm_feature(env, ARM_FEATURE_PMU)) {
1700 pmu_init(cpu);
1701
1702 if (!kvm_enabled()) {
1703 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1704 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1705 }
1706
1707 #ifndef CONFIG_USER_ONLY
1708 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1709 cpu);
1710 #endif
1711 } else {
1712 cpu->isar.id_aa64dfr0 =
1713 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
1714 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
1715 cpu->pmceid0 = 0;
1716 cpu->pmceid1 = 0;
1717 }
1718
1719 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1720 /* Disable the hypervisor feature bits in the processor feature
1721 * registers if we don't have EL2. These are id_pfr1[15:12] and
1722 * id_aa64pfr0_el1[11:8].
1723 */
1724 cpu->isar.id_aa64pfr0 &= ~0xf00;
1725 cpu->id_pfr1 &= ~0xf000;
1726 }
1727
1728 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1729 * to false or by setting pmsav7-dregion to 0.
1730 */
1731 if (!cpu->has_mpu) {
1732 cpu->pmsav7_dregion = 0;
1733 }
1734 if (cpu->pmsav7_dregion == 0) {
1735 cpu->has_mpu = false;
1736 }
1737
1738 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1739 arm_feature(env, ARM_FEATURE_V7)) {
1740 uint32_t nr = cpu->pmsav7_dregion;
1741
1742 if (nr > 0xff) {
1743 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1744 return;
1745 }
1746
1747 if (nr) {
1748 if (arm_feature(env, ARM_FEATURE_V8)) {
1749 /* PMSAv8 */
1750 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1751 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1752 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1753 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1754 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1755 }
1756 } else {
1757 env->pmsav7.drbar = g_new0(uint32_t, nr);
1758 env->pmsav7.drsr = g_new0(uint32_t, nr);
1759 env->pmsav7.dracr = g_new0(uint32_t, nr);
1760 }
1761 }
1762 }
1763
1764 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1765 uint32_t nr = cpu->sau_sregion;
1766
1767 if (nr > 0xff) {
1768 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1769 return;
1770 }
1771
1772 if (nr) {
1773 env->sau.rbar = g_new0(uint32_t, nr);
1774 env->sau.rlar = g_new0(uint32_t, nr);
1775 }
1776 }
1777
1778 if (arm_feature(env, ARM_FEATURE_EL3)) {
1779 set_feature(env, ARM_FEATURE_VBAR);
1780 }
1781
1782 register_cp_regs_for_features(cpu);
1783 arm_cpu_register_gdb_regs_for_features(cpu);
1784
1785 init_cpreg_list(cpu);
1786
1787 #ifndef CONFIG_USER_ONLY
1788 MachineState *ms = MACHINE(qdev_get_machine());
1789 unsigned int smp_cpus = ms->smp.cpus;
1790
1791 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1792 cs->num_ases = 2;
1793
1794 if (!cpu->secure_memory) {
1795 cpu->secure_memory = cs->memory;
1796 }
1797 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1798 cpu->secure_memory);
1799 } else {
1800 cs->num_ases = 1;
1801 }
1802 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1803
1804 /* No core_count specified, default to smp_cpus. */
1805 if (cpu->core_count == -1) {
1806 cpu->core_count = smp_cpus;
1807 }
1808 #endif
1809
1810 qemu_init_vcpu(cs);
1811 cpu_reset(cs);
1812
1813 acc->parent_realize(dev, errp);
1814 }
1815
1816 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1817 {
1818 ObjectClass *oc;
1819 char *typename;
1820 char **cpuname;
1821 const char *cpunamestr;
1822
1823 cpuname = g_strsplit(cpu_model, ",", 1);
1824 cpunamestr = cpuname[0];
1825 #ifdef CONFIG_USER_ONLY
1826 /* For backwards compatibility usermode emulation allows "-cpu any",
1827 * which has the same semantics as "-cpu max".
1828 */
1829 if (!strcmp(cpunamestr, "any")) {
1830 cpunamestr = "max";
1831 }
1832 #endif
1833 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1834 oc = object_class_by_name(typename);
1835 g_strfreev(cpuname);
1836 g_free(typename);
1837 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1838 object_class_is_abstract(oc)) {
1839 return NULL;
1840 }
1841 return oc;
1842 }
1843
1844 /* CPU models. These are not needed for the AArch64 linux-user build. */
1845 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1846
1847 static void arm926_initfn(Object *obj)
1848 {
1849 ARMCPU *cpu = ARM_CPU(obj);
1850
1851 cpu->dtb_compatible = "arm,arm926";
1852 set_feature(&cpu->env, ARM_FEATURE_V5);
1853 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1854 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1855 cpu->midr = 0x41069265;
1856 cpu->reset_fpsid = 0x41011090;
1857 cpu->ctr = 0x1dd20d2;
1858 cpu->reset_sctlr = 0x00090078;
1859
1860 /*
1861 * ARMv5 does not have the ID_ISAR registers, but we can still
1862 * set the field to indicate Jazelle support within QEMU.
1863 */
1864 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1865 /*
1866 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
1867 * support even though ARMv5 doesn't have this register.
1868 */
1869 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1870 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
1871 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
1872 }
1873
1874 static void arm946_initfn(Object *obj)
1875 {
1876 ARMCPU *cpu = ARM_CPU(obj);
1877
1878 cpu->dtb_compatible = "arm,arm946";
1879 set_feature(&cpu->env, ARM_FEATURE_V5);
1880 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1881 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1882 cpu->midr = 0x41059461;
1883 cpu->ctr = 0x0f004006;
1884 cpu->reset_sctlr = 0x00000078;
1885 }
1886
1887 static void arm1026_initfn(Object *obj)
1888 {
1889 ARMCPU *cpu = ARM_CPU(obj);
1890
1891 cpu->dtb_compatible = "arm,arm1026";
1892 set_feature(&cpu->env, ARM_FEATURE_V5);
1893 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1894 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1895 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1896 cpu->midr = 0x4106a262;
1897 cpu->reset_fpsid = 0x410110a0;
1898 cpu->ctr = 0x1dd20d2;
1899 cpu->reset_sctlr = 0x00090078;
1900 cpu->reset_auxcr = 1;
1901
1902 /*
1903 * ARMv5 does not have the ID_ISAR registers, but we can still
1904 * set the field to indicate Jazelle support within QEMU.
1905 */
1906 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1907 /*
1908 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
1909 * support even though ARMv5 doesn't have this register.
1910 */
1911 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1912 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
1913 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
1914
1915 {
1916 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1917 ARMCPRegInfo ifar = {
1918 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1919 .access = PL1_RW,
1920 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1921 .resetvalue = 0
1922 };
1923 define_one_arm_cp_reg(cpu, &ifar);
1924 }
1925 }
1926
1927 static void arm1136_r2_initfn(Object *obj)
1928 {
1929 ARMCPU *cpu = ARM_CPU(obj);
1930 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1931 * older core than plain "arm1136". In particular this does not
1932 * have the v6K features.
1933 * These ID register values are correct for 1136 but may be wrong
1934 * for 1136_r2 (in particular r0p2 does not actually implement most
1935 * of the ID registers).
1936 */
1937
1938 cpu->dtb_compatible = "arm,arm1136";
1939 set_feature(&cpu->env, ARM_FEATURE_V6);
1940 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1941 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1942 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1943 cpu->midr = 0x4107b362;
1944 cpu->reset_fpsid = 0x410120b4;
1945 cpu->isar.mvfr0 = 0x11111111;
1946 cpu->isar.mvfr1 = 0x00000000;
1947 cpu->ctr = 0x1dd20d2;
1948 cpu->reset_sctlr = 0x00050078;
1949 cpu->id_pfr0 = 0x111;
1950 cpu->id_pfr1 = 0x1;
1951 cpu->isar.id_dfr0 = 0x2;
1952 cpu->id_afr0 = 0x3;
1953 cpu->isar.id_mmfr0 = 0x01130003;
1954 cpu->isar.id_mmfr1 = 0x10030302;
1955 cpu->isar.id_mmfr2 = 0x01222110;
1956 cpu->isar.id_isar0 = 0x00140011;
1957 cpu->isar.id_isar1 = 0x12002111;
1958 cpu->isar.id_isar2 = 0x11231111;
1959 cpu->isar.id_isar3 = 0x01102131;
1960 cpu->isar.id_isar4 = 0x141;
1961 cpu->reset_auxcr = 7;
1962 }
1963
1964 static void arm1136_initfn(Object *obj)
1965 {
1966 ARMCPU *cpu = ARM_CPU(obj);
1967
1968 cpu->dtb_compatible = "arm,arm1136";
1969 set_feature(&cpu->env, ARM_FEATURE_V6K);
1970 set_feature(&cpu->env, ARM_FEATURE_V6);
1971 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1972 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1973 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1974 cpu->midr = 0x4117b363;
1975 cpu->reset_fpsid = 0x410120b4;
1976 cpu->isar.mvfr0 = 0x11111111;
1977 cpu->isar.mvfr1 = 0x00000000;
1978 cpu->ctr = 0x1dd20d2;
1979 cpu->reset_sctlr = 0x00050078;
1980 cpu->id_pfr0 = 0x111;
1981 cpu->id_pfr1 = 0x1;
1982 cpu->isar.id_dfr0 = 0x2;
1983 cpu->id_afr0 = 0x3;
1984 cpu->isar.id_mmfr0 = 0x01130003;
1985 cpu->isar.id_mmfr1 = 0x10030302;
1986 cpu->isar.id_mmfr2 = 0x01222110;
1987 cpu->isar.id_isar0 = 0x00140011;
1988 cpu->isar.id_isar1 = 0x12002111;
1989 cpu->isar.id_isar2 = 0x11231111;
1990 cpu->isar.id_isar3 = 0x01102131;
1991 cpu->isar.id_isar4 = 0x141;
1992 cpu->reset_auxcr = 7;
1993 }
1994
1995 static void arm1176_initfn(Object *obj)
1996 {
1997 ARMCPU *cpu = ARM_CPU(obj);
1998
1999 cpu->dtb_compatible = "arm,arm1176";
2000 set_feature(&cpu->env, ARM_FEATURE_V6K);
2001 set_feature(&cpu->env, ARM_FEATURE_VAPA);
2002 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2003 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
2004 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
2005 set_feature(&cpu->env, ARM_FEATURE_EL3);
2006 cpu->midr = 0x410fb767;
2007 cpu->reset_fpsid = 0x410120b5;
2008 cpu->isar.mvfr0 = 0x11111111;
2009 cpu->isar.mvfr1 = 0x00000000;
2010 cpu->ctr = 0x1dd20d2;
2011 cpu->reset_sctlr = 0x00050078;
2012 cpu->id_pfr0 = 0x111;
2013 cpu->id_pfr1 = 0x11;
2014 cpu->isar.id_dfr0 = 0x33;
2015 cpu->id_afr0 = 0;
2016 cpu->isar.id_mmfr0 = 0x01130003;
2017 cpu->isar.id_mmfr1 = 0x10030302;
2018 cpu->isar.id_mmfr2 = 0x01222100;
2019 cpu->isar.id_isar0 = 0x0140011;
2020 cpu->isar.id_isar1 = 0x12002111;
2021 cpu->isar.id_isar2 = 0x11231121;
2022 cpu->isar.id_isar3 = 0x01102131;
2023 cpu->isar.id_isar4 = 0x01141;
2024 cpu->reset_auxcr = 7;
2025 }
2026
2027 static void arm11mpcore_initfn(Object *obj)
2028 {
2029 ARMCPU *cpu = ARM_CPU(obj);
2030
2031 cpu->dtb_compatible = "arm,arm11mpcore";
2032 set_feature(&cpu->env, ARM_FEATURE_V6K);
2033 set_feature(&cpu->env, ARM_FEATURE_VAPA);
2034 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
2035 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2036 cpu->midr = 0x410fb022;
2037 cpu->reset_fpsid = 0x410120b4;
2038 cpu->isar.mvfr0 = 0x11111111;
2039 cpu->isar.mvfr1 = 0x00000000;
2040 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
2041 cpu->id_pfr0 = 0x111;
2042 cpu->id_pfr1 = 0x1;
2043 cpu->isar.id_dfr0 = 0;
2044 cpu->id_afr0 = 0x2;
2045 cpu->isar.id_mmfr0 = 0x01100103;
2046 cpu->isar.id_mmfr1 = 0x10020302;
2047 cpu->isar.id_mmfr2 = 0x01222000;
2048 cpu->isar.id_isar0 = 0x00100011;
2049 cpu->isar.id_isar1 = 0x12002111;
2050 cpu->isar.id_isar2 = 0x11221011;
2051 cpu->isar.id_isar3 = 0x01102131;
2052 cpu->isar.id_isar4 = 0x141;
2053 cpu->reset_auxcr = 1;
2054 }
2055
2056 static void cortex_m0_initfn(Object *obj)
2057 {
2058 ARMCPU *cpu = ARM_CPU(obj);
2059 set_feature(&cpu->env, ARM_FEATURE_V6);
2060 set_feature(&cpu->env, ARM_FEATURE_M);
2061
2062 cpu->midr = 0x410cc200;
2063 }
2064
2065 static void cortex_m3_initfn(Object *obj)
2066 {
2067 ARMCPU *cpu = ARM_CPU(obj);
2068 set_feature(&cpu->env, ARM_FEATURE_V7);
2069 set_feature(&cpu->env, ARM_FEATURE_M);
2070 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
2071 cpu->midr = 0x410fc231;
2072 cpu->pmsav7_dregion = 8;
2073 cpu->id_pfr0 = 0x00000030;
2074 cpu->id_pfr1 = 0x00000200;
2075 cpu->isar.id_dfr0 = 0x00100000;
2076 cpu->id_afr0 = 0x00000000;
2077 cpu->isar.id_mmfr0 = 0x00000030;
2078 cpu->isar.id_mmfr1 = 0x00000000;
2079 cpu->isar.id_mmfr2 = 0x00000000;
2080 cpu->isar.id_mmfr3 = 0x00000000;
2081 cpu->isar.id_isar0 = 0x01141110;
2082 cpu->isar.id_isar1 = 0x02111000;
2083 cpu->isar.id_isar2 = 0x21112231;
2084 cpu->isar.id_isar3 = 0x01111110;
2085 cpu->isar.id_isar4 = 0x01310102;
2086 cpu->isar.id_isar5 = 0x00000000;
2087 cpu->isar.id_isar6 = 0x00000000;
2088 }
2089
2090 static void cortex_m4_initfn(Object *obj)
2091 {
2092 ARMCPU *cpu = ARM_CPU(obj);
2093
2094 set_feature(&cpu->env, ARM_FEATURE_V7);
2095 set_feature(&cpu->env, ARM_FEATURE_M);
2096 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
2097 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
2098 cpu->midr = 0x410fc240; /* r0p0 */
2099 cpu->pmsav7_dregion = 8;
2100 cpu->isar.mvfr0 = 0x10110021;
2101 cpu->isar.mvfr1 = 0x11000011;
2102 cpu->isar.mvfr2 = 0x00000000;
2103 cpu->id_pfr0 = 0x00000030;
2104 cpu->id_pfr1 = 0x00000200;
2105 cpu->isar.id_dfr0 = 0x00100000;
2106 cpu->id_afr0 = 0x00000000;
2107 cpu->isar.id_mmfr0 = 0x00000030;
2108 cpu->isar.id_mmfr1 = 0x00000000;
2109 cpu->isar.id_mmfr2 = 0x00000000;
2110 cpu->isar.id_mmfr3 = 0x00000000;
2111 cpu->isar.id_isar0 = 0x01141110;
2112 cpu->isar.id_isar1 = 0x02111000;
2113 cpu->isar.id_isar2 = 0x21112231;
2114 cpu->isar.id_isar3 = 0x01111110;
2115 cpu->isar.id_isar4 = 0x01310102;
2116 cpu->isar.id_isar5 = 0x00000000;
2117 cpu->isar.id_isar6 = 0x00000000;
2118 }
2119
2120 static void cortex_m7_initfn(Object *obj)
2121 {
2122 ARMCPU *cpu = ARM_CPU(obj);
2123
2124 set_feature(&cpu->env, ARM_FEATURE_V7);
2125 set_feature(&cpu->env, ARM_FEATURE_M);
2126 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
2127 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
2128 cpu->midr = 0x411fc272; /* r1p2 */
2129 cpu->pmsav7_dregion = 8;
2130 cpu->isar.mvfr0 = 0x10110221;
2131 cpu->isar.mvfr1 = 0x12000011;
2132 cpu->isar.mvfr2 = 0x00000040;
2133 cpu->id_pfr0 = 0x00000030;
2134 cpu->id_pfr1 = 0x00000200;
2135 cpu->isar.id_dfr0 = 0x00100000;
2136 cpu->id_afr0 = 0x00000000;
2137 cpu->isar.id_mmfr0 = 0x00100030;
2138 cpu->isar.id_mmfr1 = 0x00000000;
2139 cpu->isar.id_mmfr2 = 0x01000000;
2140 cpu->isar.id_mmfr3 = 0x00000000;
2141 cpu->isar.id_isar0 = 0x01101110;
2142 cpu->isar.id_isar1 = 0x02112000;
2143 cpu->isar.id_isar2 = 0x20232231;
2144 cpu->isar.id_isar3 = 0x01111131;
2145 cpu->isar.id_isar4 = 0x01310132;
2146 cpu->isar.id_isar5 = 0x00000000;
2147 cpu->isar.id_isar6 = 0x00000000;
2148 }
2149
2150 static void cortex_m33_initfn(Object *obj)
2151 {
2152 ARMCPU *cpu = ARM_CPU(obj);
2153
2154 set_feature(&cpu->env, ARM_FEATURE_V8);
2155 set_feature(&cpu->env, ARM_FEATURE_M);
2156 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
2157 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
2158 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
2159 cpu->midr = 0x410fd213; /* r0p3 */
2160 cpu->pmsav7_dregion = 16;
2161 cpu->sau_sregion = 8;
2162 cpu->isar.mvfr0 = 0x10110021;
2163 cpu->isar.mvfr1 = 0x11000011;
2164 cpu->isar.mvfr2 = 0x00000040;
2165 cpu->id_pfr0 = 0x00000030;
2166 cpu->id_pfr1 = 0x00000210;
2167 cpu->isar.id_dfr0 = 0x00200000;
2168 cpu->id_afr0 = 0x00000000;
2169 cpu->isar.id_mmfr0 = 0x00101F40;
2170 cpu->isar.id_mmfr1 = 0x00000000;
2171 cpu->isar.id_mmfr2 = 0x01000000;
2172 cpu->isar.id_mmfr3 = 0x00000000;
2173 cpu->isar.id_isar0 = 0x01101110;
2174 cpu->isar.id_isar1 = 0x02212000;
2175 cpu->isar.id_isar2 = 0x20232232;
2176 cpu->isar.id_isar3 = 0x01111131;
2177 cpu->isar.id_isar4 = 0x01310132;
2178 cpu->isar.id_isar5 = 0x00000000;
2179 cpu->isar.id_isar6 = 0x00000000;
2180 cpu->clidr = 0x00000000;
2181 cpu->ctr = 0x8000c000;
2182 }
2183
2184 static void arm_v7m_class_init(ObjectClass *oc, void *data)
2185 {
2186 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2187 CPUClass *cc = CPU_CLASS(oc);
2188
2189 acc->info = data;
2190 #ifndef CONFIG_USER_ONLY
2191 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
2192 #endif
2193
2194 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
2195 }
2196
2197 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
2198 /* Dummy the TCM region regs for the moment */
2199 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2200 .access = PL1_RW, .type = ARM_CP_CONST },
2201 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2202 .access = PL1_RW, .type = ARM_CP_CONST },
2203 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
2204 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
2205 REGINFO_SENTINEL
2206 };
2207
2208 static void cortex_r5_initfn(Object *obj)
2209 {
2210 ARMCPU *cpu = ARM_CPU(obj);
2211
2212 set_feature(&cpu->env, ARM_FEATURE_V7);
2213 set_feature(&cpu->env, ARM_FEATURE_V7MP);
2214 set_feature(&cpu->env, ARM_FEATURE_PMSA);
2215 set_feature(&cpu->env, ARM_FEATURE_PMU);
2216 cpu->midr = 0x411fc153; /* r1p3 */
2217 cpu->id_pfr0 = 0x0131;
2218 cpu->id_pfr1 = 0x001;
2219 cpu->isar.id_dfr0 = 0x010400;
2220 cpu->id_afr0 = 0x0;
2221 cpu->isar.id_mmfr0 = 0x0210030;
2222 cpu->isar.id_mmfr1 = 0x00000000;
2223 cpu->isar.id_mmfr2 = 0x01200000;
2224 cpu->isar.id_mmfr3 = 0x0211;
2225 cpu->isar.id_isar0 = 0x02101111;
2226 cpu->isar.id_isar1 = 0x13112111;
2227 cpu->isar.id_isar2 = 0x21232141;
2228 cpu->isar.id_isar3 = 0x01112131;
2229 cpu->isar.id_isar4 = 0x0010142;
2230 cpu->isar.id_isar5 = 0x0;
2231 cpu->isar.id_isar6 = 0x0;
2232 cpu->mp_is_up = true;
2233 cpu->pmsav7_dregion = 16;
2234 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
2235 }
2236
2237 static void cortex_r5f_initfn(Object *obj)
2238 {
2239 ARMCPU *cpu = ARM_CPU(obj);
2240
2241 cortex_r5_initfn(obj);
2242 cpu->isar.mvfr0 = 0x10110221;
2243 cpu->isar.mvfr1 = 0x00000011;
2244 }
2245
2246 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
2247 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
2248 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2249 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2250 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2251 REGINFO_SENTINEL
2252 };
2253
2254 static void cortex_a8_initfn(Object *obj)
2255 {
2256 ARMCPU *cpu = ARM_CPU(obj);
2257
2258 cpu->dtb_compatible = "arm,cortex-a8";
2259 set_feature(&cpu->env, ARM_FEATURE_V7);
2260 set_feature(&cpu->env, ARM_FEATURE_NEON);
2261 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2262 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2263 set_feature(&cpu->env, ARM_FEATURE_EL3);
2264 cpu->midr = 0x410fc080;
2265 cpu->reset_fpsid = 0x410330c0;
2266 cpu->isar.mvfr0 = 0x11110222;
2267 cpu->isar.mvfr1 = 0x00011111;
2268 cpu->ctr = 0x82048004;
2269 cpu->reset_sctlr = 0x00c50078;
2270 cpu->id_pfr0 = 0x1031;
2271 cpu->id_pfr1 = 0x11;
2272 cpu->isar.id_dfr0 = 0x400;
2273 cpu->id_afr0 = 0;
2274 cpu->isar.id_mmfr0 = 0x31100003;
2275 cpu->isar.id_mmfr1 = 0x20000000;
2276 cpu->isar.id_mmfr2 = 0x01202000;
2277 cpu->isar.id_mmfr3 = 0x11;
2278 cpu->isar.id_isar0 = 0x00101111;
2279 cpu->isar.id_isar1 = 0x12112111;
2280 cpu->isar.id_isar2 = 0x21232031;
2281 cpu->isar.id_isar3 = 0x11112131;
2282 cpu->isar.id_isar4 = 0x00111142;
2283 cpu->isar.dbgdidr = 0x15141000;
2284 cpu->clidr = (1 << 27) | (2 << 24) | 3;
2285 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2286 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2287 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2288 cpu->reset_auxcr = 2;
2289 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
2290 }
2291
2292 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
2293 /* power_control should be set to maximum latency. Again,
2294 * default to 0 and set by private hook
2295 */
2296 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2297 .access = PL1_RW, .resetvalue = 0,
2298 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
2299 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
2300 .access = PL1_RW, .resetvalue = 0,
2301 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
2302 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
2303 .access = PL1_RW, .resetvalue = 0,
2304 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
2305 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2306 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2307 /* TLB lockdown control */
2308 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
2309 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2310 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
2311 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2312 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
2313 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2314 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
2315 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2316 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
2317 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2318 REGINFO_SENTINEL
2319 };
2320
2321 static void cortex_a9_initfn(Object *obj)
2322 {
2323 ARMCPU *cpu = ARM_CPU(obj);
2324
2325 cpu->dtb_compatible = "arm,cortex-a9";
2326 set_feature(&cpu->env, ARM_FEATURE_V7);
2327 set_feature(&cpu->env, ARM_FEATURE_NEON);
2328 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2329 set_feature(&cpu->env, ARM_FEATURE_EL3);
2330 /* Note that A9 supports the MP extensions even for
2331 * A9UP and single-core A9MP (which are both different
2332 * and valid configurations; we don't model A9UP).
2333 */
2334 set_feature(&cpu->env, ARM_FEATURE_V7MP);
2335 set_feature(&cpu->env, ARM_FEATURE_CBAR);
2336 cpu->midr = 0x410fc090;
2337 cpu->reset_fpsid = 0x41033090;
2338 cpu->isar.mvfr0 = 0x11110222;
2339 cpu->isar.mvfr1 = 0x01111111;
2340 cpu->ctr = 0x80038003;
2341 cpu->reset_sctlr = 0x00c50078;
2342 cpu->id_pfr0 = 0x1031;
2343 cpu->id_pfr1 = 0x11;
2344 cpu->isar.id_dfr0 = 0x000;
2345 cpu->id_afr0 = 0;
2346 cpu->isar.id_mmfr0 = 0x00100103;
2347 cpu->isar.id_mmfr1 = 0x20000000;
2348 cpu->isar.id_mmfr2 = 0x01230000;
2349 cpu->isar.id_mmfr3 = 0x00002111;
2350 cpu->isar.id_isar0 = 0x00101111;
2351 cpu->isar.id_isar1 = 0x13112111;
2352 cpu->isar.id_isar2 = 0x21232041;
2353 cpu->isar.id_isar3 = 0x11112131;
2354 cpu->isar.id_isar4 = 0x00111142;
2355 cpu->isar.dbgdidr = 0x35141000;
2356 cpu->clidr = (1 << 27) | (1 << 24) | 3;
2357 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2358 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
2359 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
2360 }
2361
2362 #ifndef CONFIG_USER_ONLY
2363 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2364 {
2365 MachineState *ms = MACHINE(qdev_get_machine());
2366
2367 /* Linux wants the number of processors from here.
2368 * Might as well set the interrupt-controller bit too.
2369 */
2370 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
2371 }
2372 #endif
2373
2374 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
2375 #ifndef CONFIG_USER_ONLY
2376 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2377 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
2378 .writefn = arm_cp_write_ignore, },
2379 #endif
2380 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
2381 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2382 REGINFO_SENTINEL
2383 };
2384
2385 static void cortex_a7_initfn(Object *obj)
2386 {
2387 ARMCPU *cpu = ARM_CPU(obj);
2388
2389 cpu->dtb_compatible = "arm,cortex-a7";
2390 set_feature(&cpu->env, ARM_FEATURE_V7VE);
2391 set_feature(&cpu->env, ARM_FEATURE_NEON);
2392 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2393 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2394 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2395 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2396 set_feature(&cpu->env, ARM_FEATURE_EL2);
2397 set_feature(&cpu->env, ARM_FEATURE_EL3);
2398 set_feature(&cpu->env, ARM_FEATURE_PMU);
2399 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
2400 cpu->midr = 0x410fc075;
2401 cpu->reset_fpsid = 0x41023075;
2402 cpu->isar.mvfr0 = 0x10110222;
2403 cpu->isar.mvfr1 = 0x11111111;
2404 cpu->ctr = 0x84448003;
2405 cpu->reset_sctlr = 0x00c50078;
2406 cpu->id_pfr0 = 0x00001131;
2407 cpu->id_pfr1 = 0x00011011;
2408 cpu->isar.id_dfr0 = 0x02010555;
2409 cpu->id_afr0 = 0x00000000;
2410 cpu->isar.id_mmfr0 = 0x10101105;
2411 cpu->isar.id_mmfr1 = 0x40000000;
2412 cpu->isar.id_mmfr2 = 0x01240000;
2413 cpu->isar.id_mmfr3 = 0x02102211;
2414 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2415 * table 4-41 gives 0x02101110, which includes the arm div insns.
2416 */
2417 cpu->isar.id_isar0 = 0x02101110;
2418 cpu->isar.id_isar1 = 0x13112111;
2419 cpu->isar.id_isar2 = 0x21232041;
2420 cpu->isar.id_isar3 = 0x11112131;
2421 cpu->isar.id_isar4 = 0x10011142;
2422 cpu->isar.dbgdidr = 0x3515f005;
2423 cpu->clidr = 0x0a200023;
2424 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2425 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2426 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2427 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2428 }
2429
2430 static void cortex_a15_initfn(Object *obj)
2431 {
2432 ARMCPU *cpu = ARM_CPU(obj);
2433
2434 cpu->dtb_compatible = "arm,cortex-a15";
2435 set_feature(&cpu->env, ARM_FEATURE_V7VE);
2436 set_feature(&cpu->env, ARM_FEATURE_NEON);
2437 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2438 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2439 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2440 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2441 set_feature(&cpu->env, ARM_FEATURE_EL2);
2442 set_feature(&cpu->env, ARM_FEATURE_EL3);
2443 set_feature(&cpu->env, ARM_FEATURE_PMU);
2444 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
2445 cpu->midr = 0x412fc0f1;
2446 cpu->reset_fpsid = 0x410430f0;
2447 cpu->isar.mvfr0 = 0x10110222;
2448 cpu->isar.mvfr1 = 0x11111111;
2449 cpu->ctr = 0x8444c004;
2450 cpu->reset_sctlr = 0x00c50078;
2451 cpu->id_pfr0 = 0x00001131;
2452 cpu->id_pfr1 = 0x00011011;
2453 cpu->isar.id_dfr0 = 0x02010555;
2454 cpu->id_afr0 = 0x00000000;
2455 cpu->isar.id_mmfr0 = 0x10201105;
2456 cpu->isar.id_mmfr1 = 0x20000000;
2457 cpu->isar.id_mmfr2 = 0x01240000;
2458 cpu->isar.id_mmfr3 = 0x02102211;
2459 cpu->isar.id_isar0 = 0x02101110;
2460 cpu->isar.id_isar1 = 0x13112111;
2461 cpu->isar.id_isar2 = 0x21232041;
2462 cpu->isar.id_isar3 = 0x11112131;
2463 cpu->isar.id_isar4 = 0x10011142;
2464 cpu->isar.dbgdidr = 0x3515f021;
2465 cpu->clidr = 0x0a200023;
2466 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2467 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2468 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2469 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
2470 }
2471
2472 static void ti925t_initfn(Object *obj)
2473 {
2474 ARMCPU *cpu = ARM_CPU(obj);
2475 set_feature(&cpu->env, ARM_FEATURE_V4T);
2476 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
2477 cpu->midr = ARM_CPUID_TI925T;
2478 cpu->ctr = 0x5109149;
2479 cpu->reset_sctlr = 0x00000070;
2480 }
2481
2482 static void sa1100_initfn(Object *obj)
2483 {
2484 ARMCPU *cpu = ARM_CPU(obj);
2485
2486 cpu->dtb_compatible = "intel,sa1100";
2487 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
2488 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2489 cpu->midr = 0x4401A11B;
2490 cpu->reset_sctlr = 0x00000070;
2491 }
2492
2493 static void sa1110_initfn(Object *obj)
2494 {
2495 ARMCPU *cpu = ARM_CPU(obj);
2496 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
2497 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2498 cpu->midr = 0x6901B119;
2499 cpu->reset_sctlr = 0x00000070;
2500 }
2501
2502 static void pxa250_initfn(Object *obj)
2503 {
2504 ARMCPU *cpu = ARM_CPU(obj);
2505
2506 cpu->dtb_compatible = "marvell,xscale";
2507 set_feature(&cpu->env, ARM_FEATURE_V5);
2508 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2509 cpu->midr = 0x69052100;
2510 cpu->ctr = 0xd172172;
2511 cpu->reset_sctlr = 0x00000078;
2512 }
2513
2514 static void pxa255_initfn(Object *obj)
2515 {
2516 ARMCPU *cpu = ARM_CPU(obj);
2517
2518 cpu->dtb_compatible = "marvell,xscale";
2519 set_feature(&cpu->env, ARM_FEATURE_V5);
2520 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2521 cpu->midr = 0x69052d00;
2522 cpu->ctr = 0xd172172;
2523 cpu->reset_sctlr = 0x00000078;
2524 }
2525
2526 static void pxa260_initfn(Object *obj)
2527 {
2528 ARMCPU *cpu = ARM_CPU(obj);
2529
2530 cpu->dtb_compatible = "marvell,xscale";
2531 set_feature(&cpu->env, ARM_FEATURE_V5);
2532 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2533 cpu->midr = 0x69052903;
2534 cpu->ctr = 0xd172172;
2535 cpu->reset_sctlr = 0x00000078;
2536 }
2537
2538 static void pxa261_initfn(Object *obj)
2539 {
2540 ARMCPU *cpu = ARM_CPU(obj);
2541
2542 cpu->dtb_compatible = "marvell,xscale";
2543 set_feature(&cpu->env, ARM_FEATURE_V5);
2544 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2545 cpu->midr = 0x69052d05;
2546 cpu->ctr = 0xd172172;
2547 cpu->reset_sctlr = 0x00000078;
2548 }
2549
2550 static void pxa262_initfn(Object *obj)
2551 {
2552 ARMCPU *cpu = ARM_CPU(obj);
2553
2554 cpu->dtb_compatible = "marvell,xscale";
2555 set_feature(&cpu->env, ARM_FEATURE_V5);
2556 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2557 cpu->midr = 0x69052d06;
2558 cpu->ctr = 0xd172172;
2559 cpu->reset_sctlr = 0x00000078;
2560 }
2561
2562 static void pxa270a0_initfn(Object *obj)
2563 {
2564 ARMCPU *cpu = ARM_CPU(obj);
2565
2566 cpu->dtb_compatible = "marvell,xscale";
2567 set_feature(&cpu->env, ARM_FEATURE_V5);
2568 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2569 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2570 cpu->midr = 0x69054110;
2571 cpu->ctr = 0xd172172;
2572 cpu->reset_sctlr = 0x00000078;
2573 }
2574
2575 static void pxa270a1_initfn(Object *obj)
2576 {
2577 ARMCPU *cpu = ARM_CPU(obj);
2578
2579 cpu->dtb_compatible = "marvell,xscale";
2580 set_feature(&cpu->env, ARM_FEATURE_V5);
2581 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2582 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2583 cpu->midr = 0x69054111;
2584 cpu->ctr = 0xd172172;
2585 cpu->reset_sctlr = 0x00000078;
2586 }
2587
2588 static void pxa270b0_initfn(Object *obj)
2589 {
2590 ARMCPU *cpu = ARM_CPU(obj);
2591
2592 cpu->dtb_compatible = "marvell,xscale";
2593 set_feature(&cpu->env, ARM_FEATURE_V5);
2594 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2595 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2596 cpu->midr = 0x69054112;
2597 cpu->ctr = 0xd172172;
2598 cpu->reset_sctlr = 0x00000078;
2599 }
2600
2601 static void pxa270b1_initfn(Object *obj)
2602 {
2603 ARMCPU *cpu = ARM_CPU(obj);
2604
2605 cpu->dtb_compatible = "marvell,xscale";
2606 set_feature(&cpu->env, ARM_FEATURE_V5);
2607 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2608 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2609 cpu->midr = 0x69054113;
2610 cpu->ctr = 0xd172172;
2611 cpu->reset_sctlr = 0x00000078;
2612 }
2613
2614 static void pxa270c0_initfn(Object *obj)
2615 {
2616 ARMCPU *cpu = ARM_CPU(obj);
2617
2618 cpu->dtb_compatible = "marvell,xscale";
2619 set_feature(&cpu->env, ARM_FEATURE_V5);
2620 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2621 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2622 cpu->midr = 0x69054114;
2623 cpu->ctr = 0xd172172;
2624 cpu->reset_sctlr = 0x00000078;
2625 }
2626
2627 static void pxa270c5_initfn(Object *obj)
2628 {
2629 ARMCPU *cpu = ARM_CPU(obj);
2630
2631 cpu->dtb_compatible = "marvell,xscale";
2632 set_feature(&cpu->env, ARM_FEATURE_V5);
2633 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2634 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2635 cpu->midr = 0x69054117;
2636 cpu->ctr = 0xd172172;
2637 cpu->reset_sctlr = 0x00000078;
2638 }
2639
2640 #ifndef TARGET_AARCH64
2641 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2642 * otherwise, a CPU with as many features enabled as our emulation supports.
2643 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2644 * this only needs to handle 32 bits.
2645 */
2646 static void arm_max_initfn(Object *obj)
2647 {
2648 ARMCPU *cpu = ARM_CPU(obj);
2649
2650 if (kvm_enabled()) {
2651 kvm_arm_set_cpu_features_from_host(cpu);
2652 kvm_arm_add_vcpu_properties(obj);
2653 } else {
2654 cortex_a15_initfn(obj);
2655
2656 /* old-style VFP short-vector support */
2657 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
2658
2659 #ifdef CONFIG_USER_ONLY
2660 /* We don't set these in system emulation mode for the moment,
2661 * since we don't correctly set (all of) the ID registers to
2662 * advertise them.
2663 */
2664 set_feature(&cpu->env, ARM_FEATURE_V8);
2665 {
2666 uint32_t t;
2667
2668 t = cpu->isar.id_isar5;
2669 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2670 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2671 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2672 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2673 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2674 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2675 cpu->isar.id_isar5 = t;
2676
2677 t = cpu->isar.id_isar6;
2678 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
2679 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
2680 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
2681 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
2682 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
2683 cpu->isar.id_isar6 = t;
2684
2685 t = cpu->isar.mvfr1;
2686 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
2687 cpu->isar.mvfr1 = t;
2688
2689 t = cpu->isar.mvfr2;
2690 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2691 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
2692 cpu->isar.mvfr2 = t;
2693
2694 t = cpu->isar.id_mmfr3;
2695 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
2696 cpu->isar.id_mmfr3 = t;
2697
2698 t = cpu->isar.id_mmfr4;
2699 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2700 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
2701 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
2702 cpu->isar.id_mmfr4 = t;
2703 }
2704 #endif
2705 }
2706 }
2707 #endif
2708
2709 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2710
2711 struct ARMCPUInfo {
2712 const char *name;
2713 void (*initfn)(Object *obj);
2714 void (*class_init)(ObjectClass *oc, void *data);
2715 };
2716
2717 static const ARMCPUInfo arm_cpus[] = {
2718 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2719 { .name = "arm926", .initfn = arm926_initfn },
2720 { .name = "arm946", .initfn = arm946_initfn },
2721 { .name = "arm1026", .initfn = arm1026_initfn },
2722 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2723 * older core than plain "arm1136". In particular this does not
2724 * have the v6K features.
2725 */
2726 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
2727 { .name = "arm1136", .initfn = arm1136_initfn },
2728 { .name = "arm1176", .initfn = arm1176_initfn },
2729 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
2730 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
2731 .class_init = arm_v7m_class_init },
2732 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
2733 .class_init = arm_v7m_class_init },
2734 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
2735 .class_init = arm_v7m_class_init },
2736 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
2737 .class_init = arm_v7m_class_init },
2738 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
2739 .class_init = arm_v7m_class_init },
2740 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
2741 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
2742 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
2743 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
2744 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
2745 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2746 { .name = "ti925t", .initfn = ti925t_initfn },
2747 { .name = "sa1100", .initfn = sa1100_initfn },
2748 { .name = "sa1110", .initfn = sa1110_initfn },
2749 { .name = "pxa250", .initfn = pxa250_initfn },
2750 { .name = "pxa255", .initfn = pxa255_initfn },
2751 { .name = "pxa260", .initfn = pxa260_initfn },
2752 { .name = "pxa261", .initfn = pxa261_initfn },
2753 { .name = "pxa262", .initfn = pxa262_initfn },
2754 /* "pxa270" is an alias for "pxa270-a0" */
2755 { .name = "pxa270", .initfn = pxa270a0_initfn },
2756 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
2757 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
2758 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
2759 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
2760 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
2761 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
2762 #ifndef TARGET_AARCH64
2763 { .name = "max", .initfn = arm_max_initfn },
2764 #endif
2765 #ifdef CONFIG_USER_ONLY
2766 { .name = "any", .initfn = arm_max_initfn },
2767 #endif
2768 #endif
2769 { .name = NULL }
2770 };
2771
2772 static Property arm_cpu_properties[] = {
2773 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
2774 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2775 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
2776 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2777 mp_affinity, ARM64_AFFINITY_INVALID),
2778 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2779 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2780 DEFINE_PROP_END_OF_LIST()
2781 };
2782
2783 static gchar *arm_gdb_arch_name(CPUState *cs)
2784 {
2785 ARMCPU *cpu = ARM_CPU(cs);
2786 CPUARMState *env = &cpu->env;
2787
2788 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2789 return g_strdup("iwmmxt");
2790 }
2791 return g_strdup("arm");
2792 }
2793
2794 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2795 {
2796 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2797 CPUClass *cc = CPU_CLASS(acc);
2798 DeviceClass *dc = DEVICE_CLASS(oc);
2799
2800 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2801 &acc->parent_realize);
2802
2803 device_class_set_props(dc, arm_cpu_properties);
2804 cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset);
2805
2806 cc->class_by_name = arm_cpu_class_by_name;
2807 cc->has_work = arm_cpu_has_work;
2808 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2809 cc->dump_state = arm_cpu_dump_state;
2810 cc->set_pc = arm_cpu_set_pc;
2811 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
2812 cc->gdb_read_register = arm_cpu_gdb_read_register;
2813 cc->gdb_write_register = arm_cpu_gdb_write_register;
2814 #ifndef CONFIG_USER_ONLY
2815 cc->do_interrupt = arm_cpu_do_interrupt;
2816 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2817 cc->asidx_from_attrs = arm_asidx_from_attrs;
2818 cc->vmsd = &vmstate_arm_cpu;
2819 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2820 cc->write_elf64_note = arm_cpu_write_elf64_note;
2821 cc->write_elf32_note = arm_cpu_write_elf32_note;
2822 #endif
2823 cc->gdb_num_core_regs = 26;
2824 cc->gdb_core_xml_file = "arm-core.xml";
2825 cc->gdb_arch_name = arm_gdb_arch_name;
2826 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2827 cc->gdb_stop_before_watchpoint = true;
2828 cc->disas_set_info = arm_disas_set_info;
2829 #ifdef CONFIG_TCG
2830 cc->tcg_initialize = arm_translate_init;
2831 cc->tlb_fill = arm_cpu_tlb_fill;
2832 cc->debug_excp_handler = arm_debug_excp_handler;
2833 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2834 #if !defined(CONFIG_USER_ONLY)
2835 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2836 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2837 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2838 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2839 #endif
2840 }
2841
2842 #ifdef CONFIG_KVM
2843 static void arm_host_initfn(Object *obj)
2844 {
2845 ARMCPU *cpu = ARM_CPU(obj);
2846
2847 kvm_arm_set_cpu_features_from_host(cpu);
2848 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2849 aarch64_add_sve_properties(obj);
2850 }
2851 kvm_arm_add_vcpu_properties(obj);
2852 arm_cpu_post_init(obj);
2853 }
2854
2855 static const TypeInfo host_arm_cpu_type_info = {
2856 .name = TYPE_ARM_HOST_CPU,
2857 #ifdef TARGET_AARCH64
2858 .parent = TYPE_AARCH64_CPU,
2859 #else
2860 .parent = TYPE_ARM_CPU,
2861 #endif
2862 .instance_init = arm_host_initfn,
2863 };
2864
2865 #endif
2866
2867 static void arm_cpu_instance_init(Object *obj)
2868 {
2869 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2870
2871 acc->info->initfn(obj);
2872 arm_cpu_post_init(obj);
2873 }
2874
2875 static void cpu_register_class_init(ObjectClass *oc, void *data)
2876 {
2877 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2878
2879 acc->info = data;
2880 }
2881
2882 static void cpu_register(const ARMCPUInfo *info)
2883 {
2884 TypeInfo type_info = {
2885 .parent = TYPE_ARM_CPU,
2886 .instance_size = sizeof(ARMCPU),
2887 .instance_init = arm_cpu_instance_init,
2888 .class_size = sizeof(ARMCPUClass),
2889 .class_init = info->class_init ?: cpu_register_class_init,
2890 .class_data = (void *)info,
2891 };
2892
2893 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2894 type_register(&type_info);
2895 g_free((void *)type_info.name);
2896 }
2897
2898 static const TypeInfo arm_cpu_type_info = {
2899 .name = TYPE_ARM_CPU,
2900 .parent = TYPE_CPU,
2901 .instance_size = sizeof(ARMCPU),
2902 .instance_init = arm_cpu_initfn,
2903 .instance_finalize = arm_cpu_finalizefn,
2904 .abstract = true,
2905 .class_size = sizeof(ARMCPUClass),
2906 .class_init = arm_cpu_class_init,
2907 };
2908
2909 static const TypeInfo idau_interface_type_info = {
2910 .name = TYPE_IDAU_INTERFACE,
2911 .parent = TYPE_INTERFACE,
2912 .class_size = sizeof(IDAUInterfaceClass),
2913 };
2914
2915 static void arm_cpu_register_types(void)
2916 {
2917 const ARMCPUInfo *info = arm_cpus;
2918
2919 type_register_static(&arm_cpu_type_info);
2920 type_register_static(&idau_interface_type_info);
2921
2922 while (info->name) {
2923 cpu_register(info);
2924 info++;
2925 }
2926
2927 #ifdef CONFIG_KVM
2928 type_register_static(&host_arm_cpu_type_info);
2929 #endif
2930 }
2931
2932 type_init(arm_cpu_register_types)
AR7 emulation for QEMU