target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) cpu_##insn##_data(env, addr);                         \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lw, ldl, int32_t)
  94 #if defined(TARGET_MIPS64)
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     cpu_##insn##_data(env, addr, val);                                  \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #if defined(TARGET_MIPS64)
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 static inline target_ulong bitswap(target_ulong v)
 269 {
 270     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 271               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 272     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 273               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 274     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 275               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 276     return v;
 277 }
 278
 279 #ifdef TARGET_MIPS64
 280 target_ulong helper_dbitswap(target_ulong rt)
 281 {
 282     return bitswap(rt);
 283 }
 284 #endif
 285
 286 target_ulong helper_bitswap(target_ulong rt)
 287 {
 288     return (int32_t)bitswap(rt);
 289 }
 290
 291 #ifndef CONFIG_USER_ONLY
 292
 293 static inline hwaddr do_translate_address(CPUMIPSState *env,
 294                                                       target_ulong address,
 295                                                       int rw)
 296 {
 297     hwaddr lladdr;
 298
 299     lladdr = cpu_mips_translate_address(env, address, rw);
 300
 301     if (lladdr == -1LL) {
 302         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 303     } else {
 304         return lladdr;
 305     }
 306 }
 307
 308 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 310 {                                                                             \
 311     if (arg & almask) {                                                       \
 312         env->CP0_BadVAddr = arg;                                              \
 313         helper_raise_exception(env, EXCP_AdEL);                               \
 314     }                                                                         \
 315     env->lladdr = do_translate_address(env, arg, 0);                          \
 316     env->llval = do_##insn(env, arg, mem_idx);                                \
 317     return env->llval;                                                        \
 318 }
 319 HELPER_LD_ATOMIC(ll, lw, 0x3)
 320 #ifdef TARGET_MIPS64
 321 HELPER_LD_ATOMIC(lld, ld, 0x7)
 322 #endif
 323 #undef HELPER_LD_ATOMIC
 324
 325 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 326 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 327                            target_ulong arg2, int mem_idx)                    \
 328 {                                                                             \
 329     target_long tmp;                                                          \
 330                                                                               \
 331     if (arg2 & almask) {                                                      \
 332         env->CP0_BadVAddr = arg2;                                             \
 333         helper_raise_exception(env, EXCP_AdES);                               \
 334     }                                                                         \
 335     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 336         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 337         if (tmp == env->llval) {                                              \
 338             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 339             return 1;                                                         \
 340         }                                                                     \
 341     }                                                                         \
 342     return 0;                                                                 \
 343 }
 344 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 345 #ifdef TARGET_MIPS64
 346 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 347 #endif
 348 #undef HELPER_ST_ATOMIC
 349 #endif
 350
 351 #ifdef TARGET_WORDS_BIGENDIAN
 352 #define GET_LMASK(v) ((v) & 3)
 353 #define GET_OFFSET(addr, offset) (addr + (offset))
 354 #else
 355 #define GET_LMASK(v) (((v) & 3) ^ 3)
 356 #define GET_OFFSET(addr, offset) (addr - (offset))
 357 #endif
 358
 359 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 360                 int mem_idx)
 361 {
 362     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 363
 364     if (GET_LMASK(arg2) <= 2)
 365         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 366
 367     if (GET_LMASK(arg2) <= 1)
 368         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 369
 370     if (GET_LMASK(arg2) == 0)
 371         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 372 }
 373
 374 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 375                 int mem_idx)
 376 {
 377     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 378
 379     if (GET_LMASK(arg2) >= 1)
 380         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 381
 382     if (GET_LMASK(arg2) >= 2)
 383         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 384
 385     if (GET_LMASK(arg2) == 3)
 386         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 387 }
 388
 389 #if defined(TARGET_MIPS64)
 390 /* "half" load and stores.  We must do the memory access inline,
 391    or fault handling won't work.  */
 392
 393 #ifdef TARGET_WORDS_BIGENDIAN
 394 #define GET_LMASK64(v) ((v) & 7)
 395 #else
 396 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 397 #endif
 398
 399 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 400                 int mem_idx)
 401 {
 402     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 403
 404     if (GET_LMASK64(arg2) <= 6)
 405         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 406
 407     if (GET_LMASK64(arg2) <= 5)
 408         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 409
 410     if (GET_LMASK64(arg2) <= 4)
 411         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 412
 413     if (GET_LMASK64(arg2) <= 3)
 414         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 415
 416     if (GET_LMASK64(arg2) <= 2)
 417         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 418
 419     if (GET_LMASK64(arg2) <= 1)
 420         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 421
 422     if (GET_LMASK64(arg2) <= 0)
 423         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 424 }
 425
 426 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 427                 int mem_idx)
 428 {
 429     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 430
 431     if (GET_LMASK64(arg2) >= 1)
 432         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 433
 434     if (GET_LMASK64(arg2) >= 2)
 435         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 436
 437     if (GET_LMASK64(arg2) >= 3)
 438         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 439
 440     if (GET_LMASK64(arg2) >= 4)
 441         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 442
 443     if (GET_LMASK64(arg2) >= 5)
 444         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 445
 446     if (GET_LMASK64(arg2) >= 6)
 447         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 448
 449     if (GET_LMASK64(arg2) == 7)
 450         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 451 }
 452 #endif /* TARGET_MIPS64 */
 453
 454 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 455
 456 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 457                 uint32_t mem_idx)
 458 {
 459     target_ulong base_reglist = reglist & 0xf;
 460     target_ulong do_r31 = reglist & 0x10;
 461
 462     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 463         target_ulong i;
 464
 465         for (i = 0; i < base_reglist; i++) {
 466             env->active_tc.gpr[multiple_regs[i]] =
 467                 (target_long)do_lw(env, addr, mem_idx);
 468             addr += 4;
 469         }
 470     }
 471
 472     if (do_r31) {
 473         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 474     }
 475 }
 476
 477 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 478                 uint32_t mem_idx)
 479 {
 480     target_ulong base_reglist = reglist & 0xf;
 481     target_ulong do_r31 = reglist & 0x10;
 482
 483     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 484         target_ulong i;
 485
 486         for (i = 0; i < base_reglist; i++) {
 487             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 488             addr += 4;
 489         }
 490     }
 491
 492     if (do_r31) {
 493         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 494     }
 495 }
 496
 497 #if defined(TARGET_MIPS64)
 498 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 499                 uint32_t mem_idx)
 500 {
 501     target_ulong base_reglist = reglist & 0xf;
 502     target_ulong do_r31 = reglist & 0x10;
 503
 504     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 505         target_ulong i;
 506
 507         for (i = 0; i < base_reglist; i++) {
 508             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 509             addr += 8;
 510         }
 511     }
 512
 513     if (do_r31) {
 514         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 515     }
 516 }
 517
 518 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 519                 uint32_t mem_idx)
 520 {
 521     target_ulong base_reglist = reglist & 0xf;
 522     target_ulong do_r31 = reglist & 0x10;
 523
 524     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 525         target_ulong i;
 526
 527         for (i = 0; i < base_reglist; i++) {
 528             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 529             addr += 8;
 530         }
 531     }
 532
 533     if (do_r31) {
 534         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 535     }
 536 }
 537 #endif
 538
 539 #ifndef CONFIG_USER_ONLY
 540 /* SMP helpers.  */
 541 static bool mips_vpe_is_wfi(MIPSCPU *c)
 542 {
 543     CPUState *cpu = CPU(c);
 544     CPUMIPSState *env = &c->env;
 545
 546     /* If the VPE is halted but otherwise active, it means it's waiting for
 547        an interrupt.  */
 548     return cpu->halted && mips_vpe_active(env);
 549 }
 550
 551 static inline void mips_vpe_wake(MIPSCPU *c)
 552 {
 553     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 554        because there might be other conditions that state that c should
 555        be sleeping.  */
 556     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 557 }
 558
 559 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 560 {
 561     CPUState *cs = CPU(cpu);
 562
 563     /* The VPE was shut off, really go to bed.
 564        Reset any old _WAKE requests.  */
 565     cs->halted = 1;
 566     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 567 }
 568
 569 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 570 {
 571     CPUMIPSState *c = &cpu->env;
 572
 573     /* FIXME: TC reschedule.  */
 574     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 575         mips_vpe_wake(cpu);
 576     }
 577 }
 578
 579 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 580 {
 581     CPUMIPSState *c = &cpu->env;
 582
 583     /* FIXME: TC reschedule.  */
 584     if (!mips_vpe_active(c)) {
 585         mips_vpe_sleep(cpu);
 586     }
 587 }
 588
 589 /**
 590  * mips_cpu_map_tc:
 591  * @env: CPU from which mapping is performed.
 592  * @tc: Should point to an int with the value of the global TC index.
 593  *
 594  * This function will transform @tc into a local index within the
 595  * returned #CPUMIPSState.
 596  */
 597 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 598           which depends on runtime setup. Can probably be fixed by
 599           walking the list of CPUMIPSStates.  */
 600 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 601 {
 602     MIPSCPU *cpu;
 603     CPUState *cs;
 604     CPUState *other_cs;
 605     int vpe_idx;
 606     int tc_idx = *tc;
 607
 608     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 609         /* Not allowed to address other CPUs.  */
 610         *tc = env->current_tc;
 611         return env;
 612     }
 613
 614     cs = CPU(mips_env_get_cpu(env));
 615     vpe_idx = tc_idx / cs->nr_threads;
 616     *tc = tc_idx % cs->nr_threads;
 617     other_cs = qemu_get_cpu(vpe_idx);
 618     if (other_cs == NULL) {
 619         return env;
 620     }
 621     cpu = MIPS_CPU(other_cs);
 622     return &cpu->env;
 623 }
 624
 625 /* The per VPE CP0_Status register shares some fields with the per TC
 626    CP0_TCStatus registers. These fields are wired to the same registers,
 627    so changes to either of them should be reflected on both registers.
 628
 629    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 630
 631    These helper call synchronizes the regs for a given cpu.  */
 632
 633 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 634 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 635                                      int tc);  */
 636
 637 /* Called for updates to CP0_TCStatus.  */
 638 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 639                              target_ulong v)
 640 {
 641     uint32_t status;
 642     uint32_t tcu, tmx, tasid, tksu;
 643     uint32_t mask = ((1U << CP0St_CU3)
 644                        | (1 << CP0St_CU2)
 645                        | (1 << CP0St_CU1)
 646                        | (1 << CP0St_CU0)
 647                        | (1 << CP0St_MX)
 648                        | (3 << CP0St_KSU));
 649
 650     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 651     tmx = (v >> CP0TCSt_TMX) & 0x1;
 652     tasid = v & 0xff;
 653     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 654
 655     status = tcu << CP0St_CU0;
 656     status |= tmx << CP0St_MX;
 657     status |= tksu << CP0St_KSU;
 658
 659     cpu->CP0_Status &= ~mask;
 660     cpu->CP0_Status |= status;
 661
 662     /* Sync the TASID with EntryHi.  */
 663     cpu->CP0_EntryHi &= ~0xff;
 664     cpu->CP0_EntryHi = tasid;
 665
 666     compute_hflags(cpu);
 667 }
 668
 669 /* Called for updates to CP0_EntryHi.  */
 670 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 671 {
 672     int32_t *tcst;
 673     uint32_t asid, v = cpu->CP0_EntryHi;
 674
 675     asid = v & 0xff;
 676
 677     if (tc == cpu->current_tc) {
 678         tcst = &cpu->active_tc.CP0_TCStatus;
 679     } else {
 680         tcst = &cpu->tcs[tc].CP0_TCStatus;
 681     }
 682
 683     *tcst &= ~0xff;
 684     *tcst |= asid;
 685 }
 686
 687 /* CP0 helpers */
 688 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 689 {
 690     return env->mvp->CP0_MVPControl;
 691 }
 692
 693 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 694 {
 695     return env->mvp->CP0_MVPConf0;
 696 }
 697
 698 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 699 {
 700     return env->mvp->CP0_MVPConf1;
 701 }
 702
 703 target_ulong helper_mfc0_random(CPUMIPSState *env)
 704 {
 705     return (int32_t)cpu_mips_get_random(env);
 706 }
 707
 708 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 709 {
 710     return env->active_tc.CP0_TCStatus;
 711 }
 712
 713 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 714 {
 715     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 716     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 717
 718     if (other_tc == other->current_tc)
 719         return other->active_tc.CP0_TCStatus;
 720     else
 721         return other->tcs[other_tc].CP0_TCStatus;
 722 }
 723
 724 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 725 {
 726     return env->active_tc.CP0_TCBind;
 727 }
 728
 729 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 730 {
 731     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 732     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 733
 734     if (other_tc == other->current_tc)
 735         return other->active_tc.CP0_TCBind;
 736     else
 737         return other->tcs[other_tc].CP0_TCBind;
 738 }
 739
 740 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 741 {
 742     return env->active_tc.PC;
 743 }
 744
 745 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 746 {
 747     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 748     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 749
 750     if (other_tc == other->current_tc)
 751         return other->active_tc.PC;
 752     else
 753         return other->tcs[other_tc].PC;
 754 }
 755
 756 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 757 {
 758     return env->active_tc.CP0_TCHalt;
 759 }
 760
 761 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 762 {
 763     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 764     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 765
 766     if (other_tc == other->current_tc)
 767         return other->active_tc.CP0_TCHalt;
 768     else
 769         return other->tcs[other_tc].CP0_TCHalt;
 770 }
 771
 772 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 773 {
 774     return env->active_tc.CP0_TCContext;
 775 }
 776
 777 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 778 {
 779     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 780     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 781
 782     if (other_tc == other->current_tc)
 783         return other->active_tc.CP0_TCContext;
 784     else
 785         return other->tcs[other_tc].CP0_TCContext;
 786 }
 787
 788 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 789 {
 790     return env->active_tc.CP0_TCSchedule;
 791 }
 792
 793 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 794 {
 795     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 796     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 797
 798     if (other_tc == other->current_tc)
 799         return other->active_tc.CP0_TCSchedule;
 800     else
 801         return other->tcs[other_tc].CP0_TCSchedule;
 802 }
 803
 804 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 805 {
 806     return env->active_tc.CP0_TCScheFBack;
 807 }
 808
 809 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 810 {
 811     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 812     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 813
 814     if (other_tc == other->current_tc)
 815         return other->active_tc.CP0_TCScheFBack;
 816     else
 817         return other->tcs[other_tc].CP0_TCScheFBack;
 818 }
 819
 820 target_ulong helper_mfc0_count(CPUMIPSState *env)
 821 {
 822     return (int32_t)cpu_mips_get_count(env);
 823 }
 824
 825 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 826 {
 827     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 828     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 829
 830     return other->CP0_EntryHi;
 831 }
 832
 833 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 834 {
 835     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 836     int32_t tccause;
 837     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 838
 839     if (other_tc == other->current_tc) {
 840         tccause = other->CP0_Cause;
 841     } else {
 842         tccause = other->CP0_Cause;
 843     }
 844
 845     return tccause;
 846 }
 847
 848 target_ulong helper_mftc0_status(CPUMIPSState *env)
 849 {
 850     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 851     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 852
 853     return other->CP0_Status;
 854 }
 855
 856 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 857 {
 858     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 859 }
 860
 861 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 862 {
 863     return (int32_t)env->CP0_WatchLo[sel];
 864 }
 865
 866 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 867 {
 868     return env->CP0_WatchHi[sel];
 869 }
 870
 871 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 872 {
 873     target_ulong t0 = env->CP0_Debug;
 874     if (env->hflags & MIPS_HFLAG_DM)
 875         t0 |= 1 << CP0DB_DM;
 876
 877     return t0;
 878 }
 879
 880 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 881 {
 882     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 883     int32_t tcstatus;
 884     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 885
 886     if (other_tc == other->current_tc)
 887         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 888     else
 889         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 890
 891     /* XXX: Might be wrong, check with EJTAG spec. */
 892     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 893             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 894 }
 895
 896 #if defined(TARGET_MIPS64)
 897 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 898 {
 899     return env->active_tc.PC;
 900 }
 901
 902 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 903 {
 904     return env->active_tc.CP0_TCHalt;
 905 }
 906
 907 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 908 {
 909     return env->active_tc.CP0_TCContext;
 910 }
 911
 912 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 913 {
 914     return env->active_tc.CP0_TCSchedule;
 915 }
 916
 917 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 918 {
 919     return env->active_tc.CP0_TCScheFBack;
 920 }
 921
 922 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 923 {
 924     return env->lladdr >> env->CP0_LLAddr_shift;
 925 }
 926
 927 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 928 {
 929     return env->CP0_WatchLo[sel];
 930 }
 931 #endif /* TARGET_MIPS64 */
 932
 933 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 934 {
 935     uint32_t index_p = env->CP0_Index & 0x80000000;
 936     uint32_t tlb_index = arg1 & 0x7fffffff;
 937     if (tlb_index < env->tlb->nb_tlb) {
 938         if (env->insn_flags & ISA_MIPS32R6) {
 939             index_p |= arg1 & 0x80000000;
 940         }
 941         env->CP0_Index = index_p | tlb_index;
 942     }
 943 }
 944
 945 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 946 {
 947     uint32_t mask = 0;
 948     uint32_t newval;
 949
 950     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 951         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 952                 (1 << CP0MVPCo_EVP);
 953     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 954         mask |= (1 << CP0MVPCo_STLB);
 955     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 956
 957     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 958
 959     env->mvp->CP0_MVPControl = newval;
 960 }
 961
 962 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 963 {
 964     uint32_t mask;
 965     uint32_t newval;
 966
 967     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 968            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 969     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 970
 971     /* Yield scheduler intercept not implemented. */
 972     /* Gating storage scheduler intercept not implemented. */
 973
 974     // TODO: Enable/disable TCs.
 975
 976     env->CP0_VPEControl = newval;
 977 }
 978
 979 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 980 {
 981     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 982     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 983     uint32_t mask;
 984     uint32_t newval;
 985
 986     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 987            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 988     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 989
 990     /* TODO: Enable/disable TCs.  */
 991
 992     other->CP0_VPEControl = newval;
 993 }
 994
 995 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 996 {
 997     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 998     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 999     /* FIXME: Mask away return zero on read bits.  */
1000     return other->CP0_VPEControl;
1001 }
1002
1003 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1004 {
1005     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007
1008     return other->CP0_VPEConf0;
1009 }
1010
1011 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1012 {
1013     uint32_t mask = 0;
1014     uint32_t newval;
1015
1016     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1017         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1018             mask |= (0xff << CP0VPEC0_XTC);
1019         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1020     }
1021     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1022
1023     // TODO: TC exclusive handling due to ERL/EXL.
1024
1025     env->CP0_VPEConf0 = newval;
1026 }
1027
1028 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1029 {
1030     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1031     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1032     uint32_t mask = 0;
1033     uint32_t newval;
1034
1035     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1036     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1037
1038     /* TODO: TC exclusive handling due to ERL/EXL.  */
1039     other->CP0_VPEConf0 = newval;
1040 }
1041
1042 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1043 {
1044     uint32_t mask = 0;
1045     uint32_t newval;
1046
1047     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1048         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1049                 (0xff << CP0VPEC1_NCP1);
1050     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1051
1052     /* UDI not implemented. */
1053     /* CP2 not implemented. */
1054
1055     // TODO: Handle FPU (CP1) binding.
1056
1057     env->CP0_VPEConf1 = newval;
1058 }
1059
1060 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1061 {
1062     /* Yield qualifier inputs not implemented. */
1063     env->CP0_YQMask = 0x00000000;
1064 }
1065
1066 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1067 {
1068     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1069 }
1070
1071 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1072
1073 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1074 {
1075     /* 1k pages not implemented */
1076     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1077     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1078                         | (rxi << (CP0EnLo_XI - 30));
1079 }
1080
1081 #if defined(TARGET_MIPS64)
1082 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1083
1084 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1085 {
1086     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1087     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1088 }
1089 #endif
1090
1091 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1092 {
1093     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1094     uint32_t newval;
1095
1096     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1097
1098     env->active_tc.CP0_TCStatus = newval;
1099     sync_c0_tcstatus(env, env->current_tc, newval);
1100 }
1101
1102 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1103 {
1104     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1105     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1106
1107     if (other_tc == other->current_tc)
1108         other->active_tc.CP0_TCStatus = arg1;
1109     else
1110         other->tcs[other_tc].CP0_TCStatus = arg1;
1111     sync_c0_tcstatus(other, other_tc, arg1);
1112 }
1113
1114 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1115 {
1116     uint32_t mask = (1 << CP0TCBd_TBE);
1117     uint32_t newval;
1118
1119     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1120         mask |= (1 << CP0TCBd_CurVPE);
1121     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1122     env->active_tc.CP0_TCBind = newval;
1123 }
1124
1125 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1126 {
1127     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1128     uint32_t mask = (1 << CP0TCBd_TBE);
1129     uint32_t newval;
1130     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1131
1132     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1133         mask |= (1 << CP0TCBd_CurVPE);
1134     if (other_tc == other->current_tc) {
1135         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1136         other->active_tc.CP0_TCBind = newval;
1137     } else {
1138         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1139         other->tcs[other_tc].CP0_TCBind = newval;
1140     }
1141 }
1142
1143 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1144 {
1145     env->active_tc.PC = arg1;
1146     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1147     env->lladdr = 0ULL;
1148     /* MIPS16 not implemented. */
1149 }
1150
1151 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1152 {
1153     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1154     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1155
1156     if (other_tc == other->current_tc) {
1157         other->active_tc.PC = arg1;
1158         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159         other->lladdr = 0ULL;
1160         /* MIPS16 not implemented. */
1161     } else {
1162         other->tcs[other_tc].PC = arg1;
1163         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1164         other->lladdr = 0ULL;
1165         /* MIPS16 not implemented. */
1166     }
1167 }
1168
1169 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1170 {
1171     MIPSCPU *cpu = mips_env_get_cpu(env);
1172
1173     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1174
1175     // TODO: Halt TC / Restart (if allocated+active) TC.
1176     if (env->active_tc.CP0_TCHalt & 1) {
1177         mips_tc_sleep(cpu, env->current_tc);
1178     } else {
1179         mips_tc_wake(cpu, env->current_tc);
1180     }
1181 }
1182
1183 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1184 {
1185     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1186     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1187     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1188
1189     // TODO: Halt TC / Restart (if allocated+active) TC.
1190
1191     if (other_tc == other->current_tc)
1192         other->active_tc.CP0_TCHalt = arg1;
1193     else
1194         other->tcs[other_tc].CP0_TCHalt = arg1;
1195
1196     if (arg1 & 1) {
1197         mips_tc_sleep(other_cpu, other_tc);
1198     } else {
1199         mips_tc_wake(other_cpu, other_tc);
1200     }
1201 }
1202
1203 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205     env->active_tc.CP0_TCContext = arg1;
1206 }
1207
1208 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1209 {
1210     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1211     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1212
1213     if (other_tc == other->current_tc)
1214         other->active_tc.CP0_TCContext = arg1;
1215     else
1216         other->tcs[other_tc].CP0_TCContext = arg1;
1217 }
1218
1219 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221     env->active_tc.CP0_TCSchedule = arg1;
1222 }
1223
1224 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1225 {
1226     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1227     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1228
1229     if (other_tc == other->current_tc)
1230         other->active_tc.CP0_TCSchedule = arg1;
1231     else
1232         other->tcs[other_tc].CP0_TCSchedule = arg1;
1233 }
1234
1235 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237     env->active_tc.CP0_TCScheFBack = arg1;
1238 }
1239
1240 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1241 {
1242     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1243     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1244
1245     if (other_tc == other->current_tc)
1246         other->active_tc.CP0_TCScheFBack = arg1;
1247     else
1248         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1249 }
1250
1251 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1252 {
1253     /* 1k pages not implemented */
1254     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1255     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1256                         | (rxi << (CP0EnLo_XI - 30));
1257 }
1258
1259 #if defined(TARGET_MIPS64)
1260 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1261 {
1262     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1263     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1264 }
1265 #endif
1266
1267 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1270 }
1271
1272 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1273 {
1274     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1275     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1276         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1277          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1278          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1279         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1280     }
1281 }
1282
1283 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1284 {
1285     /* SmartMIPS not implemented */
1286     /* 1k pages not implemented */
1287     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1288                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1289     compute_hflags(env);
1290     restore_pamask(env);
1291 }
1292
1293 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1294 {
1295     if (env->insn_flags & ISA_MIPS32R6) {
1296         if (arg1 < env->tlb->nb_tlb) {
1297             env->CP0_Wired = arg1;
1298         }
1299     } else {
1300         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1301     }
1302 }
1303
1304 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1305 {
1306     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1307 }
1308
1309 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1310 {
1311     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1312 }
1313
1314 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1315 {
1316     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1317 }
1318
1319 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1320 {
1321     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1322 }
1323
1324 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1325 {
1326     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1327 }
1328
1329 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1330 {
1331     uint32_t mask = 0x0000000F;
1332
1333     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1334         mask |= (1 << 29);
1335
1336         if (arg1 & (1 << 29)) {
1337             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1338         } else {
1339             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1340         }
1341     }
1342
1343     env->CP0_HWREna = arg1 & mask;
1344 }
1345
1346 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1347 {
1348     cpu_mips_store_count(env, arg1);
1349 }
1350
1351 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1352 {
1353     target_ulong old, val, mask;
1354     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1355     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1356         mask |= 1 << CP0EnHi_EHINV;
1357     }
1358
1359     /* 1k pages not implemented */
1360 #if defined(TARGET_MIPS64)
1361     if (env->insn_flags & ISA_MIPS32R6) {
1362         int entryhi_r = extract64(arg1, 62, 2);
1363         int config0_at = extract32(env->CP0_Config0, 13, 2);
1364         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1365         if ((entryhi_r == 2) ||
1366             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1367             /* skip EntryHi.R field if new value is reserved */
1368             mask &= ~(0x3ull << 62);
1369         }
1370     }
1371     mask &= env->SEGMask;
1372 #endif
1373     old = env->CP0_EntryHi;
1374     val = (arg1 & mask) | (old & ~mask);
1375     env->CP0_EntryHi = val;
1376     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1377         sync_c0_entryhi(env, env->current_tc);
1378     }
1379     /* If the ASID changes, flush qemu's TLB.  */
1380     if ((old & 0xFF) != (val & 0xFF))
1381         cpu_mips_tlb_flush(env, 1);
1382 }
1383
1384 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1385 {
1386     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1387     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1388
1389     other->CP0_EntryHi = arg1;
1390     sync_c0_entryhi(other, other_tc);
1391 }
1392
1393 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1394 {
1395     cpu_mips_store_compare(env, arg1);
1396 }
1397
1398 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1399 {
1400     MIPSCPU *cpu = mips_env_get_cpu(env);
1401     uint32_t val, old;
1402
1403     old = env->CP0_Status;
1404     cpu_mips_store_status(env, arg1);
1405     val = env->CP0_Status;
1406
1407     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1408         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1409                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1410                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1411                 env->CP0_Cause);
1412         switch (env->hflags & MIPS_HFLAG_KSU) {
1413         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1414         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1415         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1416         default:
1417             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1418             break;
1419         }
1420     }
1421 }
1422
1423 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1424 {
1425     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1427     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1428
1429     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1430     sync_c0_status(env, other, other_tc);
1431 }
1432
1433 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1434 {
1435     /* vectored interrupts not implemented, no performance counters. */
1436     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1437 }
1438
1439 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1440 {
1441     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1442     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1443 }
1444
1445 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1446 {
1447     cpu_mips_store_cause(env, arg1);
1448 }
1449
1450 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1451 {
1452     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1453     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1454
1455     cpu_mips_store_cause(other, arg1);
1456 }
1457
1458 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1459 {
1460     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1461     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1462
1463     return other->CP0_EPC;
1464 }
1465
1466 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1467 {
1468     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1469     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1470
1471     return other->CP0_EBase;
1472 }
1473
1474 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1475 {
1476     /* vectored interrupts not implemented */
1477     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1478 }
1479
1480 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1481 {
1482     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1483     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1484     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1485 }
1486
1487 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1488 {
1489     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1490     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1491
1492     switch (idx) {
1493     case 0: return other->CP0_Config0;
1494     case 1: return other->CP0_Config1;
1495     case 2: return other->CP0_Config2;
1496     case 3: return other->CP0_Config3;
1497     /* 4 and 5 are reserved.  */
1498     case 6: return other->CP0_Config6;
1499     case 7: return other->CP0_Config7;
1500     default:
1501         break;
1502     }
1503     return 0;
1504 }
1505
1506 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1507 {
1508     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1509 }
1510
1511 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1512 {
1513     /* tertiary/secondary caches not implemented */
1514     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1515 }
1516
1517 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1518 {
1519     if (env->insn_flags & ASE_MICROMIPS) {
1520         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1521                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1522     }
1523 }
1524
1525 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1526 {
1527     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1528                        (arg1 & env->CP0_Config4_rw_bitmask);
1529 }
1530
1531 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1532 {
1533     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1534                        (arg1 & env->CP0_Config5_rw_bitmask);
1535     compute_hflags(env);
1536 }
1537
1538 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1539 {
1540     target_long mask = env->CP0_LLAddr_rw_bitmask;
1541     arg1 = arg1 << env->CP0_LLAddr_shift;
1542     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1543 }
1544
1545 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1546 {
1547     /* Watch exceptions for instructions, data loads, data stores
1548        not implemented. */
1549     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1550 }
1551
1552 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1553 {
1554     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1555     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1556 }
1557
1558 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1559 {
1560     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1561     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1562 }
1563
1564 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1565 {
1566     env->CP0_Framemask = arg1; /* XXX */
1567 }
1568
1569 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1570 {
1571     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1572     if (arg1 & (1 << CP0DB_DM))
1573         env->hflags |= MIPS_HFLAG_DM;
1574     else
1575         env->hflags &= ~MIPS_HFLAG_DM;
1576 }
1577
1578 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1579 {
1580     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1581     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1582     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1583
1584     /* XXX: Might be wrong, check with EJTAG spec. */
1585     if (other_tc == other->current_tc)
1586         other->active_tc.CP0_Debug_tcstatus = val;
1587     else
1588         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1589     other->CP0_Debug = (other->CP0_Debug &
1590                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1591                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1592 }
1593
1594 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1595 {
1596     env->CP0_Performance0 = arg1 & 0x000007ff;
1597 }
1598
1599 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1600 {
1601     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1602 }
1603
1604 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1605 {
1606     env->CP0_DataLo = arg1; /* XXX */
1607 }
1608
1609 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1610 {
1611     env->CP0_TagHi = arg1; /* XXX */
1612 }
1613
1614 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1615 {
1616     env->CP0_DataHi = arg1; /* XXX */
1617 }
1618
1619 /* MIPS MT functions */
1620 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1621 {
1622     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1623     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1624
1625     if (other_tc == other->current_tc)
1626         return other->active_tc.gpr[sel];
1627     else
1628         return other->tcs[other_tc].gpr[sel];
1629 }
1630
1631 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1632 {
1633     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1634     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1635
1636     if (other_tc == other->current_tc)
1637         return other->active_tc.LO[sel];
1638     else
1639         return other->tcs[other_tc].LO[sel];
1640 }
1641
1642 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1643 {
1644     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1645     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1646
1647     if (other_tc == other->current_tc)
1648         return other->active_tc.HI[sel];
1649     else
1650         return other->tcs[other_tc].HI[sel];
1651 }
1652
1653 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1654 {
1655     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1656     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1657
1658     if (other_tc == other->current_tc)
1659         return other->active_tc.ACX[sel];
1660     else
1661         return other->tcs[other_tc].ACX[sel];
1662 }
1663
1664 target_ulong helper_mftdsp(CPUMIPSState *env)
1665 {
1666     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1667     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1668
1669     if (other_tc == other->current_tc)
1670         return other->active_tc.DSPControl;
1671     else
1672         return other->tcs[other_tc].DSPControl;
1673 }
1674
1675 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1676 {
1677     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1678     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1679
1680     if (other_tc == other->current_tc)
1681         other->active_tc.gpr[sel] = arg1;
1682     else
1683         other->tcs[other_tc].gpr[sel] = arg1;
1684 }
1685
1686 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1687 {
1688     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1689     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1690
1691     if (other_tc == other->current_tc)
1692         other->active_tc.LO[sel] = arg1;
1693     else
1694         other->tcs[other_tc].LO[sel] = arg1;
1695 }
1696
1697 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1698 {
1699     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1700     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1701
1702     if (other_tc == other->current_tc)
1703         other->active_tc.HI[sel] = arg1;
1704     else
1705         other->tcs[other_tc].HI[sel] = arg1;
1706 }
1707
1708 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1709 {
1710     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1711     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1712
1713     if (other_tc == other->current_tc)
1714         other->active_tc.ACX[sel] = arg1;
1715     else
1716         other->tcs[other_tc].ACX[sel] = arg1;
1717 }
1718
1719 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1720 {
1721     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1722     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1723
1724     if (other_tc == other->current_tc)
1725         other->active_tc.DSPControl = arg1;
1726     else
1727         other->tcs[other_tc].DSPControl = arg1;
1728 }
1729
1730 /* MIPS MT functions */
1731 target_ulong helper_dmt(void)
1732 {
1733     // TODO
1734      return 0;
1735 }
1736
1737 target_ulong helper_emt(void)
1738 {
1739     // TODO
1740     return 0;
1741 }
1742
1743 target_ulong helper_dvpe(CPUMIPSState *env)
1744 {
1745     CPUState *other_cs = first_cpu;
1746     target_ulong prev = env->mvp->CP0_MVPControl;
1747
1748     CPU_FOREACH(other_cs) {
1749         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1750         /* Turn off all VPEs except the one executing the dvpe.  */
1751         if (&other_cpu->env != env) {
1752             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1753             mips_vpe_sleep(other_cpu);
1754         }
1755     }
1756     return prev;
1757 }
1758
1759 target_ulong helper_evpe(CPUMIPSState *env)
1760 {
1761     CPUState *other_cs = first_cpu;
1762     target_ulong prev = env->mvp->CP0_MVPControl;
1763
1764     CPU_FOREACH(other_cs) {
1765         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1766
1767         if (&other_cpu->env != env
1768             /* If the VPE is WFI, don't disturb its sleep.  */
1769             && !mips_vpe_is_wfi(other_cpu)) {
1770             /* Enable the VPE.  */
1771             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1772             mips_vpe_wake(other_cpu); /* And wake it up.  */
1773         }
1774     }
1775     return prev;
1776 }
1777 #endif /* !CONFIG_USER_ONLY */
1778
1779 void helper_fork(target_ulong arg1, target_ulong arg2)
1780 {
1781     // arg1 = rt, arg2 = rs
1782     // TODO: store to TC register
1783 }
1784
1785 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1786 {
1787     target_long arg1 = arg;
1788
1789     if (arg1 < 0) {
1790         /* No scheduling policy implemented. */
1791         if (arg1 != -2) {
1792             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1793                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1794                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1795                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1796                 helper_raise_exception(env, EXCP_THREAD);
1797             }
1798         }
1799     } else if (arg1 == 0) {
1800         if (0 /* TODO: TC underflow */) {
1801             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1802             helper_raise_exception(env, EXCP_THREAD);
1803         } else {
1804             // TODO: Deallocate TC
1805         }
1806     } else if (arg1 > 0) {
1807         /* Yield qualifier inputs not implemented. */
1808         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1809         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1810         helper_raise_exception(env, EXCP_THREAD);
1811     }
1812     return env->CP0_YQMask;
1813 }
1814
1815 #ifndef CONFIG_USER_ONLY
1816 /* TLB management */
1817 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1818 {
1819     MIPSCPU *cpu = mips_env_get_cpu(env);
1820
1821     /* Flush qemu's TLB and discard all shadowed entries.  */
1822     tlb_flush(CPU(cpu), flush_global);
1823     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1824 }
1825
1826 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1827 {
1828     /* Discard entries from env->tlb[first] onwards.  */
1829     while (env->tlb->tlb_in_use > first) {
1830         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1831     }
1832 }
1833
1834 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1835 {
1836 #if defined(TARGET_MIPS64)
1837     return extract64(entrylo, 6, 54);
1838 #else
1839     return extract64(entrylo, 6, 24) | /* PFN */
1840            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1841 #endif
1842 }
1843
1844 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1845 {
1846     r4k_tlb_t *tlb;
1847
1848     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1849     tlb = &env->tlb->mmu.r4k.tlb[idx];
1850     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1851         tlb->EHINV = 1;
1852         return;
1853     }
1854     tlb->EHINV = 0;
1855     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1856 #if defined(TARGET_MIPS64)
1857     tlb->VPN &= env->SEGMask;
1858 #endif
1859     tlb->ASID = env->CP0_EntryHi & 0xFF;
1860     tlb->PageMask = env->CP0_PageMask;
1861     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1862     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1863     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1864     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1865     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1866     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1867     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1868     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1869     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1870     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1871     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1872     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1873     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1874 }
1875
1876 void r4k_helper_tlbinv(CPUMIPSState *env)
1877 {
1878     int idx;
1879     r4k_tlb_t *tlb;
1880     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1881
1882     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1883         tlb = &env->tlb->mmu.r4k.tlb[idx];
1884         if (!tlb->G && tlb->ASID == ASID) {
1885             tlb->EHINV = 1;
1886         }
1887     }
1888     cpu_mips_tlb_flush(env, 1);
1889 }
1890
1891 void r4k_helper_tlbinvf(CPUMIPSState *env)
1892 {
1893     int idx;
1894
1895     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1896         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1897     }
1898     cpu_mips_tlb_flush(env, 1);
1899 }
1900
1901 void r4k_helper_tlbwi(CPUMIPSState *env)
1902 {
1903     r4k_tlb_t *tlb;
1904     int idx;
1905     target_ulong VPN;
1906     uint8_t ASID;
1907     bool G, V0, D0, V1, D1;
1908
1909     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1910     tlb = &env->tlb->mmu.r4k.tlb[idx];
1911     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1912 #if defined(TARGET_MIPS64)
1913     VPN &= env->SEGMask;
1914 #endif
1915     ASID = env->CP0_EntryHi & 0xff;
1916     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1917     V0 = (env->CP0_EntryLo0 & 2) != 0;
1918     D0 = (env->CP0_EntryLo0 & 4) != 0;
1919     V1 = (env->CP0_EntryLo1 & 2) != 0;
1920     D1 = (env->CP0_EntryLo1 & 4) != 0;
1921
1922     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1923        permissions on the current entry. */
1924     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1925         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1926         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1927         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1928     }
1929
1930     r4k_invalidate_tlb(env, idx, 0);
1931     r4k_fill_tlb(env, idx);
1932 }
1933
1934 void r4k_helper_tlbwr(CPUMIPSState *env)
1935 {
1936     int r = cpu_mips_get_random(env);
1937
1938     r4k_invalidate_tlb(env, r, 1);
1939     r4k_fill_tlb(env, r);
1940 }
1941
1942 void r4k_helper_tlbp(CPUMIPSState *env)
1943 {
1944     r4k_tlb_t *tlb;
1945     target_ulong mask;
1946     target_ulong tag;
1947     target_ulong VPN;
1948     uint8_t ASID;
1949     int i;
1950
1951     ASID = env->CP0_EntryHi & 0xFF;
1952     for (i = 0; i < env->tlb->nb_tlb; i++) {
1953         tlb = &env->tlb->mmu.r4k.tlb[i];
1954         /* 1k pages are not supported. */
1955         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1956         tag = env->CP0_EntryHi & ~mask;
1957         VPN = tlb->VPN & ~mask;
1958 #if defined(TARGET_MIPS64)
1959         tag &= env->SEGMask;
1960 #endif
1961         /* Check ASID, virtual page number & size */
1962         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1963             /* TLB match */
1964             env->CP0_Index = i;
1965             break;
1966         }
1967     }
1968     if (i == env->tlb->nb_tlb) {
1969         /* No match.  Discard any shadow entries, if any of them match.  */
1970         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1971             tlb = &env->tlb->mmu.r4k.tlb[i];
1972             /* 1k pages are not supported. */
1973             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1974             tag = env->CP0_EntryHi & ~mask;
1975             VPN = tlb->VPN & ~mask;
1976 #if defined(TARGET_MIPS64)
1977             tag &= env->SEGMask;
1978 #endif
1979             /* Check ASID, virtual page number & size */
1980             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1981                 r4k_mips_tlb_flush_extra (env, i);
1982                 break;
1983             }
1984         }
1985
1986         env->CP0_Index |= 0x80000000;
1987     }
1988 }
1989
1990 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
1991 {
1992 #if defined(TARGET_MIPS64)
1993     return tlb_pfn << 6;
1994 #else
1995     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
1996            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
1997 #endif
1998 }
1999
2000 void r4k_helper_tlbr(CPUMIPSState *env)
2001 {
2002     r4k_tlb_t *tlb;
2003     uint8_t ASID;
2004     int idx;
2005
2006     ASID = env->CP0_EntryHi & 0xFF;
2007     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2008     tlb = &env->tlb->mmu.r4k.tlb[idx];
2009
2010     /* If this will change the current ASID, flush qemu's TLB.  */
2011     if (ASID != tlb->ASID)
2012         cpu_mips_tlb_flush (env, 1);
2013
2014     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2015
2016     if (tlb->EHINV) {
2017         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2018         env->CP0_PageMask = 0;
2019         env->CP0_EntryLo0 = 0;
2020         env->CP0_EntryLo1 = 0;
2021     } else {
2022         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2023         env->CP0_PageMask = tlb->PageMask;
2024         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2025                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2026                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2027                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2028         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2029                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2030                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2031                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2032     }
2033 }
2034
2035 void helper_tlbwi(CPUMIPSState *env)
2036 {
2037     env->tlb->helper_tlbwi(env);
2038 }
2039
2040 void helper_tlbwr(CPUMIPSState *env)
2041 {
2042     env->tlb->helper_tlbwr(env);
2043 }
2044
2045 void helper_tlbp(CPUMIPSState *env)
2046 {
2047     env->tlb->helper_tlbp(env);
2048 }
2049
2050 void helper_tlbr(CPUMIPSState *env)
2051 {
2052     env->tlb->helper_tlbr(env);
2053 }
2054
2055 void helper_tlbinv(CPUMIPSState *env)
2056 {
2057     env->tlb->helper_tlbinv(env);
2058 }
2059
2060 void helper_tlbinvf(CPUMIPSState *env)
2061 {
2062     env->tlb->helper_tlbinvf(env);
2063 }
2064
2065 /* Specials */
2066 target_ulong helper_di(CPUMIPSState *env)
2067 {
2068     target_ulong t0 = env->CP0_Status;
2069
2070     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2071     return t0;
2072 }
2073
2074 target_ulong helper_ei(CPUMIPSState *env)
2075 {
2076     target_ulong t0 = env->CP0_Status;
2077
2078     env->CP0_Status = t0 | (1 << CP0St_IE);
2079     return t0;
2080 }
2081
2082 static void debug_pre_eret(CPUMIPSState *env)
2083 {
2084     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2085         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2086                 env->active_tc.PC, env->CP0_EPC);
2087         if (env->CP0_Status & (1 << CP0St_ERL))
2088             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2089         if (env->hflags & MIPS_HFLAG_DM)
2090             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2091         qemu_log("\n");
2092     }
2093 }
2094
2095 static void debug_post_eret(CPUMIPSState *env)
2096 {
2097     MIPSCPU *cpu = mips_env_get_cpu(env);
2098
2099     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2100         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2101                 env->active_tc.PC, env->CP0_EPC);
2102         if (env->CP0_Status & (1 << CP0St_ERL))
2103             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2104         if (env->hflags & MIPS_HFLAG_DM)
2105             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2106         switch (env->hflags & MIPS_HFLAG_KSU) {
2107         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2108         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2109         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2110         default:
2111             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2112             break;
2113         }
2114     }
2115 }
2116
2117 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2118 {
2119     env->active_tc.PC = error_pc & ~(target_ulong)1;
2120     if (error_pc & 1) {
2121         env->hflags |= MIPS_HFLAG_M16;
2122     } else {
2123         env->hflags &= ~(MIPS_HFLAG_M16);
2124     }
2125 }
2126
2127 static inline void exception_return(CPUMIPSState *env)
2128 {
2129     debug_pre_eret(env);
2130     if (env->CP0_Status & (1 << CP0St_ERL)) {
2131         set_pc(env, env->CP0_ErrorEPC);
2132         env->CP0_Status &= ~(1 << CP0St_ERL);
2133     } else {
2134         set_pc(env, env->CP0_EPC);
2135         env->CP0_Status &= ~(1 << CP0St_EXL);
2136     }
2137     compute_hflags(env);
2138     debug_post_eret(env);
2139 }
2140
2141 void helper_eret(CPUMIPSState *env)
2142 {
2143     exception_return(env);
2144     env->lladdr = 1;
2145 }
2146
2147 void helper_eretnc(CPUMIPSState *env)
2148 {
2149     exception_return(env);
2150 }
2151
2152 void helper_deret(CPUMIPSState *env)
2153 {
2154     debug_pre_eret(env);
2155     set_pc(env, env->CP0_DEPC);
2156
2157     env->hflags &= MIPS_HFLAG_DM;
2158     compute_hflags(env);
2159     debug_post_eret(env);
2160     env->lladdr = 1;
2161 }
2162 #endif /* !CONFIG_USER_ONLY */
2163
2164 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2165 {
2166     if ((env->hflags & MIPS_HFLAG_CP0) ||
2167         (env->CP0_HWREna & (1 << 0)))
2168         return env->CP0_EBase & 0x3ff;
2169     else
2170         helper_raise_exception(env, EXCP_RI);
2171
2172     return 0;
2173 }
2174
2175 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2176 {
2177     if ((env->hflags & MIPS_HFLAG_CP0) ||
2178         (env->CP0_HWREna & (1 << 1)))
2179         return env->SYNCI_Step;
2180     else
2181         helper_raise_exception(env, EXCP_RI);
2182
2183     return 0;
2184 }
2185
2186 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2187 {
2188     if ((env->hflags & MIPS_HFLAG_CP0) ||
2189         (env->CP0_HWREna & (1 << 2)))
2190         return env->CP0_Count;
2191     else
2192         helper_raise_exception(env, EXCP_RI);
2193
2194     return 0;
2195 }
2196
2197 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2198 {
2199     if ((env->hflags & MIPS_HFLAG_CP0) ||
2200         (env->CP0_HWREna & (1 << 3)))
2201         return env->CCRes;
2202     else
2203         helper_raise_exception(env, EXCP_RI);
2204
2205     return 0;
2206 }
2207
2208 void helper_pmon(CPUMIPSState *env, int function)
2209 {
2210     function /= 2;
2211     switch (function) {
2212     case 2: /* TODO: char inbyte(int waitflag); */
2213         if (env->active_tc.gpr[4] == 0)
2214             env->active_tc.gpr[2] = -1;
2215         /* Fall through */
2216     case 11: /* TODO: char inbyte (void); */
2217         env->active_tc.gpr[2] = -1;
2218         break;
2219     case 3:
2220     case 12:
2221         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2222         break;
2223     case 17:
2224         break;
2225     case 158:
2226         {
2227             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2228             printf("%s", fmt);
2229         }
2230         break;
2231     }
2232 }
2233
2234 void helper_wait(CPUMIPSState *env)
2235 {
2236     CPUState *cs = CPU(mips_env_get_cpu(env));
2237
2238     cs->halted = 1;
2239     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2240     helper_raise_exception(env, EXCP_HLT);
2241 }
2242
2243 #if !defined(CONFIG_USER_ONLY)
2244
2245 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2246                                   int access_type, int is_user,
2247                                   uintptr_t retaddr)
2248 {
2249     MIPSCPU *cpu = MIPS_CPU(cs);
2250     CPUMIPSState *env = &cpu->env;
2251     int error_code = 0;
2252     int excp;
2253
2254     env->CP0_BadVAddr = addr;
2255
2256     if (access_type == MMU_DATA_STORE) {
2257         excp = EXCP_AdES;
2258     } else {
2259         excp = EXCP_AdEL;
2260         if (access_type == MMU_INST_FETCH) {
2261             error_code |= EXCP_INST_NOTAVAIL;
2262         }
2263     }
2264
2265     do_raise_exception_err(env, excp, error_code, retaddr);
2266 }
2267
2268 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2269               uintptr_t retaddr)
2270 {
2271     int ret;
2272
2273     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2274     if (ret) {
2275         MIPSCPU *cpu = MIPS_CPU(cs);
2276         CPUMIPSState *env = &cpu->env;
2277
2278         do_raise_exception_err(env, cs->exception_index,
2279                                env->error_code, retaddr);
2280     }
2281 }
2282
2283 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2284                                 bool is_write, bool is_exec, int unused,
2285                                 unsigned size)
2286 {
2287     MIPSCPU *cpu = MIPS_CPU(cs);
2288     CPUMIPSState *env = &cpu->env;
2289
2290     /*
2291      * Raising an exception with KVM enabled will crash because it won't be from
2292      * the main execution loop so the longjmp won't have a matching setjmp.
2293      * Until we can trigger a bus error exception through KVM lets just ignore
2294      * the access.
2295      */
2296     if (kvm_enabled()) {
2297         return;
2298     }
2299
2300     if (is_exec) {
2301         helper_raise_exception(env, EXCP_IBE);
2302     } else {
2303         helper_raise_exception(env, EXCP_DBE);
2304     }
2305 }
2306 #endif /* !CONFIG_USER_ONLY */
2307
2308 /* Complex FPU operations which may need stack space. */
2309
2310 #define FLOAT_TWO32 make_float32(1 << 30)
2311 #define FLOAT_TWO64 make_float64(1ULL << 62)
2312 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2313 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2314
2315 /* convert MIPS rounding mode in FCR31 to IEEE library */
2316 unsigned int ieee_rm[] = {
2317     float_round_nearest_even,
2318     float_round_to_zero,
2319     float_round_up,
2320     float_round_down
2321 };
2322
2323 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2324 {
2325     target_ulong arg1 = 0;
2326
2327     switch (reg) {
2328     case 0:
2329         arg1 = (int32_t)env->active_fpu.fcr0;
2330         break;
2331     case 1:
2332         /* UFR Support - Read Status FR */
2333         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2334             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2335                 arg1 = (int32_t)
2336                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2337             } else {
2338                 helper_raise_exception(env, EXCP_RI);
2339             }
2340         }
2341         break;
2342     case 5:
2343         /* FRE Support - read Config5.FRE bit */
2344         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2345             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2346                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2347             } else {
2348                 helper_raise_exception(env, EXCP_RI);
2349             }
2350         }
2351         break;
2352     case 25:
2353         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2354         break;
2355     case 26:
2356         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2357         break;
2358     case 28:
2359         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2360         break;
2361     default:
2362         arg1 = (int32_t)env->active_fpu.fcr31;
2363         break;
2364     }
2365
2366     return arg1;
2367 }
2368
2369 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2370 {
2371     switch (fs) {
2372     case 1:
2373         /* UFR Alias - Reset Status FR */
2374         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2375             return;
2376         }
2377         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2378             env->CP0_Status &= ~(1 << CP0St_FR);
2379             compute_hflags(env);
2380         } else {
2381             helper_raise_exception(env, EXCP_RI);
2382         }
2383         break;
2384     case 4:
2385         /* UNFR Alias - Set Status FR */
2386         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2387             return;
2388         }
2389         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2390             env->CP0_Status |= (1 << CP0St_FR);
2391             compute_hflags(env);
2392         } else {
2393             helper_raise_exception(env, EXCP_RI);
2394         }
2395         break;
2396     case 5:
2397         /* FRE Support - clear Config5.FRE bit */
2398         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2399             return;
2400         }
2401         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2402             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2403             compute_hflags(env);
2404         } else {
2405             helper_raise_exception(env, EXCP_RI);
2406         }
2407         break;
2408     case 6:
2409         /* FRE Support - set Config5.FRE bit */
2410         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2411             return;
2412         }
2413         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2414             env->CP0_Config5 |= (1 << CP0C5_FRE);
2415             compute_hflags(env);
2416         } else {
2417             helper_raise_exception(env, EXCP_RI);
2418         }
2419         break;
2420     case 25:
2421         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2422             return;
2423         }
2424         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2425                      ((arg1 & 0x1) << 23);
2426         break;
2427     case 26:
2428         if (arg1 & 0x007c0000)
2429             return;
2430         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2431         break;
2432     case 28:
2433         if (arg1 & 0x007c0000)
2434             return;
2435         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2436                      ((arg1 & 0x4) << 22);
2437         break;
2438     case 31:
2439         if (env->insn_flags & ISA_MIPS32R6) {
2440             uint32_t mask = 0xfefc0000;
2441             env->active_fpu.fcr31 = (arg1 & ~mask) |
2442                 (env->active_fpu.fcr31 & mask);
2443         } else if (!(arg1 & 0x007c0000)) {
2444             env->active_fpu.fcr31 = arg1;
2445         }
2446         break;
2447     default:
2448         return;
2449     }
2450     /* set rounding mode */
2451     restore_rounding_mode(env);
2452     /* set flush-to-zero mode */
2453     restore_flush_mode(env);
2454     set_float_exception_flags(0, &env->active_fpu.fp_status);
2455     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2456         do_raise_exception(env, EXCP_FPE, GETPC());
2457 }
2458
2459 int ieee_ex_to_mips(int xcpt)
2460 {
2461     int ret = 0;
2462     if (xcpt) {
2463         if (xcpt & float_flag_invalid) {
2464             ret |= FP_INVALID;
2465         }
2466         if (xcpt & float_flag_overflow) {
2467             ret |= FP_OVERFLOW;
2468         }
2469         if (xcpt & float_flag_underflow) {
2470             ret |= FP_UNDERFLOW;
2471         }
2472         if (xcpt & float_flag_divbyzero) {
2473             ret |= FP_DIV0;
2474         }
2475         if (xcpt & float_flag_inexact) {
2476             ret |= FP_INEXACT;
2477         }
2478     }
2479     return ret;
2480 }
2481
2482 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2483 {
2484     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2485
2486     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2487
2488     if (tmp) {
2489         set_float_exception_flags(0, &env->active_fpu.fp_status);
2490
2491         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2492             do_raise_exception(env, EXCP_FPE, pc);
2493         } else {
2494             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2495         }
2496     }
2497 }
2498
2499 /* Float support.
2500    Single precition routines have a "s" suffix, double precision a
2501    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2502    paired single lower "pl", paired single upper "pu".  */
2503
2504 /* unary operations, modifying fp status  */
2505 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2506 {
2507     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2508     update_fcr31(env, GETPC());
2509     return fdt0;
2510 }
2511
2512 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2513 {
2514     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2515     update_fcr31(env, GETPC());
2516     return fst0;
2517 }
2518
2519 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2520 {
2521     uint64_t fdt2;
2522
2523     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2524     update_fcr31(env, GETPC());
2525     return fdt2;
2526 }
2527
2528 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2529 {
2530     uint64_t fdt2;
2531
2532     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2533     update_fcr31(env, GETPC());
2534     return fdt2;
2535 }
2536
2537 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2538 {
2539     uint64_t fdt2;
2540
2541     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2542     update_fcr31(env, GETPC());
2543     return fdt2;
2544 }
2545
2546 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2547 {
2548     uint64_t dt2;
2549
2550     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2551     if (get_float_exception_flags(&env->active_fpu.fp_status)
2552         & (float_flag_invalid | float_flag_overflow)) {
2553         dt2 = FP_TO_INT64_OVERFLOW;
2554     }
2555     update_fcr31(env, GETPC());
2556     return dt2;
2557 }
2558
2559 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2560 {
2561     uint64_t dt2;
2562
2563     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2564     if (get_float_exception_flags(&env->active_fpu.fp_status)
2565         & (float_flag_invalid | float_flag_overflow)) {
2566         dt2 = FP_TO_INT64_OVERFLOW;
2567     }
2568     update_fcr31(env, GETPC());
2569     return dt2;
2570 }
2571
2572 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2573 {
2574     uint32_t fst2;
2575     uint32_t fsth2;
2576
2577     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2578     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2579     update_fcr31(env, GETPC());
2580     return ((uint64_t)fsth2 << 32) | fst2;
2581 }
2582
2583 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2584 {
2585     uint32_t wt2;
2586     uint32_t wth2;
2587     int excp, excph;
2588
2589     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2590     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2591     if (excp & (float_flag_overflow | float_flag_invalid)) {
2592         wt2 = FP_TO_INT32_OVERFLOW;
2593     }
2594
2595     set_float_exception_flags(0, &env->active_fpu.fp_status);
2596     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2597     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2598     if (excph & (float_flag_overflow | float_flag_invalid)) {
2599         wth2 = FP_TO_INT32_OVERFLOW;
2600     }
2601
2602     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2603     update_fcr31(env, GETPC());
2604
2605     return ((uint64_t)wth2 << 32) | wt2;
2606 }
2607
2608 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2609 {
2610     uint32_t fst2;
2611
2612     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2613     update_fcr31(env, GETPC());
2614     return fst2;
2615 }
2616
2617 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2618 {
2619     uint32_t fst2;
2620
2621     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2622     update_fcr31(env, GETPC());
2623     return fst2;
2624 }
2625
2626 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2627 {
2628     uint32_t fst2;
2629
2630     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2631     update_fcr31(env, GETPC());
2632     return fst2;
2633 }
2634
2635 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2636 {
2637     uint32_t wt2;
2638
2639     wt2 = wt0;
2640     update_fcr31(env, GETPC());
2641     return wt2;
2642 }
2643
2644 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2645 {
2646     uint32_t wt2;
2647
2648     wt2 = wth0;
2649     update_fcr31(env, GETPC());
2650     return wt2;
2651 }
2652
2653 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2654 {
2655     uint32_t wt2;
2656
2657     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2658     if (get_float_exception_flags(&env->active_fpu.fp_status)
2659         & (float_flag_invalid | float_flag_overflow)) {
2660         wt2 = FP_TO_INT32_OVERFLOW;
2661     }
2662     update_fcr31(env, GETPC());
2663     return wt2;
2664 }
2665
2666 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2667 {
2668     uint32_t wt2;
2669
2670     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2671     if (get_float_exception_flags(&env->active_fpu.fp_status)
2672         & (float_flag_invalid | float_flag_overflow)) {
2673         wt2 = FP_TO_INT32_OVERFLOW;
2674     }
2675     update_fcr31(env, GETPC());
2676     return wt2;
2677 }
2678
2679 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2680 {
2681     uint64_t dt2;
2682
2683     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2684     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2685     restore_rounding_mode(env);
2686     if (get_float_exception_flags(&env->active_fpu.fp_status)
2687         & (float_flag_invalid | float_flag_overflow)) {
2688         dt2 = FP_TO_INT64_OVERFLOW;
2689     }
2690     update_fcr31(env, GETPC());
2691     return dt2;
2692 }
2693
2694 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2695 {
2696     uint64_t dt2;
2697
2698     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2699     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2700     restore_rounding_mode(env);
2701     if (get_float_exception_flags(&env->active_fpu.fp_status)
2702         & (float_flag_invalid | float_flag_overflow)) {
2703         dt2 = FP_TO_INT64_OVERFLOW;
2704     }
2705     update_fcr31(env, GETPC());
2706     return dt2;
2707 }
2708
2709 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2710 {
2711     uint32_t wt2;
2712
2713     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2714     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2715     restore_rounding_mode(env);
2716     if (get_float_exception_flags(&env->active_fpu.fp_status)
2717         & (float_flag_invalid | float_flag_overflow)) {
2718         wt2 = FP_TO_INT32_OVERFLOW;
2719     }
2720     update_fcr31(env, GETPC());
2721     return wt2;
2722 }
2723
2724 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2725 {
2726     uint32_t wt2;
2727
2728     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2729     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2730     restore_rounding_mode(env);
2731     if (get_float_exception_flags(&env->active_fpu.fp_status)
2732         & (float_flag_invalid | float_flag_overflow)) {
2733         wt2 = FP_TO_INT32_OVERFLOW;
2734     }
2735     update_fcr31(env, GETPC());
2736     return wt2;
2737 }
2738
2739 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2740 {
2741     uint64_t dt2;
2742
2743     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2744     if (get_float_exception_flags(&env->active_fpu.fp_status)
2745         & (float_flag_invalid | float_flag_overflow)) {
2746         dt2 = FP_TO_INT64_OVERFLOW;
2747     }
2748     update_fcr31(env, GETPC());
2749     return dt2;
2750 }
2751
2752 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2753 {
2754     uint64_t dt2;
2755
2756     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2757     if (get_float_exception_flags(&env->active_fpu.fp_status)
2758         & (float_flag_invalid | float_flag_overflow)) {
2759         dt2 = FP_TO_INT64_OVERFLOW;
2760     }
2761     update_fcr31(env, GETPC());
2762     return dt2;
2763 }
2764
2765 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2766 {
2767     uint32_t wt2;
2768
2769     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2770     if (get_float_exception_flags(&env->active_fpu.fp_status)
2771         & (float_flag_invalid | float_flag_overflow)) {
2772         wt2 = FP_TO_INT32_OVERFLOW;
2773     }
2774     update_fcr31(env, GETPC());
2775     return wt2;
2776 }
2777
2778 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2779 {
2780     uint32_t wt2;
2781
2782     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2783     if (get_float_exception_flags(&env->active_fpu.fp_status)
2784         & (float_flag_invalid | float_flag_overflow)) {
2785         wt2 = FP_TO_INT32_OVERFLOW;
2786     }
2787     update_fcr31(env, GETPC());
2788     return wt2;
2789 }
2790
2791 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2792 {
2793     uint64_t dt2;
2794
2795     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2796     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2797     restore_rounding_mode(env);
2798     if (get_float_exception_flags(&env->active_fpu.fp_status)
2799         & (float_flag_invalid | float_flag_overflow)) {
2800         dt2 = FP_TO_INT64_OVERFLOW;
2801     }
2802     update_fcr31(env, GETPC());
2803     return dt2;
2804 }
2805
2806 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2807 {
2808     uint64_t dt2;
2809
2810     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2811     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2812     restore_rounding_mode(env);
2813     if (get_float_exception_flags(&env->active_fpu.fp_status)
2814         & (float_flag_invalid | float_flag_overflow)) {
2815         dt2 = FP_TO_INT64_OVERFLOW;
2816     }
2817     update_fcr31(env, GETPC());
2818     return dt2;
2819 }
2820
2821 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2822 {
2823     uint32_t wt2;
2824
2825     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2826     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2827     restore_rounding_mode(env);
2828     if (get_float_exception_flags(&env->active_fpu.fp_status)
2829         & (float_flag_invalid | float_flag_overflow)) {
2830         wt2 = FP_TO_INT32_OVERFLOW;
2831     }
2832     update_fcr31(env, GETPC());
2833     return wt2;
2834 }
2835
2836 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2837 {
2838     uint32_t wt2;
2839
2840     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2841     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2842     restore_rounding_mode(env);
2843     if (get_float_exception_flags(&env->active_fpu.fp_status)
2844         & (float_flag_invalid | float_flag_overflow)) {
2845         wt2 = FP_TO_INT32_OVERFLOW;
2846     }
2847     update_fcr31(env, GETPC());
2848     return wt2;
2849 }
2850
2851 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2852 {
2853     uint64_t dt2;
2854
2855     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2856     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2857     restore_rounding_mode(env);
2858     if (get_float_exception_flags(&env->active_fpu.fp_status)
2859         & (float_flag_invalid | float_flag_overflow)) {
2860         dt2 = FP_TO_INT64_OVERFLOW;
2861     }
2862     update_fcr31(env, GETPC());
2863     return dt2;
2864 }
2865
2866 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2867 {
2868     uint64_t dt2;
2869
2870     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2871     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2872     restore_rounding_mode(env);
2873     if (get_float_exception_flags(&env->active_fpu.fp_status)
2874         & (float_flag_invalid | float_flag_overflow)) {
2875         dt2 = FP_TO_INT64_OVERFLOW;
2876     }
2877     update_fcr31(env, GETPC());
2878     return dt2;
2879 }
2880
2881 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2882 {
2883     uint32_t wt2;
2884
2885     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2886     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2887     restore_rounding_mode(env);
2888     if (get_float_exception_flags(&env->active_fpu.fp_status)
2889         & (float_flag_invalid | float_flag_overflow)) {
2890         wt2 = FP_TO_INT32_OVERFLOW;
2891     }
2892     update_fcr31(env, GETPC());
2893     return wt2;
2894 }
2895
2896 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2897 {
2898     uint32_t wt2;
2899
2900     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2901     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2902     restore_rounding_mode(env);
2903     if (get_float_exception_flags(&env->active_fpu.fp_status)
2904         & (float_flag_invalid | float_flag_overflow)) {
2905         wt2 = FP_TO_INT32_OVERFLOW;
2906     }
2907     update_fcr31(env, GETPC());
2908     return wt2;
2909 }
2910
2911 /* unary operations, not modifying fp status  */
2912 #define FLOAT_UNOP(name)                                       \
2913 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2914 {                                                              \
2915     return float64_ ## name(fdt0);                             \
2916 }                                                              \
2917 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2918 {                                                              \
2919     return float32_ ## name(fst0);                             \
2920 }                                                              \
2921 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2922 {                                                              \
2923     uint32_t wt0;                                              \
2924     uint32_t wth0;                                             \
2925                                                                \
2926     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2927     wth0 = float32_ ## name(fdt0 >> 32);                       \
2928     return ((uint64_t)wth0 << 32) | wt0;                       \
2929 }
2930 FLOAT_UNOP(abs)
2931 FLOAT_UNOP(chs)
2932 #undef FLOAT_UNOP
2933
2934 /* MIPS specific unary operations */
2935 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2936 {
2937     uint64_t fdt2;
2938
2939     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2940     update_fcr31(env, GETPC());
2941     return fdt2;
2942 }
2943
2944 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2945 {
2946     uint32_t fst2;
2947
2948     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2949     update_fcr31(env, GETPC());
2950     return fst2;
2951 }
2952
2953 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2954 {
2955     uint64_t fdt2;
2956
2957     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2958     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2959     update_fcr31(env, GETPC());
2960     return fdt2;
2961 }
2962
2963 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2964 {
2965     uint32_t fst2;
2966
2967     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2968     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2969     update_fcr31(env, GETPC());
2970     return fst2;
2971 }
2972
2973 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2974 {
2975     uint64_t fdt2;
2976
2977     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2978     update_fcr31(env, GETPC());
2979     return fdt2;
2980 }
2981
2982 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2983 {
2984     uint32_t fst2;
2985
2986     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2987     update_fcr31(env, GETPC());
2988     return fst2;
2989 }
2990
2991 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2992 {
2993     uint32_t fst2;
2994     uint32_t fsth2;
2995
2996     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2997     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2998     update_fcr31(env, GETPC());
2999     return ((uint64_t)fsth2 << 32) | fst2;
3000 }
3001
3002 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3003 {
3004     uint64_t fdt2;
3005
3006     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3007     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3008     update_fcr31(env, GETPC());
3009     return fdt2;
3010 }
3011
3012 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3013 {
3014     uint32_t fst2;
3015
3016     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3017     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3018     update_fcr31(env, GETPC());
3019     return fst2;
3020 }
3021
3022 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3023 {
3024     uint32_t fst2;
3025     uint32_t fsth2;
3026
3027     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3028     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3029     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3030     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3031     update_fcr31(env, GETPC());
3032     return ((uint64_t)fsth2 << 32) | fst2;
3033 }
3034
3035 #define FLOAT_RINT(name, bits)                                              \
3036 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3037                                           uint ## bits ## _t fs)            \
3038 {                                                                           \
3039     uint ## bits ## _t fdret;                                               \
3040                                                                             \
3041     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3042     update_fcr31(env, GETPC());                                             \
3043     return fdret;                                                           \
3044 }
3045
3046 FLOAT_RINT(rint_s, 32)
3047 FLOAT_RINT(rint_d, 64)
3048 #undef FLOAT_RINT
3049
3050 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3051 #define FLOAT_CLASS_QUIET_NAN          0x002
3052 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3053 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3054 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3055 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3056 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3057 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3058 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3059 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3060
3061 #define FLOAT_CLASS(name, bits)                                      \
3062 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3063 {                                                                    \
3064     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3065         return FLOAT_CLASS_SIGNALING_NAN;                            \
3066     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3067         return FLOAT_CLASS_QUIET_NAN;                                \
3068     } else if (float ## bits ## _is_neg(arg)) {                      \
3069         if (float ## bits ## _is_infinity(arg)) {                    \
3070             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3071         } else if (float ## bits ## _is_zero(arg)) {                 \
3072             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3073         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3074             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3075         } else {                                                     \
3076             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3077         }                                                            \
3078     } else {                                                         \
3079         if (float ## bits ## _is_infinity(arg)) {                    \
3080             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3081         } else if (float ## bits ## _is_zero(arg)) {                 \
3082             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3083         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3084             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3085         } else {                                                     \
3086             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3087         }                                                            \
3088     }                                                                \
3089 }
3090
3091 FLOAT_CLASS(class_s, 32)
3092 FLOAT_CLASS(class_d, 64)
3093 #undef FLOAT_CLASS
3094
3095 /* binary operations */
3096 #define FLOAT_BINOP(name)                                          \
3097 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3098                                      uint64_t fdt0, uint64_t fdt1) \
3099 {                                                                  \
3100     uint64_t dt2;                                                  \
3101                                                                    \
3102     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3103     update_fcr31(env, GETPC());                                    \
3104     return dt2;                                                    \
3105 }                                                                  \
3106                                                                    \
3107 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3108                                      uint32_t fst0, uint32_t fst1) \
3109 {                                                                  \
3110     uint32_t wt2;                                                  \
3111                                                                    \
3112     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3113     update_fcr31(env, GETPC());                                    \
3114     return wt2;                                                    \
3115 }                                                                  \
3116                                                                    \
3117 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3118                                       uint64_t fdt0,               \
3119                                       uint64_t fdt1)               \
3120 {                                                                  \
3121     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3122     uint32_t fsth0 = fdt0 >> 32;                                   \
3123     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3124     uint32_t fsth1 = fdt1 >> 32;                                   \
3125     uint32_t wt2;                                                  \
3126     uint32_t wth2;                                                 \
3127                                                                    \
3128     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3129     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3130     update_fcr31(env, GETPC());                                    \
3131     return ((uint64_t)wth2 << 32) | wt2;                           \
3132 }
3133
3134 FLOAT_BINOP(add)
3135 FLOAT_BINOP(sub)
3136 FLOAT_BINOP(mul)
3137 FLOAT_BINOP(div)
3138 #undef FLOAT_BINOP
3139
3140 /* MIPS specific binary operations */
3141 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3142 {
3143     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3144     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3145     update_fcr31(env, GETPC());
3146     return fdt2;
3147 }
3148
3149 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3150 {
3151     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3152     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3153     update_fcr31(env, GETPC());
3154     return fst2;
3155 }
3156
3157 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3158 {
3159     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3160     uint32_t fsth0 = fdt0 >> 32;
3161     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3162     uint32_t fsth2 = fdt2 >> 32;
3163
3164     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3165     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3166     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3167     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3168     update_fcr31(env, GETPC());
3169     return ((uint64_t)fsth2 << 32) | fst2;
3170 }
3171
3172 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3173 {
3174     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3175     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3176     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3177     update_fcr31(env, GETPC());
3178     return fdt2;
3179 }
3180
3181 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3182 {
3183     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3184     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3185     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3186     update_fcr31(env, GETPC());
3187     return fst2;
3188 }
3189
3190 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3191 {
3192     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3193     uint32_t fsth0 = fdt0 >> 32;
3194     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3195     uint32_t fsth2 = fdt2 >> 32;
3196
3197     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3198     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3199     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3200     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3201     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3202     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3203     update_fcr31(env, GETPC());
3204     return ((uint64_t)fsth2 << 32) | fst2;
3205 }
3206
3207 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3208 {
3209     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3210     uint32_t fsth0 = fdt0 >> 32;
3211     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3212     uint32_t fsth1 = fdt1 >> 32;
3213     uint32_t fst2;
3214     uint32_t fsth2;
3215
3216     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3217     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3218     update_fcr31(env, GETPC());
3219     return ((uint64_t)fsth2 << 32) | fst2;
3220 }
3221
3222 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3223 {
3224     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3225     uint32_t fsth0 = fdt0 >> 32;
3226     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3227     uint32_t fsth1 = fdt1 >> 32;
3228     uint32_t fst2;
3229     uint32_t fsth2;
3230
3231     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3232     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3233     update_fcr31(env, GETPC());
3234     return ((uint64_t)fsth2 << 32) | fst2;
3235 }
3236
3237 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3238 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3239                                           uint ## bits ## _t fs,        \
3240                                           uint ## bits ## _t ft)        \
3241 {                                                                       \
3242     uint ## bits ## _t fdret;                                           \
3243                                                                         \
3244     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3245                                            &env->active_fpu.fp_status); \
3246     update_fcr31(env, GETPC());                                         \
3247     return fdret;                                                       \
3248 }
3249
3250 FLOAT_MINMAX(max_s, 32, maxnum)
3251 FLOAT_MINMAX(max_d, 64, maxnum)
3252 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3253 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3254
3255 FLOAT_MINMAX(min_s, 32, minnum)
3256 FLOAT_MINMAX(min_d, 64, minnum)
3257 FLOAT_MINMAX(mina_s, 32, minnummag)
3258 FLOAT_MINMAX(mina_d, 64, minnummag)
3259 #undef FLOAT_MINMAX
3260
3261 /* ternary operations */
3262 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3263 {                                                                    \
3264     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3265     if ((flags) & float_muladd_negate_c) {                           \
3266         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3267     } else {                                                         \
3268         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3269     }                                                                \
3270     if ((flags) & float_muladd_negate_result) {                      \
3271         a = prefix##_chs(a);                                         \
3272     }                                                                \
3273 }
3274
3275 /* FMA based operations */
3276 #define FLOAT_FMA(name, type)                                        \
3277 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3278                                      uint64_t fdt0, uint64_t fdt1,   \
3279                                      uint64_t fdt2)                  \
3280 {                                                                    \
3281     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3282     update_fcr31(env, GETPC());                                      \
3283     return fdt0;                                                     \
3284 }                                                                    \
3285                                                                      \
3286 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3287                                      uint32_t fst0, uint32_t fst1,   \
3288                                      uint32_t fst2)                  \
3289 {                                                                    \
3290     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3291     update_fcr31(env, GETPC());                                      \
3292     return fst0;                                                     \
3293 }                                                                    \
3294                                                                      \
3295 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3296                                       uint64_t fdt0, uint64_t fdt1,  \
3297                                       uint64_t fdt2)                 \
3298 {                                                                    \
3299     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3300     uint32_t fsth0 = fdt0 >> 32;                                     \
3301     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3302     uint32_t fsth1 = fdt1 >> 32;                                     \
3303     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3304     uint32_t fsth2 = fdt2 >> 32;                                     \
3305                                                                      \
3306     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3307     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3308     update_fcr31(env, GETPC());                                      \
3309     return ((uint64_t)fsth0 << 32) | fst0;                           \
3310 }
3311 FLOAT_FMA(madd, 0)
3312 FLOAT_FMA(msub, float_muladd_negate_c)
3313 FLOAT_FMA(nmadd, float_muladd_negate_result)
3314 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3315 #undef FLOAT_FMA
3316
3317 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3318 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3319                                           uint ## bits ## _t fs,        \
3320                                           uint ## bits ## _t ft,        \
3321                                           uint ## bits ## _t fd)        \
3322 {                                                                       \
3323     uint ## bits ## _t fdret;                                           \
3324                                                                         \
3325     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3326                                      &env->active_fpu.fp_status);       \
3327     update_fcr31(env, GETPC());                                         \
3328     return fdret;                                                       \
3329 }
3330
3331 FLOAT_FMADDSUB(maddf_s, 32, 0)
3332 FLOAT_FMADDSUB(maddf_d, 64, 0)
3333 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3334 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3335 #undef FLOAT_FMADDSUB
3336
3337 /* compare operations */
3338 #define FOP_COND_D(op, cond)                                   \
3339 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3340                          uint64_t fdt1, int cc)                \
3341 {                                                              \
3342     int c;                                                     \
3343     c = cond;                                                  \
3344     update_fcr31(env, GETPC());                                \
3345     if (c)                                                     \
3346         SET_FP_COND(cc, env->active_fpu);                      \
3347     else                                                       \
3348         CLEAR_FP_COND(cc, env->active_fpu);                    \
3349 }                                                              \
3350 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3351                             uint64_t fdt1, int cc)             \
3352 {                                                              \
3353     int c;                                                     \
3354     fdt0 = float64_abs(fdt0);                                  \
3355     fdt1 = float64_abs(fdt1);                                  \
3356     c = cond;                                                  \
3357     update_fcr31(env, GETPC());                                \
3358     if (c)                                                     \
3359         SET_FP_COND(cc, env->active_fpu);                      \
3360     else                                                       \
3361         CLEAR_FP_COND(cc, env->active_fpu);                    \
3362 }
3363
3364 /* NOTE: the comma operator will make "cond" to eval to false,
3365  * but float64_unordered_quiet() is still called. */
3366 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3367 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3368 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3369 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3370 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3371 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3372 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3373 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3374 /* NOTE: the comma operator will make "cond" to eval to false,
3375  * but float64_unordered() is still called. */
3376 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3377 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3378 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3379 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3380 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3381 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3382 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3383 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3384
3385 #define FOP_COND_S(op, cond)                                   \
3386 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3387                          uint32_t fst1, int cc)                \
3388 {                                                              \
3389     int c;                                                     \
3390     c = cond;                                                  \
3391     update_fcr31(env, GETPC());                                \
3392     if (c)                                                     \
3393         SET_FP_COND(cc, env->active_fpu);                      \
3394     else                                                       \
3395         CLEAR_FP_COND(cc, env->active_fpu);                    \
3396 }                                                              \
3397 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3398                             uint32_t fst1, int cc)             \
3399 {                                                              \
3400     int c;                                                     \
3401     fst0 = float32_abs(fst0);                                  \
3402     fst1 = float32_abs(fst1);                                  \
3403     c = cond;                                                  \
3404     update_fcr31(env, GETPC());                                \
3405     if (c)                                                     \
3406         SET_FP_COND(cc, env->active_fpu);                      \
3407     else                                                       \
3408         CLEAR_FP_COND(cc, env->active_fpu);                    \
3409 }
3410
3411 /* NOTE: the comma operator will make "cond" to eval to false,
3412  * but float32_unordered_quiet() is still called. */
3413 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3414 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3415 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3416 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3417 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3418 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3419 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3420 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3421 /* NOTE: the comma operator will make "cond" to eval to false,
3422  * but float32_unordered() is still called. */
3423 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3424 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3425 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3426 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3427 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3428 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3429 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3430 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3431
3432 #define FOP_COND_PS(op, condl, condh)                           \
3433 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3434                           uint64_t fdt1, int cc)                \
3435 {                                                               \
3436     uint32_t fst0, fsth0, fst1, fsth1;                          \
3437     int ch, cl;                                                 \
3438     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3439     fsth0 = fdt0 >> 32;                                         \
3440     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3441     fsth1 = fdt1 >> 32;                                         \
3442     cl = condl;                                                 \
3443     ch = condh;                                                 \
3444     update_fcr31(env, GETPC());                                 \
3445     if (cl)                                                     \
3446         SET_FP_COND(cc, env->active_fpu);                       \
3447     else                                                        \
3448         CLEAR_FP_COND(cc, env->active_fpu);                     \
3449     if (ch)                                                     \
3450         SET_FP_COND(cc + 1, env->active_fpu);                   \
3451     else                                                        \
3452         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3453 }                                                               \
3454 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3455                              uint64_t fdt1, int cc)             \
3456 {                                                               \
3457     uint32_t fst0, fsth0, fst1, fsth1;                          \
3458     int ch, cl;                                                 \
3459     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3460     fsth0 = float32_abs(fdt0 >> 32);                            \
3461     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3462     fsth1 = float32_abs(fdt1 >> 32);                            \
3463     cl = condl;                                                 \
3464     ch = condh;                                                 \
3465     update_fcr31(env, GETPC());                                 \
3466     if (cl)                                                     \
3467         SET_FP_COND(cc, env->active_fpu);                       \
3468     else                                                        \
3469         CLEAR_FP_COND(cc, env->active_fpu);                     \
3470     if (ch)                                                     \
3471         SET_FP_COND(cc + 1, env->active_fpu);                   \
3472     else                                                        \
3473         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3474 }
3475
3476 /* NOTE: the comma operator will make "cond" to eval to false,
3477  * but float32_unordered_quiet() is still called. */
3478 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3479                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3480 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3481                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3482 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3483                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3484 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3485                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3486 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3487                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3488 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3489                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3490 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3491                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3492 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3493                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3494 /* NOTE: the comma operator will make "cond" to eval to false,
3495  * but float32_unordered() is still called. */
3496 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3497                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3498 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3499                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3500 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3501                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3502 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3503                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3504 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3505                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3506 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3507                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3508 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3509                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3510 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3511                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3512
3513 /* R6 compare operations */
3514 #define FOP_CONDN_D(op, cond)                                       \
3515 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3516                          uint64_t fdt1)                             \
3517 {                                                                   \
3518     uint64_t c;                                                     \
3519     c = cond;                                                       \
3520     update_fcr31(env, GETPC());                                     \
3521     if (c) {                                                        \
3522         return -1;                                                  \
3523     } else {                                                        \
3524         return 0;                                                   \
3525     }                                                               \
3526 }
3527
3528 /* NOTE: the comma operator will make "cond" to eval to false,
3529  * but float64_unordered_quiet() is still called. */
3530 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3531 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3532 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3533 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3534                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3535 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3536 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3537                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3538 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3539 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3540                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3541 /* NOTE: the comma operator will make "cond" to eval to false,
3542  * but float64_unordered() is still called. */
3543 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3544 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3545 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3546 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3547                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3548 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3549 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3550                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3551 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3552 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3553                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3554 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3555                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3556 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3557                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3558                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3559 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3560                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3561 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3562                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3563 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3564                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3565                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3566 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3567                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3568
3569 #define FOP_CONDN_S(op, cond)                                       \
3570 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3571                          uint32_t fst1)                             \
3572 {                                                                   \
3573     uint64_t c;                                                     \
3574     c = cond;                                                       \
3575     update_fcr31(env, GETPC());                                     \
3576     if (c) {                                                        \
3577         return -1;                                                  \
3578     } else {                                                        \
3579         return 0;                                                   \
3580     }                                                               \
3581 }
3582
3583 /* NOTE: the comma operator will make "cond" to eval to false,
3584  * but float32_unordered_quiet() is still called. */
3585 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3586 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3587 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3588 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3589                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3590 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3591 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3592                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3593 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3594 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3595                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3596 /* NOTE: the comma operator will make "cond" to eval to false,
3597  * but float32_unordered() is still called. */
3598 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3599 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3600 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3601 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3602                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3603 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3604 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3605                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3606 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3607 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3608                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3609 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3610                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3611 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3612                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3613                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3614 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3615                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3616 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3617                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3618 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3619                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3620                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3621 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3622                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3623
3624 /* MSA */
3625 /* Data format min and max values */
3626 #define DF_BITS(df) (1 << ((df) + 3))
3627
3628 /* Element-by-element access macros */
3629 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3630
3631 #if !defined(CONFIG_USER_ONLY)
3632 #define MEMOP_IDX(DF)                                           \
3633         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3634                                         cpu_mmu_index(env));
3635 #else
3636 #define MEMOP_IDX(DF)
3637 #endif
3638
3639 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3640 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3641                             target_ulong addr)                          \
3642 {                                                                       \
3643     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3644     wr_t wx;                                                            \
3645     int i;                                                              \
3646     MEMOP_IDX(DF)                                                       \
3647     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3648         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3649     }                                                                   \
3650     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3651 }
3652
3653 #if !defined(CONFIG_USER_ONLY)
3654 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3655 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3656 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3657 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3658 #else
3659 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3660 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3661 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3662 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3663 #endif
3664
3665 #define MSA_PAGESPAN(x) \
3666         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3667
3668 static inline void ensure_writable_pages(CPUMIPSState *env,
3669                                          target_ulong addr,
3670                                          int mmu_idx,
3671                                          uintptr_t retaddr)
3672 {
3673 #if !defined(CONFIG_USER_ONLY)
3674     target_ulong page_addr;
3675     if (unlikely(MSA_PAGESPAN(addr))) {
3676         /* first page */
3677         probe_write(env, addr, mmu_idx, retaddr);
3678         /* second page */
3679         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3680         probe_write(env, page_addr, mmu_idx, retaddr);
3681     }
3682 #endif
3683 }
3684
3685 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3686 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3687                             target_ulong addr)                          \
3688 {                                                                       \
3689     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3690     int mmu_idx = cpu_mmu_index(env);                                   \
3691     int i;                                                              \
3692     MEMOP_IDX(DF)                                                       \
3693     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3694     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3695         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3696     }                                                                   \
3697 }
3698
3699 #if !defined(CONFIG_USER_ONLY)
3700 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3701 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3702 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3703 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3704 #else
3705 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3706 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3707 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3708 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3709 #endif