2 * QEMU Sparc SLAVIO aux io port emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
29 #include "qemu/module.h"
30 #include "sysemu/runstate.h"
32 #include "qom/object.h"
35 * This is the auxio port, chip control and system control part of
36 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
39 * This also includes the PMC CPU idle controller.
42 #define TYPE_SLAVIO_MISC "slavio_misc"
43 typedef struct MiscState MiscState
;
44 DECLARE_INSTANCE_CHECKER(MiscState
, SLAVIO_MISC
,
48 SysBusDevice parent_obj
;
50 MemoryRegion cfg_iomem
;
51 MemoryRegion diag_iomem
;
52 MemoryRegion mdm_iomem
;
53 MemoryRegion led_iomem
;
54 MemoryRegion sysctrl_iomem
;
55 MemoryRegion aux1_iomem
;
56 MemoryRegion aux2_iomem
;
67 #define TYPE_APC "apc"
68 typedef struct APCState APCState
;
69 DECLARE_INSTANCE_CHECKER(APCState
, APC
,
73 SysBusDevice parent_obj
;
81 #define SYSCTRL_SIZE 4
85 #define AUX2_PWROFF 0x01
86 #define AUX2_PWRINTCLR 0x02
87 #define AUX2_PWRFAIL 0x20
89 #define CFG_PWRINTEN 0x08
91 #define SYS_RESET 0x01
92 #define SYS_RESETSTAT 0x02
94 static void slavio_misc_update_irq(void *opaque
)
96 MiscState
*s
= opaque
;
98 if ((s
->aux2
& AUX2_PWRFAIL
) && (s
->config
& CFG_PWRINTEN
)) {
99 trace_slavio_misc_update_irq_raise();
100 qemu_irq_raise(s
->irq
);
102 trace_slavio_misc_update_irq_lower();
103 qemu_irq_lower(s
->irq
);
107 static void slavio_misc_reset(DeviceState
*d
)
109 MiscState
*s
= SLAVIO_MISC(d
);
111 // Diagnostic and system control registers not cleared in reset
112 s
->config
= s
->aux1
= s
->aux2
= s
->mctrl
= 0;
115 static void slavio_set_power_fail(void *opaque
, int irq
, int power_failing
)
117 MiscState
*s
= opaque
;
119 trace_slavio_set_power_fail(power_failing
, s
->config
);
120 if (power_failing
&& (s
->config
& CFG_PWRINTEN
)) {
121 s
->aux2
|= AUX2_PWRFAIL
;
123 s
->aux2
&= ~AUX2_PWRFAIL
;
125 slavio_misc_update_irq(s
);
128 static void slavio_cfg_mem_writeb(void *opaque
, hwaddr addr
,
129 uint64_t val
, unsigned size
)
131 MiscState
*s
= opaque
;
133 trace_slavio_cfg_mem_writeb(val
& 0xff);
134 s
->config
= val
& 0xff;
135 slavio_misc_update_irq(s
);
138 static uint64_t slavio_cfg_mem_readb(void *opaque
, hwaddr addr
,
141 MiscState
*s
= opaque
;
145 trace_slavio_cfg_mem_readb(ret
);
149 static const MemoryRegionOps slavio_cfg_mem_ops
= {
150 .read
= slavio_cfg_mem_readb
,
151 .write
= slavio_cfg_mem_writeb
,
152 .endianness
= DEVICE_NATIVE_ENDIAN
,
154 .min_access_size
= 1,
155 .max_access_size
= 1,
159 static void slavio_diag_mem_writeb(void *opaque
, hwaddr addr
,
160 uint64_t val
, unsigned size
)
162 MiscState
*s
= opaque
;
164 trace_slavio_diag_mem_writeb(val
& 0xff);
165 s
->diag
= val
& 0xff;
168 static uint64_t slavio_diag_mem_readb(void *opaque
, hwaddr addr
,
171 MiscState
*s
= opaque
;
175 trace_slavio_diag_mem_readb(ret
);
179 static const MemoryRegionOps slavio_diag_mem_ops
= {
180 .read
= slavio_diag_mem_readb
,
181 .write
= slavio_diag_mem_writeb
,
182 .endianness
= DEVICE_NATIVE_ENDIAN
,
184 .min_access_size
= 1,
185 .max_access_size
= 1,
189 static void slavio_mdm_mem_writeb(void *opaque
, hwaddr addr
,
190 uint64_t val
, unsigned size
)
192 MiscState
*s
= opaque
;
194 trace_slavio_mdm_mem_writeb(val
& 0xff);
195 s
->mctrl
= val
& 0xff;
198 static uint64_t slavio_mdm_mem_readb(void *opaque
, hwaddr addr
,
201 MiscState
*s
= opaque
;
205 trace_slavio_mdm_mem_readb(ret
);
209 static const MemoryRegionOps slavio_mdm_mem_ops
= {
210 .read
= slavio_mdm_mem_readb
,
211 .write
= slavio_mdm_mem_writeb
,
212 .endianness
= DEVICE_NATIVE_ENDIAN
,
214 .min_access_size
= 1,
215 .max_access_size
= 1,
219 static void slavio_aux1_mem_writeb(void *opaque
, hwaddr addr
,
220 uint64_t val
, unsigned size
)
222 MiscState
*s
= opaque
;
224 trace_slavio_aux1_mem_writeb(val
& 0xff);
226 // Send a pulse to floppy terminal count line
228 qemu_irq_raise(s
->fdc_tc
);
229 qemu_irq_lower(s
->fdc_tc
);
233 s
->aux1
= val
& 0xff;
236 static uint64_t slavio_aux1_mem_readb(void *opaque
, hwaddr addr
,
239 MiscState
*s
= opaque
;
243 trace_slavio_aux1_mem_readb(ret
);
247 static const MemoryRegionOps slavio_aux1_mem_ops
= {
248 .read
= slavio_aux1_mem_readb
,
249 .write
= slavio_aux1_mem_writeb
,
250 .endianness
= DEVICE_NATIVE_ENDIAN
,
252 .min_access_size
= 1,
253 .max_access_size
= 1,
257 static void slavio_aux2_mem_writeb(void *opaque
, hwaddr addr
,
258 uint64_t val
, unsigned size
)
260 MiscState
*s
= opaque
;
262 val
&= AUX2_PWRINTCLR
| AUX2_PWROFF
;
263 trace_slavio_aux2_mem_writeb(val
& 0xff);
264 val
|= s
->aux2
& AUX2_PWRFAIL
;
265 if (val
& AUX2_PWRINTCLR
) // Clear Power Fail int
268 if (val
& AUX2_PWROFF
)
269 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
270 slavio_misc_update_irq(s
);
273 static uint64_t slavio_aux2_mem_readb(void *opaque
, hwaddr addr
,
276 MiscState
*s
= opaque
;
280 trace_slavio_aux2_mem_readb(ret
);
284 static const MemoryRegionOps slavio_aux2_mem_ops
= {
285 .read
= slavio_aux2_mem_readb
,
286 .write
= slavio_aux2_mem_writeb
,
287 .endianness
= DEVICE_NATIVE_ENDIAN
,
289 .min_access_size
= 1,
290 .max_access_size
= 1,
294 static void apc_mem_writeb(void *opaque
, hwaddr addr
,
295 uint64_t val
, unsigned size
)
297 APCState
*s
= opaque
;
299 trace_apc_mem_writeb(val
& 0xff);
300 qemu_irq_raise(s
->cpu_halt
);
303 static uint64_t apc_mem_readb(void *opaque
, hwaddr addr
,
308 trace_apc_mem_readb(ret
);
312 static const MemoryRegionOps apc_mem_ops
= {
313 .read
= apc_mem_readb
,
314 .write
= apc_mem_writeb
,
315 .endianness
= DEVICE_NATIVE_ENDIAN
,
317 .min_access_size
= 1,
318 .max_access_size
= 1,
322 static uint64_t slavio_sysctrl_mem_readl(void *opaque
, hwaddr addr
,
325 MiscState
*s
= opaque
;
335 trace_slavio_sysctrl_mem_readl(ret
);
339 static void slavio_sysctrl_mem_writel(void *opaque
, hwaddr addr
,
340 uint64_t val
, unsigned size
)
342 MiscState
*s
= opaque
;
344 trace_slavio_sysctrl_mem_writel(val
);
347 if (val
& SYS_RESET
) {
348 s
->sysctrl
= SYS_RESETSTAT
;
349 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
357 static const MemoryRegionOps slavio_sysctrl_mem_ops
= {
358 .read
= slavio_sysctrl_mem_readl
,
359 .write
= slavio_sysctrl_mem_writel
,
360 .endianness
= DEVICE_NATIVE_ENDIAN
,
362 .min_access_size
= 4,
363 .max_access_size
= 4,
367 static uint64_t slavio_led_mem_readw(void *opaque
, hwaddr addr
,
370 MiscState
*s
= opaque
;
380 trace_slavio_led_mem_readw(ret
);
384 static void slavio_led_mem_writew(void *opaque
, hwaddr addr
,
385 uint64_t val
, unsigned size
)
387 MiscState
*s
= opaque
;
389 trace_slavio_led_mem_writew(val
& 0xffff);
399 static const MemoryRegionOps slavio_led_mem_ops
= {
400 .read
= slavio_led_mem_readw
,
401 .write
= slavio_led_mem_writew
,
402 .endianness
= DEVICE_NATIVE_ENDIAN
,
404 .min_access_size
= 2,
405 .max_access_size
= 2,
409 static const VMStateDescription vmstate_misc
= {
410 .name
="slavio_misc",
412 .minimum_version_id
= 1,
413 .fields
= (VMStateField
[]) {
414 VMSTATE_UINT32(dummy
, MiscState
),
415 VMSTATE_UINT8(config
, MiscState
),
416 VMSTATE_UINT8(aux1
, MiscState
),
417 VMSTATE_UINT8(aux2
, MiscState
),
418 VMSTATE_UINT8(diag
, MiscState
),
419 VMSTATE_UINT8(mctrl
, MiscState
),
420 VMSTATE_UINT8(sysctrl
, MiscState
),
421 VMSTATE_END_OF_LIST()
425 static void apc_init(Object
*obj
)
427 APCState
*s
= APC(obj
);
428 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
430 sysbus_init_irq(dev
, &s
->cpu_halt
);
432 /* Power management (APC) XXX: not a Slavio device */
433 memory_region_init_io(&s
->iomem
, obj
, &apc_mem_ops
, s
,
435 sysbus_init_mmio(dev
, &s
->iomem
);
438 static void slavio_misc_init(Object
*obj
)
440 DeviceState
*dev
= DEVICE(obj
);
441 MiscState
*s
= SLAVIO_MISC(obj
);
442 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
444 sysbus_init_irq(sbd
, &s
->irq
);
445 sysbus_init_irq(sbd
, &s
->fdc_tc
);
447 /* 8 bit registers */
449 memory_region_init_io(&s
->cfg_iomem
, obj
, &slavio_cfg_mem_ops
, s
,
450 "configuration", MISC_SIZE
);
451 sysbus_init_mmio(sbd
, &s
->cfg_iomem
);
454 memory_region_init_io(&s
->diag_iomem
, obj
, &slavio_diag_mem_ops
, s
,
455 "diagnostic", MISC_SIZE
);
456 sysbus_init_mmio(sbd
, &s
->diag_iomem
);
459 memory_region_init_io(&s
->mdm_iomem
, obj
, &slavio_mdm_mem_ops
, s
,
461 sysbus_init_mmio(sbd
, &s
->mdm_iomem
);
463 /* 16 bit registers */
464 /* ss600mp diag LEDs */
465 memory_region_init_io(&s
->led_iomem
, obj
, &slavio_led_mem_ops
, s
,
467 sysbus_init_mmio(sbd
, &s
->led_iomem
);
469 /* 32 bit registers */
471 memory_region_init_io(&s
->sysctrl_iomem
, obj
, &slavio_sysctrl_mem_ops
, s
,
472 "system-control", SYSCTRL_SIZE
);
473 sysbus_init_mmio(sbd
, &s
->sysctrl_iomem
);
475 /* AUX 1 (Misc System Functions) */
476 memory_region_init_io(&s
->aux1_iomem
, obj
, &slavio_aux1_mem_ops
, s
,
477 "misc-system-functions", MISC_SIZE
);
478 sysbus_init_mmio(sbd
, &s
->aux1_iomem
);
480 /* AUX 2 (Software Powerdown Control) */
481 memory_region_init_io(&s
->aux2_iomem
, obj
, &slavio_aux2_mem_ops
, s
,
482 "software-powerdown-control", MISC_SIZE
);
483 sysbus_init_mmio(sbd
, &s
->aux2_iomem
);
485 qdev_init_gpio_in(dev
, slavio_set_power_fail
, 1);
488 static void slavio_misc_class_init(ObjectClass
*klass
, void *data
)
490 DeviceClass
*dc
= DEVICE_CLASS(klass
);
492 dc
->reset
= slavio_misc_reset
;
493 dc
->vmsd
= &vmstate_misc
;
496 static const TypeInfo slavio_misc_info
= {
497 .name
= TYPE_SLAVIO_MISC
,
498 .parent
= TYPE_SYS_BUS_DEVICE
,
499 .instance_size
= sizeof(MiscState
),
500 .instance_init
= slavio_misc_init
,
501 .class_init
= slavio_misc_class_init
,
504 static const TypeInfo apc_info
= {
506 .parent
= TYPE_SYS_BUS_DEVICE
,
507 .instance_size
= sizeof(MiscState
),
508 .instance_init
= apc_init
,
511 static void slavio_misc_register_types(void)
513 type_register_static(&slavio_misc_info
);
514 type_register_static(&apc_info
);
517 type_init(slavio_misc_register_types
)