2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
34 #include "firmware_abi.h"
41 #include "exec-memory.h"
48 #define CPUIRQ_DPRINTF(fmt, ...) \
49 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
51 #define CPUIRQ_DPRINTF(fmt, ...)
55 #define EBUS_DPRINTF(fmt, ...) \
56 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
58 #define EBUS_DPRINTF(fmt, ...)
62 #define TIMER_DPRINTF(fmt, ...) \
63 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
65 #define TIMER_DPRINTF(fmt, ...)
68 #define KERNEL_LOAD_ADDR 0x00404000
69 #define CMDLINE_ADDR 0x003ff000
70 #define INITRD_LOAD_ADDR 0x00300000
71 #define PROM_SIZE_MAX (4 * 1024 * 1024)
72 #define PROM_VADDR 0x000ffd00000ULL
73 #define APB_SPECIAL_BASE 0x1fe00000000ULL
74 #define APB_MEM_BASE 0x1ff00000000ULL
75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
76 #define PROM_FILENAME "openbios-sparc64"
77 #define NVRAM_SIZE 0x2000
79 #define BIOS_CFG_IOPORT 0x510
80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
86 #define TICK_MAX 0x7fffffffffffffffULL
89 const char * const default_cpu_model
;
92 uint64_t console_serial_base
;
95 typedef struct EbusState
{
101 int DMA_get_channel_mode (int nchan
)
105 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
109 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
113 void DMA_hold_DREQ (int nchan
) {}
114 void DMA_release_DREQ (int nchan
) {}
115 void DMA_schedule(int nchan
) {}
117 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
121 void DMA_register_channel (int nchan
,
122 DMA_transfer_handler transfer_handler
,
127 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
129 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
133 static int sun4u_NVRAM_set_params(M48t59State
*nvram
, uint16_t NVRAM_size
,
134 const char *arch
, ram_addr_t RAM_size
,
135 const char *boot_devices
,
136 uint32_t kernel_image
, uint32_t kernel_size
,
138 uint32_t initrd_image
, uint32_t initrd_size
,
139 uint32_t NVRAM_image
,
140 int width
, int height
, int depth
,
141 const uint8_t *macaddr
)
145 uint8_t image
[0x1ff0];
146 struct OpenBIOS_nvpart_v1
*part_header
;
148 memset(image
, '\0', sizeof(image
));
152 // OpenBIOS nvram variables
153 // Variable partition
154 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
155 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
156 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
158 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
159 for (i
= 0; i
< nb_prom_envs
; i
++)
160 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
165 end
= start
+ ((end
- start
+ 15) & ~15);
166 OpenBIOS_finish_partition(part_header
, end
- start
);
170 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
171 part_header
->signature
= OPENBIOS_PART_FREE
;
172 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
175 OpenBIOS_finish_partition(part_header
, end
- start
);
177 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
179 for (i
= 0; i
< sizeof(image
); i
++)
180 m48t59_write(nvram
, i
, image
[i
]);
184 static unsigned long sun4u_load_kernel(const char *kernel_filename
,
185 const char *initrd_filename
,
186 ram_addr_t RAM_size
, long *initrd_size
)
193 linux_boot
= (kernel_filename
!= NULL
);
204 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, NULL
,
205 NULL
, NULL
, 1, ELF_MACHINE
, 0);
207 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
208 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
211 kernel_size
= load_image_targphys(kernel_filename
,
213 RAM_size
- KERNEL_LOAD_ADDR
);
214 if (kernel_size
< 0) {
215 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
222 if (initrd_filename
) {
223 *initrd_size
= load_image_targphys(initrd_filename
,
225 RAM_size
- INITRD_LOAD_ADDR
);
226 if (*initrd_size
< 0) {
227 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
232 if (*initrd_size
> 0) {
233 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
234 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
235 if (ldl_p(ptr
+ 8) == 0x48647253) { /* HdrS */
236 stl_p(ptr
+ 24, INITRD_LOAD_ADDR
+ KERNEL_LOAD_ADDR
- 0x4000);
237 stl_p(ptr
+ 28, *initrd_size
);
246 void cpu_check_irqs(CPUState
*env
)
248 uint32_t pil
= env
->pil_in
|
249 (env
->softint
& ~(SOFTINT_TIMER
| SOFTINT_STIMER
));
251 /* check if TM or SM in SOFTINT are set
252 setting these also causes interrupt 14 */
253 if (env
->softint
& (SOFTINT_TIMER
| SOFTINT_STIMER
)) {
257 /* The bit corresponding to psrpil is (1<< psrpil), the next bit
259 if (pil
< (2 << env
->psrpil
)){
260 if (env
->interrupt_request
& CPU_INTERRUPT_HARD
) {
261 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
262 env
->interrupt_index
);
263 env
->interrupt_index
= 0;
264 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
269 if (cpu_interrupts_enabled(env
)) {
273 for (i
= 15; i
> env
->psrpil
; i
--) {
274 if (pil
& (1 << i
)) {
275 int old_interrupt
= env
->interrupt_index
;
276 int new_interrupt
= TT_EXTINT
| i
;
278 if (env
->tl
> 0 && cpu_tsptr(env
)->tt
> new_interrupt
) {
279 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
280 "current %x >= pending %x\n",
281 env
->tl
, cpu_tsptr(env
)->tt
, new_interrupt
);
282 } else if (old_interrupt
!= new_interrupt
) {
283 env
->interrupt_index
= new_interrupt
;
284 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i
,
285 old_interrupt
, new_interrupt
);
286 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
291 } else if (env
->interrupt_request
& CPU_INTERRUPT_HARD
) {
292 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
293 "current interrupt %x\n",
294 pil
, env
->pil_in
, env
->softint
, env
->interrupt_index
);
295 env
->interrupt_index
= 0;
296 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
300 static void cpu_kick_irq(CPUState
*env
)
307 static void cpu_set_irq(void *opaque
, int irq
, int level
)
309 CPUState
*env
= opaque
;
312 CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq
);
313 env
->pil_in
|= 1 << irq
;
316 CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq
);
317 env
->pil_in
&= ~(1 << irq
);
322 typedef struct ResetData
{
327 void cpu_put_timer(QEMUFile
*f
, CPUTimer
*s
)
329 qemu_put_be32s(f
, &s
->frequency
);
330 qemu_put_be32s(f
, &s
->disabled
);
331 qemu_put_be64s(f
, &s
->disabled_mask
);
332 qemu_put_sbe64s(f
, &s
->clock_offset
);
334 qemu_put_timer(f
, s
->qtimer
);
337 void cpu_get_timer(QEMUFile
*f
, CPUTimer
*s
)
339 qemu_get_be32s(f
, &s
->frequency
);
340 qemu_get_be32s(f
, &s
->disabled
);
341 qemu_get_be64s(f
, &s
->disabled_mask
);
342 qemu_get_sbe64s(f
, &s
->clock_offset
);
344 qemu_get_timer(f
, s
->qtimer
);
347 static CPUTimer
* cpu_timer_create(const char* name
, CPUState
*env
,
348 QEMUBHFunc
*cb
, uint32_t frequency
,
349 uint64_t disabled_mask
)
351 CPUTimer
*timer
= g_malloc0(sizeof (CPUTimer
));
354 timer
->frequency
= frequency
;
355 timer
->disabled_mask
= disabled_mask
;
358 timer
->clock_offset
= qemu_get_clock_ns(vm_clock
);
360 timer
->qtimer
= qemu_new_timer_ns(vm_clock
, cb
, env
);
365 static void cpu_timer_reset(CPUTimer
*timer
)
368 timer
->clock_offset
= qemu_get_clock_ns(vm_clock
);
370 qemu_del_timer(timer
->qtimer
);
373 static void main_cpu_reset(void *opaque
)
375 ResetData
*s
= (ResetData
*)opaque
;
376 CPUState
*env
= s
->env
;
377 static unsigned int nr_resets
;
379 cpu_state_reset(env
);
381 cpu_timer_reset(env
->tick
);
382 cpu_timer_reset(env
->stick
);
383 cpu_timer_reset(env
->hstick
);
385 env
->gregs
[1] = 0; // Memory start
386 env
->gregs
[2] = ram_size
; // Memory size
387 env
->gregs
[3] = 0; // Machine description XXX
388 if (nr_resets
++ == 0) {
390 env
->pc
= s
->prom_addr
+ 0x20ULL
;
392 env
->pc
= s
->prom_addr
+ 0x40ULL
;
394 env
->npc
= env
->pc
+ 4;
397 static void tick_irq(void *opaque
)
399 CPUState
*env
= opaque
;
401 CPUTimer
* timer
= env
->tick
;
403 if (timer
->disabled
) {
404 CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
407 CPUIRQ_DPRINTF("tick: fire\n");
410 env
->softint
|= SOFTINT_TIMER
;
414 static void stick_irq(void *opaque
)
416 CPUState
*env
= opaque
;
418 CPUTimer
* timer
= env
->stick
;
420 if (timer
->disabled
) {
421 CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
424 CPUIRQ_DPRINTF("stick: fire\n");
427 env
->softint
|= SOFTINT_STIMER
;
431 static void hstick_irq(void *opaque
)
433 CPUState
*env
= opaque
;
435 CPUTimer
* timer
= env
->hstick
;
437 if (timer
->disabled
) {
438 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
441 CPUIRQ_DPRINTF("hstick: fire\n");
444 env
->softint
|= SOFTINT_STIMER
;
448 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks
, uint32_t frequency
)
450 return muldiv64(cpu_ticks
, get_ticks_per_sec(), frequency
);
453 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks
, uint32_t frequency
)
455 return muldiv64(timer_ticks
, frequency
, get_ticks_per_sec());
458 void cpu_tick_set_count(CPUTimer
*timer
, uint64_t count
)
460 uint64_t real_count
= count
& ~timer
->disabled_mask
;
461 uint64_t disabled_bit
= count
& timer
->disabled_mask
;
463 int64_t vm_clock_offset
= qemu_get_clock_ns(vm_clock
) -
464 cpu_to_timer_ticks(real_count
, timer
->frequency
);
466 TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
467 timer
->name
, real_count
,
468 timer
->disabled
?"disabled":"enabled", timer
);
470 timer
->disabled
= disabled_bit
? 1 : 0;
471 timer
->clock_offset
= vm_clock_offset
;
474 uint64_t cpu_tick_get_count(CPUTimer
*timer
)
476 uint64_t real_count
= timer_to_cpu_ticks(
477 qemu_get_clock_ns(vm_clock
) - timer
->clock_offset
,
480 TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
481 timer
->name
, real_count
,
482 timer
->disabled
?"disabled":"enabled", timer
);
485 real_count
|= timer
->disabled_mask
;
490 void cpu_tick_set_limit(CPUTimer
*timer
, uint64_t limit
)
492 int64_t now
= qemu_get_clock_ns(vm_clock
);
494 uint64_t real_limit
= limit
& ~timer
->disabled_mask
;
495 timer
->disabled
= (limit
& timer
->disabled_mask
) ? 1 : 0;
497 int64_t expires
= cpu_to_timer_ticks(real_limit
, timer
->frequency
) +
504 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
505 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
506 timer
->name
, real_limit
,
507 timer
->disabled
?"disabled":"enabled",
509 timer_to_cpu_ticks(now
- timer
->clock_offset
,
511 timer_to_cpu_ticks(expires
- now
, timer
->frequency
));
514 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
516 qemu_del_timer(timer
->qtimer
);
517 } else if (timer
->disabled
) {
518 qemu_del_timer(timer
->qtimer
);
520 qemu_mod_timer(timer
->qtimer
, expires
);
524 static void dummy_isa_irq_handler(void *opaque
, int n
, int level
)
528 /* EBUS (Eight bit bus) bridge */
530 pci_ebus_init(PCIBus
*bus
, int devfn
)
536 pci_dev
= pci_create_simple(bus
, devfn
, "ebus");
537 isa_bus
= DO_UPCAST(ISABus
, qbus
,
538 qdev_get_child_bus(&pci_dev
->qdev
, "isa.0"));
539 isa_irq
= qemu_allocate_irqs(dummy_isa_irq_handler
, NULL
, 16);
540 isa_bus_irqs(isa_bus
, isa_irq
);
545 pci_ebus_init1(PCIDevice
*pci_dev
)
547 EbusState
*s
= DO_UPCAST(EbusState
, pci_dev
, pci_dev
);
549 isa_bus_new(&pci_dev
->qdev
, pci_address_space_io(pci_dev
));
551 pci_dev
->config
[0x04] = 0x06; // command = bus master, pci mem
552 pci_dev
->config
[0x05] = 0x00;
553 pci_dev
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
554 pci_dev
->config
[0x07] = 0x03; // status = medium devsel
555 pci_dev
->config
[0x09] = 0x00; // programming i/f
556 pci_dev
->config
[0x0D] = 0x0a; // latency_timer
558 isa_mmio_setup(&s
->bar0
, 0x1000000);
559 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
560 isa_mmio_setup(&s
->bar1
, 0x800000);
561 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
565 static void ebus_class_init(ObjectClass
*klass
, void *data
)
567 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
569 k
->init
= pci_ebus_init1
;
570 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
571 k
->device_id
= PCI_DEVICE_ID_SUN_EBUS
;
573 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
576 static TypeInfo ebus_info
= {
578 .parent
= TYPE_PCI_DEVICE
,
579 .instance_size
= sizeof(EbusState
),
580 .class_init
= ebus_class_init
,
583 typedef struct PROMState
{
588 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
590 target_phys_addr_t
*base_addr
= (target_phys_addr_t
*)opaque
;
591 return addr
+ *base_addr
- PROM_VADDR
;
594 /* Boot PROM (OpenBIOS) */
595 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
602 dev
= qdev_create(NULL
, "openprom");
603 qdev_init_nofail(dev
);
604 s
= sysbus_from_qdev(dev
);
606 sysbus_mmio_map(s
, 0, addr
);
609 if (bios_name
== NULL
) {
610 bios_name
= PROM_FILENAME
;
612 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
614 ret
= load_elf(filename
, translate_prom_address
, &addr
,
615 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
616 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
617 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
623 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
624 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
629 static int prom_init1(SysBusDevice
*dev
)
631 PROMState
*s
= FROM_SYSBUS(PROMState
, dev
);
633 memory_region_init_ram(&s
->prom
, "sun4u.prom", PROM_SIZE_MAX
);
634 vmstate_register_ram_global(&s
->prom
);
635 memory_region_set_readonly(&s
->prom
, true);
636 sysbus_init_mmio(dev
, &s
->prom
);
640 static Property prom_properties
[] = {
641 {/* end of property list */},
644 static void prom_class_init(ObjectClass
*klass
, void *data
)
646 DeviceClass
*dc
= DEVICE_CLASS(klass
);
647 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
649 k
->init
= prom_init1
;
650 dc
->props
= prom_properties
;
653 static TypeInfo prom_info
= {
655 .parent
= TYPE_SYS_BUS_DEVICE
,
656 .instance_size
= sizeof(PROMState
),
657 .class_init
= prom_class_init
,
661 typedef struct RamDevice
669 static int ram_init1(SysBusDevice
*dev
)
671 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
673 memory_region_init_ram(&d
->ram
, "sun4u.ram", d
->size
);
674 vmstate_register_ram_global(&d
->ram
);
675 sysbus_init_mmio(dev
, &d
->ram
);
679 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
)
686 dev
= qdev_create(NULL
, "memory");
687 s
= sysbus_from_qdev(dev
);
689 d
= FROM_SYSBUS(RamDevice
, s
);
691 qdev_init_nofail(dev
);
693 sysbus_mmio_map(s
, 0, addr
);
696 static Property ram_properties
[] = {
697 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
698 DEFINE_PROP_END_OF_LIST(),
701 static void ram_class_init(ObjectClass
*klass
, void *data
)
703 DeviceClass
*dc
= DEVICE_CLASS(klass
);
704 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
707 dc
->props
= ram_properties
;
710 static TypeInfo ram_info
= {
712 .parent
= TYPE_SYS_BUS_DEVICE
,
713 .instance_size
= sizeof(RamDevice
),
714 .class_init
= ram_class_init
,
717 static CPUState
*cpu_devinit(const char *cpu_model
, const struct hwdef
*hwdef
)
720 ResetData
*reset_info
;
722 uint32_t tick_frequency
= 100*1000000;
723 uint32_t stick_frequency
= 100*1000000;
724 uint32_t hstick_frequency
= 100*1000000;
727 cpu_model
= hwdef
->default_cpu_model
;
728 env
= cpu_init(cpu_model
);
730 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
734 env
->tick
= cpu_timer_create("tick", env
, tick_irq
,
735 tick_frequency
, TICK_NPT_MASK
);
737 env
->stick
= cpu_timer_create("stick", env
, stick_irq
,
738 stick_frequency
, TICK_INT_DIS
);
740 env
->hstick
= cpu_timer_create("hstick", env
, hstick_irq
,
741 hstick_frequency
, TICK_INT_DIS
);
743 reset_info
= g_malloc0(sizeof(ResetData
));
744 reset_info
->env
= env
;
745 reset_info
->prom_addr
= hwdef
->prom_addr
;
746 qemu_register_reset(main_cpu_reset
, reset_info
);
751 static void sun4uv_init(MemoryRegion
*address_space_mem
,
753 const char *boot_devices
,
754 const char *kernel_filename
, const char *kernel_cmdline
,
755 const char *initrd_filename
, const char *cpu_model
,
756 const struct hwdef
*hwdef
)
761 long initrd_size
, kernel_size
;
762 PCIBus
*pci_bus
, *pci_bus2
, *pci_bus3
;
765 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
766 DriveInfo
*fd
[MAX_FD
];
770 env
= cpu_devinit(cpu_model
, hwdef
);
773 ram_init(0, RAM_size
);
775 prom_init(hwdef
->prom_addr
, bios_name
);
778 irq
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
779 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, irq
, &pci_bus2
,
781 pci_vga_init(pci_bus
);
783 // XXX Should be pci_bus3
784 isa_bus
= pci_ebus_init(pci_bus
, -1);
787 if (hwdef
->console_serial_base
) {
788 serial_mm_init(address_space_mem
, hwdef
->console_serial_base
, 0,
789 NULL
, 115200, serial_hds
[i
], DEVICE_BIG_ENDIAN
);
792 for(; i
< MAX_SERIAL_PORTS
; i
++) {
794 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
798 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
799 if (parallel_hds
[i
]) {
800 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
804 for(i
= 0; i
< nb_nics
; i
++)
805 pci_nic_init_nofail(&nd_table
[i
], "ne2k_pci", NULL
);
807 ide_drive_get(hd
, MAX_IDE_BUS
);
809 pci_cmd646_ide_init(pci_bus
, hd
, 1);
811 isa_create_simple(isa_bus
, "i8042");
812 for(i
= 0; i
< MAX_FD
; i
++) {
813 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
815 fdctrl_init_isa(isa_bus
, fd
);
816 nvram
= m48t59_init_isa(isa_bus
, 0x0074, NVRAM_SIZE
, 59);
819 kernel_size
= sun4u_load_kernel(kernel_filename
, initrd_filename
,
820 ram_size
, &initrd_size
);
822 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", RAM_size
, boot_devices
,
823 KERNEL_LOAD_ADDR
, kernel_size
,
825 INITRD_LOAD_ADDR
, initrd_size
,
826 /* XXX: need an option to load a NVRAM image */
828 graphic_width
, graphic_height
, graphic_depth
,
829 (uint8_t *)&nd_table
[0].macaddr
);
831 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
832 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
833 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
834 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
835 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
836 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
837 if (kernel_cmdline
) {
838 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
839 strlen(kernel_cmdline
) + 1);
840 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
841 (uint8_t*)strdup(kernel_cmdline
),
842 strlen(kernel_cmdline
) + 1);
844 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
846 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
847 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
848 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_devices
[0]);
850 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
851 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
852 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
854 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
863 static const struct hwdef hwdefs
[] = {
864 /* Sun4u generic PC-like machine */
866 .default_cpu_model
= "TI UltraSparc IIi",
867 .machine_id
= sun4u_id
,
868 .prom_addr
= 0x1fff0000000ULL
,
869 .console_serial_base
= 0,
871 /* Sun4v generic PC-like machine */
873 .default_cpu_model
= "Sun UltraSparc T1",
874 .machine_id
= sun4v_id
,
875 .prom_addr
= 0x1fff0000000ULL
,
876 .console_serial_base
= 0,
878 /* Sun4v generic Niagara machine */
880 .default_cpu_model
= "Sun UltraSparc T1",
881 .machine_id
= niagara_id
,
882 .prom_addr
= 0xfff0000000ULL
,
883 .console_serial_base
= 0xfff0c2c000ULL
,
887 /* Sun4u hardware initialisation */
888 static void sun4u_init(ram_addr_t RAM_size
,
889 const char *boot_devices
,
890 const char *kernel_filename
, const char *kernel_cmdline
,
891 const char *initrd_filename
, const char *cpu_model
)
893 sun4uv_init(get_system_memory(), RAM_size
, boot_devices
, kernel_filename
,
894 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[0]);
897 /* Sun4v hardware initialisation */
898 static void sun4v_init(ram_addr_t RAM_size
,
899 const char *boot_devices
,
900 const char *kernel_filename
, const char *kernel_cmdline
,
901 const char *initrd_filename
, const char *cpu_model
)
903 sun4uv_init(get_system_memory(), RAM_size
, boot_devices
, kernel_filename
,
904 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[1]);
907 /* Niagara hardware initialisation */
908 static void niagara_init(ram_addr_t RAM_size
,
909 const char *boot_devices
,
910 const char *kernel_filename
, const char *kernel_cmdline
,
911 const char *initrd_filename
, const char *cpu_model
)
913 sun4uv_init(get_system_memory(), RAM_size
, boot_devices
, kernel_filename
,
914 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[2]);
917 static QEMUMachine sun4u_machine
= {
919 .desc
= "Sun4u platform",
921 .max_cpus
= 1, // XXX for now
925 static QEMUMachine sun4v_machine
= {
927 .desc
= "Sun4v platform",
929 .max_cpus
= 1, // XXX for now
932 static QEMUMachine niagara_machine
= {
934 .desc
= "Sun4v platform, Niagara",
935 .init
= niagara_init
,
936 .max_cpus
= 1, // XXX for now
939 static void sun4u_register_types(void)
941 type_register_static(&ebus_info
);
942 type_register_static(&prom_info
);
943 type_register_static(&ram_info
);
946 static void sun4u_machine_init(void)
948 qemu_register_machine(&sun4u_machine
);
949 qemu_register_machine(&sun4v_machine
);
950 qemu_register_machine(&niagara_machine
);
953 type_init(sun4u_register_types
)
954 machine_init(sun4u_machine_init
);