target/s390x/ioinst.c

   1 /*
   2  * I/O instructions for S/390
   3  *
   4  * Copyright 2012, 2015 IBM Corp.
   5  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8  * your option) any later version. See the COPYING file in the top-level
   9  * directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13
  14 #include "cpu.h"
  15 #include "internal.h"
  16 #include "hw/s390x/ioinst.h"
  17 #include "trace.h"
  18 #include "hw/s390x/s390-pci-bus.h"
  19
  20 int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
  21                                  int *schid)
  22 {
  23     if (!IOINST_SCHID_ONE(value)) {
  24         return -EINVAL;
  25     }
  26     if (!IOINST_SCHID_M(value)) {
  27         if (IOINST_SCHID_CSSID(value)) {
  28             return -EINVAL;
  29         }
  30         *cssid = 0;
  31         *m = 0;
  32     } else {
  33         *cssid = IOINST_SCHID_CSSID(value);
  34         *m = 1;
  35     }
  36     *ssid = IOINST_SCHID_SSID(value);
  37     *schid = IOINST_SCHID_NR(value);
  38     return 0;
  39 }
  40
  41 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra)
  42 {
  43     int cssid, ssid, schid, m;
  44     SubchDev *sch;
  45
  46     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  47         s390_program_interrupt(&cpu->env, PGM_OPERAND, 4, ra);
  48         return;
  49     }
  50     trace_ioinst_sch_id("xsch", cssid, ssid, schid);
  51     sch = css_find_subch(m, cssid, ssid, schid);
  52     if (!sch || !css_subch_visible(sch)) {
  53         setcc(cpu, 3);
  54         return;
  55     }
  56     setcc(cpu, css_do_xsch(sch));
  57 }
  58
  59 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra)
  60 {
  61     int cssid, ssid, schid, m;
  62     SubchDev *sch;
  63
  64     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  65         s390_program_interrupt(&cpu->env, PGM_OPERAND, 4, ra);
  66         return;
  67     }
  68     trace_ioinst_sch_id("csch", cssid, ssid, schid);
  69     sch = css_find_subch(m, cssid, ssid, schid);
  70     if (!sch || !css_subch_visible(sch)) {
  71         setcc(cpu, 3);
  72         return;
  73     }
  74     setcc(cpu, css_do_csch(sch));
  75 }
  76
  77 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra)
  78 {
  79     int cssid, ssid, schid, m;
  80     SubchDev *sch;
  81
  82     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  83         s390_program_interrupt(&cpu->env, PGM_OPERAND, 4, ra);
  84         return;
  85     }
  86     trace_ioinst_sch_id("hsch", cssid, ssid, schid);
  87     sch = css_find_subch(m, cssid, ssid, schid);
  88     if (!sch || !css_subch_visible(sch)) {
  89         setcc(cpu, 3);
  90         return;
  91     }
  92     setcc(cpu, css_do_hsch(sch));
  93 }
  94
  95 static int ioinst_schib_valid(SCHIB *schib)
  96 {
  97     if ((be16_to_cpu(schib->pmcw.flags) & PMCW_FLAGS_MASK_INVALID) ||
  98         (be32_to_cpu(schib->pmcw.chars) & PMCW_CHARS_MASK_INVALID)) {
  99         return 0;
 100     }
 101     /* Disallow extended measurements for now. */
 102     if (be32_to_cpu(schib->pmcw.chars) & PMCW_CHARS_MASK_XMWME) {
 103         return 0;
 104     }
 105     return 1;
 106 }
 107
 108 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra)
 109 {
 110     int cssid, ssid, schid, m;
 111     SubchDev *sch;
 112     SCHIB schib;
 113     uint64_t addr;
 114     CPUS390XState *env = &cpu->env;
 115     uint8_t ar;
 116
 117     addr = decode_basedisp_s(env, ipb, &ar);
 118     if (addr & 3) {
 119         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 120         return;
 121     }
 122     if (s390_cpu_virt_mem_read(cpu, addr, ar, &schib, sizeof(schib))) {
 123         return;
 124     }
 125     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 126         !ioinst_schib_valid(&schib)) {
 127         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 128         return;
 129     }
 130     trace_ioinst_sch_id("msch", cssid, ssid, schid);
 131     sch = css_find_subch(m, cssid, ssid, schid);
 132     if (!sch || !css_subch_visible(sch)) {
 133         setcc(cpu, 3);
 134         return;
 135     }
 136     setcc(cpu, css_do_msch(sch, &schib));
 137 }
 138
 139 static void copy_orb_from_guest(ORB *dest, const ORB *src)
 140 {
 141     dest->intparm = be32_to_cpu(src->intparm);
 142     dest->ctrl0 = be16_to_cpu(src->ctrl0);
 143     dest->lpm = src->lpm;
 144     dest->ctrl1 = src->ctrl1;
 145     dest->cpa = be32_to_cpu(src->cpa);
 146 }
 147
 148 static int ioinst_orb_valid(ORB *orb)
 149 {
 150     if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
 151         (orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
 152         return 0;
 153     }
 154     /* We don't support MIDA. */
 155     if (orb->ctrl1 & ORB_CTRL1_MASK_MIDAW) {
 156         return 0;
 157     }
 158     if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
 159         return 0;
 160     }
 161     return 1;
 162 }
 163
 164 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra)
 165 {
 166     int cssid, ssid, schid, m;
 167     SubchDev *sch;
 168     ORB orig_orb, orb;
 169     uint64_t addr;
 170     CPUS390XState *env = &cpu->env;
 171     uint8_t ar;
 172
 173     addr = decode_basedisp_s(env, ipb, &ar);
 174     if (addr & 3) {
 175         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 176         return;
 177     }
 178     if (s390_cpu_virt_mem_read(cpu, addr, ar, &orig_orb, sizeof(orb))) {
 179         return;
 180     }
 181     copy_orb_from_guest(&orb, &orig_orb);
 182     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 183         !ioinst_orb_valid(&orb)) {
 184         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 185         return;
 186     }
 187     trace_ioinst_sch_id("ssch", cssid, ssid, schid);
 188     sch = css_find_subch(m, cssid, ssid, schid);
 189     if (!sch || !css_subch_visible(sch)) {
 190         setcc(cpu, 3);
 191         return;
 192     }
 193     setcc(cpu, css_do_ssch(sch, &orb));
 194 }
 195
 196 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb, uintptr_t ra)
 197 {
 198     CRW crw;
 199     uint64_t addr;
 200     int cc;
 201     CPUS390XState *env = &cpu->env;
 202     uint8_t ar;
 203
 204     addr = decode_basedisp_s(env, ipb, &ar);
 205     if (addr & 3) {
 206         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 207         return;
 208     }
 209
 210     cc = css_do_stcrw(&crw);
 211     /* 0 - crw stored, 1 - zeroes stored */
 212
 213     if (s390_cpu_virt_mem_write(cpu, addr, ar, &crw, sizeof(crw)) == 0) {
 214         setcc(cpu, cc);
 215     } else if (cc == 0) {
 216         /* Write failed: requeue CRW since STCRW is a suppressing instruction */
 217         css_undo_stcrw(&crw);
 218     }
 219 }
 220
 221 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
 222                          uintptr_t ra)
 223 {
 224     int cssid, ssid, schid, m;
 225     SubchDev *sch;
 226     uint64_t addr;
 227     int cc;
 228     SCHIB schib;
 229     CPUS390XState *env = &cpu->env;
 230     uint8_t ar;
 231
 232     addr = decode_basedisp_s(env, ipb, &ar);
 233     if (addr & 3) {
 234         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 235         return;
 236     }
 237
 238     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 239         /*
 240          * As operand exceptions have a lower priority than access exceptions,
 241          * we check whether the memory area is writeable (injecting the
 242          * access execption if it is not) first.
 243          */
 244         if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {
 245             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 246         }
 247         return;
 248     }
 249     trace_ioinst_sch_id("stsch", cssid, ssid, schid);
 250     sch = css_find_subch(m, cssid, ssid, schid);
 251     if (sch) {
 252         if (css_subch_visible(sch)) {
 253             css_do_stsch(sch, &schib);
 254             cc = 0;
 255         } else {
 256             /* Indicate no more subchannels in this css/ss */
 257             cc = 3;
 258         }
 259     } else {
 260         if (css_schid_final(m, cssid, ssid, schid)) {
 261             cc = 3; /* No more subchannels in this css/ss */
 262         } else {
 263             /* Store an empty schib. */
 264             memset(&schib, 0, sizeof(schib));
 265             cc = 0;
 266         }
 267     }
 268     if (cc != 3) {
 269         if (s390_cpu_virt_mem_write(cpu, addr, ar, &schib,
 270                                     sizeof(schib)) != 0) {
 271             return;
 272         }
 273     } else {
 274         /* Access exceptions have a higher priority than cc3 */
 275         if (s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib)) != 0) {
 276             return;
 277         }
 278     }
 279     setcc(cpu, cc);
 280 }
 281
 282 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra)
 283 {
 284     CPUS390XState *env = &cpu->env;
 285     int cssid, ssid, schid, m;
 286     SubchDev *sch;
 287     IRB irb;
 288     uint64_t addr;
 289     int cc, irb_len;
 290     uint8_t ar;
 291
 292     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 293         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 294         return -EIO;
 295     }
 296     trace_ioinst_sch_id("tsch", cssid, ssid, schid);
 297     addr = decode_basedisp_s(env, ipb, &ar);
 298     if (addr & 3) {
 299         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 300         return -EIO;
 301     }
 302
 303     sch = css_find_subch(m, cssid, ssid, schid);
 304     if (sch && css_subch_visible(sch)) {
 305         cc = css_do_tsch_get_irb(sch, &irb, &irb_len);
 306     } else {
 307         cc = 3;
 308     }
 309     /* 0 - status pending, 1 - not status pending, 3 - not operational */
 310     if (cc != 3) {
 311         if (s390_cpu_virt_mem_write(cpu, addr, ar, &irb, irb_len) != 0) {
 312             return -EFAULT;
 313         }
 314         css_do_tsch_update_subch(sch);
 315     } else {
 316         irb_len = sizeof(irb) - sizeof(irb.emw);
 317         /* Access exceptions have a higher priority than cc3 */
 318         if (s390_cpu_virt_mem_check_write(cpu, addr, ar, irb_len) != 0) {
 319             return -EFAULT;
 320         }
 321     }
 322
 323     setcc(cpu, cc);
 324     return 0;
 325 }
 326
 327 typedef struct ChscReq {
 328     uint16_t len;
 329     uint16_t command;
 330     uint32_t param0;
 331     uint32_t param1;
 332     uint32_t param2;
 333 } QEMU_PACKED ChscReq;
 334
 335 typedef struct ChscResp {
 336     uint16_t len;
 337     uint16_t code;
 338     uint32_t param;
 339     char data[0];
 340 } QEMU_PACKED ChscResp;
 341
 342 #define CHSC_MIN_RESP_LEN 0x0008
 343
 344 #define CHSC_SCPD 0x0002
 345 #define CHSC_SCSC 0x0010
 346 #define CHSC_SDA  0x0031
 347 #define CHSC_SEI  0x000e
 348
 349 #define CHSC_SCPD_0_M 0x20000000
 350 #define CHSC_SCPD_0_C 0x10000000
 351 #define CHSC_SCPD_0_FMT 0x0f000000
 352 #define CHSC_SCPD_0_CSSID 0x00ff0000
 353 #define CHSC_SCPD_0_RFMT 0x00000f00
 354 #define CHSC_SCPD_0_RES 0xc000f000
 355 #define CHSC_SCPD_1_RES 0xffffff00
 356 #define CHSC_SCPD_01_CHPID 0x000000ff
 357 static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
 358 {
 359     uint16_t len = be16_to_cpu(req->len);
 360     uint32_t param0 = be32_to_cpu(req->param0);
 361     uint32_t param1 = be32_to_cpu(req->param1);
 362     uint16_t resp_code;
 363     int rfmt;
 364     uint16_t cssid;
 365     uint8_t f_chpid, l_chpid;
 366     int desc_size;
 367     int m;
 368
 369     rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
 370     if ((rfmt == 0) ||  (rfmt == 1)) {
 371         rfmt = !!(param0 & CHSC_SCPD_0_C);
 372     }
 373     if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
 374         (param1 & CHSC_SCPD_1_RES) || req->param2) {
 375         resp_code = 0x0003;
 376         goto out_err;
 377     }
 378     if (param0 & CHSC_SCPD_0_FMT) {
 379         resp_code = 0x0007;
 380         goto out_err;
 381     }
 382     cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
 383     m = param0 & CHSC_SCPD_0_M;
 384     if (cssid != 0) {
 385         if (!m || !css_present(cssid)) {
 386             resp_code = 0x0008;
 387             goto out_err;
 388         }
 389     }
 390     f_chpid = param0 & CHSC_SCPD_01_CHPID;
 391     l_chpid = param1 & CHSC_SCPD_01_CHPID;
 392     if (l_chpid < f_chpid) {
 393         resp_code = 0x0003;
 394         goto out_err;
 395     }
 396     /* css_collect_chp_desc() is endian-aware */
 397     desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
 398                                      &res->data);
 399     res->code = cpu_to_be16(0x0001);
 400     res->len = cpu_to_be16(8 + desc_size);
 401     res->param = cpu_to_be32(rfmt);
 402     return;
 403
 404   out_err:
 405     res->code = cpu_to_be16(resp_code);
 406     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 407     res->param = cpu_to_be32(rfmt);
 408 }
 409
 410 #define CHSC_SCSC_0_M 0x20000000
 411 #define CHSC_SCSC_0_FMT 0x000f0000
 412 #define CHSC_SCSC_0_CSSID 0x0000ff00
 413 #define CHSC_SCSC_0_RES 0xdff000ff
 414 static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
 415 {
 416     uint16_t len = be16_to_cpu(req->len);
 417     uint32_t param0 = be32_to_cpu(req->param0);
 418     uint8_t cssid;
 419     uint16_t resp_code;
 420     uint32_t general_chars[510];
 421     uint32_t chsc_chars[508];
 422
 423     if (len != 0x0010) {
 424         resp_code = 0x0003;
 425         goto out_err;
 426     }
 427
 428     if (param0 & CHSC_SCSC_0_FMT) {
 429         resp_code = 0x0007;
 430         goto out_err;
 431     }
 432     cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
 433     if (cssid != 0) {
 434         if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
 435             resp_code = 0x0008;
 436             goto out_err;
 437         }
 438     }
 439     if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
 440         resp_code = 0x0003;
 441         goto out_err;
 442     }
 443     res->code = cpu_to_be16(0x0001);
 444     res->len = cpu_to_be16(4080);
 445     res->param = 0;
 446
 447     memset(general_chars, 0, sizeof(general_chars));
 448     memset(chsc_chars, 0, sizeof(chsc_chars));
 449
 450     general_chars[0] = cpu_to_be32(0x03000000);
 451     general_chars[1] = cpu_to_be32(0x00079000);
 452     general_chars[3] = cpu_to_be32(0x00080000);
 453
 454     chsc_chars[0] = cpu_to_be32(0x40000000);
 455     chsc_chars[3] = cpu_to_be32(0x00040000);
 456
 457     memcpy(res->data, general_chars, sizeof(general_chars));
 458     memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
 459     return;
 460
 461   out_err:
 462     res->code = cpu_to_be16(resp_code);
 463     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 464     res->param = 0;
 465 }
 466
 467 #define CHSC_SDA_0_FMT 0x0f000000
 468 #define CHSC_SDA_0_OC 0x0000ffff
 469 #define CHSC_SDA_0_RES 0xf0ff0000
 470 #define CHSC_SDA_OC_MCSSE 0x0
 471 #define CHSC_SDA_OC_MSS 0x2
 472 static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
 473 {
 474     uint16_t resp_code = 0x0001;
 475     uint16_t len = be16_to_cpu(req->len);
 476     uint32_t param0 = be32_to_cpu(req->param0);
 477     uint16_t oc;
 478     int ret;
 479
 480     if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
 481         resp_code = 0x0003;
 482         goto out;
 483     }
 484
 485     if (param0 & CHSC_SDA_0_FMT) {
 486         resp_code = 0x0007;
 487         goto out;
 488     }
 489
 490     oc = param0 & CHSC_SDA_0_OC;
 491     switch (oc) {
 492     case CHSC_SDA_OC_MCSSE:
 493         ret = css_enable_mcsse();
 494         if (ret == -EINVAL) {
 495             resp_code = 0x0101;
 496             goto out;
 497         }
 498         break;
 499     case CHSC_SDA_OC_MSS:
 500         ret = css_enable_mss();
 501         if (ret == -EINVAL) {
 502             resp_code = 0x0101;
 503             goto out;
 504         }
 505         break;
 506     default:
 507         resp_code = 0x0003;
 508         goto out;
 509     }
 510
 511 out:
 512     res->code = cpu_to_be16(resp_code);
 513     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 514     res->param = 0;
 515 }
 516
 517 static int chsc_sei_nt0_get_event(void *res)
 518 {
 519     /* no events yet */
 520     return 1;
 521 }
 522
 523 static int chsc_sei_nt0_have_event(void)
 524 {
 525     /* no events yet */
 526     return 0;
 527 }
 528
 529 static int chsc_sei_nt2_get_event(void *res)
 530 {
 531     if (s390_has_feat(S390_FEAT_ZPCI)) {
 532         return pci_chsc_sei_nt2_get_event(res);
 533     }
 534     return 1;
 535 }
 536
 537 static int chsc_sei_nt2_have_event(void)
 538 {
 539     if (s390_has_feat(S390_FEAT_ZPCI)) {
 540         return pci_chsc_sei_nt2_have_event();
 541     }
 542     return 0;
 543 }
 544
 545 #define CHSC_SEI_NT0    (1ULL << 63)
 546 #define CHSC_SEI_NT2    (1ULL << 61)
 547 static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
 548 {
 549     uint64_t selection_mask = ldq_p(&req->param1);
 550     uint8_t *res_flags = (uint8_t *)res->data;
 551     int have_event = 0;
 552     int have_more = 0;
 553
 554     /* regarding architecture nt0 can not be masked */
 555     have_event = !chsc_sei_nt0_get_event(res);
 556     have_more = chsc_sei_nt0_have_event();
 557
 558     if (selection_mask & CHSC_SEI_NT2) {
 559         if (!have_event) {
 560             have_event = !chsc_sei_nt2_get_event(res);
 561         }
 562
 563         if (!have_more) {
 564             have_more = chsc_sei_nt2_have_event();
 565         }
 566     }
 567
 568     if (have_event) {
 569         res->code = cpu_to_be16(0x0001);
 570         if (have_more) {
 571             (*res_flags) |= 0x80;
 572         } else {
 573             (*res_flags) &= ~0x80;
 574             css_clear_sei_pending();
 575         }
 576     } else {
 577         res->code = cpu_to_be16(0x0005);
 578         res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 579     }
 580 }
 581
 582 static void ioinst_handle_chsc_unimplemented(ChscResp *res)
 583 {
 584     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 585     res->code = cpu_to_be16(0x0004);
 586     res->param = 0;
 587 }
 588
 589 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb, uintptr_t ra)
 590 {
 591     ChscReq *req;
 592     ChscResp *res;
 593     uint64_t addr;
 594     int reg;
 595     uint16_t len;
 596     uint16_t command;
 597     CPUS390XState *env = &cpu->env;
 598     uint8_t buf[TARGET_PAGE_SIZE];
 599
 600     trace_ioinst("chsc");
 601     reg = (ipb >> 20) & 0x00f;
 602     addr = env->regs[reg];
 603     /* Page boundary? */
 604     if (addr & 0xfff) {
 605         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 606         return;
 607     }
 608     /*
 609      * Reading sizeof(ChscReq) bytes is currently enough for all of our
 610      * present CHSC sub-handlers ... if we ever need more, we should take
 611      * care of req->len here first.
 612      */
 613     if (s390_cpu_virt_mem_read(cpu, addr, reg, buf, sizeof(ChscReq))) {
 614         return;
 615     }
 616     req = (ChscReq *)buf;
 617     len = be16_to_cpu(req->len);
 618     /* Length field valid? */
 619     if ((len < 16) || (len > 4088) || (len & 7)) {
 620         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 621         return;
 622     }
 623     memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
 624     res = (void *)((char *)req + len);
 625     command = be16_to_cpu(req->command);
 626     trace_ioinst_chsc_cmd(command, len);
 627     switch (command) {
 628     case CHSC_SCSC:
 629         ioinst_handle_chsc_scsc(req, res);
 630         break;
 631     case CHSC_SCPD:
 632         ioinst_handle_chsc_scpd(req, res);
 633         break;
 634     case CHSC_SDA:
 635         ioinst_handle_chsc_sda(req, res);
 636         break;
 637     case CHSC_SEI:
 638         ioinst_handle_chsc_sei(req, res);
 639         break;
 640     default:
 641         ioinst_handle_chsc_unimplemented(res);
 642         break;
 643     }
 644
 645     if (!s390_cpu_virt_mem_write(cpu, addr + len, reg, res,
 646                                  be16_to_cpu(res->len))) {
 647         setcc(cpu, 0);    /* Command execution complete */
 648     }
 649 }
 650
 651 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
 652 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
 653 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
 654 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
 655
 656 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
 657                         uint32_t ipb, uintptr_t ra)
 658 {
 659     uint8_t mbk;
 660     int update;
 661     int dct;
 662     CPUS390XState *env = &cpu->env;
 663
 664     trace_ioinst("schm");
 665
 666     if (SCHM_REG1_RES(reg1)) {
 667         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 668         return;
 669     }
 670
 671     mbk = SCHM_REG1_MBK(reg1);
 672     update = SCHM_REG1_UPD(reg1);
 673     dct = SCHM_REG1_DCT(reg1);
 674
 675     if (update && (reg2 & 0x000000000000001f)) {
 676         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 677         return;
 678     }
 679
 680     css_do_schm(mbk, update, dct, update ? reg2 : 0);
 681 }
 682
 683 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra)
 684 {
 685     int cssid, ssid, schid, m;
 686     SubchDev *sch;
 687
 688     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 689         s390_program_interrupt(&cpu->env, PGM_OPERAND, 4, ra);
 690         return;
 691     }
 692     trace_ioinst_sch_id("rsch", cssid, ssid, schid);
 693     sch = css_find_subch(m, cssid, ssid, schid);
 694     if (!sch || !css_subch_visible(sch)) {
 695         setcc(cpu, 3);
 696         return;
 697     }
 698     setcc(cpu, css_do_rsch(sch));
 699 }
 700
 701 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
 702 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
 703 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
 704 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1, uintptr_t ra)
 705 {
 706     int cc;
 707     uint8_t cssid;
 708     uint8_t chpid;
 709     int ret;
 710     CPUS390XState *env = &cpu->env;
 711
 712     if (RCHP_REG1_RES(reg1)) {
 713         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 714         return;
 715     }
 716
 717     cssid = RCHP_REG1_CSSID(reg1);
 718     chpid = RCHP_REG1_CHPID(reg1);
 719
 720     trace_ioinst_chp_id("rchp", cssid, chpid);
 721
 722     ret = css_do_rchp(cssid, chpid);
 723
 724     switch (ret) {
 725     case -ENODEV:
 726         cc = 3;
 727         break;
 728     case -EBUSY:
 729         cc = 2;
 730         break;
 731     case 0:
 732         cc = 0;
 733         break;
 734     default:
 735         /* Invalid channel subsystem. */
 736         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 737         return;
 738     }
 739     setcc(cpu, cc);
 740 }
 741
 742 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
 743 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1, uintptr_t ra)
 744 {
 745     /* We do not provide address limit checking, so let's suppress it. */
 746     if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
 747         s390_program_interrupt(&cpu->env, PGM_OPERAND, 4, ra);
 748     }
 749 }