2 * Intel XScale PXA255/270 OS Timers.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
12 #include "hw/qdev-properties.h"
13 #include "qemu/timer.h"
14 #include "sysemu/runstate.h"
15 #include "hw/arm/pxa.h"
16 #include "hw/sysbus.h"
17 #include "migration/vmstate.h"
19 #include "qemu/module.h"
20 #include "qom/object.h"
34 #define OSCR 0x10 /* OS Timer Count */
43 #define OSSR 0x14 /* Timer status register */
45 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
46 #define OMCR4 0xc0 /* OS Match Control registers */
56 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
57 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
59 static int pxa2xx_timer4_freq
[8] = {
65 /* [5] is the "Externally supplied clock". Assign if necessary. */
69 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
70 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxTimerInfo
, PXA2XX_TIMER
)
78 PXA2xxTimerInfo
*info
;
90 struct PXA2xxTimerInfo
{
91 SysBusDevice parent_obj
;
100 PXA2xxTimer0 timer
[4];
102 uint32_t irq_enabled
;
110 #define PXA2XX_TIMER_HAVE_TM4 0
112 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo
*s
)
114 return s
->flags
& (1 << PXA2XX_TIMER_HAVE_TM4
);
117 static void pxa2xx_timer_update(void *opaque
, uint64_t now_qemu
)
119 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
125 muldiv64(now_qemu
- s
->lastload
, s
->freq
, NANOSECONDS_PER_SECOND
);
127 for (i
= 0; i
< 4; i
++) {
128 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->timer
[i
].value
- now_vm
),
129 NANOSECONDS_PER_SECOND
, s
->freq
);
130 timer_mod(s
->timer
[i
].qtimer
, new_qemu
);
134 static void pxa2xx_timer_update4(void *opaque
, uint64_t now_qemu
, int n
)
136 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
139 static const int counters
[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
142 assert(n
< ARRAY_SIZE(counters
));
143 if (s
->tm4
[n
].control
& (1 << 7))
146 counter
= counters
[n
];
148 if (!s
->tm4
[counter
].freq
) {
149 timer_del(s
->tm4
[n
].tm
.qtimer
);
153 now_vm
= s
->tm4
[counter
].clock
+ muldiv64(now_qemu
-
154 s
->tm4
[counter
].lastload
,
155 s
->tm4
[counter
].freq
, NANOSECONDS_PER_SECOND
);
157 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->tm4
[n
].tm
.value
- now_vm
),
158 NANOSECONDS_PER_SECOND
, s
->tm4
[counter
].freq
);
159 timer_mod(s
->tm4
[n
].tm
.qtimer
, new_qemu
);
162 static uint64_t pxa2xx_timer_read(void *opaque
, hwaddr offset
,
165 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
176 return s
->timer
[tm
].value
;
192 if (!pxa2xx_timer_has_tm4(s
))
194 return s
->tm4
[tm
].tm
.value
;
196 return s
->clock
+ muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
197 s
->lastload
, s
->freq
, NANOSECONDS_PER_SECOND
);
213 if (!pxa2xx_timer_has_tm4(s
))
216 if ((tm
== 9 - 4 || tm
== 11 - 4) && (s
->tm4
[tm
].control
& (1 << 9))) {
217 if (s
->tm4
[tm
- 1].freq
)
218 s
->snapshot
= s
->tm4
[tm
- 1].clock
+ muldiv64(
219 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
220 s
->tm4
[tm
- 1].lastload
,
221 s
->tm4
[tm
- 1].freq
, NANOSECONDS_PER_SECOND
);
223 s
->snapshot
= s
->tm4
[tm
- 1].clock
;
226 if (!s
->tm4
[tm
].freq
)
227 return s
->tm4
[tm
].clock
;
228 return s
->tm4
[tm
].clock
+
229 muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
230 s
->tm4
[tm
].lastload
, s
->tm4
[tm
].freq
,
231 NANOSECONDS_PER_SECOND
);
233 return s
->irq_enabled
;
234 case OSSR
: /* Status register */
253 if (!pxa2xx_timer_has_tm4(s
))
255 return s
->tm4
[tm
].control
;
259 qemu_log_mask(LOG_UNIMP
,
260 "%s: unknown register 0x%02" HWADDR_PRIx
"\n",
264 qemu_log_mask(LOG_GUEST_ERROR
,
265 "%s: incorrect register 0x%02" HWADDR_PRIx
"\n",
272 static void pxa2xx_timer_write(void *opaque
, hwaddr offset
,
273 uint64_t value
, unsigned size
)
276 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
286 s
->timer
[tm
].value
= value
;
287 pxa2xx_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
304 if (!pxa2xx_timer_has_tm4(s
))
306 s
->tm4
[tm
].tm
.value
= value
;
307 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
310 s
->oldclock
= s
->clock
;
311 s
->lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
313 pxa2xx_timer_update(s
, s
->lastload
);
330 if (!pxa2xx_timer_has_tm4(s
))
332 s
->tm4
[tm
].oldclock
= s
->tm4
[tm
].clock
;
333 s
->tm4
[tm
].lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
334 s
->tm4
[tm
].clock
= value
;
335 pxa2xx_timer_update4(s
, s
->tm4
[tm
].lastload
, tm
);
338 s
->irq_enabled
= value
& 0xfff;
340 case OSSR
: /* Status register */
343 for (i
= 0; i
< 4; i
++, value
>>= 1)
345 qemu_irq_lower(s
->timer
[i
].irq
);
346 if (pxa2xx_timer_has_tm4(s
) && !(s
->events
& 0xff0) && value
)
347 qemu_irq_lower(s
->irq4
);
349 case OWER
: /* XXX: Reset on OSMR3 match? */
359 if (!pxa2xx_timer_has_tm4(s
))
361 s
->tm4
[tm
].control
= value
& 0x0ff;
362 /* XXX Stop if running (shouldn't happen) */
363 if ((value
& (1 << 7)) || tm
== 0)
364 s
->tm4
[tm
].freq
= pxa2xx_timer4_freq
[value
& 7];
367 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
377 if (!pxa2xx_timer_has_tm4(s
))
379 s
->tm4
[tm
].control
= value
& 0x3ff;
380 /* XXX Stop if running (shouldn't happen) */
381 if ((value
& (1 << 7)) || !(tm
& 1))
383 pxa2xx_timer4_freq
[(value
& (1 << 8)) ? 0 : (value
& 7)];
386 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
390 qemu_log_mask(LOG_UNIMP
,
391 "%s: unknown register 0x%02" HWADDR_PRIx
" "
392 "(value 0x%08" PRIx64
")\n", __func__
, offset
, value
);
395 qemu_log_mask(LOG_GUEST_ERROR
,
396 "%s: incorrect register 0x%02" HWADDR_PRIx
" "
397 "(value 0x%08" PRIx64
")\n", __func__
, offset
, value
);
401 static const MemoryRegionOps pxa2xx_timer_ops
= {
402 .read
= pxa2xx_timer_read
,
403 .write
= pxa2xx_timer_write
,
404 .endianness
= DEVICE_NATIVE_ENDIAN
,
407 static void pxa2xx_timer_tick(void *opaque
)
409 PXA2xxTimer0
*t
= (PXA2xxTimer0
*) opaque
;
410 PXA2xxTimerInfo
*i
= t
->info
;
412 if (i
->irq_enabled
& (1 << t
->num
)) {
413 i
->events
|= 1 << t
->num
;
414 qemu_irq_raise(t
->irq
);
420 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
424 static void pxa2xx_timer_tick4(void *opaque
)
426 PXA2xxTimer4
*t
= (PXA2xxTimer4
*) opaque
;
427 PXA2xxTimerInfo
*i
= (PXA2xxTimerInfo
*) t
->tm
.info
;
429 pxa2xx_timer_tick(&t
->tm
);
430 if (t
->control
& (1 << 3))
432 if (t
->control
& (1 << 6))
433 pxa2xx_timer_update4(i
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), t
->tm
.num
- 4);
434 if (i
->events
& 0xff0)
435 qemu_irq_raise(i
->irq4
);
438 static int pxa25x_timer_post_load(void *opaque
, int version_id
)
440 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
444 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
445 pxa2xx_timer_update(s
, now
);
447 if (pxa2xx_timer_has_tm4(s
))
448 for (i
= 0; i
< 8; i
++)
449 pxa2xx_timer_update4(s
, now
, i
);
454 static void pxa2xx_timer_init(Object
*obj
)
456 PXA2xxTimerInfo
*s
= PXA2XX_TIMER(obj
);
457 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
462 s
->lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
465 memory_region_init_io(&s
->iomem
, obj
, &pxa2xx_timer_ops
, s
,
466 "pxa2xx-timer", 0x00001000);
467 sysbus_init_mmio(dev
, &s
->iomem
);
470 static void pxa2xx_timer_realize(DeviceState
*dev
, Error
**errp
)
472 PXA2xxTimerInfo
*s
= PXA2XX_TIMER(dev
);
473 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
476 for (i
= 0; i
< 4; i
++) {
477 s
->timer
[i
].value
= 0;
478 sysbus_init_irq(sbd
, &s
->timer
[i
].irq
);
479 s
->timer
[i
].info
= s
;
481 s
->timer
[i
].qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
482 pxa2xx_timer_tick
, &s
->timer
[i
]);
485 if (s
->flags
& (1 << PXA2XX_TIMER_HAVE_TM4
)) {
486 sysbus_init_irq(sbd
, &s
->irq4
);
488 for (i
= 0; i
< 8; i
++) {
489 s
->tm4
[i
].tm
.value
= 0;
490 s
->tm4
[i
].tm
.info
= s
;
491 s
->tm4
[i
].tm
.num
= i
+ 4;
493 s
->tm4
[i
].control
= 0x0;
494 s
->tm4
[i
].tm
.qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
495 pxa2xx_timer_tick4
, &s
->tm4
[i
]);
500 static const VMStateDescription vmstate_pxa2xx_timer0_regs
= {
501 .name
= "pxa2xx_timer0",
503 .minimum_version_id
= 2,
504 .fields
= (const VMStateField
[]) {
505 VMSTATE_UINT32(value
, PXA2xxTimer0
),
506 VMSTATE_END_OF_LIST(),
510 static const VMStateDescription vmstate_pxa2xx_timer4_regs
= {
511 .name
= "pxa2xx_timer4",
513 .minimum_version_id
= 1,
514 .fields
= (const VMStateField
[]) {
515 VMSTATE_STRUCT(tm
, PXA2xxTimer4
, 1,
516 vmstate_pxa2xx_timer0_regs
, PXA2xxTimer0
),
517 VMSTATE_INT32(oldclock
, PXA2xxTimer4
),
518 VMSTATE_INT32(clock
, PXA2xxTimer4
),
519 VMSTATE_UINT64(lastload
, PXA2xxTimer4
),
520 VMSTATE_UINT32(freq
, PXA2xxTimer4
),
521 VMSTATE_UINT32(control
, PXA2xxTimer4
),
522 VMSTATE_END_OF_LIST(),
526 static bool pxa2xx_timer_has_tm4_test(void *opaque
, int version_id
)
528 return pxa2xx_timer_has_tm4(opaque
);
531 static const VMStateDescription vmstate_pxa2xx_timer_regs
= {
532 .name
= "pxa2xx_timer",
534 .minimum_version_id
= 1,
535 .post_load
= pxa25x_timer_post_load
,
536 .fields
= (const VMStateField
[]) {
537 VMSTATE_INT32(clock
, PXA2xxTimerInfo
),
538 VMSTATE_INT32(oldclock
, PXA2xxTimerInfo
),
539 VMSTATE_UINT64(lastload
, PXA2xxTimerInfo
),
540 VMSTATE_STRUCT_ARRAY(timer
, PXA2xxTimerInfo
, 4, 1,
541 vmstate_pxa2xx_timer0_regs
, PXA2xxTimer0
),
542 VMSTATE_UINT32(events
, PXA2xxTimerInfo
),
543 VMSTATE_UINT32(irq_enabled
, PXA2xxTimerInfo
),
544 VMSTATE_UINT32(reset3
, PXA2xxTimerInfo
),
545 VMSTATE_UINT32(snapshot
, PXA2xxTimerInfo
),
546 VMSTATE_STRUCT_ARRAY_TEST(tm4
, PXA2xxTimerInfo
, 8,
547 pxa2xx_timer_has_tm4_test
, 0,
548 vmstate_pxa2xx_timer4_regs
, PXA2xxTimer4
),
549 VMSTATE_END_OF_LIST(),
553 static Property pxa25x_timer_dev_properties
[] = {
554 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo
, freq
, PXA25X_FREQ
),
555 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo
, flags
,
556 PXA2XX_TIMER_HAVE_TM4
, false),
557 DEFINE_PROP_END_OF_LIST(),
560 static void pxa25x_timer_dev_class_init(ObjectClass
*klass
, void *data
)
562 DeviceClass
*dc
= DEVICE_CLASS(klass
);
564 dc
->desc
= "PXA25x timer";
565 device_class_set_props(dc
, pxa25x_timer_dev_properties
);
568 static const TypeInfo pxa25x_timer_dev_info
= {
569 .name
= "pxa25x-timer",
570 .parent
= TYPE_PXA2XX_TIMER
,
571 .instance_size
= sizeof(PXA2xxTimerInfo
),
572 .class_init
= pxa25x_timer_dev_class_init
,
575 static Property pxa27x_timer_dev_properties
[] = {
576 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo
, freq
, PXA27X_FREQ
),
577 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo
, flags
,
578 PXA2XX_TIMER_HAVE_TM4
, true),
579 DEFINE_PROP_END_OF_LIST(),
582 static void pxa27x_timer_dev_class_init(ObjectClass
*klass
, void *data
)
584 DeviceClass
*dc
= DEVICE_CLASS(klass
);
586 dc
->desc
= "PXA27x timer";
587 device_class_set_props(dc
, pxa27x_timer_dev_properties
);
590 static const TypeInfo pxa27x_timer_dev_info
= {
591 .name
= "pxa27x-timer",
592 .parent
= TYPE_PXA2XX_TIMER
,
593 .instance_size
= sizeof(PXA2xxTimerInfo
),
594 .class_init
= pxa27x_timer_dev_class_init
,
597 static void pxa2xx_timer_class_init(ObjectClass
*oc
, void *data
)
599 DeviceClass
*dc
= DEVICE_CLASS(oc
);
601 dc
->realize
= pxa2xx_timer_realize
;
602 dc
->vmsd
= &vmstate_pxa2xx_timer_regs
;
605 static const TypeInfo pxa2xx_timer_type_info
= {
606 .name
= TYPE_PXA2XX_TIMER
,
607 .parent
= TYPE_SYS_BUS_DEVICE
,
608 .instance_size
= sizeof(PXA2xxTimerInfo
),
609 .instance_init
= pxa2xx_timer_init
,
611 .class_init
= pxa2xx_timer_class_init
,
614 static void pxa2xx_timer_register_types(void)
616 type_register_static(&pxa2xx_timer_type_info
);
617 type_register_static(&pxa25x_timer_dev_info
);
618 type_register_static(&pxa27x_timer_dev_info
);
621 type_init(pxa2xx_timer_register_types
)