hw/pci-host/prep.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/hw.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_bus.h"
  29 #include "hw/pci/pci_host.h"
  30 #include "hw/i386/pc.h"
  31 #include "hw/loader.h"
  32 #include "exec/address-spaces.h"
  33 #include "elf.h"
  34
  35 #define TYPE_RAVEN_PCI_DEVICE "raven"
  36 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  37
  38 #define RAVEN_PCI_DEVICE(obj) \
  39     OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
  40
  41 typedef struct RavenPCIState {
  42     PCIDevice dev;
  43
  44     uint32_t elf_machine;
  45     char *bios_name;
  46     MemoryRegion bios;
  47 } RavenPCIState;
  48
  49 #define RAVEN_PCI_HOST_BRIDGE(obj) \
  50     OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
  51
  52 typedef struct PRePPCIState {
  53     PCIHostState parent_obj;
  54
  55     qemu_irq irq[PCI_NUM_PINS];
  56     PCIBus pci_bus;
  57     AddressSpace pci_io_as;
  58     MemoryRegion pci_io;
  59     MemoryRegion pci_io_non_contiguous;
  60     MemoryRegion pci_intack;
  61     RavenPCIState pci_dev;
  62
  63     int contiguous_map;
  64 } PREPPCIState;
  65
  66 #define BIOS_SIZE (1024 * 1024)
  67
  68 static inline uint32_t PPC_PCIIO_config(hwaddr addr)
  69 {
  70     int i;
  71
  72     for (i = 0; i < 11; i++) {
  73         if ((addr & (1 << (11 + i))) != 0) {
  74             break;
  75         }
  76     }
  77     return (addr & 0x7ff) |  (i << 11);
  78 }
  79
  80 static void ppc_pci_io_write(void *opaque, hwaddr addr,
  81                              uint64_t val, unsigned int size)
  82 {
  83     PREPPCIState *s = opaque;
  84     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  85     pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
  86 }
  87
  88 static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
  89                                 unsigned int size)
  90 {
  91     PREPPCIState *s = opaque;
  92     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  93     return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
  94 }
  95
  96 static const MemoryRegionOps PPC_PCIIO_ops = {
  97     .read = ppc_pci_io_read,
  98     .write = ppc_pci_io_write,
  99     .endianness = DEVICE_LITTLE_ENDIAN,
 100 };
 101
 102 static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
 103                                 unsigned int size)
 104 {
 105     return pic_read_irq(isa_pic);
 106 }
 107
 108 static const MemoryRegionOps PPC_intack_ops = {
 109     .read = ppc_intack_read,
 110     .valid = {
 111         .max_access_size = 1,
 112     },
 113 };
 114
 115 static inline hwaddr raven_io_address(PREPPCIState *s,
 116                                       hwaddr addr)
 117 {
 118     if (s->contiguous_map == 0) {
 119         /* 64 KB contiguous space for IOs */
 120         addr &= 0xFFFF;
 121     } else {
 122         /* 8 MB non-contiguous space for IOs */
 123         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 124     }
 125
 126     /* FIXME: handle endianness switch */
 127
 128     return addr;
 129 }
 130
 131 static uint64_t raven_io_read(void *opaque, hwaddr addr,
 132                               unsigned int size)
 133 {
 134     PREPPCIState *s = opaque;
 135     uint8_t buf[4];
 136
 137     addr = raven_io_address(s, addr);
 138     address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size);
 139
 140     if (size == 1) {
 141         return buf[0];
 142     } else if (size == 2) {
 143         return lduw_p(buf);
 144     } else if (size == 4) {
 145         return ldl_p(buf);
 146     } else {
 147         g_assert_not_reached();
 148     }
 149 }
 150
 151 static void raven_io_write(void *opaque, hwaddr addr,
 152                            uint64_t val, unsigned int size)
 153 {
 154     PREPPCIState *s = opaque;
 155     uint8_t buf[4];
 156
 157     addr = raven_io_address(s, addr);
 158
 159     if (size == 1) {
 160         buf[0] = val;
 161     } else if (size == 2) {
 162         stw_p(buf, val);
 163     } else if (size == 4) {
 164         stl_p(buf, val);
 165     } else {
 166         g_assert_not_reached();
 167     }
 168
 169     address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size);
 170 }
 171
 172 static const MemoryRegionOps raven_io_ops = {
 173     .read = raven_io_read,
 174     .write = raven_io_write,
 175     .endianness = DEVICE_LITTLE_ENDIAN,
 176     .impl.max_access_size = 4,
 177     .valid.unaligned = true,
 178 };
 179
 180 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 181 {
 182     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 183 }
 184
 185 static void prep_set_irq(void *opaque, int irq_num, int level)
 186 {
 187     qemu_irq *pic = opaque;
 188
 189     qemu_set_irq(pic[irq_num] , level);
 190 }
 191
 192 static void raven_change_gpio(void *opaque, int n, int level)
 193 {
 194     PREPPCIState *s = opaque;
 195
 196     s->contiguous_map = level;
 197 }
 198
 199 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 200 {
 201     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 202     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 203     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 204     MemoryRegion *address_space_mem = get_system_memory();
 205     int i;
 206
 207     isa_mem_base = 0xc0000000;
 208
 209     for (i = 0; i < PCI_NUM_PINS; i++) {
 210         sysbus_init_irq(dev, &s->irq[i]);
 211     }
 212
 213     qdev_init_gpio_in(d, raven_change_gpio, 1);
 214
 215     pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);
 216
 217     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,
 218                           "pci-conf-idx", 1);
 219     memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
 220
 221     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s,
 222                           "pci-conf-data", 1);
 223     memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
 224
 225     memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000);
 226     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 227
 228     memory_region_init_io(&s->pci_intack, OBJECT(s), &PPC_intack_ops, s,
 229                           "pci-intack", 1);
 230     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
 231
 232     /* TODO Remove once realize propagates to child devices. */
 233     object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
 234 }
 235
 236 static void raven_pcihost_initfn(Object *obj)
 237 {
 238     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 239     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 240     MemoryRegion *address_space_mem = get_system_memory();
 241     DeviceState *pci_dev;
 242
 243     memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
 244     memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
 245                           "pci-io-non-contiguous", 0x00800000);
 246     address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
 247
 248     /* CPU address space */
 249     memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
 250     memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
 251                                         &s->pci_io_non_contiguous, 1);
 252     pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
 253                         address_space_mem, &s->pci_io, 0, TYPE_PCI_BUS);
 254
 255     h->bus = &s->pci_bus;
 256
 257     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
 258     pci_dev = DEVICE(&s->pci_dev);
 259     qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
 260     object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
 261                             NULL);
 262     qdev_prop_set_bit(pci_dev, "multifunction", false);
 263 }
 264
 265 static int raven_init(PCIDevice *d)
 266 {
 267     RavenPCIState *s = RAVEN_PCI_DEVICE(d);
 268     char *filename;
 269     int bios_size = -1;
 270
 271     d->config[0x0C] = 0x08; // cache_line_size
 272     d->config[0x0D] = 0x10; // latency_timer
 273     d->config[0x34] = 0x00; // capabilities_pointer
 274
 275     memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE);
 276     memory_region_set_readonly(&s->bios, true);
 277     memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
 278                                 &s->bios);
 279     vmstate_register_ram_global(&s->bios);
 280     if (s->bios_name) {
 281         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
 282         if (filename) {
 283             if (s->elf_machine != EM_NONE) {
 284                 bios_size = load_elf(filename, NULL, NULL, NULL,
 285                                      NULL, NULL, 1, s->elf_machine, 0);
 286             }
 287             if (bios_size < 0) {
 288                 bios_size = get_image_size(filename);
 289                 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 290                     hwaddr bios_addr;
 291                     bios_size = (bios_size + 0xfff) & ~0xfff;
 292                     bios_addr = (uint32_t)(-BIOS_SIZE);
 293                     bios_size = load_image_targphys(filename, bios_addr,
 294                                                     bios_size);
 295                 }
 296             }
 297         }
 298         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 299             hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
 300         }
 301         if (filename) {
 302             g_free(filename);
 303         }
 304     }
 305
 306     return 0;
 307 }
 308
 309 static const VMStateDescription vmstate_raven = {
 310     .name = "raven",
 311     .version_id = 0,
 312     .minimum_version_id = 0,
 313     .fields = (VMStateField[]) {
 314         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 315         VMSTATE_END_OF_LIST()
 316     },
 317 };
 318
 319 static void raven_class_init(ObjectClass *klass, void *data)
 320 {
 321     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 322     DeviceClass *dc = DEVICE_CLASS(klass);
 323
 324     k->init = raven_init;
 325     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 326     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 327     k->revision = 0x00;
 328     k->class_id = PCI_CLASS_BRIDGE_HOST;
 329     dc->desc = "PReP Host Bridge - Motorola Raven";
 330     dc->vmsd = &vmstate_raven;
 331     /*
 332      * PCI-facing part of the host bridge, not usable without the
 333      * host-facing part, which can't be device_add'ed, yet.
 334      */
 335     dc->cannot_instantiate_with_device_add_yet = true;
 336 }
 337
 338 static const TypeInfo raven_info = {
 339     .name = TYPE_RAVEN_PCI_DEVICE,
 340     .parent = TYPE_PCI_DEVICE,
 341     .instance_size = sizeof(RavenPCIState),
 342     .class_init = raven_class_init,
 343 };
 344
 345 static Property raven_pcihost_properties[] = {
 346     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
 347                        EM_NONE),
 348     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
 349     DEFINE_PROP_END_OF_LIST()
 350 };
 351
 352 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 353 {
 354     DeviceClass *dc = DEVICE_CLASS(klass);
 355
 356     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 357     dc->realize = raven_pcihost_realizefn;
 358     dc->props = raven_pcihost_properties;
 359     dc->fw_name = "pci";
 360 }
 361
 362 static const TypeInfo raven_pcihost_info = {
 363     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 364     .parent = TYPE_PCI_HOST_BRIDGE,
 365     .instance_size = sizeof(PREPPCIState),
 366     .instance_init = raven_pcihost_initfn,
 367     .class_init = raven_pcihost_class_init,
 368 };
 369
 370 static void raven_register_types(void)
 371 {
 372     type_register_static(&raven_pcihost_info);
 373     type_register_static(&raven_info);
 374 }
 375
 376 type_init(raven_register_types)