Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fp-20210516' into staging
[qemu/ar7.git] / target / arm / helper.c
blob3b365a78cbc341a73a2db691594e1767693c0445
1 /*
2 * ARM generic helpers.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
12 #include "trace.h"
13 #include "cpu.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
24 #include "hw/irq.h"
25 #include "semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/tcg.h"
30 #include "qemu/range.h"
31 #include "qapi/qapi-commands-machine-target.h"
32 #include "qapi/error.h"
33 #include "qemu/guest-random.h"
34 #ifdef CONFIG_TCG
35 #include "arm_ldst.h"
36 #include "exec/cpu_ldst.h"
37 #include "semihosting/common-semi.h"
38 #endif
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
41 #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
43 #ifndef CONFIG_USER_ONLY
45 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
46 MMUAccessType access_type, ARMMMUIdx mmu_idx,
47 bool s1_is_el0,
48 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
49 target_ulong *page_size_ptr,
50 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
51 __attribute__((nonnull));
52 #endif
54 static void switch_mode(CPUARMState *env, int mode);
55 static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
57 static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
59 ARMCPU *cpu = env_archcpu(env);
60 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
62 /* VFP data registers are always little-endian. */
63 if (reg < nregs) {
64 return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
66 if (arm_feature(env, ARM_FEATURE_NEON)) {
67 /* Aliases for Q regs. */
68 nregs += 16;
69 if (reg < nregs) {
70 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
71 return gdb_get_reg128(buf, q[0], q[1]);
74 switch (reg - nregs) {
75 case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
76 case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
77 case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
79 return 0;
82 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
84 ARMCPU *cpu = env_archcpu(env);
85 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
87 if (reg < nregs) {
88 *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
89 return 8;
91 if (arm_feature(env, ARM_FEATURE_NEON)) {
92 nregs += 16;
93 if (reg < nregs) {
94 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
95 q[0] = ldq_le_p(buf);
96 q[1] = ldq_le_p(buf + 8);
97 return 16;
100 switch (reg - nregs) {
101 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
102 case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
103 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
105 return 0;
108 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
110 switch (reg) {
111 case 0 ... 31:
113 /* 128 bit FP register - quads are in LE order */
114 uint64_t *q = aa64_vfp_qreg(env, reg);
115 return gdb_get_reg128(buf, q[1], q[0]);
117 case 32:
118 /* FPSR */
119 return gdb_get_reg32(buf, vfp_get_fpsr(env));
120 case 33:
121 /* FPCR */
122 return gdb_get_reg32(buf,vfp_get_fpcr(env));
123 default:
124 return 0;
128 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
130 switch (reg) {
131 case 0 ... 31:
132 /* 128 bit FP register */
134 uint64_t *q = aa64_vfp_qreg(env, reg);
135 q[0] = ldq_le_p(buf);
136 q[1] = ldq_le_p(buf + 8);
137 return 16;
139 case 32:
140 /* FPSR */
141 vfp_set_fpsr(env, ldl_p(buf));
142 return 4;
143 case 33:
144 /* FPCR */
145 vfp_set_fpcr(env, ldl_p(buf));
146 return 4;
147 default:
148 return 0;
152 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
154 assert(ri->fieldoffset);
155 if (cpreg_field_is_64bit(ri)) {
156 return CPREG_FIELD64(env, ri);
157 } else {
158 return CPREG_FIELD32(env, ri);
162 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
163 uint64_t value)
165 assert(ri->fieldoffset);
166 if (cpreg_field_is_64bit(ri)) {
167 CPREG_FIELD64(env, ri) = value;
168 } else {
169 CPREG_FIELD32(env, ri) = value;
173 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
175 return (char *)env + ri->fieldoffset;
178 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
180 /* Raw read of a coprocessor register (as needed for migration, etc). */
181 if (ri->type & ARM_CP_CONST) {
182 return ri->resetvalue;
183 } else if (ri->raw_readfn) {
184 return ri->raw_readfn(env, ri);
185 } else if (ri->readfn) {
186 return ri->readfn(env, ri);
187 } else {
188 return raw_read(env, ri);
192 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
193 uint64_t v)
195 /* Raw write of a coprocessor register (as needed for migration, etc).
196 * Note that constant registers are treated as write-ignored; the
197 * caller should check for success by whether a readback gives the
198 * value written.
200 if (ri->type & ARM_CP_CONST) {
201 return;
202 } else if (ri->raw_writefn) {
203 ri->raw_writefn(env, ri, v);
204 } else if (ri->writefn) {
205 ri->writefn(env, ri, v);
206 } else {
207 raw_write(env, ri, v);
212 * arm_get/set_gdb_*: get/set a gdb register
213 * @env: the CPU state
214 * @buf: a buffer to copy to/from
215 * @reg: register number (offset from start of group)
217 * We return the number of bytes copied
220 static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
222 ARMCPU *cpu = env_archcpu(env);
223 const ARMCPRegInfo *ri;
224 uint32_t key;
226 key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
227 ri = get_arm_cp_reginfo(cpu->cp_regs, key);
228 if (ri) {
229 if (cpreg_field_is_64bit(ri)) {
230 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
231 } else {
232 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
235 return 0;
238 static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
240 return 0;
243 #ifdef TARGET_AARCH64
244 static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
246 ARMCPU *cpu = env_archcpu(env);
248 switch (reg) {
249 /* The first 32 registers are the zregs */
250 case 0 ... 31:
252 int vq, len = 0;
253 for (vq = 0; vq < cpu->sve_max_vq; vq++) {
254 len += gdb_get_reg128(buf,
255 env->vfp.zregs[reg].d[vq * 2 + 1],
256 env->vfp.zregs[reg].d[vq * 2]);
258 return len;
260 case 32:
261 return gdb_get_reg32(buf, vfp_get_fpsr(env));
262 case 33:
263 return gdb_get_reg32(buf, vfp_get_fpcr(env));
264 /* then 16 predicates and the ffr */
265 case 34 ... 50:
267 int preg = reg - 34;
268 int vq, len = 0;
269 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
270 len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
272 return len;
274 case 51:
277 * We report in Vector Granules (VG) which is 64bit in a Z reg
278 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
280 int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
281 return gdb_get_reg64(buf, vq * 2);
283 default:
284 /* gdbstub asked for something out our range */
285 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
286 break;
289 return 0;
292 static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
294 ARMCPU *cpu = env_archcpu(env);
296 /* The first 32 registers are the zregs */
297 switch (reg) {
298 /* The first 32 registers are the zregs */
299 case 0 ... 31:
301 int vq, len = 0;
302 uint64_t *p = (uint64_t *) buf;
303 for (vq = 0; vq < cpu->sve_max_vq; vq++) {
304 env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
305 env->vfp.zregs[reg].d[vq * 2] = *p++;
306 len += 16;
308 return len;
310 case 32:
311 vfp_set_fpsr(env, *(uint32_t *)buf);
312 return 4;
313 case 33:
314 vfp_set_fpcr(env, *(uint32_t *)buf);
315 return 4;
316 case 34 ... 50:
318 int preg = reg - 34;
319 int vq, len = 0;
320 uint64_t *p = (uint64_t *) buf;
321 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
322 env->vfp.pregs[preg].p[vq / 4] = *p++;
323 len += 8;
325 return len;
327 case 51:
328 /* cannot set vg via gdbstub */
329 return 0;
330 default:
331 /* gdbstub asked for something out our range */
332 break;
335 return 0;
337 #endif /* TARGET_AARCH64 */
339 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
341 /* Return true if the regdef would cause an assertion if you called
342 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
343 * program bug for it not to have the NO_RAW flag).
344 * NB that returning false here doesn't necessarily mean that calling
345 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
346 * read/write access functions which are safe for raw use" from "has
347 * read/write access functions which have side effects but has forgotten
348 * to provide raw access functions".
349 * The tests here line up with the conditions in read/write_raw_cp_reg()
350 * and assertions in raw_read()/raw_write().
352 if ((ri->type & ARM_CP_CONST) ||
353 ri->fieldoffset ||
354 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
355 return false;
357 return true;
360 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
362 /* Write the coprocessor state from cpu->env to the (index,value) list. */
363 int i;
364 bool ok = true;
366 for (i = 0; i < cpu->cpreg_array_len; i++) {
367 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
368 const ARMCPRegInfo *ri;
369 uint64_t newval;
371 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
372 if (!ri) {
373 ok = false;
374 continue;
376 if (ri->type & ARM_CP_NO_RAW) {
377 continue;
380 newval = read_raw_cp_reg(&cpu->env, ri);
381 if (kvm_sync) {
383 * Only sync if the previous list->cpustate sync succeeded.
384 * Rather than tracking the success/failure state for every
385 * item in the list, we just recheck "does the raw write we must
386 * have made in write_list_to_cpustate() read back OK" here.
388 uint64_t oldval = cpu->cpreg_values[i];
390 if (oldval == newval) {
391 continue;
394 write_raw_cp_reg(&cpu->env, ri, oldval);
395 if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
396 continue;
399 write_raw_cp_reg(&cpu->env, ri, newval);
401 cpu->cpreg_values[i] = newval;
403 return ok;
406 bool write_list_to_cpustate(ARMCPU *cpu)
408 int i;
409 bool ok = true;
411 for (i = 0; i < cpu->cpreg_array_len; i++) {
412 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
413 uint64_t v = cpu->cpreg_values[i];
414 const ARMCPRegInfo *ri;
416 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
417 if (!ri) {
418 ok = false;
419 continue;
421 if (ri->type & ARM_CP_NO_RAW) {
422 continue;
424 /* Write value and confirm it reads back as written
425 * (to catch read-only registers and partially read-only
426 * registers where the incoming migration value doesn't match)
428 write_raw_cp_reg(&cpu->env, ri, v);
429 if (read_raw_cp_reg(&cpu->env, ri) != v) {
430 ok = false;
433 return ok;
436 static void add_cpreg_to_list(gpointer key, gpointer opaque)
438 ARMCPU *cpu = opaque;
439 uint64_t regidx;
440 const ARMCPRegInfo *ri;
442 regidx = *(uint32_t *)key;
443 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
445 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
446 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
447 /* The value array need not be initialized at this point */
448 cpu->cpreg_array_len++;
452 static void count_cpreg(gpointer key, gpointer opaque)
454 ARMCPU *cpu = opaque;
455 uint64_t regidx;
456 const ARMCPRegInfo *ri;
458 regidx = *(uint32_t *)key;
459 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
461 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
462 cpu->cpreg_array_len++;
466 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
468 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
469 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
471 if (aidx > bidx) {
472 return 1;
474 if (aidx < bidx) {
475 return -1;
477 return 0;
480 void init_cpreg_list(ARMCPU *cpu)
482 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
483 * Note that we require cpreg_tuples[] to be sorted by key ID.
485 GList *keys;
486 int arraylen;
488 keys = g_hash_table_get_keys(cpu->cp_regs);
489 keys = g_list_sort(keys, cpreg_key_compare);
491 cpu->cpreg_array_len = 0;
493 g_list_foreach(keys, count_cpreg, cpu);
495 arraylen = cpu->cpreg_array_len;
496 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
497 cpu->cpreg_values = g_new(uint64_t, arraylen);
498 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
499 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
500 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
501 cpu->cpreg_array_len = 0;
503 g_list_foreach(keys, add_cpreg_to_list, cpu);
505 assert(cpu->cpreg_array_len == arraylen);
507 g_list_free(keys);
511 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
513 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
514 const ARMCPRegInfo *ri,
515 bool isread)
517 if (!is_a64(env) && arm_current_el(env) == 3 &&
518 arm_is_secure_below_el3(env)) {
519 return CP_ACCESS_TRAP_UNCATEGORIZED;
521 return CP_ACCESS_OK;
524 /* Some secure-only AArch32 registers trap to EL3 if used from
525 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
526 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
527 * We assume that the .access field is set to PL1_RW.
529 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
530 const ARMCPRegInfo *ri,
531 bool isread)
533 if (arm_current_el(env) == 3) {
534 return CP_ACCESS_OK;
536 if (arm_is_secure_below_el3(env)) {
537 if (env->cp15.scr_el3 & SCR_EEL2) {
538 return CP_ACCESS_TRAP_EL2;
540 return CP_ACCESS_TRAP_EL3;
542 /* This will be EL1 NS and EL2 NS, which just UNDEF */
543 return CP_ACCESS_TRAP_UNCATEGORIZED;
546 static uint64_t arm_mdcr_el2_eff(CPUARMState *env)
548 return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;
551 /* Check for traps to "powerdown debug" registers, which are controlled
552 * by MDCR.TDOSA
554 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
555 bool isread)
557 int el = arm_current_el(env);
558 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
559 bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) ||
560 (arm_hcr_el2_eff(env) & HCR_TGE);
562 if (el < 2 && mdcr_el2_tdosa) {
563 return CP_ACCESS_TRAP_EL2;
565 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
566 return CP_ACCESS_TRAP_EL3;
568 return CP_ACCESS_OK;
571 /* Check for traps to "debug ROM" registers, which are controlled
572 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
574 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
575 bool isread)
577 int el = arm_current_el(env);
578 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
579 bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) ||
580 (arm_hcr_el2_eff(env) & HCR_TGE);
582 if (el < 2 && mdcr_el2_tdra) {
583 return CP_ACCESS_TRAP_EL2;
585 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
586 return CP_ACCESS_TRAP_EL3;
588 return CP_ACCESS_OK;
591 /* Check for traps to general debug registers, which are controlled
592 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
594 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
595 bool isread)
597 int el = arm_current_el(env);
598 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
599 bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
600 (arm_hcr_el2_eff(env) & HCR_TGE);
602 if (el < 2 && mdcr_el2_tda) {
603 return CP_ACCESS_TRAP_EL2;
605 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
606 return CP_ACCESS_TRAP_EL3;
608 return CP_ACCESS_OK;
611 /* Check for traps to performance monitor registers, which are controlled
612 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
614 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
615 bool isread)
617 int el = arm_current_el(env);
618 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
620 if (el < 2 && (mdcr_el2 & MDCR_TPM)) {
621 return CP_ACCESS_TRAP_EL2;
623 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
624 return CP_ACCESS_TRAP_EL3;
626 return CP_ACCESS_OK;
629 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
630 static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
631 bool isread)
633 if (arm_current_el(env) == 1) {
634 uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
635 if (arm_hcr_el2_eff(env) & trap) {
636 return CP_ACCESS_TRAP_EL2;
639 return CP_ACCESS_OK;
642 /* Check for traps from EL1 due to HCR_EL2.TSW. */
643 static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
644 bool isread)
646 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) {
647 return CP_ACCESS_TRAP_EL2;
649 return CP_ACCESS_OK;
652 /* Check for traps from EL1 due to HCR_EL2.TACR. */
653 static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
654 bool isread)
656 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) {
657 return CP_ACCESS_TRAP_EL2;
659 return CP_ACCESS_OK;
662 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
663 static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
664 bool isread)
666 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
667 return CP_ACCESS_TRAP_EL2;
669 return CP_ACCESS_OK;
672 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
674 ARMCPU *cpu = env_archcpu(env);
676 raw_write(env, ri, value);
677 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
680 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
682 ARMCPU *cpu = env_archcpu(env);
684 if (raw_read(env, ri) != value) {
685 /* Unlike real hardware the qemu TLB uses virtual addresses,
686 * not modified virtual addresses, so this causes a TLB flush.
688 tlb_flush(CPU(cpu));
689 raw_write(env, ri, value);
693 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
696 ARMCPU *cpu = env_archcpu(env);
698 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
699 && !extended_addresses_enabled(env)) {
700 /* For VMSA (when not using the LPAE long descriptor page table
701 * format) this register includes the ASID, so do a TLB flush.
702 * For PMSA it is purely a process ID and no action is needed.
704 tlb_flush(CPU(cpu));
706 raw_write(env, ri, value);
709 /* IS variants of TLB operations must affect all cores */
710 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
711 uint64_t value)
713 CPUState *cs = env_cpu(env);
715 tlb_flush_all_cpus_synced(cs);
718 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
719 uint64_t value)
721 CPUState *cs = env_cpu(env);
723 tlb_flush_all_cpus_synced(cs);
726 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
727 uint64_t value)
729 CPUState *cs = env_cpu(env);
731 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
734 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
735 uint64_t value)
737 CPUState *cs = env_cpu(env);
739 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
743 * Non-IS variants of TLB operations are upgraded to
744 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
745 * force broadcast of these operations.
747 static bool tlb_force_broadcast(CPUARMState *env)
749 return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
752 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
753 uint64_t value)
755 /* Invalidate all (TLBIALL) */
756 CPUState *cs = env_cpu(env);
758 if (tlb_force_broadcast(env)) {
759 tlb_flush_all_cpus_synced(cs);
760 } else {
761 tlb_flush(cs);
765 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
766 uint64_t value)
768 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
769 CPUState *cs = env_cpu(env);
771 value &= TARGET_PAGE_MASK;
772 if (tlb_force_broadcast(env)) {
773 tlb_flush_page_all_cpus_synced(cs, value);
774 } else {
775 tlb_flush_page(cs, value);
779 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
780 uint64_t value)
782 /* Invalidate by ASID (TLBIASID) */
783 CPUState *cs = env_cpu(env);
785 if (tlb_force_broadcast(env)) {
786 tlb_flush_all_cpus_synced(cs);
787 } else {
788 tlb_flush(cs);
792 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
793 uint64_t value)
795 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
796 CPUState *cs = env_cpu(env);
798 value &= TARGET_PAGE_MASK;
799 if (tlb_force_broadcast(env)) {
800 tlb_flush_page_all_cpus_synced(cs, value);
801 } else {
802 tlb_flush_page(cs, value);
806 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
807 uint64_t value)
809 CPUState *cs = env_cpu(env);
811 tlb_flush_by_mmuidx(cs,
812 ARMMMUIdxBit_E10_1 |
813 ARMMMUIdxBit_E10_1_PAN |
814 ARMMMUIdxBit_E10_0);
817 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
818 uint64_t value)
820 CPUState *cs = env_cpu(env);
822 tlb_flush_by_mmuidx_all_cpus_synced(cs,
823 ARMMMUIdxBit_E10_1 |
824 ARMMMUIdxBit_E10_1_PAN |
825 ARMMMUIdxBit_E10_0);
829 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
830 uint64_t value)
832 CPUState *cs = env_cpu(env);
834 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
837 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
838 uint64_t value)
840 CPUState *cs = env_cpu(env);
842 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
845 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
846 uint64_t value)
848 CPUState *cs = env_cpu(env);
849 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
851 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
854 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
855 uint64_t value)
857 CPUState *cs = env_cpu(env);
858 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
860 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
861 ARMMMUIdxBit_E2);
864 static const ARMCPRegInfo cp_reginfo[] = {
865 /* Define the secure and non-secure FCSE identifier CP registers
866 * separately because there is no secure bank in V8 (no _EL3). This allows
867 * the secure register to be properly reset and migrated. There is also no
868 * v8 EL1 version of the register so the non-secure instance stands alone.
870 { .name = "FCSEIDR",
871 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
872 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
873 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
874 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
875 { .name = "FCSEIDR_S",
876 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
877 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
878 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
879 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
880 /* Define the secure and non-secure context identifier CP registers
881 * separately because there is no secure bank in V8 (no _EL3). This allows
882 * the secure register to be properly reset and migrated. In the
883 * non-secure case, the 32-bit register will have reset and migration
884 * disabled during registration as it is handled by the 64-bit instance.
886 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
887 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
888 .access = PL1_RW, .accessfn = access_tvm_trvm,
889 .secure = ARM_CP_SECSTATE_NS,
890 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
891 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
892 { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
893 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
894 .access = PL1_RW, .accessfn = access_tvm_trvm,
895 .secure = ARM_CP_SECSTATE_S,
896 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
897 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
898 REGINFO_SENTINEL
901 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
902 /* NB: Some of these registers exist in v8 but with more precise
903 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
905 /* MMU Domain access control / MPU write buffer control */
906 { .name = "DACR",
907 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
908 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
909 .writefn = dacr_write, .raw_writefn = raw_write,
910 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
911 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
912 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
913 * For v6 and v5, these mappings are overly broad.
915 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
916 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
917 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
918 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
919 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
920 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
921 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
922 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
923 /* Cache maintenance ops; some of this space may be overridden later. */
924 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
925 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
926 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
927 REGINFO_SENTINEL
930 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
931 /* Not all pre-v6 cores implemented this WFI, so this is slightly
932 * over-broad.
934 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
935 .access = PL1_W, .type = ARM_CP_WFI },
936 REGINFO_SENTINEL
939 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
940 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
941 * is UNPREDICTABLE; we choose to NOP as most implementations do).
943 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
944 .access = PL1_W, .type = ARM_CP_WFI },
945 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
946 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
947 * OMAPCP will override this space.
949 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
950 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
951 .resetvalue = 0 },
952 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
953 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
954 .resetvalue = 0 },
955 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
956 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
957 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
958 .resetvalue = 0 },
959 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
960 * implementing it as RAZ means the "debug architecture version" bits
961 * will read as a reserved value, which should cause Linux to not try
962 * to use the debug hardware.
964 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
965 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
966 /* MMU TLB control. Note that the wildcarding means we cover not just
967 * the unified TLB ops but also the dside/iside/inner-shareable variants.
969 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
970 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
971 .type = ARM_CP_NO_RAW },
972 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
973 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
974 .type = ARM_CP_NO_RAW },
975 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
976 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
977 .type = ARM_CP_NO_RAW },
978 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
979 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
980 .type = ARM_CP_NO_RAW },
981 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
982 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
983 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
984 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
985 REGINFO_SENTINEL
988 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
989 uint64_t value)
991 uint32_t mask = 0;
993 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
994 if (!arm_feature(env, ARM_FEATURE_V8)) {
995 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
996 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
997 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
999 if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
1000 /* VFP coprocessor: cp10 & cp11 [23:20] */
1001 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
1003 if (!arm_feature(env, ARM_FEATURE_NEON)) {
1004 /* ASEDIS [31] bit is RAO/WI */
1005 value |= (1 << 31);
1008 /* VFPv3 and upwards with NEON implement 32 double precision
1009 * registers (D0-D31).
1011 if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
1012 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
1013 value |= (1 << 30);
1016 value &= mask;
1020 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1021 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1023 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
1024 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
1025 value &= ~(0xf << 20);
1026 value |= env->cp15.cpacr_el1 & (0xf << 20);
1029 env->cp15.cpacr_el1 = value;
1032 static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1035 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1036 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1038 uint64_t value = env->cp15.cpacr_el1;
1040 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
1041 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
1042 value &= ~(0xf << 20);
1044 return value;
1048 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1050 /* Call cpacr_write() so that we reset with the correct RAO bits set
1051 * for our CPU features.
1053 cpacr_write(env, ri, 0);
1056 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1057 bool isread)
1059 if (arm_feature(env, ARM_FEATURE_V8)) {
1060 /* Check if CPACR accesses are to be trapped to EL2 */
1061 if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) &&
1062 (env->cp15.cptr_el[2] & CPTR_TCPAC)) {
1063 return CP_ACCESS_TRAP_EL2;
1064 /* Check if CPACR accesses are to be trapped to EL3 */
1065 } else if (arm_current_el(env) < 3 &&
1066 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
1067 return CP_ACCESS_TRAP_EL3;
1071 return CP_ACCESS_OK;
1074 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1075 bool isread)
1077 /* Check if CPTR accesses are set to trap to EL3 */
1078 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
1079 return CP_ACCESS_TRAP_EL3;
1082 return CP_ACCESS_OK;
1085 static const ARMCPRegInfo v6_cp_reginfo[] = {
1086 /* prefetch by MVA in v6, NOP in v7 */
1087 { .name = "MVA_prefetch",
1088 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
1089 .access = PL1_W, .type = ARM_CP_NOP },
1090 /* We need to break the TB after ISB to execute self-modifying code
1091 * correctly and also to take any pending interrupts immediately.
1092 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
1094 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
1095 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
1096 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
1097 .access = PL0_W, .type = ARM_CP_NOP },
1098 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
1099 .access = PL0_W, .type = ARM_CP_NOP },
1100 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
1101 .access = PL1_RW, .accessfn = access_tvm_trvm,
1102 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
1103 offsetof(CPUARMState, cp15.ifar_ns) },
1104 .resetvalue = 0, },
1105 /* Watchpoint Fault Address Register : should actually only be present
1106 * for 1136, 1176, 11MPCore.
1108 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1109 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
1110 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
1111 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
1112 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
1113 .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
1114 REGINFO_SENTINEL
1117 /* Definitions for the PMU registers */
1118 #define PMCRN_MASK 0xf800
1119 #define PMCRN_SHIFT 11
1120 #define PMCRLC 0x40
1121 #define PMCRDP 0x20
1122 #define PMCRX 0x10
1123 #define PMCRD 0x8
1124 #define PMCRC 0x4
1125 #define PMCRP 0x2
1126 #define PMCRE 0x1
1128 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1129 * which can be written as 1 to trigger behaviour but which stay RAZ).
1131 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1133 #define PMXEVTYPER_P 0x80000000
1134 #define PMXEVTYPER_U 0x40000000
1135 #define PMXEVTYPER_NSK 0x20000000
1136 #define PMXEVTYPER_NSU 0x10000000
1137 #define PMXEVTYPER_NSH 0x08000000
1138 #define PMXEVTYPER_M 0x04000000
1139 #define PMXEVTYPER_MT 0x02000000
1140 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1141 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1142 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1143 PMXEVTYPER_M | PMXEVTYPER_MT | \
1144 PMXEVTYPER_EVTCOUNT)
1146 #define PMCCFILTR 0xf8000000
1147 #define PMCCFILTR_M PMXEVTYPER_M
1148 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1150 static inline uint32_t pmu_num_counters(CPUARMState *env)
1152 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
1155 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1156 static inline uint64_t pmu_counter_mask(CPUARMState *env)
1158 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
1161 typedef struct pm_event {
1162 uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
1163 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1164 bool (*supported)(CPUARMState *);
1166 * Retrieve the current count of the underlying event. The programmed
1167 * counters hold a difference from the return value from this function
1169 uint64_t (*get_count)(CPUARMState *);
1171 * Return how many nanoseconds it will take (at a minimum) for count events
1172 * to occur. A negative value indicates the counter will never overflow, or
1173 * that the counter has otherwise arranged for the overflow bit to be set
1174 * and the PMU interrupt to be raised on overflow.
1176 int64_t (*ns_per_count)(uint64_t);
1177 } pm_event;
1179 static bool event_always_supported(CPUARMState *env)
1181 return true;
1184 static uint64_t swinc_get_count(CPUARMState *env)
1187 * SW_INCR events are written directly to the pmevcntr's by writes to
1188 * PMSWINC, so there is no underlying count maintained by the PMU itself
1190 return 0;
1193 static int64_t swinc_ns_per(uint64_t ignored)
1195 return -1;
1199 * Return the underlying cycle count for the PMU cycle counters. If we're in
1200 * usermode, simply return 0.
1202 static uint64_t cycles_get_count(CPUARMState *env)
1204 #ifndef CONFIG_USER_ONLY
1205 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1206 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1207 #else
1208 return cpu_get_host_ticks();
1209 #endif
1212 #ifndef CONFIG_USER_ONLY
1213 static int64_t cycles_ns_per(uint64_t cycles)
1215 return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles;
1218 static bool instructions_supported(CPUARMState *env)
1220 return icount_enabled() == 1; /* Precise instruction counting */
1223 static uint64_t instructions_get_count(CPUARMState *env)
1225 return (uint64_t)icount_get_raw();
1228 static int64_t instructions_ns_per(uint64_t icount)
1230 return icount_to_ns((int64_t)icount);
1232 #endif
1234 static bool pmu_8_1_events_supported(CPUARMState *env)
1236 /* For events which are supported in any v8.1 PMU */
1237 return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
1240 static bool pmu_8_4_events_supported(CPUARMState *env)
1242 /* For events which are supported in any v8.1 PMU */
1243 return cpu_isar_feature(any_pmu_8_4, env_archcpu(env));
1246 static uint64_t zero_event_get_count(CPUARMState *env)
1248 /* For events which on QEMU never fire, so their count is always zero */
1249 return 0;
1252 static int64_t zero_event_ns_per(uint64_t cycles)
1254 /* An event which never fires can never overflow */
1255 return -1;
1258 static const pm_event pm_events[] = {
1259 { .number = 0x000, /* SW_INCR */
1260 .supported = event_always_supported,
1261 .get_count = swinc_get_count,
1262 .ns_per_count = swinc_ns_per,
1264 #ifndef CONFIG_USER_ONLY
1265 { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
1266 .supported = instructions_supported,
1267 .get_count = instructions_get_count,
1268 .ns_per_count = instructions_ns_per,
1270 { .number = 0x011, /* CPU_CYCLES, Cycle */
1271 .supported = event_always_supported,
1272 .get_count = cycles_get_count,
1273 .ns_per_count = cycles_ns_per,
1275 #endif
1276 { .number = 0x023, /* STALL_FRONTEND */
1277 .supported = pmu_8_1_events_supported,
1278 .get_count = zero_event_get_count,
1279 .ns_per_count = zero_event_ns_per,
1281 { .number = 0x024, /* STALL_BACKEND */
1282 .supported = pmu_8_1_events_supported,
1283 .get_count = zero_event_get_count,
1284 .ns_per_count = zero_event_ns_per,
1286 { .number = 0x03c, /* STALL */
1287 .supported = pmu_8_4_events_supported,
1288 .get_count = zero_event_get_count,
1289 .ns_per_count = zero_event_ns_per,
1294 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1295 * events (i.e. the statistical profiling extension), this implementation
1296 * should first be updated to something sparse instead of the current
1297 * supported_event_map[] array.
1299 #define MAX_EVENT_ID 0x3c
1300 #define UNSUPPORTED_EVENT UINT16_MAX
1301 static uint16_t supported_event_map[MAX_EVENT_ID + 1];
1304 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1305 * of ARM event numbers to indices in our pm_events array.
1307 * Note: Events in the 0x40XX range are not currently supported.
1309 void pmu_init(ARMCPU *cpu)
1311 unsigned int i;
1314 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1315 * events to them
1317 for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) {
1318 supported_event_map[i] = UNSUPPORTED_EVENT;
1320 cpu->pmceid0 = 0;
1321 cpu->pmceid1 = 0;
1323 for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
1324 const pm_event *cnt = &pm_events[i];
1325 assert(cnt->number <= MAX_EVENT_ID);
1326 /* We do not currently support events in the 0x40xx range */
1327 assert(cnt->number <= 0x3f);
1329 if (cnt->supported(&cpu->env)) {
1330 supported_event_map[cnt->number] = i;
1331 uint64_t event_mask = 1ULL << (cnt->number & 0x1f);
1332 if (cnt->number & 0x20) {
1333 cpu->pmceid1 |= event_mask;
1334 } else {
1335 cpu->pmceid0 |= event_mask;
1342 * Check at runtime whether a PMU event is supported for the current machine
1344 static bool event_supported(uint16_t number)
1346 if (number > MAX_EVENT_ID) {
1347 return false;
1349 return supported_event_map[number] != UNSUPPORTED_EVENT;
1352 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
1353 bool isread)
1355 /* Performance monitor registers user accessibility is controlled
1356 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1357 * trapping to EL2 or EL3 for other accesses.
1359 int el = arm_current_el(env);
1360 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
1362 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
1363 return CP_ACCESS_TRAP;
1365 if (el < 2 && (mdcr_el2 & MDCR_TPM)) {
1366 return CP_ACCESS_TRAP_EL2;
1368 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
1369 return CP_ACCESS_TRAP_EL3;
1372 return CP_ACCESS_OK;
1375 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
1376 const ARMCPRegInfo *ri,
1377 bool isread)
1379 /* ER: event counter read trap control */
1380 if (arm_feature(env, ARM_FEATURE_V8)
1381 && arm_current_el(env) == 0
1382 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
1383 && isread) {
1384 return CP_ACCESS_OK;
1387 return pmreg_access(env, ri, isread);
1390 static CPAccessResult pmreg_access_swinc(CPUARMState *env,
1391 const ARMCPRegInfo *ri,
1392 bool isread)
1394 /* SW: software increment write trap control */
1395 if (arm_feature(env, ARM_FEATURE_V8)
1396 && arm_current_el(env) == 0
1397 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
1398 && !isread) {
1399 return CP_ACCESS_OK;
1402 return pmreg_access(env, ri, isread);
1405 static CPAccessResult pmreg_access_selr(CPUARMState *env,
1406 const ARMCPRegInfo *ri,
1407 bool isread)
1409 /* ER: event counter read trap control */
1410 if (arm_feature(env, ARM_FEATURE_V8)
1411 && arm_current_el(env) == 0
1412 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
1413 return CP_ACCESS_OK;
1416 return pmreg_access(env, ri, isread);
1419 static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
1420 const ARMCPRegInfo *ri,
1421 bool isread)
1423 /* CR: cycle counter read trap control */
1424 if (arm_feature(env, ARM_FEATURE_V8)
1425 && arm_current_el(env) == 0
1426 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
1427 && isread) {
1428 return CP_ACCESS_OK;
1431 return pmreg_access(env, ri, isread);
1434 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1435 * the current EL, security state, and register configuration.
1437 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
1439 uint64_t filter;
1440 bool e, p, u, nsk, nsu, nsh, m;
1441 bool enabled, prohibited, filtered;
1442 bool secure = arm_is_secure(env);
1443 int el = arm_current_el(env);
1444 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
1445 uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
1447 if (!arm_feature(env, ARM_FEATURE_PMU)) {
1448 return false;
1451 if (!arm_feature(env, ARM_FEATURE_EL2) ||
1452 (counter < hpmn || counter == 31)) {
1453 e = env->cp15.c9_pmcr & PMCRE;
1454 } else {
1455 e = mdcr_el2 & MDCR_HPME;
1457 enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
1459 if (!secure) {
1460 if (el == 2 && (counter < hpmn || counter == 31)) {
1461 prohibited = mdcr_el2 & MDCR_HPMD;
1462 } else {
1463 prohibited = false;
1465 } else {
1466 prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
1467 !(env->cp15.mdcr_el3 & MDCR_SPME);
1470 if (prohibited && counter == 31) {
1471 prohibited = env->cp15.c9_pmcr & PMCRDP;
1474 if (counter == 31) {
1475 filter = env->cp15.pmccfiltr_el0;
1476 } else {
1477 filter = env->cp15.c14_pmevtyper[counter];
1480 p = filter & PMXEVTYPER_P;
1481 u = filter & PMXEVTYPER_U;
1482 nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK);
1483 nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU);
1484 nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH);
1485 m = arm_el_is_aa64(env, 1) &&
1486 arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M);
1488 if (el == 0) {
1489 filtered = secure ? u : u != nsu;
1490 } else if (el == 1) {
1491 filtered = secure ? p : p != nsk;
1492 } else if (el == 2) {
1493 filtered = !nsh;
1494 } else { /* EL3 */
1495 filtered = m != p;
1498 if (counter != 31) {
1500 * If not checking PMCCNTR, ensure the counter is setup to an event we
1501 * support
1503 uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
1504 if (!event_supported(event)) {
1505 return false;
1509 return enabled && !prohibited && !filtered;
1512 static void pmu_update_irq(CPUARMState *env)
1514 ARMCPU *cpu = env_archcpu(env);
1515 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
1516 (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
1520 * Ensure c15_ccnt is the guest-visible count so that operations such as
1521 * enabling/disabling the counter or filtering, modifying the count itself,
1522 * etc. can be done logically. This is essentially a no-op if the counter is
1523 * not enabled at the time of the call.
1525 static void pmccntr_op_start(CPUARMState *env)
1527 uint64_t cycles = cycles_get_count(env);
1529 if (pmu_counter_enabled(env, 31)) {
1530 uint64_t eff_cycles = cycles;
1531 if (env->cp15.c9_pmcr & PMCRD) {
1532 /* Increment once every 64 processor clock cycles */
1533 eff_cycles /= 64;
1536 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta;
1538 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
1539 1ull << 63 : 1ull << 31;
1540 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
1541 env->cp15.c9_pmovsr |= (1 << 31);
1542 pmu_update_irq(env);
1545 env->cp15.c15_ccnt = new_pmccntr;
1547 env->cp15.c15_ccnt_delta = cycles;
1551 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1552 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1553 * pmccntr_op_start.
1555 static void pmccntr_op_finish(CPUARMState *env)
1557 if (pmu_counter_enabled(env, 31)) {
1558 #ifndef CONFIG_USER_ONLY
1559 /* Calculate when the counter will next overflow */
1560 uint64_t remaining_cycles = -env->cp15.c15_ccnt;
1561 if (!(env->cp15.c9_pmcr & PMCRLC)) {
1562 remaining_cycles = (uint32_t)remaining_cycles;
1564 int64_t overflow_in = cycles_ns_per(remaining_cycles);
1566 if (overflow_in > 0) {
1567 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1568 overflow_in;
1569 ARMCPU *cpu = env_archcpu(env);
1570 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1572 #endif
1574 uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
1575 if (env->cp15.c9_pmcr & PMCRD) {
1576 /* Increment once every 64 processor clock cycles */
1577 prev_cycles /= 64;
1579 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;
1583 static void pmevcntr_op_start(CPUARMState *env, uint8_t counter)
1586 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1587 uint64_t count = 0;
1588 if (event_supported(event)) {
1589 uint16_t event_idx = supported_event_map[event];
1590 count = pm_events[event_idx].get_count(env);
1593 if (pmu_counter_enabled(env, counter)) {
1594 uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter];
1596 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) {
1597 env->cp15.c9_pmovsr |= (1 << counter);
1598 pmu_update_irq(env);
1600 env->cp15.c14_pmevcntr[counter] = new_pmevcntr;
1602 env->cp15.c14_pmevcntr_delta[counter] = count;
1605 static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
1607 if (pmu_counter_enabled(env, counter)) {
1608 #ifndef CONFIG_USER_ONLY
1609 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1610 uint16_t event_idx = supported_event_map[event];
1611 uint64_t delta = UINT32_MAX -
1612 (uint32_t)env->cp15.c14_pmevcntr[counter] + 1;
1613 int64_t overflow_in = pm_events[event_idx].ns_per_count(delta);
1615 if (overflow_in > 0) {
1616 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1617 overflow_in;
1618 ARMCPU *cpu = env_archcpu(env);
1619 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1621 #endif
1623 env->cp15.c14_pmevcntr_delta[counter] -=
1624 env->cp15.c14_pmevcntr[counter];
1628 void pmu_op_start(CPUARMState *env)
1630 unsigned int i;
1631 pmccntr_op_start(env);
1632 for (i = 0; i < pmu_num_counters(env); i++) {
1633 pmevcntr_op_start(env, i);
1637 void pmu_op_finish(CPUARMState *env)
1639 unsigned int i;
1640 pmccntr_op_finish(env);
1641 for (i = 0; i < pmu_num_counters(env); i++) {
1642 pmevcntr_op_finish(env, i);
1646 void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
1648 pmu_op_start(&cpu->env);
1651 void pmu_post_el_change(ARMCPU *cpu, void *ignored)
1653 pmu_op_finish(&cpu->env);
1656 void arm_pmu_timer_cb(void *opaque)
1658 ARMCPU *cpu = opaque;
1661 * Update all the counter values based on the current underlying counts,
1662 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1663 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1664 * counter may expire.
1666 pmu_op_start(&cpu->env);
1667 pmu_op_finish(&cpu->env);
1670 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1671 uint64_t value)
1673 pmu_op_start(env);
1675 if (value & PMCRC) {
1676 /* The counter has been reset */
1677 env->cp15.c15_ccnt = 0;
1680 if (value & PMCRP) {
1681 unsigned int i;
1682 for (i = 0; i < pmu_num_counters(env); i++) {
1683 env->cp15.c14_pmevcntr[i] = 0;
1687 env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
1688 env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
1690 pmu_op_finish(env);
1693 static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri,
1694 uint64_t value)
1696 unsigned int i;
1697 for (i = 0; i < pmu_num_counters(env); i++) {
1698 /* Increment a counter's count iff: */
1699 if ((value & (1 << i)) && /* counter's bit is set */
1700 /* counter is enabled and not filtered */
1701 pmu_counter_enabled(env, i) &&
1702 /* counter is SW_INCR */
1703 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
1704 pmevcntr_op_start(env, i);
1707 * Detect if this write causes an overflow since we can't predict
1708 * PMSWINC overflows like we can for other events
1710 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
1712 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
1713 env->cp15.c9_pmovsr |= (1 << i);
1714 pmu_update_irq(env);
1717 env->cp15.c14_pmevcntr[i] = new_pmswinc;
1719 pmevcntr_op_finish(env, i);
1724 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1726 uint64_t ret;
1727 pmccntr_op_start(env);
1728 ret = env->cp15.c15_ccnt;
1729 pmccntr_op_finish(env);
1730 return ret;
1733 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1734 uint64_t value)
1736 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1737 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1738 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1739 * accessed.
1741 env->cp15.c9_pmselr = value & 0x1f;
1744 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1745 uint64_t value)
1747 pmccntr_op_start(env);
1748 env->cp15.c15_ccnt = value;
1749 pmccntr_op_finish(env);
1752 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
1753 uint64_t value)
1755 uint64_t cur_val = pmccntr_read(env, NULL);
1757 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
1760 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1761 uint64_t value)
1763 pmccntr_op_start(env);
1764 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0;
1765 pmccntr_op_finish(env);
1768 static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
1769 uint64_t value)
1771 pmccntr_op_start(env);
1772 /* M is not accessible from AArch32 */
1773 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) |
1774 (value & PMCCFILTR);
1775 pmccntr_op_finish(env);
1778 static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
1780 /* M is not visible in AArch32 */
1781 return env->cp15.pmccfiltr_el0 & PMCCFILTR;
1784 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1785 uint64_t value)
1787 value &= pmu_counter_mask(env);
1788 env->cp15.c9_pmcnten |= value;
1791 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1792 uint64_t value)
1794 value &= pmu_counter_mask(env);
1795 env->cp15.c9_pmcnten &= ~value;
1798 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1799 uint64_t value)
1801 value &= pmu_counter_mask(env);
1802 env->cp15.c9_pmovsr &= ~value;
1803 pmu_update_irq(env);
1806 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1807 uint64_t value)
1809 value &= pmu_counter_mask(env);
1810 env->cp15.c9_pmovsr |= value;
1811 pmu_update_irq(env);
1814 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1815 uint64_t value, const uint8_t counter)
1817 if (counter == 31) {
1818 pmccfiltr_write(env, ri, value);
1819 } else if (counter < pmu_num_counters(env)) {
1820 pmevcntr_op_start(env, counter);
1823 * If this counter's event type is changing, store the current
1824 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1825 * pmevcntr_op_finish has the correct baseline when it converts back to
1826 * a delta.
1828 uint16_t old_event = env->cp15.c14_pmevtyper[counter] &
1829 PMXEVTYPER_EVTCOUNT;
1830 uint16_t new_event = value & PMXEVTYPER_EVTCOUNT;
1831 if (old_event != new_event) {
1832 uint64_t count = 0;
1833 if (event_supported(new_event)) {
1834 uint16_t event_idx = supported_event_map[new_event];
1835 count = pm_events[event_idx].get_count(env);
1837 env->cp15.c14_pmevcntr_delta[counter] = count;
1840 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
1841 pmevcntr_op_finish(env, counter);
1843 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1844 * PMSELR value is equal to or greater than the number of implemented
1845 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1849 static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri,
1850 const uint8_t counter)
1852 if (counter == 31) {
1853 return env->cp15.pmccfiltr_el0;
1854 } else if (counter < pmu_num_counters(env)) {
1855 return env->cp15.c14_pmevtyper[counter];
1856 } else {
1858 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1859 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1861 return 0;
1865 static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1866 uint64_t value)
1868 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1869 pmevtyper_write(env, ri, value, counter);
1872 static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1873 uint64_t value)
1875 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1876 env->cp15.c14_pmevtyper[counter] = value;
1879 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1880 * pmu_op_finish calls when loading saved state for a migration. Because
1881 * we're potentially updating the type of event here, the value written to
1882 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1883 * different counter type. Therefore, we need to set this value to the
1884 * current count for the counter type we're writing so that pmu_op_finish
1885 * has the correct count for its calculation.
1887 uint16_t event = value & PMXEVTYPER_EVTCOUNT;
1888 if (event_supported(event)) {
1889 uint16_t event_idx = supported_event_map[event];
1890 env->cp15.c14_pmevcntr_delta[counter] =
1891 pm_events[event_idx].get_count(env);
1895 static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1897 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1898 return pmevtyper_read(env, ri, counter);
1901 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1902 uint64_t value)
1904 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31);
1907 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
1909 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31);
1912 static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1913 uint64_t value, uint8_t counter)
1915 if (counter < pmu_num_counters(env)) {
1916 pmevcntr_op_start(env, counter);
1917 env->cp15.c14_pmevcntr[counter] = value;
1918 pmevcntr_op_finish(env, counter);
1921 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1922 * are CONSTRAINED UNPREDICTABLE.
1926 static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1927 uint8_t counter)
1929 if (counter < pmu_num_counters(env)) {
1930 uint64_t ret;
1931 pmevcntr_op_start(env, counter);
1932 ret = env->cp15.c14_pmevcntr[counter];
1933 pmevcntr_op_finish(env, counter);
1934 return ret;
1935 } else {
1936 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1937 * are CONSTRAINED UNPREDICTABLE. */
1938 return 0;
1942 static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1943 uint64_t value)
1945 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1946 pmevcntr_write(env, ri, value, counter);
1949 static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1951 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1952 return pmevcntr_read(env, ri, counter);
1955 static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1956 uint64_t value)
1958 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1959 assert(counter < pmu_num_counters(env));
1960 env->cp15.c14_pmevcntr[counter] = value;
1961 pmevcntr_write(env, ri, value, counter);
1964 static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri)
1966 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1967 assert(counter < pmu_num_counters(env));
1968 return env->cp15.c14_pmevcntr[counter];
1971 static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1972 uint64_t value)
1974 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31);
1977 static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1979 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31);
1982 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1983 uint64_t value)
1985 if (arm_feature(env, ARM_FEATURE_V8)) {
1986 env->cp15.c9_pmuserenr = value & 0xf;
1987 } else {
1988 env->cp15.c9_pmuserenr = value & 1;
1992 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1993 uint64_t value)
1995 /* We have no event counters so only the C bit can be changed */
1996 value &= pmu_counter_mask(env);
1997 env->cp15.c9_pminten |= value;
1998 pmu_update_irq(env);
2001 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2002 uint64_t value)
2004 value &= pmu_counter_mask(env);
2005 env->cp15.c9_pminten &= ~value;
2006 pmu_update_irq(env);
2009 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2010 uint64_t value)
2012 /* Note that even though the AArch64 view of this register has bits
2013 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
2014 * architectural requirements for bits which are RES0 only in some
2015 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
2016 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
2018 raw_write(env, ri, value & ~0x1FULL);
2021 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2023 /* Begin with base v8.0 state. */
2024 uint32_t valid_mask = 0x3fff;
2025 ARMCPU *cpu = env_archcpu(env);
2027 if (ri->state == ARM_CP_STATE_AA64) {
2028 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
2029 !cpu_isar_feature(aa64_aa32_el1, cpu)) {
2030 value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
2032 valid_mask &= ~SCR_NET;
2034 if (cpu_isar_feature(aa64_lor, cpu)) {
2035 valid_mask |= SCR_TLOR;
2037 if (cpu_isar_feature(aa64_pauth, cpu)) {
2038 valid_mask |= SCR_API | SCR_APK;
2040 if (cpu_isar_feature(aa64_sel2, cpu)) {
2041 valid_mask |= SCR_EEL2;
2043 if (cpu_isar_feature(aa64_mte, cpu)) {
2044 valid_mask |= SCR_ATA;
2046 } else {
2047 valid_mask &= ~(SCR_RW | SCR_ST);
2050 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2051 valid_mask &= ~SCR_HCE;
2053 /* On ARMv7, SMD (or SCD as it is called in v7) is only
2054 * supported if EL2 exists. The bit is UNK/SBZP when
2055 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
2056 * when EL2 is unavailable.
2057 * On ARMv8, this bit is always available.
2059 if (arm_feature(env, ARM_FEATURE_V7) &&
2060 !arm_feature(env, ARM_FEATURE_V8)) {
2061 valid_mask &= ~SCR_SMD;
2065 /* Clear all-context RES0 bits. */
2066 value &= valid_mask;
2067 raw_write(env, ri, value);
2070 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2073 * scr_write will set the RES1 bits on an AArch64-only CPU.
2074 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
2076 scr_write(env, ri, 0);
2079 static CPAccessResult access_aa64_tid2(CPUARMState *env,
2080 const ARMCPRegInfo *ri,
2081 bool isread)
2083 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
2084 return CP_ACCESS_TRAP_EL2;
2087 return CP_ACCESS_OK;
2090 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2092 ARMCPU *cpu = env_archcpu(env);
2094 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
2095 * bank
2097 uint32_t index = A32_BANKED_REG_GET(env, csselr,
2098 ri->secure & ARM_CP_SECSTATE_S);
2100 return cpu->ccsidr[index];
2103 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2104 uint64_t value)
2106 raw_write(env, ri, value & 0xf);
2109 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2111 CPUState *cs = env_cpu(env);
2112 bool el1 = arm_current_el(env) == 1;
2113 uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0;
2114 uint64_t ret = 0;
2116 if (hcr_el2 & HCR_IMO) {
2117 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
2118 ret |= CPSR_I;
2120 } else {
2121 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
2122 ret |= CPSR_I;
2126 if (hcr_el2 & HCR_FMO) {
2127 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
2128 ret |= CPSR_F;
2130 } else {
2131 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
2132 ret |= CPSR_F;
2136 /* External aborts are not possible in QEMU so A bit is always clear */
2137 return ret;
2140 static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2141 bool isread)
2143 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) {
2144 return CP_ACCESS_TRAP_EL2;
2147 return CP_ACCESS_OK;
2150 static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2151 bool isread)
2153 if (arm_feature(env, ARM_FEATURE_V8)) {
2154 return access_aa64_tid1(env, ri, isread);
2157 return CP_ACCESS_OK;
2160 static const ARMCPRegInfo v7_cp_reginfo[] = {
2161 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2162 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
2163 .access = PL1_W, .type = ARM_CP_NOP },
2164 /* Performance monitors are implementation defined in v7,
2165 * but with an ARM recommended set of registers, which we
2166 * follow.
2168 * Performance registers fall into three categories:
2169 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2170 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2171 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2172 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2173 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2175 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
2176 .access = PL0_RW, .type = ARM_CP_ALIAS,
2177 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
2178 .writefn = pmcntenset_write,
2179 .accessfn = pmreg_access,
2180 .raw_writefn = raw_write },
2181 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
2182 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
2183 .access = PL0_RW, .accessfn = pmreg_access,
2184 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
2185 .writefn = pmcntenset_write, .raw_writefn = raw_write },
2186 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
2187 .access = PL0_RW,
2188 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
2189 .accessfn = pmreg_access,
2190 .writefn = pmcntenclr_write,
2191 .type = ARM_CP_ALIAS },
2192 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
2193 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
2194 .access = PL0_RW, .accessfn = pmreg_access,
2195 .type = ARM_CP_ALIAS,
2196 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
2197 .writefn = pmcntenclr_write },
2198 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
2199 .access = PL0_RW, .type = ARM_CP_IO,
2200 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2201 .accessfn = pmreg_access,
2202 .writefn = pmovsr_write,
2203 .raw_writefn = raw_write },
2204 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
2205 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
2206 .access = PL0_RW, .accessfn = pmreg_access,
2207 .type = ARM_CP_ALIAS | ARM_CP_IO,
2208 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2209 .writefn = pmovsr_write,
2210 .raw_writefn = raw_write },
2211 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
2212 .access = PL0_W, .accessfn = pmreg_access_swinc,
2213 .type = ARM_CP_NO_RAW | ARM_CP_IO,
2214 .writefn = pmswinc_write },
2215 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
2216 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
2217 .access = PL0_W, .accessfn = pmreg_access_swinc,
2218 .type = ARM_CP_NO_RAW | ARM_CP_IO,
2219 .writefn = pmswinc_write },
2220 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
2221 .access = PL0_RW, .type = ARM_CP_ALIAS,
2222 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
2223 .accessfn = pmreg_access_selr, .writefn = pmselr_write,
2224 .raw_writefn = raw_write},
2225 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
2226 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
2227 .access = PL0_RW, .accessfn = pmreg_access_selr,
2228 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
2229 .writefn = pmselr_write, .raw_writefn = raw_write, },
2230 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
2231 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
2232 .readfn = pmccntr_read, .writefn = pmccntr_write32,
2233 .accessfn = pmreg_access_ccntr },
2234 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
2235 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
2236 .access = PL0_RW, .accessfn = pmreg_access_ccntr,
2237 .type = ARM_CP_IO,
2238 .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
2239 .readfn = pmccntr_read, .writefn = pmccntr_write,
2240 .raw_readfn = raw_read, .raw_writefn = raw_write, },
2241 { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
2242 .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
2243 .access = PL0_RW, .accessfn = pmreg_access,
2244 .type = ARM_CP_ALIAS | ARM_CP_IO,
2245 .resetvalue = 0, },
2246 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
2247 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
2248 .writefn = pmccfiltr_write, .raw_writefn = raw_write,
2249 .access = PL0_RW, .accessfn = pmreg_access,
2250 .type = ARM_CP_IO,
2251 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
2252 .resetvalue = 0, },
2253 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
2254 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2255 .accessfn = pmreg_access,
2256 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2257 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
2258 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
2259 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2260 .accessfn = pmreg_access,
2261 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2262 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
2263 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2264 .accessfn = pmreg_access_xevcntr,
2265 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2266 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
2267 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
2268 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2269 .accessfn = pmreg_access_xevcntr,
2270 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2271 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
2272 .access = PL0_R | PL1_RW, .accessfn = access_tpm,
2273 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
2274 .resetvalue = 0,
2275 .writefn = pmuserenr_write, .raw_writefn = raw_write },
2276 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
2277 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
2278 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
2279 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
2280 .resetvalue = 0,
2281 .writefn = pmuserenr_write, .raw_writefn = raw_write },
2282 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
2283 .access = PL1_RW, .accessfn = access_tpm,
2284 .type = ARM_CP_ALIAS | ARM_CP_IO,
2285 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
2286 .resetvalue = 0,
2287 .writefn = pmintenset_write, .raw_writefn = raw_write },
2288 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
2289 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
2290 .access = PL1_RW, .accessfn = access_tpm,
2291 .type = ARM_CP_IO,
2292 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2293 .writefn = pmintenset_write, .raw_writefn = raw_write,
2294 .resetvalue = 0x0 },
2295 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
2296 .access = PL1_RW, .accessfn = access_tpm,
2297 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
2298 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2299 .writefn = pmintenclr_write, },
2300 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
2301 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
2302 .access = PL1_RW, .accessfn = access_tpm,
2303 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
2304 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2305 .writefn = pmintenclr_write },
2306 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2307 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
2308 .access = PL1_R,
2309 .accessfn = access_aa64_tid2,
2310 .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
2311 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2312 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
2313 .access = PL1_RW,
2314 .accessfn = access_aa64_tid2,
2315 .writefn = csselr_write, .resetvalue = 0,
2316 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
2317 offsetof(CPUARMState, cp15.csselr_ns) } },
2318 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2319 * just RAZ for all cores:
2321 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2322 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
2323 .access = PL1_R, .type = ARM_CP_CONST,
2324 .accessfn = access_aa64_tid1,
2325 .resetvalue = 0 },
2326 /* Auxiliary fault status registers: these also are IMPDEF, and we
2327 * choose to RAZ/WI for all cores.
2329 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
2330 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
2331 .access = PL1_RW, .accessfn = access_tvm_trvm,
2332 .type = ARM_CP_CONST, .resetvalue = 0 },
2333 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
2334 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
2335 .access = PL1_RW, .accessfn = access_tvm_trvm,
2336 .type = ARM_CP_CONST, .resetvalue = 0 },
2337 /* MAIR can just read-as-written because we don't implement caches
2338 * and so don't need to care about memory attributes.
2340 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
2341 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2342 .access = PL1_RW, .accessfn = access_tvm_trvm,
2343 .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
2344 .resetvalue = 0 },
2345 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
2346 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
2347 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
2348 .resetvalue = 0 },
2349 /* For non-long-descriptor page tables these are PRRR and NMRR;
2350 * regardless they still act as reads-as-written for QEMU.
2352 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2353 * allows them to assign the correct fieldoffset based on the endianness
2354 * handled in the field definitions.
2356 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2357 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2358 .access = PL1_RW, .accessfn = access_tvm_trvm,
2359 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
2360 offsetof(CPUARMState, cp15.mair0_ns) },
2361 .resetfn = arm_cp_reset_ignore },
2362 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
2363 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1,
2364 .access = PL1_RW, .accessfn = access_tvm_trvm,
2365 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
2366 offsetof(CPUARMState, cp15.mair1_ns) },
2367 .resetfn = arm_cp_reset_ignore },
2368 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2369 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
2370 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
2371 /* 32 bit ITLB invalidates */
2372 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2373 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2374 .writefn = tlbiall_write },
2375 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2376 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2377 .writefn = tlbimva_write },
2378 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2379 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2380 .writefn = tlbiasid_write },
2381 /* 32 bit DTLB invalidates */
2382 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2383 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2384 .writefn = tlbiall_write },
2385 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2386 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2387 .writefn = tlbimva_write },
2388 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2389 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2390 .writefn = tlbiasid_write },
2391 /* 32 bit TLB invalidates */
2392 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2393 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2394 .writefn = tlbiall_write },
2395 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2396 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2397 .writefn = tlbimva_write },
2398 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2399 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2400 .writefn = tlbiasid_write },
2401 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2402 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2403 .writefn = tlbimvaa_write },
2404 REGINFO_SENTINEL
2407 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
2408 /* 32 bit TLB invalidates, Inner Shareable */
2409 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2410 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2411 .writefn = tlbiall_is_write },
2412 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2413 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2414 .writefn = tlbimva_is_write },
2415 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2416 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2417 .writefn = tlbiasid_is_write },
2418 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2419 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2420 .writefn = tlbimvaa_is_write },
2421 REGINFO_SENTINEL
2424 static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
2425 /* PMOVSSET is not implemented in v7 before v7ve */
2426 { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
2427 .access = PL0_RW, .accessfn = pmreg_access,
2428 .type = ARM_CP_ALIAS | ARM_CP_IO,
2429 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2430 .writefn = pmovsset_write,
2431 .raw_writefn = raw_write },
2432 { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
2433 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
2434 .access = PL0_RW, .accessfn = pmreg_access,
2435 .type = ARM_CP_ALIAS | ARM_CP_IO,
2436 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2437 .writefn = pmovsset_write,
2438 .raw_writefn = raw_write },
2439 REGINFO_SENTINEL
2442 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2443 uint64_t value)
2445 value &= 1;
2446 env->teecr = value;
2449 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
2450 bool isread)
2452 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
2453 return CP_ACCESS_TRAP;
2455 return CP_ACCESS_OK;
2458 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
2459 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
2460 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
2461 .resetvalue = 0,
2462 .writefn = teecr_write },
2463 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
2464 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
2465 .accessfn = teehbr_access, .resetvalue = 0 },
2466 REGINFO_SENTINEL
2469 static const ARMCPRegInfo v6k_cp_reginfo[] = {
2470 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
2471 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
2472 .access = PL0_RW,
2473 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
2474 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
2475 .access = PL0_RW,
2476 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
2477 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
2478 .resetfn = arm_cp_reset_ignore },
2479 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
2480 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
2481 .access = PL0_R|PL1_W,
2482 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
2483 .resetvalue = 0},
2484 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
2485 .access = PL0_R|PL1_W,
2486 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
2487 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
2488 .resetfn = arm_cp_reset_ignore },
2489 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
2490 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
2491 .access = PL1_RW,
2492 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
2493 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
2494 .access = PL1_RW,
2495 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
2496 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
2497 .resetvalue = 0 },
2498 REGINFO_SENTINEL
2501 #ifndef CONFIG_USER_ONLY
2503 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
2504 bool isread)
2506 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2507 * Writable only at the highest implemented exception level.
2509 int el = arm_current_el(env);
2510 uint64_t hcr;
2511 uint32_t cntkctl;
2513 switch (el) {
2514 case 0:
2515 hcr = arm_hcr_el2_eff(env);
2516 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2517 cntkctl = env->cp15.cnthctl_el2;
2518 } else {
2519 cntkctl = env->cp15.c14_cntkctl;
2521 if (!extract32(cntkctl, 0, 2)) {
2522 return CP_ACCESS_TRAP;
2524 break;
2525 case 1:
2526 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
2527 arm_is_secure_below_el3(env)) {
2528 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2529 return CP_ACCESS_TRAP_UNCATEGORIZED;
2531 break;
2532 case 2:
2533 case 3:
2534 break;
2537 if (!isread && el < arm_highest_el(env)) {
2538 return CP_ACCESS_TRAP_UNCATEGORIZED;
2541 return CP_ACCESS_OK;
2544 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
2545 bool isread)
2547 unsigned int cur_el = arm_current_el(env);
2548 bool has_el2 = arm_is_el2_enabled(env);
2549 uint64_t hcr = arm_hcr_el2_eff(env);
2551 switch (cur_el) {
2552 case 0:
2553 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2554 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2555 return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
2556 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2559 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2560 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
2561 return CP_ACCESS_TRAP;
2564 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2565 if (hcr & HCR_E2H) {
2566 if (timeridx == GTIMER_PHYS &&
2567 !extract32(env->cp15.cnthctl_el2, 10, 1)) {
2568 return CP_ACCESS_TRAP_EL2;
2570 } else {
2571 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2572 if (has_el2 && timeridx == GTIMER_PHYS &&
2573 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
2574 return CP_ACCESS_TRAP_EL2;
2577 break;
2579 case 1:
2580 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2581 if (has_el2 && timeridx == GTIMER_PHYS &&
2582 (hcr & HCR_E2H
2583 ? !extract32(env->cp15.cnthctl_el2, 10, 1)
2584 : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
2585 return CP_ACCESS_TRAP_EL2;
2587 break;
2589 return CP_ACCESS_OK;
2592 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
2593 bool isread)
2595 unsigned int cur_el = arm_current_el(env);
2596 bool has_el2 = arm_is_el2_enabled(env);
2597 uint64_t hcr = arm_hcr_el2_eff(env);
2599 switch (cur_el) {
2600 case 0:
2601 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2602 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2603 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
2604 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2608 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2609 * EL0 if EL0[PV]TEN is zero.
2611 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
2612 return CP_ACCESS_TRAP;
2614 /* fall through */
2616 case 1:
2617 if (has_el2 && timeridx == GTIMER_PHYS) {
2618 if (hcr & HCR_E2H) {
2619 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2620 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
2621 return CP_ACCESS_TRAP_EL2;
2623 } else {
2624 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2625 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
2626 return CP_ACCESS_TRAP_EL2;
2630 break;
2632 return CP_ACCESS_OK;
2635 static CPAccessResult gt_pct_access(CPUARMState *env,
2636 const ARMCPRegInfo *ri,
2637 bool isread)
2639 return gt_counter_access(env, GTIMER_PHYS, isread);
2642 static CPAccessResult gt_vct_access(CPUARMState *env,
2643 const ARMCPRegInfo *ri,
2644 bool isread)
2646 return gt_counter_access(env, GTIMER_VIRT, isread);
2649 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2650 bool isread)
2652 return gt_timer_access(env, GTIMER_PHYS, isread);
2655 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2656 bool isread)
2658 return gt_timer_access(env, GTIMER_VIRT, isread);
2661 static CPAccessResult gt_stimer_access(CPUARMState *env,
2662 const ARMCPRegInfo *ri,
2663 bool isread)
2665 /* The AArch64 register view of the secure physical timer is
2666 * always accessible from EL3, and configurably accessible from
2667 * Secure EL1.
2669 switch (arm_current_el(env)) {
2670 case 1:
2671 if (!arm_is_secure(env)) {
2672 return CP_ACCESS_TRAP;
2674 if (!(env->cp15.scr_el3 & SCR_ST)) {
2675 return CP_ACCESS_TRAP_EL3;
2677 return CP_ACCESS_OK;
2678 case 0:
2679 case 2:
2680 return CP_ACCESS_TRAP;
2681 case 3:
2682 return CP_ACCESS_OK;
2683 default:
2684 g_assert_not_reached();
2688 static uint64_t gt_get_countervalue(CPUARMState *env)
2690 ARMCPU *cpu = env_archcpu(env);
2692 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu);
2695 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
2697 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
2699 if (gt->ctl & 1) {
2700 /* Timer enabled: calculate and set current ISTATUS, irq, and
2701 * reset timer to when ISTATUS next has to change
2703 uint64_t offset = timeridx == GTIMER_VIRT ?
2704 cpu->env.cp15.cntvoff_el2 : 0;
2705 uint64_t count = gt_get_countervalue(&cpu->env);
2706 /* Note that this must be unsigned 64 bit arithmetic: */
2707 int istatus = count - offset >= gt->cval;
2708 uint64_t nexttick;
2709 int irqstate;
2711 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
2713 irqstate = (istatus && !(gt->ctl & 2));
2714 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2716 if (istatus) {
2717 /* Next transition is when count rolls back over to zero */
2718 nexttick = UINT64_MAX;
2719 } else {
2720 /* Next transition is when we hit cval */
2721 nexttick = gt->cval + offset;
2723 /* Note that the desired next expiry time might be beyond the
2724 * signed-64-bit range of a QEMUTimer -- in this case we just
2725 * set the timer for as far in the future as possible. When the
2726 * timer expires we will reset the timer for any remaining period.
2728 if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {
2729 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX);
2730 } else {
2731 timer_mod(cpu->gt_timer[timeridx], nexttick);
2733 trace_arm_gt_recalc(timeridx, irqstate, nexttick);
2734 } else {
2735 /* Timer disabled: ISTATUS and timer output always clear */
2736 gt->ctl &= ~4;
2737 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
2738 timer_del(cpu->gt_timer[timeridx]);
2739 trace_arm_gt_recalc_disabled(timeridx);
2743 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
2744 int timeridx)
2746 ARMCPU *cpu = env_archcpu(env);
2748 timer_del(cpu->gt_timer[timeridx]);
2751 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2753 return gt_get_countervalue(env);
2756 static uint64_t gt_virt_cnt_offset(CPUARMState *env)
2758 uint64_t hcr;
2760 switch (arm_current_el(env)) {
2761 case 2:
2762 hcr = arm_hcr_el2_eff(env);
2763 if (hcr & HCR_E2H) {
2764 return 0;
2766 break;
2767 case 0:
2768 hcr = arm_hcr_el2_eff(env);
2769 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2770 return 0;
2772 break;
2775 return env->cp15.cntvoff_el2;
2778 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2780 return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
2783 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2784 int timeridx,
2785 uint64_t value)
2787 trace_arm_gt_cval_write(timeridx, value);
2788 env->cp15.c14_timer[timeridx].cval = value;
2789 gt_recalc_timer(env_archcpu(env), timeridx);
2792 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
2793 int timeridx)
2795 uint64_t offset = 0;
2797 switch (timeridx) {
2798 case GTIMER_VIRT:
2799 case GTIMER_HYPVIRT:
2800 offset = gt_virt_cnt_offset(env);
2801 break;
2804 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
2805 (gt_get_countervalue(env) - offset));
2808 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2809 int timeridx,
2810 uint64_t value)
2812 uint64_t offset = 0;
2814 switch (timeridx) {
2815 case GTIMER_VIRT:
2816 case GTIMER_HYPVIRT:
2817 offset = gt_virt_cnt_offset(env);
2818 break;
2821 trace_arm_gt_tval_write(timeridx, value);
2822 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
2823 sextract64(value, 0, 32);
2824 gt_recalc_timer(env_archcpu(env), timeridx);
2827 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2828 int timeridx,
2829 uint64_t value)
2831 ARMCPU *cpu = env_archcpu(env);
2832 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
2834 trace_arm_gt_ctl_write(timeridx, value);
2835 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
2836 if ((oldval ^ value) & 1) {
2837 /* Enable toggled */
2838 gt_recalc_timer(cpu, timeridx);
2839 } else if ((oldval ^ value) & 2) {
2840 /* IMASK toggled: don't need to recalculate,
2841 * just set the interrupt line based on ISTATUS
2843 int irqstate = (oldval & 4) && !(value & 2);
2845 trace_arm_gt_imask_toggle(timeridx, irqstate);
2846 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2850 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2852 gt_timer_reset(env, ri, GTIMER_PHYS);
2855 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856 uint64_t value)
2858 gt_cval_write(env, ri, GTIMER_PHYS, value);
2861 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2863 return gt_tval_read(env, ri, GTIMER_PHYS);
2866 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2867 uint64_t value)
2869 gt_tval_write(env, ri, GTIMER_PHYS, value);
2872 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2873 uint64_t value)
2875 gt_ctl_write(env, ri, GTIMER_PHYS, value);
2878 static int gt_phys_redir_timeridx(CPUARMState *env)
2880 switch (arm_mmu_idx(env)) {
2881 case ARMMMUIdx_E20_0:
2882 case ARMMMUIdx_E20_2:
2883 case ARMMMUIdx_E20_2_PAN:
2884 case ARMMMUIdx_SE20_0:
2885 case ARMMMUIdx_SE20_2:
2886 case ARMMMUIdx_SE20_2_PAN:
2887 return GTIMER_HYP;
2888 default:
2889 return GTIMER_PHYS;
2893 static int gt_virt_redir_timeridx(CPUARMState *env)
2895 switch (arm_mmu_idx(env)) {
2896 case ARMMMUIdx_E20_0:
2897 case ARMMMUIdx_E20_2:
2898 case ARMMMUIdx_E20_2_PAN:
2899 case ARMMMUIdx_SE20_0:
2900 case ARMMMUIdx_SE20_2:
2901 case ARMMMUIdx_SE20_2_PAN:
2902 return GTIMER_HYPVIRT;
2903 default:
2904 return GTIMER_VIRT;
2908 static uint64_t gt_phys_redir_cval_read(CPUARMState *env,
2909 const ARMCPRegInfo *ri)
2911 int timeridx = gt_phys_redir_timeridx(env);
2912 return env->cp15.c14_timer[timeridx].cval;
2915 static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2916 uint64_t value)
2918 int timeridx = gt_phys_redir_timeridx(env);
2919 gt_cval_write(env, ri, timeridx, value);
2922 static uint64_t gt_phys_redir_tval_read(CPUARMState *env,
2923 const ARMCPRegInfo *ri)
2925 int timeridx = gt_phys_redir_timeridx(env);
2926 return gt_tval_read(env, ri, timeridx);
2929 static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2930 uint64_t value)
2932 int timeridx = gt_phys_redir_timeridx(env);
2933 gt_tval_write(env, ri, timeridx, value);
2936 static uint64_t gt_phys_redir_ctl_read(CPUARMState *env,
2937 const ARMCPRegInfo *ri)
2939 int timeridx = gt_phys_redir_timeridx(env);
2940 return env->cp15.c14_timer[timeridx].ctl;
2943 static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2944 uint64_t value)
2946 int timeridx = gt_phys_redir_timeridx(env);
2947 gt_ctl_write(env, ri, timeridx, value);
2950 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2952 gt_timer_reset(env, ri, GTIMER_VIRT);
2955 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2956 uint64_t value)
2958 gt_cval_write(env, ri, GTIMER_VIRT, value);
2961 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2963 return gt_tval_read(env, ri, GTIMER_VIRT);
2966 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2967 uint64_t value)
2969 gt_tval_write(env, ri, GTIMER_VIRT, value);
2972 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2973 uint64_t value)
2975 gt_ctl_write(env, ri, GTIMER_VIRT, value);
2978 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
2979 uint64_t value)
2981 ARMCPU *cpu = env_archcpu(env);
2983 trace_arm_gt_cntvoff_write(value);
2984 raw_write(env, ri, value);
2985 gt_recalc_timer(cpu, GTIMER_VIRT);
2988 static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
2989 const ARMCPRegInfo *ri)
2991 int timeridx = gt_virt_redir_timeridx(env);
2992 return env->cp15.c14_timer[timeridx].cval;
2995 static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2996 uint64_t value)
2998 int timeridx = gt_virt_redir_timeridx(env);
2999 gt_cval_write(env, ri, timeridx, value);
3002 static uint64_t gt_virt_redir_tval_read(CPUARMState *env,
3003 const ARMCPRegInfo *ri)
3005 int timeridx = gt_virt_redir_timeridx(env);
3006 return gt_tval_read(env, ri, timeridx);
3009 static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3010 uint64_t value)
3012 int timeridx = gt_virt_redir_timeridx(env);
3013 gt_tval_write(env, ri, timeridx, value);
3016 static uint64_t gt_virt_redir_ctl_read(CPUARMState *env,
3017 const ARMCPRegInfo *ri)
3019 int timeridx = gt_virt_redir_timeridx(env);
3020 return env->cp15.c14_timer[timeridx].ctl;
3023 static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3024 uint64_t value)
3026 int timeridx = gt_virt_redir_timeridx(env);
3027 gt_ctl_write(env, ri, timeridx, value);
3030 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3032 gt_timer_reset(env, ri, GTIMER_HYP);
3035 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3036 uint64_t value)
3038 gt_cval_write(env, ri, GTIMER_HYP, value);
3041 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3043 return gt_tval_read(env, ri, GTIMER_HYP);
3046 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3047 uint64_t value)
3049 gt_tval_write(env, ri, GTIMER_HYP, value);
3052 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3053 uint64_t value)
3055 gt_ctl_write(env, ri, GTIMER_HYP, value);
3058 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3060 gt_timer_reset(env, ri, GTIMER_SEC);
3063 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3064 uint64_t value)
3066 gt_cval_write(env, ri, GTIMER_SEC, value);
3069 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3071 return gt_tval_read(env, ri, GTIMER_SEC);
3074 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3075 uint64_t value)
3077 gt_tval_write(env, ri, GTIMER_SEC, value);
3080 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3081 uint64_t value)
3083 gt_ctl_write(env, ri, GTIMER_SEC, value);
3086 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3088 gt_timer_reset(env, ri, GTIMER_HYPVIRT);
3091 static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3092 uint64_t value)
3094 gt_cval_write(env, ri, GTIMER_HYPVIRT, value);
3097 static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3099 return gt_tval_read(env, ri, GTIMER_HYPVIRT);
3102 static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3103 uint64_t value)
3105 gt_tval_write(env, ri, GTIMER_HYPVIRT, value);
3108 static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3109 uint64_t value)
3111 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value);
3114 void arm_gt_ptimer_cb(void *opaque)
3116 ARMCPU *cpu = opaque;
3118 gt_recalc_timer(cpu, GTIMER_PHYS);
3121 void arm_gt_vtimer_cb(void *opaque)
3123 ARMCPU *cpu = opaque;
3125 gt_recalc_timer(cpu, GTIMER_VIRT);
3128 void arm_gt_htimer_cb(void *opaque)
3130 ARMCPU *cpu = opaque;
3132 gt_recalc_timer(cpu, GTIMER_HYP);
3135 void arm_gt_stimer_cb(void *opaque)
3137 ARMCPU *cpu = opaque;
3139 gt_recalc_timer(cpu, GTIMER_SEC);
3142 void arm_gt_hvtimer_cb(void *opaque)
3144 ARMCPU *cpu = opaque;
3146 gt_recalc_timer(cpu, GTIMER_HYPVIRT);
3149 static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
3151 ARMCPU *cpu = env_archcpu(env);
3153 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
3156 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3157 /* Note that CNTFRQ is purely reads-as-written for the benefit
3158 * of software; writing it doesn't actually change the timer frequency.
3159 * Our reset value matches the fixed frequency we implement the timer at.
3161 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
3162 .type = ARM_CP_ALIAS,
3163 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3164 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
3166 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3167 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3168 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3169 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3170 .resetfn = arm_gt_cntfrq_reset,
3172 /* overall control: mostly access permissions */
3173 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
3174 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
3175 .access = PL1_RW,
3176 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
3177 .resetvalue = 0,
3179 /* per-timer control */
3180 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3181 .secure = ARM_CP_SECSTATE_NS,
3182 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3183 .accessfn = gt_ptimer_access,
3184 .fieldoffset = offsetoflow32(CPUARMState,
3185 cp15.c14_timer[GTIMER_PHYS].ctl),
3186 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3187 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
3189 { .name = "CNTP_CTL_S",
3190 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3191 .secure = ARM_CP_SECSTATE_S,
3192 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3193 .accessfn = gt_ptimer_access,
3194 .fieldoffset = offsetoflow32(CPUARMState,
3195 cp15.c14_timer[GTIMER_SEC].ctl),
3196 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3198 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
3199 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
3200 .type = ARM_CP_IO, .access = PL0_RW,
3201 .accessfn = gt_ptimer_access,
3202 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
3203 .resetvalue = 0,
3204 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3205 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
3207 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
3208 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3209 .accessfn = gt_vtimer_access,
3210 .fieldoffset = offsetoflow32(CPUARMState,
3211 cp15.c14_timer[GTIMER_VIRT].ctl),
3212 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3213 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
3215 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
3216 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
3217 .type = ARM_CP_IO, .access = PL0_RW,
3218 .accessfn = gt_vtimer_access,
3219 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
3220 .resetvalue = 0,
3221 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3222 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
3224 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3225 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3226 .secure = ARM_CP_SECSTATE_NS,
3227 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3228 .accessfn = gt_ptimer_access,
3229 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
3231 { .name = "CNTP_TVAL_S",
3232 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3233 .secure = ARM_CP_SECSTATE_S,
3234 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3235 .accessfn = gt_ptimer_access,
3236 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
3238 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3239 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
3240 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3241 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
3242 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
3244 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
3245 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3246 .accessfn = gt_vtimer_access,
3247 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
3249 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3250 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
3251 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3252 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
3253 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
3255 /* The counter itself */
3256 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
3257 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3258 .accessfn = gt_pct_access,
3259 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
3261 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
3262 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
3263 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3264 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
3266 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
3267 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3268 .accessfn = gt_vct_access,
3269 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
3271 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3272 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3273 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3274 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
3276 /* Comparison value, indicating when the timer goes off */
3277 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
3278 .secure = ARM_CP_SECSTATE_NS,
3279 .access = PL0_RW,
3280 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3281 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
3282 .accessfn = gt_ptimer_access,
3283 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3284 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
3286 { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
3287 .secure = ARM_CP_SECSTATE_S,
3288 .access = PL0_RW,
3289 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3290 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3291 .accessfn = gt_ptimer_access,
3292 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3294 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3295 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
3296 .access = PL0_RW,
3297 .type = ARM_CP_IO,
3298 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
3299 .resetvalue = 0, .accessfn = gt_ptimer_access,
3300 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3301 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
3303 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
3304 .access = PL0_RW,
3305 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3306 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3307 .accessfn = gt_vtimer_access,
3308 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3309 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
3311 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3312 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
3313 .access = PL0_RW,
3314 .type = ARM_CP_IO,
3315 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3316 .resetvalue = 0, .accessfn = gt_vtimer_access,
3317 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3318 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
3320 /* Secure timer -- this is actually restricted to only EL3
3321 * and configurably Secure-EL1 via the accessfn.
3323 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
3324 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
3325 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
3326 .accessfn = gt_stimer_access,
3327 .readfn = gt_sec_tval_read,
3328 .writefn = gt_sec_tval_write,
3329 .resetfn = gt_sec_timer_reset,
3331 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
3332 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
3333 .type = ARM_CP_IO, .access = PL1_RW,
3334 .accessfn = gt_stimer_access,
3335 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
3336 .resetvalue = 0,
3337 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3339 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
3340 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
3341 .type = ARM_CP_IO, .access = PL1_RW,
3342 .accessfn = gt_stimer_access,
3343 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3344 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3346 REGINFO_SENTINEL
3349 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
3350 bool isread)
3352 if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
3353 return CP_ACCESS_TRAP;
3355 return CP_ACCESS_OK;
3358 #else
3360 /* In user-mode most of the generic timer registers are inaccessible
3361 * however modern kernels (4.12+) allow access to cntvct_el0
3364 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
3366 ARMCPU *cpu = env_archcpu(env);
3368 /* Currently we have no support for QEMUTimer in linux-user so we
3369 * can't call gt_get_countervalue(env), instead we directly
3370 * call the lower level functions.
3372 return cpu_get_clock() / gt_cntfrq_period_ns(cpu);
3375 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3376 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3377 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3378 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
3379 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3380 .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
3382 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3383 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3384 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3385 .readfn = gt_virt_cnt_read,
3387 REGINFO_SENTINEL
3390 #endif
3392 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3394 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3395 raw_write(env, ri, value);
3396 } else if (arm_feature(env, ARM_FEATURE_V7)) {
3397 raw_write(env, ri, value & 0xfffff6ff);
3398 } else {
3399 raw_write(env, ri, value & 0xfffff1ff);
3403 #ifndef CONFIG_USER_ONLY
3404 /* get_phys_addr() isn't present for user-mode-only targets */
3406 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
3407 bool isread)
3409 if (ri->opc2 & 4) {
3410 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3411 * Secure EL1 (which can only happen if EL3 is AArch64).
3412 * They are simply UNDEF if executed from NS EL1.
3413 * They function normally from EL2 or EL3.
3415 if (arm_current_el(env) == 1) {
3416 if (arm_is_secure_below_el3(env)) {
3417 if (env->cp15.scr_el3 & SCR_EEL2) {
3418 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
3420 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
3422 return CP_ACCESS_TRAP_UNCATEGORIZED;
3425 return CP_ACCESS_OK;
3428 #ifdef CONFIG_TCG
3429 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
3430 MMUAccessType access_type, ARMMMUIdx mmu_idx)
3432 hwaddr phys_addr;
3433 target_ulong page_size;
3434 int prot;
3435 bool ret;
3436 uint64_t par64;
3437 bool format64 = false;
3438 MemTxAttrs attrs = {};
3439 ARMMMUFaultInfo fi = {};
3440 ARMCacheAttrs cacheattrs = {};
3442 ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
3443 &prot, &page_size, &fi, &cacheattrs);
3445 if (ret) {
3447 * Some kinds of translation fault must cause exceptions rather
3448 * than being reported in the PAR.
3450 int current_el = arm_current_el(env);
3451 int target_el;
3452 uint32_t syn, fsr, fsc;
3453 bool take_exc = false;
3455 if (fi.s1ptw && current_el == 1
3456 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
3458 * Synchronous stage 2 fault on an access made as part of the
3459 * translation table walk for AT S1E0* or AT S1E1* insn
3460 * executed from NS EL1. If this is a synchronous external abort
3461 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3462 * to EL3. Otherwise the fault is taken as an exception to EL2,
3463 * and HPFAR_EL2 holds the faulting IPA.
3465 if (fi.type == ARMFault_SyncExternalOnWalk &&
3466 (env->cp15.scr_el3 & SCR_EA)) {
3467 target_el = 3;
3468 } else {
3469 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
3470 if (arm_is_secure_below_el3(env) && fi.s1ns) {
3471 env->cp15.hpfar_el2 |= HPFAR_NS;
3473 target_el = 2;
3475 take_exc = true;
3476 } else if (fi.type == ARMFault_SyncExternalOnWalk) {
3478 * Synchronous external aborts during a translation table walk
3479 * are taken as Data Abort exceptions.
3481 if (fi.stage2) {
3482 if (current_el == 3) {
3483 target_el = 3;
3484 } else {
3485 target_el = 2;
3487 } else {
3488 target_el = exception_target_el(env);
3490 take_exc = true;
3493 if (take_exc) {
3494 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3495 if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
3496 arm_s1_regime_using_lpae_format(env, mmu_idx)) {
3497 fsr = arm_fi_to_lfsc(&fi);
3498 fsc = extract32(fsr, 0, 6);
3499 } else {
3500 fsr = arm_fi_to_sfsc(&fi);
3501 fsc = 0x3f;
3504 * Report exception with ESR indicating a fault due to a
3505 * translation table walk for a cache maintenance instruction.
3507 syn = syn_data_abort_no_iss(current_el == target_el, 0,
3508 fi.ea, 1, fi.s1ptw, 1, fsc);
3509 env->exception.vaddress = value;
3510 env->exception.fsr = fsr;
3511 raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
3515 if (is_a64(env)) {
3516 format64 = true;
3517 } else if (arm_feature(env, ARM_FEATURE_LPAE)) {
3519 * ATS1Cxx:
3520 * * TTBCR.EAE determines whether the result is returned using the
3521 * 32-bit or the 64-bit PAR format
3522 * * Instructions executed in Hyp mode always use the 64bit format
3524 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3525 * * The Non-secure TTBCR.EAE bit is set to 1
3526 * * The implementation includes EL2, and the value of HCR.VM is 1
3528 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3530 * ATS1Hx always uses the 64bit format.
3532 format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
3534 if (arm_feature(env, ARM_FEATURE_EL2)) {
3535 if (mmu_idx == ARMMMUIdx_E10_0 ||
3536 mmu_idx == ARMMMUIdx_E10_1 ||
3537 mmu_idx == ARMMMUIdx_E10_1_PAN) {
3538 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
3539 } else {
3540 format64 |= arm_current_el(env) == 2;
3545 if (format64) {
3546 /* Create a 64-bit PAR */
3547 par64 = (1 << 11); /* LPAE bit always set */
3548 if (!ret) {
3549 par64 |= phys_addr & ~0xfffULL;
3550 if (!attrs.secure) {
3551 par64 |= (1 << 9); /* NS */
3553 par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
3554 par64 |= cacheattrs.shareability << 7; /* SH */
3555 } else {
3556 uint32_t fsr = arm_fi_to_lfsc(&fi);
3558 par64 |= 1; /* F */
3559 par64 |= (fsr & 0x3f) << 1; /* FS */
3560 if (fi.stage2) {
3561 par64 |= (1 << 9); /* S */
3563 if (fi.s1ptw) {
3564 par64 |= (1 << 8); /* PTW */
3567 } else {
3568 /* fsr is a DFSR/IFSR value for the short descriptor
3569 * translation table format (with WnR always clear).
3570 * Convert it to a 32-bit PAR.
3572 if (!ret) {
3573 /* We do not set any attribute bits in the PAR */
3574 if (page_size == (1 << 24)
3575 && arm_feature(env, ARM_FEATURE_V7)) {
3576 par64 = (phys_addr & 0xff000000) | (1 << 1);
3577 } else {
3578 par64 = phys_addr & 0xfffff000;
3580 if (!attrs.secure) {
3581 par64 |= (1 << 9); /* NS */
3583 } else {
3584 uint32_t fsr = arm_fi_to_sfsc(&fi);
3586 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
3587 ((fsr & 0xf) << 1) | 1;
3590 return par64;
3592 #endif /* CONFIG_TCG */
3594 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3596 #ifdef CONFIG_TCG
3597 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3598 uint64_t par64;
3599 ARMMMUIdx mmu_idx;
3600 int el = arm_current_el(env);
3601 bool secure = arm_is_secure_below_el3(env);
3603 switch (ri->opc2 & 6) {
3604 case 0:
3605 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3606 switch (el) {
3607 case 3:
3608 mmu_idx = ARMMMUIdx_SE3;
3609 break;
3610 case 2:
3611 g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
3612 /* fall through */
3613 case 1:
3614 if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
3615 mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
3616 : ARMMMUIdx_Stage1_E1_PAN);
3617 } else {
3618 mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
3620 break;
3621 default:
3622 g_assert_not_reached();
3624 break;
3625 case 2:
3626 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3627 switch (el) {
3628 case 3:
3629 mmu_idx = ARMMMUIdx_SE10_0;
3630 break;
3631 case 2:
3632 g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
3633 mmu_idx = ARMMMUIdx_Stage1_E0;
3634 break;
3635 case 1:
3636 mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
3637 break;
3638 default:
3639 g_assert_not_reached();
3641 break;
3642 case 4:
3643 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3644 mmu_idx = ARMMMUIdx_E10_1;
3645 break;
3646 case 6:
3647 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3648 mmu_idx = ARMMMUIdx_E10_0;
3649 break;
3650 default:
3651 g_assert_not_reached();
3654 par64 = do_ats_write(env, value, access_type, mmu_idx);
3656 A32_BANKED_CURRENT_REG_SET(env, par, par64);
3657 #else
3658 /* Handled by hardware accelerator. */
3659 g_assert_not_reached();
3660 #endif /* CONFIG_TCG */
3663 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
3664 uint64_t value)
3666 #ifdef CONFIG_TCG
3667 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3668 uint64_t par64;
3670 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
3672 A32_BANKED_CURRENT_REG_SET(env, par, par64);
3673 #else
3674 /* Handled by hardware accelerator. */
3675 g_assert_not_reached();
3676 #endif /* CONFIG_TCG */
3679 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
3680 bool isread)
3682 if (arm_current_el(env) == 3 &&
3683 !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
3684 return CP_ACCESS_TRAP;
3686 return CP_ACCESS_OK;
3689 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
3690 uint64_t value)
3692 #ifdef CONFIG_TCG
3693 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3694 ARMMMUIdx mmu_idx;
3695 int secure = arm_is_secure_below_el3(env);
3697 switch (ri->opc2 & 6) {
3698 case 0:
3699 switch (ri->opc1) {
3700 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3701 if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
3702 mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
3703 : ARMMMUIdx_Stage1_E1_PAN);
3704 } else {
3705 mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
3707 break;
3708 case 4: /* AT S1E2R, AT S1E2W */
3709 mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2;
3710 break;
3711 case 6: /* AT S1E3R, AT S1E3W */
3712 mmu_idx = ARMMMUIdx_SE3;
3713 break;
3714 default:
3715 g_assert_not_reached();
3717 break;
3718 case 2: /* AT S1E0R, AT S1E0W */
3719 mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
3720 break;
3721 case 4: /* AT S12E1R, AT S12E1W */
3722 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
3723 break;
3724 case 6: /* AT S12E0R, AT S12E0W */
3725 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
3726 break;
3727 default:
3728 g_assert_not_reached();
3731 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
3732 #else
3733 /* Handled by hardware accelerator. */
3734 g_assert_not_reached();
3735 #endif /* CONFIG_TCG */
3737 #endif
3739 static const ARMCPRegInfo vapa_cp_reginfo[] = {
3740 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
3741 .access = PL1_RW, .resetvalue = 0,
3742 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
3743 offsetoflow32(CPUARMState, cp15.par_ns) },
3744 .writefn = par_write },
3745 #ifndef CONFIG_USER_ONLY
3746 /* This underdecoding is safe because the reginfo is NO_RAW. */
3747 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
3748 .access = PL1_W, .accessfn = ats_access,
3749 .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
3750 #endif
3751 REGINFO_SENTINEL
3754 /* Return basic MPU access permission bits. */
3755 static uint32_t simple_mpu_ap_bits(uint32_t val)
3757 uint32_t ret;
3758 uint32_t mask;
3759 int i;
3760 ret = 0;
3761 mask = 3;
3762 for (i = 0; i < 16; i += 2) {
3763 ret |= (val >> i) & mask;
3764 mask <<= 2;
3766 return ret;
3769 /* Pad basic MPU access permission bits to extended format. */
3770 static uint32_t extended_mpu_ap_bits(uint32_t val)
3772 uint32_t ret;
3773 uint32_t mask;
3774 int i;
3775 ret = 0;
3776 mask = 3;
3777 for (i = 0; i < 16; i += 2) {
3778 ret |= (val & mask) << i;
3779 mask <<= 2;
3781 return ret;
3784 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3785 uint64_t value)
3787 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
3790 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
3792 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
3795 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3796 uint64_t value)
3798 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
3801 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
3803 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
3806 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
3808 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3810 if (!u32p) {
3811 return 0;
3814 u32p += env->pmsav7.rnr[M_REG_NS];
3815 return *u32p;
3818 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
3819 uint64_t value)
3821 ARMCPU *cpu = env_archcpu(env);
3822 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3824 if (!u32p) {
3825 return;
3828 u32p += env->pmsav7.rnr[M_REG_NS];
3829 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
3830 *u32p = value;
3833 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3834 uint64_t value)
3836 ARMCPU *cpu = env_archcpu(env);
3837 uint32_t nrgs = cpu->pmsav7_dregion;
3839 if (value >= nrgs) {
3840 qemu_log_mask(LOG_GUEST_ERROR,
3841 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3842 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
3843 return;
3846 raw_write(env, ri, value);
3849 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
3850 /* Reset for all these registers is handled in arm_cpu_reset(),
3851 * because the PMSAv7 is also used by M-profile CPUs, which do
3852 * not register cpregs but still need the state to be reset.
3854 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
3855 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3856 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
3857 .readfn = pmsav7_read, .writefn = pmsav7_write,
3858 .resetfn = arm_cp_reset_ignore },
3859 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
3860 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3861 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
3862 .readfn = pmsav7_read, .writefn = pmsav7_write,
3863 .resetfn = arm_cp_reset_ignore },
3864 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
3865 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3866 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
3867 .readfn = pmsav7_read, .writefn = pmsav7_write,
3868 .resetfn = arm_cp_reset_ignore },
3869 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
3870 .access = PL1_RW,
3871 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
3872 .writefn = pmsav7_rgnr_write,
3873 .resetfn = arm_cp_reset_ignore },
3874 REGINFO_SENTINEL
3877 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
3878 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
3879 .access = PL1_RW, .type = ARM_CP_ALIAS,
3880 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3881 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
3882 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
3883 .access = PL1_RW, .type = ARM_CP_ALIAS,
3884 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3885 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
3886 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
3887 .access = PL1_RW,
3888 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3889 .resetvalue = 0, },
3890 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
3891 .access = PL1_RW,
3892 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3893 .resetvalue = 0, },
3894 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3895 .access = PL1_RW,
3896 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
3897 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
3898 .access = PL1_RW,
3899 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
3900 /* Protection region base and size registers */
3901 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
3902 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3903 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
3904 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
3905 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3906 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
3907 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
3908 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3909 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
3910 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
3911 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3912 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
3913 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
3914 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3915 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
3916 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
3917 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3918 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
3919 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
3920 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3921 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
3922 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
3923 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3924 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
3925 REGINFO_SENTINEL
3928 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
3929 uint64_t value)
3931 TCR *tcr = raw_ptr(env, ri);
3932 int maskshift = extract32(value, 0, 3);
3934 if (!arm_feature(env, ARM_FEATURE_V8)) {
3935 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
3936 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3937 * using Long-desciptor translation table format */
3938 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
3939 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
3940 /* In an implementation that includes the Security Extensions
3941 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3942 * Short-descriptor translation table format.
3944 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
3945 } else {
3946 value &= TTBCR_N;
3950 /* Update the masks corresponding to the TCR bank being written
3951 * Note that we always calculate mask and base_mask, but
3952 * they are only used for short-descriptor tables (ie if EAE is 0);
3953 * for long-descriptor tables the TCR fields are used differently
3954 * and the mask and base_mask values are meaningless.
3956 tcr->raw_tcr = value;
3957 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
3958 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
3961 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3962 uint64_t value)
3964 ARMCPU *cpu = env_archcpu(env);
3965 TCR *tcr = raw_ptr(env, ri);
3967 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3968 /* With LPAE the TTBCR could result in a change of ASID
3969 * via the TTBCR.A1 bit, so do a TLB flush.
3971 tlb_flush(CPU(cpu));
3973 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3974 value = deposit64(tcr->raw_tcr, 0, 32, value);
3975 vmsa_ttbcr_raw_write(env, ri, value);
3978 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3980 TCR *tcr = raw_ptr(env, ri);
3982 /* Reset both the TCR as well as the masks corresponding to the bank of
3983 * the TCR being reset.
3985 tcr->raw_tcr = 0;
3986 tcr->mask = 0;
3987 tcr->base_mask = 0xffffc000u;
3990 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
3991 uint64_t value)
3993 ARMCPU *cpu = env_archcpu(env);
3994 TCR *tcr = raw_ptr(env, ri);
3996 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3997 tlb_flush(CPU(cpu));
3998 tcr->raw_tcr = value;
4001 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4002 uint64_t value)
4004 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4005 if (cpreg_field_is_64bit(ri) &&
4006 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
4007 ARMCPU *cpu = env_archcpu(env);
4008 tlb_flush(CPU(cpu));
4010 raw_write(env, ri, value);
4013 static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4014 uint64_t value)
4017 * If we are running with E2&0 regime, then an ASID is active.
4018 * Flush if that might be changing. Note we're not checking
4019 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4020 * holds the active ASID, only checking the field that might.
4022 if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
4023 (arm_hcr_el2_eff(env) & HCR_E2H)) {
4024 uint16_t mask = ARMMMUIdxBit_E20_2 |
4025 ARMMMUIdxBit_E20_2_PAN |
4026 ARMMMUIdxBit_E20_0;
4028 if (arm_is_secure_below_el3(env)) {
4029 mask >>= ARM_MMU_IDX_A_NS;
4032 tlb_flush_by_mmuidx(env_cpu(env), mask);
4034 raw_write(env, ri, value);
4037 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4038 uint64_t value)
4040 ARMCPU *cpu = env_archcpu(env);
4041 CPUState *cs = CPU(cpu);
4044 * A change in VMID to the stage2 page table (Stage2) invalidates
4045 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
4047 if (raw_read(env, ri) != value) {
4048 uint16_t mask = ARMMMUIdxBit_E10_1 |
4049 ARMMMUIdxBit_E10_1_PAN |
4050 ARMMMUIdxBit_E10_0;
4052 if (arm_is_secure_below_el3(env)) {
4053 mask >>= ARM_MMU_IDX_A_NS;
4056 tlb_flush_by_mmuidx(cs, mask);
4057 raw_write(env, ri, value);
4061 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
4062 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
4063 .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS,
4064 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
4065 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
4066 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
4067 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
4068 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
4069 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
4070 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
4071 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
4072 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
4073 offsetof(CPUARMState, cp15.dfar_ns) } },
4074 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
4075 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
4076 .access = PL1_RW, .accessfn = access_tvm_trvm,
4077 .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
4078 .resetvalue = 0, },
4079 REGINFO_SENTINEL
4082 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
4083 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
4084 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
4085 .access = PL1_RW, .accessfn = access_tvm_trvm,
4086 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
4087 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
4088 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
4089 .access = PL1_RW, .accessfn = access_tvm_trvm,
4090 .writefn = vmsa_ttbr_write, .resetvalue = 0,
4091 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4092 offsetof(CPUARMState, cp15.ttbr0_ns) } },
4093 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
4094 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
4095 .access = PL1_RW, .accessfn = access_tvm_trvm,
4096 .writefn = vmsa_ttbr_write, .resetvalue = 0,
4097 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4098 offsetof(CPUARMState, cp15.ttbr1_ns) } },
4099 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
4100 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
4101 .access = PL1_RW, .accessfn = access_tvm_trvm,
4102 .writefn = vmsa_tcr_el12_write,
4103 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
4104 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
4105 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
4106 .access = PL1_RW, .accessfn = access_tvm_trvm,
4107 .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
4108 .raw_writefn = vmsa_ttbcr_raw_write,
4109 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
4110 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
4111 REGINFO_SENTINEL
4114 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4115 * qemu tlbs nor adjusting cached masks.
4117 static const ARMCPRegInfo ttbcr2_reginfo = {
4118 .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
4119 .access = PL1_RW, .accessfn = access_tvm_trvm,
4120 .type = ARM_CP_ALIAS,
4121 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
4122 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
4125 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
4126 uint64_t value)
4128 env->cp15.c15_ticonfig = value & 0xe7;
4129 /* The OS_TYPE bit in this register changes the reported CPUID! */
4130 env->cp15.c0_cpuid = (value & (1 << 5)) ?
4131 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
4134 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
4135 uint64_t value)
4137 env->cp15.c15_threadid = value & 0xffff;
4140 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
4141 uint64_t value)
4143 /* Wait-for-interrupt (deprecated) */
4144 cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
4147 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
4148 uint64_t value)
4150 /* On OMAP there are registers indicating the max/min index of dcache lines
4151 * containing a dirty line; cache flush operations have to reset these.
4153 env->cp15.c15_i_max = 0x000;
4154 env->cp15.c15_i_min = 0xff0;
4157 static const ARMCPRegInfo omap_cp_reginfo[] = {
4158 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
4159 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
4160 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
4161 .resetvalue = 0, },
4162 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
4163 .access = PL1_RW, .type = ARM_CP_NOP },
4164 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
4165 .access = PL1_RW,
4166 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
4167 .writefn = omap_ticonfig_write },
4168 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
4169 .access = PL1_RW,
4170 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
4171 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
4172 .access = PL1_RW, .resetvalue = 0xff0,
4173 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
4174 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
4175 .access = PL1_RW,
4176 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
4177 .writefn = omap_threadid_write },
4178 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
4179 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4180 .type = ARM_CP_NO_RAW,
4181 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
4182 /* TODO: Peripheral port remap register:
4183 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4184 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4185 * when MMU is off.
4187 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
4188 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
4189 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
4190 .writefn = omap_cachemaint_write },
4191 { .name = "C9", .cp = 15, .crn = 9,
4192 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
4193 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
4194 REGINFO_SENTINEL
4197 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
4198 uint64_t value)
4200 env->cp15.c15_cpar = value & 0x3fff;
4203 static const ARMCPRegInfo xscale_cp_reginfo[] = {
4204 { .name = "XSCALE_CPAR",
4205 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4206 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
4207 .writefn = xscale_cpar_write, },
4208 { .name = "XSCALE_AUXCR",
4209 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
4210 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
4211 .resetvalue = 0, },
4212 /* XScale specific cache-lockdown: since we have no cache we NOP these
4213 * and hope the guest does not really rely on cache behaviour.
4215 { .name = "XSCALE_LOCK_ICACHE_LINE",
4216 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
4217 .access = PL1_W, .type = ARM_CP_NOP },
4218 { .name = "XSCALE_UNLOCK_ICACHE",
4219 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
4220 .access = PL1_W, .type = ARM_CP_NOP },
4221 { .name = "XSCALE_DCACHE_LOCK",
4222 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
4223 .access = PL1_RW, .type = ARM_CP_NOP },
4224 { .name = "XSCALE_UNLOCK_DCACHE",
4225 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
4226 .access = PL1_W, .type = ARM_CP_NOP },
4227 REGINFO_SENTINEL
4230 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
4231 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4232 * implementation of this implementation-defined space.
4233 * Ideally this should eventually disappear in favour of actually
4234 * implementing the correct behaviour for all cores.
4236 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
4237 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
4238 .access = PL1_RW,
4239 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
4240 .resetvalue = 0 },
4241 REGINFO_SENTINEL
4244 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
4245 /* Cache status: RAZ because we have no cache so it's always clean */
4246 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
4247 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4248 .resetvalue = 0 },
4249 REGINFO_SENTINEL
4252 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
4253 /* We never have a a block transfer operation in progress */
4254 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
4255 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4256 .resetvalue = 0 },
4257 /* The cache ops themselves: these all NOP for QEMU */
4258 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
4259 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4260 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
4261 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4262 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
4263 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4264 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
4265 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4266 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
4267 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4268 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
4269 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4270 REGINFO_SENTINEL
4273 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
4274 /* The cache test-and-clean instructions always return (1 << 30)
4275 * to indicate that there are no dirty cache lines.
4277 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
4278 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4279 .resetvalue = (1 << 30) },
4280 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
4281 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4282 .resetvalue = (1 << 30) },
4283 REGINFO_SENTINEL
4286 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
4287 /* Ignore ReadBuffer accesses */
4288 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
4289 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
4290 .access = PL1_RW, .resetvalue = 0,
4291 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
4292 REGINFO_SENTINEL
4295 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4297 unsigned int cur_el = arm_current_el(env);
4299 if (arm_is_el2_enabled(env) && cur_el == 1) {
4300 return env->cp15.vpidr_el2;
4302 return raw_read(env, ri);
4305 static uint64_t mpidr_read_val(CPUARMState *env)
4307 ARMCPU *cpu = env_archcpu(env);
4308 uint64_t mpidr = cpu->mp_affinity;
4310 if (arm_feature(env, ARM_FEATURE_V7MP)) {
4311 mpidr |= (1U << 31);
4312 /* Cores which are uniprocessor (non-coherent)
4313 * but still implement the MP extensions set
4314 * bit 30. (For instance, Cortex-R5).
4316 if (cpu->mp_is_up) {
4317 mpidr |= (1u << 30);
4320 return mpidr;
4323 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4325 unsigned int cur_el = arm_current_el(env);
4327 if (arm_is_el2_enabled(env) && cur_el == 1) {
4328 return env->cp15.vmpidr_el2;
4330 return mpidr_read_val(env);
4333 static const ARMCPRegInfo lpae_cp_reginfo[] = {
4334 /* NOP AMAIR0/1 */
4335 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
4336 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
4337 .access = PL1_RW, .accessfn = access_tvm_trvm,
4338 .type = ARM_CP_CONST, .resetvalue = 0 },
4339 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4340 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
4341 .access = PL1_RW, .accessfn = access_tvm_trvm,
4342 .type = ARM_CP_CONST, .resetvalue = 0 },
4343 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
4344 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
4345 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
4346 offsetof(CPUARMState, cp15.par_ns)} },
4347 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
4348 .access = PL1_RW, .accessfn = access_tvm_trvm,
4349 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4350 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4351 offsetof(CPUARMState, cp15.ttbr0_ns) },
4352 .writefn = vmsa_ttbr_write, },
4353 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
4354 .access = PL1_RW, .accessfn = access_tvm_trvm,
4355 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4356 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4357 offsetof(CPUARMState, cp15.ttbr1_ns) },
4358 .writefn = vmsa_ttbr_write, },
4359 REGINFO_SENTINEL
4362 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4364 return vfp_get_fpcr(env);
4367 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4368 uint64_t value)
4370 vfp_set_fpcr(env, value);
4373 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4375 return vfp_get_fpsr(env);
4378 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4379 uint64_t value)
4381 vfp_set_fpsr(env, value);
4384 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
4385 bool isread)
4387 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
4388 return CP_ACCESS_TRAP;
4390 return CP_ACCESS_OK;
4393 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
4394 uint64_t value)
4396 env->daif = value & PSTATE_DAIF;
4399 static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri)
4401 return env->pstate & PSTATE_PAN;
4404 static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri,
4405 uint64_t value)
4407 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN);
4410 static const ARMCPRegInfo pan_reginfo = {
4411 .name = "PAN", .state = ARM_CP_STATE_AA64,
4412 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3,
4413 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4414 .readfn = aa64_pan_read, .writefn = aa64_pan_write
4417 static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri)
4419 return env->pstate & PSTATE_UAO;
4422 static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri,
4423 uint64_t value)
4425 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO);
4428 static const ARMCPRegInfo uao_reginfo = {
4429 .name = "UAO", .state = ARM_CP_STATE_AA64,
4430 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
4431 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4432 .readfn = aa64_uao_read, .writefn = aa64_uao_write
4435 static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri)
4437 return env->pstate & PSTATE_DIT;
4440 static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri,
4441 uint64_t value)
4443 env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT);
4446 static const ARMCPRegInfo dit_reginfo = {
4447 .name = "DIT", .state = ARM_CP_STATE_AA64,
4448 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5,
4449 .type = ARM_CP_NO_RAW, .access = PL0_RW,
4450 .readfn = aa64_dit_read, .writefn = aa64_dit_write
4453 static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
4455 return env->pstate & PSTATE_SSBS;
4458 static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
4459 uint64_t value)
4461 env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);
4464 static const ARMCPRegInfo ssbs_reginfo = {
4465 .name = "SSBS", .state = ARM_CP_STATE_AA64,
4466 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,
4467 .type = ARM_CP_NO_RAW, .access = PL0_RW,
4468 .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write
4471 static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
4472 const ARMCPRegInfo *ri,
4473 bool isread)
4475 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4476 switch (arm_current_el(env)) {
4477 case 0:
4478 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4479 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
4480 return CP_ACCESS_TRAP;
4482 /* fall through */
4483 case 1:
4484 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4485 if (arm_hcr_el2_eff(env) & HCR_TPCP) {
4486 return CP_ACCESS_TRAP_EL2;
4488 break;
4490 return CP_ACCESS_OK;
4493 static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
4494 const ARMCPRegInfo *ri,
4495 bool isread)
4497 /* Cache invalidate/clean to Point of Unification... */
4498 switch (arm_current_el(env)) {
4499 case 0:
4500 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4501 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
4502 return CP_ACCESS_TRAP;
4504 /* fall through */
4505 case 1:
4506 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4507 if (arm_hcr_el2_eff(env) & HCR_TPU) {
4508 return CP_ACCESS_TRAP_EL2;
4510 break;
4512 return CP_ACCESS_OK;
4515 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4516 * Page D4-1736 (DDI0487A.b)
4519 static int vae1_tlbmask(CPUARMState *env)
4521 uint64_t hcr = arm_hcr_el2_eff(env);
4522 uint16_t mask;
4524 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
4525 mask = ARMMMUIdxBit_E20_2 |
4526 ARMMMUIdxBit_E20_2_PAN |
4527 ARMMMUIdxBit_E20_0;
4528 } else {
4529 mask = ARMMMUIdxBit_E10_1 |
4530 ARMMMUIdxBit_E10_1_PAN |
4531 ARMMMUIdxBit_E10_0;
4534 if (arm_is_secure_below_el3(env)) {
4535 mask >>= ARM_MMU_IDX_A_NS;
4538 return mask;
4541 /* Return 56 if TBI is enabled, 64 otherwise. */
4542 static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
4543 uint64_t addr)
4545 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
4546 int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
4547 int select = extract64(addr, 55, 1);
4549 return (tbi >> select) & 1 ? 56 : 64;
4552 static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
4554 uint64_t hcr = arm_hcr_el2_eff(env);
4555 ARMMMUIdx mmu_idx;
4557 /* Only the regime of the mmu_idx below is significant. */
4558 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
4559 mmu_idx = ARMMMUIdx_E20_0;
4560 } else {
4561 mmu_idx = ARMMMUIdx_E10_0;
4564 if (arm_is_secure_below_el3(env)) {
4565 mmu_idx &= ~ARM_MMU_IDX_A_NS;
4568 return tlbbits_for_regime(env, mmu_idx, addr);
4571 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4572 uint64_t value)
4574 CPUState *cs = env_cpu(env);
4575 int mask = vae1_tlbmask(env);
4577 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4580 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4581 uint64_t value)
4583 CPUState *cs = env_cpu(env);
4584 int mask = vae1_tlbmask(env);
4586 if (tlb_force_broadcast(env)) {
4587 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4588 } else {
4589 tlb_flush_by_mmuidx(cs, mask);
4593 static int alle1_tlbmask(CPUARMState *env)
4596 * Note that the 'ALL' scope must invalidate both stage 1 and
4597 * stage 2 translations, whereas most other scopes only invalidate
4598 * stage 1 translations.
4600 if (arm_is_secure_below_el3(env)) {
4601 return ARMMMUIdxBit_SE10_1 |
4602 ARMMMUIdxBit_SE10_1_PAN |
4603 ARMMMUIdxBit_SE10_0;
4604 } else {
4605 return ARMMMUIdxBit_E10_1 |
4606 ARMMMUIdxBit_E10_1_PAN |
4607 ARMMMUIdxBit_E10_0;
4611 static int e2_tlbmask(CPUARMState *env)
4613 if (arm_is_secure_below_el3(env)) {
4614 return ARMMMUIdxBit_SE20_0 |
4615 ARMMMUIdxBit_SE20_2 |
4616 ARMMMUIdxBit_SE20_2_PAN |
4617 ARMMMUIdxBit_SE2;
4618 } else {
4619 return ARMMMUIdxBit_E20_0 |
4620 ARMMMUIdxBit_E20_2 |
4621 ARMMMUIdxBit_E20_2_PAN |
4622 ARMMMUIdxBit_E2;
4626 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4627 uint64_t value)
4629 CPUState *cs = env_cpu(env);
4630 int mask = alle1_tlbmask(env);
4632 tlb_flush_by_mmuidx(cs, mask);
4635 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4636 uint64_t value)
4638 CPUState *cs = env_cpu(env);
4639 int mask = e2_tlbmask(env);
4641 tlb_flush_by_mmuidx(cs, mask);
4644 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4645 uint64_t value)
4647 ARMCPU *cpu = env_archcpu(env);
4648 CPUState *cs = CPU(cpu);
4650 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
4653 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4654 uint64_t value)
4656 CPUState *cs = env_cpu(env);
4657 int mask = alle1_tlbmask(env);
4659 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4662 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4663 uint64_t value)
4665 CPUState *cs = env_cpu(env);
4666 int mask = e2_tlbmask(env);
4668 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4671 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4672 uint64_t value)
4674 CPUState *cs = env_cpu(env);
4676 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
4679 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4680 uint64_t value)
4682 /* Invalidate by VA, EL2
4683 * Currently handles both VAE2 and VALE2, since we don't support
4684 * flush-last-level-only.
4686 CPUState *cs = env_cpu(env);
4687 int mask = e2_tlbmask(env);
4688 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4690 tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
4693 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4694 uint64_t value)
4696 /* Invalidate by VA, EL3
4697 * Currently handles both VAE3 and VALE3, since we don't support
4698 * flush-last-level-only.
4700 ARMCPU *cpu = env_archcpu(env);
4701 CPUState *cs = CPU(cpu);
4702 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4704 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
4707 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4708 uint64_t value)
4710 CPUState *cs = env_cpu(env);
4711 int mask = vae1_tlbmask(env);
4712 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4713 int bits = vae1_tlbbits(env, pageaddr);
4715 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
4718 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4719 uint64_t value)
4721 /* Invalidate by VA, EL1&0 (AArch64 version).
4722 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4723 * since we don't support flush-for-specific-ASID-only or
4724 * flush-last-level-only.
4726 CPUState *cs = env_cpu(env);
4727 int mask = vae1_tlbmask(env);
4728 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4729 int bits = vae1_tlbbits(env, pageaddr);
4731 if (tlb_force_broadcast(env)) {
4732 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
4733 } else {
4734 tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
4738 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4739 uint64_t value)
4741 CPUState *cs = env_cpu(env);
4742 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4743 bool secure = arm_is_secure_below_el3(env);
4744 int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2;
4745 int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2,
4746 pageaddr);
4748 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
4751 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4752 uint64_t value)
4754 CPUState *cs = env_cpu(env);
4755 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4756 int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
4758 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
4759 ARMMMUIdxBit_SE3, bits);
4762 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
4763 bool isread)
4765 int cur_el = arm_current_el(env);
4767 if (cur_el < 2) {
4768 uint64_t hcr = arm_hcr_el2_eff(env);
4770 if (cur_el == 0) {
4771 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
4772 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
4773 return CP_ACCESS_TRAP_EL2;
4775 } else {
4776 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
4777 return CP_ACCESS_TRAP;
4779 if (hcr & HCR_TDZ) {
4780 return CP_ACCESS_TRAP_EL2;
4783 } else if (hcr & HCR_TDZ) {
4784 return CP_ACCESS_TRAP_EL2;
4787 return CP_ACCESS_OK;
4790 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
4792 ARMCPU *cpu = env_archcpu(env);
4793 int dzp_bit = 1 << 4;
4795 /* DZP indicates whether DC ZVA access is allowed */
4796 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
4797 dzp_bit = 0;
4799 return cpu->dcz_blocksize | dzp_bit;
4802 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4803 bool isread)
4805 if (!(env->pstate & PSTATE_SP)) {
4806 /* Access to SP_EL0 is undefined if it's being used as
4807 * the stack pointer.
4809 return CP_ACCESS_TRAP_UNCATEGORIZED;
4811 return CP_ACCESS_OK;
4814 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
4816 return env->pstate & PSTATE_SP;
4819 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
4821 update_spsel(env, val);
4824 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4825 uint64_t value)
4827 ARMCPU *cpu = env_archcpu(env);
4829 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
4830 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4831 value &= ~SCTLR_M;
4834 /* ??? Lots of these bits are not implemented. */
4836 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
4837 if (ri->opc1 == 6) { /* SCTLR_EL3 */
4838 value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
4839 } else {
4840 value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
4841 SCTLR_ATA0 | SCTLR_ATA);
4845 if (raw_read(env, ri) == value) {
4846 /* Skip the TLB flush if nothing actually changed; Linux likes
4847 * to do a lot of pointless SCTLR writes.
4849 return;
4852 raw_write(env, ri, value);
4854 /* This may enable/disable the MMU, so do a TLB flush. */
4855 tlb_flush(CPU(cpu));
4857 if (ri->type & ARM_CP_SUPPRESS_TB_END) {
4859 * Normally we would always end the TB on an SCTLR write; see the
4860 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4861 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4862 * of hflags from the translator, so do it here.
4864 arm_rebuild_hflags(env);
4868 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
4869 bool isread)
4871 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
4872 return CP_ACCESS_TRAP_FP_EL2;
4874 if (env->cp15.cptr_el[3] & CPTR_TFP) {
4875 return CP_ACCESS_TRAP_FP_EL3;
4877 return CP_ACCESS_OK;
4880 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4881 uint64_t value)
4883 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
4886 static const ARMCPRegInfo v8_cp_reginfo[] = {
4887 /* Minimal set of EL0-visible registers. This will need to be expanded
4888 * significantly for system emulation of AArch64 CPUs.
4890 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
4891 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
4892 .access = PL0_RW, .type = ARM_CP_NZCV },
4893 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
4894 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
4895 .type = ARM_CP_NO_RAW,
4896 .access = PL0_RW, .accessfn = aa64_daif_access,
4897 .fieldoffset = offsetof(CPUARMState, daif),
4898 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
4899 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
4900 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
4901 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
4902 .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
4903 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
4904 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
4905 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
4906 .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
4907 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
4908 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
4909 .access = PL0_R, .type = ARM_CP_NO_RAW,
4910 .readfn = aa64_dczid_read },
4911 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
4912 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
4913 .access = PL0_W, .type = ARM_CP_DC_ZVA,
4914 #ifndef CONFIG_USER_ONLY
4915 /* Avoid overhead of an access check that always passes in user-mode */
4916 .accessfn = aa64_zva_access,
4917 #endif
4919 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
4920 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
4921 .access = PL1_R, .type = ARM_CP_CURRENTEL },
4922 /* Cache ops: all NOPs since we don't emulate caches */
4923 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
4924 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
4925 .access = PL1_W, .type = ARM_CP_NOP,
4926 .accessfn = aa64_cacheop_pou_access },
4927 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
4928 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
4929 .access = PL1_W, .type = ARM_CP_NOP,
4930 .accessfn = aa64_cacheop_pou_access },
4931 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
4932 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
4933 .access = PL0_W, .type = ARM_CP_NOP,
4934 .accessfn = aa64_cacheop_pou_access },
4935 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
4936 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
4937 .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
4938 .type = ARM_CP_NOP },
4939 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
4940 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
4941 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
4942 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
4943 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
4944 .access = PL0_W, .type = ARM_CP_NOP,
4945 .accessfn = aa64_cacheop_poc_access },
4946 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
4947 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
4948 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
4949 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
4950 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
4951 .access = PL0_W, .type = ARM_CP_NOP,
4952 .accessfn = aa64_cacheop_pou_access },
4953 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
4954 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
4955 .access = PL0_W, .type = ARM_CP_NOP,
4956 .accessfn = aa64_cacheop_poc_access },
4957 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
4958 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
4959 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
4960 /* TLBI operations */
4961 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
4962 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
4963 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4964 .writefn = tlbi_aa64_vmalle1is_write },
4965 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
4966 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
4967 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4968 .writefn = tlbi_aa64_vae1is_write },
4969 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
4970 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
4971 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4972 .writefn = tlbi_aa64_vmalle1is_write },
4973 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
4974 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
4975 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4976 .writefn = tlbi_aa64_vae1is_write },
4977 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
4978 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
4979 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4980 .writefn = tlbi_aa64_vae1is_write },
4981 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
4982 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
4983 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4984 .writefn = tlbi_aa64_vae1is_write },
4985 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
4986 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
4987 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4988 .writefn = tlbi_aa64_vmalle1_write },
4989 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
4990 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
4991 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4992 .writefn = tlbi_aa64_vae1_write },
4993 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
4994 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
4995 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4996 .writefn = tlbi_aa64_vmalle1_write },
4997 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
4998 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
4999 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
5000 .writefn = tlbi_aa64_vae1_write },
5001 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
5002 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
5003 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
5004 .writefn = tlbi_aa64_vae1_write },
5005 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
5006 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
5007 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
5008 .writefn = tlbi_aa64_vae1_write },
5009 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
5010 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
5011 .access = PL2_W, .type = ARM_CP_NOP },
5012 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
5013 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
5014 .access = PL2_W, .type = ARM_CP_NOP },
5015 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
5016 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
5017 .access = PL2_W, .type = ARM_CP_NO_RAW,
5018 .writefn = tlbi_aa64_alle1is_write },
5019 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
5020 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
5021 .access = PL2_W, .type = ARM_CP_NO_RAW,
5022 .writefn = tlbi_aa64_alle1is_write },
5023 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
5024 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
5025 .access = PL2_W, .type = ARM_CP_NOP },
5026 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
5027 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
5028 .access = PL2_W, .type = ARM_CP_NOP },
5029 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
5030 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
5031 .access = PL2_W, .type = ARM_CP_NO_RAW,
5032 .writefn = tlbi_aa64_alle1_write },
5033 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
5034 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
5035 .access = PL2_W, .type = ARM_CP_NO_RAW,
5036 .writefn = tlbi_aa64_alle1is_write },
5037 #ifndef CONFIG_USER_ONLY
5038 /* 64 bit address translation operations */
5039 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
5040 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
5041 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5042 .writefn = ats_write64 },
5043 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
5044 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
5045 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5046 .writefn = ats_write64 },
5047 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
5048 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
5049 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5050 .writefn = ats_write64 },
5051 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
5052 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
5053 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5054 .writefn = ats_write64 },
5055 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
5056 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
5057 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5058 .writefn = ats_write64 },
5059 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
5060 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
5061 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5062 .writefn = ats_write64 },
5063 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
5064 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
5065 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5066 .writefn = ats_write64 },
5067 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
5068 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
5069 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5070 .writefn = ats_write64 },
5071 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5072 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
5073 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
5074 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5075 .writefn = ats_write64 },
5076 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
5077 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
5078 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
5079 .writefn = ats_write64 },
5080 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
5081 .type = ARM_CP_ALIAS,
5082 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
5083 .access = PL1_RW, .resetvalue = 0,
5084 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
5085 .writefn = par_write },
5086 #endif
5087 /* TLB invalidate last level of translation table walk */
5088 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
5089 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5090 .writefn = tlbimva_is_write },
5091 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
5092 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5093 .writefn = tlbimvaa_is_write },
5094 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
5095 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5096 .writefn = tlbimva_write },
5097 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
5098 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5099 .writefn = tlbimvaa_write },
5100 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5101 .type = ARM_CP_NO_RAW, .access = PL2_W,
5102 .writefn = tlbimva_hyp_write },
5103 { .name = "TLBIMVALHIS",
5104 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5105 .type = ARM_CP_NO_RAW, .access = PL2_W,
5106 .writefn = tlbimva_hyp_is_write },
5107 { .name = "TLBIIPAS2",
5108 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
5109 .type = ARM_CP_NOP, .access = PL2_W },
5110 { .name = "TLBIIPAS2IS",
5111 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
5112 .type = ARM_CP_NOP, .access = PL2_W },
5113 { .name = "TLBIIPAS2L",
5114 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
5115 .type = ARM_CP_NOP, .access = PL2_W },
5116 { .name = "TLBIIPAS2LIS",
5117 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
5118 .type = ARM_CP_NOP, .access = PL2_W },
5119 /* 32 bit cache operations */
5120 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
5121 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5122 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
5123 .type = ARM_CP_NOP, .access = PL1_W },
5124 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
5125 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5126 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
5127 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5128 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
5129 .type = ARM_CP_NOP, .access = PL1_W },
5130 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
5131 .type = ARM_CP_NOP, .access = PL1_W },
5132 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
5133 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
5134 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
5135 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
5136 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
5137 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
5138 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
5139 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
5140 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
5141 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5142 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
5143 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
5144 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
5145 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
5146 /* MMU Domain access control / MPU write buffer control */
5147 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
5148 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
5149 .writefn = dacr_write, .raw_writefn = raw_write,
5150 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
5151 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
5152 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
5153 .type = ARM_CP_ALIAS,
5154 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
5155 .access = PL1_RW,
5156 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
5157 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
5158 .type = ARM_CP_ALIAS,
5159 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
5160 .access = PL1_RW,
5161 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
5162 /* We rely on the access checks not allowing the guest to write to the
5163 * state field when SPSel indicates that it's being used as the stack
5164 * pointer.
5166 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
5167 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
5168 .access = PL1_RW, .accessfn = sp_el0_access,
5169 .type = ARM_CP_ALIAS,
5170 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
5171 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
5172 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
5173 .access = PL2_RW, .type = ARM_CP_ALIAS,
5174 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
5175 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
5176 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
5177 .type = ARM_CP_NO_RAW,
5178 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
5179 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
5180 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
5181 .type = ARM_CP_ALIAS,
5182 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
5183 .access = PL2_RW, .accessfn = fpexc32_access },
5184 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
5185 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
5186 .access = PL2_RW, .resetvalue = 0,
5187 .writefn = dacr_write, .raw_writefn = raw_write,
5188 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
5189 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
5190 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
5191 .access = PL2_RW, .resetvalue = 0,
5192 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
5193 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
5194 .type = ARM_CP_ALIAS,
5195 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
5196 .access = PL2_RW,
5197 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
5198 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
5199 .type = ARM_CP_ALIAS,
5200 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
5201 .access = PL2_RW,
5202 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
5203 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
5204 .type = ARM_CP_ALIAS,
5205 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
5206 .access = PL2_RW,
5207 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
5208 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
5209 .type = ARM_CP_ALIAS,
5210 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
5211 .access = PL2_RW,
5212 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
5213 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
5214 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
5215 .resetvalue = 0,
5216 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
5217 { .name = "SDCR", .type = ARM_CP_ALIAS,
5218 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
5219 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5220 .writefn = sdcr_write,
5221 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
5222 REGINFO_SENTINEL
5225 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
5226 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
5227 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
5228 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5229 .access = PL2_RW,
5230 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
5231 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5232 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5233 .access = PL2_RW,
5234 .type = ARM_CP_CONST, .resetvalue = 0 },
5235 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5236 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5237 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5238 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5239 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5240 .access = PL2_RW,
5241 .type = ARM_CP_CONST, .resetvalue = 0 },
5242 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5243 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5244 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5245 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5246 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5247 .access = PL2_RW, .type = ARM_CP_CONST,
5248 .resetvalue = 0 },
5249 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
5250 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
5251 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5252 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5253 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5254 .access = PL2_RW, .type = ARM_CP_CONST,
5255 .resetvalue = 0 },
5256 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
5257 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5258 .access = PL2_RW, .type = ARM_CP_CONST,
5259 .resetvalue = 0 },
5260 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5261 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5262 .access = PL2_RW, .type = ARM_CP_CONST,
5263 .resetvalue = 0 },
5264 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5265 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5266 .access = PL2_RW, .type = ARM_CP_CONST,
5267 .resetvalue = 0 },
5268 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5269 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5270 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5271 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
5272 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5273 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5274 .type = ARM_CP_CONST, .resetvalue = 0 },
5275 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5276 .cp = 15, .opc1 = 6, .crm = 2,
5277 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5278 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
5279 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5280 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5281 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5282 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5283 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5284 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5285 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5286 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5287 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5288 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5289 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5290 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5291 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5292 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5293 .resetvalue = 0 },
5294 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5295 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5296 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5297 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5298 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5299 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5300 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5301 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5302 .resetvalue = 0 },
5303 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5304 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5305 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5306 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5307 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5308 .resetvalue = 0 },
5309 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5310 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5311 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5312 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5313 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5314 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5315 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5316 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5317 .access = PL2_RW, .accessfn = access_tda,
5318 .type = ARM_CP_CONST, .resetvalue = 0 },
5319 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
5320 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5321 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5322 .type = ARM_CP_CONST, .resetvalue = 0 },
5323 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5324 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5325 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5326 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5327 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5328 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5329 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5330 .type = ARM_CP_CONST,
5331 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5332 .access = PL2_RW, .resetvalue = 0 },
5333 REGINFO_SENTINEL
5336 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5337 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
5338 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5339 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5340 .access = PL2_RW,
5341 .type = ARM_CP_CONST, .resetvalue = 0 },
5342 REGINFO_SENTINEL
5345 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
5347 ARMCPU *cpu = env_archcpu(env);
5349 if (arm_feature(env, ARM_FEATURE_V8)) {
5350 valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5351 } else {
5352 valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5355 if (arm_feature(env, ARM_FEATURE_EL3)) {
5356 valid_mask &= ~HCR_HCD;
5357 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
5358 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5359 * However, if we're using the SMC PSCI conduit then QEMU is
5360 * effectively acting like EL3 firmware and so the guest at
5361 * EL2 should retain the ability to prevent EL1 from being
5362 * able to make SMC calls into the ersatz firmware, so in
5363 * that case HCR.TSC should be read/write.
5365 valid_mask &= ~HCR_TSC;
5368 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5369 if (cpu_isar_feature(aa64_vh, cpu)) {
5370 valid_mask |= HCR_E2H;
5372 if (cpu_isar_feature(aa64_lor, cpu)) {
5373 valid_mask |= HCR_TLOR;
5375 if (cpu_isar_feature(aa64_pauth, cpu)) {
5376 valid_mask |= HCR_API | HCR_APK;
5378 if (cpu_isar_feature(aa64_mte, cpu)) {
5379 valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
5383 /* Clear RES0 bits. */
5384 value &= valid_mask;
5387 * These bits change the MMU setup:
5388 * HCR_VM enables stage 2 translation
5389 * HCR_PTW forbids certain page-table setups
5390 * HCR_DC disables stage1 and enables stage2 translation
5391 * HCR_DCT enables tagging on (disabled) stage1 translation
5393 if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) {
5394 tlb_flush(CPU(cpu));
5396 env->cp15.hcr_el2 = value;
5399 * Updates to VI and VF require us to update the status of
5400 * virtual interrupts, which are the logical OR of these bits
5401 * and the state of the input lines from the GIC. (This requires
5402 * that we have the iothread lock, which is done by marking the
5403 * reginfo structs as ARM_CP_IO.)
5404 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5405 * possible for it to be taken immediately, because VIRQ and
5406 * VFIQ are masked unless running at EL0 or EL1, and HCR
5407 * can only be written at EL2.
5409 g_assert(qemu_mutex_iothread_locked());
5410 arm_cpu_update_virq(cpu);
5411 arm_cpu_update_vfiq(cpu);
5414 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
5416 do_hcr_write(env, value, 0);
5419 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
5420 uint64_t value)
5422 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5423 value = deposit64(env->cp15.hcr_el2, 32, 32, value);
5424 do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32));
5427 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
5428 uint64_t value)
5430 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5431 value = deposit64(env->cp15.hcr_el2, 0, 32, value);
5432 do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32));
5436 * Return the effective value of HCR_EL2.
5437 * Bits that are not included here:
5438 * RW (read from SCR_EL3.RW as needed)
5440 uint64_t arm_hcr_el2_eff(CPUARMState *env)
5442 uint64_t ret = env->cp15.hcr_el2;
5444 if (!arm_is_el2_enabled(env)) {
5446 * "This register has no effect if EL2 is not enabled in the
5447 * current Security state". This is ARMv8.4-SecEL2 speak for
5448 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5450 * Prior to that, the language was "In an implementation that
5451 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5452 * as if this field is 0 for all purposes other than a direct
5453 * read or write access of HCR_EL2". With lots of enumeration
5454 * on a per-field basis. In current QEMU, this is condition
5455 * is arm_is_secure_below_el3.
5457 * Since the v8.4 language applies to the entire register, and
5458 * appears to be backward compatible, use that.
5460 return 0;
5464 * For a cpu that supports both aarch64 and aarch32, we can set bits
5465 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5466 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5468 if (!arm_el_is_aa64(env, 2)) {
5469 uint64_t aa32_valid;
5472 * These bits are up-to-date as of ARMv8.6.
5473 * For HCR, it's easiest to list just the 2 bits that are invalid.
5474 * For HCR2, list those that are valid.
5476 aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
5477 aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
5478 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
5479 ret &= aa32_valid;
5482 if (ret & HCR_TGE) {
5483 /* These bits are up-to-date as of ARMv8.6. */
5484 if (ret & HCR_E2H) {
5485 ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
5486 HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
5487 HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
5488 HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
5489 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
5490 HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
5491 } else {
5492 ret |= HCR_FMO | HCR_IMO | HCR_AMO;
5494 ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
5495 HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
5496 HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
5497 HCR_TLOR);
5500 return ret;
5503 static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
5504 uint64_t value)
5507 * For A-profile AArch32 EL3, if NSACR.CP10
5508 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5510 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5511 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5512 value &= ~(0x3 << 10);
5513 value |= env->cp15.cptr_el[2] & (0x3 << 10);
5515 env->cp15.cptr_el[2] = value;
5518 static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
5521 * For A-profile AArch32 EL3, if NSACR.CP10
5522 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5524 uint64_t value = env->cp15.cptr_el[2];
5526 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5527 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5528 value |= 0x3 << 10;
5530 return value;
5533 static const ARMCPRegInfo el2_cp_reginfo[] = {
5534 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
5535 .type = ARM_CP_IO,
5536 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5537 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
5538 .writefn = hcr_write },
5539 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5540 .type = ARM_CP_ALIAS | ARM_CP_IO,
5541 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5542 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
5543 .writefn = hcr_writelow },
5544 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5545 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5546 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5547 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
5548 .type = ARM_CP_ALIAS,
5549 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
5550 .access = PL2_RW,
5551 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
5552 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5553 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5554 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
5555 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5556 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5557 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
5558 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5559 .type = ARM_CP_ALIAS,
5560 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5561 .access = PL2_RW,
5562 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) },
5563 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
5564 .type = ARM_CP_ALIAS,
5565 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
5566 .access = PL2_RW,
5567 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
5568 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
5569 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5570 .access = PL2_RW, .writefn = vbar_write,
5571 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
5572 .resetvalue = 0 },
5573 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
5574 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
5575 .access = PL3_RW, .type = ARM_CP_ALIAS,
5576 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
5577 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5578 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5579 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
5580 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]),
5581 .readfn = cptr_el2_read, .writefn = cptr_el2_write },
5582 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5583 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5584 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
5585 .resetvalue = 0 },
5586 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
5587 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
5588 .access = PL2_RW, .type = ARM_CP_ALIAS,
5589 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
5590 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5591 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5592 .access = PL2_RW, .type = ARM_CP_CONST,
5593 .resetvalue = 0 },
5594 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5595 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
5596 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5597 .access = PL2_RW, .type = ARM_CP_CONST,
5598 .resetvalue = 0 },
5599 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5600 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5601 .access = PL2_RW, .type = ARM_CP_CONST,
5602 .resetvalue = 0 },
5603 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5604 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5605 .access = PL2_RW, .type = ARM_CP_CONST,
5606 .resetvalue = 0 },
5607 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5608 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5609 .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
5610 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5611 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
5612 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5613 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5614 .type = ARM_CP_ALIAS,
5615 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5616 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5617 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
5618 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5619 .access = PL2_RW,
5620 /* no .writefn needed as this can't cause an ASID change;
5621 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5623 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5624 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5625 .cp = 15, .opc1 = 6, .crm = 2,
5626 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5627 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5628 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
5629 .writefn = vttbr_write },
5630 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5631 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5632 .access = PL2_RW, .writefn = vttbr_write,
5633 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
5634 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5635 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5636 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
5637 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
5638 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5639 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5640 .access = PL2_RW, .resetvalue = 0,
5641 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
5642 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5643 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5644 .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
5645 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5646 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5647 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5648 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5649 { .name = "TLBIALLNSNH",
5650 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
5651 .type = ARM_CP_NO_RAW, .access = PL2_W,
5652 .writefn = tlbiall_nsnh_write },
5653 { .name = "TLBIALLNSNHIS",
5654 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
5655 .type = ARM_CP_NO_RAW, .access = PL2_W,
5656 .writefn = tlbiall_nsnh_is_write },
5657 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5658 .type = ARM_CP_NO_RAW, .access = PL2_W,
5659 .writefn = tlbiall_hyp_write },
5660 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5661 .type = ARM_CP_NO_RAW, .access = PL2_W,
5662 .writefn = tlbiall_hyp_is_write },
5663 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5664 .type = ARM_CP_NO_RAW, .access = PL2_W,
5665 .writefn = tlbimva_hyp_write },
5666 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5667 .type = ARM_CP_NO_RAW, .access = PL2_W,
5668 .writefn = tlbimva_hyp_is_write },
5669 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
5670 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5671 .type = ARM_CP_NO_RAW, .access = PL2_W,
5672 .writefn = tlbi_aa64_alle2_write },
5673 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
5674 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5675 .type = ARM_CP_NO_RAW, .access = PL2_W,
5676 .writefn = tlbi_aa64_vae2_write },
5677 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
5678 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5679 .access = PL2_W, .type = ARM_CP_NO_RAW,
5680 .writefn = tlbi_aa64_vae2_write },
5681 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
5682 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5683 .access = PL2_W, .type = ARM_CP_NO_RAW,
5684 .writefn = tlbi_aa64_alle2is_write },
5685 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
5686 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5687 .type = ARM_CP_NO_RAW, .access = PL2_W,
5688 .writefn = tlbi_aa64_vae2is_write },
5689 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
5690 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5691 .access = PL2_W, .type = ARM_CP_NO_RAW,
5692 .writefn = tlbi_aa64_vae2is_write },
5693 #ifndef CONFIG_USER_ONLY
5694 /* Unlike the other EL2-related AT operations, these must
5695 * UNDEF from EL3 if EL2 is not implemented, which is why we
5696 * define them here rather than with the rest of the AT ops.
5698 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
5699 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5700 .access = PL2_W, .accessfn = at_s1e2_access,
5701 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
5702 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
5703 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5704 .access = PL2_W, .accessfn = at_s1e2_access,
5705 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
5706 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5707 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5708 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5709 * to behave as if SCR.NS was 1.
5711 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5712 .access = PL2_W,
5713 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
5714 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5715 .access = PL2_W,
5716 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
5717 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5718 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5719 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5720 * reset values as IMPDEF. We choose to reset to 3 to comply with
5721 * both ARMv7 and ARMv8.
5723 .access = PL2_RW, .resetvalue = 3,
5724 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
5725 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5726 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5727 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
5728 .writefn = gt_cntvoff_write,
5729 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5730 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5731 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
5732 .writefn = gt_cntvoff_write,
5733 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5734 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5735 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5736 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5737 .type = ARM_CP_IO, .access = PL2_RW,
5738 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5739 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5740 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5741 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
5742 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5743 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5744 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5745 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
5746 .resetfn = gt_hyp_timer_reset,
5747 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
5748 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5749 .type = ARM_CP_IO,
5750 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5751 .access = PL2_RW,
5752 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
5753 .resetvalue = 0,
5754 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
5755 #endif
5756 /* The only field of MDCR_EL2 that has a defined architectural reset value
5757 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
5759 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5760 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5761 .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
5762 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
5763 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
5764 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5765 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5766 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5767 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
5768 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5769 .access = PL2_RW,
5770 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5771 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5772 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5773 .access = PL2_RW,
5774 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
5775 REGINFO_SENTINEL
5778 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
5779 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5780 .type = ARM_CP_ALIAS | ARM_CP_IO,
5781 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5782 .access = PL2_RW,
5783 .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
5784 .writefn = hcr_writehigh },
5785 REGINFO_SENTINEL
5788 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
5789 bool isread)
5791 if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) {
5792 return CP_ACCESS_OK;
5794 return CP_ACCESS_TRAP_UNCATEGORIZED;
5797 static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
5798 { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64,
5799 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0,
5800 .access = PL2_RW, .accessfn = sel2_access,
5801 .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) },
5802 { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64,
5803 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
5804 .access = PL2_RW, .accessfn = sel2_access,
5805 .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
5806 REGINFO_SENTINEL
5809 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
5810 bool isread)
5812 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5813 * At Secure EL1 it traps to EL3 or EL2.
5815 if (arm_current_el(env) == 3) {
5816 return CP_ACCESS_OK;
5818 if (arm_is_secure_below_el3(env)) {
5819 if (env->cp15.scr_el3 & SCR_EEL2) {
5820 return CP_ACCESS_TRAP_EL2;
5822 return CP_ACCESS_TRAP_EL3;
5824 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5825 if (isread) {
5826 return CP_ACCESS_OK;
5828 return CP_ACCESS_TRAP_UNCATEGORIZED;
5831 static const ARMCPRegInfo el3_cp_reginfo[] = {
5832 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
5833 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
5834 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
5835 .resetfn = scr_reset, .writefn = scr_write },
5836 { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
5837 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
5838 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5839 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
5840 .writefn = scr_write },
5841 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
5842 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
5843 .access = PL3_RW, .resetvalue = 0,
5844 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
5845 { .name = "SDER",
5846 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
5847 .access = PL3_RW, .resetvalue = 0,
5848 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
5849 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
5850 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5851 .writefn = vbar_write, .resetvalue = 0,
5852 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
5853 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
5854 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
5855 .access = PL3_RW, .resetvalue = 0,
5856 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
5857 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
5858 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
5859 .access = PL3_RW,
5860 /* no .writefn needed as this can't cause an ASID change;
5861 * we must provide a .raw_writefn and .resetfn because we handle
5862 * reset and migration for the AArch32 TTBCR(S), which might be
5863 * using mask and base_mask.
5865 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
5866 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
5867 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
5868 .type = ARM_CP_ALIAS,
5869 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
5870 .access = PL3_RW,
5871 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
5872 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
5873 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
5874 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
5875 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
5876 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
5877 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
5878 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
5879 .type = ARM_CP_ALIAS,
5880 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
5881 .access = PL3_RW,
5882 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
5883 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
5884 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
5885 .access = PL3_RW, .writefn = vbar_write,
5886 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
5887 .resetvalue = 0 },
5888 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
5889 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
5890 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
5891 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
5892 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
5893 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
5894 .access = PL3_RW, .resetvalue = 0,
5895 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
5896 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
5897 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
5898 .access = PL3_RW, .type = ARM_CP_CONST,
5899 .resetvalue = 0 },
5900 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
5901 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
5902 .access = PL3_RW, .type = ARM_CP_CONST,
5903 .resetvalue = 0 },
5904 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
5905 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
5906 .access = PL3_RW, .type = ARM_CP_CONST,
5907 .resetvalue = 0 },
5908 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
5909 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
5910 .access = PL3_W, .type = ARM_CP_NO_RAW,
5911 .writefn = tlbi_aa64_alle3is_write },
5912 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
5913 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
5914 .access = PL3_W, .type = ARM_CP_NO_RAW,
5915 .writefn = tlbi_aa64_vae3is_write },
5916 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
5917 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
5918 .access = PL3_W, .type = ARM_CP_NO_RAW,
5919 .writefn = tlbi_aa64_vae3is_write },
5920 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
5921 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
5922 .access = PL3_W, .type = ARM_CP_NO_RAW,
5923 .writefn = tlbi_aa64_alle3_write },
5924 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
5925 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
5926 .access = PL3_W, .type = ARM_CP_NO_RAW,
5927 .writefn = tlbi_aa64_vae3_write },
5928 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
5929 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
5930 .access = PL3_W, .type = ARM_CP_NO_RAW,
5931 .writefn = tlbi_aa64_vae3_write },
5932 REGINFO_SENTINEL
5935 #ifndef CONFIG_USER_ONLY
5936 /* Test if system register redirection is to occur in the current state. */
5937 static bool redirect_for_e2h(CPUARMState *env)
5939 return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H);
5942 static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
5944 CPReadFn *readfn;
5946 if (redirect_for_e2h(env)) {
5947 /* Switch to the saved EL2 version of the register. */
5948 ri = ri->opaque;
5949 readfn = ri->readfn;
5950 } else {
5951 readfn = ri->orig_readfn;
5953 if (readfn == NULL) {
5954 readfn = raw_read;
5956 return readfn(env, ri);
5959 static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
5960 uint64_t value)
5962 CPWriteFn *writefn;
5964 if (redirect_for_e2h(env)) {
5965 /* Switch to the saved EL2 version of the register. */
5966 ri = ri->opaque;
5967 writefn = ri->writefn;
5968 } else {
5969 writefn = ri->orig_writefn;
5971 if (writefn == NULL) {
5972 writefn = raw_write;
5974 writefn(env, ri, value);
5977 static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
5979 struct E2HAlias {
5980 uint32_t src_key, dst_key, new_key;
5981 const char *src_name, *dst_name, *new_name;
5982 bool (*feature)(const ARMISARegisters *id);
5985 #define K(op0, op1, crn, crm, op2) \
5986 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5988 static const struct E2HAlias aliases[] = {
5989 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5990 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5991 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5992 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5993 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5994 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5995 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5996 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5997 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5998 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5999 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6000 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6001 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6002 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6003 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6004 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6005 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6006 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6007 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6008 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6009 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6010 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6011 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6012 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6013 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6014 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6015 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6016 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6017 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6018 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6019 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6020 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6023 * Note that redirection of ZCR is mentioned in the description
6024 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6025 * not in the summary table.
6027 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6028 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
6030 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6031 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
6033 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6034 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6036 #undef K
6038 size_t i;
6040 for (i = 0; i < ARRAY_SIZE(aliases); i++) {
6041 const struct E2HAlias *a = &aliases[i];
6042 ARMCPRegInfo *src_reg, *dst_reg;
6044 if (a->feature && !a->feature(&cpu->isar)) {
6045 continue;
6048 src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
6049 dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
6050 g_assert(src_reg != NULL);
6051 g_assert(dst_reg != NULL);
6053 /* Cross-compare names to detect typos in the keys. */
6054 g_assert(strcmp(src_reg->name, a->src_name) == 0);
6055 g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
6057 /* None of the core system registers use opaque; we will. */
6058 g_assert(src_reg->opaque == NULL);
6060 /* Create alias before redirection so we dup the right data. */
6061 if (a->new_key) {
6062 ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
6063 uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
6064 bool ok;
6066 new_reg->name = a->new_name;
6067 new_reg->type |= ARM_CP_ALIAS;
6068 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6069 new_reg->access &= PL2_RW | PL3_RW;
6071 ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
6072 g_assert(ok);
6075 src_reg->opaque = dst_reg;
6076 src_reg->orig_readfn = src_reg->readfn ?: raw_read;
6077 src_reg->orig_writefn = src_reg->writefn ?: raw_write;
6078 if (!src_reg->raw_readfn) {
6079 src_reg->raw_readfn = raw_read;
6081 if (!src_reg->raw_writefn) {
6082 src_reg->raw_writefn = raw_write;
6084 src_reg->readfn = el2_e2h_read;
6085 src_reg->writefn = el2_e2h_write;
6088 #endif
6090 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
6091 bool isread)
6093 int cur_el = arm_current_el(env);
6095 if (cur_el < 2) {
6096 uint64_t hcr = arm_hcr_el2_eff(env);
6098 if (cur_el == 0) {
6099 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
6100 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
6101 return CP_ACCESS_TRAP_EL2;
6103 } else {
6104 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
6105 return CP_ACCESS_TRAP;
6107 if (hcr & HCR_TID2) {
6108 return CP_ACCESS_TRAP_EL2;
6111 } else if (hcr & HCR_TID2) {
6112 return CP_ACCESS_TRAP_EL2;
6116 if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
6117 return CP_ACCESS_TRAP_EL2;
6120 return CP_ACCESS_OK;
6123 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
6124 uint64_t value)
6126 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
6127 * read via a bit in OSLSR_EL1.
6129 int oslock;
6131 if (ri->state == ARM_CP_STATE_AA32) {
6132 oslock = (value == 0xC5ACCE55);
6133 } else {
6134 oslock = value & 1;
6137 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
6140 static const ARMCPRegInfo debug_cp_reginfo[] = {
6141 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
6142 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
6143 * unlike DBGDRAR it is never accessible from EL0.
6144 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6145 * accessor.
6147 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
6148 .access = PL0_R, .accessfn = access_tdra,
6149 .type = ARM_CP_CONST, .resetvalue = 0 },
6150 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
6151 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
6152 .access = PL1_R, .accessfn = access_tdra,
6153 .type = ARM_CP_CONST, .resetvalue = 0 },
6154 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
6155 .access = PL0_R, .accessfn = access_tdra,
6156 .type = ARM_CP_CONST, .resetvalue = 0 },
6157 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6158 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
6159 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
6160 .access = PL1_RW, .accessfn = access_tda,
6161 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
6162 .resetvalue = 0 },
6163 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
6164 * We don't implement the configurable EL0 access.
6166 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
6167 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
6168 .type = ARM_CP_ALIAS,
6169 .access = PL1_R, .accessfn = access_tda,
6170 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
6171 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
6172 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
6173 .access = PL1_W, .type = ARM_CP_NO_RAW,
6174 .accessfn = access_tdosa,
6175 .writefn = oslar_write },
6176 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
6177 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
6178 .access = PL1_R, .resetvalue = 10,
6179 .accessfn = access_tdosa,
6180 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
6181 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6182 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
6183 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
6184 .access = PL1_RW, .accessfn = access_tdosa,
6185 .type = ARM_CP_NOP },
6186 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6187 * implement vector catch debug events yet.
6189 { .name = "DBGVCR",
6190 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
6191 .access = PL1_RW, .accessfn = access_tda,
6192 .type = ARM_CP_NOP },
6193 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6194 * to save and restore a 32-bit guest's DBGVCR)
6196 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
6197 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
6198 .access = PL2_RW, .accessfn = access_tda,
6199 .type = ARM_CP_NOP },
6200 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6201 * Channel but Linux may try to access this register. The 32-bit
6202 * alias is DBGDCCINT.
6204 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
6205 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
6206 .access = PL1_RW, .accessfn = access_tda,
6207 .type = ARM_CP_NOP },
6208 REGINFO_SENTINEL
6211 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
6212 /* 64 bit access versions of the (dummy) debug registers */
6213 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
6214 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
6215 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
6216 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
6217 REGINFO_SENTINEL
6220 /* Return the exception level to which exceptions should be taken
6221 * via SVEAccessTrap. If an exception should be routed through
6222 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6223 * take care of raising that exception.
6224 * C.f. the ARM pseudocode function CheckSVEEnabled.
6226 int sve_exception_el(CPUARMState *env, int el)
6228 #ifndef CONFIG_USER_ONLY
6229 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
6231 if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
6232 bool disabled = false;
6234 /* The CPACR.ZEN controls traps to EL1:
6235 * 0, 2 : trap EL0 and EL1 accesses
6236 * 1 : trap only EL0 accesses
6237 * 3 : trap no accesses
6239 if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
6240 disabled = true;
6241 } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
6242 disabled = el == 0;
6244 if (disabled) {
6245 /* route_to_el2 */
6246 return hcr_el2 & HCR_TGE ? 2 : 1;
6249 /* Check CPACR.FPEN. */
6250 if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
6251 disabled = true;
6252 } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
6253 disabled = el == 0;
6255 if (disabled) {
6256 return 0;
6260 /* CPTR_EL2. Since TZ and TFP are positive,
6261 * they will be zero when EL2 is not present.
6263 if (el <= 2 && arm_is_el2_enabled(env)) {
6264 if (env->cp15.cptr_el[2] & CPTR_TZ) {
6265 return 2;
6267 if (env->cp15.cptr_el[2] & CPTR_TFP) {
6268 return 0;
6272 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6273 if (arm_feature(env, ARM_FEATURE_EL3)
6274 && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
6275 return 3;
6277 #endif
6278 return 0;
6281 static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
6283 uint32_t end_len;
6285 end_len = start_len &= 0xf;
6286 if (!test_bit(start_len, cpu->sve_vq_map)) {
6287 end_len = find_last_bit(cpu->sve_vq_map, start_len);
6288 assert(end_len < start_len);
6290 return end_len;
6294 * Given that SVE is enabled, return the vector length for EL.
6296 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
6298 ARMCPU *cpu = env_archcpu(env);
6299 uint32_t zcr_len = cpu->sve_max_vq - 1;
6301 if (el <= 1) {
6302 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
6304 if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
6305 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
6307 if (arm_feature(env, ARM_FEATURE_EL3)) {
6308 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
6311 return sve_zcr_get_valid_len(cpu, zcr_len);
6314 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6315 uint64_t value)
6317 int cur_el = arm_current_el(env);
6318 int old_len = sve_zcr_len_for_el(env, cur_el);
6319 int new_len;
6321 /* Bits other than [3:0] are RAZ/WI. */
6322 QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
6323 raw_write(env, ri, value & 0xf);
6326 * Because we arrived here, we know both FP and SVE are enabled;
6327 * otherwise we would have trapped access to the ZCR_ELn register.
6329 new_len = sve_zcr_len_for_el(env, cur_el);
6330 if (new_len < old_len) {
6331 aarch64_sve_narrow_vq(env, new_len + 1);
6335 static const ARMCPRegInfo zcr_el1_reginfo = {
6336 .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
6337 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
6338 .access = PL1_RW, .type = ARM_CP_SVE,
6339 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
6340 .writefn = zcr_write, .raw_writefn = raw_write
6343 static const ARMCPRegInfo zcr_el2_reginfo = {
6344 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6345 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6346 .access = PL2_RW, .type = ARM_CP_SVE,
6347 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
6348 .writefn = zcr_write, .raw_writefn = raw_write
6351 static const ARMCPRegInfo zcr_no_el2_reginfo = {
6352 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6353 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6354 .access = PL2_RW, .type = ARM_CP_SVE,
6355 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
6358 static const ARMCPRegInfo zcr_el3_reginfo = {
6359 .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
6360 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
6361 .access = PL3_RW, .type = ARM_CP_SVE,
6362 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
6363 .writefn = zcr_write, .raw_writefn = raw_write
6366 void hw_watchpoint_update(ARMCPU *cpu, int n)
6368 CPUARMState *env = &cpu->env;
6369 vaddr len = 0;
6370 vaddr wvr = env->cp15.dbgwvr[n];
6371 uint64_t wcr = env->cp15.dbgwcr[n];
6372 int mask;
6373 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
6375 if (env->cpu_watchpoint[n]) {
6376 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
6377 env->cpu_watchpoint[n] = NULL;
6380 if (!extract64(wcr, 0, 1)) {
6381 /* E bit clear : watchpoint disabled */
6382 return;
6385 switch (extract64(wcr, 3, 2)) {
6386 case 0:
6387 /* LSC 00 is reserved and must behave as if the wp is disabled */
6388 return;
6389 case 1:
6390 flags |= BP_MEM_READ;
6391 break;
6392 case 2:
6393 flags |= BP_MEM_WRITE;
6394 break;
6395 case 3:
6396 flags |= BP_MEM_ACCESS;
6397 break;
6400 /* Attempts to use both MASK and BAS fields simultaneously are
6401 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6402 * thus generating a watchpoint for every byte in the masked region.
6404 mask = extract64(wcr, 24, 4);
6405 if (mask == 1 || mask == 2) {
6406 /* Reserved values of MASK; we must act as if the mask value was
6407 * some non-reserved value, or as if the watchpoint were disabled.
6408 * We choose the latter.
6410 return;
6411 } else if (mask) {
6412 /* Watchpoint covers an aligned area up to 2GB in size */
6413 len = 1ULL << mask;
6414 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6415 * whether the watchpoint fires when the unmasked bits match; we opt
6416 * to generate the exceptions.
6418 wvr &= ~(len - 1);
6419 } else {
6420 /* Watchpoint covers bytes defined by the byte address select bits */
6421 int bas = extract64(wcr, 5, 8);
6422 int basstart;
6424 if (extract64(wvr, 2, 1)) {
6425 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6426 * ignored, and BAS[3:0] define which bytes to watch.
6428 bas &= 0xf;
6431 if (bas == 0) {
6432 /* This must act as if the watchpoint is disabled */
6433 return;
6436 /* The BAS bits are supposed to be programmed to indicate a contiguous
6437 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6438 * we fire for each byte in the word/doubleword addressed by the WVR.
6439 * We choose to ignore any non-zero bits after the first range of 1s.
6441 basstart = ctz32(bas);
6442 len = cto32(bas >> basstart);
6443 wvr += basstart;
6446 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
6447 &env->cpu_watchpoint[n]);
6450 void hw_watchpoint_update_all(ARMCPU *cpu)
6452 int i;
6453 CPUARMState *env = &cpu->env;
6455 /* Completely clear out existing QEMU watchpoints and our array, to
6456 * avoid possible stale entries following migration load.
6458 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
6459 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
6461 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
6462 hw_watchpoint_update(cpu, i);
6466 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6467 uint64_t value)
6469 ARMCPU *cpu = env_archcpu(env);
6470 int i = ri->crm;
6472 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6473 * register reads and behaves as if values written are sign extended.
6474 * Bits [1:0] are RES0.
6476 value = sextract64(value, 0, 49) & ~3ULL;
6478 raw_write(env, ri, value);
6479 hw_watchpoint_update(cpu, i);
6482 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6483 uint64_t value)
6485 ARMCPU *cpu = env_archcpu(env);
6486 int i = ri->crm;
6488 raw_write(env, ri, value);
6489 hw_watchpoint_update(cpu, i);
6492 void hw_breakpoint_update(ARMCPU *cpu, int n)
6494 CPUARMState *env = &cpu->env;
6495 uint64_t bvr = env->cp15.dbgbvr[n];
6496 uint64_t bcr = env->cp15.dbgbcr[n];
6497 vaddr addr;
6498 int bt;
6499 int flags = BP_CPU;
6501 if (env->cpu_breakpoint[n]) {
6502 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
6503 env->cpu_breakpoint[n] = NULL;
6506 if (!extract64(bcr, 0, 1)) {
6507 /* E bit clear : watchpoint disabled */
6508 return;
6511 bt = extract64(bcr, 20, 4);
6513 switch (bt) {
6514 case 4: /* unlinked address mismatch (reserved if AArch64) */
6515 case 5: /* linked address mismatch (reserved if AArch64) */
6516 qemu_log_mask(LOG_UNIMP,
6517 "arm: address mismatch breakpoint types not implemented\n");
6518 return;
6519 case 0: /* unlinked address match */
6520 case 1: /* linked address match */
6522 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6523 * we behave as if the register was sign extended. Bits [1:0] are
6524 * RES0. The BAS field is used to allow setting breakpoints on 16
6525 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6526 * a bp will fire if the addresses covered by the bp and the addresses
6527 * covered by the insn overlap but the insn doesn't start at the
6528 * start of the bp address range. We choose to require the insn and
6529 * the bp to have the same address. The constraints on writing to
6530 * BAS enforced in dbgbcr_write mean we have only four cases:
6531 * 0b0000 => no breakpoint
6532 * 0b0011 => breakpoint on addr
6533 * 0b1100 => breakpoint on addr + 2
6534 * 0b1111 => breakpoint on addr
6535 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6537 int bas = extract64(bcr, 5, 4);
6538 addr = sextract64(bvr, 0, 49) & ~3ULL;
6539 if (bas == 0) {
6540 return;
6542 if (bas == 0xc) {
6543 addr += 2;
6545 break;
6547 case 2: /* unlinked context ID match */
6548 case 8: /* unlinked VMID match (reserved if no EL2) */
6549 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6550 qemu_log_mask(LOG_UNIMP,
6551 "arm: unlinked context breakpoint types not implemented\n");
6552 return;
6553 case 9: /* linked VMID match (reserved if no EL2) */
6554 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6555 case 3: /* linked context ID match */
6556 default:
6557 /* We must generate no events for Linked context matches (unless
6558 * they are linked to by some other bp/wp, which is handled in
6559 * updates for the linking bp/wp). We choose to also generate no events
6560 * for reserved values.
6562 return;
6565 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
6568 void hw_breakpoint_update_all(ARMCPU *cpu)
6570 int i;
6571 CPUARMState *env = &cpu->env;
6573 /* Completely clear out existing QEMU breakpoints and our array, to
6574 * avoid possible stale entries following migration load.
6576 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
6577 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
6579 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
6580 hw_breakpoint_update(cpu, i);
6584 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6585 uint64_t value)
6587 ARMCPU *cpu = env_archcpu(env);
6588 int i = ri->crm;
6590 raw_write(env, ri, value);
6591 hw_breakpoint_update(cpu, i);
6594 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6595 uint64_t value)
6597 ARMCPU *cpu = env_archcpu(env);
6598 int i = ri->crm;
6600 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6601 * copy of BAS[0].
6603 value = deposit64(value, 6, 1, extract64(value, 5, 1));
6604 value = deposit64(value, 8, 1, extract64(value, 7, 1));
6606 raw_write(env, ri, value);
6607 hw_breakpoint_update(cpu, i);
6610 static void define_debug_regs(ARMCPU *cpu)
6612 /* Define v7 and v8 architectural debug registers.
6613 * These are just dummy implementations for now.
6615 int i;
6616 int wrps, brps, ctx_cmps;
6619 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
6620 * use AArch32. Given that bit 15 is RES1, if the value is 0 then
6621 * the register must not exist for this cpu.
6623 if (cpu->isar.dbgdidr != 0) {
6624 ARMCPRegInfo dbgdidr = {
6625 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
6626 .opc1 = 0, .opc2 = 0,
6627 .access = PL0_R, .accessfn = access_tda,
6628 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
6630 define_one_arm_cp_reg(cpu, &dbgdidr);
6633 /* Note that all these register fields hold "number of Xs minus 1". */
6634 brps = arm_num_brps(cpu);
6635 wrps = arm_num_wrps(cpu);
6636 ctx_cmps = arm_num_ctx_cmps(cpu);
6638 assert(ctx_cmps <= brps);
6640 define_arm_cp_regs(cpu, debug_cp_reginfo);
6642 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
6643 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
6646 for (i = 0; i < brps; i++) {
6647 ARMCPRegInfo dbgregs[] = {
6648 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
6649 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
6650 .access = PL1_RW, .accessfn = access_tda,
6651 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
6652 .writefn = dbgbvr_write, .raw_writefn = raw_write
6654 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
6655 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
6656 .access = PL1_RW, .accessfn = access_tda,
6657 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
6658 .writefn = dbgbcr_write, .raw_writefn = raw_write
6660 REGINFO_SENTINEL
6662 define_arm_cp_regs(cpu, dbgregs);
6665 for (i = 0; i < wrps; i++) {
6666 ARMCPRegInfo dbgregs[] = {
6667 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
6668 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
6669 .access = PL1_RW, .accessfn = access_tda,
6670 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
6671 .writefn = dbgwvr_write, .raw_writefn = raw_write
6673 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
6674 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
6675 .access = PL1_RW, .accessfn = access_tda,
6676 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
6677 .writefn = dbgwcr_write, .raw_writefn = raw_write
6679 REGINFO_SENTINEL
6681 define_arm_cp_regs(cpu, dbgregs);
6685 static void define_pmu_regs(ARMCPU *cpu)
6688 * v7 performance monitor control register: same implementor
6689 * field as main ID register, and we implement four counters in
6690 * addition to the cycle count register.
6692 unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
6693 ARMCPRegInfo pmcr = {
6694 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
6695 .access = PL0_RW,
6696 .type = ARM_CP_IO | ARM_CP_ALIAS,
6697 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
6698 .accessfn = pmreg_access, .writefn = pmcr_write,
6699 .raw_writefn = raw_write,
6701 ARMCPRegInfo pmcr64 = {
6702 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
6703 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
6704 .access = PL0_RW, .accessfn = pmreg_access,
6705 .type = ARM_CP_IO,
6706 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
6707 .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
6708 PMCRLC,
6709 .writefn = pmcr_write, .raw_writefn = raw_write,
6711 define_one_arm_cp_reg(cpu, &pmcr);
6712 define_one_arm_cp_reg(cpu, &pmcr64);
6713 for (i = 0; i < pmcrn; i++) {
6714 char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
6715 char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
6716 char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
6717 char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
6718 ARMCPRegInfo pmev_regs[] = {
6719 { .name = pmevcntr_name, .cp = 15, .crn = 14,
6720 .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6721 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6722 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6723 .accessfn = pmreg_access },
6724 { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
6725 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
6726 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6727 .type = ARM_CP_IO,
6728 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6729 .raw_readfn = pmevcntr_rawread,
6730 .raw_writefn = pmevcntr_rawwrite },
6731 { .name = pmevtyper_name, .cp = 15, .crn = 14,
6732 .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6733 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6734 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6735 .accessfn = pmreg_access },
6736 { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
6737 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
6738 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6739 .type = ARM_CP_IO,
6740 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6741 .raw_writefn = pmevtyper_rawwrite },
6742 REGINFO_SENTINEL
6744 define_arm_cp_regs(cpu, pmev_regs);
6745 g_free(pmevcntr_name);
6746 g_free(pmevcntr_el0_name);
6747 g_free(pmevtyper_name);
6748 g_free(pmevtyper_el0_name);
6750 if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
6751 ARMCPRegInfo v81_pmu_regs[] = {
6752 { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
6753 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
6754 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6755 .resetvalue = extract64(cpu->pmceid0, 32, 32) },
6756 { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
6757 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
6758 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6759 .resetvalue = extract64(cpu->pmceid1, 32, 32) },
6760 REGINFO_SENTINEL
6762 define_arm_cp_regs(cpu, v81_pmu_regs);
6764 if (cpu_isar_feature(any_pmu_8_4, cpu)) {
6765 static const ARMCPRegInfo v84_pmmir = {
6766 .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
6767 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
6768 .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6769 .resetvalue = 0
6771 define_one_arm_cp_reg(cpu, &v84_pmmir);
6775 /* We don't know until after realize whether there's a GICv3
6776 * attached, and that is what registers the gicv3 sysregs.
6777 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6778 * at runtime.
6780 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
6782 ARMCPU *cpu = env_archcpu(env);
6783 uint64_t pfr1 = cpu->isar.id_pfr1;
6785 if (env->gicv3state) {
6786 pfr1 |= 1 << 28;
6788 return pfr1;
6791 #ifndef CONFIG_USER_ONLY
6792 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
6794 ARMCPU *cpu = env_archcpu(env);
6795 uint64_t pfr0 = cpu->isar.id_aa64pfr0;
6797 if (env->gicv3state) {
6798 pfr0 |= 1 << 24;
6800 return pfr0;
6802 #endif
6804 /* Shared logic between LORID and the rest of the LOR* registers.
6805 * Secure state exclusion has already been dealt with.
6807 static CPAccessResult access_lor_ns(CPUARMState *env,
6808 const ARMCPRegInfo *ri, bool isread)
6810 int el = arm_current_el(env);
6812 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) {
6813 return CP_ACCESS_TRAP_EL2;
6815 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) {
6816 return CP_ACCESS_TRAP_EL3;
6818 return CP_ACCESS_OK;
6821 static CPAccessResult access_lor_other(CPUARMState *env,
6822 const ARMCPRegInfo *ri, bool isread)
6824 if (arm_is_secure_below_el3(env)) {
6825 /* Access denied in secure mode. */
6826 return CP_ACCESS_TRAP;
6828 return access_lor_ns(env, ri, isread);
6832 * A trivial implementation of ARMv8.1-LOR leaves all of these
6833 * registers fixed at 0, which indicates that there are zero
6834 * supported Limited Ordering regions.
6836 static const ARMCPRegInfo lor_reginfo[] = {
6837 { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
6838 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
6839 .access = PL1_RW, .accessfn = access_lor_other,
6840 .type = ARM_CP_CONST, .resetvalue = 0 },
6841 { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
6842 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
6843 .access = PL1_RW, .accessfn = access_lor_other,
6844 .type = ARM_CP_CONST, .resetvalue = 0 },
6845 { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
6846 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
6847 .access = PL1_RW, .accessfn = access_lor_other,
6848 .type = ARM_CP_CONST, .resetvalue = 0 },
6849 { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
6850 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
6851 .access = PL1_RW, .accessfn = access_lor_other,
6852 .type = ARM_CP_CONST, .resetvalue = 0 },
6853 { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
6854 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
6855 .access = PL1_R, .accessfn = access_lor_ns,
6856 .type = ARM_CP_CONST, .resetvalue = 0 },
6857 REGINFO_SENTINEL
6860 #ifdef TARGET_AARCH64
6861 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
6862 bool isread)
6864 int el = arm_current_el(env);
6866 if (el < 2 &&
6867 arm_feature(env, ARM_FEATURE_EL2) &&
6868 !(arm_hcr_el2_eff(env) & HCR_APK)) {
6869 return CP_ACCESS_TRAP_EL2;
6871 if (el < 3 &&
6872 arm_feature(env, ARM_FEATURE_EL3) &&
6873 !(env->cp15.scr_el3 & SCR_APK)) {
6874 return CP_ACCESS_TRAP_EL3;
6876 return CP_ACCESS_OK;
6879 static const ARMCPRegInfo pauth_reginfo[] = {
6880 { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6881 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
6882 .access = PL1_RW, .accessfn = access_pauth,
6883 .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
6884 { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6885 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
6886 .access = PL1_RW, .accessfn = access_pauth,
6887 .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
6888 { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6889 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
6890 .access = PL1_RW, .accessfn = access_pauth,
6891 .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
6892 { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6893 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
6894 .access = PL1_RW, .accessfn = access_pauth,
6895 .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
6896 { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6897 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
6898 .access = PL1_RW, .accessfn = access_pauth,
6899 .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
6900 { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6901 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
6902 .access = PL1_RW, .accessfn = access_pauth,
6903 .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
6904 { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6905 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
6906 .access = PL1_RW, .accessfn = access_pauth,
6907 .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
6908 { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6909 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
6910 .access = PL1_RW, .accessfn = access_pauth,
6911 .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
6912 { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6913 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
6914 .access = PL1_RW, .accessfn = access_pauth,
6915 .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
6916 { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6917 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
6918 .access = PL1_RW, .accessfn = access_pauth,
6919 .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
6920 REGINFO_SENTINEL
6923 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
6925 Error *err = NULL;
6926 uint64_t ret;
6928 /* Success sets NZCV = 0000. */
6929 env->NF = env->CF = env->VF = 0, env->ZF = 1;
6931 if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) {
6933 * ??? Failed, for unknown reasons in the crypto subsystem.
6934 * The best we can do is log the reason and return the
6935 * timed-out indication to the guest. There is no reason
6936 * we know to expect this failure to be transitory, so the
6937 * guest may well hang retrying the operation.
6939 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
6940 ri->name, error_get_pretty(err));
6941 error_free(err);
6943 env->ZF = 0; /* NZCF = 0100 */
6944 return 0;
6946 return ret;
6949 /* We do not support re-seeding, so the two registers operate the same. */
6950 static const ARMCPRegInfo rndr_reginfo[] = {
6951 { .name = "RNDR", .state = ARM_CP_STATE_AA64,
6952 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6953 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0,
6954 .access = PL0_R, .readfn = rndr_readfn },
6955 { .name = "RNDRRS", .state = ARM_CP_STATE_AA64,
6956 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6957 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
6958 .access = PL0_R, .readfn = rndr_readfn },
6959 REGINFO_SENTINEL
6962 #ifndef CONFIG_USER_ONLY
6963 static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
6964 uint64_t value)
6966 ARMCPU *cpu = env_archcpu(env);
6967 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6968 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF);
6969 uint64_t vaddr_in = (uint64_t) value;
6970 uint64_t vaddr = vaddr_in & ~(dline_size - 1);
6971 void *haddr;
6972 int mem_idx = cpu_mmu_index(env, false);
6974 /* This won't be crossing page boundaries */
6975 haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
6976 if (haddr) {
6978 ram_addr_t offset;
6979 MemoryRegion *mr;
6981 /* RCU lock is already being held */
6982 mr = memory_region_from_host(haddr, &offset);
6984 if (mr) {
6985 memory_region_writeback(mr, offset, dline_size);
6990 static const ARMCPRegInfo dcpop_reg[] = {
6991 { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
6992 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
6993 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
6994 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
6995 REGINFO_SENTINEL
6998 static const ARMCPRegInfo dcpodp_reg[] = {
6999 { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
7000 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
7001 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
7002 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
7003 REGINFO_SENTINEL
7005 #endif /*CONFIG_USER_ONLY*/
7007 static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
7008 bool isread)
7010 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) {
7011 return CP_ACCESS_TRAP_EL2;
7014 return CP_ACCESS_OK;
7017 static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
7018 bool isread)
7020 int el = arm_current_el(env);
7022 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
7023 uint64_t hcr = arm_hcr_el2_eff(env);
7024 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
7025 return CP_ACCESS_TRAP_EL2;
7028 if (el < 3 &&
7029 arm_feature(env, ARM_FEATURE_EL3) &&
7030 !(env->cp15.scr_el3 & SCR_ATA)) {
7031 return CP_ACCESS_TRAP_EL3;
7033 return CP_ACCESS_OK;
7036 static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
7038 return env->pstate & PSTATE_TCO;
7041 static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
7043 env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO);
7046 static const ARMCPRegInfo mte_reginfo[] = {
7047 { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64,
7048 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1,
7049 .access = PL1_RW, .accessfn = access_mte,
7050 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) },
7051 { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64,
7052 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
7053 .access = PL1_RW, .accessfn = access_mte,
7054 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
7055 { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
7056 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0,
7057 .access = PL2_RW, .accessfn = access_mte,
7058 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) },
7059 { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64,
7060 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0,
7061 .access = PL3_RW,
7062 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) },
7063 { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64,
7064 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5,
7065 .access = PL1_RW, .accessfn = access_mte,
7066 .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) },
7067 { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64,
7068 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
7069 .access = PL1_RW, .accessfn = access_mte,
7070 .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
7071 { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
7072 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
7073 .access = PL1_R, .accessfn = access_aa64_tid5,
7074 .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
7075 { .name = "TCO", .state = ARM_CP_STATE_AA64,
7076 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
7077 .type = ARM_CP_NO_RAW,
7078 .access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
7079 { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
7080 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
7081 .type = ARM_CP_NOP, .access = PL1_W,
7082 .accessfn = aa64_cacheop_poc_access },
7083 { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
7084 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
7085 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
7086 { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
7087 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
7088 .type = ARM_CP_NOP, .access = PL1_W,
7089 .accessfn = aa64_cacheop_poc_access },
7090 { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
7091 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
7092 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
7093 { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
7094 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
7095 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
7096 { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
7097 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
7098 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
7099 { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
7100 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
7101 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
7102 { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
7103 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
7104 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
7105 REGINFO_SENTINEL
7108 static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
7109 { .name = "TCO", .state = ARM_CP_STATE_AA64,
7110 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
7111 .type = ARM_CP_CONST, .access = PL0_RW, },
7112 REGINFO_SENTINEL
7115 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
7116 { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
7117 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
7118 .type = ARM_CP_NOP, .access = PL0_W,
7119 .accessfn = aa64_cacheop_poc_access },
7120 { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
7121 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
7122 .type = ARM_CP_NOP, .access = PL0_W,
7123 .accessfn = aa64_cacheop_poc_access },
7124 { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
7125 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
7126 .type = ARM_CP_NOP, .access = PL0_W,
7127 .accessfn = aa64_cacheop_poc_access },
7128 { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
7129 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
7130 .type = ARM_CP_NOP, .access = PL0_W,
7131 .accessfn = aa64_cacheop_poc_access },
7132 { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
7133 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
7134 .type = ARM_CP_NOP, .access = PL0_W,
7135 .accessfn = aa64_cacheop_poc_access },
7136 { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
7137 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
7138 .type = ARM_CP_NOP, .access = PL0_W,
7139 .accessfn = aa64_cacheop_poc_access },
7140 { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
7141 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
7142 .type = ARM_CP_NOP, .access = PL0_W,
7143 .accessfn = aa64_cacheop_poc_access },
7144 { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
7145 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
7146 .type = ARM_CP_NOP, .access = PL0_W,
7147 .accessfn = aa64_cacheop_poc_access },
7148 { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
7149 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
7150 .access = PL0_W, .type = ARM_CP_DC_GVA,
7151 #ifndef CONFIG_USER_ONLY
7152 /* Avoid overhead of an access check that always passes in user-mode */
7153 .accessfn = aa64_zva_access,
7154 #endif
7156 { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
7157 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,
7158 .access = PL0_W, .type = ARM_CP_DC_GZVA,
7159 #ifndef CONFIG_USER_ONLY
7160 /* Avoid overhead of an access check that always passes in user-mode */
7161 .accessfn = aa64_zva_access,
7162 #endif
7164 REGINFO_SENTINEL
7167 #endif
7169 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
7170 bool isread)
7172 int el = arm_current_el(env);
7174 if (el == 0) {
7175 uint64_t sctlr = arm_sctlr(env, el);
7176 if (!(sctlr & SCTLR_EnRCTX)) {
7177 return CP_ACCESS_TRAP;
7179 } else if (el == 1) {
7180 uint64_t hcr = arm_hcr_el2_eff(env);
7181 if (hcr & HCR_NV) {
7182 return CP_ACCESS_TRAP_EL2;
7185 return CP_ACCESS_OK;
7188 static const ARMCPRegInfo predinv_reginfo[] = {
7189 { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
7190 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
7191 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7192 { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
7193 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
7194 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7195 { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
7196 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
7197 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7199 * Note the AArch32 opcodes have a different OPC1.
7201 { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
7202 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
7203 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7204 { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
7205 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
7206 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7207 { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
7208 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
7209 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7210 REGINFO_SENTINEL
7213 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
7215 /* Read the high 32 bits of the current CCSIDR */
7216 return extract64(ccsidr_read(env, ri), 32, 32);
7219 static const ARMCPRegInfo ccsidr2_reginfo[] = {
7220 { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
7221 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
7222 .access = PL1_R,
7223 .accessfn = access_aa64_tid2,
7224 .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
7225 REGINFO_SENTINEL
7228 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
7229 bool isread)
7231 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
7232 return CP_ACCESS_TRAP_EL2;
7235 return CP_ACCESS_OK;
7238 static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
7239 bool isread)
7241 if (arm_feature(env, ARM_FEATURE_V8)) {
7242 return access_aa64_tid3(env, ri, isread);
7245 return CP_ACCESS_OK;
7248 static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
7249 bool isread)
7251 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) {
7252 return CP_ACCESS_TRAP_EL2;
7255 return CP_ACCESS_OK;
7258 static const ARMCPRegInfo jazelle_regs[] = {
7259 { .name = "JIDR",
7260 .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
7261 .access = PL1_R, .accessfn = access_jazelle,
7262 .type = ARM_CP_CONST, .resetvalue = 0 },
7263 { .name = "JOSCR",
7264 .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
7265 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
7266 { .name = "JMCR",
7267 .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
7268 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
7269 REGINFO_SENTINEL
7272 static const ARMCPRegInfo vhe_reginfo[] = {
7273 { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
7274 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
7275 .access = PL2_RW,
7276 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
7277 { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
7278 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
7279 .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
7280 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
7281 #ifndef CONFIG_USER_ONLY
7282 { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
7283 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2,
7284 .fieldoffset =
7285 offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval),
7286 .type = ARM_CP_IO, .access = PL2_RW,
7287 .writefn = gt_hv_cval_write, .raw_writefn = raw_write },
7288 { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
7289 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0,
7290 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
7291 .resetfn = gt_hv_timer_reset,
7292 .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write },
7293 { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH,
7294 .type = ARM_CP_IO,
7295 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1,
7296 .access = PL2_RW,
7297 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl),
7298 .writefn = gt_hv_ctl_write, .raw_writefn = raw_write },
7299 { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
7300 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
7301 .type = ARM_CP_IO | ARM_CP_ALIAS,
7302 .access = PL2_RW, .accessfn = e2h_access,
7303 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
7304 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
7305 { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
7306 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
7307 .type = ARM_CP_IO | ARM_CP_ALIAS,
7308 .access = PL2_RW, .accessfn = e2h_access,
7309 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
7310 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
7311 { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64,
7312 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0,
7313 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
7314 .access = PL2_RW, .accessfn = e2h_access,
7315 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write },
7316 { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64,
7317 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0,
7318 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
7319 .access = PL2_RW, .accessfn = e2h_access,
7320 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write },
7321 { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64,
7322 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2,
7323 .type = ARM_CP_IO | ARM_CP_ALIAS,
7324 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
7325 .access = PL2_RW, .accessfn = e2h_access,
7326 .writefn = gt_phys_cval_write, .raw_writefn = raw_write },
7327 { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
7328 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
7329 .type = ARM_CP_IO | ARM_CP_ALIAS,
7330 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
7331 .access = PL2_RW, .accessfn = e2h_access,
7332 .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
7333 #endif
7334 REGINFO_SENTINEL
7337 #ifndef CONFIG_USER_ONLY
7338 static const ARMCPRegInfo ats1e1_reginfo[] = {
7339 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
7340 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
7341 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7342 .writefn = ats_write64 },
7343 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
7344 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
7345 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7346 .writefn = ats_write64 },
7347 REGINFO_SENTINEL
7350 static const ARMCPRegInfo ats1cp_reginfo[] = {
7351 { .name = "ATS1CPRP",
7352 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
7353 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7354 .writefn = ats_write },
7355 { .name = "ATS1CPWP",
7356 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
7357 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7358 .writefn = ats_write },
7359 REGINFO_SENTINEL
7361 #endif
7364 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7365 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7366 * is non-zero, which is never for ARMv7, optionally in ARMv8
7367 * and mandatorily for ARMv8.2 and up.
7368 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7369 * implementation is RAZ/WI we can ignore this detail, as we
7370 * do for ACTLR.
7372 static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
7373 { .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
7374 .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
7375 .access = PL1_RW, .accessfn = access_tacr,
7376 .type = ARM_CP_CONST, .resetvalue = 0 },
7377 { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
7378 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
7379 .access = PL2_RW, .type = ARM_CP_CONST,
7380 .resetvalue = 0 },
7381 REGINFO_SENTINEL
7384 void register_cp_regs_for_features(ARMCPU *cpu)
7386 /* Register all the coprocessor registers based on feature bits */
7387 CPUARMState *env = &cpu->env;
7388 if (arm_feature(env, ARM_FEATURE_M)) {
7389 /* M profile has no coprocessor registers */
7390 return;
7393 define_arm_cp_regs(cpu, cp_reginfo);
7394 if (!arm_feature(env, ARM_FEATURE_V8)) {
7395 /* Must go early as it is full of wildcards that may be
7396 * overridden by later definitions.
7398 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
7401 if (arm_feature(env, ARM_FEATURE_V6)) {
7402 /* The ID registers all have impdef reset values */
7403 ARMCPRegInfo v6_idregs[] = {
7404 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
7405 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
7406 .access = PL1_R, .type = ARM_CP_CONST,
7407 .accessfn = access_aa32_tid3,
7408 .resetvalue = cpu->isar.id_pfr0 },
7409 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7410 * the value of the GIC field until after we define these regs.
7412 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
7413 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
7414 .access = PL1_R, .type = ARM_CP_NO_RAW,
7415 .accessfn = access_aa32_tid3,
7416 .readfn = id_pfr1_read,
7417 .writefn = arm_cp_write_ignore },
7418 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
7419 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
7420 .access = PL1_R, .type = ARM_CP_CONST,
7421 .accessfn = access_aa32_tid3,
7422 .resetvalue = cpu->isar.id_dfr0 },
7423 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
7424 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
7425 .access = PL1_R, .type = ARM_CP_CONST,
7426 .accessfn = access_aa32_tid3,
7427 .resetvalue = cpu->id_afr0 },
7428 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
7429 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
7430 .access = PL1_R, .type = ARM_CP_CONST,
7431 .accessfn = access_aa32_tid3,
7432 .resetvalue = cpu->isar.id_mmfr0 },
7433 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
7434 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
7435 .access = PL1_R, .type = ARM_CP_CONST,
7436 .accessfn = access_aa32_tid3,
7437 .resetvalue = cpu->isar.id_mmfr1 },
7438 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
7439 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
7440 .access = PL1_R, .type = ARM_CP_CONST,
7441 .accessfn = access_aa32_tid3,
7442 .resetvalue = cpu->isar.id_mmfr2 },
7443 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
7444 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
7445 .access = PL1_R, .type = ARM_CP_CONST,
7446 .accessfn = access_aa32_tid3,
7447 .resetvalue = cpu->isar.id_mmfr3 },
7448 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
7449 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
7450 .access = PL1_R, .type = ARM_CP_CONST,
7451 .accessfn = access_aa32_tid3,
7452 .resetvalue = cpu->isar.id_isar0 },
7453 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
7454 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
7455 .access = PL1_R, .type = ARM_CP_CONST,
7456 .accessfn = access_aa32_tid3,
7457 .resetvalue = cpu->isar.id_isar1 },
7458 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
7459 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
7460 .access = PL1_R, .type = ARM_CP_CONST,
7461 .accessfn = access_aa32_tid3,
7462 .resetvalue = cpu->isar.id_isar2 },
7463 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
7464 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
7465 .access = PL1_R, .type = ARM_CP_CONST,
7466 .accessfn = access_aa32_tid3,
7467 .resetvalue = cpu->isar.id_isar3 },
7468 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
7469 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
7470 .access = PL1_R, .type = ARM_CP_CONST,
7471 .accessfn = access_aa32_tid3,
7472 .resetvalue = cpu->isar.id_isar4 },
7473 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
7474 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
7475 .access = PL1_R, .type = ARM_CP_CONST,
7476 .accessfn = access_aa32_tid3,
7477 .resetvalue = cpu->isar.id_isar5 },
7478 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
7479 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
7480 .access = PL1_R, .type = ARM_CP_CONST,
7481 .accessfn = access_aa32_tid3,
7482 .resetvalue = cpu->isar.id_mmfr4 },
7483 { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
7484 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
7485 .access = PL1_R, .type = ARM_CP_CONST,
7486 .accessfn = access_aa32_tid3,
7487 .resetvalue = cpu->isar.id_isar6 },
7488 REGINFO_SENTINEL
7490 define_arm_cp_regs(cpu, v6_idregs);
7491 define_arm_cp_regs(cpu, v6_cp_reginfo);
7492 } else {
7493 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
7495 if (arm_feature(env, ARM_FEATURE_V6K)) {
7496 define_arm_cp_regs(cpu, v6k_cp_reginfo);
7498 if (arm_feature(env, ARM_FEATURE_V7MP) &&
7499 !arm_feature(env, ARM_FEATURE_PMSA)) {
7500 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
7502 if (arm_feature(env, ARM_FEATURE_V7VE)) {
7503 define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
7505 if (arm_feature(env, ARM_FEATURE_V7)) {
7506 ARMCPRegInfo clidr = {
7507 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
7508 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
7509 .access = PL1_R, .type = ARM_CP_CONST,
7510 .accessfn = access_aa64_tid2,
7511 .resetvalue = cpu->clidr
7513 define_one_arm_cp_reg(cpu, &clidr);
7514 define_arm_cp_regs(cpu, v7_cp_reginfo);
7515 define_debug_regs(cpu);
7516 define_pmu_regs(cpu);
7517 } else {
7518 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
7520 if (arm_feature(env, ARM_FEATURE_V8)) {
7521 /* AArch64 ID registers, which all have impdef reset values.
7522 * Note that within the ID register ranges the unused slots
7523 * must all RAZ, not UNDEF; future architecture versions may
7524 * define new registers here.
7526 ARMCPRegInfo v8_idregs[] = {
7528 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7529 * emulation because we don't know the right value for the
7530 * GIC field until after we define these regs.
7532 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
7533 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
7534 .access = PL1_R,
7535 #ifdef CONFIG_USER_ONLY
7536 .type = ARM_CP_CONST,
7537 .resetvalue = cpu->isar.id_aa64pfr0
7538 #else
7539 .type = ARM_CP_NO_RAW,
7540 .accessfn = access_aa64_tid3,
7541 .readfn = id_aa64pfr0_read,
7542 .writefn = arm_cp_write_ignore
7543 #endif
7545 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
7546 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
7547 .access = PL1_R, .type = ARM_CP_CONST,
7548 .accessfn = access_aa64_tid3,
7549 .resetvalue = cpu->isar.id_aa64pfr1},
7550 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7551 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
7552 .access = PL1_R, .type = ARM_CP_CONST,
7553 .accessfn = access_aa64_tid3,
7554 .resetvalue = 0 },
7555 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7556 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
7557 .access = PL1_R, .type = ARM_CP_CONST,
7558 .accessfn = access_aa64_tid3,
7559 .resetvalue = 0 },
7560 { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
7561 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
7562 .access = PL1_R, .type = ARM_CP_CONST,
7563 .accessfn = access_aa64_tid3,
7564 /* At present, only SVEver == 0 is defined anyway. */
7565 .resetvalue = 0 },
7566 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7567 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
7568 .access = PL1_R, .type = ARM_CP_CONST,
7569 .accessfn = access_aa64_tid3,
7570 .resetvalue = 0 },
7571 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7572 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
7573 .access = PL1_R, .type = ARM_CP_CONST,
7574 .accessfn = access_aa64_tid3,
7575 .resetvalue = 0 },
7576 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7577 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
7578 .access = PL1_R, .type = ARM_CP_CONST,
7579 .accessfn = access_aa64_tid3,
7580 .resetvalue = 0 },
7581 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
7582 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
7583 .access = PL1_R, .type = ARM_CP_CONST,
7584 .accessfn = access_aa64_tid3,
7585 .resetvalue = cpu->isar.id_aa64dfr0 },
7586 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
7587 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
7588 .access = PL1_R, .type = ARM_CP_CONST,
7589 .accessfn = access_aa64_tid3,
7590 .resetvalue = cpu->isar.id_aa64dfr1 },
7591 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7592 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
7593 .access = PL1_R, .type = ARM_CP_CONST,
7594 .accessfn = access_aa64_tid3,
7595 .resetvalue = 0 },
7596 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7597 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
7598 .access = PL1_R, .type = ARM_CP_CONST,
7599 .accessfn = access_aa64_tid3,
7600 .resetvalue = 0 },
7601 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
7602 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
7603 .access = PL1_R, .type = ARM_CP_CONST,
7604 .accessfn = access_aa64_tid3,
7605 .resetvalue = cpu->id_aa64afr0 },
7606 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
7607 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
7608 .access = PL1_R, .type = ARM_CP_CONST,
7609 .accessfn = access_aa64_tid3,
7610 .resetvalue = cpu->id_aa64afr1 },
7611 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7612 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
7613 .access = PL1_R, .type = ARM_CP_CONST,
7614 .accessfn = access_aa64_tid3,
7615 .resetvalue = 0 },
7616 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7617 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
7618 .access = PL1_R, .type = ARM_CP_CONST,
7619 .accessfn = access_aa64_tid3,
7620 .resetvalue = 0 },
7621 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
7622 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
7623 .access = PL1_R, .type = ARM_CP_CONST,
7624 .accessfn = access_aa64_tid3,
7625 .resetvalue = cpu->isar.id_aa64isar0 },
7626 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
7627 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
7628 .access = PL1_R, .type = ARM_CP_CONST,
7629 .accessfn = access_aa64_tid3,
7630 .resetvalue = cpu->isar.id_aa64isar1 },
7631 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7632 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
7633 .access = PL1_R, .type = ARM_CP_CONST,
7634 .accessfn = access_aa64_tid3,
7635 .resetvalue = 0 },
7636 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7637 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
7638 .access = PL1_R, .type = ARM_CP_CONST,
7639 .accessfn = access_aa64_tid3,
7640 .resetvalue = 0 },
7641 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7642 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
7643 .access = PL1_R, .type = ARM_CP_CONST,
7644 .accessfn = access_aa64_tid3,
7645 .resetvalue = 0 },
7646 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7647 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
7648 .access = PL1_R, .type = ARM_CP_CONST,
7649 .accessfn = access_aa64_tid3,
7650 .resetvalue = 0 },
7651 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7652 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
7653 .access = PL1_R, .type = ARM_CP_CONST,
7654 .accessfn = access_aa64_tid3,
7655 .resetvalue = 0 },
7656 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7657 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
7658 .access = PL1_R, .type = ARM_CP_CONST,
7659 .accessfn = access_aa64_tid3,
7660 .resetvalue = 0 },
7661 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
7662 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
7663 .access = PL1_R, .type = ARM_CP_CONST,
7664 .accessfn = access_aa64_tid3,
7665 .resetvalue = cpu->isar.id_aa64mmfr0 },
7666 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
7667 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
7668 .access = PL1_R, .type = ARM_CP_CONST,
7669 .accessfn = access_aa64_tid3,
7670 .resetvalue = cpu->isar.id_aa64mmfr1 },
7671 { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
7672 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
7673 .access = PL1_R, .type = ARM_CP_CONST,
7674 .accessfn = access_aa64_tid3,
7675 .resetvalue = cpu->isar.id_aa64mmfr2 },
7676 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7677 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
7678 .access = PL1_R, .type = ARM_CP_CONST,
7679 .accessfn = access_aa64_tid3,
7680 .resetvalue = 0 },
7681 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7682 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
7683 .access = PL1_R, .type = ARM_CP_CONST,
7684 .accessfn = access_aa64_tid3,
7685 .resetvalue = 0 },
7686 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7687 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
7688 .access = PL1_R, .type = ARM_CP_CONST,
7689 .accessfn = access_aa64_tid3,
7690 .resetvalue = 0 },
7691 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7692 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
7693 .access = PL1_R, .type = ARM_CP_CONST,
7694 .accessfn = access_aa64_tid3,
7695 .resetvalue = 0 },
7696 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7697 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
7698 .access = PL1_R, .type = ARM_CP_CONST,
7699 .accessfn = access_aa64_tid3,
7700 .resetvalue = 0 },
7701 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
7702 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
7703 .access = PL1_R, .type = ARM_CP_CONST,
7704 .accessfn = access_aa64_tid3,
7705 .resetvalue = cpu->isar.mvfr0 },
7706 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
7707 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
7708 .access = PL1_R, .type = ARM_CP_CONST,
7709 .accessfn = access_aa64_tid3,
7710 .resetvalue = cpu->isar.mvfr1 },
7711 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
7712 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
7713 .access = PL1_R, .type = ARM_CP_CONST,
7714 .accessfn = access_aa64_tid3,
7715 .resetvalue = cpu->isar.mvfr2 },
7716 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7717 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
7718 .access = PL1_R, .type = ARM_CP_CONST,
7719 .accessfn = access_aa64_tid3,
7720 .resetvalue = 0 },
7721 { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
7722 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
7723 .access = PL1_R, .type = ARM_CP_CONST,
7724 .accessfn = access_aa64_tid3,
7725 .resetvalue = cpu->isar.id_pfr2 },
7726 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7727 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
7728 .access = PL1_R, .type = ARM_CP_CONST,
7729 .accessfn = access_aa64_tid3,
7730 .resetvalue = 0 },
7731 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7732 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
7733 .access = PL1_R, .type = ARM_CP_CONST,
7734 .accessfn = access_aa64_tid3,
7735 .resetvalue = 0 },
7736 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7737 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
7738 .access = PL1_R, .type = ARM_CP_CONST,
7739 .accessfn = access_aa64_tid3,
7740 .resetvalue = 0 },
7741 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
7742 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
7743 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7744 .resetvalue = extract64(cpu->pmceid0, 0, 32) },
7745 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
7746 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
7747 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7748 .resetvalue = cpu->pmceid0 },
7749 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
7750 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
7751 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7752 .resetvalue = extract64(cpu->pmceid1, 0, 32) },
7753 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
7754 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
7755 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7756 .resetvalue = cpu->pmceid1 },
7757 REGINFO_SENTINEL
7759 #ifdef CONFIG_USER_ONLY
7760 ARMCPRegUserSpaceInfo v8_user_idregs[] = {
7761 { .name = "ID_AA64PFR0_EL1",
7762 .exported_bits = 0x000f000f00ff0000,
7763 .fixed_bits = 0x0000000000000011 },
7764 { .name = "ID_AA64PFR1_EL1",
7765 .exported_bits = 0x00000000000000f0 },
7766 { .name = "ID_AA64PFR*_EL1_RESERVED",
7767 .is_glob = true },
7768 { .name = "ID_AA64ZFR0_EL1" },
7769 { .name = "ID_AA64MMFR0_EL1",
7770 .fixed_bits = 0x00000000ff000000 },
7771 { .name = "ID_AA64MMFR1_EL1" },
7772 { .name = "ID_AA64MMFR*_EL1_RESERVED",
7773 .is_glob = true },
7774 { .name = "ID_AA64DFR0_EL1",
7775 .fixed_bits = 0x0000000000000006 },
7776 { .name = "ID_AA64DFR1_EL1" },
7777 { .name = "ID_AA64DFR*_EL1_RESERVED",
7778 .is_glob = true },
7779 { .name = "ID_AA64AFR*",
7780 .is_glob = true },
7781 { .name = "ID_AA64ISAR0_EL1",
7782 .exported_bits = 0x00fffffff0fffff0 },
7783 { .name = "ID_AA64ISAR1_EL1",
7784 .exported_bits = 0x000000f0ffffffff },
7785 { .name = "ID_AA64ISAR*_EL1_RESERVED",
7786 .is_glob = true },
7787 REGUSERINFO_SENTINEL
7789 modify_arm_cp_regs(v8_idregs, v8_user_idregs);
7790 #endif
7791 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7792 if (!arm_feature(env, ARM_FEATURE_EL3) &&
7793 !arm_feature(env, ARM_FEATURE_EL2)) {
7794 ARMCPRegInfo rvbar = {
7795 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
7796 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
7797 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
7799 define_one_arm_cp_reg(cpu, &rvbar);
7801 define_arm_cp_regs(cpu, v8_idregs);
7802 define_arm_cp_regs(cpu, v8_cp_reginfo);
7804 if (arm_feature(env, ARM_FEATURE_EL2)) {
7805 uint64_t vmpidr_def = mpidr_read_val(env);
7806 ARMCPRegInfo vpidr_regs[] = {
7807 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
7808 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7809 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7810 .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
7811 .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
7812 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
7813 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7814 .access = PL2_RW, .resetvalue = cpu->midr,
7815 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
7816 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
7817 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7818 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7819 .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
7820 .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
7821 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
7822 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7823 .access = PL2_RW,
7824 .resetvalue = vmpidr_def,
7825 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
7826 REGINFO_SENTINEL
7828 define_arm_cp_regs(cpu, vpidr_regs);
7829 define_arm_cp_regs(cpu, el2_cp_reginfo);
7830 if (arm_feature(env, ARM_FEATURE_V8)) {
7831 define_arm_cp_regs(cpu, el2_v8_cp_reginfo);
7833 if (cpu_isar_feature(aa64_sel2, cpu)) {
7834 define_arm_cp_regs(cpu, el2_sec_cp_reginfo);
7836 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7837 if (!arm_feature(env, ARM_FEATURE_EL3)) {
7838 ARMCPRegInfo rvbar = {
7839 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
7840 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
7841 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
7843 define_one_arm_cp_reg(cpu, &rvbar);
7845 } else {
7846 /* If EL2 is missing but higher ELs are enabled, we need to
7847 * register the no_el2 reginfos.
7849 if (arm_feature(env, ARM_FEATURE_EL3)) {
7850 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7851 * of MIDR_EL1 and MPIDR_EL1.
7853 ARMCPRegInfo vpidr_regs[] = {
7854 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7855 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7856 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7857 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
7858 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
7859 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7860 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7861 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7862 .type = ARM_CP_NO_RAW,
7863 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
7864 REGINFO_SENTINEL
7866 define_arm_cp_regs(cpu, vpidr_regs);
7867 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
7868 if (arm_feature(env, ARM_FEATURE_V8)) {
7869 define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
7873 if (arm_feature(env, ARM_FEATURE_EL3)) {
7874 define_arm_cp_regs(cpu, el3_cp_reginfo);
7875 ARMCPRegInfo el3_regs[] = {
7876 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
7877 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
7878 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
7879 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
7880 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
7881 .access = PL3_RW,
7882 .raw_writefn = raw_write, .writefn = sctlr_write,
7883 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
7884 .resetvalue = cpu->reset_sctlr },
7885 REGINFO_SENTINEL
7888 define_arm_cp_regs(cpu, el3_regs);
7890 /* The behaviour of NSACR is sufficiently various that we don't
7891 * try to describe it in a single reginfo:
7892 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7893 * reads as constant 0xc00 from NS EL1 and NS EL2
7894 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7895 * if v7 without EL3, register doesn't exist
7896 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7898 if (arm_feature(env, ARM_FEATURE_EL3)) {
7899 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
7900 ARMCPRegInfo nsacr = {
7901 .name = "NSACR", .type = ARM_CP_CONST,
7902 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7903 .access = PL1_RW, .accessfn = nsacr_access,
7904 .resetvalue = 0xc00
7906 define_one_arm_cp_reg(cpu, &nsacr);
7907 } else {
7908 ARMCPRegInfo nsacr = {
7909 .name = "NSACR",
7910 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7911 .access = PL3_RW | PL1_R,
7912 .resetvalue = 0,
7913 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
7915 define_one_arm_cp_reg(cpu, &nsacr);
7917 } else {
7918 if (arm_feature(env, ARM_FEATURE_V8)) {
7919 ARMCPRegInfo nsacr = {
7920 .name = "NSACR", .type = ARM_CP_CONST,
7921 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7922 .access = PL1_R,
7923 .resetvalue = 0xc00
7925 define_one_arm_cp_reg(cpu, &nsacr);
7929 if (arm_feature(env, ARM_FEATURE_PMSA)) {
7930 if (arm_feature(env, ARM_FEATURE_V6)) {
7931 /* PMSAv6 not implemented */
7932 assert(arm_feature(env, ARM_FEATURE_V7));
7933 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7934 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
7935 } else {
7936 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
7938 } else {
7939 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7940 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
7941 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7942 if (cpu_isar_feature(aa32_hpd, cpu)) {
7943 define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
7946 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
7947 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
7949 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
7950 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
7952 if (arm_feature(env, ARM_FEATURE_VAPA)) {
7953 define_arm_cp_regs(cpu, vapa_cp_reginfo);
7955 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
7956 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
7958 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
7959 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
7961 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
7962 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
7964 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
7965 define_arm_cp_regs(cpu, omap_cp_reginfo);
7967 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
7968 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
7970 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
7971 define_arm_cp_regs(cpu, xscale_cp_reginfo);
7973 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
7974 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
7976 if (arm_feature(env, ARM_FEATURE_LPAE)) {
7977 define_arm_cp_regs(cpu, lpae_cp_reginfo);
7979 if (cpu_isar_feature(aa32_jazelle, cpu)) {
7980 define_arm_cp_regs(cpu, jazelle_regs);
7982 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7983 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7984 * be read-only (ie write causes UNDEF exception).
7987 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
7988 /* Pre-v8 MIDR space.
7989 * Note that the MIDR isn't a simple constant register because
7990 * of the TI925 behaviour where writes to another register can
7991 * cause the MIDR value to change.
7993 * Unimplemented registers in the c15 0 0 0 space default to
7994 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7995 * and friends override accordingly.
7997 { .name = "MIDR",
7998 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7999 .access = PL1_R, .resetvalue = cpu->midr,
8000 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
8001 .readfn = midr_read,
8002 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
8003 .type = ARM_CP_OVERRIDE },
8004 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8005 { .name = "DUMMY",
8006 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
8007 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
8008 { .name = "DUMMY",
8009 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
8010 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
8011 { .name = "DUMMY",
8012 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
8013 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
8014 { .name = "DUMMY",
8015 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
8016 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
8017 { .name = "DUMMY",
8018 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
8019 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
8020 REGINFO_SENTINEL
8022 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
8023 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
8024 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
8025 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
8026 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
8027 .readfn = midr_read },
8028 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
8029 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
8030 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
8031 .access = PL1_R, .resetvalue = cpu->midr },
8032 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
8033 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
8034 .access = PL1_R, .resetvalue = cpu->midr },
8035 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
8036 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
8037 .access = PL1_R,
8038 .accessfn = access_aa64_tid1,
8039 .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
8040 REGINFO_SENTINEL
8042 ARMCPRegInfo id_cp_reginfo[] = {
8043 /* These are common to v8 and pre-v8 */
8044 { .name = "CTR",
8045 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
8046 .access = PL1_R, .accessfn = ctr_el0_access,
8047 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
8048 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
8049 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
8050 .access = PL0_R, .accessfn = ctr_el0_access,
8051 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
8052 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8053 { .name = "TCMTR",
8054 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
8055 .access = PL1_R,
8056 .accessfn = access_aa32_tid1,
8057 .type = ARM_CP_CONST, .resetvalue = 0 },
8058 REGINFO_SENTINEL
8060 /* TLBTR is specific to VMSA */
8061 ARMCPRegInfo id_tlbtr_reginfo = {
8062 .name = "TLBTR",
8063 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
8064 .access = PL1_R,
8065 .accessfn = access_aa32_tid1,
8066 .type = ARM_CP_CONST, .resetvalue = 0,
8068 /* MPUIR is specific to PMSA V6+ */
8069 ARMCPRegInfo id_mpuir_reginfo = {
8070 .name = "MPUIR",
8071 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
8072 .access = PL1_R, .type = ARM_CP_CONST,
8073 .resetvalue = cpu->pmsav7_dregion << 8
8075 ARMCPRegInfo crn0_wi_reginfo = {
8076 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
8077 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
8078 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
8080 #ifdef CONFIG_USER_ONLY
8081 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
8082 { .name = "MIDR_EL1",
8083 .exported_bits = 0x00000000ffffffff },
8084 { .name = "REVIDR_EL1" },
8085 REGUSERINFO_SENTINEL
8087 modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
8088 #endif
8089 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
8090 arm_feature(env, ARM_FEATURE_STRONGARM)) {
8091 ARMCPRegInfo *r;
8092 /* Register the blanket "writes ignored" value first to cover the
8093 * whole space. Then update the specific ID registers to allow write
8094 * access, so that they ignore writes rather than causing them to
8095 * UNDEF.
8097 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
8098 for (r = id_pre_v8_midr_cp_reginfo;
8099 r->type != ARM_CP_SENTINEL; r++) {
8100 r->access = PL1_RW;
8102 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
8103 r->access = PL1_RW;
8105 id_mpuir_reginfo.access = PL1_RW;
8106 id_tlbtr_reginfo.access = PL1_RW;
8108 if (arm_feature(env, ARM_FEATURE_V8)) {
8109 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
8110 } else {
8111 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
8113 define_arm_cp_regs(cpu, id_cp_reginfo);
8114 if (!arm_feature(env, ARM_FEATURE_PMSA)) {
8115 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
8116 } else if (arm_feature(env, ARM_FEATURE_V7)) {
8117 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
8121 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
8122 ARMCPRegInfo mpidr_cp_reginfo[] = {
8123 { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
8124 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
8125 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
8126 REGINFO_SENTINEL
8128 #ifdef CONFIG_USER_ONLY
8129 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
8130 { .name = "MPIDR_EL1",
8131 .fixed_bits = 0x0000000080000000 },
8132 REGUSERINFO_SENTINEL
8134 modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
8135 #endif
8136 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
8139 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
8140 ARMCPRegInfo auxcr_reginfo[] = {
8141 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
8142 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
8143 .access = PL1_RW, .accessfn = access_tacr,
8144 .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr },
8145 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
8146 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
8147 .access = PL2_RW, .type = ARM_CP_CONST,
8148 .resetvalue = 0 },
8149 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
8150 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
8151 .access = PL3_RW, .type = ARM_CP_CONST,
8152 .resetvalue = 0 },
8153 REGINFO_SENTINEL
8155 define_arm_cp_regs(cpu, auxcr_reginfo);
8156 if (cpu_isar_feature(aa32_ac2, cpu)) {
8157 define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo);
8161 if (arm_feature(env, ARM_FEATURE_CBAR)) {
8163 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8164 * There are two flavours:
8165 * (1) older 32-bit only cores have a simple 32-bit CBAR
8166 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8167 * 32-bit register visible to AArch32 at a different encoding
8168 * to the "flavour 1" register and with the bits rearranged to
8169 * be able to squash a 64-bit address into the 32-bit view.
8170 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8171 * in future if we support AArch32-only configs of some of the
8172 * AArch64 cores we might need to add a specific feature flag
8173 * to indicate cores with "flavour 2" CBAR.
8175 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
8176 /* 32 bit view is [31:18] 0...0 [43:32]. */
8177 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
8178 | extract64(cpu->reset_cbar, 32, 12);
8179 ARMCPRegInfo cbar_reginfo[] = {
8180 { .name = "CBAR",
8181 .type = ARM_CP_CONST,
8182 .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
8183 .access = PL1_R, .resetvalue = cbar32 },
8184 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
8185 .type = ARM_CP_CONST,
8186 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
8187 .access = PL1_R, .resetvalue = cpu->reset_cbar },
8188 REGINFO_SENTINEL
8190 /* We don't implement a r/w 64 bit CBAR currently */
8191 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
8192 define_arm_cp_regs(cpu, cbar_reginfo);
8193 } else {
8194 ARMCPRegInfo cbar = {
8195 .name = "CBAR",
8196 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
8197 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
8198 .fieldoffset = offsetof(CPUARMState,
8199 cp15.c15_config_base_address)
8201 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
8202 cbar.access = PL1_R;
8203 cbar.fieldoffset = 0;
8204 cbar.type = ARM_CP_CONST;
8206 define_one_arm_cp_reg(cpu, &cbar);
8210 if (arm_feature(env, ARM_FEATURE_VBAR)) {
8211 ARMCPRegInfo vbar_cp_reginfo[] = {
8212 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
8213 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
8214 .access = PL1_RW, .writefn = vbar_write,
8215 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
8216 offsetof(CPUARMState, cp15.vbar_ns) },
8217 .resetvalue = 0 },
8218 REGINFO_SENTINEL
8220 define_arm_cp_regs(cpu, vbar_cp_reginfo);
8223 /* Generic registers whose values depend on the implementation */
8225 ARMCPRegInfo sctlr = {
8226 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
8227 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
8228 .access = PL1_RW, .accessfn = access_tvm_trvm,
8229 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
8230 offsetof(CPUARMState, cp15.sctlr_ns) },
8231 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
8232 .raw_writefn = raw_write,
8234 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
8235 /* Normally we would always end the TB on an SCTLR write, but Linux
8236 * arch/arm/mach-pxa/sleep.S expects two instructions following
8237 * an MMU enable to execute from cache. Imitate this behaviour.
8239 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
8241 define_one_arm_cp_reg(cpu, &sctlr);
8244 if (cpu_isar_feature(aa64_lor, cpu)) {
8245 define_arm_cp_regs(cpu, lor_reginfo);
8247 if (cpu_isar_feature(aa64_pan, cpu)) {
8248 define_one_arm_cp_reg(cpu, &pan_reginfo);
8250 #ifndef CONFIG_USER_ONLY
8251 if (cpu_isar_feature(aa64_ats1e1, cpu)) {
8252 define_arm_cp_regs(cpu, ats1e1_reginfo);
8254 if (cpu_isar_feature(aa32_ats1e1, cpu)) {
8255 define_arm_cp_regs(cpu, ats1cp_reginfo);
8257 #endif
8258 if (cpu_isar_feature(aa64_uao, cpu)) {
8259 define_one_arm_cp_reg(cpu, &uao_reginfo);
8262 if (cpu_isar_feature(aa64_dit, cpu)) {
8263 define_one_arm_cp_reg(cpu, &dit_reginfo);
8265 if (cpu_isar_feature(aa64_ssbs, cpu)) {
8266 define_one_arm_cp_reg(cpu, &ssbs_reginfo);
8269 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
8270 define_arm_cp_regs(cpu, vhe_reginfo);
8273 if (cpu_isar_feature(aa64_sve, cpu)) {
8274 define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
8275 if (arm_feature(env, ARM_FEATURE_EL2)) {
8276 define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
8277 } else {
8278 define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
8280 if (arm_feature(env, ARM_FEATURE_EL3)) {
8281 define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
8285 #ifdef TARGET_AARCH64
8286 if (cpu_isar_feature(aa64_pauth, cpu)) {
8287 define_arm_cp_regs(cpu, pauth_reginfo);
8289 if (cpu_isar_feature(aa64_rndr, cpu)) {
8290 define_arm_cp_regs(cpu, rndr_reginfo);
8292 #ifndef CONFIG_USER_ONLY
8293 /* Data Cache clean instructions up to PoP */
8294 if (cpu_isar_feature(aa64_dcpop, cpu)) {
8295 define_one_arm_cp_reg(cpu, dcpop_reg);
8297 if (cpu_isar_feature(aa64_dcpodp, cpu)) {
8298 define_one_arm_cp_reg(cpu, dcpodp_reg);
8301 #endif /*CONFIG_USER_ONLY*/
8304 * If full MTE is enabled, add all of the system registers.
8305 * If only "instructions available at EL0" are enabled,
8306 * then define only a RAZ/WI version of PSTATE.TCO.
8308 if (cpu_isar_feature(aa64_mte, cpu)) {
8309 define_arm_cp_regs(cpu, mte_reginfo);
8310 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
8311 } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
8312 define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
8313 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
8315 #endif
8317 if (cpu_isar_feature(any_predinv, cpu)) {
8318 define_arm_cp_regs(cpu, predinv_reginfo);
8321 if (cpu_isar_feature(any_ccidx, cpu)) {
8322 define_arm_cp_regs(cpu, ccsidr2_reginfo);
8325 #ifndef CONFIG_USER_ONLY
8327 * Register redirections and aliases must be done last,
8328 * after the registers from the other extensions have been defined.
8330 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
8331 define_arm_vh_e2h_redirects_aliases(cpu);
8333 #endif
8336 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
8338 CPUState *cs = CPU(cpu);
8339 CPUARMState *env = &cpu->env;
8341 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
8343 * The lower part of each SVE register aliases to the FPU
8344 * registers so we don't need to include both.
8346 #ifdef TARGET_AARCH64
8347 if (isar_feature_aa64_sve(&cpu->isar)) {
8348 gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
8349 arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
8350 "sve-registers.xml", 0);
8351 } else
8352 #endif
8354 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
8355 aarch64_fpu_gdb_set_reg,
8356 34, "aarch64-fpu.xml", 0);
8358 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
8359 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
8360 51, "arm-neon.xml", 0);
8361 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
8362 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
8363 35, "arm-vfp3.xml", 0);
8364 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
8365 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
8366 19, "arm-vfp.xml", 0);
8368 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
8369 arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
8370 "system-registers.xml", 0);
8374 /* Sort alphabetically by type name, except for "any". */
8375 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
8377 ObjectClass *class_a = (ObjectClass *)a;
8378 ObjectClass *class_b = (ObjectClass *)b;
8379 const char *name_a, *name_b;
8381 name_a = object_class_get_name(class_a);
8382 name_b = object_class_get_name(class_b);
8383 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
8384 return 1;
8385 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
8386 return -1;
8387 } else {
8388 return strcmp(name_a, name_b);
8392 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
8394 ObjectClass *oc = data;
8395 const char *typename;
8396 char *name;
8398 typename = object_class_get_name(oc);
8399 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
8400 qemu_printf(" %s\n", name);
8401 g_free(name);
8404 void arm_cpu_list(void)
8406 GSList *list;
8408 list = object_class_get_list(TYPE_ARM_CPU, false);
8409 list = g_slist_sort(list, arm_cpu_list_compare);
8410 qemu_printf("Available CPUs:\n");
8411 g_slist_foreach(list, arm_cpu_list_entry, NULL);
8412 g_slist_free(list);
8415 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
8417 ObjectClass *oc = data;
8418 CpuDefinitionInfoList **cpu_list = user_data;
8419 CpuDefinitionInfo *info;
8420 const char *typename;
8422 typename = object_class_get_name(oc);
8423 info = g_malloc0(sizeof(*info));
8424 info->name = g_strndup(typename,
8425 strlen(typename) - strlen("-" TYPE_ARM_CPU));
8426 info->q_typename = g_strdup(typename);
8428 QAPI_LIST_PREPEND(*cpu_list, info);
8431 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
8433 CpuDefinitionInfoList *cpu_list = NULL;
8434 GSList *list;
8436 list = object_class_get_list(TYPE_ARM_CPU, false);
8437 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
8438 g_slist_free(list);
8440 return cpu_list;
8443 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
8444 void *opaque, int state, int secstate,
8445 int crm, int opc1, int opc2,
8446 const char *name)
8448 /* Private utility function for define_one_arm_cp_reg_with_opaque():
8449 * add a single reginfo struct to the hash table.
8451 uint32_t *key = g_new(uint32_t, 1);
8452 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
8453 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
8454 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
8456 r2->name = g_strdup(name);
8457 /* Reset the secure state to the specific incoming state. This is
8458 * necessary as the register may have been defined with both states.
8460 r2->secure = secstate;
8462 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
8463 /* Register is banked (using both entries in array).
8464 * Overwriting fieldoffset as the array is only used to define
8465 * banked registers but later only fieldoffset is used.
8467 r2->fieldoffset = r->bank_fieldoffsets[ns];
8470 if (state == ARM_CP_STATE_AA32) {
8471 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
8472 /* If the register is banked then we don't need to migrate or
8473 * reset the 32-bit instance in certain cases:
8475 * 1) If the register has both 32-bit and 64-bit instances then we
8476 * can count on the 64-bit instance taking care of the
8477 * non-secure bank.
8478 * 2) If ARMv8 is enabled then we can count on a 64-bit version
8479 * taking care of the secure bank. This requires that separate
8480 * 32 and 64-bit definitions are provided.
8482 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
8483 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
8484 r2->type |= ARM_CP_ALIAS;
8486 } else if ((secstate != r->secure) && !ns) {
8487 /* The register is not banked so we only want to allow migration of
8488 * the non-secure instance.
8490 r2->type |= ARM_CP_ALIAS;
8493 if (r->state == ARM_CP_STATE_BOTH) {
8494 /* We assume it is a cp15 register if the .cp field is left unset.
8496 if (r2->cp == 0) {
8497 r2->cp = 15;
8500 #ifdef HOST_WORDS_BIGENDIAN
8501 if (r2->fieldoffset) {
8502 r2->fieldoffset += sizeof(uint32_t);
8504 #endif
8507 if (state == ARM_CP_STATE_AA64) {
8508 /* To allow abbreviation of ARMCPRegInfo
8509 * definitions, we treat cp == 0 as equivalent to
8510 * the value for "standard guest-visible sysreg".
8511 * STATE_BOTH definitions are also always "standard
8512 * sysreg" in their AArch64 view (the .cp value may
8513 * be non-zero for the benefit of the AArch32 view).
8515 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
8516 r2->cp = CP_REG_ARM64_SYSREG_CP;
8518 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
8519 r2->opc0, opc1, opc2);
8520 } else {
8521 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
8523 if (opaque) {
8524 r2->opaque = opaque;
8526 /* reginfo passed to helpers is correct for the actual access,
8527 * and is never ARM_CP_STATE_BOTH:
8529 r2->state = state;
8530 /* Make sure reginfo passed to helpers for wildcarded regs
8531 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8533 r2->crm = crm;
8534 r2->opc1 = opc1;
8535 r2->opc2 = opc2;
8536 /* By convention, for wildcarded registers only the first
8537 * entry is used for migration; the others are marked as
8538 * ALIAS so we don't try to transfer the register
8539 * multiple times. Special registers (ie NOP/WFI) are
8540 * never migratable and not even raw-accessible.
8542 if ((r->type & ARM_CP_SPECIAL)) {
8543 r2->type |= ARM_CP_NO_RAW;
8545 if (((r->crm == CP_ANY) && crm != 0) ||
8546 ((r->opc1 == CP_ANY) && opc1 != 0) ||
8547 ((r->opc2 == CP_ANY) && opc2 != 0)) {
8548 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
8551 /* Check that raw accesses are either forbidden or handled. Note that
8552 * we can't assert this earlier because the setup of fieldoffset for
8553 * banked registers has to be done first.
8555 if (!(r2->type & ARM_CP_NO_RAW)) {
8556 assert(!raw_accessors_invalid(r2));
8559 /* Overriding of an existing definition must be explicitly
8560 * requested.
8562 if (!(r->type & ARM_CP_OVERRIDE)) {
8563 ARMCPRegInfo *oldreg;
8564 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
8565 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
8566 fprintf(stderr, "Register redefined: cp=%d %d bit "
8567 "crn=%d crm=%d opc1=%d opc2=%d, "
8568 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
8569 r2->crn, r2->crm, r2->opc1, r2->opc2,
8570 oldreg->name, r2->name);
8571 g_assert_not_reached();
8574 g_hash_table_insert(cpu->cp_regs, key, r2);
8578 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
8579 const ARMCPRegInfo *r, void *opaque)
8581 /* Define implementations of coprocessor registers.
8582 * We store these in a hashtable because typically
8583 * there are less than 150 registers in a space which
8584 * is 16*16*16*8*8 = 262144 in size.
8585 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8586 * If a register is defined twice then the second definition is
8587 * used, so this can be used to define some generic registers and
8588 * then override them with implementation specific variations.
8589 * At least one of the original and the second definition should
8590 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8591 * against accidental use.
8593 * The state field defines whether the register is to be
8594 * visible in the AArch32 or AArch64 execution state. If the
8595 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8596 * reginfo structure for the AArch32 view, which sees the lower
8597 * 32 bits of the 64 bit register.
8599 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8600 * be wildcarded. AArch64 registers are always considered to be 64
8601 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8602 * the register, if any.
8604 int crm, opc1, opc2, state;
8605 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
8606 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
8607 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
8608 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
8609 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
8610 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
8611 /* 64 bit registers have only CRm and Opc1 fields */
8612 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
8613 /* op0 only exists in the AArch64 encodings */
8614 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
8615 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8616 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
8618 * This API is only for Arm's system coprocessors (14 and 15) or
8619 * (M-profile or v7A-and-earlier only) for implementation defined
8620 * coprocessors in the range 0..7. Our decode assumes this, since
8621 * 8..13 can be used for other insns including VFP and Neon. See
8622 * valid_cp() in translate.c. Assert here that we haven't tried
8623 * to use an invalid coprocessor number.
8625 switch (r->state) {
8626 case ARM_CP_STATE_BOTH:
8627 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8628 if (r->cp == 0) {
8629 break;
8631 /* fall through */
8632 case ARM_CP_STATE_AA32:
8633 if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
8634 !arm_feature(&cpu->env, ARM_FEATURE_M)) {
8635 assert(r->cp >= 14 && r->cp <= 15);
8636 } else {
8637 assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15));
8639 break;
8640 case ARM_CP_STATE_AA64:
8641 assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP);
8642 break;
8643 default:
8644 g_assert_not_reached();
8646 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8647 * encodes a minimum access level for the register. We roll this
8648 * runtime check into our general permission check code, so check
8649 * here that the reginfo's specified permissions are strict enough
8650 * to encompass the generic architectural permission check.
8652 if (r->state != ARM_CP_STATE_AA32) {
8653 int mask = 0;
8654 switch (r->opc1) {
8655 case 0:
8656 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8657 mask = PL0U_R | PL1_RW;
8658 break;
8659 case 1: case 2:
8660 /* min_EL EL1 */
8661 mask = PL1_RW;
8662 break;
8663 case 3:
8664 /* min_EL EL0 */
8665 mask = PL0_RW;
8666 break;
8667 case 4:
8668 case 5:
8669 /* min_EL EL2 */
8670 mask = PL2_RW;
8671 break;
8672 case 6:
8673 /* min_EL EL3 */
8674 mask = PL3_RW;
8675 break;
8676 case 7:
8677 /* min_EL EL1, secure mode only (we don't check the latter) */
8678 mask = PL1_RW;
8679 break;
8680 default:
8681 /* broken reginfo with out-of-range opc1 */
8682 assert(false);
8683 break;
8685 /* assert our permissions are not too lax (stricter is fine) */
8686 assert((r->access & ~mask) == 0);
8689 /* Check that the register definition has enough info to handle
8690 * reads and writes if they are permitted.
8692 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
8693 if (r->access & PL3_R) {
8694 assert((r->fieldoffset ||
8695 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8696 r->readfn);
8698 if (r->access & PL3_W) {
8699 assert((r->fieldoffset ||
8700 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8701 r->writefn);
8704 /* Bad type field probably means missing sentinel at end of reg list */
8705 assert(cptype_valid(r->type));
8706 for (crm = crmmin; crm <= crmmax; crm++) {
8707 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
8708 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
8709 for (state = ARM_CP_STATE_AA32;
8710 state <= ARM_CP_STATE_AA64; state++) {
8711 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
8712 continue;
8714 if (state == ARM_CP_STATE_AA32) {
8715 /* Under AArch32 CP registers can be common
8716 * (same for secure and non-secure world) or banked.
8718 char *name;
8720 switch (r->secure) {
8721 case ARM_CP_SECSTATE_S:
8722 case ARM_CP_SECSTATE_NS:
8723 add_cpreg_to_hashtable(cpu, r, opaque, state,
8724 r->secure, crm, opc1, opc2,
8725 r->name);
8726 break;
8727 default:
8728 name = g_strdup_printf("%s_S", r->name);
8729 add_cpreg_to_hashtable(cpu, r, opaque, state,
8730 ARM_CP_SECSTATE_S,
8731 crm, opc1, opc2, name);
8732 g_free(name);
8733 add_cpreg_to_hashtable(cpu, r, opaque, state,
8734 ARM_CP_SECSTATE_NS,
8735 crm, opc1, opc2, r->name);
8736 break;
8738 } else {
8739 /* AArch64 registers get mapped to non-secure instance
8740 * of AArch32 */
8741 add_cpreg_to_hashtable(cpu, r, opaque, state,
8742 ARM_CP_SECSTATE_NS,
8743 crm, opc1, opc2, r->name);
8751 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
8752 const ARMCPRegInfo *regs, void *opaque)
8754 /* Define a whole list of registers */
8755 const ARMCPRegInfo *r;
8756 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8757 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
8762 * Modify ARMCPRegInfo for access from userspace.
8764 * This is a data driven modification directed by
8765 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8766 * user-space cannot alter any values and dynamic values pertaining to
8767 * execution state are hidden from user space view anyway.
8769 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
8771 const ARMCPRegUserSpaceInfo *m;
8772 ARMCPRegInfo *r;
8774 for (m = mods; m->name; m++) {
8775 GPatternSpec *pat = NULL;
8776 if (m->is_glob) {
8777 pat = g_pattern_spec_new(m->name);
8779 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8780 if (pat && g_pattern_match_string(pat, r->name)) {
8781 r->type = ARM_CP_CONST;
8782 r->access = PL0U_R;
8783 r->resetvalue = 0;
8784 /* continue */
8785 } else if (strcmp(r->name, m->name) == 0) {
8786 r->type = ARM_CP_CONST;
8787 r->access = PL0U_R;
8788 r->resetvalue &= m->exported_bits;
8789 r->resetvalue |= m->fixed_bits;
8790 break;
8793 if (pat) {
8794 g_pattern_spec_free(pat);
8799 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
8801 return g_hash_table_lookup(cpregs, &encoded_cp);
8804 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
8805 uint64_t value)
8807 /* Helper coprocessor write function for write-ignore registers */
8810 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
8812 /* Helper coprocessor write function for read-as-zero registers */
8813 return 0;
8816 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
8818 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8821 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
8823 /* Return true if it is not valid for us to switch to
8824 * this CPU mode (ie all the UNPREDICTABLE cases in
8825 * the ARM ARM CPSRWriteByInstr pseudocode).
8828 /* Changes to or from Hyp via MSR and CPS are illegal. */
8829 if (write_type == CPSRWriteByInstr &&
8830 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
8831 mode == ARM_CPU_MODE_HYP)) {
8832 return 1;
8835 switch (mode) {
8836 case ARM_CPU_MODE_USR:
8837 return 0;
8838 case ARM_CPU_MODE_SYS:
8839 case ARM_CPU_MODE_SVC:
8840 case ARM_CPU_MODE_ABT:
8841 case ARM_CPU_MODE_UND:
8842 case ARM_CPU_MODE_IRQ:
8843 case ARM_CPU_MODE_FIQ:
8844 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8845 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8847 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8848 * and CPS are treated as illegal mode changes.
8850 if (write_type == CPSRWriteByInstr &&
8851 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
8852 (arm_hcr_el2_eff(env) & HCR_TGE)) {
8853 return 1;
8855 return 0;
8856 case ARM_CPU_MODE_HYP:
8857 return !arm_is_el2_enabled(env) || arm_current_el(env) < 2;
8858 case ARM_CPU_MODE_MON:
8859 return arm_current_el(env) < 3;
8860 default:
8861 return 1;
8865 uint32_t cpsr_read(CPUARMState *env)
8867 int ZF;
8868 ZF = (env->ZF == 0);
8869 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
8870 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
8871 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
8872 | ((env->condexec_bits & 0xfc) << 8)
8873 | (env->GE << 16) | (env->daif & CPSR_AIF);
8876 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
8877 CPSRWriteType write_type)
8879 uint32_t changed_daif;
8881 if (mask & CPSR_NZCV) {
8882 env->ZF = (~val) & CPSR_Z;
8883 env->NF = val;
8884 env->CF = (val >> 29) & 1;
8885 env->VF = (val << 3) & 0x80000000;
8887 if (mask & CPSR_Q)
8888 env->QF = ((val & CPSR_Q) != 0);
8889 if (mask & CPSR_T)
8890 env->thumb = ((val & CPSR_T) != 0);
8891 if (mask & CPSR_IT_0_1) {
8892 env->condexec_bits &= ~3;
8893 env->condexec_bits |= (val >> 25) & 3;
8895 if (mask & CPSR_IT_2_7) {
8896 env->condexec_bits &= 3;
8897 env->condexec_bits |= (val >> 8) & 0xfc;
8899 if (mask & CPSR_GE) {
8900 env->GE = (val >> 16) & 0xf;
8903 /* In a V7 implementation that includes the security extensions but does
8904 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8905 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8906 * bits respectively.
8908 * In a V8 implementation, it is permitted for privileged software to
8909 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8911 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
8912 arm_feature(env, ARM_FEATURE_EL3) &&
8913 !arm_feature(env, ARM_FEATURE_EL2) &&
8914 !arm_is_secure(env)) {
8916 changed_daif = (env->daif ^ val) & mask;
8918 if (changed_daif & CPSR_A) {
8919 /* Check to see if we are allowed to change the masking of async
8920 * abort exceptions from a non-secure state.
8922 if (!(env->cp15.scr_el3 & SCR_AW)) {
8923 qemu_log_mask(LOG_GUEST_ERROR,
8924 "Ignoring attempt to switch CPSR_A flag from "
8925 "non-secure world with SCR.AW bit clear\n");
8926 mask &= ~CPSR_A;
8930 if (changed_daif & CPSR_F) {
8931 /* Check to see if we are allowed to change the masking of FIQ
8932 * exceptions from a non-secure state.
8934 if (!(env->cp15.scr_el3 & SCR_FW)) {
8935 qemu_log_mask(LOG_GUEST_ERROR,
8936 "Ignoring attempt to switch CPSR_F flag from "
8937 "non-secure world with SCR.FW bit clear\n");
8938 mask &= ~CPSR_F;
8941 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8942 * If this bit is set software is not allowed to mask
8943 * FIQs, but is allowed to set CPSR_F to 0.
8945 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
8946 (val & CPSR_F)) {
8947 qemu_log_mask(LOG_GUEST_ERROR,
8948 "Ignoring attempt to enable CPSR_F flag "
8949 "(non-maskable FIQ [NMFI] support enabled)\n");
8950 mask &= ~CPSR_F;
8955 env->daif &= ~(CPSR_AIF & mask);
8956 env->daif |= val & CPSR_AIF & mask;
8958 if (write_type != CPSRWriteRaw &&
8959 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
8960 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
8961 /* Note that we can only get here in USR mode if this is a
8962 * gdb stub write; for this case we follow the architectural
8963 * behaviour for guest writes in USR mode of ignoring an attempt
8964 * to switch mode. (Those are caught by translate.c for writes
8965 * triggered by guest instructions.)
8967 mask &= ~CPSR_M;
8968 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
8969 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8970 * v7, and has defined behaviour in v8:
8971 * + leave CPSR.M untouched
8972 * + allow changes to the other CPSR fields
8973 * + set PSTATE.IL
8974 * For user changes via the GDB stub, we don't set PSTATE.IL,
8975 * as this would be unnecessarily harsh for a user error.
8977 mask &= ~CPSR_M;
8978 if (write_type != CPSRWriteByGDBStub &&
8979 arm_feature(env, ARM_FEATURE_V8)) {
8980 mask |= CPSR_IL;
8981 val |= CPSR_IL;
8983 qemu_log_mask(LOG_GUEST_ERROR,
8984 "Illegal AArch32 mode switch attempt from %s to %s\n",
8985 aarch32_mode_name(env->uncached_cpsr),
8986 aarch32_mode_name(val));
8987 } else {
8988 qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
8989 write_type == CPSRWriteExceptionReturn ?
8990 "Exception return from AArch32" :
8991 "AArch32 mode switch from",
8992 aarch32_mode_name(env->uncached_cpsr),
8993 aarch32_mode_name(val), env->regs[15]);
8994 switch_mode(env, val & CPSR_M);
8997 mask &= ~CACHED_CPSR_BITS;
8998 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
9001 /* Sign/zero extend */
9002 uint32_t HELPER(sxtb16)(uint32_t x)
9004 uint32_t res;
9005 res = (uint16_t)(int8_t)x;
9006 res |= (uint32_t)(int8_t)(x >> 16) << 16;
9007 return res;
9010 uint32_t HELPER(uxtb16)(uint32_t x)
9012 uint32_t res;
9013 res = (uint16_t)(uint8_t)x;
9014 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
9015 return res;
9018 int32_t HELPER(sdiv)(int32_t num, int32_t den)
9020 if (den == 0)
9021 return 0;
9022 if (num == INT_MIN && den == -1)
9023 return INT_MIN;
9024 return num / den;
9027 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
9029 if (den == 0)
9030 return 0;
9031 return num / den;
9034 uint32_t HELPER(rbit)(uint32_t x)
9036 return revbit32(x);
9039 #ifdef CONFIG_USER_ONLY
9041 static void switch_mode(CPUARMState *env, int mode)
9043 ARMCPU *cpu = env_archcpu(env);
9045 if (mode != ARM_CPU_MODE_USR) {
9046 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
9050 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
9051 uint32_t cur_el, bool secure)
9053 return 1;
9056 void aarch64_sync_64_to_32(CPUARMState *env)
9058 g_assert_not_reached();
9061 #else
9063 static void switch_mode(CPUARMState *env, int mode)
9065 int old_mode;
9066 int i;
9068 old_mode = env->uncached_cpsr & CPSR_M;
9069 if (mode == old_mode)
9070 return;
9072 if (old_mode == ARM_CPU_MODE_FIQ) {
9073 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
9074 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
9075 } else if (mode == ARM_CPU_MODE_FIQ) {
9076 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
9077 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
9080 i = bank_number(old_mode);
9081 env->banked_r13[i] = env->regs[13];
9082 env->banked_spsr[i] = env->spsr;
9084 i = bank_number(mode);
9085 env->regs[13] = env->banked_r13[i];
9086 env->spsr = env->banked_spsr[i];
9088 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14];
9089 env->regs[14] = env->banked_r14[r14_bank_number(mode)];
9092 /* Physical Interrupt Target EL Lookup Table
9094 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9096 * The below multi-dimensional table is used for looking up the target
9097 * exception level given numerous condition criteria. Specifically, the
9098 * target EL is based on SCR and HCR routing controls as well as the
9099 * currently executing EL and secure state.
9101 * Dimensions:
9102 * target_el_table[2][2][2][2][2][4]
9103 * | | | | | +--- Current EL
9104 * | | | | +------ Non-secure(0)/Secure(1)
9105 * | | | +--------- HCR mask override
9106 * | | +------------ SCR exec state control
9107 * | +--------------- SCR mask override
9108 * +------------------ 32-bit(0)/64-bit(1) EL3
9110 * The table values are as such:
9111 * 0-3 = EL0-EL3
9112 * -1 = Cannot occur
9114 * The ARM ARM target EL table includes entries indicating that an "exception
9115 * is not taken". The two cases where this is applicable are:
9116 * 1) An exception is taken from EL3 but the SCR does not have the exception
9117 * routed to EL3.
9118 * 2) An exception is taken from EL2 but the HCR does not have the exception
9119 * routed to EL2.
9120 * In these two cases, the below table contain a target of EL1. This value is
9121 * returned as it is expected that the consumer of the table data will check
9122 * for "target EL >= current EL" to ensure the exception is not taken.
9124 * SCR HCR
9125 * 64 EA AMO From
9126 * BIT IRQ IMO Non-secure Secure
9127 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9129 static const int8_t target_el_table[2][2][2][2][2][4] = {
9130 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9131 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9132 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9133 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9134 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9135 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9136 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9137 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9138 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9139 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9140 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9141 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9142 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9143 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9144 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9145 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9149 * Determine the target EL for physical exceptions
9151 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
9152 uint32_t cur_el, bool secure)
9154 CPUARMState *env = cs->env_ptr;
9155 bool rw;
9156 bool scr;
9157 bool hcr;
9158 int target_el;
9159 /* Is the highest EL AArch64? */
9160 bool is64 = arm_feature(env, ARM_FEATURE_AARCH64);
9161 uint64_t hcr_el2;
9163 if (arm_feature(env, ARM_FEATURE_EL3)) {
9164 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
9165 } else {
9166 /* Either EL2 is the highest EL (and so the EL2 register width
9167 * is given by is64); or there is no EL2 or EL3, in which case
9168 * the value of 'rw' does not affect the table lookup anyway.
9170 rw = is64;
9173 hcr_el2 = arm_hcr_el2_eff(env);
9174 switch (excp_idx) {
9175 case EXCP_IRQ:
9176 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
9177 hcr = hcr_el2 & HCR_IMO;
9178 break;
9179 case EXCP_FIQ:
9180 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
9181 hcr = hcr_el2 & HCR_FMO;
9182 break;
9183 default:
9184 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
9185 hcr = hcr_el2 & HCR_AMO;
9186 break;
9190 * For these purposes, TGE and AMO/IMO/FMO both force the
9191 * interrupt to EL2. Fold TGE into the bit extracted above.
9193 hcr |= (hcr_el2 & HCR_TGE) != 0;
9195 /* Perform a table-lookup for the target EL given the current state */
9196 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
9198 assert(target_el > 0);
9200 return target_el;
9203 void arm_log_exception(int idx)
9205 if (qemu_loglevel_mask(CPU_LOG_INT)) {
9206 const char *exc = NULL;
9207 static const char * const excnames[] = {
9208 [EXCP_UDEF] = "Undefined Instruction",
9209 [EXCP_SWI] = "SVC",
9210 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
9211 [EXCP_DATA_ABORT] = "Data Abort",
9212 [EXCP_IRQ] = "IRQ",
9213 [EXCP_FIQ] = "FIQ",
9214 [EXCP_BKPT] = "Breakpoint",
9215 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
9216 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
9217 [EXCP_HVC] = "Hypervisor Call",
9218 [EXCP_HYP_TRAP] = "Hypervisor Trap",
9219 [EXCP_SMC] = "Secure Monitor Call",
9220 [EXCP_VIRQ] = "Virtual IRQ",
9221 [EXCP_VFIQ] = "Virtual FIQ",
9222 [EXCP_SEMIHOST] = "Semihosting call",
9223 [EXCP_NOCP] = "v7M NOCP UsageFault",
9224 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
9225 [EXCP_STKOF] = "v8M STKOF UsageFault",
9226 [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
9227 [EXCP_LSERR] = "v8M LSERR UsageFault",
9228 [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
9231 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
9232 exc = excnames[idx];
9234 if (!exc) {
9235 exc = "unknown";
9237 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
9242 * Function used to synchronize QEMU's AArch64 register set with AArch32
9243 * register set. This is necessary when switching between AArch32 and AArch64
9244 * execution state.
9246 void aarch64_sync_32_to_64(CPUARMState *env)
9248 int i;
9249 uint32_t mode = env->uncached_cpsr & CPSR_M;
9251 /* We can blanket copy R[0:7] to X[0:7] */
9252 for (i = 0; i < 8; i++) {
9253 env->xregs[i] = env->regs[i];
9257 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9258 * Otherwise, they come from the banked user regs.
9260 if (mode == ARM_CPU_MODE_FIQ) {
9261 for (i = 8; i < 13; i++) {
9262 env->xregs[i] = env->usr_regs[i - 8];
9264 } else {
9265 for (i = 8; i < 13; i++) {
9266 env->xregs[i] = env->regs[i];
9271 * Registers x13-x23 are the various mode SP and FP registers. Registers
9272 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9273 * from the mode banked register.
9275 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
9276 env->xregs[13] = env->regs[13];
9277 env->xregs[14] = env->regs[14];
9278 } else {
9279 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
9280 /* HYP is an exception in that it is copied from r14 */
9281 if (mode == ARM_CPU_MODE_HYP) {
9282 env->xregs[14] = env->regs[14];
9283 } else {
9284 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
9288 if (mode == ARM_CPU_MODE_HYP) {
9289 env->xregs[15] = env->regs[13];
9290 } else {
9291 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
9294 if (mode == ARM_CPU_MODE_IRQ) {
9295 env->xregs[16] = env->regs[14];
9296 env->xregs[17] = env->regs[13];
9297 } else {
9298 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
9299 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
9302 if (mode == ARM_CPU_MODE_SVC) {
9303 env->xregs[18] = env->regs[14];
9304 env->xregs[19] = env->regs[13];
9305 } else {
9306 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
9307 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
9310 if (mode == ARM_CPU_MODE_ABT) {
9311 env->xregs[20] = env->regs[14];
9312 env->xregs[21] = env->regs[13];
9313 } else {
9314 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
9315 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
9318 if (mode == ARM_CPU_MODE_UND) {
9319 env->xregs[22] = env->regs[14];
9320 env->xregs[23] = env->regs[13];
9321 } else {
9322 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
9323 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
9327 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9328 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9329 * FIQ bank for r8-r14.
9331 if (mode == ARM_CPU_MODE_FIQ) {
9332 for (i = 24; i < 31; i++) {
9333 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
9335 } else {
9336 for (i = 24; i < 29; i++) {
9337 env->xregs[i] = env->fiq_regs[i - 24];
9339 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
9340 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
9343 env->pc = env->regs[15];
9347 * Function used to synchronize QEMU's AArch32 register set with AArch64
9348 * register set. This is necessary when switching between AArch32 and AArch64
9349 * execution state.
9351 void aarch64_sync_64_to_32(CPUARMState *env)
9353 int i;
9354 uint32_t mode = env->uncached_cpsr & CPSR_M;
9356 /* We can blanket copy X[0:7] to R[0:7] */
9357 for (i = 0; i < 8; i++) {
9358 env->regs[i] = env->xregs[i];
9362 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9363 * Otherwise, we copy x8-x12 into the banked user regs.
9365 if (mode == ARM_CPU_MODE_FIQ) {
9366 for (i = 8; i < 13; i++) {
9367 env->usr_regs[i - 8] = env->xregs[i];
9369 } else {
9370 for (i = 8; i < 13; i++) {
9371 env->regs[i] = env->xregs[i];
9376 * Registers r13 & r14 depend on the current mode.
9377 * If we are in a given mode, we copy the corresponding x registers to r13
9378 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9379 * for the mode.
9381 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
9382 env->regs[13] = env->xregs[13];
9383 env->regs[14] = env->xregs[14];
9384 } else {
9385 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
9388 * HYP is an exception in that it does not have its own banked r14 but
9389 * shares the USR r14
9391 if (mode == ARM_CPU_MODE_HYP) {
9392 env->regs[14] = env->xregs[14];
9393 } else {
9394 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
9398 if (mode == ARM_CPU_MODE_HYP) {
9399 env->regs[13] = env->xregs[15];
9400 } else {
9401 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
9404 if (mode == ARM_CPU_MODE_IRQ) {
9405 env->regs[14] = env->xregs[16];
9406 env->regs[13] = env->xregs[17];
9407 } else {
9408 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
9409 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
9412 if (mode == ARM_CPU_MODE_SVC) {
9413 env->regs[14] = env->xregs[18];
9414 env->regs[13] = env->xregs[19];
9415 } else {
9416 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
9417 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
9420 if (mode == ARM_CPU_MODE_ABT) {
9421 env->regs[14] = env->xregs[20];
9422 env->regs[13] = env->xregs[21];
9423 } else {
9424 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
9425 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
9428 if (mode == ARM_CPU_MODE_UND) {
9429 env->regs[14] = env->xregs[22];
9430 env->regs[13] = env->xregs[23];
9431 } else {
9432 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
9433 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
9436 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9437 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9438 * FIQ bank for r8-r14.
9440 if (mode == ARM_CPU_MODE_FIQ) {
9441 for (i = 24; i < 31; i++) {
9442 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
9444 } else {
9445 for (i = 24; i < 29; i++) {
9446 env->fiq_regs[i - 24] = env->xregs[i];
9448 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
9449 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
9452 env->regs[15] = env->pc;
9455 static void take_aarch32_exception(CPUARMState *env, int new_mode,
9456 uint32_t mask, uint32_t offset,
9457 uint32_t newpc)
9459 int new_el;
9461 /* Change the CPU state so as to actually take the exception. */
9462 switch_mode(env, new_mode);
9465 * For exceptions taken to AArch32 we must clear the SS bit in both
9466 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9468 env->pstate &= ~PSTATE_SS;
9469 env->spsr = cpsr_read(env);
9470 /* Clear IT bits. */
9471 env->condexec_bits = 0;
9472 /* Switch to the new mode, and to the correct instruction set. */
9473 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
9475 /* This must be after mode switching. */
9476 new_el = arm_current_el(env);
9478 /* Set new mode endianness */
9479 env->uncached_cpsr &= ~CPSR_E;
9480 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
9481 env->uncached_cpsr |= CPSR_E;
9483 /* J and IL must always be cleared for exception entry */
9484 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
9485 env->daif |= mask;
9487 if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
9488 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
9489 env->uncached_cpsr |= CPSR_SSBS;
9490 } else {
9491 env->uncached_cpsr &= ~CPSR_SSBS;
9495 if (new_mode == ARM_CPU_MODE_HYP) {
9496 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
9497 env->elr_el[2] = env->regs[15];
9498 } else {
9499 /* CPSR.PAN is normally preserved preserved unless... */
9500 if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
9501 switch (new_el) {
9502 case 3:
9503 if (!arm_is_secure_below_el3(env)) {
9504 /* ... the target is EL3, from non-secure state. */
9505 env->uncached_cpsr &= ~CPSR_PAN;
9506 break;
9508 /* ... the target is EL3, from secure state ... */
9509 /* fall through */
9510 case 1:
9511 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9512 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) {
9513 env->uncached_cpsr |= CPSR_PAN;
9515 break;
9519 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9520 * and we should just guard the thumb mode on V4
9522 if (arm_feature(env, ARM_FEATURE_V4T)) {
9523 env->thumb =
9524 (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
9526 env->regs[14] = env->regs[15] + offset;
9528 env->regs[15] = newpc;
9529 arm_rebuild_hflags(env);
9532 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
9535 * Handle exception entry to Hyp mode; this is sufficiently
9536 * different to entry to other AArch32 modes that we handle it
9537 * separately here.
9539 * The vector table entry used is always the 0x14 Hyp mode entry point,
9540 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9541 * The offset applied to the preferred return address is always zero
9542 * (see DDI0487C.a section G1.12.3).
9543 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9545 uint32_t addr, mask;
9546 ARMCPU *cpu = ARM_CPU(cs);
9547 CPUARMState *env = &cpu->env;
9549 switch (cs->exception_index) {
9550 case EXCP_UDEF:
9551 addr = 0x04;
9552 break;
9553 case EXCP_SWI:
9554 addr = 0x14;
9555 break;
9556 case EXCP_BKPT:
9557 /* Fall through to prefetch abort. */
9558 case EXCP_PREFETCH_ABORT:
9559 env->cp15.ifar_s = env->exception.vaddress;
9560 qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n",
9561 (uint32_t)env->exception.vaddress);
9562 addr = 0x0c;
9563 break;
9564 case EXCP_DATA_ABORT:
9565 env->cp15.dfar_s = env->exception.vaddress;
9566 qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n",
9567 (uint32_t)env->exception.vaddress);
9568 addr = 0x10;
9569 break;
9570 case EXCP_IRQ:
9571 addr = 0x18;
9572 break;
9573 case EXCP_FIQ:
9574 addr = 0x1c;
9575 break;
9576 case EXCP_HVC:
9577 addr = 0x08;
9578 break;
9579 case EXCP_HYP_TRAP:
9580 addr = 0x14;
9581 break;
9582 default:
9583 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9586 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
9587 if (!arm_feature(env, ARM_FEATURE_V8)) {
9589 * QEMU syndrome values are v8-style. v7 has the IL bit
9590 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9591 * If this is a v7 CPU, squash the IL bit in those cases.
9593 if (cs->exception_index == EXCP_PREFETCH_ABORT ||
9594 (cs->exception_index == EXCP_DATA_ABORT &&
9595 !(env->exception.syndrome & ARM_EL_ISV)) ||
9596 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) {
9597 env->exception.syndrome &= ~ARM_EL_IL;
9600 env->cp15.esr_el[2] = env->exception.syndrome;
9603 if (arm_current_el(env) != 2 && addr < 0x14) {
9604 addr = 0x14;
9607 mask = 0;
9608 if (!(env->cp15.scr_el3 & SCR_EA)) {
9609 mask |= CPSR_A;
9611 if (!(env->cp15.scr_el3 & SCR_IRQ)) {
9612 mask |= CPSR_I;
9614 if (!(env->cp15.scr_el3 & SCR_FIQ)) {
9615 mask |= CPSR_F;
9618 addr += env->cp15.hvbar;
9620 take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr);
9623 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
9625 ARMCPU *cpu = ARM_CPU(cs);
9626 CPUARMState *env = &cpu->env;
9627 uint32_t addr;
9628 uint32_t mask;
9629 int new_mode;
9630 uint32_t offset;
9631 uint32_t moe;
9633 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9634 switch (syn_get_ec(env->exception.syndrome)) {
9635 case EC_BREAKPOINT:
9636 case EC_BREAKPOINT_SAME_EL:
9637 moe = 1;
9638 break;
9639 case EC_WATCHPOINT:
9640 case EC_WATCHPOINT_SAME_EL:
9641 moe = 10;
9642 break;
9643 case EC_AA32_BKPT:
9644 moe = 3;
9645 break;
9646 case EC_VECTORCATCH:
9647 moe = 5;
9648 break;
9649 default:
9650 moe = 0;
9651 break;
9654 if (moe) {
9655 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
9658 if (env->exception.target_el == 2) {
9659 arm_cpu_do_interrupt_aarch32_hyp(cs);
9660 return;
9663 switch (cs->exception_index) {
9664 case EXCP_UDEF:
9665 new_mode = ARM_CPU_MODE_UND;
9666 addr = 0x04;
9667 mask = CPSR_I;
9668 if (env->thumb)
9669 offset = 2;
9670 else
9671 offset = 4;
9672 break;
9673 case EXCP_SWI:
9674 new_mode = ARM_CPU_MODE_SVC;
9675 addr = 0x08;
9676 mask = CPSR_I;
9677 /* The PC already points to the next instruction. */
9678 offset = 0;
9679 break;
9680 case EXCP_BKPT:
9681 /* Fall through to prefetch abort. */
9682 case EXCP_PREFETCH_ABORT:
9683 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
9684 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
9685 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
9686 env->exception.fsr, (uint32_t)env->exception.vaddress);
9687 new_mode = ARM_CPU_MODE_ABT;
9688 addr = 0x0c;
9689 mask = CPSR_A | CPSR_I;
9690 offset = 4;
9691 break;
9692 case EXCP_DATA_ABORT:
9693 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
9694 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
9695 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
9696 env->exception.fsr,
9697 (uint32_t)env->exception.vaddress);
9698 new_mode = ARM_CPU_MODE_ABT;
9699 addr = 0x10;
9700 mask = CPSR_A | CPSR_I;
9701 offset = 8;
9702 break;
9703 case EXCP_IRQ:
9704 new_mode = ARM_CPU_MODE_IRQ;
9705 addr = 0x18;
9706 /* Disable IRQ and imprecise data aborts. */
9707 mask = CPSR_A | CPSR_I;
9708 offset = 4;
9709 if (env->cp15.scr_el3 & SCR_IRQ) {
9710 /* IRQ routed to monitor mode */
9711 new_mode = ARM_CPU_MODE_MON;
9712 mask |= CPSR_F;
9714 break;
9715 case EXCP_FIQ:
9716 new_mode = ARM_CPU_MODE_FIQ;
9717 addr = 0x1c;
9718 /* Disable FIQ, IRQ and imprecise data aborts. */
9719 mask = CPSR_A | CPSR_I | CPSR_F;
9720 if (env->cp15.scr_el3 & SCR_FIQ) {
9721 /* FIQ routed to monitor mode */
9722 new_mode = ARM_CPU_MODE_MON;
9724 offset = 4;
9725 break;
9726 case EXCP_VIRQ:
9727 new_mode = ARM_CPU_MODE_IRQ;
9728 addr = 0x18;
9729 /* Disable IRQ and imprecise data aborts. */
9730 mask = CPSR_A | CPSR_I;
9731 offset = 4;
9732 break;
9733 case EXCP_VFIQ:
9734 new_mode = ARM_CPU_MODE_FIQ;
9735 addr = 0x1c;
9736 /* Disable FIQ, IRQ and imprecise data aborts. */
9737 mask = CPSR_A | CPSR_I | CPSR_F;
9738 offset = 4;
9739 break;
9740 case EXCP_SMC:
9741 new_mode = ARM_CPU_MODE_MON;
9742 addr = 0x08;
9743 mask = CPSR_A | CPSR_I | CPSR_F;
9744 offset = 0;
9745 break;
9746 default:
9747 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9748 return; /* Never happens. Keep compiler happy. */
9751 if (new_mode == ARM_CPU_MODE_MON) {
9752 addr += env->cp15.mvbar;
9753 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
9754 /* High vectors. When enabled, base address cannot be remapped. */
9755 addr += 0xffff0000;
9756 } else {
9757 /* ARM v7 architectures provide a vector base address register to remap
9758 * the interrupt vector table.
9759 * This register is only followed in non-monitor mode, and is banked.
9760 * Note: only bits 31:5 are valid.
9762 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
9765 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
9766 env->cp15.scr_el3 &= ~SCR_NS;
9769 take_aarch32_exception(env, new_mode, mask, offset, addr);
9772 static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
9775 * Return the register number of the AArch64 view of the AArch32
9776 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9777 * be that of the AArch32 mode the exception came from.
9779 int mode = env->uncached_cpsr & CPSR_M;
9781 switch (aarch32_reg) {
9782 case 0 ... 7:
9783 return aarch32_reg;
9784 case 8 ... 12:
9785 return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg;
9786 case 13:
9787 switch (mode) {
9788 case ARM_CPU_MODE_USR:
9789 case ARM_CPU_MODE_SYS:
9790 return 13;
9791 case ARM_CPU_MODE_HYP:
9792 return 15;
9793 case ARM_CPU_MODE_IRQ:
9794 return 17;
9795 case ARM_CPU_MODE_SVC:
9796 return 19;
9797 case ARM_CPU_MODE_ABT:
9798 return 21;
9799 case ARM_CPU_MODE_UND:
9800 return 23;
9801 case ARM_CPU_MODE_FIQ:
9802 return 29;
9803 default:
9804 g_assert_not_reached();
9806 case 14:
9807 switch (mode) {
9808 case ARM_CPU_MODE_USR:
9809 case ARM_CPU_MODE_SYS:
9810 case ARM_CPU_MODE_HYP:
9811 return 14;
9812 case ARM_CPU_MODE_IRQ:
9813 return 16;
9814 case ARM_CPU_MODE_SVC:
9815 return 18;
9816 case ARM_CPU_MODE_ABT:
9817 return 20;
9818 case ARM_CPU_MODE_UND:
9819 return 22;
9820 case ARM_CPU_MODE_FIQ:
9821 return 30;
9822 default:
9823 g_assert_not_reached();
9825 case 15:
9826 return 31;
9827 default:
9828 g_assert_not_reached();
9832 static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
9834 uint32_t ret = cpsr_read(env);
9836 /* Move DIT to the correct location for SPSR_ELx */
9837 if (ret & CPSR_DIT) {
9838 ret &= ~CPSR_DIT;
9839 ret |= PSTATE_DIT;
9841 /* Merge PSTATE.SS into SPSR_ELx */
9842 ret |= env->pstate & PSTATE_SS;
9844 return ret;
9847 /* Handle exception entry to a target EL which is using AArch64 */
9848 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
9850 ARMCPU *cpu = ARM_CPU(cs);
9851 CPUARMState *env = &cpu->env;
9852 unsigned int new_el = env->exception.target_el;
9853 target_ulong addr = env->cp15.vbar_el[new_el];
9854 unsigned int new_mode = aarch64_pstate_mode(new_el, true);
9855 unsigned int old_mode;
9856 unsigned int cur_el = arm_current_el(env);
9857 int rt;
9860 * Note that new_el can never be 0. If cur_el is 0, then
9861 * el0_a64 is is_a64(), else el0_a64 is ignored.
9863 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
9865 if (cur_el < new_el) {
9866 /* Entry vector offset depends on whether the implemented EL
9867 * immediately lower than the target level is using AArch32 or AArch64
9869 bool is_aa64;
9870 uint64_t hcr;
9872 switch (new_el) {
9873 case 3:
9874 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
9875 break;
9876 case 2:
9877 hcr = arm_hcr_el2_eff(env);
9878 if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
9879 is_aa64 = (hcr & HCR_RW) != 0;
9880 break;
9882 /* fall through */
9883 case 1:
9884 is_aa64 = is_a64(env);
9885 break;
9886 default:
9887 g_assert_not_reached();
9890 if (is_aa64) {
9891 addr += 0x400;
9892 } else {
9893 addr += 0x600;
9895 } else if (pstate_read(env) & PSTATE_SP) {
9896 addr += 0x200;
9899 switch (cs->exception_index) {
9900 case EXCP_PREFETCH_ABORT:
9901 case EXCP_DATA_ABORT:
9902 env->cp15.far_el[new_el] = env->exception.vaddress;
9903 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
9904 env->cp15.far_el[new_el]);
9905 /* fall through */
9906 case EXCP_BKPT:
9907 case EXCP_UDEF:
9908 case EXCP_SWI:
9909 case EXCP_HVC:
9910 case EXCP_HYP_TRAP:
9911 case EXCP_SMC:
9912 switch (syn_get_ec(env->exception.syndrome)) {
9913 case EC_ADVSIMDFPACCESSTRAP:
9915 * QEMU internal FP/SIMD syndromes from AArch32 include the
9916 * TA and coproc fields which are only exposed if the exception
9917 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9918 * AArch64 format syndrome.
9920 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20);
9921 break;
9922 case EC_CP14RTTRAP:
9923 case EC_CP15RTTRAP:
9924 case EC_CP14DTTRAP:
9926 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
9927 * the raw register field from the insn; when taking this to
9928 * AArch64 we must convert it to the AArch64 view of the register
9929 * number. Notice that we read a 4-bit AArch32 register number and
9930 * write back a 5-bit AArch64 one.
9932 rt = extract32(env->exception.syndrome, 5, 4);
9933 rt = aarch64_regnum(env, rt);
9934 env->exception.syndrome = deposit32(env->exception.syndrome,
9935 5, 5, rt);
9936 break;
9937 case EC_CP15RRTTRAP:
9938 case EC_CP14RRTTRAP:
9939 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
9940 rt = extract32(env->exception.syndrome, 5, 4);
9941 rt = aarch64_regnum(env, rt);
9942 env->exception.syndrome = deposit32(env->exception.syndrome,
9943 5, 5, rt);
9944 rt = extract32(env->exception.syndrome, 10, 4);
9945 rt = aarch64_regnum(env, rt);
9946 env->exception.syndrome = deposit32(env->exception.syndrome,
9947 10, 5, rt);
9948 break;
9950 env->cp15.esr_el[new_el] = env->exception.syndrome;
9951 break;
9952 case EXCP_IRQ:
9953 case EXCP_VIRQ:
9954 addr += 0x80;
9955 break;
9956 case EXCP_FIQ:
9957 case EXCP_VFIQ:
9958 addr += 0x100;
9959 break;
9960 default:
9961 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9964 if (is_a64(env)) {
9965 old_mode = pstate_read(env);
9966 aarch64_save_sp(env, arm_current_el(env));
9967 env->elr_el[new_el] = env->pc;
9968 } else {
9969 old_mode = cpsr_read_for_spsr_elx(env);
9970 env->elr_el[new_el] = env->regs[15];
9972 aarch64_sync_32_to_64(env);
9974 env->condexec_bits = 0;
9976 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
9978 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
9979 env->elr_el[new_el]);
9981 if (cpu_isar_feature(aa64_pan, cpu)) {
9982 /* The value of PSTATE.PAN is normally preserved, except when ... */
9983 new_mode |= old_mode & PSTATE_PAN;
9984 switch (new_el) {
9985 case 2:
9986 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9987 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE))
9988 != (HCR_E2H | HCR_TGE)) {
9989 break;
9991 /* fall through */
9992 case 1:
9993 /* ... the target is EL1 ... */
9994 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9995 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) {
9996 new_mode |= PSTATE_PAN;
9998 break;
10001 if (cpu_isar_feature(aa64_mte, cpu)) {
10002 new_mode |= PSTATE_TCO;
10005 if (cpu_isar_feature(aa64_ssbs, cpu)) {
10006 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
10007 new_mode |= PSTATE_SSBS;
10008 } else {
10009 new_mode &= ~PSTATE_SSBS;
10013 pstate_write(env, PSTATE_DAIF | new_mode);
10014 env->aarch64 = 1;
10015 aarch64_restore_sp(env, new_el);
10016 helper_rebuild_hflags_a64(env, new_el);
10018 env->pc = addr;
10020 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
10021 new_el, env->pc, pstate_read(env));
10025 * Do semihosting call and set the appropriate return value. All the
10026 * permission and validity checks have been done at translate time.
10028 * We only see semihosting exceptions in TCG only as they are not
10029 * trapped to the hypervisor in KVM.
10031 #ifdef CONFIG_TCG
10032 static void handle_semihosting(CPUState *cs)
10034 ARMCPU *cpu = ARM_CPU(cs);
10035 CPUARMState *env = &cpu->env;
10037 if (is_a64(env)) {
10038 qemu_log_mask(CPU_LOG_INT,
10039 "...handling as semihosting call 0x%" PRIx64 "\n",
10040 env->xregs[0]);
10041 env->xregs[0] = do_common_semihosting(cs);
10042 env->pc += 4;
10043 } else {
10044 qemu_log_mask(CPU_LOG_INT,
10045 "...handling as semihosting call 0x%x\n",
10046 env->regs[0]);
10047 env->regs[0] = do_common_semihosting(cs);
10048 env->regs[15] += env->thumb ? 2 : 4;
10051 #endif
10053 /* Handle a CPU exception for A and R profile CPUs.
10054 * Do any appropriate logging, handle PSCI calls, and then hand off
10055 * to the AArch64-entry or AArch32-entry function depending on the
10056 * target exception level's register width.
10058 * Note: this is used for both TCG (as the do_interrupt tcg op),
10059 * and KVM to re-inject guest debug exceptions, and to
10060 * inject a Synchronous-External-Abort.
10062 void arm_cpu_do_interrupt(CPUState *cs)
10064 ARMCPU *cpu = ARM_CPU(cs);
10065 CPUARMState *env = &cpu->env;
10066 unsigned int new_el = env->exception.target_el;
10068 assert(!arm_feature(env, ARM_FEATURE_M));
10070 arm_log_exception(cs->exception_index);
10071 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
10072 new_el);
10073 if (qemu_loglevel_mask(CPU_LOG_INT)
10074 && !excp_is_internal(cs->exception_index)) {
10075 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
10076 syn_get_ec(env->exception.syndrome),
10077 env->exception.syndrome);
10080 if (arm_is_psci_call(cpu, cs->exception_index)) {
10081 arm_handle_psci_call(cpu);
10082 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
10083 return;
10087 * Semihosting semantics depend on the register width of the code
10088 * that caused the exception, not the target exception level, so
10089 * must be handled here.
10091 #ifdef CONFIG_TCG
10092 if (cs->exception_index == EXCP_SEMIHOST) {
10093 handle_semihosting(cs);
10094 return;
10096 #endif
10098 /* Hooks may change global state so BQL should be held, also the
10099 * BQL needs to be held for any modification of
10100 * cs->interrupt_request.
10102 g_assert(qemu_mutex_iothread_locked());
10104 arm_call_pre_el_change_hook(cpu);
10106 assert(!excp_is_internal(cs->exception_index));
10107 if (arm_el_is_aa64(env, new_el)) {
10108 arm_cpu_do_interrupt_aarch64(cs);
10109 } else {
10110 arm_cpu_do_interrupt_aarch32(cs);
10113 arm_call_el_change_hook(cpu);
10115 if (!kvm_enabled()) {
10116 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
10119 #endif /* !CONFIG_USER_ONLY */
10121 uint64_t arm_sctlr(CPUARMState *env, int el)
10123 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10124 if (el == 0) {
10125 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
10126 el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0)
10127 ? 2 : 1;
10129 return env->cp15.sctlr_el[el];
10132 /* Return the SCTLR value which controls this address translation regime */
10133 static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
10135 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
10138 #ifndef CONFIG_USER_ONLY
10140 /* Return true if the specified stage of address translation is disabled */
10141 static inline bool regime_translation_disabled(CPUARMState *env,
10142 ARMMMUIdx mmu_idx)
10144 uint64_t hcr_el2;
10146 if (arm_feature(env, ARM_FEATURE_M)) {
10147 switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
10148 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
10149 case R_V7M_MPU_CTRL_ENABLE_MASK:
10150 /* Enabled, but not for HardFault and NMI */
10151 return mmu_idx & ARM_MMU_IDX_M_NEGPRI;
10152 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
10153 /* Enabled for all cases */
10154 return false;
10155 case 0:
10156 default:
10157 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
10158 * we warned about that in armv7m_nvic.c when the guest set it.
10160 return true;
10164 hcr_el2 = arm_hcr_el2_eff(env);
10166 if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
10167 /* HCR.DC means HCR.VM behaves as 1 */
10168 return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
10171 if (hcr_el2 & HCR_TGE) {
10172 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10173 if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
10174 return true;
10178 if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
10179 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10180 return true;
10183 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
10186 static inline bool regime_translation_big_endian(CPUARMState *env,
10187 ARMMMUIdx mmu_idx)
10189 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
10192 /* Return the TTBR associated with this translation regime */
10193 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
10194 int ttbrn)
10196 if (mmu_idx == ARMMMUIdx_Stage2) {
10197 return env->cp15.vttbr_el2;
10199 if (mmu_idx == ARMMMUIdx_Stage2_S) {
10200 return env->cp15.vsttbr_el2;
10202 if (ttbrn == 0) {
10203 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
10204 } else {
10205 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
10209 #endif /* !CONFIG_USER_ONLY */
10211 /* Convert a possible stage1+2 MMU index into the appropriate
10212 * stage 1 MMU index
10214 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
10216 switch (mmu_idx) {
10217 case ARMMMUIdx_SE10_0:
10218 return ARMMMUIdx_Stage1_SE0;
10219 case ARMMMUIdx_SE10_1:
10220 return ARMMMUIdx_Stage1_SE1;
10221 case ARMMMUIdx_SE10_1_PAN:
10222 return ARMMMUIdx_Stage1_SE1_PAN;
10223 case ARMMMUIdx_E10_0:
10224 return ARMMMUIdx_Stage1_E0;
10225 case ARMMMUIdx_E10_1:
10226 return ARMMMUIdx_Stage1_E1;
10227 case ARMMMUIdx_E10_1_PAN:
10228 return ARMMMUIdx_Stage1_E1_PAN;
10229 default:
10230 return mmu_idx;
10234 /* Return true if the translation regime is using LPAE format page tables */
10235 static inline bool regime_using_lpae_format(CPUARMState *env,
10236 ARMMMUIdx mmu_idx)
10238 int el = regime_el(env, mmu_idx);
10239 if (el == 2 || arm_el_is_aa64(env, el)) {
10240 return true;
10242 if (arm_feature(env, ARM_FEATURE_LPAE)
10243 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
10244 return true;
10246 return false;
10249 /* Returns true if the stage 1 translation regime is using LPAE format page
10250 * tables. Used when raising alignment exceptions, whose FSR changes depending
10251 * on whether the long or short descriptor format is in use. */
10252 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
10254 mmu_idx = stage_1_mmu_idx(mmu_idx);
10256 return regime_using_lpae_format(env, mmu_idx);
10259 #ifndef CONFIG_USER_ONLY
10260 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
10262 switch (mmu_idx) {
10263 case ARMMMUIdx_SE10_0:
10264 case ARMMMUIdx_E20_0:
10265 case ARMMMUIdx_SE20_0:
10266 case ARMMMUIdx_Stage1_E0:
10267 case ARMMMUIdx_Stage1_SE0:
10268 case ARMMMUIdx_MUser:
10269 case ARMMMUIdx_MSUser:
10270 case ARMMMUIdx_MUserNegPri:
10271 case ARMMMUIdx_MSUserNegPri:
10272 return true;
10273 default:
10274 return false;
10275 case ARMMMUIdx_E10_0:
10276 case ARMMMUIdx_E10_1:
10277 case ARMMMUIdx_E10_1_PAN:
10278 g_assert_not_reached();
10282 /* Translate section/page access permissions to page
10283 * R/W protection flags
10285 * @env: CPUARMState
10286 * @mmu_idx: MMU index indicating required translation regime
10287 * @ap: The 3-bit access permissions (AP[2:0])
10288 * @domain_prot: The 2-bit domain access permissions
10290 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
10291 int ap, int domain_prot)
10293 bool is_user = regime_is_user(env, mmu_idx);
10295 if (domain_prot == 3) {
10296 return PAGE_READ | PAGE_WRITE;
10299 switch (ap) {
10300 case 0:
10301 if (arm_feature(env, ARM_FEATURE_V7)) {
10302 return 0;
10304 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
10305 case SCTLR_S:
10306 return is_user ? 0 : PAGE_READ;
10307 case SCTLR_R:
10308 return PAGE_READ;
10309 default:
10310 return 0;
10312 case 1:
10313 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
10314 case 2:
10315 if (is_user) {
10316 return PAGE_READ;
10317 } else {
10318 return PAGE_READ | PAGE_WRITE;
10320 case 3:
10321 return PAGE_READ | PAGE_WRITE;
10322 case 4: /* Reserved. */
10323 return 0;
10324 case 5:
10325 return is_user ? 0 : PAGE_READ;
10326 case 6:
10327 return PAGE_READ;
10328 case 7:
10329 if (!arm_feature(env, ARM_FEATURE_V6K)) {
10330 return 0;
10332 return PAGE_READ;
10333 default:
10334 g_assert_not_reached();
10338 /* Translate section/page access permissions to page
10339 * R/W protection flags.
10341 * @ap: The 2-bit simple AP (AP[2:1])
10342 * @is_user: TRUE if accessing from PL0
10344 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
10346 switch (ap) {
10347 case 0:
10348 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
10349 case 1:
10350 return PAGE_READ | PAGE_WRITE;
10351 case 2:
10352 return is_user ? 0 : PAGE_READ;
10353 case 3:
10354 return PAGE_READ;
10355 default:
10356 g_assert_not_reached();
10360 static inline int
10361 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
10363 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
10366 /* Translate S2 section/page access permissions to protection flags
10368 * @env: CPUARMState
10369 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10370 * @xn: XN (execute-never) bits
10371 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
10373 static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
10375 int prot = 0;
10377 if (s2ap & 1) {
10378 prot |= PAGE_READ;
10380 if (s2ap & 2) {
10381 prot |= PAGE_WRITE;
10384 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
10385 switch (xn) {
10386 case 0:
10387 prot |= PAGE_EXEC;
10388 break;
10389 case 1:
10390 if (s1_is_el0) {
10391 prot |= PAGE_EXEC;
10393 break;
10394 case 2:
10395 break;
10396 case 3:
10397 if (!s1_is_el0) {
10398 prot |= PAGE_EXEC;
10400 break;
10401 default:
10402 g_assert_not_reached();
10404 } else {
10405 if (!extract32(xn, 1, 1)) {
10406 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
10407 prot |= PAGE_EXEC;
10411 return prot;
10414 /* Translate section/page access permissions to protection flags
10416 * @env: CPUARMState
10417 * @mmu_idx: MMU index indicating required translation regime
10418 * @is_aa64: TRUE if AArch64
10419 * @ap: The 2-bit simple AP (AP[2:1])
10420 * @ns: NS (non-secure) bit
10421 * @xn: XN (execute-never) bit
10422 * @pxn: PXN (privileged execute-never) bit
10424 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
10425 int ap, int ns, int xn, int pxn)
10427 bool is_user = regime_is_user(env, mmu_idx);
10428 int prot_rw, user_rw;
10429 bool have_wxn;
10430 int wxn = 0;
10432 assert(mmu_idx != ARMMMUIdx_Stage2);
10433 assert(mmu_idx != ARMMMUIdx_Stage2_S);
10435 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
10436 if (is_user) {
10437 prot_rw = user_rw;
10438 } else {
10439 if (user_rw && regime_is_pan(env, mmu_idx)) {
10440 /* PAN forbids data accesses but doesn't affect insn fetch */
10441 prot_rw = 0;
10442 } else {
10443 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
10447 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
10448 return prot_rw;
10451 /* TODO have_wxn should be replaced with
10452 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10453 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10454 * compatible processors have EL2, which is required for [U]WXN.
10456 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
10458 if (have_wxn) {
10459 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
10462 if (is_aa64) {
10463 if (regime_has_2_ranges(mmu_idx) && !is_user) {
10464 xn = pxn || (user_rw & PAGE_WRITE);
10466 } else if (arm_feature(env, ARM_FEATURE_V7)) {
10467 switch (regime_el(env, mmu_idx)) {
10468 case 1:
10469 case 3:
10470 if (is_user) {
10471 xn = xn || !(user_rw & PAGE_READ);
10472 } else {
10473 int uwxn = 0;
10474 if (have_wxn) {
10475 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
10477 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
10478 (uwxn && (user_rw & PAGE_WRITE));
10480 break;
10481 case 2:
10482 break;
10484 } else {
10485 xn = wxn = 0;
10488 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
10489 return prot_rw;
10491 return prot_rw | PAGE_EXEC;
10494 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
10495 uint32_t *table, uint32_t address)
10497 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10498 TCR *tcr = regime_tcr(env, mmu_idx);
10500 if (address & tcr->mask) {
10501 if (tcr->raw_tcr & TTBCR_PD1) {
10502 /* Translation table walk disabled for TTBR1 */
10503 return false;
10505 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
10506 } else {
10507 if (tcr->raw_tcr & TTBCR_PD0) {
10508 /* Translation table walk disabled for TTBR0 */
10509 return false;
10511 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
10513 *table |= (address >> 18) & 0x3ffc;
10514 return true;
10517 /* Translate a S1 pagetable walk through S2 if needed. */
10518 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
10519 hwaddr addr, bool *is_secure,
10520 ARMMMUFaultInfo *fi)
10522 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
10523 !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
10524 target_ulong s2size;
10525 hwaddr s2pa;
10526 int s2prot;
10527 int ret;
10528 ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
10529 : ARMMMUIdx_Stage2;
10530 ARMCacheAttrs cacheattrs = {};
10531 MemTxAttrs txattrs = {};
10533 ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
10534 &s2pa, &txattrs, &s2prot, &s2size, fi,
10535 &cacheattrs);
10536 if (ret) {
10537 assert(fi->type != ARMFault_None);
10538 fi->s2addr = addr;
10539 fi->stage2 = true;
10540 fi->s1ptw = true;
10541 fi->s1ns = !*is_secure;
10542 return ~0;
10544 if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
10545 (cacheattrs.attrs & 0xf0) == 0) {
10547 * PTW set and S1 walk touched S2 Device memory:
10548 * generate Permission fault.
10550 fi->type = ARMFault_Permission;
10551 fi->s2addr = addr;
10552 fi->stage2 = true;
10553 fi->s1ptw = true;
10554 fi->s1ns = !*is_secure;
10555 return ~0;
10558 if (arm_is_secure_below_el3(env)) {
10559 /* Check if page table walk is to secure or non-secure PA space. */
10560 if (*is_secure) {
10561 *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
10562 } else {
10563 *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
10565 } else {
10566 assert(!*is_secure);
10569 addr = s2pa;
10571 return addr;
10574 /* All loads done in the course of a page table walk go through here. */
10575 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
10576 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
10578 ARMCPU *cpu = ARM_CPU(cs);
10579 CPUARMState *env = &cpu->env;
10580 MemTxAttrs attrs = {};
10581 MemTxResult result = MEMTX_OK;
10582 AddressSpace *as;
10583 uint32_t data;
10585 addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
10586 attrs.secure = is_secure;
10587 as = arm_addressspace(cs, attrs);
10588 if (fi->s1ptw) {
10589 return 0;
10591 if (regime_translation_big_endian(env, mmu_idx)) {
10592 data = address_space_ldl_be(as, addr, attrs, &result);
10593 } else {
10594 data = address_space_ldl_le(as, addr, attrs, &result);
10596 if (result == MEMTX_OK) {
10597 return data;
10599 fi->type = ARMFault_SyncExternalOnWalk;
10600 fi->ea = arm_extabort_type(result);
10601 return 0;
10604 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
10605 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
10607 ARMCPU *cpu = ARM_CPU(cs);
10608 CPUARMState *env = &cpu->env;
10609 MemTxAttrs attrs = {};
10610 MemTxResult result = MEMTX_OK;
10611 AddressSpace *as;
10612 uint64_t data;
10614 addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
10615 attrs.secure = is_secure;
10616 as = arm_addressspace(cs, attrs);
10617 if (fi->s1ptw) {
10618 return 0;
10620 if (regime_translation_big_endian(env, mmu_idx)) {
10621 data = address_space_ldq_be(as, addr, attrs, &result);
10622 } else {
10623 data = address_space_ldq_le(as, addr, attrs, &result);
10625 if (result == MEMTX_OK) {
10626 return data;
10628 fi->type = ARMFault_SyncExternalOnWalk;
10629 fi->ea = arm_extabort_type(result);
10630 return 0;
10633 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
10634 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10635 hwaddr *phys_ptr, int *prot,
10636 target_ulong *page_size,
10637 ARMMMUFaultInfo *fi)
10639 CPUState *cs = env_cpu(env);
10640 int level = 1;
10641 uint32_t table;
10642 uint32_t desc;
10643 int type;
10644 int ap;
10645 int domain = 0;
10646 int domain_prot;
10647 hwaddr phys_addr;
10648 uint32_t dacr;
10650 /* Pagetable walk. */
10651 /* Lookup l1 descriptor. */
10652 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
10653 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10654 fi->type = ARMFault_Translation;
10655 goto do_fault;
10657 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10658 mmu_idx, fi);
10659 if (fi->type != ARMFault_None) {
10660 goto do_fault;
10662 type = (desc & 3);
10663 domain = (desc >> 5) & 0x0f;
10664 if (regime_el(env, mmu_idx) == 1) {
10665 dacr = env->cp15.dacr_ns;
10666 } else {
10667 dacr = env->cp15.dacr_s;
10669 domain_prot = (dacr >> (domain * 2)) & 3;
10670 if (type == 0) {
10671 /* Section translation fault. */
10672 fi->type = ARMFault_Translation;
10673 goto do_fault;
10675 if (type != 2) {
10676 level = 2;
10678 if (domain_prot == 0 || domain_prot == 2) {
10679 fi->type = ARMFault_Domain;
10680 goto do_fault;
10682 if (type == 2) {
10683 /* 1Mb section. */
10684 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
10685 ap = (desc >> 10) & 3;
10686 *page_size = 1024 * 1024;
10687 } else {
10688 /* Lookup l2 entry. */
10689 if (type == 1) {
10690 /* Coarse pagetable. */
10691 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
10692 } else {
10693 /* Fine pagetable. */
10694 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
10696 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10697 mmu_idx, fi);
10698 if (fi->type != ARMFault_None) {
10699 goto do_fault;
10701 switch (desc & 3) {
10702 case 0: /* Page translation fault. */
10703 fi->type = ARMFault_Translation;
10704 goto do_fault;
10705 case 1: /* 64k page. */
10706 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10707 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
10708 *page_size = 0x10000;
10709 break;
10710 case 2: /* 4k page. */
10711 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10712 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
10713 *page_size = 0x1000;
10714 break;
10715 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10716 if (type == 1) {
10717 /* ARMv6/XScale extended small page format */
10718 if (arm_feature(env, ARM_FEATURE_XSCALE)
10719 || arm_feature(env, ARM_FEATURE_V6)) {
10720 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10721 *page_size = 0x1000;
10722 } else {
10723 /* UNPREDICTABLE in ARMv5; we choose to take a
10724 * page translation fault.
10726 fi->type = ARMFault_Translation;
10727 goto do_fault;
10729 } else {
10730 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
10731 *page_size = 0x400;
10733 ap = (desc >> 4) & 3;
10734 break;
10735 default:
10736 /* Never happens, but compiler isn't smart enough to tell. */
10737 abort();
10740 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10741 *prot |= *prot ? PAGE_EXEC : 0;
10742 if (!(*prot & (1 << access_type))) {
10743 /* Access permission fault. */
10744 fi->type = ARMFault_Permission;
10745 goto do_fault;
10747 *phys_ptr = phys_addr;
10748 return false;
10749 do_fault:
10750 fi->domain = domain;
10751 fi->level = level;
10752 return true;
10755 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
10756 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10757 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
10758 target_ulong *page_size, ARMMMUFaultInfo *fi)
10760 CPUState *cs = env_cpu(env);
10761 ARMCPU *cpu = env_archcpu(env);
10762 int level = 1;
10763 uint32_t table;
10764 uint32_t desc;
10765 uint32_t xn;
10766 uint32_t pxn = 0;
10767 int type;
10768 int ap;
10769 int domain = 0;
10770 int domain_prot;
10771 hwaddr phys_addr;
10772 uint32_t dacr;
10773 bool ns;
10775 /* Pagetable walk. */
10776 /* Lookup l1 descriptor. */
10777 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
10778 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10779 fi->type = ARMFault_Translation;
10780 goto do_fault;
10782 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10783 mmu_idx, fi);
10784 if (fi->type != ARMFault_None) {
10785 goto do_fault;
10787 type = (desc & 3);
10788 if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
10789 /* Section translation fault, or attempt to use the encoding
10790 * which is Reserved on implementations without PXN.
10792 fi->type = ARMFault_Translation;
10793 goto do_fault;
10795 if ((type == 1) || !(desc & (1 << 18))) {
10796 /* Page or Section. */
10797 domain = (desc >> 5) & 0x0f;
10799 if (regime_el(env, mmu_idx) == 1) {
10800 dacr = env->cp15.dacr_ns;
10801 } else {
10802 dacr = env->cp15.dacr_s;
10804 if (type == 1) {
10805 level = 2;
10807 domain_prot = (dacr >> (domain * 2)) & 3;
10808 if (domain_prot == 0 || domain_prot == 2) {
10809 /* Section or Page domain fault */
10810 fi->type = ARMFault_Domain;
10811 goto do_fault;
10813 if (type != 1) {
10814 if (desc & (1 << 18)) {
10815 /* Supersection. */
10816 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
10817 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
10818 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
10819 *page_size = 0x1000000;
10820 } else {
10821 /* Section. */
10822 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
10823 *page_size = 0x100000;
10825 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
10826 xn = desc & (1 << 4);
10827 pxn = desc & 1;
10828 ns = extract32(desc, 19, 1);
10829 } else {
10830 if (cpu_isar_feature(aa32_pxn, cpu)) {
10831 pxn = (desc >> 2) & 1;
10833 ns = extract32(desc, 3, 1);
10834 /* Lookup l2 entry. */
10835 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
10836 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10837 mmu_idx, fi);
10838 if (fi->type != ARMFault_None) {
10839 goto do_fault;
10841 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
10842 switch (desc & 3) {
10843 case 0: /* Page translation fault. */
10844 fi->type = ARMFault_Translation;
10845 goto do_fault;
10846 case 1: /* 64k page. */
10847 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10848 xn = desc & (1 << 15);
10849 *page_size = 0x10000;
10850 break;
10851 case 2: case 3: /* 4k page. */
10852 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10853 xn = desc & 1;
10854 *page_size = 0x1000;
10855 break;
10856 default:
10857 /* Never happens, but compiler isn't smart enough to tell. */
10858 abort();
10861 if (domain_prot == 3) {
10862 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10863 } else {
10864 if (pxn && !regime_is_user(env, mmu_idx)) {
10865 xn = 1;
10867 if (xn && access_type == MMU_INST_FETCH) {
10868 fi->type = ARMFault_Permission;
10869 goto do_fault;
10872 if (arm_feature(env, ARM_FEATURE_V6K) &&
10873 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
10874 /* The simplified model uses AP[0] as an access control bit. */
10875 if ((ap & 1) == 0) {
10876 /* Access flag fault. */
10877 fi->type = ARMFault_AccessFlag;
10878 goto do_fault;
10880 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
10881 } else {
10882 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10884 if (*prot && !xn) {
10885 *prot |= PAGE_EXEC;
10887 if (!(*prot & (1 << access_type))) {
10888 /* Access permission fault. */
10889 fi->type = ARMFault_Permission;
10890 goto do_fault;
10893 if (ns) {
10894 /* The NS bit will (as required by the architecture) have no effect if
10895 * the CPU doesn't support TZ or this is a non-secure translation
10896 * regime, because the attribute will already be non-secure.
10898 attrs->secure = false;
10900 *phys_ptr = phys_addr;
10901 return false;
10902 do_fault:
10903 fi->domain = domain;
10904 fi->level = level;
10905 return true;
10909 * check_s2_mmu_setup
10910 * @cpu: ARMCPU
10911 * @is_aa64: True if the translation regime is in AArch64 state
10912 * @startlevel: Suggested starting level
10913 * @inputsize: Bitsize of IPAs
10914 * @stride: Page-table stride (See the ARM ARM)
10916 * Returns true if the suggested S2 translation parameters are OK and
10917 * false otherwise.
10919 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
10920 int inputsize, int stride)
10922 const int grainsize = stride + 3;
10923 int startsizecheck;
10925 /* Negative levels are never allowed. */
10926 if (level < 0) {
10927 return false;
10930 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
10931 if (startsizecheck < 1 || startsizecheck > stride + 4) {
10932 return false;
10935 if (is_aa64) {
10936 CPUARMState *env = &cpu->env;
10937 unsigned int pamax = arm_pamax(cpu);
10939 switch (stride) {
10940 case 13: /* 64KB Pages. */
10941 if (level == 0 || (level == 1 && pamax <= 42)) {
10942 return false;
10944 break;
10945 case 11: /* 16KB Pages. */
10946 if (level == 0 || (level == 1 && pamax <= 40)) {
10947 return false;
10949 break;
10950 case 9: /* 4KB Pages. */
10951 if (level == 0 && pamax <= 42) {
10952 return false;
10954 break;
10955 default:
10956 g_assert_not_reached();
10959 /* Inputsize checks. */
10960 if (inputsize > pamax &&
10961 (arm_el_is_aa64(env, 1) || inputsize > 40)) {
10962 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10963 return false;
10965 } else {
10966 /* AArch32 only supports 4KB pages. Assert on that. */
10967 assert(stride == 9);
10969 if (level == 0) {
10970 return false;
10973 return true;
10976 /* Translate from the 4-bit stage 2 representation of
10977 * memory attributes (without cache-allocation hints) to
10978 * the 8-bit representation of the stage 1 MAIR registers
10979 * (which includes allocation hints).
10981 * ref: shared/translation/attrs/S2AttrDecode()
10982 * .../S2ConvertAttrsHints()
10984 static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
10986 uint8_t hiattr = extract32(s2attrs, 2, 2);
10987 uint8_t loattr = extract32(s2attrs, 0, 2);
10988 uint8_t hihint = 0, lohint = 0;
10990 if (hiattr != 0) { /* normal memory */
10991 if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
10992 hiattr = loattr = 1; /* non-cacheable */
10993 } else {
10994 if (hiattr != 1) { /* Write-through or write-back */
10995 hihint = 3; /* RW allocate */
10997 if (loattr != 1) { /* Write-through or write-back */
10998 lohint = 3; /* RW allocate */
11003 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
11005 #endif /* !CONFIG_USER_ONLY */
11007 static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
11009 if (regime_has_2_ranges(mmu_idx)) {
11010 return extract64(tcr, 37, 2);
11011 } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
11012 return 0; /* VTCR_EL2 */
11013 } else {
11014 /* Replicate the single TBI bit so we always have 2 bits. */
11015 return extract32(tcr, 20, 1) * 3;
11019 static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
11021 if (regime_has_2_ranges(mmu_idx)) {
11022 return extract64(tcr, 51, 2);
11023 } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
11024 return 0; /* VTCR_EL2 */
11025 } else {
11026 /* Replicate the single TBID bit so we always have 2 bits. */
11027 return extract32(tcr, 29, 1) * 3;
11031 static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
11033 if (regime_has_2_ranges(mmu_idx)) {
11034 return extract64(tcr, 57, 2);
11035 } else {
11036 /* Replicate the single TCMA bit so we always have 2 bits. */
11037 return extract32(tcr, 30, 1) * 3;
11041 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
11042 ARMMMUIdx mmu_idx, bool data)
11044 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
11045 bool epd, hpd, using16k, using64k;
11046 int select, tsz, tbi, max_tsz;
11048 if (!regime_has_2_ranges(mmu_idx)) {
11049 select = 0;
11050 tsz = extract32(tcr, 0, 6);
11051 using64k = extract32(tcr, 14, 1);
11052 using16k = extract32(tcr, 15, 1);
11053 if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
11054 /* VTCR_EL2 */
11055 hpd = false;
11056 } else {
11057 hpd = extract32(tcr, 24, 1);
11059 epd = false;
11060 } else {
11062 * Bit 55 is always between the two regions, and is canonical for
11063 * determining if address tagging is enabled.
11065 select = extract64(va, 55, 1);
11066 if (!select) {
11067 tsz = extract32(tcr, 0, 6);
11068 epd = extract32(tcr, 7, 1);
11069 using64k = extract32(tcr, 14, 1);
11070 using16k = extract32(tcr, 15, 1);
11071 hpd = extract64(tcr, 41, 1);
11072 } else {
11073 int tg = extract32(tcr, 30, 2);
11074 using16k = tg == 1;
11075 using64k = tg == 3;
11076 tsz = extract32(tcr, 16, 6);
11077 epd = extract32(tcr, 23, 1);
11078 hpd = extract64(tcr, 42, 1);
11082 if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
11083 max_tsz = 48 - using64k;
11084 } else {
11085 max_tsz = 39;
11088 tsz = MIN(tsz, max_tsz);
11089 tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
11091 /* Present TBI as a composite with TBID. */
11092 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
11093 if (!data) {
11094 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
11096 tbi = (tbi >> select) & 1;
11098 return (ARMVAParameters) {
11099 .tsz = tsz,
11100 .select = select,
11101 .tbi = tbi,
11102 .epd = epd,
11103 .hpd = hpd,
11104 .using16k = using16k,
11105 .using64k = using64k,
11109 #ifndef CONFIG_USER_ONLY
11110 static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
11111 ARMMMUIdx mmu_idx)
11113 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
11114 uint32_t el = regime_el(env, mmu_idx);
11115 int select, tsz;
11116 bool epd, hpd;
11118 assert(mmu_idx != ARMMMUIdx_Stage2_S);
11120 if (mmu_idx == ARMMMUIdx_Stage2) {
11121 /* VTCR */
11122 bool sext = extract32(tcr, 4, 1);
11123 bool sign = extract32(tcr, 3, 1);
11126 * If the sign-extend bit is not the same as t0sz[3], the result
11127 * is unpredictable. Flag this as a guest error.
11129 if (sign != sext) {
11130 qemu_log_mask(LOG_GUEST_ERROR,
11131 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
11133 tsz = sextract32(tcr, 0, 4) + 8;
11134 select = 0;
11135 hpd = false;
11136 epd = false;
11137 } else if (el == 2) {
11138 /* HTCR */
11139 tsz = extract32(tcr, 0, 3);
11140 select = 0;
11141 hpd = extract64(tcr, 24, 1);
11142 epd = false;
11143 } else {
11144 int t0sz = extract32(tcr, 0, 3);
11145 int t1sz = extract32(tcr, 16, 3);
11147 if (t1sz == 0) {
11148 select = va > (0xffffffffu >> t0sz);
11149 } else {
11150 /* Note that we will detect errors later. */
11151 select = va >= ~(0xffffffffu >> t1sz);
11153 if (!select) {
11154 tsz = t0sz;
11155 epd = extract32(tcr, 7, 1);
11156 hpd = extract64(tcr, 41, 1);
11157 } else {
11158 tsz = t1sz;
11159 epd = extract32(tcr, 23, 1);
11160 hpd = extract64(tcr, 42, 1);
11162 /* For aarch32, hpd0 is not enabled without t2e as well. */
11163 hpd &= extract32(tcr, 6, 1);
11166 return (ARMVAParameters) {
11167 .tsz = tsz,
11168 .select = select,
11169 .epd = epd,
11170 .hpd = hpd,
11175 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
11177 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11178 * prot and page_size may not be filled in, and the populated fsr value provides
11179 * information on why the translation aborted, in the format of a long-format
11180 * DFSR/IFSR fault register, with the following caveats:
11181 * * the WnR bit is never set (the caller must do this).
11183 * @env: CPUARMState
11184 * @address: virtual address to get physical address for
11185 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
11186 * @mmu_idx: MMU index indicating required translation regime
11187 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
11188 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
11189 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
11190 * @phys_ptr: set to the physical address corresponding to the virtual address
11191 * @attrs: set to the memory transaction attributes to use
11192 * @prot: set to the permissions for the page containing phys_ptr
11193 * @page_size_ptr: set to the size of the page containing phys_ptr
11194 * @fi: set to fault info if the translation fails
11195 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11197 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
11198 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11199 bool s1_is_el0,
11200 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
11201 target_ulong *page_size_ptr,
11202 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
11204 ARMCPU *cpu = env_archcpu(env);
11205 CPUState *cs = CPU(cpu);
11206 /* Read an LPAE long-descriptor translation table. */
11207 ARMFaultType fault_type = ARMFault_Translation;
11208 uint32_t level;
11209 ARMVAParameters param;
11210 uint64_t ttbr;
11211 hwaddr descaddr, indexmask, indexmask_grainsize;
11212 uint32_t tableattrs;
11213 target_ulong page_size;
11214 uint32_t attrs;
11215 int32_t stride;
11216 int addrsize, inputsize;
11217 TCR *tcr = regime_tcr(env, mmu_idx);
11218 int ap, ns, xn, pxn;
11219 uint32_t el = regime_el(env, mmu_idx);
11220 uint64_t descaddrmask;
11221 bool aarch64 = arm_el_is_aa64(env, el);
11222 bool guarded = false;
11224 /* TODO: This code does not support shareability levels. */
11225 if (aarch64) {
11226 param = aa64_va_parameters(env, address, mmu_idx,
11227 access_type != MMU_INST_FETCH);
11228 level = 0;
11229 addrsize = 64 - 8 * param.tbi;
11230 inputsize = 64 - param.tsz;
11231 } else {
11232 param = aa32_va_parameters(env, address, mmu_idx);
11233 level = 1;
11234 addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
11235 inputsize = addrsize - param.tsz;
11239 * We determined the region when collecting the parameters, but we
11240 * have not yet validated that the address is valid for the region.
11241 * Extract the top bits and verify that they all match select.
11243 * For aa32, if inputsize == addrsize, then we have selected the
11244 * region by exclusion in aa32_va_parameters and there is no more
11245 * validation to do here.
11247 if (inputsize < addrsize) {
11248 target_ulong top_bits = sextract64(address, inputsize,
11249 addrsize - inputsize);
11250 if (-top_bits != param.select) {
11251 /* The gap between the two regions is a Translation fault */
11252 fault_type = ARMFault_Translation;
11253 goto do_fault;
11257 if (param.using64k) {
11258 stride = 13;
11259 } else if (param.using16k) {
11260 stride = 11;
11261 } else {
11262 stride = 9;
11265 /* Note that QEMU ignores shareability and cacheability attributes,
11266 * so we don't need to do anything with the SH, ORGN, IRGN fields
11267 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11268 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11269 * implement any ASID-like capability so we can ignore it (instead
11270 * we will always flush the TLB any time the ASID is changed).
11272 ttbr = regime_ttbr(env, mmu_idx, param.select);
11274 /* Here we should have set up all the parameters for the translation:
11275 * inputsize, ttbr, epd, stride, tbi
11278 if (param.epd) {
11279 /* Translation table walk disabled => Translation fault on TLB miss
11280 * Note: This is always 0 on 64-bit EL2 and EL3.
11282 goto do_fault;
11285 if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
11286 /* The starting level depends on the virtual address size (which can
11287 * be up to 48 bits) and the translation granule size. It indicates
11288 * the number of strides (stride bits at a time) needed to
11289 * consume the bits of the input address. In the pseudocode this is:
11290 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11291 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11292 * our 'stride + 3' and 'stride' is our 'stride'.
11293 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11294 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11295 * = 4 - (inputsize - 4) / stride;
11297 level = 4 - (inputsize - 4) / stride;
11298 } else {
11299 /* For stage 2 translations the starting level is specified by the
11300 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11302 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
11303 uint32_t startlevel;
11304 bool ok;
11306 if (!aarch64 || stride == 9) {
11307 /* AArch32 or 4KB pages */
11308 startlevel = 2 - sl0;
11310 if (cpu_isar_feature(aa64_st, cpu)) {
11311 startlevel &= 3;
11313 } else {
11314 /* 16KB or 64KB pages */
11315 startlevel = 3 - sl0;
11318 /* Check that the starting level is valid. */
11319 ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
11320 inputsize, stride);
11321 if (!ok) {
11322 fault_type = ARMFault_Translation;
11323 goto do_fault;
11325 level = startlevel;
11328 indexmask_grainsize = (1ULL << (stride + 3)) - 1;
11329 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
11331 /* Now we can extract the actual base address from the TTBR */
11332 descaddr = extract64(ttbr, 0, 48);
11334 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
11335 * and also to mask out CnP (bit 0) which could validly be non-zero.
11337 descaddr &= ~indexmask;
11339 /* The address field in the descriptor goes up to bit 39 for ARMv7
11340 * but up to bit 47 for ARMv8, but we use the descaddrmask
11341 * up to bit 39 for AArch32, because we don't need other bits in that case
11342 * to construct next descriptor address (anyway they should be all zeroes).
11344 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
11345 ~indexmask_grainsize;
11347 /* Secure accesses start with the page table in secure memory and
11348 * can be downgraded to non-secure at any step. Non-secure accesses
11349 * remain non-secure. We implement this by just ORing in the NSTable/NS
11350 * bits at each step.
11352 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
11353 for (;;) {
11354 uint64_t descriptor;
11355 bool nstable;
11357 descaddr |= (address >> (stride * (4 - level))) & indexmask;
11358 descaddr &= ~7ULL;
11359 nstable = extract32(tableattrs, 4, 1);
11360 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
11361 if (fi->type != ARMFault_None) {
11362 goto do_fault;
11365 if (!(descriptor & 1) ||
11366 (!(descriptor & 2) && (level == 3))) {
11367 /* Invalid, or the Reserved level 3 encoding */
11368 goto do_fault;
11370 descaddr = descriptor & descaddrmask;
11372 if ((descriptor & 2) && (level < 3)) {
11373 /* Table entry. The top five bits are attributes which may
11374 * propagate down through lower levels of the table (and
11375 * which are all arranged so that 0 means "no effect", so
11376 * we can gather them up by ORing in the bits at each level).
11378 tableattrs |= extract64(descriptor, 59, 5);
11379 level++;
11380 indexmask = indexmask_grainsize;
11381 continue;
11383 /* Block entry at level 1 or 2, or page entry at level 3.
11384 * These are basically the same thing, although the number
11385 * of bits we pull in from the vaddr varies.
11387 page_size = (1ULL << ((stride * (4 - level)) + 3));
11388 descaddr |= (address & (page_size - 1));
11389 /* Extract attributes from the descriptor */
11390 attrs = extract64(descriptor, 2, 10)
11391 | (extract64(descriptor, 52, 12) << 10);
11393 if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
11394 /* Stage 2 table descriptors do not include any attribute fields */
11395 break;
11397 /* Merge in attributes from table descriptors */
11398 attrs |= nstable << 3; /* NS */
11399 guarded = extract64(descriptor, 50, 1); /* GP */
11400 if (param.hpd) {
11401 /* HPD disables all the table attributes except NSTable. */
11402 break;
11404 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
11405 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11406 * means "force PL1 access only", which means forcing AP[1] to 0.
11408 attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
11409 attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
11410 break;
11412 /* Here descaddr is the final physical address, and attributes
11413 * are all in attrs.
11415 fault_type = ARMFault_AccessFlag;
11416 if ((attrs & (1 << 8)) == 0) {
11417 /* Access flag */
11418 goto do_fault;
11421 ap = extract32(attrs, 4, 2);
11423 if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
11424 ns = mmu_idx == ARMMMUIdx_Stage2;
11425 xn = extract32(attrs, 11, 2);
11426 *prot = get_S2prot(env, ap, xn, s1_is_el0);
11427 } else {
11428 ns = extract32(attrs, 3, 1);
11429 xn = extract32(attrs, 12, 1);
11430 pxn = extract32(attrs, 11, 1);
11431 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
11434 fault_type = ARMFault_Permission;
11435 if (!(*prot & (1 << access_type))) {
11436 goto do_fault;
11439 if (ns) {
11440 /* The NS bit will (as required by the architecture) have no effect if
11441 * the CPU doesn't support TZ or this is a non-secure translation
11442 * regime, because the attribute will already be non-secure.
11444 txattrs->secure = false;
11446 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11447 if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
11448 arm_tlb_bti_gp(txattrs) = true;
11451 if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
11452 cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4));
11453 } else {
11454 /* Index into MAIR registers for cache attributes */
11455 uint8_t attrindx = extract32(attrs, 0, 3);
11456 uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
11457 assert(attrindx <= 7);
11458 cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
11460 cacheattrs->shareability = extract32(attrs, 6, 2);
11462 *phys_ptr = descaddr;
11463 *page_size_ptr = page_size;
11464 return false;
11466 do_fault:
11467 fi->type = fault_type;
11468 fi->level = level;
11469 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11470 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 ||
11471 mmu_idx == ARMMMUIdx_Stage2_S);
11472 fi->s1ns = mmu_idx == ARMMMUIdx_Stage2;
11473 return true;
11476 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
11477 ARMMMUIdx mmu_idx,
11478 int32_t address, int *prot)
11480 if (!arm_feature(env, ARM_FEATURE_M)) {
11481 *prot = PAGE_READ | PAGE_WRITE;
11482 switch (address) {
11483 case 0xF0000000 ... 0xFFFFFFFF:
11484 if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
11485 /* hivecs execing is ok */
11486 *prot |= PAGE_EXEC;
11488 break;
11489 case 0x00000000 ... 0x7FFFFFFF:
11490 *prot |= PAGE_EXEC;
11491 break;
11493 } else {
11494 /* Default system address map for M profile cores.
11495 * The architecture specifies which regions are execute-never;
11496 * at the MPU level no other checks are defined.
11498 switch (address) {
11499 case 0x00000000 ... 0x1fffffff: /* ROM */
11500 case 0x20000000 ... 0x3fffffff: /* SRAM */
11501 case 0x60000000 ... 0x7fffffff: /* RAM */
11502 case 0x80000000 ... 0x9fffffff: /* RAM */
11503 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11504 break;
11505 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11506 case 0xa0000000 ... 0xbfffffff: /* Device */
11507 case 0xc0000000 ... 0xdfffffff: /* Device */
11508 case 0xe0000000 ... 0xffffffff: /* System */
11509 *prot = PAGE_READ | PAGE_WRITE;
11510 break;
11511 default:
11512 g_assert_not_reached();
11517 static bool pmsav7_use_background_region(ARMCPU *cpu,
11518 ARMMMUIdx mmu_idx, bool is_user)
11520 /* Return true if we should use the default memory map as a
11521 * "background" region if there are no hits against any MPU regions.
11523 CPUARMState *env = &cpu->env;
11525 if (is_user) {
11526 return false;
11529 if (arm_feature(env, ARM_FEATURE_M)) {
11530 return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
11531 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
11532 } else {
11533 return regime_sctlr(env, mmu_idx) & SCTLR_BR;
11537 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
11539 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11540 return arm_feature(env, ARM_FEATURE_M) &&
11541 extract32(address, 20, 12) == 0xe00;
11544 static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
11546 /* True if address is in the M profile system region
11547 * 0xe0000000 - 0xffffffff
11549 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
11552 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
11553 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11554 hwaddr *phys_ptr, int *prot,
11555 target_ulong *page_size,
11556 ARMMMUFaultInfo *fi)
11558 ARMCPU *cpu = env_archcpu(env);
11559 int n;
11560 bool is_user = regime_is_user(env, mmu_idx);
11562 *phys_ptr = address;
11563 *page_size = TARGET_PAGE_SIZE;
11564 *prot = 0;
11566 if (regime_translation_disabled(env, mmu_idx) ||
11567 m_is_ppb_region(env, address)) {
11568 /* MPU disabled or M profile PPB access: use default memory map.
11569 * The other case which uses the default memory map in the
11570 * v7M ARM ARM pseudocode is exception vector reads from the vector
11571 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11572 * which always does a direct read using address_space_ldl(), rather
11573 * than going via this function, so we don't need to check that here.
11575 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11576 } else { /* MPU enabled */
11577 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11578 /* region search */
11579 uint32_t base = env->pmsav7.drbar[n];
11580 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
11581 uint32_t rmask;
11582 bool srdis = false;
11584 if (!(env->pmsav7.drsr[n] & 0x1)) {
11585 continue;
11588 if (!rsize) {
11589 qemu_log_mask(LOG_GUEST_ERROR,
11590 "DRSR[%d]: Rsize field cannot be 0\n", n);
11591 continue;
11593 rsize++;
11594 rmask = (1ull << rsize) - 1;
11596 if (base & rmask) {
11597 qemu_log_mask(LOG_GUEST_ERROR,
11598 "DRBAR[%d]: 0x%" PRIx32 " misaligned "
11599 "to DRSR region size, mask = 0x%" PRIx32 "\n",
11600 n, base, rmask);
11601 continue;
11604 if (address < base || address > base + rmask) {
11606 * Address not in this region. We must check whether the
11607 * region covers addresses in the same page as our address.
11608 * In that case we must not report a size that covers the
11609 * whole page for a subsequent hit against a different MPU
11610 * region or the background region, because it would result in
11611 * incorrect TLB hits for subsequent accesses to addresses that
11612 * are in this MPU region.
11614 if (ranges_overlap(base, rmask,
11615 address & TARGET_PAGE_MASK,
11616 TARGET_PAGE_SIZE)) {
11617 *page_size = 1;
11619 continue;
11622 /* Region matched */
11624 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
11625 int i, snd;
11626 uint32_t srdis_mask;
11628 rsize -= 3; /* sub region size (power of 2) */
11629 snd = ((address - base) >> rsize) & 0x7;
11630 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
11632 srdis_mask = srdis ? 0x3 : 0x0;
11633 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
11634 /* This will check in groups of 2, 4 and then 8, whether
11635 * the subregion bits are consistent. rsize is incremented
11636 * back up to give the region size, considering consistent
11637 * adjacent subregions as one region. Stop testing if rsize
11638 * is already big enough for an entire QEMU page.
11640 int snd_rounded = snd & ~(i - 1);
11641 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
11642 snd_rounded + 8, i);
11643 if (srdis_mask ^ srdis_multi) {
11644 break;
11646 srdis_mask = (srdis_mask << i) | srdis_mask;
11647 rsize++;
11650 if (srdis) {
11651 continue;
11653 if (rsize < TARGET_PAGE_BITS) {
11654 *page_size = 1 << rsize;
11656 break;
11659 if (n == -1) { /* no hits */
11660 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
11661 /* background fault */
11662 fi->type = ARMFault_Background;
11663 return true;
11665 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11666 } else { /* a MPU hit! */
11667 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
11668 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
11670 if (m_is_system_region(env, address)) {
11671 /* System space is always execute never */
11672 xn = 1;
11675 if (is_user) { /* User mode AP bit decoding */
11676 switch (ap) {
11677 case 0:
11678 case 1:
11679 case 5:
11680 break; /* no access */
11681 case 3:
11682 *prot |= PAGE_WRITE;
11683 /* fall through */
11684 case 2:
11685 case 6:
11686 *prot |= PAGE_READ | PAGE_EXEC;
11687 break;
11688 case 7:
11689 /* for v7M, same as 6; for R profile a reserved value */
11690 if (arm_feature(env, ARM_FEATURE_M)) {
11691 *prot |= PAGE_READ | PAGE_EXEC;
11692 break;
11694 /* fall through */
11695 default:
11696 qemu_log_mask(LOG_GUEST_ERROR,
11697 "DRACR[%d]: Bad value for AP bits: 0x%"
11698 PRIx32 "\n", n, ap);
11700 } else { /* Priv. mode AP bits decoding */
11701 switch (ap) {
11702 case 0:
11703 break; /* no access */
11704 case 1:
11705 case 2:
11706 case 3:
11707 *prot |= PAGE_WRITE;
11708 /* fall through */
11709 case 5:
11710 case 6:
11711 *prot |= PAGE_READ | PAGE_EXEC;
11712 break;
11713 case 7:
11714 /* for v7M, same as 6; for R profile a reserved value */
11715 if (arm_feature(env, ARM_FEATURE_M)) {
11716 *prot |= PAGE_READ | PAGE_EXEC;
11717 break;
11719 /* fall through */
11720 default:
11721 qemu_log_mask(LOG_GUEST_ERROR,
11722 "DRACR[%d]: Bad value for AP bits: 0x%"
11723 PRIx32 "\n", n, ap);
11727 /* execute never */
11728 if (xn) {
11729 *prot &= ~PAGE_EXEC;
11734 fi->type = ARMFault_Permission;
11735 fi->level = 1;
11736 return !(*prot & (1 << access_type));
11739 static bool v8m_is_sau_exempt(CPUARMState *env,
11740 uint32_t address, MMUAccessType access_type)
11742 /* The architecture specifies that certain address ranges are
11743 * exempt from v8M SAU/IDAU checks.
11745 return
11746 (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
11747 (address >= 0xe0000000 && address <= 0xe0002fff) ||
11748 (address >= 0xe000e000 && address <= 0xe000efff) ||
11749 (address >= 0xe002e000 && address <= 0xe002efff) ||
11750 (address >= 0xe0040000 && address <= 0xe0041fff) ||
11751 (address >= 0xe00ff000 && address <= 0xe00fffff);
11754 void v8m_security_lookup(CPUARMState *env, uint32_t address,
11755 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11756 V8M_SAttributes *sattrs)
11758 /* Look up the security attributes for this address. Compare the
11759 * pseudocode SecurityCheck() function.
11760 * We assume the caller has zero-initialized *sattrs.
11762 ARMCPU *cpu = env_archcpu(env);
11763 int r;
11764 bool idau_exempt = false, idau_ns = true, idau_nsc = true;
11765 int idau_region = IREGION_NOTVALID;
11766 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11767 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
11769 if (cpu->idau) {
11770 IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
11771 IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
11773 iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
11774 &idau_nsc);
11777 if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
11778 /* 0xf0000000..0xffffffff is always S for insn fetches */
11779 return;
11782 if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
11783 sattrs->ns = !regime_is_secure(env, mmu_idx);
11784 return;
11787 if (idau_region != IREGION_NOTVALID) {
11788 sattrs->irvalid = true;
11789 sattrs->iregion = idau_region;
11792 switch (env->sau.ctrl & 3) {
11793 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11794 break;
11795 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11796 sattrs->ns = true;
11797 break;
11798 default: /* SAU.ENABLE == 1 */
11799 for (r = 0; r < cpu->sau_sregion; r++) {
11800 if (env->sau.rlar[r] & 1) {
11801 uint32_t base = env->sau.rbar[r] & ~0x1f;
11802 uint32_t limit = env->sau.rlar[r] | 0x1f;
11804 if (base <= address && limit >= address) {
11805 if (base > addr_page_base || limit < addr_page_limit) {
11806 sattrs->subpage = true;
11808 if (sattrs->srvalid) {
11809 /* If we hit in more than one region then we must report
11810 * as Secure, not NS-Callable, with no valid region
11811 * number info.
11813 sattrs->ns = false;
11814 sattrs->nsc = false;
11815 sattrs->sregion = 0;
11816 sattrs->srvalid = false;
11817 break;
11818 } else {
11819 if (env->sau.rlar[r] & 2) {
11820 sattrs->nsc = true;
11821 } else {
11822 sattrs->ns = true;
11824 sattrs->srvalid = true;
11825 sattrs->sregion = r;
11827 } else {
11829 * Address not in this region. We must check whether the
11830 * region covers addresses in the same page as our address.
11831 * In that case we must not report a size that covers the
11832 * whole page for a subsequent hit against a different MPU
11833 * region or the background region, because it would result
11834 * in incorrect TLB hits for subsequent accesses to
11835 * addresses that are in this MPU region.
11837 if (limit >= base &&
11838 ranges_overlap(base, limit - base + 1,
11839 addr_page_base,
11840 TARGET_PAGE_SIZE)) {
11841 sattrs->subpage = true;
11846 break;
11850 * The IDAU will override the SAU lookup results if it specifies
11851 * higher security than the SAU does.
11853 if (!idau_ns) {
11854 if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
11855 sattrs->ns = false;
11856 sattrs->nsc = idau_nsc;
11861 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
11862 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11863 hwaddr *phys_ptr, MemTxAttrs *txattrs,
11864 int *prot, bool *is_subpage,
11865 ARMMMUFaultInfo *fi, uint32_t *mregion)
11867 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11868 * that a full phys-to-virt translation does).
11869 * mregion is (if not NULL) set to the region number which matched,
11870 * or -1 if no region number is returned (MPU off, address did not
11871 * hit a region, address hit in multiple regions).
11872 * We set is_subpage to true if the region hit doesn't cover the
11873 * entire TARGET_PAGE the address is within.
11875 ARMCPU *cpu = env_archcpu(env);
11876 bool is_user = regime_is_user(env, mmu_idx);
11877 uint32_t secure = regime_is_secure(env, mmu_idx);
11878 int n;
11879 int matchregion = -1;
11880 bool hit = false;
11881 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11882 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
11884 *is_subpage = false;
11885 *phys_ptr = address;
11886 *prot = 0;
11887 if (mregion) {
11888 *mregion = -1;
11891 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11892 * was an exception vector read from the vector table (which is always
11893 * done using the default system address map), because those accesses
11894 * are done in arm_v7m_load_vector(), which always does a direct
11895 * read using address_space_ldl(), rather than going via this function.
11897 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
11898 hit = true;
11899 } else if (m_is_ppb_region(env, address)) {
11900 hit = true;
11901 } else {
11902 if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
11903 hit = true;
11906 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11907 /* region search */
11908 /* Note that the base address is bits [31:5] from the register
11909 * with bits [4:0] all zeroes, but the limit address is bits
11910 * [31:5] from the register with bits [4:0] all ones.
11912 uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
11913 uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
11915 if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
11916 /* Region disabled */
11917 continue;
11920 if (address < base || address > limit) {
11922 * Address not in this region. We must check whether the
11923 * region covers addresses in the same page as our address.
11924 * In that case we must not report a size that covers the
11925 * whole page for a subsequent hit against a different MPU
11926 * region or the background region, because it would result in
11927 * incorrect TLB hits for subsequent accesses to addresses that
11928 * are in this MPU region.
11930 if (limit >= base &&
11931 ranges_overlap(base, limit - base + 1,
11932 addr_page_base,
11933 TARGET_PAGE_SIZE)) {
11934 *is_subpage = true;
11936 continue;
11939 if (base > addr_page_base || limit < addr_page_limit) {
11940 *is_subpage = true;
11943 if (matchregion != -1) {
11944 /* Multiple regions match -- always a failure (unlike
11945 * PMSAv7 where highest-numbered-region wins)
11947 fi->type = ARMFault_Permission;
11948 fi->level = 1;
11949 return true;
11952 matchregion = n;
11953 hit = true;
11957 if (!hit) {
11958 /* background fault */
11959 fi->type = ARMFault_Background;
11960 return true;
11963 if (matchregion == -1) {
11964 /* hit using the background region */
11965 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11966 } else {
11967 uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
11968 uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
11969 bool pxn = false;
11971 if (arm_feature(env, ARM_FEATURE_V8_1M)) {
11972 pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
11975 if (m_is_system_region(env, address)) {
11976 /* System space is always execute never */
11977 xn = 1;
11980 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
11981 if (*prot && !xn && !(pxn && !is_user)) {
11982 *prot |= PAGE_EXEC;
11984 /* We don't need to look the attribute up in the MAIR0/MAIR1
11985 * registers because that only tells us about cacheability.
11987 if (mregion) {
11988 *mregion = matchregion;
11992 fi->type = ARMFault_Permission;
11993 fi->level = 1;
11994 return !(*prot & (1 << access_type));
11998 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
11999 MMUAccessType access_type, ARMMMUIdx mmu_idx,
12000 hwaddr *phys_ptr, MemTxAttrs *txattrs,
12001 int *prot, target_ulong *page_size,
12002 ARMMMUFaultInfo *fi)
12004 uint32_t secure = regime_is_secure(env, mmu_idx);
12005 V8M_SAttributes sattrs = {};
12006 bool ret;
12007 bool mpu_is_subpage;
12009 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
12010 v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
12011 if (access_type == MMU_INST_FETCH) {
12012 /* Instruction fetches always use the MMU bank and the
12013 * transaction attribute determined by the fetch address,
12014 * regardless of CPU state. This is painful for QEMU
12015 * to handle, because it would mean we need to encode
12016 * into the mmu_idx not just the (user, negpri) information
12017 * for the current security state but also that for the
12018 * other security state, which would balloon the number
12019 * of mmu_idx values needed alarmingly.
12020 * Fortunately we can avoid this because it's not actually
12021 * possible to arbitrarily execute code from memory with
12022 * the wrong security attribute: it will always generate
12023 * an exception of some kind or another, apart from the
12024 * special case of an NS CPU executing an SG instruction
12025 * in S&NSC memory. So we always just fail the translation
12026 * here and sort things out in the exception handler
12027 * (including possibly emulating an SG instruction).
12029 if (sattrs.ns != !secure) {
12030 if (sattrs.nsc) {
12031 fi->type = ARMFault_QEMU_NSCExec;
12032 } else {
12033 fi->type = ARMFault_QEMU_SFault;
12035 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
12036 *phys_ptr = address;
12037 *prot = 0;
12038 return true;
12040 } else {
12041 /* For data accesses we always use the MMU bank indicated
12042 * by the current CPU state, but the security attributes
12043 * might downgrade a secure access to nonsecure.
12045 if (sattrs.ns) {
12046 txattrs->secure = false;
12047 } else if (!secure) {
12048 /* NS access to S memory must fault.
12049 * Architecturally we should first check whether the
12050 * MPU information for this address indicates that we
12051 * are doing an unaligned access to Device memory, which
12052 * should generate a UsageFault instead. QEMU does not
12053 * currently check for that kind of unaligned access though.
12054 * If we added it we would need to do so as a special case
12055 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
12057 fi->type = ARMFault_QEMU_SFault;
12058 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
12059 *phys_ptr = address;
12060 *prot = 0;
12061 return true;
12066 ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
12067 txattrs, prot, &mpu_is_subpage, fi, NULL);
12068 *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
12069 return ret;
12072 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
12073 MMUAccessType access_type, ARMMMUIdx mmu_idx,
12074 hwaddr *phys_ptr, int *prot,
12075 ARMMMUFaultInfo *fi)
12077 int n;
12078 uint32_t mask;
12079 uint32_t base;
12080 bool is_user = regime_is_user(env, mmu_idx);
12082 if (regime_translation_disabled(env, mmu_idx)) {
12083 /* MPU disabled. */
12084 *phys_ptr = address;
12085 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
12086 return false;
12089 *phys_ptr = address;
12090 for (n = 7; n >= 0; n--) {
12091 base = env->cp15.c6_region[n];
12092 if ((base & 1) == 0) {
12093 continue;
12095 mask = 1 << ((base >> 1) & 0x1f);
12096 /* Keep this shift separate from the above to avoid an
12097 (undefined) << 32. */
12098 mask = (mask << 1) - 1;
12099 if (((base ^ address) & ~mask) == 0) {
12100 break;
12103 if (n < 0) {
12104 fi->type = ARMFault_Background;
12105 return true;
12108 if (access_type == MMU_INST_FETCH) {
12109 mask = env->cp15.pmsav5_insn_ap;
12110 } else {
12111 mask = env->cp15.pmsav5_data_ap;
12113 mask = (mask >> (n * 4)) & 0xf;
12114 switch (mask) {
12115 case 0:
12116 fi->type = ARMFault_Permission;
12117 fi->level = 1;
12118 return true;
12119 case 1:
12120 if (is_user) {
12121 fi->type = ARMFault_Permission;
12122 fi->level = 1;
12123 return true;
12125 *prot = PAGE_READ | PAGE_WRITE;
12126 break;
12127 case 2:
12128 *prot = PAGE_READ;
12129 if (!is_user) {
12130 *prot |= PAGE_WRITE;
12132 break;
12133 case 3:
12134 *prot = PAGE_READ | PAGE_WRITE;
12135 break;
12136 case 5:
12137 if (is_user) {
12138 fi->type = ARMFault_Permission;
12139 fi->level = 1;
12140 return true;
12142 *prot = PAGE_READ;
12143 break;
12144 case 6:
12145 *prot = PAGE_READ;
12146 break;
12147 default:
12148 /* Bad permission. */
12149 fi->type = ARMFault_Permission;
12150 fi->level = 1;
12151 return true;
12153 *prot |= PAGE_EXEC;
12154 return false;
12157 /* Combine either inner or outer cacheability attributes for normal
12158 * memory, according to table D4-42 and pseudocode procedure
12159 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
12161 * NB: only stage 1 includes allocation hints (RW bits), leading to
12162 * some asymmetry.
12164 static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
12166 if (s1 == 4 || s2 == 4) {
12167 /* non-cacheable has precedence */
12168 return 4;
12169 } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
12170 /* stage 1 write-through takes precedence */
12171 return s1;
12172 } else if (extract32(s2, 2, 2) == 2) {
12173 /* stage 2 write-through takes precedence, but the allocation hint
12174 * is still taken from stage 1
12176 return (2 << 2) | extract32(s1, 0, 2);
12177 } else { /* write-back */
12178 return s1;
12182 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
12183 * and CombineS1S2Desc()
12185 * @s1: Attributes from stage 1 walk
12186 * @s2: Attributes from stage 2 walk
12188 static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
12190 uint8_t s1lo, s2lo, s1hi, s2hi;
12191 ARMCacheAttrs ret;
12192 bool tagged = false;
12194 if (s1.attrs == 0xf0) {
12195 tagged = true;
12196 s1.attrs = 0xff;
12199 s1lo = extract32(s1.attrs, 0, 4);
12200 s2lo = extract32(s2.attrs, 0, 4);
12201 s1hi = extract32(s1.attrs, 4, 4);
12202 s2hi = extract32(s2.attrs, 4, 4);
12204 /* Combine shareability attributes (table D4-43) */
12205 if (s1.shareability == 2 || s2.shareability == 2) {
12206 /* if either are outer-shareable, the result is outer-shareable */
12207 ret.shareability = 2;
12208 } else if (s1.shareability == 3 || s2.shareability == 3) {
12209 /* if either are inner-shareable, the result is inner-shareable */
12210 ret.shareability = 3;
12211 } else {
12212 /* both non-shareable */
12213 ret.shareability = 0;
12216 /* Combine memory type and cacheability attributes */
12217 if (s1hi == 0 || s2hi == 0) {
12218 /* Device has precedence over normal */
12219 if (s1lo == 0 || s2lo == 0) {
12220 /* nGnRnE has precedence over anything */
12221 ret.attrs = 0;
12222 } else if (s1lo == 4 || s2lo == 4) {
12223 /* non-Reordering has precedence over Reordering */
12224 ret.attrs = 4; /* nGnRE */
12225 } else if (s1lo == 8 || s2lo == 8) {
12226 /* non-Gathering has precedence over Gathering */
12227 ret.attrs = 8; /* nGRE */
12228 } else {
12229 ret.attrs = 0xc; /* GRE */
12232 /* Any location for which the resultant memory type is any
12233 * type of Device memory is always treated as Outer Shareable.
12235 ret.shareability = 2;
12236 } else { /* Normal memory */
12237 /* Outer/inner cacheability combine independently */
12238 ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
12239 | combine_cacheattr_nibble(s1lo, s2lo);
12241 if (ret.attrs == 0x44) {
12242 /* Any location for which the resultant memory type is Normal
12243 * Inner Non-cacheable, Outer Non-cacheable is always treated
12244 * as Outer Shareable.
12246 ret.shareability = 2;
12250 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
12251 if (tagged && ret.attrs == 0xff) {
12252 ret.attrs = 0xf0;
12255 return ret;
12259 /* get_phys_addr - get the physical address for this virtual address
12261 * Find the physical address corresponding to the given virtual address,
12262 * by doing a translation table walk on MMU based systems or using the
12263 * MPU state on MPU based systems.
12265 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12266 * prot and page_size may not be filled in, and the populated fsr value provides
12267 * information on why the translation aborted, in the format of a
12268 * DFSR/IFSR fault register, with the following caveats:
12269 * * we honour the short vs long DFSR format differences.
12270 * * the WnR bit is never set (the caller must do this).
12271 * * for PSMAv5 based systems we don't bother to return a full FSR format
12272 * value.
12274 * @env: CPUARMState
12275 * @address: virtual address to get physical address for
12276 * @access_type: 0 for read, 1 for write, 2 for execute
12277 * @mmu_idx: MMU index indicating required translation regime
12278 * @phys_ptr: set to the physical address corresponding to the virtual address
12279 * @attrs: set to the memory transaction attributes to use
12280 * @prot: set to the permissions for the page containing phys_ptr
12281 * @page_size: set to the size of the page containing phys_ptr
12282 * @fi: set to fault info if the translation fails
12283 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
12285 bool get_phys_addr(CPUARMState *env, target_ulong address,
12286 MMUAccessType access_type, ARMMMUIdx mmu_idx,
12287 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
12288 target_ulong *page_size,
12289 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
12291 ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
12293 if (mmu_idx != s1_mmu_idx) {
12294 /* Call ourselves recursively to do the stage 1 and then stage 2
12295 * translations if mmu_idx is a two-stage regime.
12297 if (arm_feature(env, ARM_FEATURE_EL2)) {
12298 hwaddr ipa;
12299 int s2_prot;
12300 int ret;
12301 ARMCacheAttrs cacheattrs2 = {};
12302 ARMMMUIdx s2_mmu_idx;
12303 bool is_el0;
12305 ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
12306 attrs, prot, page_size, fi, cacheattrs);
12308 /* If S1 fails or S2 is disabled, return early. */
12309 if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
12310 *phys_ptr = ipa;
12311 return ret;
12314 s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
12315 is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
12317 /* S1 is done. Now do S2 translation. */
12318 ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
12319 phys_ptr, attrs, &s2_prot,
12320 page_size, fi, &cacheattrs2);
12321 fi->s2addr = ipa;
12322 /* Combine the S1 and S2 perms. */
12323 *prot &= s2_prot;
12325 /* If S2 fails, return early. */
12326 if (ret) {
12327 return ret;
12330 /* Combine the S1 and S2 cache attributes. */
12331 if (arm_hcr_el2_eff(env) & HCR_DC) {
12333 * HCR.DC forces the first stage attributes to
12334 * Normal Non-Shareable,
12335 * Inner Write-Back Read-Allocate Write-Allocate,
12336 * Outer Write-Back Read-Allocate Write-Allocate.
12337 * Do not overwrite Tagged within attrs.
12339 if (cacheattrs->attrs != 0xf0) {
12340 cacheattrs->attrs = 0xff;
12342 cacheattrs->shareability = 0;
12344 *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
12346 /* Check if IPA translates to secure or non-secure PA space. */
12347 if (arm_is_secure_below_el3(env)) {
12348 if (attrs->secure) {
12349 attrs->secure =
12350 !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW));
12351 } else {
12352 attrs->secure =
12353 !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW))
12354 || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA));
12357 return 0;
12358 } else {
12360 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12362 mmu_idx = stage_1_mmu_idx(mmu_idx);
12366 /* The page table entries may downgrade secure to non-secure, but
12367 * cannot upgrade an non-secure translation regime's attributes
12368 * to secure.
12370 attrs->secure = regime_is_secure(env, mmu_idx);
12371 attrs->user = regime_is_user(env, mmu_idx);
12373 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12374 * In v7 and earlier it affects all stage 1 translations.
12376 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2
12377 && !arm_feature(env, ARM_FEATURE_V8)) {
12378 if (regime_el(env, mmu_idx) == 3) {
12379 address += env->cp15.fcseidr_s;
12380 } else {
12381 address += env->cp15.fcseidr_ns;
12385 if (arm_feature(env, ARM_FEATURE_PMSA)) {
12386 bool ret;
12387 *page_size = TARGET_PAGE_SIZE;
12389 if (arm_feature(env, ARM_FEATURE_V8)) {
12390 /* PMSAv8 */
12391 ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
12392 phys_ptr, attrs, prot, page_size, fi);
12393 } else if (arm_feature(env, ARM_FEATURE_V7)) {
12394 /* PMSAv7 */
12395 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
12396 phys_ptr, prot, page_size, fi);
12397 } else {
12398 /* Pre-v7 MPU */
12399 ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
12400 phys_ptr, prot, fi);
12402 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
12403 " mmu_idx %u -> %s (prot %c%c%c)\n",
12404 access_type == MMU_DATA_LOAD ? "reading" :
12405 (access_type == MMU_DATA_STORE ? "writing" : "execute"),
12406 (uint32_t)address, mmu_idx,
12407 ret ? "Miss" : "Hit",
12408 *prot & PAGE_READ ? 'r' : '-',
12409 *prot & PAGE_WRITE ? 'w' : '-',
12410 *prot & PAGE_EXEC ? 'x' : '-');
12412 return ret;
12415 /* Definitely a real MMU, not an MPU */
12417 if (regime_translation_disabled(env, mmu_idx)) {
12418 uint64_t hcr;
12419 uint8_t memattr;
12422 * MMU disabled. S1 addresses within aa64 translation regimes are
12423 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
12425 if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
12426 int r_el = regime_el(env, mmu_idx);
12427 if (arm_el_is_aa64(env, r_el)) {
12428 int pamax = arm_pamax(env_archcpu(env));
12429 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
12430 int addrtop, tbi;
12432 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
12433 if (access_type == MMU_INST_FETCH) {
12434 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
12436 tbi = (tbi >> extract64(address, 55, 1)) & 1;
12437 addrtop = (tbi ? 55 : 63);
12439 if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
12440 fi->type = ARMFault_AddressSize;
12441 fi->level = 0;
12442 fi->stage2 = false;
12443 return 1;
12447 * When TBI is disabled, we've just validated that all of the
12448 * bits above PAMax are zero, so logically we only need to
12449 * clear the top byte for TBI. But it's clearer to follow
12450 * the pseudocode set of addrdesc.paddress.
12452 address = extract64(address, 0, 52);
12455 *phys_ptr = address;
12456 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
12457 *page_size = TARGET_PAGE_SIZE;
12459 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
12460 hcr = arm_hcr_el2_eff(env);
12461 cacheattrs->shareability = 0;
12462 if (hcr & HCR_DC) {
12463 if (hcr & HCR_DCT) {
12464 memattr = 0xf0; /* Tagged, Normal, WB, RWA */
12465 } else {
12466 memattr = 0xff; /* Normal, WB, RWA */
12468 } else if (access_type == MMU_INST_FETCH) {
12469 if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
12470 memattr = 0xee; /* Normal, WT, RA, NT */
12471 } else {
12472 memattr = 0x44; /* Normal, NC, No */
12474 cacheattrs->shareability = 2; /* outer sharable */
12475 } else {
12476 memattr = 0x00; /* Device, nGnRnE */
12478 cacheattrs->attrs = memattr;
12479 return 0;
12482 if (regime_using_lpae_format(env, mmu_idx)) {
12483 return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
12484 phys_ptr, attrs, prot, page_size,
12485 fi, cacheattrs);
12486 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
12487 return get_phys_addr_v6(env, address, access_type, mmu_idx,
12488 phys_ptr, attrs, prot, page_size, fi);
12489 } else {
12490 return get_phys_addr_v5(env, address, access_type, mmu_idx,
12491 phys_ptr, prot, page_size, fi);
12495 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
12496 MemTxAttrs *attrs)
12498 ARMCPU *cpu = ARM_CPU(cs);
12499 CPUARMState *env = &cpu->env;
12500 hwaddr phys_addr;
12501 target_ulong page_size;
12502 int prot;
12503 bool ret;
12504 ARMMMUFaultInfo fi = {};
12505 ARMMMUIdx mmu_idx = arm_mmu_idx(env);
12506 ARMCacheAttrs cacheattrs = {};
12508 *attrs = (MemTxAttrs) {};
12510 ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
12511 attrs, &prot, &page_size, &fi, &cacheattrs);
12513 if (ret) {
12514 return -1;
12516 return phys_addr;
12519 #endif
12521 /* Note that signed overflow is undefined in C. The following routines are
12522 careful to use unsigned types where modulo arithmetic is required.
12523 Failure to do so _will_ break on newer gcc. */
12525 /* Signed saturating arithmetic. */
12527 /* Perform 16-bit signed saturating addition. */
12528 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
12530 uint16_t res;
12532 res = a + b;
12533 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
12534 if (a & 0x8000)
12535 res = 0x8000;
12536 else
12537 res = 0x7fff;
12539 return res;
12542 /* Perform 8-bit signed saturating addition. */
12543 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
12545 uint8_t res;
12547 res = a + b;
12548 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
12549 if (a & 0x80)
12550 res = 0x80;
12551 else
12552 res = 0x7f;
12554 return res;
12557 /* Perform 16-bit signed saturating subtraction. */
12558 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
12560 uint16_t res;
12562 res = a - b;
12563 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
12564 if (a & 0x8000)
12565 res = 0x8000;
12566 else
12567 res = 0x7fff;
12569 return res;
12572 /* Perform 8-bit signed saturating subtraction. */
12573 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
12575 uint8_t res;
12577 res = a - b;
12578 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
12579 if (a & 0x80)
12580 res = 0x80;
12581 else
12582 res = 0x7f;
12584 return res;
12587 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12588 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12589 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12590 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12591 #define PFX q
12593 #include "op_addsub.h"
12595 /* Unsigned saturating arithmetic. */
12596 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
12598 uint16_t res;
12599 res = a + b;
12600 if (res < a)
12601 res = 0xffff;
12602 return res;
12605 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
12607 if (a > b)
12608 return a - b;
12609 else
12610 return 0;
12613 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
12615 uint8_t res;
12616 res = a + b;
12617 if (res < a)
12618 res = 0xff;
12619 return res;
12622 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
12624 if (a > b)
12625 return a - b;
12626 else
12627 return 0;
12630 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12631 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12632 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12633 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12634 #define PFX uq
12636 #include "op_addsub.h"
12638 /* Signed modulo arithmetic. */
12639 #define SARITH16(a, b, n, op) do { \
12640 int32_t sum; \
12641 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12642 RESULT(sum, n, 16); \
12643 if (sum >= 0) \
12644 ge |= 3 << (n * 2); \
12645 } while(0)
12647 #define SARITH8(a, b, n, op) do { \
12648 int32_t sum; \
12649 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12650 RESULT(sum, n, 8); \
12651 if (sum >= 0) \
12652 ge |= 1 << n; \
12653 } while(0)
12656 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12657 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12658 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12659 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12660 #define PFX s
12661 #define ARITH_GE
12663 #include "op_addsub.h"
12665 /* Unsigned modulo arithmetic. */
12666 #define ADD16(a, b, n) do { \
12667 uint32_t sum; \
12668 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12669 RESULT(sum, n, 16); \
12670 if ((sum >> 16) == 1) \
12671 ge |= 3 << (n * 2); \
12672 } while(0)
12674 #define ADD8(a, b, n) do { \
12675 uint32_t sum; \
12676 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12677 RESULT(sum, n, 8); \
12678 if ((sum >> 8) == 1) \
12679 ge |= 1 << n; \
12680 } while(0)
12682 #define SUB16(a, b, n) do { \
12683 uint32_t sum; \
12684 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12685 RESULT(sum, n, 16); \
12686 if ((sum >> 16) == 0) \
12687 ge |= 3 << (n * 2); \
12688 } while(0)
12690 #define SUB8(a, b, n) do { \
12691 uint32_t sum; \
12692 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12693 RESULT(sum, n, 8); \
12694 if ((sum >> 8) == 0) \
12695 ge |= 1 << n; \
12696 } while(0)
12698 #define PFX u
12699 #define ARITH_GE
12701 #include "op_addsub.h"
12703 /* Halved signed arithmetic. */
12704 #define ADD16(a, b, n) \
12705 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12706 #define SUB16(a, b, n) \
12707 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12708 #define ADD8(a, b, n) \
12709 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12710 #define SUB8(a, b, n) \
12711 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12712 #define PFX sh
12714 #include "op_addsub.h"
12716 /* Halved unsigned arithmetic. */
12717 #define ADD16(a, b, n) \
12718 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12719 #define SUB16(a, b, n) \
12720 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12721 #define ADD8(a, b, n) \
12722 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12723 #define SUB8(a, b, n) \
12724 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12725 #define PFX uh
12727 #include "op_addsub.h"
12729 static inline uint8_t do_usad(uint8_t a, uint8_t b)
12731 if (a > b)
12732 return a - b;
12733 else
12734 return b - a;
12737 /* Unsigned sum of absolute byte differences. */
12738 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
12740 uint32_t sum;
12741 sum = do_usad(a, b);
12742 sum += do_usad(a >> 8, b >> 8);
12743 sum += do_usad(a >> 16, b >> 16);
12744 sum += do_usad(a >> 24, b >> 24);
12745 return sum;
12748 /* For ARMv6 SEL instruction. */
12749 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
12751 uint32_t mask;
12753 mask = 0;
12754 if (flags & 1)
12755 mask |= 0xff;
12756 if (flags & 2)
12757 mask |= 0xff00;
12758 if (flags & 4)
12759 mask |= 0xff0000;
12760 if (flags & 8)
12761 mask |= 0xff000000;
12762 return (a & mask) | (b & ~mask);
12765 /* CRC helpers.
12766 * The upper bytes of val (above the number specified by 'bytes') must have
12767 * been zeroed out by the caller.
12769 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
12771 uint8_t buf[4];
12773 stl_le_p(buf, val);
12775 /* zlib crc32 converts the accumulator and output to one's complement. */
12776 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
12779 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
12781 uint8_t buf[4];
12783 stl_le_p(buf, val);
12785 /* Linux crc32c converts the output to one's complement. */
12786 return crc32c(acc, buf, bytes) ^ 0xffffffff;
12789 /* Return the exception level to which FP-disabled exceptions should
12790 * be taken, or 0 if FP is enabled.
12792 int fp_exception_el(CPUARMState *env, int cur_el)
12794 #ifndef CONFIG_USER_ONLY
12795 /* CPACR and the CPTR registers don't exist before v6, so FP is
12796 * always accessible
12798 if (!arm_feature(env, ARM_FEATURE_V6)) {
12799 return 0;
12802 if (arm_feature(env, ARM_FEATURE_M)) {
12803 /* CPACR can cause a NOCP UsageFault taken to current security state */
12804 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) {
12805 return 1;
12808 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) {
12809 if (!extract32(env->v7m.nsacr, 10, 1)) {
12810 /* FP insns cause a NOCP UsageFault taken to Secure */
12811 return 3;
12815 return 0;
12818 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12819 * 0, 2 : trap EL0 and EL1/PL1 accesses
12820 * 1 : trap only EL0 accesses
12821 * 3 : trap no accesses
12822 * This register is ignored if E2H+TGE are both set.
12824 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
12825 int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
12827 switch (fpen) {
12828 case 0:
12829 case 2:
12830 if (cur_el == 0 || cur_el == 1) {
12831 /* Trap to PL1, which might be EL1 or EL3 */
12832 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
12833 return 3;
12835 return 1;
12837 if (cur_el == 3 && !is_a64(env)) {
12838 /* Secure PL1 running at EL3 */
12839 return 3;
12841 break;
12842 case 1:
12843 if (cur_el == 0) {
12844 return 1;
12846 break;
12847 case 3:
12848 break;
12853 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12854 * to control non-secure access to the FPU. It doesn't have any
12855 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12857 if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
12858 cur_el <= 2 && !arm_is_secure_below_el3(env))) {
12859 if (!extract32(env->cp15.nsacr, 10, 1)) {
12860 /* FP insns act as UNDEF */
12861 return cur_el == 2 ? 2 : 1;
12865 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12866 * check because zero bits in the registers mean "don't trap".
12869 /* CPTR_EL2 : present in v7VE or v8 */
12870 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
12871 && arm_is_el2_enabled(env)) {
12872 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12873 return 2;
12876 /* CPTR_EL3 : present in v8 */
12877 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
12878 /* Trap all FP ops to EL3 */
12879 return 3;
12881 #endif
12882 return 0;
12885 /* Return the exception level we're running at if this is our mmu_idx */
12886 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
12888 if (mmu_idx & ARM_MMU_IDX_M) {
12889 return mmu_idx & ARM_MMU_IDX_M_PRIV;
12892 switch (mmu_idx) {
12893 case ARMMMUIdx_E10_0:
12894 case ARMMMUIdx_E20_0:
12895 case ARMMMUIdx_SE10_0:
12896 case ARMMMUIdx_SE20_0:
12897 return 0;
12898 case ARMMMUIdx_E10_1:
12899 case ARMMMUIdx_E10_1_PAN:
12900 case ARMMMUIdx_SE10_1:
12901 case ARMMMUIdx_SE10_1_PAN:
12902 return 1;
12903 case ARMMMUIdx_E2:
12904 case ARMMMUIdx_E20_2:
12905 case ARMMMUIdx_E20_2_PAN:
12906 case ARMMMUIdx_SE2:
12907 case ARMMMUIdx_SE20_2:
12908 case ARMMMUIdx_SE20_2_PAN:
12909 return 2;
12910 case ARMMMUIdx_SE3:
12911 return 3;
12912 default:
12913 g_assert_not_reached();
12917 #ifndef CONFIG_TCG
12918 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
12920 g_assert_not_reached();
12922 #endif
12924 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
12926 ARMMMUIdx idx;
12927 uint64_t hcr;
12929 if (arm_feature(env, ARM_FEATURE_M)) {
12930 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
12933 /* See ARM pseudo-function ELIsInHost. */
12934 switch (el) {
12935 case 0:
12936 hcr = arm_hcr_el2_eff(env);
12937 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
12938 idx = ARMMMUIdx_E20_0;
12939 } else {
12940 idx = ARMMMUIdx_E10_0;
12942 break;
12943 case 1:
12944 if (env->pstate & PSTATE_PAN) {
12945 idx = ARMMMUIdx_E10_1_PAN;
12946 } else {
12947 idx = ARMMMUIdx_E10_1;
12949 break;
12950 case 2:
12951 /* Note that TGE does not apply at EL2. */
12952 if (arm_hcr_el2_eff(env) & HCR_E2H) {
12953 if (env->pstate & PSTATE_PAN) {
12954 idx = ARMMMUIdx_E20_2_PAN;
12955 } else {
12956 idx = ARMMMUIdx_E20_2;
12958 } else {
12959 idx = ARMMMUIdx_E2;
12961 break;
12962 case 3:
12963 return ARMMMUIdx_SE3;
12964 default:
12965 g_assert_not_reached();
12968 if (arm_is_secure_below_el3(env)) {
12969 idx &= ~ARM_MMU_IDX_A_NS;
12972 return idx;
12975 ARMMMUIdx arm_mmu_idx(CPUARMState *env)
12977 return arm_mmu_idx_el(env, arm_current_el(env));
12980 #ifndef CONFIG_USER_ONLY
12981 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
12983 return stage_1_mmu_idx(arm_mmu_idx(env));
12985 #endif
12987 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
12988 ARMMMUIdx mmu_idx,
12989 CPUARMTBFlags flags)
12991 DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
12992 DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
12994 if (arm_singlestep_active(env)) {
12995 DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
12997 return flags;
13000 static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
13001 ARMMMUIdx mmu_idx,
13002 CPUARMTBFlags flags)
13004 bool sctlr_b = arm_sctlr_b(env);
13006 if (sctlr_b) {
13007 DP_TBFLAG_A32(flags, SCTLR__B, 1);
13009 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
13010 DP_TBFLAG_ANY(flags, BE_DATA, 1);
13012 DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
13014 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
13017 static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
13018 ARMMMUIdx mmu_idx)
13020 CPUARMTBFlags flags = {};
13021 uint32_t ccr = env->v7m.ccr[env->v7m.secure];
13023 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
13024 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
13025 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
13028 if (arm_v7m_is_handler_mode(env)) {
13029 DP_TBFLAG_M32(flags, HANDLER, 1);
13033 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
13034 * is suppressing them because the requested execution priority
13035 * is less than 0.
13037 if (arm_feature(env, ARM_FEATURE_V8) &&
13038 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
13039 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
13040 DP_TBFLAG_M32(flags, STACKCHECK, 1);
13043 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
13046 static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env)
13048 CPUARMTBFlags flags = {};
13050 DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env));
13051 return flags;
13054 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
13055 ARMMMUIdx mmu_idx)
13057 CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
13058 int el = arm_current_el(env);
13060 if (arm_sctlr(env, el) & SCTLR_A) {
13061 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
13064 if (arm_el_is_aa64(env, 1)) {
13065 DP_TBFLAG_A32(flags, VFPEN, 1);
13068 if (el < 2 && env->cp15.hstr_el2 &&
13069 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
13070 DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
13073 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
13076 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
13077 ARMMMUIdx mmu_idx)
13079 CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
13080 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
13081 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
13082 uint64_t sctlr;
13083 int tbii, tbid;
13085 DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
13087 /* Get control bits for tagged addresses. */
13088 tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
13089 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
13091 DP_TBFLAG_A64(flags, TBII, tbii);
13092 DP_TBFLAG_A64(flags, TBID, tbid);
13094 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
13095 int sve_el = sve_exception_el(env, el);
13096 uint32_t zcr_len;
13099 * If SVE is disabled, but FP is enabled,
13100 * then the effective len is 0.
13102 if (sve_el != 0 && fp_el == 0) {
13103 zcr_len = 0;
13104 } else {
13105 zcr_len = sve_zcr_len_for_el(env, el);
13107 DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
13108 DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len);
13111 sctlr = regime_sctlr(env, stage1);
13113 if (sctlr & SCTLR_A) {
13114 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
13117 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
13118 DP_TBFLAG_ANY(flags, BE_DATA, 1);
13121 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
13123 * In order to save space in flags, we record only whether
13124 * pauth is "inactive", meaning all insns are implemented as
13125 * a nop, or "active" when some action must be performed.
13126 * The decision of which action to take is left to a helper.
13128 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
13129 DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
13133 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
13134 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
13135 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
13136 DP_TBFLAG_A64(flags, BT, 1);
13140 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
13141 if (!(env->pstate & PSTATE_UAO)) {
13142 switch (mmu_idx) {
13143 case ARMMMUIdx_E10_1:
13144 case ARMMMUIdx_E10_1_PAN:
13145 case ARMMMUIdx_SE10_1:
13146 case ARMMMUIdx_SE10_1_PAN:
13147 /* TODO: ARMv8.3-NV */
13148 DP_TBFLAG_A64(flags, UNPRIV, 1);
13149 break;
13150 case ARMMMUIdx_E20_2:
13151 case ARMMMUIdx_E20_2_PAN:
13152 case ARMMMUIdx_SE20_2:
13153 case ARMMMUIdx_SE20_2_PAN:
13155 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
13156 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
13158 if (env->cp15.hcr_el2 & HCR_TGE) {
13159 DP_TBFLAG_A64(flags, UNPRIV, 1);
13161 break;
13162 default:
13163 break;
13167 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
13169 * Set MTE_ACTIVE if any access may be Checked, and leave clear
13170 * if all accesses must be Unchecked:
13171 * 1) If no TBI, then there are no tags in the address to check,
13172 * 2) If Tag Check Override, then all accesses are Unchecked,
13173 * 3) If Tag Check Fail == 0, then Checked access have no effect,
13174 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
13176 if (allocation_tag_access_enabled(env, el, sctlr)) {
13177 DP_TBFLAG_A64(flags, ATA, 1);
13178 if (tbid
13179 && !(env->pstate & PSTATE_TCO)
13180 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
13181 DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
13184 /* And again for unprivileged accesses, if required. */
13185 if (EX_TBFLAG_A64(flags, UNPRIV)
13186 && tbid
13187 && !(env->pstate & PSTATE_TCO)
13188 && (sctlr & SCTLR_TCF0)
13189 && allocation_tag_access_enabled(env, 0, sctlr)) {
13190 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
13192 /* Cache TCMA as well as TBI. */
13193 DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
13196 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
13199 static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
13201 int el = arm_current_el(env);
13202 int fp_el = fp_exception_el(env, el);
13203 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13205 if (is_a64(env)) {
13206 return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
13207 } else if (arm_feature(env, ARM_FEATURE_M)) {
13208 return rebuild_hflags_m32(env, fp_el, mmu_idx);
13209 } else {
13210 return rebuild_hflags_a32(env, fp_el, mmu_idx);
13214 void arm_rebuild_hflags(CPUARMState *env)
13216 env->hflags = rebuild_hflags_internal(env);
13220 * If we have triggered a EL state change we can't rely on the
13221 * translator having passed it to us, we need to recompute.
13223 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
13225 int el = arm_current_el(env);
13226 int fp_el = fp_exception_el(env, el);
13227 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13229 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
13232 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
13234 int fp_el = fp_exception_el(env, el);
13235 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13237 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
13241 * If we have triggered a EL state change we can't rely on the
13242 * translator having passed it to us, we need to recompute.
13244 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
13246 int el = arm_current_el(env);
13247 int fp_el = fp_exception_el(env, el);
13248 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13249 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
13252 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
13254 int fp_el = fp_exception_el(env, el);
13255 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13257 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
13260 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
13262 int fp_el = fp_exception_el(env, el);
13263 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13265 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
13268 static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
13270 #ifdef CONFIG_DEBUG_TCG
13271 CPUARMTBFlags c = env->hflags;
13272 CPUARMTBFlags r = rebuild_hflags_internal(env);
13274 if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
13275 fprintf(stderr, "TCG hflags mismatch "
13276 "(current:(0x%08x,0x" TARGET_FMT_lx ")"
13277 " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
13278 c.flags, c.flags2, r.flags, r.flags2);
13279 abort();
13281 #endif
13284 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
13285 target_ulong *cs_base, uint32_t *pflags)
13287 CPUARMTBFlags flags;
13289 assert_hflags_rebuild_correctly(env);
13290 flags = env->hflags;
13292 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
13293 *pc = env->pc;
13294 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
13295 DP_TBFLAG_A64(flags, BTYPE, env->btype);
13297 } else {
13298 *pc = env->regs[15];
13300 if (arm_feature(env, ARM_FEATURE_M)) {
13301 if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
13302 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
13303 != env->v7m.secure) {
13304 DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1);
13307 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
13308 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
13309 (env->v7m.secure &&
13310 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
13312 * ASPEN is set, but FPCA/SFPA indicate that there is no
13313 * active FP context; we must create a new FP context before
13314 * executing any FP insn.
13316 DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1);
13319 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
13320 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
13321 DP_TBFLAG_M32(flags, LSPACT, 1);
13323 } else {
13325 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
13326 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
13328 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
13329 DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar);
13330 } else {
13331 DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len);
13332 DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride);
13334 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
13335 DP_TBFLAG_A32(flags, VFPEN, 1);
13339 DP_TBFLAG_AM32(flags, THUMB, env->thumb);
13340 DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits);
13344 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13345 * states defined in the ARM ARM for software singlestep:
13346 * SS_ACTIVE PSTATE.SS State
13347 * 0 x Inactive (the TB flag for SS is always 0)
13348 * 1 0 Active-pending
13349 * 1 1 Active-not-pending
13350 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
13352 if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) {
13353 DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
13356 *pflags = flags.flags;
13357 *cs_base = flags.flags2;
13360 #ifdef TARGET_AARCH64
13362 * The manual says that when SVE is enabled and VQ is widened the
13363 * implementation is allowed to zero the previously inaccessible
13364 * portion of the registers. The corollary to that is that when
13365 * SVE is enabled and VQ is narrowed we are also allowed to zero
13366 * the now inaccessible portion of the registers.
13368 * The intent of this is that no predicate bit beyond VQ is ever set.
13369 * Which means that some operations on predicate registers themselves
13370 * may operate on full uint64_t or even unrolled across the maximum
13371 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13372 * may well be cheaper than conditionals to restrict the operation
13373 * to the relevant portion of a uint16_t[16].
13375 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
13377 int i, j;
13378 uint64_t pmask;
13380 assert(vq >= 1 && vq <= ARM_MAX_VQ);
13381 assert(vq <= env_archcpu(env)->sve_max_vq);
13383 /* Zap the high bits of the zregs. */
13384 for (i = 0; i < 32; i++) {
13385 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
13388 /* Zap the high bits of the pregs and ffr. */
13389 pmask = 0;
13390 if (vq & 3) {
13391 pmask = ~(-1ULL << (16 * (vq & 3)));
13393 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
13394 for (i = 0; i < 17; ++i) {
13395 env->vfp.pregs[i].p[j] &= pmask;
13397 pmask = 0;
13402 * Notice a change in SVE vector size when changing EL.
13404 void aarch64_sve_change_el(CPUARMState *env, int old_el,
13405 int new_el, bool el0_a64)
13407 ARMCPU *cpu = env_archcpu(env);
13408 int old_len, new_len;
13409 bool old_a64, new_a64;
13411 /* Nothing to do if no SVE. */
13412 if (!cpu_isar_feature(aa64_sve, cpu)) {
13413 return;
13416 /* Nothing to do if FP is disabled in either EL. */
13417 if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
13418 return;
13422 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13423 * at ELx, or not available because the EL is in AArch32 state, then
13424 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13425 * has an effective value of 0".
13427 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13428 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13429 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13430 * we already have the correct register contents when encountering the
13431 * vq0->vq0 transition between EL0->EL1.
13433 old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
13434 old_len = (old_a64 && !sve_exception_el(env, old_el)
13435 ? sve_zcr_len_for_el(env, old_el) : 0);
13436 new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
13437 new_len = (new_a64 && !sve_exception_el(env, new_el)
13438 ? sve_zcr_len_for_el(env, new_el) : 0);
13440 /* When changing vector length, clear inaccessible state. */
13441 if (new_len < old_len) {
13442 aarch64_sve_narrow_vq(env, new_len + 1);
13445 #endif