target-arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 /* internal defines */
   5 typedef struct DisasContext {
   6     target_ulong pc;
   7     uint32_t insn;
   8     int is_jmp;
   9     /* Nonzero if this instruction has been conditionally skipped.  */
  10     int condjmp;
  11     /* The label that will be jumped to when the instruction is skipped.  */
  12     TCGLabel *condlabel;
  13     /* Thumb-2 conditional execution bits.  */
  14     int condexec_mask;
  15     int condexec_cond;
  16     struct TranslationBlock *tb;
  17     int singlestep_enabled;
  18     int thumb;
  19     int sctlr_b;
  20     TCGMemOp be_data;
  21 #if !defined(CONFIG_USER_ONLY)
  22     int user;
  23 #endif
  24     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  25     bool tbi0;         /* TBI0 for EL0/1 or TBI for EL2/3 */
  26     bool tbi1;         /* TBI1 for EL0/1, not used for EL2/3 */
  27     bool ns;        /* Use non-secure CPREG bank on access */
  28     int fp_excp_el; /* FP exception EL or 0 if enabled */
  29     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  30     bool secure_routed_to_el3;
  31     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  32     int vec_len;
  33     int vec_stride;
  34     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  35      * so that top level loop can generate correct syndrome information.
  36      */
  37     uint32_t svc_imm;
  38     int aarch64;
  39     int current_el;
  40     GHashTable *cp_regs;
  41     uint64_t features; /* CPU features bits */
  42     /* Because unallocated encodings generate different exception syndrome
  43      * information from traps due to FP being disabled, we can't do a single
  44      * "is fp access disabled" check at a high level in the decode tree.
  45      * To help in catching bugs where the access check was forgotten in some
  46      * code path, we set this flag when the access check is done, and assert
  47      * that it is set at the point where we actually touch the FP regs.
  48      */
  49     bool fp_access_checked;
  50     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  51      * single-step support).
  52      */
  53     bool ss_active;
  54     bool pstate_ss;
  55     /* True if the insn just emitted was a load-exclusive instruction
  56      * (necessary for syndrome information for single step exceptions),
  57      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  58      */
  59     bool is_ldex;
  60     /* True if a single-step exception will be taken to the current EL */
  61     bool ss_same_el;
  62     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  63     int c15_cpar;
  64     /* TCG op index of the current insn_start.  */
  65     int insn_start_idx;
  66 #define TMP_A64_MAX 16
  67     int tmp_a64_count;
  68     TCGv_i64 tmp_a64[TMP_A64_MAX];
  69 } DisasContext;
  70
  71 typedef struct DisasCompare {
  72     TCGCond cond;
  73     TCGv_i32 value;
  74     bool value_global;
  75 } DisasCompare;
  76
  77 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
  78 extern TCGv_env cpu_env;
  79 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
  80 extern TCGv_i64 cpu_exclusive_addr;
  81 extern TCGv_i64 cpu_exclusive_val;
  82
  83 static inline int arm_dc_feature(DisasContext *dc, int feature)
  84 {
  85     return (dc->features & (1ULL << feature)) != 0;
  86 }
  87
  88 static inline int get_mem_index(DisasContext *s)
  89 {
  90     return s->mmu_idx;
  91 }
  92
  93 /* Function used to determine the target exception EL when otherwise not known
  94  * or default.
  95  */
  96 static inline int default_exception_el(DisasContext *s)
  97 {
  98     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
  99      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 100      * exceptions can only be routed to ELs above 1, so we target the higher of
 101      * 1 or the current EL.
 102      */
 103     return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 104             ? 3 : MAX(1, s->current_el);
 105 }
 106
 107 /* target-specific extra values for is_jmp */
 108 /* These instructions trap after executing, so the A32/T32 decoder must
 109  * defer them until after the conditional execution state has been updated.
 110  * WFI also needs special handling when single-stepping.
 111  */
 112 #define DISAS_WFI 4
 113 #define DISAS_SWI 5
 114 /* For instructions which unconditionally cause an exception we can skip
 115  * emitting unreachable code at the end of the TB in the A64 decoder
 116  */
 117 #define DISAS_EXC 6
 118 /* WFE */
 119 #define DISAS_WFE 7
 120 #define DISAS_HVC 8
 121 #define DISAS_SMC 9
 122 #define DISAS_YIELD 10
 123
 124 #ifdef TARGET_AARCH64
 125 void a64_translate_init(void);
 126 void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
 127 void gen_a64_set_pc_im(uint64_t val);
 128 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 129                             fprintf_function cpu_fprintf, int flags);
 130 #else
 131 static inline void a64_translate_init(void)
 132 {
 133 }
 134
 135 static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
 136 {
 137 }
 138
 139 static inline void gen_a64_set_pc_im(uint64_t val)
 140 {
 141 }
 142
 143 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 144                                           fprintf_function cpu_fprintf,
 145                                           int flags)
 146 {
 147 }
 148 #endif
 149
 150 void arm_test_cc(DisasCompare *cmp, int cc);
 151 void arm_free_cc(DisasCompare *cmp);
 152 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 153 void arm_gen_test_cc(int cc, TCGLabel *label);
 154
 155 #endif /* TARGET_ARM_TRANSLATE_H */