?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw: Do not include qemu/log.h if it is not necessary
[qemu/ar7.git] / hw / arm / aspeed_ast2600.c
blob504aabf173715362229f0b887453a47726b7f7e2
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "cpu.h"
13 #include "exec/address-spaces.h"
14 #include "hw/misc/unimp.h"
15 #include "hw/arm/aspeed_soc.h"
16 #include "hw/char/serial.h"
17 #include "qemu/module.h"
18 #include "qemu/error-report.h"
19 #include "hw/i2c/aspeed_i2c.h"
20 #include "net/net.h"
21 #include "sysemu/sysemu.h"
22
23 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
24
25 static const hwaddr aspeed_soc_ast2600_memmap[] = {
26 [ASPEED_DEV_SRAM] = 0x10000000,
27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
28 [ASPEED_DEV_IOMEM] = 0x1E600000,
29 [ASPEED_DEV_PWM] = 0x1E610000,
30 [ASPEED_DEV_FMC] = 0x1E620000,
31 [ASPEED_DEV_SPI1] = 0x1E630000,
32 [ASPEED_DEV_SPI2] = 0x1E641000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
35 [ASPEED_DEV_MII1] = 0x1E650000,
36 [ASPEED_DEV_MII2] = 0x1E650008,
37 [ASPEED_DEV_MII3] = 0x1E650010,
38 [ASPEED_DEV_MII4] = 0x1E650018,
39 [ASPEED_DEV_ETH1] = 0x1E660000,
40 [ASPEED_DEV_ETH3] = 0x1E670000,
41 [ASPEED_DEV_ETH2] = 0x1E680000,
42 [ASPEED_DEV_ETH4] = 0x1E690000,
43 [ASPEED_DEV_VIC] = 0x1E6C0000,
44 [ASPEED_DEV_SDMC] = 0x1E6E0000,
45 [ASPEED_DEV_SCU] = 0x1E6E2000,
46 [ASPEED_DEV_XDMA] = 0x1E6E7000,
47 [ASPEED_DEV_ADC] = 0x1E6E9000,
48 [ASPEED_DEV_VIDEO] = 0x1E700000,
49 [ASPEED_DEV_SDHCI] = 0x1E740000,
50 [ASPEED_DEV_EMMC] = 0x1E750000,
51 [ASPEED_DEV_GPIO] = 0x1E780000,
52 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
53 [ASPEED_DEV_RTC] = 0x1E781000,
54 [ASPEED_DEV_TIMER1] = 0x1E782000,
55 [ASPEED_DEV_WDT] = 0x1E785000,
56 [ASPEED_DEV_LPC] = 0x1E789000,
57 [ASPEED_DEV_IBT] = 0x1E789140,
58 [ASPEED_DEV_I2C] = 0x1E78A000,
59 [ASPEED_DEV_UART1] = 0x1E783000,
60 [ASPEED_DEV_UART5] = 0x1E784000,
61 [ASPEED_DEV_VUART] = 0x1E787000,
62 [ASPEED_DEV_SDRAM] = 0x80000000,
63 };
64
65 #define ASPEED_A7MPCORE_ADDR 0x40460000
66
67 #define AST2600_MAX_IRQ 197
68
69 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
70 static const int aspeed_soc_ast2600_irqmap[] = {
71 [ASPEED_DEV_UART1] = 47,
72 [ASPEED_DEV_UART2] = 48,
73 [ASPEED_DEV_UART3] = 49,
74 [ASPEED_DEV_UART4] = 50,
75 [ASPEED_DEV_UART5] = 8,
76 [ASPEED_DEV_VUART] = 8,
77 [ASPEED_DEV_FMC] = 39,
78 [ASPEED_DEV_SDMC] = 0,
79 [ASPEED_DEV_SCU] = 12,
80 [ASPEED_DEV_ADC] = 78,
81 [ASPEED_DEV_XDMA] = 6,
82 [ASPEED_DEV_SDHCI] = 43,
83 [ASPEED_DEV_EHCI1] = 5,
84 [ASPEED_DEV_EHCI2] = 9,
85 [ASPEED_DEV_EMMC] = 15,
86 [ASPEED_DEV_GPIO] = 40,
87 [ASPEED_DEV_GPIO_1_8V] = 11,
88 [ASPEED_DEV_RTC] = 13,
89 [ASPEED_DEV_TIMER1] = 16,
90 [ASPEED_DEV_TIMER2] = 17,
91 [ASPEED_DEV_TIMER3] = 18,
92 [ASPEED_DEV_TIMER4] = 19,
93 [ASPEED_DEV_TIMER5] = 20,
94 [ASPEED_DEV_TIMER6] = 21,
95 [ASPEED_DEV_TIMER7] = 22,
96 [ASPEED_DEV_TIMER8] = 23,
97 [ASPEED_DEV_WDT] = 24,
98 [ASPEED_DEV_PWM] = 44,
99 [ASPEED_DEV_LPC] = 35,
100 [ASPEED_DEV_IBT] = 143,
101 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
102 [ASPEED_DEV_ETH1] = 2,
103 [ASPEED_DEV_ETH2] = 3,
104 [ASPEED_DEV_ETH3] = 32,
105 [ASPEED_DEV_ETH4] = 33,
106 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
107 };
108
109 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
110 {
111 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
112
113 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
114 }
115
116 static void aspeed_soc_ast2600_init(Object *obj)
117 {
118 AspeedSoCState *s = ASPEED_SOC(obj);
119 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
120 int i;
121 char socname[8];
122 char typename[64];
123
124 if (sscanf(sc->name, "%7s", socname) != 1) {
125 g_assert_not_reached();
126 }
127
128 for (i = 0; i < sc->num_cpus; i++) {
129 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
130 }
131
132 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
133 object_initialize_child(obj, "scu", &s->scu, typename);
134 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
135 sc->silicon_rev);
136 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
137 "hw-strap1");
138 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
139 "hw-strap2");
140 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
141 "hw-prot-key");
142
143 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
144 TYPE_A15MPCORE_PRIV);
145
146 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
147
148 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
149 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
150
151 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
152 object_initialize_child(obj, "i2c", &s->i2c, typename);
153
154 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
155 object_initialize_child(obj, "fmc", &s->fmc, typename);
156 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
157
158 for (i = 0; i < sc->spis_num; i++) {
159 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
160 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
161 }
162
163 for (i = 0; i < sc->ehcis_num; i++) {
164 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
165 TYPE_PLATFORM_EHCI);
166 }
167
168 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
169 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
170 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
171 "ram-size");
172 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
173 "max-ram-size");
174
175 for (i = 0; i < sc->wdts_num; i++) {
176 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
177 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
178 }
179
180 for (i = 0; i < sc->macs_num; i++) {
181 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
182 TYPE_FTGMAC100);
183
184 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
185 }
186
187 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
188
189 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
190 object_initialize_child(obj, "gpio", &s->gpio, typename);
191
192 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
193 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
194
195 object_initialize_child(obj, "sd-controller", &s->sdhci,
196 TYPE_ASPEED_SDHCI);
197
198 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
199
200 /* Init sd card slot class here so that they're under the correct parent */
201 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
202 object_initialize_child(obj, "sd-controller.sdhci[*]",
203 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
204 }
205
206 object_initialize_child(obj, "emmc-controller", &s->emmc,
207 TYPE_ASPEED_SDHCI);
208
209 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
210
211 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
212 TYPE_SYSBUS_SDHCI);
213
214 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
215 }
216
217 /*
218 * ASPEED ast2600 has 0xf as cluster ID
219 *
220 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
221 */
222 static uint64_t aspeed_calc_affinity(int cpu)
223 {
224 return (0xf << ARM_AFF1_SHIFT) | cpu;
225 }
226
227 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
228 {
229 int i;
230 AspeedSoCState *s = ASPEED_SOC(dev);
231 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
232 Error *err = NULL;
233 qemu_irq irq;
234
235 /* IO space */
236 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
237 ASPEED_SOC_IOMEM_SIZE);
238
239 /* Video engine stub */
240 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
241 0x1000);
242
243 /* CPU */
244 for (i = 0; i < sc->num_cpus; i++) {
245 if (sc->num_cpus > 1) {
246 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
247 ASPEED_A7MPCORE_ADDR, &error_abort);
248 }
249 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
250 aspeed_calc_affinity(i), &error_abort);
251
252 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
253 &error_abort);
254
255 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
256 return;
257 }
258 }
259
260 /* A7MPCORE */
261 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
262 &error_abort);
263 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
264 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
265 &error_abort);
266
267 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
268 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
269
270 for (i = 0; i < sc->num_cpus; i++) {
271 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
272 DeviceState *d = DEVICE(qemu_get_cpu(i));
273
274 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
275 sysbus_connect_irq(sbd, i, irq);
276 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
277 sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
278 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
279 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
280 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
281 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
282 }
283
284 /* SRAM */
285 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
286 sc->sram_size, &err);
287 if (err) {
288 error_propagate(errp, err);
289 return;
290 }
291 memory_region_add_subregion(get_system_memory(),
292 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
293
294 /* SCU */
295 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
296 return;
297 }
298 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
299
300 /* RTC */
301 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
302 return;
303 }
304 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
305 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
306 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
307
308 /* Timer */
309 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
310 &error_abort);
311 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
312 return;
313 }
314 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
315 sc->memmap[ASPEED_DEV_TIMER1]);
316 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
317 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
319 }
320
321 /* UART - attach an 8250 to the IO space as our UART5 */
322 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
323 aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
324 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
325
326 /* I2C */
327 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
328 &error_abort);
329 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
330 return;
331 }
332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
333 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
334 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
335 sc->irqmap[ASPEED_DEV_I2C] + i);
336 /*
337 * The AST2600 SoC has one IRQ per I2C bus. Skip the common
338 * IRQ (AST2400 and AST2500) and connect all bussses.
339 */
340 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
341 }
342
343 /* FMC, The number of CS is set at the board level */
344 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
345 &error_abort);
346 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base",
347 sc->memmap[ASPEED_DEV_SDRAM], errp)) {
348 return;
349 }
350 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
351 return;
352 }
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
355 s->fmc.ctrl->flash_window_base);
356 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
357 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
358
359 /* SPI */
360 for (i = 0; i < sc->spis_num; i++) {
361 object_property_set_link(OBJECT(&s->spi[i]), "dram",
362 OBJECT(s->dram_mr), &error_abort);
363 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort);
364 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
365 return;
366 }
367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
368 sc->memmap[ASPEED_DEV_SPI1 + i]);
369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
370 s->spi[i].ctrl->flash_window_base);
371 }
372
373 /* EHCI */
374 for (i = 0; i < sc->ehcis_num; i++) {
375 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
376 return;
377 }
378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
379 sc->memmap[ASPEED_DEV_EHCI1 + i]);
380 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
381 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
382 }
383
384 /* SDMC - SDRAM Memory Controller */
385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
386 return;
387 }
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
389
390 /* Watch dog */
391 for (i = 0; i < sc->wdts_num; i++) {
392 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
393
394 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
395 &error_abort);
396 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
397 return;
398 }
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
400 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
401 }
402
403 /* Net */
404 for (i = 0; i < sc->macs_num; i++) {
405 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
406 &error_abort);
407 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
408 return;
409 }
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
411 sc->memmap[ASPEED_DEV_ETH1 + i]);
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
413 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
414
415 object_property_set_link(OBJECT(&s->mii[i]), "nic",
416 OBJECT(&s->ftgmac100[i]), &error_abort);
417 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
418 return;
419 }
420
421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
422 sc->memmap[ASPEED_DEV_MII1 + i]);
423 }
424
425 /* XDMA */
426 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
427 return;
428 }
429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
430 sc->memmap[ASPEED_DEV_XDMA]);
431 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
432 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
433
434 /* GPIO */
435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
436 return;
437 }
438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
440 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
441
442 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
443 return;
444 }
445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
446 sc->memmap[ASPEED_DEV_GPIO_1_8V]);
447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
448 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
449
450 /* SDHCI */
451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
452 return;
453 }
454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
455 sc->memmap[ASPEED_DEV_SDHCI]);
456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
457 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
458
459 /* eMMC */
460 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
461 return;
462 }
463 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]);
464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
465 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
466
467 /* LPC */
468 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
469 return;
470 }
471 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
472
473 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
474 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
475 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
476
477 /*
478 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
479 *
480 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
481 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
482 * shared across the subdevices, and the shared IRQ output to the VIC is at
483 * offset 0.
484 */
485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
486 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
487 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
488
489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
490 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
491 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
492
493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
494 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
495 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
496
497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
498 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
499 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
500 }
501
502 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
503 {
504 DeviceClass *dc = DEVICE_CLASS(oc);
505 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
506
507 dc->realize = aspeed_soc_ast2600_realize;
508
509 sc->name = "ast2600-a1";
510 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
511 sc->silicon_rev = AST2600_A1_SILICON_REV;
512 sc->sram_size = 0x16400;
513 sc->spis_num = 2;
514 sc->ehcis_num = 2;
515 sc->wdts_num = 4;
516 sc->macs_num = 4;
517 sc->irqmap = aspeed_soc_ast2600_irqmap;
518 sc->memmap = aspeed_soc_ast2600_memmap;
519 sc->num_cpus = 2;
520 }
521
522 static const TypeInfo aspeed_soc_ast2600_type_info = {
523 .name = "ast2600-a1",
524 .parent = TYPE_ASPEED_SOC,
525 .instance_size = sizeof(AspeedSoCState),
526 .instance_init = aspeed_soc_ast2600_init,
527 .class_init = aspeed_soc_ast2600_class_init,
528 .class_size = sizeof(AspeedSoCClass),
529 };
530
531 static void aspeed_soc_register_types(void)
532 {
533 type_register_static(&aspeed_soc_ast2600_type_info);
534 };
535
536 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU