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hw: Do not include qemu/log.h if it is not necessary
[qemu/ar7.git] / hw / arm / aspeed.c
blobc3345fce5366e87dc7ecef5fad1e7cc28c235cd1
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "cpu.h"
15 #include "exec/address-spaces.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/aspeed.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/boards.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/misc/pca9552.h"
22 #include "hw/misc/tmp105.h"
23 #include "hw/misc/led.h"
24 #include "hw/qdev-properties.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/loader.h"
28 #include "qemu/error-report.h"
29 #include "qemu/units.h"
30
31 static struct arm_boot_info aspeed_board_binfo = {
32 .board_id = -1, /* device-tree-only board */
33 };
34
35 struct AspeedMachineState {
36 /* Private */
37 MachineState parent_obj;
38 /* Public */
39
40 AspeedSoCState soc;
41 MemoryRegion ram_container;
42 MemoryRegion max_ram;
43 bool mmio_exec;
44 char *fmc_model;
45 char *spi_model;
46 };
47
48 /* Palmetto hardware value: 0x120CE416 */
49 #define PALMETTO_BMC_HW_STRAP1 ( \
50 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
51 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
52 SCU_AST2400_HW_STRAP_ACPI_DIS | \
53 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
54 SCU_HW_STRAP_VGA_CLASS_CODE | \
55 SCU_HW_STRAP_LPC_RESET_PIN | \
56 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
57 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
58 SCU_HW_STRAP_SPI_WIDTH | \
59 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
60 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
61
62 /* TODO: Find the actual hardware value */
63 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
64 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
65 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
66 SCU_AST2400_HW_STRAP_ACPI_DIS | \
67 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
68 SCU_HW_STRAP_VGA_CLASS_CODE | \
69 SCU_HW_STRAP_LPC_RESET_PIN | \
70 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
71 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
72 SCU_HW_STRAP_SPI_WIDTH | \
73 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
74 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
75
76 /* AST2500 evb hardware value: 0xF100C2E6 */
77 #define AST2500_EVB_HW_STRAP1 (( \
78 AST2500_HW_STRAP1_DEFAULTS | \
79 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
80 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
81 SCU_AST2500_HW_STRAP_UART_DEBUG | \
82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
83 SCU_HW_STRAP_MAC1_RGMII | \
84 SCU_HW_STRAP_MAC0_RGMII) & \
85 ~SCU_HW_STRAP_2ND_BOOT_WDT)
86
87 /* Romulus hardware value: 0xF10AD206 */
88 #define ROMULUS_BMC_HW_STRAP1 ( \
89 AST2500_HW_STRAP1_DEFAULTS | \
90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
92 SCU_AST2500_HW_STRAP_UART_DEBUG | \
93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
94 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
96
97 /* Sonorapass hardware value: 0xF100D216 */
98 #define SONORAPASS_BMC_HW_STRAP1 ( \
99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
101 SCU_AST2500_HW_STRAP_UART_DEBUG | \
102 SCU_AST2500_HW_STRAP_RESERVED28 | \
103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
104 SCU_HW_STRAP_VGA_CLASS_CODE | \
105 SCU_HW_STRAP_LPC_RESET_PIN | \
106 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
107 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
108 SCU_HW_STRAP_VGA_BIOS_ROM | \
109 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
110 SCU_AST2500_HW_STRAP_RESERVED1)
111
112 /* Swift hardware value: 0xF11AD206 */
113 #define SWIFT_BMC_HW_STRAP1 ( \
114 AST2500_HW_STRAP1_DEFAULTS | \
115 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
116 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
117 SCU_AST2500_HW_STRAP_UART_DEBUG | \
118 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
119 SCU_H_PLL_BYPASS_EN | \
120 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
121 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
122
123 #define G220A_BMC_HW_STRAP1 ( \
124 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
125 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
126 SCU_AST2500_HW_STRAP_UART_DEBUG | \
127 SCU_AST2500_HW_STRAP_RESERVED28 | \
128 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
129 SCU_HW_STRAP_2ND_BOOT_WDT | \
130 SCU_HW_STRAP_VGA_CLASS_CODE | \
131 SCU_HW_STRAP_LPC_RESET_PIN | \
132 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
133 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
134 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
135 SCU_AST2500_HW_STRAP_RESERVED1)
136
137 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
138 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
139
140 /* AST2600 evb hardware value */
141 #define AST2600_EVB_HW_STRAP1 0x000000C0
142 #define AST2600_EVB_HW_STRAP2 0x00000003
143
144 /* Tacoma hardware value */
145 #define TACOMA_BMC_HW_STRAP1 0x00000000
146 #define TACOMA_BMC_HW_STRAP2 0x00000040
147
148 /*
149 * The max ram region is for firmwares that scan the address space
150 * with load/store to guess how much RAM the SoC has.
151 */
152 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
153 {
154 return 0;
155 }
156
157 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
158 unsigned size)
159 {
160 /* Discard writes */
161 }
162
163 static const MemoryRegionOps max_ram_ops = {
164 .read = max_ram_read,
165 .write = max_ram_write,
166 .endianness = DEVICE_NATIVE_ENDIAN,
167 };
168
169 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
170 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
171 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
172 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
173 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
174 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
175 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
176
177 static void aspeed_write_smpboot(ARMCPU *cpu,
178 const struct arm_boot_info *info)
179 {
180 static const uint32_t poll_mailbox_ready[] = {
181 /*
182 * r2 = per-cpu go sign value
183 * r1 = AST_SMP_MBOX_FIELD_ENTRY
184 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
185 */
186 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
187 0xe21000ff, /* ands r0, r0, #255 */
188 0xe59f201c, /* ldr r2, [pc, #28] */
189 0xe1822000, /* orr r2, r2, r0 */
190
191 0xe59f1018, /* ldr r1, [pc, #24] */
192 0xe59f0018, /* ldr r0, [pc, #24] */
193
194 0xe320f002, /* wfe */
195 0xe5904000, /* ldr r4, [r0] */
196 0xe1520004, /* cmp r2, r4 */
197 0x1afffffb, /* bne <wfe> */
198 0xe591f000, /* ldr pc, [r1] */
199 AST_SMP_MBOX_GOSIGN,
200 AST_SMP_MBOX_FIELD_ENTRY,
201 AST_SMP_MBOX_FIELD_GOSIGN,
202 };
203
204 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
205 sizeof(poll_mailbox_ready),
206 info->smp_loader_start);
207 }
208
209 static void aspeed_reset_secondary(ARMCPU *cpu,
210 const struct arm_boot_info *info)
211 {
212 AddressSpace *as = arm_boot_address_space(cpu, info);
213 CPUState *cs = CPU(cpu);
214
215 /* info->smp_bootreg_addr */
216 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
217 MEMTXATTRS_UNSPECIFIED, NULL);
218 cpu_set_pc(cs, info->smp_loader_start);
219 }
220
221 #define FIRMWARE_ADDR 0x0
222
223 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
224 Error **errp)
225 {
226 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
227 uint8_t *storage;
228 int64_t size;
229
230 /* The block backend size should have already been 'validated' by
231 * the creation of the m25p80 object.
232 */
233 size = blk_getlength(blk);
234 if (size <= 0) {
235 error_setg(errp, "failed to get flash size");
236 return;
237 }
238
239 if (rom_size > size) {
240 rom_size = size;
241 }
242
243 storage = g_new0(uint8_t, rom_size);
244 if (blk_pread(blk, 0, storage, rom_size) < 0) {
245 error_setg(errp, "failed to read the initial flash content");
246 return;
247 }
248
249 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
250 g_free(storage);
251 }
252
253 static void aspeed_board_init_flashes(AspeedSMCState *s,
254 const char *flashtype)
255 {
256 int i ;
257
258 for (i = 0; i < s->num_cs; ++i) {
259 AspeedSMCFlash *fl = &s->flashes[i];
260 DriveInfo *dinfo = drive_get_next(IF_MTD);
261 qemu_irq cs_line;
262
263 fl->flash = qdev_new(flashtype);
264 if (dinfo) {
265 qdev_prop_set_drive(fl->flash, "drive",
266 blk_by_legacy_dinfo(dinfo));
267 }
268 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
269
270 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
271 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
272 }
273 }
274
275 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
276 {
277 DeviceState *card;
278
279 if (!dinfo) {
280 return;
281 }
282 card = qdev_new(TYPE_SD_CARD);
283 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
284 &error_fatal);
285 qdev_realize_and_unref(card,
286 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
287 &error_fatal);
288 }
289
290 static void aspeed_machine_init(MachineState *machine)
291 {
292 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
293 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
294 AspeedSoCClass *sc;
295 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
296 ram_addr_t max_ram_size;
297 int i;
298 NICInfo *nd = &nd_table[0];
299
300 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
301 4 * GiB);
302 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
303
304 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
305
306 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
307
308 /*
309 * This will error out if isize is not supported by memory controller.
310 */
311 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
312 &error_fatal);
313
314 for (i = 0; i < sc->macs_num; i++) {
315 if ((amc->macs_mask & (1 << i)) && nd->used) {
316 qemu_check_nic_model(nd, TYPE_FTGMAC100);
317 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
318 nd++;
319 }
320 }
321
322 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
323 &error_abort);
324 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
325 &error_abort);
326 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
327 &error_abort);
328 object_property_set_link(OBJECT(&bmc->soc), "dram",
329 OBJECT(&bmc->ram_container), &error_abort);
330 if (machine->kernel_filename) {
331 /*
332 * When booting with a -kernel command line there is no u-boot
333 * that runs to unlock the SCU. In this case set the default to
334 * be unlocked as the kernel expects
335 */
336 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
337 ASPEED_SCU_PROT_KEY, &error_abort);
338 }
339 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
340
341 memory_region_add_subregion(get_system_memory(),
342 sc->memmap[ASPEED_DEV_SDRAM],
343 &bmc->ram_container);
344
345 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
346 &error_abort);
347 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
348 "max_ram", max_ram_size - machine->ram_size);
349 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
350
351 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
352 bmc->fmc_model : amc->fmc_model);
353 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
354 bmc->spi_model : amc->spi_model);
355
356 /* Install first FMC flash content as a boot rom. */
357 if (drive0) {
358 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
359 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
360
361 /*
362 * create a ROM region using the default mapping window size of
363 * the flash module. The window size is 64MB for the AST2400
364 * SoC and 128MB for the AST2500 SoC, which is twice as big as
365 * needed by the flash modules of the Aspeed machines.
366 */
367 if (ASPEED_MACHINE(machine)->mmio_exec) {
368 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
369 &fl->mmio, 0, fl->size);
370 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
371 boot_rom);
372 } else {
373 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
374 fl->size, &error_abort);
375 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
376 boot_rom);
377 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
378 }
379 }
380
381 if (machine->kernel_filename && sc->num_cpus > 1) {
382 /* With no u-boot we must set up a boot stub for the secondary CPU */
383 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
384 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
385 0x80, &error_abort);
386 memory_region_add_subregion(get_system_memory(),
387 AST_SMP_MAILBOX_BASE, smpboot);
388
389 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
390 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
391 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
392 }
393
394 aspeed_board_binfo.ram_size = machine->ram_size;
395 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
396 aspeed_board_binfo.nb_cpus = sc->num_cpus;
397
398 if (amc->i2c_init) {
399 amc->i2c_init(bmc);
400 }
401
402 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
403 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
404 }
405
406 if (bmc->soc.emmc.num_slots) {
407 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
408 }
409
410 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
411 }
412
413 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
414 {
415 AspeedSoCState *soc = &bmc->soc;
416 DeviceState *dev;
417 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
418
419 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
420 * enough to provide basic RTC features. Alarms will be missing */
421 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
422
423 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
424 eeprom_buf);
425
426 /* add a TMP423 temperature sensor */
427 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
428 "tmp423", 0x4c));
429 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
430 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
431 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
432 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
433 }
434
435 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
436 {
437 AspeedSoCState *soc = &bmc->soc;
438 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
439
440 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
441 eeprom_buf);
442
443 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
444 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
445 TYPE_TMP105, 0x4d);
446
447 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
448 * plugged on the I2C bus header */
449 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
450 }
451
452 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
453 {
454 /* Start with some devices on our I2C busses */
455 ast2500_evb_i2c_init(bmc);
456 }
457
458 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
459 {
460 AspeedSoCState *soc = &bmc->soc;
461
462 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
463 * good enough */
464 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
465 }
466
467 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
468 {
469 AspeedSoCState *soc = &bmc->soc;
470
471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
472
473 /* The swift board expects a TMP275 but a TMP105 is compatible */
474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
475 /* The swift board expects a pca9551 but a pca9552 is compatible */
476 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
477
478 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
481
482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
483 /* The swift board expects a pca9539 but a pca9552 is compatible */
484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
485
486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
487 /* The swift board expects a pca9539 but a pca9552 is compatible */
488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
489 0x74);
490
491 /* The swift board expects a TMP275 but a TMP105 is compatible */
492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
494 }
495
496 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
497 {
498 AspeedSoCState *soc = &bmc->soc;
499
500 /* bus 2 : */
501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
502 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
503 /* bus 2 : pca9546 @ 0x73 */
504
505 /* bus 3 : pca9548 @ 0x70 */
506
507 /* bus 4 : */
508 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
509 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
510 eeprom4_54);
511 /* PCA9539 @ 0x76, but PCA9552 is compatible */
512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
513 /* PCA9539 @ 0x77, but PCA9552 is compatible */
514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
515
516 /* bus 6 : */
517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
519 /* bus 6 : pca9546 @ 0x73 */
520
521 /* bus 8 : */
522 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
523 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
524 eeprom8_56);
525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
527 /* bus 8 : adc128d818 @ 0x1d */
528 /* bus 8 : adc128d818 @ 0x1f */
529
530 /*
531 * bus 13 : pca9548 @ 0x71
532 * - channel 3:
533 * - tmm421 @ 0x4c
534 * - tmp421 @ 0x4e
535 * - tmp421 @ 0x4f
536 */
537
538 }
539
540 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
541 {
542 static const struct {
543 unsigned gpio_id;
544 LEDColor color;
545 const char *description;
546 bool gpio_polarity;
547 } pca1_leds[] = {
548 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
549 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
550 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
551 };
552 AspeedSoCState *soc = &bmc->soc;
553 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
554 DeviceState *dev;
555 LEDState *led;
556
557 /* Bus 3: TODO bmp280@77 */
558 /* Bus 3: TODO max31785@52 */
559 /* Bus 3: TODO dps310@76 */
560 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
561 qdev_prop_set_string(dev, "description", "pca1");
562 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
563 aspeed_i2c_get_bus(&soc->i2c, 3),
564 &error_fatal);
565
566 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
567 led = led_create_simple(OBJECT(bmc),
568 pca1_leds[i].gpio_polarity,
569 pca1_leds[i].color,
570 pca1_leds[i].description);
571 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
572 qdev_get_gpio_in(DEVICE(led), 0));
573 }
574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
575 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
576
577 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
579 0x4a);
580
581 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
582 * good enough */
583 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
584
585 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
586 eeprom_buf);
587 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
588 qdev_prop_set_string(dev, "description", "pca0");
589 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
590 aspeed_i2c_get_bus(&soc->i2c, 11),
591 &error_fatal);
592 /* Bus 11: TODO ucd90160@64 */
593 }
594
595 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
596 {
597 AspeedSoCState *soc = &bmc->soc;
598 DeviceState *dev;
599
600 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
601 "emc1413", 0x4c));
602 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
603 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
604 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
605
606 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
607 "emc1413", 0x4c));
608 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
609 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
610 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
611
612 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
613 "emc1413", 0x4c));
614 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
615 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
616 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
617
618 static uint8_t eeprom_buf[2 * 1024] = {
619 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
620 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
621 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
622 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
623 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
624 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
626 };
627 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
628 eeprom_buf);
629 }
630
631 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
632 {
633 return ASPEED_MACHINE(obj)->mmio_exec;
634 }
635
636 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
637 {
638 ASPEED_MACHINE(obj)->mmio_exec = value;
639 }
640
641 static void aspeed_machine_instance_init(Object *obj)
642 {
643 ASPEED_MACHINE(obj)->mmio_exec = false;
644 }
645
646 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
647 {
648 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
649 return g_strdup(bmc->fmc_model);
650 }
651
652 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
653 {
654 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
655
656 g_free(bmc->fmc_model);
657 bmc->fmc_model = g_strdup(value);
658 }
659
660 static char *aspeed_get_spi_model(Object *obj, Error **errp)
661 {
662 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
663 return g_strdup(bmc->spi_model);
664 }
665
666 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
667 {
668 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
669
670 g_free(bmc->spi_model);
671 bmc->spi_model = g_strdup(value);
672 }
673
674 static void aspeed_machine_class_props_init(ObjectClass *oc)
675 {
676 object_class_property_add_bool(oc, "execute-in-place",
677 aspeed_get_mmio_exec,
678 aspeed_set_mmio_exec);
679 object_class_property_set_description(oc, "execute-in-place",
680 "boot directly from CE0 flash device");
681
682 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
683 aspeed_set_fmc_model);
684 object_class_property_set_description(oc, "fmc-model",
685 "Change the FMC Flash model");
686 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
687 aspeed_set_spi_model);
688 object_class_property_set_description(oc, "spi-model",
689 "Change the SPI Flash model");
690 }
691
692 static int aspeed_soc_num_cpus(const char *soc_name)
693 {
694 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
695 return sc->num_cpus;
696 }
697
698 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
699 {
700 MachineClass *mc = MACHINE_CLASS(oc);
701 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
702
703 mc->init = aspeed_machine_init;
704 mc->no_floppy = 1;
705 mc->no_cdrom = 1;
706 mc->no_parallel = 1;
707 mc->default_ram_id = "ram";
708 amc->macs_mask = ASPEED_MAC0_ON;
709
710 aspeed_machine_class_props_init(oc);
711 }
712
713 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
714 {
715 MachineClass *mc = MACHINE_CLASS(oc);
716 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
717
718 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
719 amc->soc_name = "ast2400-a1";
720 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
721 amc->fmc_model = "n25q256a";
722 amc->spi_model = "mx25l25635e";
723 amc->num_cs = 1;
724 amc->i2c_init = palmetto_bmc_i2c_init;
725 mc->default_ram_size = 256 * MiB;
726 mc->default_cpus = mc->min_cpus = mc->max_cpus =
727 aspeed_soc_num_cpus(amc->soc_name);
728 };
729
730 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
731 void *data)
732 {
733 MachineClass *mc = MACHINE_CLASS(oc);
734 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
735
736 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
737 amc->soc_name = "ast2400-a1";
738 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
739 amc->fmc_model = "mx25l25635e";
740 amc->spi_model = "mx25l25635e";
741 amc->num_cs = 1;
742 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
743 amc->i2c_init = palmetto_bmc_i2c_init;
744 mc->default_ram_size = 256 * MiB;
745 }
746
747 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
748 {
749 MachineClass *mc = MACHINE_CLASS(oc);
750 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
751
752 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
753 amc->soc_name = "ast2500-a1";
754 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
755 amc->fmc_model = "w25q256";
756 amc->spi_model = "mx25l25635e";
757 amc->num_cs = 1;
758 amc->i2c_init = ast2500_evb_i2c_init;
759 mc->default_ram_size = 512 * MiB;
760 mc->default_cpus = mc->min_cpus = mc->max_cpus =
761 aspeed_soc_num_cpus(amc->soc_name);
762 };
763
764 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
765 {
766 MachineClass *mc = MACHINE_CLASS(oc);
767 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
768
769 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
770 amc->soc_name = "ast2500-a1";
771 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
772 amc->fmc_model = "n25q256a";
773 amc->spi_model = "mx66l1g45g";
774 amc->num_cs = 2;
775 amc->i2c_init = romulus_bmc_i2c_init;
776 mc->default_ram_size = 512 * MiB;
777 mc->default_cpus = mc->min_cpus = mc->max_cpus =
778 aspeed_soc_num_cpus(amc->soc_name);
779 };
780
781 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
782 {
783 MachineClass *mc = MACHINE_CLASS(oc);
784 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
785
786 mc->desc = "OCP SonoraPass BMC (ARM1176)";
787 amc->soc_name = "ast2500-a1";
788 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
789 amc->fmc_model = "mx66l1g45g";
790 amc->spi_model = "mx66l1g45g";
791 amc->num_cs = 2;
792 amc->i2c_init = sonorapass_bmc_i2c_init;
793 mc->default_ram_size = 512 * MiB;
794 mc->default_cpus = mc->min_cpus = mc->max_cpus =
795 aspeed_soc_num_cpus(amc->soc_name);
796 };
797
798 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
799 {
800 MachineClass *mc = MACHINE_CLASS(oc);
801 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
802
803 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
804 amc->soc_name = "ast2500-a1";
805 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
806 amc->fmc_model = "mx66l1g45g";
807 amc->spi_model = "mx66l1g45g";
808 amc->num_cs = 2;
809 amc->i2c_init = swift_bmc_i2c_init;
810 mc->default_ram_size = 512 * MiB;
811 mc->default_cpus = mc->min_cpus = mc->max_cpus =
812 aspeed_soc_num_cpus(amc->soc_name);
813 };
814
815 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
816 {
817 MachineClass *mc = MACHINE_CLASS(oc);
818 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
819
820 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
821 amc->soc_name = "ast2500-a1";
822 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
823 amc->fmc_model = "mx25l25635e";
824 amc->spi_model = "mx66l1g45g";
825 amc->num_cs = 2;
826 amc->i2c_init = witherspoon_bmc_i2c_init;
827 mc->default_ram_size = 512 * MiB;
828 mc->default_cpus = mc->min_cpus = mc->max_cpus =
829 aspeed_soc_num_cpus(amc->soc_name);
830 };
831
832 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
833 {
834 MachineClass *mc = MACHINE_CLASS(oc);
835 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
836
837 mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
838 amc->soc_name = "ast2600-a1";
839 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
840 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
841 amc->fmc_model = "w25q512jv";
842 amc->spi_model = "mx66u51235f";
843 amc->num_cs = 1;
844 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
845 amc->i2c_init = ast2600_evb_i2c_init;
846 mc->default_ram_size = 1 * GiB;
847 mc->default_cpus = mc->min_cpus = mc->max_cpus =
848 aspeed_soc_num_cpus(amc->soc_name);
849 };
850
851 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
852 {
853 MachineClass *mc = MACHINE_CLASS(oc);
854 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
855
856 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
857 amc->soc_name = "ast2600-a1";
858 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
859 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
860 amc->fmc_model = "mx66l1g45g";
861 amc->spi_model = "mx66l1g45g";
862 amc->num_cs = 2;
863 amc->macs_mask = ASPEED_MAC2_ON;
864 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
865 mc->default_ram_size = 1 * GiB;
866 mc->default_cpus = mc->min_cpus = mc->max_cpus =
867 aspeed_soc_num_cpus(amc->soc_name);
868 };
869
870 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
871 {
872 MachineClass *mc = MACHINE_CLASS(oc);
873 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
874
875 mc->desc = "Bytedance G220A BMC (ARM1176)";
876 amc->soc_name = "ast2500-a1";
877 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
878 amc->fmc_model = "n25q512a";
879 amc->spi_model = "mx25l25635e";
880 amc->num_cs = 2;
881 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON;
882 amc->i2c_init = g220a_bmc_i2c_init;
883 mc->default_ram_size = 1024 * MiB;
884 mc->default_cpus = mc->min_cpus = mc->max_cpus =
885 aspeed_soc_num_cpus(amc->soc_name);
886 };
887
888 static const TypeInfo aspeed_machine_types[] = {
889 {
890 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
891 .parent = TYPE_ASPEED_MACHINE,
892 .class_init = aspeed_machine_palmetto_class_init,
893 }, {
894 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
895 .parent = TYPE_ASPEED_MACHINE,
896 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
897 }, {
898 .name = MACHINE_TYPE_NAME("ast2500-evb"),
899 .parent = TYPE_ASPEED_MACHINE,
900 .class_init = aspeed_machine_ast2500_evb_class_init,
901 }, {
902 .name = MACHINE_TYPE_NAME("romulus-bmc"),
903 .parent = TYPE_ASPEED_MACHINE,
904 .class_init = aspeed_machine_romulus_class_init,
905 }, {
906 .name = MACHINE_TYPE_NAME("swift-bmc"),
907 .parent = TYPE_ASPEED_MACHINE,
908 .class_init = aspeed_machine_swift_class_init,
909 }, {
910 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
911 .parent = TYPE_ASPEED_MACHINE,
912 .class_init = aspeed_machine_sonorapass_class_init,
913 }, {
914 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
915 .parent = TYPE_ASPEED_MACHINE,
916 .class_init = aspeed_machine_witherspoon_class_init,
917 }, {
918 .name = MACHINE_TYPE_NAME("ast2600-evb"),
919 .parent = TYPE_ASPEED_MACHINE,
920 .class_init = aspeed_machine_ast2600_evb_class_init,
921 }, {
922 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
923 .parent = TYPE_ASPEED_MACHINE,
924 .class_init = aspeed_machine_tacoma_class_init,
925 }, {
926 .name = MACHINE_TYPE_NAME("g220a-bmc"),
927 .parent = TYPE_ASPEED_MACHINE,
928 .class_init = aspeed_machine_g220a_class_init,
929 }, {
930 .name = TYPE_ASPEED_MACHINE,
931 .parent = TYPE_MACHINE,
932 .instance_size = sizeof(AspeedMachineState),
933 .instance_init = aspeed_machine_instance_init,
934 .class_size = sizeof(AspeedMachineClass),
935 .class_init = aspeed_machine_class_init,
936 .abstract = true,
937 }
938 };
939
940 DEFINE_TYPES(aspeed_machine_types)
AR7 emulation for QEMU