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qapi: New QAPISourceInfo, replacing dict
[qemu/ar7.git] / target / mips / op_helper.c
blob4de64657efe81d75a94b29e73f96255433be49e3
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/memop.h"
28 #include "sysemu/kvm.h"
29 #include "fpu/softfloat.h"
30
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
33
34 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
35 int error_code)
36 {
37 do_raise_exception_err(env, exception, error_code, 0);
38 }
39
40 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
41 {
42 do_raise_exception(env, exception, GETPC());
43 }
44
45 void helper_raise_exception_debug(CPUMIPSState *env)
46 {
47 do_raise_exception(env, EXCP_DEBUG, 0);
48 }
49
50 static void raise_exception(CPUMIPSState *env, uint32_t exception)
51 {
52 do_raise_exception(env, exception, 0);
53 }
54
55 #if defined(CONFIG_USER_ONLY)
56 #define HELPER_LD(name, insn, type) \
57 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
58 int mem_idx, uintptr_t retaddr) \
59 { \
60 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61 }
62 #else
63 #define HELPER_LD(name, insn, type) \
64 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
65 int mem_idx, uintptr_t retaddr) \
66 { \
67 switch (mem_idx) \
68 { \
69 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
70 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
71 default: \
72 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
73 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
74 } \
75 }
76 #endif
77 HELPER_LD(lw, ldl, int32_t)
78 #if defined(TARGET_MIPS64)
79 HELPER_LD(ld, ldq, int64_t)
80 #endif
81 #undef HELPER_LD
82
83 #if defined(CONFIG_USER_ONLY)
84 #define HELPER_ST(name, insn, type) \
85 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
86 type val, int mem_idx, uintptr_t retaddr) \
87 { \
88 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89 }
90 #else
91 #define HELPER_ST(name, insn, type) \
92 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
93 type val, int mem_idx, uintptr_t retaddr) \
94 { \
95 switch (mem_idx) \
96 { \
97 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
98 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
99 default: \
100 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
101 case 3: \
102 cpu_##insn##_error_ra(env, addr, val, retaddr); \
103 break; \
104 } \
105 }
106 #endif
107 HELPER_ST(sb, stb, uint8_t)
108 HELPER_ST(sw, stl, uint32_t)
109 #if defined(TARGET_MIPS64)
110 HELPER_ST(sd, stq, uint64_t)
111 #endif
112 #undef HELPER_ST
113
114 /* 64 bits arithmetic for 32 bits hosts */
115 static inline uint64_t get_HILO(CPUMIPSState *env)
116 {
117 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
118 }
119
120 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
121 {
122 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
123 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
124 }
125
126 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
127 {
128 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
129 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
130 return tmp;
131 }
132
133 /* Multiplication variants of the vr54xx. */
134 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
135 target_ulong arg2)
136 {
137 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
138 (int64_t)(int32_t)arg2));
139 }
140
141 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
142 target_ulong arg2)
143 {
144 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
145 (uint64_t)(uint32_t)arg2);
146 }
147
148 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
149 target_ulong arg2)
150 {
151 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
152 (int64_t)(int32_t)arg2);
153 }
154
155 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
156 target_ulong arg2)
157 {
158 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
159 (int64_t)(int32_t)arg2);
160 }
161
162 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
163 target_ulong arg2)
164 {
165 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
166 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
167 }
168
169 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
170 target_ulong arg2)
171 {
172 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
173 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
174 }
175
176 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
177 target_ulong arg2)
178 {
179 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
180 (int64_t)(int32_t)arg2);
181 }
182
183 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
184 target_ulong arg2)
185 {
186 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
187 (int64_t)(int32_t)arg2);
188 }
189
190 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
191 target_ulong arg2)
192 {
193 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
194 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
195 }
196
197 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
198 target_ulong arg2)
199 {
200 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
201 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
202 }
203
204 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
205 target_ulong arg2)
206 {
207 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
208 }
209
210 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
211 target_ulong arg2)
212 {
213 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
214 (uint64_t)(uint32_t)arg2);
215 }
216
217 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
218 target_ulong arg2)
219 {
220 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
221 (int64_t)(int32_t)arg2);
222 }
223
224 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
225 target_ulong arg2)
226 {
227 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
228 (uint64_t)(uint32_t)arg2);
229 }
230
231 static inline target_ulong bitswap(target_ulong v)
232 {
233 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
234 ((v & (target_ulong)0x5555555555555555ULL) << 1);
235 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
236 ((v & (target_ulong)0x3333333333333333ULL) << 2);
237 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
238 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
239 return v;
240 }
241
242 #ifdef TARGET_MIPS64
243 target_ulong helper_dbitswap(target_ulong rt)
244 {
245 return bitswap(rt);
246 }
247 #endif
248
249 target_ulong helper_bitswap(target_ulong rt)
250 {
251 return (int32_t)bitswap(rt);
252 }
253
254 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
255 uint32_t stripe)
256 {
257 int i;
258 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
259 uint64_t tmp1 = tmp0;
260 for (i = 0; i <= 46; i++) {
261 int s;
262 if (i & 0x8) {
263 s = shift;
264 } else {
265 s = shiftx;
266 }
267
268 if (stripe != 0 && !(i & 0x4)) {
269 s = ~s;
270 }
271 if (s & 0x10) {
272 if (tmp0 & (1LL << (i + 16))) {
273 tmp1 |= 1LL << i;
274 } else {
275 tmp1 &= ~(1LL << i);
276 }
277 }
278 }
279
280 uint64_t tmp2 = tmp1;
281 for (i = 0; i <= 38; i++) {
282 int s;
283 if (i & 0x4) {
284 s = shift;
285 } else {
286 s = shiftx;
287 }
288
289 if (s & 0x8) {
290 if (tmp1 & (1LL << (i + 8))) {
291 tmp2 |= 1LL << i;
292 } else {
293 tmp2 &= ~(1LL << i);
294 }
295 }
296 }
297
298 uint64_t tmp3 = tmp2;
299 for (i = 0; i <= 34; i++) {
300 int s;
301 if (i & 0x2) {
302 s = shift;
303 } else {
304 s = shiftx;
305 }
306 if (s & 0x4) {
307 if (tmp2 & (1LL << (i + 4))) {
308 tmp3 |= 1LL << i;
309 } else {
310 tmp3 &= ~(1LL << i);
311 }
312 }
313 }
314
315 uint64_t tmp4 = tmp3;
316 for (i = 0; i <= 32; i++) {
317 int s;
318 if (i & 0x1) {
319 s = shift;
320 } else {
321 s = shiftx;
322 }
323 if (s & 0x2) {
324 if (tmp3 & (1LL << (i + 2))) {
325 tmp4 |= 1LL << i;
326 } else {
327 tmp4 &= ~(1LL << i);
328 }
329 }
330 }
331
332 uint64_t tmp5 = tmp4;
333 for (i = 0; i <= 31; i++) {
334 int s;
335 s = shift;
336 if (s & 0x1) {
337 if (tmp4 & (1LL << (i + 1))) {
338 tmp5 |= 1LL << i;
339 } else {
340 tmp5 &= ~(1LL << i);
341 }
342 }
343 }
344
345 return (int64_t)(int32_t)(uint32_t)tmp5;
346 }
347
348 #ifndef CONFIG_USER_ONLY
349
350 static inline hwaddr do_translate_address(CPUMIPSState *env,
351 target_ulong address,
352 int rw, uintptr_t retaddr)
353 {
354 hwaddr paddr;
355 CPUState *cs = env_cpu(env);
356
357 paddr = cpu_mips_translate_address(env, address, rw);
358
359 if (paddr == -1LL) {
360 cpu_loop_exit_restore(cs, retaddr);
361 } else {
362 return paddr;
363 }
364 }
365
366 #define HELPER_LD_ATOMIC(name, insn, almask) \
367 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
368 { \
369 if (arg & almask) { \
370 if (!(env->hflags & MIPS_HFLAG_DM)) { \
371 env->CP0_BadVAddr = arg; \
372 } \
373 do_raise_exception(env, EXCP_AdEL, GETPC()); \
374 } \
375 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
376 env->lladdr = arg; \
377 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
378 return env->llval; \
379 }
380 HELPER_LD_ATOMIC(ll, lw, 0x3)
381 #ifdef TARGET_MIPS64
382 HELPER_LD_ATOMIC(lld, ld, 0x7)
383 #endif
384 #undef HELPER_LD_ATOMIC
385 #endif
386
387 #ifdef TARGET_WORDS_BIGENDIAN
388 #define GET_LMASK(v) ((v) & 3)
389 #define GET_OFFSET(addr, offset) (addr + (offset))
390 #else
391 #define GET_LMASK(v) (((v) & 3) ^ 3)
392 #define GET_OFFSET(addr, offset) (addr - (offset))
393 #endif
394
395 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
396 int mem_idx)
397 {
398 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
399
400 if (GET_LMASK(arg2) <= 2) {
401 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
402 GETPC());
403 }
404
405 if (GET_LMASK(arg2) <= 1) {
406 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
407 GETPC());
408 }
409
410 if (GET_LMASK(arg2) == 0) {
411 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
412 GETPC());
413 }
414 }
415
416 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
417 int mem_idx)
418 {
419 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
420
421 if (GET_LMASK(arg2) >= 1) {
422 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
423 GETPC());
424 }
425
426 if (GET_LMASK(arg2) >= 2) {
427 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
428 GETPC());
429 }
430
431 if (GET_LMASK(arg2) == 3) {
432 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
433 GETPC());
434 }
435 }
436
437 #if defined(TARGET_MIPS64)
438 /* "half" load and stores. We must do the memory access inline,
439 or fault handling won't work. */
440
441 #ifdef TARGET_WORDS_BIGENDIAN
442 #define GET_LMASK64(v) ((v) & 7)
443 #else
444 #define GET_LMASK64(v) (((v) & 7) ^ 7)
445 #endif
446
447 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
448 int mem_idx)
449 {
450 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
451
452 if (GET_LMASK64(arg2) <= 6) {
453 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
454 GETPC());
455 }
456
457 if (GET_LMASK64(arg2) <= 5) {
458 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
459 GETPC());
460 }
461
462 if (GET_LMASK64(arg2) <= 4) {
463 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
464 GETPC());
465 }
466
467 if (GET_LMASK64(arg2) <= 3) {
468 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
469 GETPC());
470 }
471
472 if (GET_LMASK64(arg2) <= 2) {
473 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
474 GETPC());
475 }
476
477 if (GET_LMASK64(arg2) <= 1) {
478 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
479 GETPC());
480 }
481
482 if (GET_LMASK64(arg2) <= 0) {
483 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
484 GETPC());
485 }
486 }
487
488 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
489 int mem_idx)
490 {
491 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
492
493 if (GET_LMASK64(arg2) >= 1) {
494 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
495 GETPC());
496 }
497
498 if (GET_LMASK64(arg2) >= 2) {
499 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
500 GETPC());
501 }
502
503 if (GET_LMASK64(arg2) >= 3) {
504 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
505 GETPC());
506 }
507
508 if (GET_LMASK64(arg2) >= 4) {
509 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
510 GETPC());
511 }
512
513 if (GET_LMASK64(arg2) >= 5) {
514 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
515 GETPC());
516 }
517
518 if (GET_LMASK64(arg2) >= 6) {
519 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
520 GETPC());
521 }
522
523 if (GET_LMASK64(arg2) == 7) {
524 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
525 GETPC());
526 }
527 }
528 #endif /* TARGET_MIPS64 */
529
530 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
531
532 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
533 uint32_t mem_idx)
534 {
535 target_ulong base_reglist = reglist & 0xf;
536 target_ulong do_r31 = reglist & 0x10;
537
538 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
539 target_ulong i;
540
541 for (i = 0; i < base_reglist; i++) {
542 env->active_tc.gpr[multiple_regs[i]] =
543 (target_long)do_lw(env, addr, mem_idx, GETPC());
544 addr += 4;
545 }
546 }
547
548 if (do_r31) {
549 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
550 GETPC());
551 }
552 }
553
554 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
555 uint32_t mem_idx)
556 {
557 target_ulong base_reglist = reglist & 0xf;
558 target_ulong do_r31 = reglist & 0x10;
559
560 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
561 target_ulong i;
562
563 for (i = 0; i < base_reglist; i++) {
564 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
565 GETPC());
566 addr += 4;
567 }
568 }
569
570 if (do_r31) {
571 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
572 }
573 }
574
575 #if defined(TARGET_MIPS64)
576 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
577 uint32_t mem_idx)
578 {
579 target_ulong base_reglist = reglist & 0xf;
580 target_ulong do_r31 = reglist & 0x10;
581
582 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
583 target_ulong i;
584
585 for (i = 0; i < base_reglist; i++) {
586 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
587 GETPC());
588 addr += 8;
589 }
590 }
591
592 if (do_r31) {
593 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
594 }
595 }
596
597 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
598 uint32_t mem_idx)
599 {
600 target_ulong base_reglist = reglist & 0xf;
601 target_ulong do_r31 = reglist & 0x10;
602
603 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
604 target_ulong i;
605
606 for (i = 0; i < base_reglist; i++) {
607 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
608 GETPC());
609 addr += 8;
610 }
611 }
612
613 if (do_r31) {
614 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
615 }
616 }
617 #endif
618
619 #ifndef CONFIG_USER_ONLY
620 /* SMP helpers. */
621 static bool mips_vpe_is_wfi(MIPSCPU *c)
622 {
623 CPUState *cpu = CPU(c);
624 CPUMIPSState *env = &c->env;
625
626 /* If the VPE is halted but otherwise active, it means it's waiting for
627 an interrupt. */
628 return cpu->halted && mips_vpe_active(env);
629 }
630
631 static bool mips_vp_is_wfi(MIPSCPU *c)
632 {
633 CPUState *cpu = CPU(c);
634 CPUMIPSState *env = &c->env;
635
636 return cpu->halted && mips_vp_active(env);
637 }
638
639 static inline void mips_vpe_wake(MIPSCPU *c)
640 {
641 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
642 because there might be other conditions that state that c should
643 be sleeping. */
644 qemu_mutex_lock_iothread();
645 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
646 qemu_mutex_unlock_iothread();
647 }
648
649 static inline void mips_vpe_sleep(MIPSCPU *cpu)
650 {
651 CPUState *cs = CPU(cpu);
652
653 /* The VPE was shut off, really go to bed.
654 Reset any old _WAKE requests. */
655 cs->halted = 1;
656 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
657 }
658
659 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
660 {
661 CPUMIPSState *c = &cpu->env;
662
663 /* FIXME: TC reschedule. */
664 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
665 mips_vpe_wake(cpu);
666 }
667 }
668
669 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
670 {
671 CPUMIPSState *c = &cpu->env;
672
673 /* FIXME: TC reschedule. */
674 if (!mips_vpe_active(c)) {
675 mips_vpe_sleep(cpu);
676 }
677 }
678
679 /**
680 * mips_cpu_map_tc:
681 * @env: CPU from which mapping is performed.
682 * @tc: Should point to an int with the value of the global TC index.
683 *
684 * This function will transform @tc into a local index within the
685 * returned #CPUMIPSState.
686 */
687 /* FIXME: This code assumes that all VPEs have the same number of TCs,
688 which depends on runtime setup. Can probably be fixed by
689 walking the list of CPUMIPSStates. */
690 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
691 {
692 MIPSCPU *cpu;
693 CPUState *cs;
694 CPUState *other_cs;
695 int vpe_idx;
696 int tc_idx = *tc;
697
698 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
699 /* Not allowed to address other CPUs. */
700 *tc = env->current_tc;
701 return env;
702 }
703
704 cs = env_cpu(env);
705 vpe_idx = tc_idx / cs->nr_threads;
706 *tc = tc_idx % cs->nr_threads;
707 other_cs = qemu_get_cpu(vpe_idx);
708 if (other_cs == NULL) {
709 return env;
710 }
711 cpu = MIPS_CPU(other_cs);
712 return &cpu->env;
713 }
714
715 /* The per VPE CP0_Status register shares some fields with the per TC
716 CP0_TCStatus registers. These fields are wired to the same registers,
717 so changes to either of them should be reflected on both registers.
718
719 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
720
721 These helper call synchronizes the regs for a given cpu. */
722
723 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
724 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
725 int tc); */
726
727 /* Called for updates to CP0_TCStatus. */
728 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
729 target_ulong v)
730 {
731 uint32_t status;
732 uint32_t tcu, tmx, tasid, tksu;
733 uint32_t mask = ((1U << CP0St_CU3)
734 | (1 << CP0St_CU2)
735 | (1 << CP0St_CU1)
736 | (1 << CP0St_CU0)
737 | (1 << CP0St_MX)
738 | (3 << CP0St_KSU));
739
740 tcu = (v >> CP0TCSt_TCU0) & 0xf;
741 tmx = (v >> CP0TCSt_TMX) & 0x1;
742 tasid = v & cpu->CP0_EntryHi_ASID_mask;
743 tksu = (v >> CP0TCSt_TKSU) & 0x3;
744
745 status = tcu << CP0St_CU0;
746 status |= tmx << CP0St_MX;
747 status |= tksu << CP0St_KSU;
748
749 cpu->CP0_Status &= ~mask;
750 cpu->CP0_Status |= status;
751
752 /* Sync the TASID with EntryHi. */
753 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
754 cpu->CP0_EntryHi |= tasid;
755
756 compute_hflags(cpu);
757 }
758
759 /* Called for updates to CP0_EntryHi. */
760 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
761 {
762 int32_t *tcst;
763 uint32_t asid, v = cpu->CP0_EntryHi;
764
765 asid = v & cpu->CP0_EntryHi_ASID_mask;
766
767 if (tc == cpu->current_tc) {
768 tcst = &cpu->active_tc.CP0_TCStatus;
769 } else {
770 tcst = &cpu->tcs[tc].CP0_TCStatus;
771 }
772
773 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
774 *tcst |= asid;
775 }
776
777 /* CP0 helpers */
778 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
779 {
780 return env->mvp->CP0_MVPControl;
781 }
782
783 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
784 {
785 return env->mvp->CP0_MVPConf0;
786 }
787
788 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
789 {
790 return env->mvp->CP0_MVPConf1;
791 }
792
793 target_ulong helper_mfc0_random(CPUMIPSState *env)
794 {
795 return (int32_t)cpu_mips_get_random(env);
796 }
797
798 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
799 {
800 return env->active_tc.CP0_TCStatus;
801 }
802
803 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
804 {
805 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
806 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
807
808 if (other_tc == other->current_tc)
809 return other->active_tc.CP0_TCStatus;
810 else
811 return other->tcs[other_tc].CP0_TCStatus;
812 }
813
814 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
815 {
816 return env->active_tc.CP0_TCBind;
817 }
818
819 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
820 {
821 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
822 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
823
824 if (other_tc == other->current_tc)
825 return other->active_tc.CP0_TCBind;
826 else
827 return other->tcs[other_tc].CP0_TCBind;
828 }
829
830 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
831 {
832 return env->active_tc.PC;
833 }
834
835 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
836 {
837 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
838 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
839
840 if (other_tc == other->current_tc)
841 return other->active_tc.PC;
842 else
843 return other->tcs[other_tc].PC;
844 }
845
846 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
847 {
848 return env->active_tc.CP0_TCHalt;
849 }
850
851 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
852 {
853 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
854 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
855
856 if (other_tc == other->current_tc)
857 return other->active_tc.CP0_TCHalt;
858 else
859 return other->tcs[other_tc].CP0_TCHalt;
860 }
861
862 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
863 {
864 return env->active_tc.CP0_TCContext;
865 }
866
867 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
868 {
869 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
870 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
871
872 if (other_tc == other->current_tc)
873 return other->active_tc.CP0_TCContext;
874 else
875 return other->tcs[other_tc].CP0_TCContext;
876 }
877
878 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
879 {
880 return env->active_tc.CP0_TCSchedule;
881 }
882
883 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
884 {
885 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
886 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
887
888 if (other_tc == other->current_tc)
889 return other->active_tc.CP0_TCSchedule;
890 else
891 return other->tcs[other_tc].CP0_TCSchedule;
892 }
893
894 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
895 {
896 return env->active_tc.CP0_TCScheFBack;
897 }
898
899 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
900 {
901 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
902 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
903
904 if (other_tc == other->current_tc)
905 return other->active_tc.CP0_TCScheFBack;
906 else
907 return other->tcs[other_tc].CP0_TCScheFBack;
908 }
909
910 target_ulong helper_mfc0_count(CPUMIPSState *env)
911 {
912 return (int32_t)cpu_mips_get_count(env);
913 }
914
915 target_ulong helper_mfc0_saar(CPUMIPSState *env)
916 {
917 if ((env->CP0_SAARI & 0x3f) < 2) {
918 return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
919 }
920 return 0;
921 }
922
923 target_ulong helper_mfhc0_saar(CPUMIPSState *env)
924 {
925 if ((env->CP0_SAARI & 0x3f) < 2) {
926 return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
927 }
928 return 0;
929 }
930
931 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
932 {
933 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
934 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
935
936 return other->CP0_EntryHi;
937 }
938
939 target_ulong helper_mftc0_cause(CPUMIPSState *env)
940 {
941 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
942 int32_t tccause;
943 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
944
945 if (other_tc == other->current_tc) {
946 tccause = other->CP0_Cause;
947 } else {
948 tccause = other->CP0_Cause;
949 }
950
951 return tccause;
952 }
953
954 target_ulong helper_mftc0_status(CPUMIPSState *env)
955 {
956 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
957 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
958
959 return other->CP0_Status;
960 }
961
962 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
963 {
964 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
965 }
966
967 target_ulong helper_mfc0_maar(CPUMIPSState *env)
968 {
969 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
970 }
971
972 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
973 {
974 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
975 }
976
977 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
978 {
979 return (int32_t)env->CP0_WatchLo[sel];
980 }
981
982 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
983 {
984 return env->CP0_WatchHi[sel];
985 }
986
987 target_ulong helper_mfc0_debug(CPUMIPSState *env)
988 {
989 target_ulong t0 = env->CP0_Debug;
990 if (env->hflags & MIPS_HFLAG_DM)
991 t0 |= 1 << CP0DB_DM;
992
993 return t0;
994 }
995
996 target_ulong helper_mftc0_debug(CPUMIPSState *env)
997 {
998 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
999 int32_t tcstatus;
1000 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1001
1002 if (other_tc == other->current_tc)
1003 tcstatus = other->active_tc.CP0_Debug_tcstatus;
1004 else
1005 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1006
1007 /* XXX: Might be wrong, check with EJTAG spec. */
1008 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1009 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1010 }
1011
1012 #if defined(TARGET_MIPS64)
1013 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1014 {
1015 return env->active_tc.PC;
1016 }
1017
1018 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1019 {
1020 return env->active_tc.CP0_TCHalt;
1021 }
1022
1023 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1024 {
1025 return env->active_tc.CP0_TCContext;
1026 }
1027
1028 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1029 {
1030 return env->active_tc.CP0_TCSchedule;
1031 }
1032
1033 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1034 {
1035 return env->active_tc.CP0_TCScheFBack;
1036 }
1037
1038 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1039 {
1040 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
1041 }
1042
1043 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1044 {
1045 return env->CP0_MAAR[env->CP0_MAARI];
1046 }
1047
1048 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1049 {
1050 return env->CP0_WatchLo[sel];
1051 }
1052
1053 target_ulong helper_dmfc0_saar(CPUMIPSState *env)
1054 {
1055 if ((env->CP0_SAARI & 0x3f) < 2) {
1056 return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
1057 }
1058 return 0;
1059 }
1060 #endif /* TARGET_MIPS64 */
1061
1062 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1063 {
1064 uint32_t index_p = env->CP0_Index & 0x80000000;
1065 uint32_t tlb_index = arg1 & 0x7fffffff;
1066 if (tlb_index < env->tlb->nb_tlb) {
1067 if (env->insn_flags & ISA_MIPS32R6) {
1068 index_p |= arg1 & 0x80000000;
1069 }
1070 env->CP0_Index = index_p | tlb_index;
1071 }
1072 }
1073
1074 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1075 {
1076 uint32_t mask = 0;
1077 uint32_t newval;
1078
1079 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1080 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1081 (1 << CP0MVPCo_EVP);
1082 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1083 mask |= (1 << CP0MVPCo_STLB);
1084 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1085
1086 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1087
1088 env->mvp->CP0_MVPControl = newval;
1089 }
1090
1091 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1092 {
1093 uint32_t mask;
1094 uint32_t newval;
1095
1096 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1097 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1098 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1099
1100 /* Yield scheduler intercept not implemented. */
1101 /* Gating storage scheduler intercept not implemented. */
1102
1103 // TODO: Enable/disable TCs.
1104
1105 env->CP0_VPEControl = newval;
1106 }
1107
1108 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1109 {
1110 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1111 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1112 uint32_t mask;
1113 uint32_t newval;
1114
1115 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1116 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1117 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1118
1119 /* TODO: Enable/disable TCs. */
1120
1121 other->CP0_VPEControl = newval;
1122 }
1123
1124 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1125 {
1126 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1127 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1128 /* FIXME: Mask away return zero on read bits. */
1129 return other->CP0_VPEControl;
1130 }
1131
1132 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1133 {
1134 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1135 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1136
1137 return other->CP0_VPEConf0;
1138 }
1139
1140 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1141 {
1142 uint32_t mask = 0;
1143 uint32_t newval;
1144
1145 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1146 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1147 mask |= (0xff << CP0VPEC0_XTC);
1148 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1149 }
1150 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1151
1152 // TODO: TC exclusive handling due to ERL/EXL.
1153
1154 env->CP0_VPEConf0 = newval;
1155 }
1156
1157 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1158 {
1159 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1160 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1161 uint32_t mask = 0;
1162 uint32_t newval;
1163
1164 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1165 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1166
1167 /* TODO: TC exclusive handling due to ERL/EXL. */
1168 other->CP0_VPEConf0 = newval;
1169 }
1170
1171 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1172 {
1173 uint32_t mask = 0;
1174 uint32_t newval;
1175
1176 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1177 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1178 (0xff << CP0VPEC1_NCP1);
1179 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1180
1181 /* UDI not implemented. */
1182 /* CP2 not implemented. */
1183
1184 // TODO: Handle FPU (CP1) binding.
1185
1186 env->CP0_VPEConf1 = newval;
1187 }
1188
1189 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1190 {
1191 /* Yield qualifier inputs not implemented. */
1192 env->CP0_YQMask = 0x00000000;
1193 }
1194
1195 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1196 {
1197 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1198 }
1199
1200 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1201
1202 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1203 {
1204 /* 1k pages not implemented */
1205 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1206 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1207 | (rxi << (CP0EnLo_XI - 30));
1208 }
1209
1210 #if defined(TARGET_MIPS64)
1211 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1212
1213 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1214 {
1215 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1216 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1217 }
1218 #endif
1219
1220 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1221 {
1222 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1223 uint32_t newval;
1224
1225 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1226
1227 env->active_tc.CP0_TCStatus = newval;
1228 sync_c0_tcstatus(env, env->current_tc, newval);
1229 }
1230
1231 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1232 {
1233 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235
1236 if (other_tc == other->current_tc)
1237 other->active_tc.CP0_TCStatus = arg1;
1238 else
1239 other->tcs[other_tc].CP0_TCStatus = arg1;
1240 sync_c0_tcstatus(other, other_tc, arg1);
1241 }
1242
1243 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1244 {
1245 uint32_t mask = (1 << CP0TCBd_TBE);
1246 uint32_t newval;
1247
1248 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1249 mask |= (1 << CP0TCBd_CurVPE);
1250 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1251 env->active_tc.CP0_TCBind = newval;
1252 }
1253
1254 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1255 {
1256 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1257 uint32_t mask = (1 << CP0TCBd_TBE);
1258 uint32_t newval;
1259 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1260
1261 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1262 mask |= (1 << CP0TCBd_CurVPE);
1263 if (other_tc == other->current_tc) {
1264 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1265 other->active_tc.CP0_TCBind = newval;
1266 } else {
1267 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1268 other->tcs[other_tc].CP0_TCBind = newval;
1269 }
1270 }
1271
1272 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1273 {
1274 env->active_tc.PC = arg1;
1275 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1276 env->CP0_LLAddr = 0;
1277 env->lladdr = 0;
1278 /* MIPS16 not implemented. */
1279 }
1280
1281 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1282 {
1283 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1284 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1285
1286 if (other_tc == other->current_tc) {
1287 other->active_tc.PC = arg1;
1288 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1289 other->CP0_LLAddr = 0;
1290 other->lladdr = 0;
1291 /* MIPS16 not implemented. */
1292 } else {
1293 other->tcs[other_tc].PC = arg1;
1294 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1295 other->CP0_LLAddr = 0;
1296 other->lladdr = 0;
1297 /* MIPS16 not implemented. */
1298 }
1299 }
1300
1301 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1302 {
1303 MIPSCPU *cpu = env_archcpu(env);
1304
1305 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1306
1307 // TODO: Halt TC / Restart (if allocated+active) TC.
1308 if (env->active_tc.CP0_TCHalt & 1) {
1309 mips_tc_sleep(cpu, env->current_tc);
1310 } else {
1311 mips_tc_wake(cpu, env->current_tc);
1312 }
1313 }
1314
1315 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1316 {
1317 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1318 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1319 MIPSCPU *other_cpu = env_archcpu(other);
1320
1321 // TODO: Halt TC / Restart (if allocated+active) TC.
1322
1323 if (other_tc == other->current_tc)
1324 other->active_tc.CP0_TCHalt = arg1;
1325 else
1326 other->tcs[other_tc].CP0_TCHalt = arg1;
1327
1328 if (arg1 & 1) {
1329 mips_tc_sleep(other_cpu, other_tc);
1330 } else {
1331 mips_tc_wake(other_cpu, other_tc);
1332 }
1333 }
1334
1335 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1336 {
1337 env->active_tc.CP0_TCContext = arg1;
1338 }
1339
1340 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1341 {
1342 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1343 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1344
1345 if (other_tc == other->current_tc)
1346 other->active_tc.CP0_TCContext = arg1;
1347 else
1348 other->tcs[other_tc].CP0_TCContext = arg1;
1349 }
1350
1351 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1352 {
1353 env->active_tc.CP0_TCSchedule = arg1;
1354 }
1355
1356 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1357 {
1358 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1359 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1360
1361 if (other_tc == other->current_tc)
1362 other->active_tc.CP0_TCSchedule = arg1;
1363 else
1364 other->tcs[other_tc].CP0_TCSchedule = arg1;
1365 }
1366
1367 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1368 {
1369 env->active_tc.CP0_TCScheFBack = arg1;
1370 }
1371
1372 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1373 {
1374 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1375 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1376
1377 if (other_tc == other->current_tc)
1378 other->active_tc.CP0_TCScheFBack = arg1;
1379 else
1380 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1381 }
1382
1383 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1384 {
1385 /* 1k pages not implemented */
1386 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1387 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1388 | (rxi << (CP0EnLo_XI - 30));
1389 }
1390
1391 #if defined(TARGET_MIPS64)
1392 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1393 {
1394 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1395 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1396 }
1397 #endif
1398
1399 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1400 {
1401 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1402 }
1403
1404 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
1405 {
1406 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1407 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1408 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1409 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1410 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1411 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1412 }
1413 }
1414
1415 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1416 {
1417 update_pagemask(env, arg1, &env->CP0_PageMask);
1418 }
1419
1420 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1421 {
1422 /* SmartMIPS not implemented */
1423 /* 1k pages not implemented */
1424 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1425 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1426 compute_hflags(env);
1427 restore_pamask(env);
1428 }
1429
1430 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1431 {
1432 CPUState *cs = env_cpu(env);
1433
1434 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1435 tlb_flush(cs);
1436 }
1437
1438 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1439 {
1440 CPUState *cs = env_cpu(env);
1441
1442 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1443 tlb_flush(cs);
1444 }
1445
1446 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1447 {
1448 CPUState *cs = env_cpu(env);
1449
1450 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1451 tlb_flush(cs);
1452 }
1453
1454 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1455 {
1456 #if defined(TARGET_MIPS64)
1457 uint64_t mask = 0x3F3FFFFFFFULL;
1458 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1459 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1460
1461 if ((env->insn_flags & ISA_MIPS32R6)) {
1462 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1463 mask &= ~(0x3FULL << CP0PF_BDI);
1464 }
1465 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1466 mask &= ~(0x3FULL << CP0PF_GDI);
1467 }
1468 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1469 mask &= ~(0x3FULL << CP0PF_UDI);
1470 }
1471 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1472 mask &= ~(0x3FULL << CP0PF_MDI);
1473 }
1474 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1475 mask &= ~(0x3FULL << CP0PF_PTI);
1476 }
1477 }
1478 env->CP0_PWField = arg1 & mask;
1479
1480 if ((new_ptei >= 32) ||
1481 ((env->insn_flags & ISA_MIPS32R6) &&
1482 (new_ptei == 0 || new_ptei == 1))) {
1483 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1484 (old_ptei << CP0PF_PTEI);
1485 }
1486 #else
1487 uint32_t mask = 0x3FFFFFFF;
1488 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1489 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1490
1491 if ((env->insn_flags & ISA_MIPS32R6)) {
1492 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1493 mask &= ~(0x3F << CP0PF_GDW);
1494 }
1495 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1496 mask &= ~(0x3F << CP0PF_UDW);
1497 }
1498 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1499 mask &= ~(0x3F << CP0PF_MDW);
1500 }
1501 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1502 mask &= ~(0x3F << CP0PF_PTW);
1503 }
1504 }
1505 env->CP0_PWField = arg1 & mask;
1506
1507 if ((new_ptew >= 32) ||
1508 ((env->insn_flags & ISA_MIPS32R6) &&
1509 (new_ptew == 0 || new_ptew == 1))) {
1510 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1511 (old_ptew << CP0PF_PTEW);
1512 }
1513 #endif
1514 }
1515
1516 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1517 {
1518 #if defined(TARGET_MIPS64)
1519 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1520 #else
1521 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1522 #endif
1523 }
1524
1525 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1526 {
1527 if (env->insn_flags & ISA_MIPS32R6) {
1528 if (arg1 < env->tlb->nb_tlb) {
1529 env->CP0_Wired = arg1;
1530 }
1531 } else {
1532 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1533 }
1534 }
1535
1536 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1537 {
1538 #if defined(TARGET_MIPS64)
1539 /* PWEn = 0. Hardware page table walking is not implemented. */
1540 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1541 #else
1542 env->CP0_PWCtl = (arg1 & 0x800000FF);
1543 #endif
1544 }
1545
1546 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1547 {
1548 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1549 }
1550
1551 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1552 {
1553 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1554 }
1555
1556 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1557 {
1558 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1559 }
1560
1561 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1562 {
1563 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1564 }
1565
1566 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1567 {
1568 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1569 }
1570
1571 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1572 {
1573 uint32_t mask = 0x0000000F;
1574
1575 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1576 (env->insn_flags & ISA_MIPS32R6)) {
1577 mask |= (1 << 4);
1578 }
1579 if (env->insn_flags & ISA_MIPS32R6) {
1580 mask |= (1 << 5);
1581 }
1582 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1583 mask |= (1 << 29);
1584
1585 if (arg1 & (1 << 29)) {
1586 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1587 } else {
1588 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1589 }
1590 }
1591
1592 env->CP0_HWREna = arg1 & mask;
1593 }
1594
1595 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1596 {
1597 cpu_mips_store_count(env, arg1);
1598 }
1599
1600 void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1601 {
1602 uint32_t target = arg1 & 0x3f;
1603 if (target <= 1) {
1604 env->CP0_SAARI = target;
1605 }
1606 }
1607
1608 void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1609 {
1610 uint32_t target = env->CP0_SAARI & 0x3f;
1611 if (target < 2) {
1612 env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1613 switch (target) {
1614 case 0:
1615 if (env->itu) {
1616 itc_reconfigure(env->itu);
1617 }
1618 break;
1619 }
1620 }
1621 }
1622
1623 void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1624 {
1625 uint32_t target = env->CP0_SAARI & 0x3f;
1626 if (target < 2) {
1627 env->CP0_SAAR[target] =
1628 (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1629 (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1630 switch (target) {
1631 case 0:
1632 if (env->itu) {
1633 itc_reconfigure(env->itu);
1634 }
1635 break;
1636 }
1637 }
1638 }
1639
1640 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1641 {
1642 target_ulong old, val, mask;
1643 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1644 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1645 mask |= 1 << CP0EnHi_EHINV;
1646 }
1647
1648 /* 1k pages not implemented */
1649 #if defined(TARGET_MIPS64)
1650 if (env->insn_flags & ISA_MIPS32R6) {
1651 int entryhi_r = extract64(arg1, 62, 2);
1652 int config0_at = extract32(env->CP0_Config0, 13, 2);
1653 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1654 if ((entryhi_r == 2) ||
1655 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1656 /* skip EntryHi.R field if new value is reserved */
1657 mask &= ~(0x3ull << 62);
1658 }
1659 }
1660 mask &= env->SEGMask;
1661 #endif
1662 old = env->CP0_EntryHi;
1663 val = (arg1 & mask) | (old & ~mask);
1664 env->CP0_EntryHi = val;
1665 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1666 sync_c0_entryhi(env, env->current_tc);
1667 }
1668 /* If the ASID changes, flush qemu's TLB. */
1669 if ((old & env->CP0_EntryHi_ASID_mask) !=
1670 (val & env->CP0_EntryHi_ASID_mask)) {
1671 tlb_flush(env_cpu(env));
1672 }
1673 }
1674
1675 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1676 {
1677 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1678 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1679
1680 other->CP0_EntryHi = arg1;
1681 sync_c0_entryhi(other, other_tc);
1682 }
1683
1684 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1685 {
1686 cpu_mips_store_compare(env, arg1);
1687 }
1688
1689 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1690 {
1691 uint32_t val, old;
1692
1693 old = env->CP0_Status;
1694 cpu_mips_store_status(env, arg1);
1695 val = env->CP0_Status;
1696
1697 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1698 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1699 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1700 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1701 env->CP0_Cause);
1702 switch (cpu_mmu_index(env, false)) {
1703 case 3:
1704 qemu_log(", ERL\n");
1705 break;
1706 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1707 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1708 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1709 default:
1710 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1711 break;
1712 }
1713 }
1714 }
1715
1716 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1717 {
1718 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1719 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1720 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1721
1722 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1723 sync_c0_status(env, other, other_tc);
1724 }
1725
1726 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1727 {
1728 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1729 }
1730
1731 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1732 {
1733 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1734 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1735 }
1736
1737 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1738 {
1739 cpu_mips_store_cause(env, arg1);
1740 }
1741
1742 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1743 {
1744 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1745 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1746
1747 cpu_mips_store_cause(other, arg1);
1748 }
1749
1750 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1751 {
1752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1753 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1754
1755 return other->CP0_EPC;
1756 }
1757
1758 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1759 {
1760 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1761 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1762
1763 return other->CP0_EBase;
1764 }
1765
1766 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1767 {
1768 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1769 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1770 mask |= ~0x3FFFFFFF;
1771 }
1772 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1773 }
1774
1775 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1776 {
1777 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1778 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1779 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1780 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1781 mask |= ~0x3FFFFFFF;
1782 }
1783 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1784 }
1785
1786 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1787 {
1788 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1789 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1790
1791 switch (idx) {
1792 case 0: return other->CP0_Config0;
1793 case 1: return other->CP0_Config1;
1794 case 2: return other->CP0_Config2;
1795 case 3: return other->CP0_Config3;
1796 /* 4 and 5 are reserved. */
1797 case 6: return other->CP0_Config6;
1798 case 7: return other->CP0_Config7;
1799 default:
1800 break;
1801 }
1802 return 0;
1803 }
1804
1805 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1806 {
1807 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1808 }
1809
1810 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1811 {
1812 /* tertiary/secondary caches not implemented */
1813 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1814 }
1815
1816 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1817 {
1818 if (env->insn_flags & ASE_MICROMIPS) {
1819 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1820 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1821 }
1822 }
1823
1824 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1825 {
1826 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1827 (arg1 & env->CP0_Config4_rw_bitmask);
1828 }
1829
1830 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1831 {
1832 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1833 (arg1 & env->CP0_Config5_rw_bitmask);
1834 compute_hflags(env);
1835 }
1836
1837 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1838 {
1839 target_long mask = env->CP0_LLAddr_rw_bitmask;
1840 arg1 = arg1 << env->CP0_LLAddr_shift;
1841 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1842 }
1843
1844 #define MTC0_MAAR_MASK(env) \
1845 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1846
1847 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1848 {
1849 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1850 }
1851
1852 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1853 {
1854 env->CP0_MAAR[env->CP0_MAARI] =
1855 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1856 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1857 }
1858
1859 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1860 {
1861 int index = arg1 & 0x3f;
1862 if (index == 0x3f) {
1863 /* Software may write all ones to INDEX to determine the
1864 maximum value supported. */
1865 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1866 } else if (index < MIPS_MAAR_MAX) {
1867 env->CP0_MAARI = index;
1868 }
1869 /* Other than the all ones, if the
1870 value written is not supported, then INDEX is unchanged
1871 from its previous value. */
1872 }
1873
1874 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1875 {
1876 /* Watch exceptions for instructions, data loads, data stores
1877 not implemented. */
1878 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1879 }
1880
1881 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1882 {
1883 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1884 env->CP0_WatchHi[sel] = arg1 & mask;
1885 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1886 }
1887
1888 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1889 {
1890 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1891 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1892 }
1893
1894 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1895 {
1896 env->CP0_Framemask = arg1; /* XXX */
1897 }
1898
1899 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1900 {
1901 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1902 if (arg1 & (1 << CP0DB_DM))
1903 env->hflags |= MIPS_HFLAG_DM;
1904 else
1905 env->hflags &= ~MIPS_HFLAG_DM;
1906 }
1907
1908 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1909 {
1910 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1911 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1912 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1913
1914 /* XXX: Might be wrong, check with EJTAG spec. */
1915 if (other_tc == other->current_tc)
1916 other->active_tc.CP0_Debug_tcstatus = val;
1917 else
1918 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1919 other->CP0_Debug = (other->CP0_Debug &
1920 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1921 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1922 }
1923
1924 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1925 {
1926 env->CP0_Performance0 = arg1 & 0x000007ff;
1927 }
1928
1929 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1930 {
1931 int32_t wst = arg1 & (1 << CP0EC_WST);
1932 int32_t spr = arg1 & (1 << CP0EC_SPR);
1933 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1934
1935 env->CP0_ErrCtl = wst | spr | itc;
1936
1937 if (itc && !wst && !spr) {
1938 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1939 } else {
1940 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1941 }
1942 }
1943
1944 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1945 {
1946 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1947 /* If CACHE instruction is configured for ITC tags then make all
1948 CP0.TagLo bits writable. The actual write to ITC Configuration
1949 Tag will take care of the read-only bits. */
1950 env->CP0_TagLo = arg1;
1951 } else {
1952 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1953 }
1954 }
1955
1956 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1957 {
1958 env->CP0_DataLo = arg1; /* XXX */
1959 }
1960
1961 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1962 {
1963 env->CP0_TagHi = arg1; /* XXX */
1964 }
1965
1966 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1967 {
1968 env->CP0_DataHi = arg1; /* XXX */
1969 }
1970
1971 /* MIPS MT functions */
1972 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1973 {
1974 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1975 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1976
1977 if (other_tc == other->current_tc)
1978 return other->active_tc.gpr[sel];
1979 else
1980 return other->tcs[other_tc].gpr[sel];
1981 }
1982
1983 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1984 {
1985 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1986 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1987
1988 if (other_tc == other->current_tc)
1989 return other->active_tc.LO[sel];
1990 else
1991 return other->tcs[other_tc].LO[sel];
1992 }
1993
1994 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1995 {
1996 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1997 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1998
1999 if (other_tc == other->current_tc)
2000 return other->active_tc.HI[sel];
2001 else
2002 return other->tcs[other_tc].HI[sel];
2003 }
2004
2005 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
2006 {
2007 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2008 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2009
2010 if (other_tc == other->current_tc)
2011 return other->active_tc.ACX[sel];
2012 else
2013 return other->tcs[other_tc].ACX[sel];
2014 }
2015
2016 target_ulong helper_mftdsp(CPUMIPSState *env)
2017 {
2018 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2019 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2020
2021 if (other_tc == other->current_tc)
2022 return other->active_tc.DSPControl;
2023 else
2024 return other->tcs[other_tc].DSPControl;
2025 }
2026
2027 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2028 {
2029 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2030 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2031
2032 if (other_tc == other->current_tc)
2033 other->active_tc.gpr[sel] = arg1;
2034 else
2035 other->tcs[other_tc].gpr[sel] = arg1;
2036 }
2037
2038 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2039 {
2040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2041 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2042
2043 if (other_tc == other->current_tc)
2044 other->active_tc.LO[sel] = arg1;
2045 else
2046 other->tcs[other_tc].LO[sel] = arg1;
2047 }
2048
2049 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2050 {
2051 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2052 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2053
2054 if (other_tc == other->current_tc)
2055 other->active_tc.HI[sel] = arg1;
2056 else
2057 other->tcs[other_tc].HI[sel] = arg1;
2058 }
2059
2060 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2061 {
2062 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2063 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2064
2065 if (other_tc == other->current_tc)
2066 other->active_tc.ACX[sel] = arg1;
2067 else
2068 other->tcs[other_tc].ACX[sel] = arg1;
2069 }
2070
2071 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2072 {
2073 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2074 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2075
2076 if (other_tc == other->current_tc)
2077 other->active_tc.DSPControl = arg1;
2078 else
2079 other->tcs[other_tc].DSPControl = arg1;
2080 }
2081
2082 /* MIPS MT functions */
2083 target_ulong helper_dmt(void)
2084 {
2085 // TODO
2086 return 0;
2087 }
2088
2089 target_ulong helper_emt(void)
2090 {
2091 // TODO
2092 return 0;
2093 }
2094
2095 target_ulong helper_dvpe(CPUMIPSState *env)
2096 {
2097 CPUState *other_cs = first_cpu;
2098 target_ulong prev = env->mvp->CP0_MVPControl;
2099
2100 CPU_FOREACH(other_cs) {
2101 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2102 /* Turn off all VPEs except the one executing the dvpe. */
2103 if (&other_cpu->env != env) {
2104 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2105 mips_vpe_sleep(other_cpu);
2106 }
2107 }
2108 return prev;
2109 }
2110
2111 target_ulong helper_evpe(CPUMIPSState *env)
2112 {
2113 CPUState *other_cs = first_cpu;
2114 target_ulong prev = env->mvp->CP0_MVPControl;
2115
2116 CPU_FOREACH(other_cs) {
2117 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2118
2119 if (&other_cpu->env != env
2120 /* If the VPE is WFI, don't disturb its sleep. */
2121 && !mips_vpe_is_wfi(other_cpu)) {
2122 /* Enable the VPE. */
2123 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2124 mips_vpe_wake(other_cpu); /* And wake it up. */
2125 }
2126 }
2127 return prev;
2128 }
2129 #endif /* !CONFIG_USER_ONLY */
2130
2131 void helper_fork(target_ulong arg1, target_ulong arg2)
2132 {
2133 // arg1 = rt, arg2 = rs
2134 // TODO: store to TC register
2135 }
2136
2137 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2138 {
2139 target_long arg1 = arg;
2140
2141 if (arg1 < 0) {
2142 /* No scheduling policy implemented. */
2143 if (arg1 != -2) {
2144 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2145 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2146 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2147 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2148 do_raise_exception(env, EXCP_THREAD, GETPC());
2149 }
2150 }
2151 } else if (arg1 == 0) {
2152 if (0 /* TODO: TC underflow */) {
2153 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2154 do_raise_exception(env, EXCP_THREAD, GETPC());
2155 } else {
2156 // TODO: Deallocate TC
2157 }
2158 } else if (arg1 > 0) {
2159 /* Yield qualifier inputs not implemented. */
2160 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2161 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2162 do_raise_exception(env, EXCP_THREAD, GETPC());
2163 }
2164 return env->CP0_YQMask;
2165 }
2166
2167 /* R6 Multi-threading */
2168 #ifndef CONFIG_USER_ONLY
2169 target_ulong helper_dvp(CPUMIPSState *env)
2170 {
2171 CPUState *other_cs = first_cpu;
2172 target_ulong prev = env->CP0_VPControl;
2173
2174 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2175 CPU_FOREACH(other_cs) {
2176 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2177 /* Turn off all VPs except the one executing the dvp. */
2178 if (&other_cpu->env != env) {
2179 mips_vpe_sleep(other_cpu);
2180 }
2181 }
2182 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2183 }
2184 return prev;
2185 }
2186
2187 target_ulong helper_evp(CPUMIPSState *env)
2188 {
2189 CPUState *other_cs = first_cpu;
2190 target_ulong prev = env->CP0_VPControl;
2191
2192 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2193 CPU_FOREACH(other_cs) {
2194 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2195 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2196 /* If the VP is WFI, don't disturb its sleep.
2197 * Otherwise, wake it up. */
2198 mips_vpe_wake(other_cpu);
2199 }
2200 }
2201 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2202 }
2203 return prev;
2204 }
2205 #endif /* !CONFIG_USER_ONLY */
2206
2207 #ifndef CONFIG_USER_ONLY
2208 /* TLB management */
2209 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
2210 {
2211 /* Discard entries from env->tlb[first] onwards. */
2212 while (env->tlb->tlb_in_use > first) {
2213 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2214 }
2215 }
2216
2217 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2218 {
2219 #if defined(TARGET_MIPS64)
2220 return extract64(entrylo, 6, 54);
2221 #else
2222 return extract64(entrylo, 6, 24) | /* PFN */
2223 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2224 #endif
2225 }
2226
2227 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2228 {
2229 r4k_tlb_t *tlb;
2230 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2231
2232 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2233 tlb = &env->tlb->mmu.r4k.tlb[idx];
2234 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2235 tlb->EHINV = 1;
2236 return;
2237 }
2238 tlb->EHINV = 0;
2239 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2240 #if defined(TARGET_MIPS64)
2241 tlb->VPN &= env->SEGMask;
2242 #endif
2243 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2244 tlb->PageMask = env->CP0_PageMask;
2245 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2246 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2247 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2248 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2249 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2250 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2251 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2252 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2253 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2254 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2255 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2256 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2257 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2258 }
2259
2260 void r4k_helper_tlbinv(CPUMIPSState *env)
2261 {
2262 int idx;
2263 r4k_tlb_t *tlb;
2264 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2265
2266 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2267 tlb = &env->tlb->mmu.r4k.tlb[idx];
2268 if (!tlb->G && tlb->ASID == ASID) {
2269 tlb->EHINV = 1;
2270 }
2271 }
2272 cpu_mips_tlb_flush(env);
2273 }
2274
2275 void r4k_helper_tlbinvf(CPUMIPSState *env)
2276 {
2277 int idx;
2278
2279 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2280 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2281 }
2282 cpu_mips_tlb_flush(env);
2283 }
2284
2285 void r4k_helper_tlbwi(CPUMIPSState *env)
2286 {
2287 r4k_tlb_t *tlb;
2288 int idx;
2289 target_ulong VPN;
2290 uint16_t ASID;
2291 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2292
2293 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2294 tlb = &env->tlb->mmu.r4k.tlb[idx];
2295 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2296 #if defined(TARGET_MIPS64)
2297 VPN &= env->SEGMask;
2298 #endif
2299 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2300 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2301 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2302 V0 = (env->CP0_EntryLo0 & 2) != 0;
2303 D0 = (env->CP0_EntryLo0 & 4) != 0;
2304 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2305 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2306 V1 = (env->CP0_EntryLo1 & 2) != 0;
2307 D1 = (env->CP0_EntryLo1 & 4) != 0;
2308 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2309 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2310
2311 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2312 permissions on the current entry. */
2313 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2314 (!tlb->EHINV && EHINV) ||
2315 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2316 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2317 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2318 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2319 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2320 }
2321
2322 r4k_invalidate_tlb(env, idx, 0);
2323 r4k_fill_tlb(env, idx);
2324 }
2325
2326 void r4k_helper_tlbwr(CPUMIPSState *env)
2327 {
2328 int r = cpu_mips_get_random(env);
2329
2330 r4k_invalidate_tlb(env, r, 1);
2331 r4k_fill_tlb(env, r);
2332 }
2333
2334 void r4k_helper_tlbp(CPUMIPSState *env)
2335 {
2336 r4k_tlb_t *tlb;
2337 target_ulong mask;
2338 target_ulong tag;
2339 target_ulong VPN;
2340 uint16_t ASID;
2341 int i;
2342
2343 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2344 for (i = 0; i < env->tlb->nb_tlb; i++) {
2345 tlb = &env->tlb->mmu.r4k.tlb[i];
2346 /* 1k pages are not supported. */
2347 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2348 tag = env->CP0_EntryHi & ~mask;
2349 VPN = tlb->VPN & ~mask;
2350 #if defined(TARGET_MIPS64)
2351 tag &= env->SEGMask;
2352 #endif
2353 /* Check ASID, virtual page number & size */
2354 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2355 /* TLB match */
2356 env->CP0_Index = i;
2357 break;
2358 }
2359 }
2360 if (i == env->tlb->nb_tlb) {
2361 /* No match. Discard any shadow entries, if any of them match. */
2362 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2363 tlb = &env->tlb->mmu.r4k.tlb[i];
2364 /* 1k pages are not supported. */
2365 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2366 tag = env->CP0_EntryHi & ~mask;
2367 VPN = tlb->VPN & ~mask;
2368 #if defined(TARGET_MIPS64)
2369 tag &= env->SEGMask;
2370 #endif
2371 /* Check ASID, virtual page number & size */
2372 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2373 r4k_mips_tlb_flush_extra (env, i);
2374 break;
2375 }
2376 }
2377
2378 env->CP0_Index |= 0x80000000;
2379 }
2380 }
2381
2382 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2383 {
2384 #if defined(TARGET_MIPS64)
2385 return tlb_pfn << 6;
2386 #else
2387 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2388 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2389 #endif
2390 }
2391
2392 void r4k_helper_tlbr(CPUMIPSState *env)
2393 {
2394 r4k_tlb_t *tlb;
2395 uint16_t ASID;
2396 int idx;
2397
2398 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2399 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2400 tlb = &env->tlb->mmu.r4k.tlb[idx];
2401
2402 /* If this will change the current ASID, flush qemu's TLB. */
2403 if (ASID != tlb->ASID)
2404 cpu_mips_tlb_flush(env);
2405
2406 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2407
2408 if (tlb->EHINV) {
2409 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2410 env->CP0_PageMask = 0;
2411 env->CP0_EntryLo0 = 0;
2412 env->CP0_EntryLo1 = 0;
2413 } else {
2414 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2415 env->CP0_PageMask = tlb->PageMask;
2416 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2417 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2418 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2419 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2420 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2421 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2422 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2423 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2424 }
2425 }
2426
2427 void helper_tlbwi(CPUMIPSState *env)
2428 {
2429 env->tlb->helper_tlbwi(env);
2430 }
2431
2432 void helper_tlbwr(CPUMIPSState *env)
2433 {
2434 env->tlb->helper_tlbwr(env);
2435 }
2436
2437 void helper_tlbp(CPUMIPSState *env)
2438 {
2439 env->tlb->helper_tlbp(env);
2440 }
2441
2442 void helper_tlbr(CPUMIPSState *env)
2443 {
2444 env->tlb->helper_tlbr(env);
2445 }
2446
2447 void helper_tlbinv(CPUMIPSState *env)
2448 {
2449 env->tlb->helper_tlbinv(env);
2450 }
2451
2452 void helper_tlbinvf(CPUMIPSState *env)
2453 {
2454 env->tlb->helper_tlbinvf(env);
2455 }
2456
2457 /* Specials */
2458 target_ulong helper_di(CPUMIPSState *env)
2459 {
2460 target_ulong t0 = env->CP0_Status;
2461
2462 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2463 return t0;
2464 }
2465
2466 target_ulong helper_ei(CPUMIPSState *env)
2467 {
2468 target_ulong t0 = env->CP0_Status;
2469
2470 env->CP0_Status = t0 | (1 << CP0St_IE);
2471 return t0;
2472 }
2473
2474 static void debug_pre_eret(CPUMIPSState *env)
2475 {
2476 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2477 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2478 env->active_tc.PC, env->CP0_EPC);
2479 if (env->CP0_Status & (1 << CP0St_ERL))
2480 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2481 if (env->hflags & MIPS_HFLAG_DM)
2482 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2483 qemu_log("\n");
2484 }
2485 }
2486
2487 static void debug_post_eret(CPUMIPSState *env)
2488 {
2489 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2490 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2491 env->active_tc.PC, env->CP0_EPC);
2492 if (env->CP0_Status & (1 << CP0St_ERL))
2493 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2494 if (env->hflags & MIPS_HFLAG_DM)
2495 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2496 switch (cpu_mmu_index(env, false)) {
2497 case 3:
2498 qemu_log(", ERL\n");
2499 break;
2500 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2501 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2502 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2503 default:
2504 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
2505 break;
2506 }
2507 }
2508 }
2509
2510 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2511 {
2512 env->active_tc.PC = error_pc & ~(target_ulong)1;
2513 if (error_pc & 1) {
2514 env->hflags |= MIPS_HFLAG_M16;
2515 } else {
2516 env->hflags &= ~(MIPS_HFLAG_M16);
2517 }
2518 }
2519
2520 static inline void exception_return(CPUMIPSState *env)
2521 {
2522 debug_pre_eret(env);
2523 if (env->CP0_Status & (1 << CP0St_ERL)) {
2524 set_pc(env, env->CP0_ErrorEPC);
2525 env->CP0_Status &= ~(1 << CP0St_ERL);
2526 } else {
2527 set_pc(env, env->CP0_EPC);
2528 env->CP0_Status &= ~(1 << CP0St_EXL);
2529 }
2530 compute_hflags(env);
2531 debug_post_eret(env);
2532 }
2533
2534 void helper_eret(CPUMIPSState *env)
2535 {
2536 exception_return(env);
2537 env->CP0_LLAddr = 1;
2538 env->lladdr = 1;
2539 }
2540
2541 void helper_eretnc(CPUMIPSState *env)
2542 {
2543 exception_return(env);
2544 }
2545
2546 void helper_deret(CPUMIPSState *env)
2547 {
2548 debug_pre_eret(env);
2549
2550 env->hflags &= ~MIPS_HFLAG_DM;
2551 compute_hflags(env);
2552
2553 set_pc(env, env->CP0_DEPC);
2554
2555 debug_post_eret(env);
2556 }
2557 #endif /* !CONFIG_USER_ONLY */
2558
2559 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2560 {
2561 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2562 return;
2563 }
2564 do_raise_exception(env, EXCP_RI, pc);
2565 }
2566
2567 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2568 {
2569 check_hwrena(env, 0, GETPC());
2570 return env->CP0_EBase & 0x3ff;
2571 }
2572
2573 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2574 {
2575 check_hwrena(env, 1, GETPC());
2576 return env->SYNCI_Step;
2577 }
2578
2579 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2580 {
2581 check_hwrena(env, 2, GETPC());
2582 #ifdef CONFIG_USER_ONLY
2583 return env->CP0_Count;
2584 #else
2585 return (int32_t)cpu_mips_get_count(env);
2586 #endif
2587 }
2588
2589 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2590 {
2591 check_hwrena(env, 3, GETPC());
2592 return env->CCRes;
2593 }
2594
2595 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2596 {
2597 check_hwrena(env, 4, GETPC());
2598 return env->CP0_Performance0;
2599 }
2600
2601 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2602 {
2603 check_hwrena(env, 5, GETPC());
2604 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2605 }
2606
2607 void helper_pmon(CPUMIPSState *env, int function)
2608 {
2609 function /= 2;
2610 switch (function) {
2611 case 2: /* TODO: char inbyte(int waitflag); */
2612 if (env->active_tc.gpr[4] == 0)
2613 env->active_tc.gpr[2] = -1;
2614 /* Fall through */
2615 case 11: /* TODO: char inbyte (void); */
2616 env->active_tc.gpr[2] = -1;
2617 break;
2618 case 3:
2619 case 12:
2620 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2621 break;
2622 case 17:
2623 break;
2624 case 158:
2625 {
2626 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2627 printf("%s", fmt);
2628 }
2629 break;
2630 }
2631 }
2632
2633 void helper_wait(CPUMIPSState *env)
2634 {
2635 CPUState *cs = env_cpu(env);
2636
2637 cs->halted = 1;
2638 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2639 /* Last instruction in the block, PC was updated before
2640 - no need to recover PC and icount */
2641 raise_exception(env, EXCP_HLT);
2642 }
2643
2644 #if !defined(CONFIG_USER_ONLY)
2645
2646 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2647 MMUAccessType access_type,
2648 int mmu_idx, uintptr_t retaddr)
2649 {
2650 MIPSCPU *cpu = MIPS_CPU(cs);
2651 CPUMIPSState *env = &cpu->env;
2652 int error_code = 0;
2653 int excp;
2654
2655 if (!(env->hflags & MIPS_HFLAG_DM)) {
2656 env->CP0_BadVAddr = addr;
2657 }
2658
2659 if (access_type == MMU_DATA_STORE) {
2660 excp = EXCP_AdES;
2661 } else {
2662 excp = EXCP_AdEL;
2663 if (access_type == MMU_INST_FETCH) {
2664 error_code |= EXCP_INST_NOTAVAIL;
2665 }
2666 }
2667
2668 do_raise_exception_err(env, excp, error_code, retaddr);
2669 }
2670
2671 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
2672 vaddr addr, unsigned size,
2673 MMUAccessType access_type,
2674 int mmu_idx, MemTxAttrs attrs,
2675 MemTxResult response, uintptr_t retaddr)
2676 {
2677 MIPSCPU *cpu = MIPS_CPU(cs);
2678 CPUMIPSState *env = &cpu->env;
2679
2680 if (access_type == MMU_INST_FETCH) {
2681 do_raise_exception(env, EXCP_IBE, retaddr);
2682 } else {
2683 do_raise_exception(env, EXCP_DBE, retaddr);
2684 }
2685 }
2686 #endif /* !CONFIG_USER_ONLY */
2687
2688 /* Complex FPU operations which may need stack space. */
2689
2690 #define FLOAT_TWO32 make_float32(1 << 30)
2691 #define FLOAT_TWO64 make_float64(1ULL << 62)
2692
2693 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2694 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2695
2696 /* convert MIPS rounding mode in FCR31 to IEEE library */
2697 unsigned int ieee_rm[] = {
2698 float_round_nearest_even,
2699 float_round_to_zero,
2700 float_round_up,
2701 float_round_down
2702 };
2703
2704 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2705 {
2706 target_ulong arg1 = 0;
2707
2708 switch (reg) {
2709 case 0:
2710 arg1 = (int32_t)env->active_fpu.fcr0;
2711 break;
2712 case 1:
2713 /* UFR Support - Read Status FR */
2714 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2715 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2716 arg1 = (int32_t)
2717 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2718 } else {
2719 do_raise_exception(env, EXCP_RI, GETPC());
2720 }
2721 }
2722 break;
2723 case 5:
2724 /* FRE Support - read Config5.FRE bit */
2725 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2726 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2727 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2728 } else {
2729 helper_raise_exception(env, EXCP_RI);
2730 }
2731 }
2732 break;
2733 case 25:
2734 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2735 break;
2736 case 26:
2737 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2738 break;
2739 case 28:
2740 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2741 break;
2742 default:
2743 arg1 = (int32_t)env->active_fpu.fcr31;
2744 break;
2745 }
2746
2747 return arg1;
2748 }
2749
2750 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2751 {
2752 switch (fs) {
2753 case 1:
2754 /* UFR Alias - Reset Status FR */
2755 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2756 return;
2757 }
2758 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2759 env->CP0_Status &= ~(1 << CP0St_FR);
2760 compute_hflags(env);
2761 } else {
2762 do_raise_exception(env, EXCP_RI, GETPC());
2763 }
2764 break;
2765 case 4:
2766 /* UNFR Alias - Set Status FR */
2767 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2768 return;
2769 }
2770 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2771 env->CP0_Status |= (1 << CP0St_FR);
2772 compute_hflags(env);
2773 } else {
2774 do_raise_exception(env, EXCP_RI, GETPC());
2775 }
2776 break;
2777 case 5:
2778 /* FRE Support - clear Config5.FRE bit */
2779 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2780 return;
2781 }
2782 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2783 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2784 compute_hflags(env);
2785 } else {
2786 helper_raise_exception(env, EXCP_RI);
2787 }
2788 break;
2789 case 6:
2790 /* FRE Support - set Config5.FRE bit */
2791 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2792 return;
2793 }
2794 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2795 env->CP0_Config5 |= (1 << CP0C5_FRE);
2796 compute_hflags(env);
2797 } else {
2798 helper_raise_exception(env, EXCP_RI);
2799 }
2800 break;
2801 case 25:
2802 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2803 return;
2804 }
2805 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2806 ((arg1 & 0x1) << 23);
2807 break;
2808 case 26:
2809 if (arg1 & 0x007c0000)
2810 return;
2811 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2812 break;
2813 case 28:
2814 if (arg1 & 0x007c0000)
2815 return;
2816 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2817 ((arg1 & 0x4) << 22);
2818 break;
2819 case 31:
2820 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2821 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2822 break;
2823 default:
2824 if (env->insn_flags & ISA_MIPS32R6) {
2825 do_raise_exception(env, EXCP_RI, GETPC());
2826 }
2827 return;
2828 }
2829 restore_fp_status(env);
2830 set_float_exception_flags(0, &env->active_fpu.fp_status);
2831 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2832 do_raise_exception(env, EXCP_FPE, GETPC());
2833 }
2834
2835 int ieee_ex_to_mips(int xcpt)
2836 {
2837 int ret = 0;
2838 if (xcpt) {
2839 if (xcpt & float_flag_invalid) {
2840 ret |= FP_INVALID;
2841 }
2842 if (xcpt & float_flag_overflow) {
2843 ret |= FP_OVERFLOW;
2844 }
2845 if (xcpt & float_flag_underflow) {
2846 ret |= FP_UNDERFLOW;
2847 }
2848 if (xcpt & float_flag_divbyzero) {
2849 ret |= FP_DIV0;
2850 }
2851 if (xcpt & float_flag_inexact) {
2852 ret |= FP_INEXACT;
2853 }
2854 }
2855 return ret;
2856 }
2857
2858 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2859 {
2860 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2861
2862 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2863
2864 if (tmp) {
2865 set_float_exception_flags(0, &env->active_fpu.fp_status);
2866
2867 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2868 do_raise_exception(env, EXCP_FPE, pc);
2869 } else {
2870 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2871 }
2872 }
2873 }
2874
2875 /* Float support.
2876 Single precition routines have a "s" suffix, double precision a
2877 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2878 paired single lower "pl", paired single upper "pu". */
2879
2880 /* unary operations, modifying fp status */
2881 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2882 {
2883 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2884 update_fcr31(env, GETPC());
2885 return fdt0;
2886 }
2887
2888 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2889 {
2890 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2891 update_fcr31(env, GETPC());
2892 return fst0;
2893 }
2894
2895 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2896 {
2897 uint64_t fdt2;
2898
2899 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2900 update_fcr31(env, GETPC());
2901 return fdt2;
2902 }
2903
2904 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2905 {
2906 uint64_t fdt2;
2907
2908 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2909 update_fcr31(env, GETPC());
2910 return fdt2;
2911 }
2912
2913 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2914 {
2915 uint64_t fdt2;
2916
2917 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2918 update_fcr31(env, GETPC());
2919 return fdt2;
2920 }
2921
2922 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2923 {
2924 uint64_t dt2;
2925
2926 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2927 if (get_float_exception_flags(&env->active_fpu.fp_status)
2928 & (float_flag_invalid | float_flag_overflow)) {
2929 dt2 = FP_TO_INT64_OVERFLOW;
2930 }
2931 update_fcr31(env, GETPC());
2932 return dt2;
2933 }
2934
2935 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2936 {
2937 uint64_t dt2;
2938
2939 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2940 if (get_float_exception_flags(&env->active_fpu.fp_status)
2941 & (float_flag_invalid | float_flag_overflow)) {
2942 dt2 = FP_TO_INT64_OVERFLOW;
2943 }
2944 update_fcr31(env, GETPC());
2945 return dt2;
2946 }
2947
2948 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2949 {
2950 uint32_t fst2;
2951 uint32_t fsth2;
2952
2953 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2954 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2955 update_fcr31(env, GETPC());
2956 return ((uint64_t)fsth2 << 32) | fst2;
2957 }
2958
2959 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2960 {
2961 uint32_t wt2;
2962 uint32_t wth2;
2963 int excp, excph;
2964
2965 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2966 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2967 if (excp & (float_flag_overflow | float_flag_invalid)) {
2968 wt2 = FP_TO_INT32_OVERFLOW;
2969 }
2970
2971 set_float_exception_flags(0, &env->active_fpu.fp_status);
2972 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2973 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2974 if (excph & (float_flag_overflow | float_flag_invalid)) {
2975 wth2 = FP_TO_INT32_OVERFLOW;
2976 }
2977
2978 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2979 update_fcr31(env, GETPC());
2980
2981 return ((uint64_t)wth2 << 32) | wt2;
2982 }
2983
2984 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2985 {
2986 uint32_t fst2;
2987
2988 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2989 update_fcr31(env, GETPC());
2990 return fst2;
2991 }
2992
2993 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2994 {
2995 uint32_t fst2;
2996
2997 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2998 update_fcr31(env, GETPC());
2999 return fst2;
3000 }
3001
3002 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
3003 {
3004 uint32_t fst2;
3005
3006 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
3007 update_fcr31(env, GETPC());
3008 return fst2;
3009 }
3010
3011 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
3012 {
3013 uint32_t wt2;
3014
3015 wt2 = wt0;
3016 update_fcr31(env, GETPC());
3017 return wt2;
3018 }
3019
3020 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
3021 {
3022 uint32_t wt2;
3023
3024 wt2 = wth0;
3025 update_fcr31(env, GETPC());
3026 return wt2;
3027 }
3028
3029 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3030 {
3031 uint32_t wt2;
3032
3033 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3034 if (get_float_exception_flags(&env->active_fpu.fp_status)
3035 & (float_flag_invalid | float_flag_overflow)) {
3036 wt2 = FP_TO_INT32_OVERFLOW;
3037 }
3038 update_fcr31(env, GETPC());
3039 return wt2;
3040 }
3041
3042 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3043 {
3044 uint32_t wt2;
3045
3046 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3047 if (get_float_exception_flags(&env->active_fpu.fp_status)
3048 & (float_flag_invalid | float_flag_overflow)) {
3049 wt2 = FP_TO_INT32_OVERFLOW;
3050 }
3051 update_fcr31(env, GETPC());
3052 return wt2;
3053 }
3054
3055 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3056 {
3057 uint64_t dt2;
3058
3059 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3060 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3061 restore_rounding_mode(env);
3062 if (get_float_exception_flags(&env->active_fpu.fp_status)
3063 & (float_flag_invalid | float_flag_overflow)) {
3064 dt2 = FP_TO_INT64_OVERFLOW;
3065 }
3066 update_fcr31(env, GETPC());
3067 return dt2;
3068 }
3069
3070 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3071 {
3072 uint64_t dt2;
3073
3074 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3075 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3076 restore_rounding_mode(env);
3077 if (get_float_exception_flags(&env->active_fpu.fp_status)
3078 & (float_flag_invalid | float_flag_overflow)) {
3079 dt2 = FP_TO_INT64_OVERFLOW;
3080 }
3081 update_fcr31(env, GETPC());
3082 return dt2;
3083 }
3084
3085 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3086 {
3087 uint32_t wt2;
3088
3089 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3090 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3091 restore_rounding_mode(env);
3092 if (get_float_exception_flags(&env->active_fpu.fp_status)
3093 & (float_flag_invalid | float_flag_overflow)) {
3094 wt2 = FP_TO_INT32_OVERFLOW;
3095 }
3096 update_fcr31(env, GETPC());
3097 return wt2;
3098 }
3099
3100 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3101 {
3102 uint32_t wt2;
3103
3104 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3105 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3106 restore_rounding_mode(env);
3107 if (get_float_exception_flags(&env->active_fpu.fp_status)
3108 & (float_flag_invalid | float_flag_overflow)) {
3109 wt2 = FP_TO_INT32_OVERFLOW;
3110 }
3111 update_fcr31(env, GETPC());
3112 return wt2;
3113 }
3114
3115 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3116 {
3117 uint64_t dt2;
3118
3119 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3120 if (get_float_exception_flags(&env->active_fpu.fp_status)
3121 & (float_flag_invalid | float_flag_overflow)) {
3122 dt2 = FP_TO_INT64_OVERFLOW;
3123 }
3124 update_fcr31(env, GETPC());
3125 return dt2;
3126 }
3127
3128 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3129 {
3130 uint64_t dt2;
3131
3132 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3133 if (get_float_exception_flags(&env->active_fpu.fp_status)
3134 & (float_flag_invalid | float_flag_overflow)) {
3135 dt2 = FP_TO_INT64_OVERFLOW;
3136 }
3137 update_fcr31(env, GETPC());
3138 return dt2;
3139 }
3140
3141 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3142 {
3143 uint32_t wt2;
3144
3145 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3146 if (get_float_exception_flags(&env->active_fpu.fp_status)
3147 & (float_flag_invalid | float_flag_overflow)) {
3148 wt2 = FP_TO_INT32_OVERFLOW;
3149 }
3150 update_fcr31(env, GETPC());
3151 return wt2;
3152 }
3153
3154 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3155 {
3156 uint32_t wt2;
3157
3158 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3159 if (get_float_exception_flags(&env->active_fpu.fp_status)
3160 & (float_flag_invalid | float_flag_overflow)) {
3161 wt2 = FP_TO_INT32_OVERFLOW;
3162 }
3163 update_fcr31(env, GETPC());
3164 return wt2;
3165 }
3166
3167 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3168 {
3169 uint64_t dt2;
3170
3171 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3172 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3173 restore_rounding_mode(env);
3174 if (get_float_exception_flags(&env->active_fpu.fp_status)
3175 & (float_flag_invalid | float_flag_overflow)) {
3176 dt2 = FP_TO_INT64_OVERFLOW;
3177 }
3178 update_fcr31(env, GETPC());
3179 return dt2;
3180 }
3181
3182 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3183 {
3184 uint64_t dt2;
3185
3186 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3187 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3188 restore_rounding_mode(env);
3189 if (get_float_exception_flags(&env->active_fpu.fp_status)
3190 & (float_flag_invalid | float_flag_overflow)) {
3191 dt2 = FP_TO_INT64_OVERFLOW;
3192 }
3193 update_fcr31(env, GETPC());
3194 return dt2;
3195 }
3196
3197 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3198 {
3199 uint32_t wt2;
3200
3201 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3202 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3203 restore_rounding_mode(env);
3204 if (get_float_exception_flags(&env->active_fpu.fp_status)
3205 & (float_flag_invalid | float_flag_overflow)) {
3206 wt2 = FP_TO_INT32_OVERFLOW;
3207 }
3208 update_fcr31(env, GETPC());
3209 return wt2;
3210 }
3211
3212 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3213 {
3214 uint32_t wt2;
3215
3216 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3217 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3218 restore_rounding_mode(env);
3219 if (get_float_exception_flags(&env->active_fpu.fp_status)
3220 & (float_flag_invalid | float_flag_overflow)) {
3221 wt2 = FP_TO_INT32_OVERFLOW;
3222 }
3223 update_fcr31(env, GETPC());
3224 return wt2;
3225 }
3226
3227 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3228 {
3229 uint64_t dt2;
3230
3231 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3232 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3233 restore_rounding_mode(env);
3234 if (get_float_exception_flags(&env->active_fpu.fp_status)
3235 & (float_flag_invalid | float_flag_overflow)) {
3236 dt2 = FP_TO_INT64_OVERFLOW;
3237 }
3238 update_fcr31(env, GETPC());
3239 return dt2;
3240 }
3241
3242 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3243 {
3244 uint64_t dt2;
3245
3246 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3247 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3248 restore_rounding_mode(env);
3249 if (get_float_exception_flags(&env->active_fpu.fp_status)
3250 & (float_flag_invalid | float_flag_overflow)) {
3251 dt2 = FP_TO_INT64_OVERFLOW;
3252 }
3253 update_fcr31(env, GETPC());
3254 return dt2;
3255 }
3256
3257 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3258 {
3259 uint32_t wt2;
3260
3261 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3262 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3263 restore_rounding_mode(env);
3264 if (get_float_exception_flags(&env->active_fpu.fp_status)
3265 & (float_flag_invalid | float_flag_overflow)) {
3266 wt2 = FP_TO_INT32_OVERFLOW;
3267 }
3268 update_fcr31(env, GETPC());
3269 return wt2;
3270 }
3271
3272 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3273 {
3274 uint32_t wt2;
3275
3276 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3277 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3278 restore_rounding_mode(env);
3279 if (get_float_exception_flags(&env->active_fpu.fp_status)
3280 & (float_flag_invalid | float_flag_overflow)) {
3281 wt2 = FP_TO_INT32_OVERFLOW;
3282 }
3283 update_fcr31(env, GETPC());
3284 return wt2;
3285 }
3286
3287 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3288 {
3289 uint64_t dt2;
3290
3291 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3292 if (get_float_exception_flags(&env->active_fpu.fp_status)
3293 & float_flag_invalid) {
3294 if (float64_is_any_nan(fdt0)) {
3295 dt2 = 0;
3296 }
3297 }
3298 update_fcr31(env, GETPC());
3299 return dt2;
3300 }
3301
3302 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3303 {
3304 uint64_t dt2;
3305
3306 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3307 if (get_float_exception_flags(&env->active_fpu.fp_status)
3308 & float_flag_invalid) {
3309 if (float32_is_any_nan(fst0)) {
3310 dt2 = 0;
3311 }
3312 }
3313 update_fcr31(env, GETPC());
3314 return dt2;
3315 }
3316
3317 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3318 {
3319 uint32_t wt2;
3320
3321 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3322 if (get_float_exception_flags(&env->active_fpu.fp_status)
3323 & float_flag_invalid) {
3324 if (float64_is_any_nan(fdt0)) {
3325 wt2 = 0;
3326 }
3327 }
3328 update_fcr31(env, GETPC());
3329 return wt2;
3330 }
3331
3332 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3333 {
3334 uint32_t wt2;
3335
3336 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3337 if (get_float_exception_flags(&env->active_fpu.fp_status)
3338 & float_flag_invalid) {
3339 if (float32_is_any_nan(fst0)) {
3340 wt2 = 0;
3341 }
3342 }
3343 update_fcr31(env, GETPC());
3344 return wt2;
3345 }
3346
3347 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3348 {
3349 uint64_t dt2;
3350
3351 set_float_rounding_mode(float_round_nearest_even,
3352 &env->active_fpu.fp_status);
3353 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3354 restore_rounding_mode(env);
3355 if (get_float_exception_flags(&env->active_fpu.fp_status)
3356 & float_flag_invalid) {
3357 if (float64_is_any_nan(fdt0)) {
3358 dt2 = 0;
3359 }
3360 }
3361 update_fcr31(env, GETPC());
3362 return dt2;
3363 }
3364
3365 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3366 {
3367 uint64_t dt2;
3368
3369 set_float_rounding_mode(float_round_nearest_even,
3370 &env->active_fpu.fp_status);
3371 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3372 restore_rounding_mode(env);
3373 if (get_float_exception_flags(&env->active_fpu.fp_status)
3374 & float_flag_invalid) {
3375 if (float32_is_any_nan(fst0)) {
3376 dt2 = 0;
3377 }
3378 }
3379 update_fcr31(env, GETPC());
3380 return dt2;
3381 }
3382
3383 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3384 {
3385 uint32_t wt2;
3386
3387 set_float_rounding_mode(float_round_nearest_even,
3388 &env->active_fpu.fp_status);
3389 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3390 restore_rounding_mode(env);
3391 if (get_float_exception_flags(&env->active_fpu.fp_status)
3392 & float_flag_invalid) {
3393 if (float64_is_any_nan(fdt0)) {
3394 wt2 = 0;
3395 }
3396 }
3397 update_fcr31(env, GETPC());
3398 return wt2;
3399 }
3400
3401 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3402 {
3403 uint32_t wt2;
3404
3405 set_float_rounding_mode(float_round_nearest_even,
3406 &env->active_fpu.fp_status);
3407 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3408 restore_rounding_mode(env);
3409 if (get_float_exception_flags(&env->active_fpu.fp_status)
3410 & float_flag_invalid) {
3411 if (float32_is_any_nan(fst0)) {
3412 wt2 = 0;
3413 }
3414 }
3415 update_fcr31(env, GETPC());
3416 return wt2;
3417 }
3418
3419 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3420 {
3421 uint64_t dt2;
3422
3423 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3424 if (get_float_exception_flags(&env->active_fpu.fp_status)
3425 & float_flag_invalid) {
3426 if (float64_is_any_nan(fdt0)) {
3427 dt2 = 0;
3428 }
3429 }
3430 update_fcr31(env, GETPC());
3431 return dt2;
3432 }
3433
3434 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3435 {
3436 uint64_t dt2;
3437
3438 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3439 if (get_float_exception_flags(&env->active_fpu.fp_status)
3440 & float_flag_invalid) {
3441 if (float32_is_any_nan(fst0)) {
3442 dt2 = 0;
3443 }
3444 }
3445 update_fcr31(env, GETPC());
3446 return dt2;
3447 }
3448
3449 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3450 {
3451 uint32_t wt2;
3452
3453 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3454 if (get_float_exception_flags(&env->active_fpu.fp_status)
3455 & float_flag_invalid) {
3456 if (float64_is_any_nan(fdt0)) {
3457 wt2 = 0;
3458 }
3459 }
3460 update_fcr31(env, GETPC());
3461 return wt2;
3462 }
3463
3464 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3465 {
3466 uint32_t wt2;
3467
3468 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3469 if (get_float_exception_flags(&env->active_fpu.fp_status)
3470 & float_flag_invalid) {
3471 if (float32_is_any_nan(fst0)) {
3472 wt2 = 0;
3473 }
3474 }
3475 update_fcr31(env, GETPC());
3476 return wt2;
3477 }
3478
3479 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3480 {
3481 uint64_t dt2;
3482
3483 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3484 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3485 restore_rounding_mode(env);
3486 if (get_float_exception_flags(&env->active_fpu.fp_status)
3487 & float_flag_invalid) {
3488 if (float64_is_any_nan(fdt0)) {
3489 dt2 = 0;
3490 }
3491 }
3492 update_fcr31(env, GETPC());
3493 return dt2;
3494 }
3495
3496 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3497 {
3498 uint64_t dt2;
3499
3500 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3501 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3502 restore_rounding_mode(env);
3503 if (get_float_exception_flags(&env->active_fpu.fp_status)
3504 & float_flag_invalid) {
3505 if (float32_is_any_nan(fst0)) {
3506 dt2 = 0;
3507 }
3508 }
3509 update_fcr31(env, GETPC());
3510 return dt2;
3511 }
3512
3513 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3514 {
3515 uint32_t wt2;
3516
3517 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3518 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3519 restore_rounding_mode(env);
3520 if (get_float_exception_flags(&env->active_fpu.fp_status)
3521 & float_flag_invalid) {
3522 if (float64_is_any_nan(fdt0)) {
3523 wt2 = 0;
3524 }
3525 }
3526 update_fcr31(env, GETPC());
3527 return wt2;
3528 }
3529
3530 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3531 {
3532 uint32_t wt2;
3533
3534 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3535 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3536 restore_rounding_mode(env);
3537 if (get_float_exception_flags(&env->active_fpu.fp_status)
3538 & float_flag_invalid) {
3539 if (float32_is_any_nan(fst0)) {
3540 wt2 = 0;
3541 }
3542 }
3543 update_fcr31(env, GETPC());
3544 return wt2;
3545 }
3546
3547 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3548 {
3549 uint64_t dt2;
3550
3551 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3552 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3553 restore_rounding_mode(env);
3554 if (get_float_exception_flags(&env->active_fpu.fp_status)
3555 & float_flag_invalid) {
3556 if (float64_is_any_nan(fdt0)) {
3557 dt2 = 0;
3558 }
3559 }
3560 update_fcr31(env, GETPC());
3561 return dt2;
3562 }
3563
3564 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3565 {
3566 uint64_t dt2;
3567
3568 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3569 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3570 restore_rounding_mode(env);
3571 if (get_float_exception_flags(&env->active_fpu.fp_status)
3572 & float_flag_invalid) {
3573 if (float32_is_any_nan(fst0)) {
3574 dt2 = 0;
3575 }
3576 }
3577 update_fcr31(env, GETPC());
3578 return dt2;
3579 }
3580
3581 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3582 {
3583 uint32_t wt2;
3584
3585 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3586 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3587 restore_rounding_mode(env);
3588 if (get_float_exception_flags(&env->active_fpu.fp_status)
3589 & float_flag_invalid) {
3590 if (float64_is_any_nan(fdt0)) {
3591 wt2 = 0;
3592 }
3593 }
3594 update_fcr31(env, GETPC());
3595 return wt2;
3596 }
3597
3598 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3599 {
3600 uint32_t wt2;
3601
3602 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3603 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3604 restore_rounding_mode(env);
3605 if (get_float_exception_flags(&env->active_fpu.fp_status)
3606 & float_flag_invalid) {
3607 if (float32_is_any_nan(fst0)) {
3608 wt2 = 0;
3609 }
3610 }
3611 update_fcr31(env, GETPC());
3612 return wt2;
3613 }
3614
3615 /* unary operations, not modifying fp status */
3616 #define FLOAT_UNOP(name) \
3617 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3618 { \
3619 return float64_ ## name(fdt0); \
3620 } \
3621 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3622 { \
3623 return float32_ ## name(fst0); \
3624 } \
3625 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3626 { \
3627 uint32_t wt0; \
3628 uint32_t wth0; \
3629 \
3630 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3631 wth0 = float32_ ## name(fdt0 >> 32); \
3632 return ((uint64_t)wth0 << 32) | wt0; \
3633 }
3634 FLOAT_UNOP(abs)
3635 FLOAT_UNOP(chs)
3636 #undef FLOAT_UNOP
3637
3638 /* MIPS specific unary operations */
3639 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3640 {
3641 uint64_t fdt2;
3642
3643 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3644 update_fcr31(env, GETPC());
3645 return fdt2;
3646 }
3647
3648 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3649 {
3650 uint32_t fst2;
3651
3652 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3653 update_fcr31(env, GETPC());
3654 return fst2;
3655 }
3656
3657 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3658 {
3659 uint64_t fdt2;
3660
3661 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3662 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3663 update_fcr31(env, GETPC());
3664 return fdt2;
3665 }
3666
3667 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3668 {
3669 uint32_t fst2;
3670
3671 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3672 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3673 update_fcr31(env, GETPC());
3674 return fst2;
3675 }
3676
3677 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3678 {
3679 uint64_t fdt2;
3680
3681 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3682 update_fcr31(env, GETPC());
3683 return fdt2;
3684 }
3685
3686 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3687 {
3688 uint32_t fst2;
3689
3690 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3691 update_fcr31(env, GETPC());
3692 return fst2;
3693 }
3694
3695 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3696 {
3697 uint32_t fst2;
3698 uint32_t fsth2;
3699
3700 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3701 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3702 update_fcr31(env, GETPC());
3703 return ((uint64_t)fsth2 << 32) | fst2;
3704 }
3705
3706 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3707 {
3708 uint64_t fdt2;
3709
3710 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3711 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3712 update_fcr31(env, GETPC());
3713 return fdt2;
3714 }
3715
3716 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3717 {
3718 uint32_t fst2;
3719
3720 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3721 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3722 update_fcr31(env, GETPC());
3723 return fst2;
3724 }
3725
3726 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3727 {
3728 uint32_t fst2;
3729 uint32_t fsth2;
3730
3731 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3732 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3733 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3734 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3735 update_fcr31(env, GETPC());
3736 return ((uint64_t)fsth2 << 32) | fst2;
3737 }
3738
3739 #define FLOAT_RINT(name, bits) \
3740 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3741 uint ## bits ## _t fs) \
3742 { \
3743 uint ## bits ## _t fdret; \
3744 \
3745 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3746 update_fcr31(env, GETPC()); \
3747 return fdret; \
3748 }
3749
3750 FLOAT_RINT(rint_s, 32)
3751 FLOAT_RINT(rint_d, 64)
3752 #undef FLOAT_RINT
3753
3754 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3755 #define FLOAT_CLASS_QUIET_NAN 0x002
3756 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3757 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3758 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3759 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3760 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3761 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3762 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3763 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3764
3765 #define FLOAT_CLASS(name, bits) \
3766 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3767 float_status *status) \
3768 { \
3769 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3770 return FLOAT_CLASS_SIGNALING_NAN; \
3771 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3772 return FLOAT_CLASS_QUIET_NAN; \
3773 } else if (float ## bits ## _is_neg(arg)) { \
3774 if (float ## bits ## _is_infinity(arg)) { \
3775 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3776 } else if (float ## bits ## _is_zero(arg)) { \
3777 return FLOAT_CLASS_NEGATIVE_ZERO; \
3778 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3779 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3780 } else { \
3781 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3782 } \
3783 } else { \
3784 if (float ## bits ## _is_infinity(arg)) { \
3785 return FLOAT_CLASS_POSITIVE_INFINITY; \
3786 } else if (float ## bits ## _is_zero(arg)) { \
3787 return FLOAT_CLASS_POSITIVE_ZERO; \
3788 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3789 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3790 } else { \
3791 return FLOAT_CLASS_POSITIVE_NORMAL; \
3792 } \
3793 } \
3794 } \
3795 \
3796 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3797 uint ## bits ## _t arg) \
3798 { \
3799 return float_ ## name(arg, &env->active_fpu.fp_status); \
3800 }
3801
3802 FLOAT_CLASS(class_s, 32)
3803 FLOAT_CLASS(class_d, 64)
3804 #undef FLOAT_CLASS
3805
3806 /* binary operations */
3807 #define FLOAT_BINOP(name) \
3808 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3809 uint64_t fdt0, uint64_t fdt1) \
3810 { \
3811 uint64_t dt2; \
3812 \
3813 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3814 update_fcr31(env, GETPC()); \
3815 return dt2; \
3816 } \
3817 \
3818 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3819 uint32_t fst0, uint32_t fst1) \
3820 { \
3821 uint32_t wt2; \
3822 \
3823 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3824 update_fcr31(env, GETPC()); \
3825 return wt2; \
3826 } \
3827 \
3828 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3829 uint64_t fdt0, \
3830 uint64_t fdt1) \
3831 { \
3832 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3833 uint32_t fsth0 = fdt0 >> 32; \
3834 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3835 uint32_t fsth1 = fdt1 >> 32; \
3836 uint32_t wt2; \
3837 uint32_t wth2; \
3838 \
3839 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3840 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3841 update_fcr31(env, GETPC()); \
3842 return ((uint64_t)wth2 << 32) | wt2; \
3843 }
3844
3845 FLOAT_BINOP(add)
3846 FLOAT_BINOP(sub)
3847 FLOAT_BINOP(mul)
3848 FLOAT_BINOP(div)
3849 #undef FLOAT_BINOP
3850
3851 /* MIPS specific binary operations */
3852 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3853 {
3854 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3855 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3856 update_fcr31(env, GETPC());
3857 return fdt2;
3858 }
3859
3860 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3861 {
3862 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3863 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3864 update_fcr31(env, GETPC());
3865 return fst2;
3866 }
3867
3868 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3869 {
3870 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3871 uint32_t fsth0 = fdt0 >> 32;
3872 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3873 uint32_t fsth2 = fdt2 >> 32;
3874
3875 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3876 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3877 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3878 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3879 update_fcr31(env, GETPC());
3880 return ((uint64_t)fsth2 << 32) | fst2;
3881 }
3882
3883 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3884 {
3885 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3886 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3887 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3888 update_fcr31(env, GETPC());
3889 return fdt2;
3890 }
3891
3892 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3893 {
3894 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3895 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3896 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3897 update_fcr31(env, GETPC());
3898 return fst2;
3899 }
3900
3901 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3902 {
3903 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3904 uint32_t fsth0 = fdt0 >> 32;
3905 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3906 uint32_t fsth2 = fdt2 >> 32;
3907
3908 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3909 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3910 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3911 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3912 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3913 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3914 update_fcr31(env, GETPC());
3915 return ((uint64_t)fsth2 << 32) | fst2;
3916 }
3917
3918 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3919 {
3920 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3921 uint32_t fsth0 = fdt0 >> 32;
3922 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3923 uint32_t fsth1 = fdt1 >> 32;
3924 uint32_t fst2;
3925 uint32_t fsth2;
3926
3927 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3928 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3929 update_fcr31(env, GETPC());
3930 return ((uint64_t)fsth2 << 32) | fst2;
3931 }
3932
3933 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3934 {
3935 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3936 uint32_t fsth0 = fdt0 >> 32;
3937 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3938 uint32_t fsth1 = fdt1 >> 32;
3939 uint32_t fst2;
3940 uint32_t fsth2;
3941
3942 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3943 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3944 update_fcr31(env, GETPC());
3945 return ((uint64_t)fsth2 << 32) | fst2;
3946 }
3947
3948 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3949 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3950 uint ## bits ## _t fs, \
3951 uint ## bits ## _t ft) \
3952 { \
3953 uint ## bits ## _t fdret; \
3954 \
3955 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3956 &env->active_fpu.fp_status); \
3957 update_fcr31(env, GETPC()); \
3958 return fdret; \
3959 }
3960
3961 FLOAT_MINMAX(max_s, 32, maxnum)
3962 FLOAT_MINMAX(max_d, 64, maxnum)
3963 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3964 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3965
3966 FLOAT_MINMAX(min_s, 32, minnum)
3967 FLOAT_MINMAX(min_d, 64, minnum)
3968 FLOAT_MINMAX(mina_s, 32, minnummag)
3969 FLOAT_MINMAX(mina_d, 64, minnummag)
3970 #undef FLOAT_MINMAX
3971
3972 /* ternary operations */
3973 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3974 { \
3975 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3976 if ((flags) & float_muladd_negate_c) { \
3977 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3978 } else { \
3979 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3980 } \
3981 if ((flags) & float_muladd_negate_result) { \
3982 a = prefix##_chs(a); \
3983 } \
3984 }
3985
3986 /* FMA based operations */
3987 #define FLOAT_FMA(name, type) \
3988 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3989 uint64_t fdt0, uint64_t fdt1, \
3990 uint64_t fdt2) \
3991 { \
3992 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3993 update_fcr31(env, GETPC()); \
3994 return fdt0; \
3995 } \
3996 \
3997 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3998 uint32_t fst0, uint32_t fst1, \
3999 uint32_t fst2) \
4000 { \
4001 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4002 update_fcr31(env, GETPC()); \
4003 return fst0; \
4004 } \
4005 \
4006 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4007 uint64_t fdt0, uint64_t fdt1, \
4008 uint64_t fdt2) \
4009 { \
4010 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4011 uint32_t fsth0 = fdt0 >> 32; \
4012 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4013 uint32_t fsth1 = fdt1 >> 32; \
4014 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4015 uint32_t fsth2 = fdt2 >> 32; \
4016 \
4017 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4018 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4019 update_fcr31(env, GETPC()); \
4020 return ((uint64_t)fsth0 << 32) | fst0; \
4021 }
4022 FLOAT_FMA(madd, 0)
4023 FLOAT_FMA(msub, float_muladd_negate_c)
4024 FLOAT_FMA(nmadd, float_muladd_negate_result)
4025 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
4026 #undef FLOAT_FMA
4027
4028 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4029 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4030 uint ## bits ## _t fs, \
4031 uint ## bits ## _t ft, \
4032 uint ## bits ## _t fd) \
4033 { \
4034 uint ## bits ## _t fdret; \
4035 \
4036 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4037 &env->active_fpu.fp_status); \
4038 update_fcr31(env, GETPC()); \
4039 return fdret; \
4040 }
4041
4042 FLOAT_FMADDSUB(maddf_s, 32, 0)
4043 FLOAT_FMADDSUB(maddf_d, 64, 0)
4044 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4045 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4046 #undef FLOAT_FMADDSUB
4047
4048 /* compare operations */
4049 #define FOP_COND_D(op, cond) \
4050 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4051 uint64_t fdt1, int cc) \
4052 { \
4053 int c; \
4054 c = cond; \
4055 update_fcr31(env, GETPC()); \
4056 if (c) \
4057 SET_FP_COND(cc, env->active_fpu); \
4058 else \
4059 CLEAR_FP_COND(cc, env->active_fpu); \
4060 } \
4061 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4062 uint64_t fdt1, int cc) \
4063 { \
4064 int c; \
4065 fdt0 = float64_abs(fdt0); \
4066 fdt1 = float64_abs(fdt1); \
4067 c = cond; \
4068 update_fcr31(env, GETPC()); \
4069 if (c) \
4070 SET_FP_COND(cc, env->active_fpu); \
4071 else \
4072 CLEAR_FP_COND(cc, env->active_fpu); \
4073 }
4074
4075 /* NOTE: the comma operator will make "cond" to eval to false,
4076 * but float64_unordered_quiet() is still called. */
4077 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4078 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
4079 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4080 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4081 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4082 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4083 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4084 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4085 /* NOTE: the comma operator will make "cond" to eval to false,
4086 * but float64_unordered() is still called. */
4087 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4088 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
4089 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4090 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4091 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4092 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4093 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4094 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4095
4096 #define FOP_COND_S(op, cond) \
4097 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4098 uint32_t fst1, int cc) \
4099 { \
4100 int c; \
4101 c = cond; \
4102 update_fcr31(env, GETPC()); \
4103 if (c) \
4104 SET_FP_COND(cc, env->active_fpu); \
4105 else \
4106 CLEAR_FP_COND(cc, env->active_fpu); \
4107 } \
4108 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4109 uint32_t fst1, int cc) \
4110 { \
4111 int c; \
4112 fst0 = float32_abs(fst0); \
4113 fst1 = float32_abs(fst1); \
4114 c = cond; \
4115 update_fcr31(env, GETPC()); \
4116 if (c) \
4117 SET_FP_COND(cc, env->active_fpu); \
4118 else \
4119 CLEAR_FP_COND(cc, env->active_fpu); \
4120 }
4121
4122 /* NOTE: the comma operator will make "cond" to eval to false,
4123 * but float32_unordered_quiet() is still called. */
4124 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4125 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
4126 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4127 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4128 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4129 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4130 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4131 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4132 /* NOTE: the comma operator will make "cond" to eval to false,
4133 * but float32_unordered() is still called. */
4134 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4135 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
4136 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4137 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4138 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4139 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4140 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
4141 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
4142
4143 #define FOP_COND_PS(op, condl, condh) \
4144 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4145 uint64_t fdt1, int cc) \
4146 { \
4147 uint32_t fst0, fsth0, fst1, fsth1; \
4148 int ch, cl; \
4149 fst0 = fdt0 & 0XFFFFFFFF; \
4150 fsth0 = fdt0 >> 32; \
4151 fst1 = fdt1 & 0XFFFFFFFF; \
4152 fsth1 = fdt1 >> 32; \
4153 cl = condl; \
4154 ch = condh; \
4155 update_fcr31(env, GETPC()); \
4156 if (cl) \
4157 SET_FP_COND(cc, env->active_fpu); \
4158 else \
4159 CLEAR_FP_COND(cc, env->active_fpu); \
4160 if (ch) \
4161 SET_FP_COND(cc + 1, env->active_fpu); \
4162 else \
4163 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4164 } \
4165 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4166 uint64_t fdt1, int cc) \
4167 { \
4168 uint32_t fst0, fsth0, fst1, fsth1; \
4169 int ch, cl; \
4170 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4171 fsth0 = float32_abs(fdt0 >> 32); \
4172 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4173 fsth1 = float32_abs(fdt1 >> 32); \
4174 cl = condl; \
4175 ch = condh; \
4176 update_fcr31(env, GETPC()); \
4177 if (cl) \
4178 SET_FP_COND(cc, env->active_fpu); \
4179 else \
4180 CLEAR_FP_COND(cc, env->active_fpu); \
4181 if (ch) \
4182 SET_FP_COND(cc + 1, env->active_fpu); \
4183 else \
4184 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4185 }
4186
4187 /* NOTE: the comma operator will make "cond" to eval to false,
4188 * but float32_unordered_quiet() is still called. */
4189 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
4190 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4191 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
4192 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
4193 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4194 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4195 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4196 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4197 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4198 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4199 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4200 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4201 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4202 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4203 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4204 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4205 /* NOTE: the comma operator will make "cond" to eval to false,
4206 * but float32_unordered() is still called. */
4207 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
4208 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4209 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
4210 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
4211 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4212 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4213 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4214 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4215 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4216 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4217 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4218 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4219 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
4220 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4221 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
4222 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4223
4224 /* R6 compare operations */
4225 #define FOP_CONDN_D(op, cond) \
4226 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4227 uint64_t fdt1) \
4228 { \
4229 uint64_t c; \
4230 c = cond; \
4231 update_fcr31(env, GETPC()); \
4232 if (c) { \
4233 return -1; \
4234 } else { \
4235 return 0; \
4236 } \
4237 }
4238
4239 /* NOTE: the comma operator will make "cond" to eval to false,
4240 * but float64_unordered_quiet() is still called. */
4241 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4242 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4243 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4244 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4245 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4246 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4247 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4248 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4249 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4250 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4251 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4252 /* NOTE: the comma operator will make "cond" to eval to false,
4253 * but float64_unordered() is still called. */
4254 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4255 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4256 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4257 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4258 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4259 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4260 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4261 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4262 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4263 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4264 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4265 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4266 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4267 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4268 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4269 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4270 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4271 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4272 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4273 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4274 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4275 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4276 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4277 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4278 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4279
4280 #define FOP_CONDN_S(op, cond) \
4281 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4282 uint32_t fst1) \
4283 { \
4284 uint64_t c; \
4285 c = cond; \
4286 update_fcr31(env, GETPC()); \
4287 if (c) { \
4288 return -1; \
4289 } else { \
4290 return 0; \
4291 } \
4292 }
4293
4294 /* NOTE: the comma operator will make "cond" to eval to false,
4295 * but float32_unordered_quiet() is still called. */
4296 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4297 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4298 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4299 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4300 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4301 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4302 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4303 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4304 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4305 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4306 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4307 /* NOTE: the comma operator will make "cond" to eval to false,
4308 * but float32_unordered() is still called. */
4309 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4310 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4311 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4312 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4313 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4314 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4315 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4316 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4317 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4318 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4319 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4320 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4321 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4322 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4323 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4324 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4325 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4326 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4327 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4328 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4329 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4330 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4331 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4332 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4333 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4334
4335 /* MSA */
4336 /* Data format min and max values */
4337 #define DF_BITS(df) (1 << ((df) + 3))
4338
4339 /* Element-by-element access macros */
4340 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4341
4342 #if !defined(CONFIG_USER_ONLY)
4343 #define MEMOP_IDX(DF) \
4344 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4345 cpu_mmu_index(env, false));
4346 #else
4347 #define MEMOP_IDX(DF)
4348 #endif
4349
4350 void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
4351 target_ulong addr)
4352 {
4353 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4354 MEMOP_IDX(DF_BYTE)
4355 #if !defined(CONFIG_USER_ONLY)
4356 #if !defined(HOST_WORDS_BIGENDIAN)
4357 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
4358 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
4359 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
4360 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
4361 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
4362 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
4363 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
4364 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
4365 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
4366 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
4367 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
4368 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
4369 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
4370 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
4371 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
4372 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
4373 #else
4374 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
4375 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
4376 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
4377 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
4378 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
4379 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
4380 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
4381 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
4382 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
4383 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
4384 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
4385 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
4386 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
4387 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
4388 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
4389 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
4390 #endif
4391 #else
4392 #if !defined(HOST_WORDS_BIGENDIAN)
4393 pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
4394 pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
4395 pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
4396 pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
4397 pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
4398 pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
4399 pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
4400 pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
4401 pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
4402 pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
4403 pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
4404 pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
4405 pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
4406 pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
4407 pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
4408 pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
4409 #else
4410 pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
4411 pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
4412 pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
4413 pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
4414 pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
4415 pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
4416 pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
4417 pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
4418 pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
4419 pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
4420 pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
4421 pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
4422 pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
4423 pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
4424 pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
4425 pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
4426 #endif
4427 #endif
4428 }
4429
4430 void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
4431 target_ulong addr)
4432 {
4433 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4434 MEMOP_IDX(DF_HALF)
4435 #if !defined(CONFIG_USER_ONLY)
4436 #if !defined(HOST_WORDS_BIGENDIAN)
4437 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
4438 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
4439 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
4440 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
4441 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
4442 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
4443 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
4444 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
4445 #else
4446 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
4447 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
4448 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
4449 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
4450 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
4451 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
4452 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
4453 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
4454 #endif
4455 #else
4456 #if !defined(HOST_WORDS_BIGENDIAN)
4457 pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
4458 pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
4459 pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
4460 pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
4461 pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
4462 pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
4463 pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
4464 pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
4465 #else
4466 pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
4467 pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
4468 pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
4469 pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
4470 pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
4471 pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
4472 pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
4473 pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
4474 #endif
4475 #endif
4476 }
4477
4478 void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
4479 target_ulong addr)
4480 {
4481 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4482 MEMOP_IDX(DF_WORD)
4483 #if !defined(CONFIG_USER_ONLY)
4484 #if !defined(HOST_WORDS_BIGENDIAN)
4485 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
4486 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
4487 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
4488 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
4489 #else
4490 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
4491 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
4492 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
4493 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
4494 #endif
4495 #else
4496 #if !defined(HOST_WORDS_BIGENDIAN)
4497 pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
4498 pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
4499 pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
4500 pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
4501 #else
4502 pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
4503 pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
4504 pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
4505 pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
4506 #endif
4507 #endif
4508 }
4509
4510 void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
4511 target_ulong addr)
4512 {
4513 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4514 MEMOP_IDX(DF_DOUBLE)
4515 #if !defined(CONFIG_USER_ONLY)
4516 pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
4517 pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
4518 #else
4519 pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
4520 pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
4521 #endif
4522 }
4523
4524 #define MSA_PAGESPAN(x) \
4525 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4526
4527 static inline void ensure_writable_pages(CPUMIPSState *env,
4528 target_ulong addr,
4529 int mmu_idx,
4530 uintptr_t retaddr)
4531 {
4532 /* FIXME: Probe the actual accesses (pass and use a size) */
4533 if (unlikely(MSA_PAGESPAN(addr))) {
4534 /* first page */
4535 probe_write(env, addr, 0, mmu_idx, retaddr);
4536 /* second page */
4537 addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4538 probe_write(env, addr, 0, mmu_idx, retaddr);
4539 }
4540 }
4541
4542 void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
4543 target_ulong addr)
4544 {
4545 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4546 int mmu_idx = cpu_mmu_index(env, false);
4547
4548 MEMOP_IDX(DF_BYTE)
4549 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4550 #if !defined(CONFIG_USER_ONLY)
4551 #if !defined(HOST_WORDS_BIGENDIAN)
4552 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
4553 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
4554 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
4555 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
4556 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
4557 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
4558 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
4559 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
4560 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
4561 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
4562 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
4563 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
4564 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
4565 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
4566 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
4567 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
4568 #else
4569 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
4570 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
4571 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
4572 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
4573 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
4574 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
4575 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
4576 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
4577 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
4578 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
4579 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
4580 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
4581 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
4582 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
4583 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
4584 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
4585 #endif
4586 #else
4587 #if !defined(HOST_WORDS_BIGENDIAN)
4588 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
4589 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
4590 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
4591 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
4592 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
4593 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
4594 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
4595 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
4596 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
4597 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
4598 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
4599 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
4600 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
4601 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
4602 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
4603 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
4604 #else
4605 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
4606 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
4607 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
4608 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
4609 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
4610 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
4611 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
4612 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
4613 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
4614 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
4615 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
4616 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
4617 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
4618 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
4619 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
4620 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
4621 #endif
4622 #endif
4623 }
4624
4625 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
4626 target_ulong addr)
4627 {
4628 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4629 int mmu_idx = cpu_mmu_index(env, false);
4630
4631 MEMOP_IDX(DF_HALF)
4632 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4633 #if !defined(CONFIG_USER_ONLY)
4634 #if !defined(HOST_WORDS_BIGENDIAN)
4635 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
4636 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
4637 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
4638 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
4639 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
4640 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
4641 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
4642 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
4643 #else
4644 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
4645 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
4646 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
4647 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
4648 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
4649 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
4650 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
4651 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
4652 #endif
4653 #else
4654 #if !defined(HOST_WORDS_BIGENDIAN)
4655 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
4656 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
4657 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
4658 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
4659 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
4660 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
4661 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
4662 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
4663 #else
4664 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
4665 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
4666 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
4667 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
4668 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
4669 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
4670 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
4671 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
4672 #endif
4673 #endif
4674 }
4675
4676 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
4677 target_ulong addr)
4678 {
4679 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4680 int mmu_idx = cpu_mmu_index(env, false);
4681
4682 MEMOP_IDX(DF_WORD)
4683 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4684 #if !defined(CONFIG_USER_ONLY)
4685 #if !defined(HOST_WORDS_BIGENDIAN)
4686 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
4687 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
4688 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
4689 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
4690 #else
4691 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
4692 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
4693 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
4694 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
4695 #endif
4696 #else
4697 #if !defined(HOST_WORDS_BIGENDIAN)
4698 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
4699 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
4700 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
4701 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
4702 #else
4703 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
4704 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
4705 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
4706 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
4707 #endif
4708 #endif
4709 }
4710
4711 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
4712 target_ulong addr)
4713 {
4714 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4715 int mmu_idx = cpu_mmu_index(env, false);
4716
4717 MEMOP_IDX(DF_DOUBLE)
4718 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4719 #if !defined(CONFIG_USER_ONLY)
4720 helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
4721 helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
4722 #else
4723 cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
4724 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
4725 #endif
4726 }
4727
4728 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4729 {
4730 #ifndef CONFIG_USER_ONLY
4731 target_ulong index = addr & 0x1fffffff;
4732 if (op == 9) {
4733 /* Index Store Tag */
4734 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4735 MO_64, MEMTXATTRS_UNSPECIFIED);
4736 } else if (op == 5) {
4737 /* Index Load Tag */
4738 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4739 MO_64, MEMTXATTRS_UNSPECIFIED);
4740 }
4741 #endif
4742 }
AR7 emulation for QEMU