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qapi: New QAPISourceInfo, replacing dict
[qemu/ar7.git] / target / i386 / kvm.c
blob92069099abf944e780cb7ca0177cc24cbb1406da
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "cpu.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
29 #include "kvm_i386.h"
30 #include "hyperv.h"
31 #include "hyperv-proto.h"
32
33 #include "exec/gdbstub.h"
34 #include "qemu/host-utils.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "hw/i386/pc.h"
39 #include "hw/i386/apic.h"
40 #include "hw/i386/apic_internal.h"
41 #include "hw/i386/apic-msidef.h"
42 #include "hw/i386/intel_iommu.h"
43 #include "hw/i386/x86-iommu.h"
44 #include "hw/i386/e820_memory_layout.h"
45
46 #include "hw/pci/pci.h"
47 #include "hw/pci/msi.h"
48 #include "hw/pci/msix.h"
49 #include "migration/blocker.h"
50 #include "exec/memattrs.h"
51 #include "trace.h"
52
53 //#define DEBUG_KVM
54
55 #ifdef DEBUG_KVM
56 #define DPRINTF(fmt, ...) \
57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58 #else
59 #define DPRINTF(fmt, ...) \
60 do { } while (0)
61 #endif
62
63 #define MSR_KVM_WALL_CLOCK 0x11
64 #define MSR_KVM_SYSTEM_TIME 0x12
65
66 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
67 * 255 kvm_msr_entry structs */
68 #define MSR_BUF_SIZE 4096
69
70 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75 };
76
77 static bool has_msr_star;
78 static bool has_msr_hsave_pa;
79 static bool has_msr_tsc_aux;
80 static bool has_msr_tsc_adjust;
81 static bool has_msr_tsc_deadline;
82 static bool has_msr_feature_control;
83 static bool has_msr_misc_enable;
84 static bool has_msr_smbase;
85 static bool has_msr_bndcfgs;
86 static int lm_capable_kernel;
87 static bool has_msr_hv_hypercall;
88 static bool has_msr_hv_crash;
89 static bool has_msr_hv_reset;
90 static bool has_msr_hv_vpindex;
91 static bool hv_vpindex_settable;
92 static bool has_msr_hv_runtime;
93 static bool has_msr_hv_synic;
94 static bool has_msr_hv_stimer;
95 static bool has_msr_hv_frequencies;
96 static bool has_msr_hv_reenlightenment;
97 static bool has_msr_xss;
98 static bool has_msr_spec_ctrl;
99 static bool has_msr_virt_ssbd;
100 static bool has_msr_smi_count;
101 static bool has_msr_arch_capabs;
102 static bool has_msr_core_capabs;
103
104 static uint32_t has_architectural_pmu_version;
105 static uint32_t num_architectural_pmu_gp_counters;
106 static uint32_t num_architectural_pmu_fixed_counters;
107
108 static int has_xsave;
109 static int has_xcrs;
110 static int has_pit_state2;
111 static int has_exception_payload;
112
113 static bool has_msr_mcg_ext_ctl;
114
115 static struct kvm_cpuid2 *cpuid_cache;
116 static struct kvm_msr_list *kvm_feature_msrs;
117
118 int kvm_has_pit_state2(void)
119 {
120 return has_pit_state2;
121 }
122
123 bool kvm_has_smm(void)
124 {
125 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
126 }
127
128 bool kvm_has_adjust_clock_stable(void)
129 {
130 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
131
132 return (ret == KVM_CLOCK_TSC_STABLE);
133 }
134
135 bool kvm_has_exception_payload(void)
136 {
137 return has_exception_payload;
138 }
139
140 bool kvm_allows_irq0_override(void)
141 {
142 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
143 }
144
145 static bool kvm_x2apic_api_set_flags(uint64_t flags)
146 {
147 KVMState *s = KVM_STATE(current_machine->accelerator);
148
149 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
150 }
151
152 #define MEMORIZE(fn, _result) \
153 ({ \
154 static bool _memorized; \
155 \
156 if (_memorized) { \
157 return _result; \
158 } \
159 _memorized = true; \
160 _result = fn; \
161 })
162
163 static bool has_x2apic_api;
164
165 bool kvm_has_x2apic_api(void)
166 {
167 return has_x2apic_api;
168 }
169
170 bool kvm_enable_x2apic(void)
171 {
172 return MEMORIZE(
173 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
174 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
175 has_x2apic_api);
176 }
177
178 bool kvm_hv_vpindex_settable(void)
179 {
180 return hv_vpindex_settable;
181 }
182
183 static int kvm_get_tsc(CPUState *cs)
184 {
185 X86CPU *cpu = X86_CPU(cs);
186 CPUX86State *env = &cpu->env;
187 struct {
188 struct kvm_msrs info;
189 struct kvm_msr_entry entries[1];
190 } msr_data;
191 int ret;
192
193 if (env->tsc_valid) {
194 return 0;
195 }
196
197 memset(&msr_data, 0, sizeof(msr_data));
198 msr_data.info.nmsrs = 1;
199 msr_data.entries[0].index = MSR_IA32_TSC;
200 env->tsc_valid = !runstate_is_running();
201
202 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
203 if (ret < 0) {
204 return ret;
205 }
206
207 assert(ret == 1);
208 env->tsc = msr_data.entries[0].data;
209 return 0;
210 }
211
212 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
213 {
214 kvm_get_tsc(cpu);
215 }
216
217 void kvm_synchronize_all_tsc(void)
218 {
219 CPUState *cpu;
220
221 if (kvm_enabled()) {
222 CPU_FOREACH(cpu) {
223 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
224 }
225 }
226 }
227
228 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
229 {
230 struct kvm_cpuid2 *cpuid;
231 int r, size;
232
233 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
234 cpuid = g_malloc0(size);
235 cpuid->nent = max;
236 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
237 if (r == 0 && cpuid->nent >= max) {
238 r = -E2BIG;
239 }
240 if (r < 0) {
241 if (r == -E2BIG) {
242 g_free(cpuid);
243 return NULL;
244 } else {
245 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
246 strerror(-r));
247 exit(1);
248 }
249 }
250 return cpuid;
251 }
252
253 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
254 * for all entries.
255 */
256 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
257 {
258 struct kvm_cpuid2 *cpuid;
259 int max = 1;
260
261 if (cpuid_cache != NULL) {
262 return cpuid_cache;
263 }
264 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
265 max *= 2;
266 }
267 cpuid_cache = cpuid;
268 return cpuid;
269 }
270
271 static const struct kvm_para_features {
272 int cap;
273 int feature;
274 } para_features[] = {
275 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
276 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
277 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
278 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
279 };
280
281 static int get_para_features(KVMState *s)
282 {
283 int i, features = 0;
284
285 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
286 if (kvm_check_extension(s, para_features[i].cap)) {
287 features |= (1 << para_features[i].feature);
288 }
289 }
290
291 return features;
292 }
293
294 static bool host_tsx_blacklisted(void)
295 {
296 int family, model, stepping;\
297 char vendor[CPUID_VENDOR_SZ + 1];
298
299 host_vendor_fms(vendor, &family, &model, &stepping);
300
301 /* Check if we are running on a Haswell host known to have broken TSX */
302 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
303 (family == 6) &&
304 ((model == 63 && stepping < 4) ||
305 model == 60 || model == 69 || model == 70);
306 }
307
308 /* Returns the value for a specific register on the cpuid entry
309 */
310 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
311 {
312 uint32_t ret = 0;
313 switch (reg) {
314 case R_EAX:
315 ret = entry->eax;
316 break;
317 case R_EBX:
318 ret = entry->ebx;
319 break;
320 case R_ECX:
321 ret = entry->ecx;
322 break;
323 case R_EDX:
324 ret = entry->edx;
325 break;
326 }
327 return ret;
328 }
329
330 /* Find matching entry for function/index on kvm_cpuid2 struct
331 */
332 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
333 uint32_t function,
334 uint32_t index)
335 {
336 int i;
337 for (i = 0; i < cpuid->nent; ++i) {
338 if (cpuid->entries[i].function == function &&
339 cpuid->entries[i].index == index) {
340 return &cpuid->entries[i];
341 }
342 }
343 /* not found: */
344 return NULL;
345 }
346
347 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
348 uint32_t index, int reg)
349 {
350 struct kvm_cpuid2 *cpuid;
351 uint32_t ret = 0;
352 uint32_t cpuid_1_edx;
353 bool found = false;
354
355 cpuid = get_supported_cpuid(s);
356
357 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
358 if (entry) {
359 found = true;
360 ret = cpuid_entry_get_reg(entry, reg);
361 }
362
363 /* Fixups for the data returned by KVM, below */
364
365 if (function == 1 && reg == R_EDX) {
366 /* KVM before 2.6.30 misreports the following features */
367 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
368 } else if (function == 1 && reg == R_ECX) {
369 /* We can set the hypervisor flag, even if KVM does not return it on
370 * GET_SUPPORTED_CPUID
371 */
372 ret |= CPUID_EXT_HYPERVISOR;
373 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
374 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
375 * and the irqchip is in the kernel.
376 */
377 if (kvm_irqchip_in_kernel() &&
378 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
379 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
380 }
381
382 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
383 * without the in-kernel irqchip
384 */
385 if (!kvm_irqchip_in_kernel()) {
386 ret &= ~CPUID_EXT_X2APIC;
387 }
388
389 if (enable_cpu_pm) {
390 int disable_exits = kvm_check_extension(s,
391 KVM_CAP_X86_DISABLE_EXITS);
392
393 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
394 ret |= CPUID_EXT_MONITOR;
395 }
396 }
397 } else if (function == 6 && reg == R_EAX) {
398 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
399 } else if (function == 7 && index == 0 && reg == R_EBX) {
400 if (host_tsx_blacklisted()) {
401 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
402 }
403 } else if (function == 7 && index == 0 && reg == R_EDX) {
404 /*
405 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
406 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
407 * returned by KVM_GET_MSR_INDEX_LIST.
408 */
409 if (!has_msr_arch_capabs) {
410 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
411 }
412 } else if (function == 0x80000001 && reg == R_ECX) {
413 /*
414 * It's safe to enable TOPOEXT even if it's not returned by
415 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
416 * us to keep CPU models including TOPOEXT runnable on older kernels.
417 */
418 ret |= CPUID_EXT3_TOPOEXT;
419 } else if (function == 0x80000001 && reg == R_EDX) {
420 /* On Intel, kvm returns cpuid according to the Intel spec,
421 * so add missing bits according to the AMD spec:
422 */
423 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
424 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
425 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
426 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
427 * be enabled without the in-kernel irqchip
428 */
429 if (!kvm_irqchip_in_kernel()) {
430 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
431 }
432 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
433 ret |= 1U << KVM_HINTS_REALTIME;
434 found = 1;
435 }
436
437 /* fallback for older kernels */
438 if ((function == KVM_CPUID_FEATURES) && !found) {
439 ret = get_para_features(s);
440 }
441
442 return ret;
443 }
444
445 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
446 {
447 struct {
448 struct kvm_msrs info;
449 struct kvm_msr_entry entries[1];
450 } msr_data;
451 uint32_t ret;
452
453 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
454 return 0;
455 }
456
457 /* Check if requested MSR is supported feature MSR */
458 int i;
459 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
460 if (kvm_feature_msrs->indices[i] == index) {
461 break;
462 }
463 if (i == kvm_feature_msrs->nmsrs) {
464 return 0; /* if the feature MSR is not supported, simply return 0 */
465 }
466
467 msr_data.info.nmsrs = 1;
468 msr_data.entries[0].index = index;
469
470 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
471 if (ret != 1) {
472 error_report("KVM get MSR (index=0x%x) feature failed, %s",
473 index, strerror(-ret));
474 exit(1);
475 }
476
477 return msr_data.entries[0].data;
478 }
479
480
481 typedef struct HWPoisonPage {
482 ram_addr_t ram_addr;
483 QLIST_ENTRY(HWPoisonPage) list;
484 } HWPoisonPage;
485
486 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
487 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
488
489 static void kvm_unpoison_all(void *param)
490 {
491 HWPoisonPage *page, *next_page;
492
493 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
494 QLIST_REMOVE(page, list);
495 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
496 g_free(page);
497 }
498 }
499
500 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
501 {
502 HWPoisonPage *page;
503
504 QLIST_FOREACH(page, &hwpoison_page_list, list) {
505 if (page->ram_addr == ram_addr) {
506 return;
507 }
508 }
509 page = g_new(HWPoisonPage, 1);
510 page->ram_addr = ram_addr;
511 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
512 }
513
514 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
515 int *max_banks)
516 {
517 int r;
518
519 r = kvm_check_extension(s, KVM_CAP_MCE);
520 if (r > 0) {
521 *max_banks = r;
522 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
523 }
524 return -ENOSYS;
525 }
526
527 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
528 {
529 CPUState *cs = CPU(cpu);
530 CPUX86State *env = &cpu->env;
531 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
532 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
533 uint64_t mcg_status = MCG_STATUS_MCIP;
534 int flags = 0;
535
536 if (code == BUS_MCEERR_AR) {
537 status |= MCI_STATUS_AR | 0x134;
538 mcg_status |= MCG_STATUS_EIPV;
539 } else {
540 status |= 0xc0;
541 mcg_status |= MCG_STATUS_RIPV;
542 }
543
544 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
545 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
546 * guest kernel back into env->mcg_ext_ctl.
547 */
548 cpu_synchronize_state(cs);
549 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
550 mcg_status |= MCG_STATUS_LMCE;
551 flags = 0;
552 }
553
554 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
555 (MCM_ADDR_PHYS << 6) | 0xc, flags);
556 }
557
558 static void hardware_memory_error(void)
559 {
560 fprintf(stderr, "Hardware memory error!\n");
561 exit(1);
562 }
563
564 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
565 {
566 X86CPU *cpu = X86_CPU(c);
567 CPUX86State *env = &cpu->env;
568 ram_addr_t ram_addr;
569 hwaddr paddr;
570
571 /* If we get an action required MCE, it has been injected by KVM
572 * while the VM was running. An action optional MCE instead should
573 * be coming from the main thread, which qemu_init_sigbus identifies
574 * as the "early kill" thread.
575 */
576 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
577
578 if ((env->mcg_cap & MCG_SER_P) && addr) {
579 ram_addr = qemu_ram_addr_from_host(addr);
580 if (ram_addr != RAM_ADDR_INVALID &&
581 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
582 kvm_hwpoison_page_add(ram_addr);
583 kvm_mce_inject(cpu, paddr, code);
584 return;
585 }
586
587 fprintf(stderr, "Hardware memory error for memory used by "
588 "QEMU itself instead of guest system!\n");
589 }
590
591 if (code == BUS_MCEERR_AR) {
592 hardware_memory_error();
593 }
594
595 /* Hope we are lucky for AO MCE */
596 }
597
598 static void kvm_reset_exception(CPUX86State *env)
599 {
600 env->exception_nr = -1;
601 env->exception_pending = 0;
602 env->exception_injected = 0;
603 env->exception_has_payload = false;
604 env->exception_payload = 0;
605 }
606
607 static void kvm_queue_exception(CPUX86State *env,
608 int32_t exception_nr,
609 uint8_t exception_has_payload,
610 uint64_t exception_payload)
611 {
612 assert(env->exception_nr == -1);
613 assert(!env->exception_pending);
614 assert(!env->exception_injected);
615 assert(!env->exception_has_payload);
616
617 env->exception_nr = exception_nr;
618
619 if (has_exception_payload) {
620 env->exception_pending = 1;
621
622 env->exception_has_payload = exception_has_payload;
623 env->exception_payload = exception_payload;
624 } else {
625 env->exception_injected = 1;
626
627 if (exception_nr == EXCP01_DB) {
628 assert(exception_has_payload);
629 env->dr[6] = exception_payload;
630 } else if (exception_nr == EXCP0E_PAGE) {
631 assert(exception_has_payload);
632 env->cr[2] = exception_payload;
633 } else {
634 assert(!exception_has_payload);
635 }
636 }
637 }
638
639 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
640 {
641 CPUX86State *env = &cpu->env;
642
643 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
644 unsigned int bank, bank_num = env->mcg_cap & 0xff;
645 struct kvm_x86_mce mce;
646
647 kvm_reset_exception(env);
648
649 /*
650 * There must be at least one bank in use if an MCE is pending.
651 * Find it and use its values for the event injection.
652 */
653 for (bank = 0; bank < bank_num; bank++) {
654 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
655 break;
656 }
657 }
658 assert(bank < bank_num);
659
660 mce.bank = bank;
661 mce.status = env->mce_banks[bank * 4 + 1];
662 mce.mcg_status = env->mcg_status;
663 mce.addr = env->mce_banks[bank * 4 + 2];
664 mce.misc = env->mce_banks[bank * 4 + 3];
665
666 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
667 }
668 return 0;
669 }
670
671 static void cpu_update_state(void *opaque, int running, RunState state)
672 {
673 CPUX86State *env = opaque;
674
675 if (running) {
676 env->tsc_valid = false;
677 }
678 }
679
680 unsigned long kvm_arch_vcpu_id(CPUState *cs)
681 {
682 X86CPU *cpu = X86_CPU(cs);
683 return cpu->apic_id;
684 }
685
686 #ifndef KVM_CPUID_SIGNATURE_NEXT
687 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
688 #endif
689
690 static bool hyperv_enabled(X86CPU *cpu)
691 {
692 CPUState *cs = CPU(cpu);
693 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
694 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
695 cpu->hyperv_features || cpu->hyperv_passthrough);
696 }
697
698 static int kvm_arch_set_tsc_khz(CPUState *cs)
699 {
700 X86CPU *cpu = X86_CPU(cs);
701 CPUX86State *env = &cpu->env;
702 int r;
703
704 if (!env->tsc_khz) {
705 return 0;
706 }
707
708 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
709 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
710 -ENOTSUP;
711 if (r < 0) {
712 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
713 * TSC frequency doesn't match the one we want.
714 */
715 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
716 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
717 -ENOTSUP;
718 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
719 warn_report("TSC frequency mismatch between "
720 "VM (%" PRId64 " kHz) and host (%d kHz), "
721 "and TSC scaling unavailable",
722 env->tsc_khz, cur_freq);
723 return r;
724 }
725 }
726
727 return 0;
728 }
729
730 static bool tsc_is_stable_and_known(CPUX86State *env)
731 {
732 if (!env->tsc_khz) {
733 return false;
734 }
735 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
736 || env->user_tsc_khz;
737 }
738
739 static struct {
740 const char *desc;
741 struct {
742 uint32_t fw;
743 uint32_t bits;
744 } flags[2];
745 uint64_t dependencies;
746 } kvm_hyperv_properties[] = {
747 [HYPERV_FEAT_RELAXED] = {
748 .desc = "relaxed timing (hv-relaxed)",
749 .flags = {
750 {.fw = FEAT_HYPERV_EAX,
751 .bits = HV_HYPERCALL_AVAILABLE},
752 {.fw = FEAT_HV_RECOMM_EAX,
753 .bits = HV_RELAXED_TIMING_RECOMMENDED}
754 }
755 },
756 [HYPERV_FEAT_VAPIC] = {
757 .desc = "virtual APIC (hv-vapic)",
758 .flags = {
759 {.fw = FEAT_HYPERV_EAX,
760 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
761 {.fw = FEAT_HV_RECOMM_EAX,
762 .bits = HV_APIC_ACCESS_RECOMMENDED}
763 }
764 },
765 [HYPERV_FEAT_TIME] = {
766 .desc = "clocksources (hv-time)",
767 .flags = {
768 {.fw = FEAT_HYPERV_EAX,
769 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
770 HV_REFERENCE_TSC_AVAILABLE}
771 }
772 },
773 [HYPERV_FEAT_CRASH] = {
774 .desc = "crash MSRs (hv-crash)",
775 .flags = {
776 {.fw = FEAT_HYPERV_EDX,
777 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
778 }
779 },
780 [HYPERV_FEAT_RESET] = {
781 .desc = "reset MSR (hv-reset)",
782 .flags = {
783 {.fw = FEAT_HYPERV_EAX,
784 .bits = HV_RESET_AVAILABLE}
785 }
786 },
787 [HYPERV_FEAT_VPINDEX] = {
788 .desc = "VP_INDEX MSR (hv-vpindex)",
789 .flags = {
790 {.fw = FEAT_HYPERV_EAX,
791 .bits = HV_VP_INDEX_AVAILABLE}
792 }
793 },
794 [HYPERV_FEAT_RUNTIME] = {
795 .desc = "VP_RUNTIME MSR (hv-runtime)",
796 .flags = {
797 {.fw = FEAT_HYPERV_EAX,
798 .bits = HV_VP_RUNTIME_AVAILABLE}
799 }
800 },
801 [HYPERV_FEAT_SYNIC] = {
802 .desc = "synthetic interrupt controller (hv-synic)",
803 .flags = {
804 {.fw = FEAT_HYPERV_EAX,
805 .bits = HV_SYNIC_AVAILABLE}
806 }
807 },
808 [HYPERV_FEAT_STIMER] = {
809 .desc = "synthetic timers (hv-stimer)",
810 .flags = {
811 {.fw = FEAT_HYPERV_EAX,
812 .bits = HV_SYNTIMERS_AVAILABLE}
813 },
814 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
815 },
816 [HYPERV_FEAT_FREQUENCIES] = {
817 .desc = "frequency MSRs (hv-frequencies)",
818 .flags = {
819 {.fw = FEAT_HYPERV_EAX,
820 .bits = HV_ACCESS_FREQUENCY_MSRS},
821 {.fw = FEAT_HYPERV_EDX,
822 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
823 }
824 },
825 [HYPERV_FEAT_REENLIGHTENMENT] = {
826 .desc = "reenlightenment MSRs (hv-reenlightenment)",
827 .flags = {
828 {.fw = FEAT_HYPERV_EAX,
829 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
830 }
831 },
832 [HYPERV_FEAT_TLBFLUSH] = {
833 .desc = "paravirtualized TLB flush (hv-tlbflush)",
834 .flags = {
835 {.fw = FEAT_HV_RECOMM_EAX,
836 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
837 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
838 },
839 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
840 },
841 [HYPERV_FEAT_EVMCS] = {
842 .desc = "enlightened VMCS (hv-evmcs)",
843 .flags = {
844 {.fw = FEAT_HV_RECOMM_EAX,
845 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
846 },
847 .dependencies = BIT(HYPERV_FEAT_VAPIC)
848 },
849 [HYPERV_FEAT_IPI] = {
850 .desc = "paravirtualized IPI (hv-ipi)",
851 .flags = {
852 {.fw = FEAT_HV_RECOMM_EAX,
853 .bits = HV_CLUSTER_IPI_RECOMMENDED |
854 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
855 },
856 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
857 },
858 [HYPERV_FEAT_STIMER_DIRECT] = {
859 .desc = "direct mode synthetic timers (hv-stimer-direct)",
860 .flags = {
861 {.fw = FEAT_HYPERV_EDX,
862 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
863 },
864 .dependencies = BIT(HYPERV_FEAT_STIMER)
865 },
866 };
867
868 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
869 {
870 struct kvm_cpuid2 *cpuid;
871 int r, size;
872
873 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
874 cpuid = g_malloc0(size);
875 cpuid->nent = max;
876
877 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
878 if (r == 0 && cpuid->nent >= max) {
879 r = -E2BIG;
880 }
881 if (r < 0) {
882 if (r == -E2BIG) {
883 g_free(cpuid);
884 return NULL;
885 } else {
886 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
887 strerror(-r));
888 exit(1);
889 }
890 }
891 return cpuid;
892 }
893
894 /*
895 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
896 * for all entries.
897 */
898 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
899 {
900 struct kvm_cpuid2 *cpuid;
901 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
902
903 /*
904 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
905 * -E2BIG, however, it doesn't report back the right size. Keep increasing
906 * it and re-trying until we succeed.
907 */
908 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
909 max++;
910 }
911 return cpuid;
912 }
913
914 /*
915 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
916 * leaves from KVM_CAP_HYPERV* and present MSRs data.
917 */
918 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
919 {
920 X86CPU *cpu = X86_CPU(cs);
921 struct kvm_cpuid2 *cpuid;
922 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
923
924 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
925 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
926 cpuid->nent = 2;
927
928 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
929 entry_feat = &cpuid->entries[0];
930 entry_feat->function = HV_CPUID_FEATURES;
931
932 entry_recomm = &cpuid->entries[1];
933 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
934 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
935
936 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
937 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
938 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
939 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
940 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
941 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
942 }
943
944 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
945 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
946 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
947 }
948
949 if (has_msr_hv_frequencies) {
950 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
951 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
952 }
953
954 if (has_msr_hv_crash) {
955 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
956 }
957
958 if (has_msr_hv_reenlightenment) {
959 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
960 }
961
962 if (has_msr_hv_reset) {
963 entry_feat->eax |= HV_RESET_AVAILABLE;
964 }
965
966 if (has_msr_hv_vpindex) {
967 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
968 }
969
970 if (has_msr_hv_runtime) {
971 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
972 }
973
974 if (has_msr_hv_synic) {
975 unsigned int cap = cpu->hyperv_synic_kvm_only ?
976 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
977
978 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
979 entry_feat->eax |= HV_SYNIC_AVAILABLE;
980 }
981 }
982
983 if (has_msr_hv_stimer) {
984 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
985 }
986
987 if (kvm_check_extension(cs->kvm_state,
988 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
989 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
990 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
991 }
992
993 if (kvm_check_extension(cs->kvm_state,
994 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
995 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
996 }
997
998 if (kvm_check_extension(cs->kvm_state,
999 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1000 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1001 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1002 }
1003
1004 return cpuid;
1005 }
1006
1007 static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1008 {
1009 struct kvm_cpuid_entry2 *entry;
1010 uint32_t func;
1011 int reg;
1012
1013 switch (fw) {
1014 case FEAT_HYPERV_EAX:
1015 reg = R_EAX;
1016 func = HV_CPUID_FEATURES;
1017 break;
1018 case FEAT_HYPERV_EDX:
1019 reg = R_EDX;
1020 func = HV_CPUID_FEATURES;
1021 break;
1022 case FEAT_HV_RECOMM_EAX:
1023 reg = R_EAX;
1024 func = HV_CPUID_ENLIGHTMENT_INFO;
1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 entry = cpuid_find_entry(cpuid, func, 0);
1031 if (!entry) {
1032 return -ENOENT;
1033 }
1034
1035 switch (reg) {
1036 case R_EAX:
1037 *r = entry->eax;
1038 break;
1039 case R_EDX:
1040 *r = entry->edx;
1041 break;
1042 default:
1043 return -EINVAL;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1050 int feature)
1051 {
1052 X86CPU *cpu = X86_CPU(cs);
1053 CPUX86State *env = &cpu->env;
1054 uint32_t r, fw, bits;
1055 uint64_t deps;
1056 int i, dep_feat;
1057
1058 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1059 return 0;
1060 }
1061
1062 deps = kvm_hyperv_properties[feature].dependencies;
1063 while (deps) {
1064 dep_feat = ctz64(deps);
1065 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1066 fprintf(stderr,
1067 "Hyper-V %s requires Hyper-V %s\n",
1068 kvm_hyperv_properties[feature].desc,
1069 kvm_hyperv_properties[dep_feat].desc);
1070 return 1;
1071 }
1072 deps &= ~(1ull << dep_feat);
1073 }
1074
1075 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1076 fw = kvm_hyperv_properties[feature].flags[i].fw;
1077 bits = kvm_hyperv_properties[feature].flags[i].bits;
1078
1079 if (!fw) {
1080 continue;
1081 }
1082
1083 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
1084 if (hyperv_feat_enabled(cpu, feature)) {
1085 fprintf(stderr,
1086 "Hyper-V %s is not supported by kernel\n",
1087 kvm_hyperv_properties[feature].desc);
1088 return 1;
1089 } else {
1090 return 0;
1091 }
1092 }
1093
1094 env->features[fw] |= bits;
1095 }
1096
1097 if (cpu->hyperv_passthrough) {
1098 cpu->hyperv_features |= BIT(feature);
1099 }
1100
1101 return 0;
1102 }
1103
1104 /*
1105 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1106 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1107 * extentions are enabled.
1108 */
1109 static int hyperv_handle_properties(CPUState *cs,
1110 struct kvm_cpuid_entry2 *cpuid_ent)
1111 {
1112 X86CPU *cpu = X86_CPU(cs);
1113 CPUX86State *env = &cpu->env;
1114 struct kvm_cpuid2 *cpuid;
1115 struct kvm_cpuid_entry2 *c;
1116 uint32_t signature[3];
1117 uint32_t cpuid_i = 0;
1118 int r;
1119
1120 if (!hyperv_enabled(cpu))
1121 return 0;
1122
1123 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1124 cpu->hyperv_passthrough) {
1125 uint16_t evmcs_version;
1126
1127 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1128 (uintptr_t)&evmcs_version);
1129
1130 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
1131 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1132 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1133 return -ENOSYS;
1134 }
1135
1136 if (!r) {
1137 env->features[FEAT_HV_RECOMM_EAX] |=
1138 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1139 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1140 }
1141 }
1142
1143 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1144 cpuid = get_supported_hv_cpuid(cs);
1145 } else {
1146 cpuid = get_supported_hv_cpuid_legacy(cs);
1147 }
1148
1149 if (cpu->hyperv_passthrough) {
1150 memcpy(cpuid_ent, &cpuid->entries[0],
1151 cpuid->nent * sizeof(cpuid->entries[0]));
1152
1153 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1154 if (c) {
1155 env->features[FEAT_HYPERV_EAX] = c->eax;
1156 env->features[FEAT_HYPERV_EBX] = c->ebx;
1157 env->features[FEAT_HYPERV_EDX] = c->eax;
1158 }
1159 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1160 if (c) {
1161 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1162
1163 /* hv-spinlocks may have been overriden */
1164 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1165 c->ebx = cpu->hyperv_spinlock_attempts;
1166 }
1167 }
1168 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1169 if (c) {
1170 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1171 }
1172 }
1173
1174 /* Features */
1175 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
1176 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1177 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1178 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1179 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1180 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1181 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1182 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1183 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1184 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1185 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1186 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1187 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1188 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1189 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
1190
1191 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1192 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1193 !cpu->hyperv_synic_kvm_only &&
1194 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1195 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
1196 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1197 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1198 r |= 1;
1199 }
1200
1201 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1202 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1203
1204 if (r) {
1205 r = -ENOSYS;
1206 goto free;
1207 }
1208
1209 if (cpu->hyperv_passthrough) {
1210 /* We already copied all feature words from KVM as is */
1211 r = cpuid->nent;
1212 goto free;
1213 }
1214
1215 c = &cpuid_ent[cpuid_i++];
1216 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1217 if (!cpu->hyperv_vendor_id) {
1218 memcpy(signature, "Microsoft Hv", 12);
1219 } else {
1220 size_t len = strlen(cpu->hyperv_vendor_id);
1221
1222 if (len > 12) {
1223 error_report("hv-vendor-id truncated to 12 characters");
1224 len = 12;
1225 }
1226 memset(signature, 0, 12);
1227 memcpy(signature, cpu->hyperv_vendor_id, len);
1228 }
1229 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1230 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1231 c->ebx = signature[0];
1232 c->ecx = signature[1];
1233 c->edx = signature[2];
1234
1235 c = &cpuid_ent[cpuid_i++];
1236 c->function = HV_CPUID_INTERFACE;
1237 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1238 c->eax = signature[0];
1239 c->ebx = 0;
1240 c->ecx = 0;
1241 c->edx = 0;
1242
1243 c = &cpuid_ent[cpuid_i++];
1244 c->function = HV_CPUID_VERSION;
1245 c->eax = 0x00001bbc;
1246 c->ebx = 0x00060001;
1247
1248 c = &cpuid_ent[cpuid_i++];
1249 c->function = HV_CPUID_FEATURES;
1250 c->eax = env->features[FEAT_HYPERV_EAX];
1251 c->ebx = env->features[FEAT_HYPERV_EBX];
1252 c->edx = env->features[FEAT_HYPERV_EDX];
1253
1254 c = &cpuid_ent[cpuid_i++];
1255 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1256 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1257 c->ebx = cpu->hyperv_spinlock_attempts;
1258
1259 c = &cpuid_ent[cpuid_i++];
1260 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1261 c->eax = cpu->hv_max_vps;
1262 c->ebx = 0x40;
1263
1264 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1265 __u32 function;
1266
1267 /* Create zeroed 0x40000006..0x40000009 leaves */
1268 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1269 function < HV_CPUID_NESTED_FEATURES; function++) {
1270 c = &cpuid_ent[cpuid_i++];
1271 c->function = function;
1272 }
1273
1274 c = &cpuid_ent[cpuid_i++];
1275 c->function = HV_CPUID_NESTED_FEATURES;
1276 c->eax = env->features[FEAT_HV_NESTED_EAX];
1277 }
1278 r = cpuid_i;
1279
1280 free:
1281 g_free(cpuid);
1282
1283 return r;
1284 }
1285
1286 static Error *hv_passthrough_mig_blocker;
1287
1288 static int hyperv_init_vcpu(X86CPU *cpu)
1289 {
1290 CPUState *cs = CPU(cpu);
1291 Error *local_err = NULL;
1292 int ret;
1293
1294 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1295 error_setg(&hv_passthrough_mig_blocker,
1296 "'hv-passthrough' CPU flag prevents migration, use explicit"
1297 " set of hv-* flags instead");
1298 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1299 if (local_err) {
1300 error_report_err(local_err);
1301 error_free(hv_passthrough_mig_blocker);
1302 return ret;
1303 }
1304 }
1305
1306 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1307 /*
1308 * the kernel doesn't support setting vp_index; assert that its value
1309 * is in sync
1310 */
1311 struct {
1312 struct kvm_msrs info;
1313 struct kvm_msr_entry entries[1];
1314 } msr_data = {
1315 .info.nmsrs = 1,
1316 .entries[0].index = HV_X64_MSR_VP_INDEX,
1317 };
1318
1319 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1320 if (ret < 0) {
1321 return ret;
1322 }
1323 assert(ret == 1);
1324
1325 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1326 error_report("kernel's vp_index != QEMU's vp_index");
1327 return -ENXIO;
1328 }
1329 }
1330
1331 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1332 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1333 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1334 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1335 if (ret < 0) {
1336 error_report("failed to turn on HyperV SynIC in KVM: %s",
1337 strerror(-ret));
1338 return ret;
1339 }
1340
1341 if (!cpu->hyperv_synic_kvm_only) {
1342 ret = hyperv_x86_synic_add(cpu);
1343 if (ret < 0) {
1344 error_report("failed to create HyperV SynIC: %s",
1345 strerror(-ret));
1346 return ret;
1347 }
1348 }
1349 }
1350
1351 return 0;
1352 }
1353
1354 static Error *invtsc_mig_blocker;
1355
1356 #define KVM_MAX_CPUID_ENTRIES 100
1357
1358 int kvm_arch_init_vcpu(CPUState *cs)
1359 {
1360 struct {
1361 struct kvm_cpuid2 cpuid;
1362 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1363 } cpuid_data;
1364 /*
1365 * The kernel defines these structs with padding fields so there
1366 * should be no extra padding in our cpuid_data struct.
1367 */
1368 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1369 sizeof(struct kvm_cpuid2) +
1370 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1371
1372 X86CPU *cpu = X86_CPU(cs);
1373 CPUX86State *env = &cpu->env;
1374 uint32_t limit, i, j, cpuid_i;
1375 uint32_t unused;
1376 struct kvm_cpuid_entry2 *c;
1377 uint32_t signature[3];
1378 int kvm_base = KVM_CPUID_SIGNATURE;
1379 int max_nested_state_len;
1380 int r;
1381 Error *local_err = NULL;
1382
1383 memset(&cpuid_data, 0, sizeof(cpuid_data));
1384
1385 cpuid_i = 0;
1386
1387 r = kvm_arch_set_tsc_khz(cs);
1388 if (r < 0) {
1389 return r;
1390 }
1391
1392 /* vcpu's TSC frequency is either specified by user, or following
1393 * the value used by KVM if the former is not present. In the
1394 * latter case, we query it from KVM and record in env->tsc_khz,
1395 * so that vcpu's TSC frequency can be migrated later via this field.
1396 */
1397 if (!env->tsc_khz) {
1398 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1399 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1400 -ENOTSUP;
1401 if (r > 0) {
1402 env->tsc_khz = r;
1403 }
1404 }
1405
1406 /* Paravirtualization CPUIDs */
1407 r = hyperv_handle_properties(cs, cpuid_data.entries);
1408 if (r < 0) {
1409 return r;
1410 } else if (r > 0) {
1411 cpuid_i = r;
1412 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1413 has_msr_hv_hypercall = true;
1414 }
1415
1416 if (cpu->expose_kvm) {
1417 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1418 c = &cpuid_data.entries[cpuid_i++];
1419 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1420 c->eax = KVM_CPUID_FEATURES | kvm_base;
1421 c->ebx = signature[0];
1422 c->ecx = signature[1];
1423 c->edx = signature[2];
1424
1425 c = &cpuid_data.entries[cpuid_i++];
1426 c->function = KVM_CPUID_FEATURES | kvm_base;
1427 c->eax = env->features[FEAT_KVM];
1428 c->edx = env->features[FEAT_KVM_HINTS];
1429 }
1430
1431 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1432
1433 for (i = 0; i <= limit; i++) {
1434 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1435 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1436 abort();
1437 }
1438 c = &cpuid_data.entries[cpuid_i++];
1439
1440 switch (i) {
1441 case 2: {
1442 /* Keep reading function 2 till all the input is received */
1443 int times;
1444
1445 c->function = i;
1446 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1447 KVM_CPUID_FLAG_STATE_READ_NEXT;
1448 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1449 times = c->eax & 0xff;
1450
1451 for (j = 1; j < times; ++j) {
1452 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1453 fprintf(stderr, "cpuid_data is full, no space for "
1454 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1455 abort();
1456 }
1457 c = &cpuid_data.entries[cpuid_i++];
1458 c->function = i;
1459 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1460 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1461 }
1462 break;
1463 }
1464 case 0x1f:
1465 if (env->nr_dies < 2) {
1466 break;
1467 }
1468 case 4:
1469 case 0xb:
1470 case 0xd:
1471 for (j = 0; ; j++) {
1472 if (i == 0xd && j == 64) {
1473 break;
1474 }
1475
1476 if (i == 0x1f && j == 64) {
1477 break;
1478 }
1479
1480 c->function = i;
1481 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1482 c->index = j;
1483 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1484
1485 if (i == 4 && c->eax == 0) {
1486 break;
1487 }
1488 if (i == 0xb && !(c->ecx & 0xff00)) {
1489 break;
1490 }
1491 if (i == 0x1f && !(c->ecx & 0xff00)) {
1492 break;
1493 }
1494 if (i == 0xd && c->eax == 0) {
1495 continue;
1496 }
1497 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1498 fprintf(stderr, "cpuid_data is full, no space for "
1499 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1500 abort();
1501 }
1502 c = &cpuid_data.entries[cpuid_i++];
1503 }
1504 break;
1505 case 0x7:
1506 case 0x14: {
1507 uint32_t times;
1508
1509 c->function = i;
1510 c->index = 0;
1511 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1512 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1513 times = c->eax;
1514
1515 for (j = 1; j <= times; ++j) {
1516 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1517 fprintf(stderr, "cpuid_data is full, no space for "
1518 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1519 abort();
1520 }
1521 c = &cpuid_data.entries[cpuid_i++];
1522 c->function = i;
1523 c->index = j;
1524 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1525 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1526 }
1527 break;
1528 }
1529 default:
1530 c->function = i;
1531 c->flags = 0;
1532 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1533 break;
1534 }
1535 }
1536
1537 if (limit >= 0x0a) {
1538 uint32_t eax, edx;
1539
1540 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1541
1542 has_architectural_pmu_version = eax & 0xff;
1543 if (has_architectural_pmu_version > 0) {
1544 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1545
1546 /* Shouldn't be more than 32, since that's the number of bits
1547 * available in EBX to tell us _which_ counters are available.
1548 * Play it safe.
1549 */
1550 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1551 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1552 }
1553
1554 if (has_architectural_pmu_version > 1) {
1555 num_architectural_pmu_fixed_counters = edx & 0x1f;
1556
1557 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1558 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1559 }
1560 }
1561 }
1562 }
1563
1564 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1565
1566 for (i = 0x80000000; i <= limit; i++) {
1567 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1568 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1569 abort();
1570 }
1571 c = &cpuid_data.entries[cpuid_i++];
1572
1573 switch (i) {
1574 case 0x8000001d:
1575 /* Query for all AMD cache information leaves */
1576 for (j = 0; ; j++) {
1577 c->function = i;
1578 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1579 c->index = j;
1580 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1581
1582 if (c->eax == 0) {
1583 break;
1584 }
1585 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1586 fprintf(stderr, "cpuid_data is full, no space for "
1587 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1588 abort();
1589 }
1590 c = &cpuid_data.entries[cpuid_i++];
1591 }
1592 break;
1593 default:
1594 c->function = i;
1595 c->flags = 0;
1596 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1597 break;
1598 }
1599 }
1600
1601 /* Call Centaur's CPUID instructions they are supported. */
1602 if (env->cpuid_xlevel2 > 0) {
1603 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1604
1605 for (i = 0xC0000000; i <= limit; i++) {
1606 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1607 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1608 abort();
1609 }
1610 c = &cpuid_data.entries[cpuid_i++];
1611
1612 c->function = i;
1613 c->flags = 0;
1614 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1615 }
1616 }
1617
1618 cpuid_data.cpuid.nent = cpuid_i;
1619
1620 if (((env->cpuid_version >> 8)&0xF) >= 6
1621 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1622 (CPUID_MCE | CPUID_MCA)
1623 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1624 uint64_t mcg_cap, unsupported_caps;
1625 int banks;
1626 int ret;
1627
1628 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1629 if (ret < 0) {
1630 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1631 return ret;
1632 }
1633
1634 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1635 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1636 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1637 return -ENOTSUP;
1638 }
1639
1640 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1641 if (unsupported_caps) {
1642 if (unsupported_caps & MCG_LMCE_P) {
1643 error_report("kvm: LMCE not supported");
1644 return -ENOTSUP;
1645 }
1646 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1647 unsupported_caps);
1648 }
1649
1650 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1651 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1652 if (ret < 0) {
1653 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1654 return ret;
1655 }
1656 }
1657
1658 qemu_add_vm_change_state_handler(cpu_update_state, env);
1659
1660 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1661 if (c) {
1662 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1663 !!(c->ecx & CPUID_EXT_SMX);
1664 }
1665
1666 if (env->mcg_cap & MCG_LMCE_P) {
1667 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1668 }
1669
1670 if (!env->user_tsc_khz) {
1671 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1672 invtsc_mig_blocker == NULL) {
1673 error_setg(&invtsc_mig_blocker,
1674 "State blocked by non-migratable CPU device"
1675 " (invtsc flag)");
1676 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1677 if (local_err) {
1678 error_report_err(local_err);
1679 error_free(invtsc_mig_blocker);
1680 return r;
1681 }
1682 }
1683 }
1684
1685 if (cpu->vmware_cpuid_freq
1686 /* Guests depend on 0x40000000 to detect this feature, so only expose
1687 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1688 && cpu->expose_kvm
1689 && kvm_base == KVM_CPUID_SIGNATURE
1690 /* TSC clock must be stable and known for this feature. */
1691 && tsc_is_stable_and_known(env)) {
1692
1693 c = &cpuid_data.entries[cpuid_i++];
1694 c->function = KVM_CPUID_SIGNATURE | 0x10;
1695 c->eax = env->tsc_khz;
1696 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1697 * APIC_BUS_CYCLE_NS */
1698 c->ebx = 1000000;
1699 c->ecx = c->edx = 0;
1700
1701 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1702 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1703 }
1704
1705 cpuid_data.cpuid.nent = cpuid_i;
1706
1707 cpuid_data.cpuid.padding = 0;
1708 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1709 if (r) {
1710 goto fail;
1711 }
1712
1713 if (has_xsave) {
1714 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1715 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
1716 }
1717
1718 max_nested_state_len = kvm_max_nested_state_length();
1719 if (max_nested_state_len > 0) {
1720 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1721
1722 if (cpu_has_vmx(env)) {
1723 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1724
1725 env->nested_state = g_malloc0(max_nested_state_len);
1726 env->nested_state->size = max_nested_state_len;
1727 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1728
1729 vmx_hdr = &env->nested_state->hdr.vmx;
1730 vmx_hdr->vmxon_pa = -1ull;
1731 vmx_hdr->vmcs12_pa = -1ull;
1732 }
1733 }
1734
1735 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1736
1737 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1738 has_msr_tsc_aux = false;
1739 }
1740
1741 r = hyperv_init_vcpu(cpu);
1742 if (r) {
1743 goto fail;
1744 }
1745
1746 return 0;
1747
1748 fail:
1749 migrate_del_blocker(invtsc_mig_blocker);
1750
1751 return r;
1752 }
1753
1754 int kvm_arch_destroy_vcpu(CPUState *cs)
1755 {
1756 X86CPU *cpu = X86_CPU(cs);
1757 CPUX86State *env = &cpu->env;
1758
1759 if (cpu->kvm_msr_buf) {
1760 g_free(cpu->kvm_msr_buf);
1761 cpu->kvm_msr_buf = NULL;
1762 }
1763
1764 if (env->nested_state) {
1765 g_free(env->nested_state);
1766 env->nested_state = NULL;
1767 }
1768
1769 return 0;
1770 }
1771
1772 void kvm_arch_reset_vcpu(X86CPU *cpu)
1773 {
1774 CPUX86State *env = &cpu->env;
1775
1776 env->xcr0 = 1;
1777 if (kvm_irqchip_in_kernel()) {
1778 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1779 KVM_MP_STATE_UNINITIALIZED;
1780 } else {
1781 env->mp_state = KVM_MP_STATE_RUNNABLE;
1782 }
1783
1784 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1785 int i;
1786 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1787 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1788 }
1789
1790 hyperv_x86_synic_reset(cpu);
1791 }
1792 /* enabled by default */
1793 env->poll_control_msr = 1;
1794 }
1795
1796 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1797 {
1798 CPUX86State *env = &cpu->env;
1799
1800 /* APs get directly into wait-for-SIPI state. */
1801 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1802 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1803 }
1804 }
1805
1806 static int kvm_get_supported_feature_msrs(KVMState *s)
1807 {
1808 int ret = 0;
1809
1810 if (kvm_feature_msrs != NULL) {
1811 return 0;
1812 }
1813
1814 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1815 return 0;
1816 }
1817
1818 struct kvm_msr_list msr_list;
1819
1820 msr_list.nmsrs = 0;
1821 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1822 if (ret < 0 && ret != -E2BIG) {
1823 error_report("Fetch KVM feature MSR list failed: %s",
1824 strerror(-ret));
1825 return ret;
1826 }
1827
1828 assert(msr_list.nmsrs > 0);
1829 kvm_feature_msrs = (struct kvm_msr_list *) \
1830 g_malloc0(sizeof(msr_list) +
1831 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1832
1833 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1834 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1835
1836 if (ret < 0) {
1837 error_report("Fetch KVM feature MSR list failed: %s",
1838 strerror(-ret));
1839 g_free(kvm_feature_msrs);
1840 kvm_feature_msrs = NULL;
1841 return ret;
1842 }
1843
1844 return 0;
1845 }
1846
1847 static int kvm_get_supported_msrs(KVMState *s)
1848 {
1849 int ret = 0;
1850 struct kvm_msr_list msr_list, *kvm_msr_list;
1851
1852 /*
1853 * Obtain MSR list from KVM. These are the MSRs that we must
1854 * save/restore.
1855 */
1856 msr_list.nmsrs = 0;
1857 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1858 if (ret < 0 && ret != -E2BIG) {
1859 return ret;
1860 }
1861 /*
1862 * Old kernel modules had a bug and could write beyond the provided
1863 * memory. Allocate at least a safe amount of 1K.
1864 */
1865 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1866 msr_list.nmsrs *
1867 sizeof(msr_list.indices[0])));
1868
1869 kvm_msr_list->nmsrs = msr_list.nmsrs;
1870 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1871 if (ret >= 0) {
1872 int i;
1873
1874 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1875 switch (kvm_msr_list->indices[i]) {
1876 case MSR_STAR:
1877 has_msr_star = true;
1878 break;
1879 case MSR_VM_HSAVE_PA:
1880 has_msr_hsave_pa = true;
1881 break;
1882 case MSR_TSC_AUX:
1883 has_msr_tsc_aux = true;
1884 break;
1885 case MSR_TSC_ADJUST:
1886 has_msr_tsc_adjust = true;
1887 break;
1888 case MSR_IA32_TSCDEADLINE:
1889 has_msr_tsc_deadline = true;
1890 break;
1891 case MSR_IA32_SMBASE:
1892 has_msr_smbase = true;
1893 break;
1894 case MSR_SMI_COUNT:
1895 has_msr_smi_count = true;
1896 break;
1897 case MSR_IA32_MISC_ENABLE:
1898 has_msr_misc_enable = true;
1899 break;
1900 case MSR_IA32_BNDCFGS:
1901 has_msr_bndcfgs = true;
1902 break;
1903 case MSR_IA32_XSS:
1904 has_msr_xss = true;
1905 break;
1906 case HV_X64_MSR_CRASH_CTL:
1907 has_msr_hv_crash = true;
1908 break;
1909 case HV_X64_MSR_RESET:
1910 has_msr_hv_reset = true;
1911 break;
1912 case HV_X64_MSR_VP_INDEX:
1913 has_msr_hv_vpindex = true;
1914 break;
1915 case HV_X64_MSR_VP_RUNTIME:
1916 has_msr_hv_runtime = true;
1917 break;
1918 case HV_X64_MSR_SCONTROL:
1919 has_msr_hv_synic = true;
1920 break;
1921 case HV_X64_MSR_STIMER0_CONFIG:
1922 has_msr_hv_stimer = true;
1923 break;
1924 case HV_X64_MSR_TSC_FREQUENCY:
1925 has_msr_hv_frequencies = true;
1926 break;
1927 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1928 has_msr_hv_reenlightenment = true;
1929 break;
1930 case MSR_IA32_SPEC_CTRL:
1931 has_msr_spec_ctrl = true;
1932 break;
1933 case MSR_VIRT_SSBD:
1934 has_msr_virt_ssbd = true;
1935 break;
1936 case MSR_IA32_ARCH_CAPABILITIES:
1937 has_msr_arch_capabs = true;
1938 break;
1939 case MSR_IA32_CORE_CAPABILITY:
1940 has_msr_core_capabs = true;
1941 break;
1942 }
1943 }
1944 }
1945
1946 g_free(kvm_msr_list);
1947
1948 return ret;
1949 }
1950
1951 static Notifier smram_machine_done;
1952 static KVMMemoryListener smram_listener;
1953 static AddressSpace smram_address_space;
1954 static MemoryRegion smram_as_root;
1955 static MemoryRegion smram_as_mem;
1956
1957 static void register_smram_listener(Notifier *n, void *unused)
1958 {
1959 MemoryRegion *smram =
1960 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1961
1962 /* Outer container... */
1963 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1964 memory_region_set_enabled(&smram_as_root, true);
1965
1966 /* ... with two regions inside: normal system memory with low
1967 * priority, and...
1968 */
1969 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1970 get_system_memory(), 0, ~0ull);
1971 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1972 memory_region_set_enabled(&smram_as_mem, true);
1973
1974 if (smram) {
1975 /* ... SMRAM with higher priority */
1976 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1977 memory_region_set_enabled(smram, true);
1978 }
1979
1980 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1981 kvm_memory_listener_register(kvm_state, &smram_listener,
1982 &smram_address_space, 1);
1983 }
1984
1985 int kvm_arch_init(MachineState *ms, KVMState *s)
1986 {
1987 uint64_t identity_base = 0xfffbc000;
1988 uint64_t shadow_mem;
1989 int ret;
1990 struct utsname utsname;
1991
1992 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1993 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1994 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1995
1996 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1997
1998 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
1999 if (has_exception_payload) {
2000 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2001 if (ret < 0) {
2002 error_report("kvm: Failed to enable exception payload cap: %s",
2003 strerror(-ret));
2004 return ret;
2005 }
2006 }
2007
2008 ret = kvm_get_supported_msrs(s);
2009 if (ret < 0) {
2010 return ret;
2011 }
2012
2013 kvm_get_supported_feature_msrs(s);
2014
2015 uname(&utsname);
2016 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2017
2018 /*
2019 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2020 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2021 * Since these must be part of guest physical memory, we need to allocate
2022 * them, both by setting their start addresses in the kernel and by
2023 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2024 *
2025 * Older KVM versions may not support setting the identity map base. In
2026 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2027 * size.
2028 */
2029 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2030 /* Allows up to 16M BIOSes. */
2031 identity_base = 0xfeffc000;
2032
2033 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2034 if (ret < 0) {
2035 return ret;
2036 }
2037 }
2038
2039 /* Set TSS base one page after EPT identity map. */
2040 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2041 if (ret < 0) {
2042 return ret;
2043 }
2044
2045 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2046 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2047 if (ret < 0) {
2048 fprintf(stderr, "e820_add_entry() table is full\n");
2049 return ret;
2050 }
2051 qemu_register_reset(kvm_unpoison_all, NULL);
2052
2053 shadow_mem = machine_kvm_shadow_mem(ms);
2054 if (shadow_mem != -1) {
2055 shadow_mem /= 4096;
2056 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2057 if (ret < 0) {
2058 return ret;
2059 }
2060 }
2061
2062 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2063 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2064 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
2065 smram_machine_done.notify = register_smram_listener;
2066 qemu_add_machine_init_done_notifier(&smram_machine_done);
2067 }
2068
2069 if (enable_cpu_pm) {
2070 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2071 int ret;
2072
2073 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2074 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2075 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2076 #endif
2077 if (disable_exits) {
2078 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2079 KVM_X86_DISABLE_EXITS_HLT |
2080 KVM_X86_DISABLE_EXITS_PAUSE |
2081 KVM_X86_DISABLE_EXITS_CSTATE);
2082 }
2083
2084 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2085 disable_exits);
2086 if (ret < 0) {
2087 error_report("kvm: guest stopping CPU not supported: %s",
2088 strerror(-ret));
2089 }
2090 }
2091
2092 return 0;
2093 }
2094
2095 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2096 {
2097 lhs->selector = rhs->selector;
2098 lhs->base = rhs->base;
2099 lhs->limit = rhs->limit;
2100 lhs->type = 3;
2101 lhs->present = 1;
2102 lhs->dpl = 3;
2103 lhs->db = 0;
2104 lhs->s = 1;
2105 lhs->l = 0;
2106 lhs->g = 0;
2107 lhs->avl = 0;
2108 lhs->unusable = 0;
2109 }
2110
2111 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2112 {
2113 unsigned flags = rhs->flags;
2114 lhs->selector = rhs->selector;
2115 lhs->base = rhs->base;
2116 lhs->limit = rhs->limit;
2117 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2118 lhs->present = (flags & DESC_P_MASK) != 0;
2119 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2120 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2121 lhs->s = (flags & DESC_S_MASK) != 0;
2122 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2123 lhs->g = (flags & DESC_G_MASK) != 0;
2124 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2125 lhs->unusable = !lhs->present;
2126 lhs->padding = 0;
2127 }
2128
2129 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2130 {
2131 lhs->selector = rhs->selector;
2132 lhs->base = rhs->base;
2133 lhs->limit = rhs->limit;
2134 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2135 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2136 (rhs->dpl << DESC_DPL_SHIFT) |
2137 (rhs->db << DESC_B_SHIFT) |
2138 (rhs->s * DESC_S_MASK) |
2139 (rhs->l << DESC_L_SHIFT) |
2140 (rhs->g * DESC_G_MASK) |
2141 (rhs->avl * DESC_AVL_MASK);
2142 }
2143
2144 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2145 {
2146 if (set) {
2147 *kvm_reg = *qemu_reg;
2148 } else {
2149 *qemu_reg = *kvm_reg;
2150 }
2151 }
2152
2153 static int kvm_getput_regs(X86CPU *cpu, int set)
2154 {
2155 CPUX86State *env = &cpu->env;
2156 struct kvm_regs regs;
2157 int ret = 0;
2158
2159 if (!set) {
2160 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2161 if (ret < 0) {
2162 return ret;
2163 }
2164 }
2165
2166 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2167 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2168 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2169 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2170 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2171 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2172 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2173 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2174 #ifdef TARGET_X86_64
2175 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2176 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2177 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2178 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2179 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2180 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2181 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2182 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2183 #endif
2184
2185 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2186 kvm_getput_reg(&regs.rip, &env->eip, set);
2187
2188 if (set) {
2189 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2190 }
2191
2192 return ret;
2193 }
2194
2195 static int kvm_put_fpu(X86CPU *cpu)
2196 {
2197 CPUX86State *env = &cpu->env;
2198 struct kvm_fpu fpu;
2199 int i;
2200
2201 memset(&fpu, 0, sizeof fpu);
2202 fpu.fsw = env->fpus & ~(7 << 11);
2203 fpu.fsw |= (env->fpstt & 7) << 11;
2204 fpu.fcw = env->fpuc;
2205 fpu.last_opcode = env->fpop;
2206 fpu.last_ip = env->fpip;
2207 fpu.last_dp = env->fpdp;
2208 for (i = 0; i < 8; ++i) {
2209 fpu.ftwx |= (!env->fptags[i]) << i;
2210 }
2211 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2212 for (i = 0; i < CPU_NB_REGS; i++) {
2213 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2214 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2215 }
2216 fpu.mxcsr = env->mxcsr;
2217
2218 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2219 }
2220
2221 #define XSAVE_FCW_FSW 0
2222 #define XSAVE_FTW_FOP 1
2223 #define XSAVE_CWD_RIP 2
2224 #define XSAVE_CWD_RDP 4
2225 #define XSAVE_MXCSR 6
2226 #define XSAVE_ST_SPACE 8
2227 #define XSAVE_XMM_SPACE 40
2228 #define XSAVE_XSTATE_BV 128
2229 #define XSAVE_YMMH_SPACE 144
2230 #define XSAVE_BNDREGS 240
2231 #define XSAVE_BNDCSR 256
2232 #define XSAVE_OPMASK 272
2233 #define XSAVE_ZMM_Hi256 288
2234 #define XSAVE_Hi16_ZMM 416
2235 #define XSAVE_PKRU 672
2236
2237 #define XSAVE_BYTE_OFFSET(word_offset) \
2238 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2239
2240 #define ASSERT_OFFSET(word_offset, field) \
2241 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2242 offsetof(X86XSaveArea, field))
2243
2244 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2245 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2246 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2247 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2248 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2249 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2250 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2251 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2252 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2253 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2254 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2255 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2256 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2257 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2258 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2259
2260 static int kvm_put_xsave(X86CPU *cpu)
2261 {
2262 CPUX86State *env = &cpu->env;
2263 X86XSaveArea *xsave = env->xsave_buf;
2264
2265 if (!has_xsave) {
2266 return kvm_put_fpu(cpu);
2267 }
2268 x86_cpu_xsave_all_areas(cpu, xsave);
2269
2270 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2271 }
2272
2273 static int kvm_put_xcrs(X86CPU *cpu)
2274 {
2275 CPUX86State *env = &cpu->env;
2276 struct kvm_xcrs xcrs = {};
2277
2278 if (!has_xcrs) {
2279 return 0;
2280 }
2281
2282 xcrs.nr_xcrs = 1;
2283 xcrs.flags = 0;
2284 xcrs.xcrs[0].xcr = 0;
2285 xcrs.xcrs[0].value = env->xcr0;
2286 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2287 }
2288
2289 static int kvm_put_sregs(X86CPU *cpu)
2290 {
2291 CPUX86State *env = &cpu->env;
2292 struct kvm_sregs sregs;
2293
2294 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2295 if (env->interrupt_injected >= 0) {
2296 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2297 (uint64_t)1 << (env->interrupt_injected % 64);
2298 }
2299
2300 if ((env->eflags & VM_MASK)) {
2301 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2302 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2303 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2304 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2305 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2306 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2307 } else {
2308 set_seg(&sregs.cs, &env->segs[R_CS]);
2309 set_seg(&sregs.ds, &env->segs[R_DS]);
2310 set_seg(&sregs.es, &env->segs[R_ES]);
2311 set_seg(&sregs.fs, &env->segs[R_FS]);
2312 set_seg(&sregs.gs, &env->segs[R_GS]);
2313 set_seg(&sregs.ss, &env->segs[R_SS]);
2314 }
2315
2316 set_seg(&sregs.tr, &env->tr);
2317 set_seg(&sregs.ldt, &env->ldt);
2318
2319 sregs.idt.limit = env->idt.limit;
2320 sregs.idt.base = env->idt.base;
2321 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2322 sregs.gdt.limit = env->gdt.limit;
2323 sregs.gdt.base = env->gdt.base;
2324 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2325
2326 sregs.cr0 = env->cr[0];
2327 sregs.cr2 = env->cr[2];
2328 sregs.cr3 = env->cr[3];
2329 sregs.cr4 = env->cr[4];
2330
2331 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2332 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2333
2334 sregs.efer = env->efer;
2335
2336 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2337 }
2338
2339 static void kvm_msr_buf_reset(X86CPU *cpu)
2340 {
2341 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2342 }
2343
2344 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2345 {
2346 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2347 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2348 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2349
2350 assert((void *)(entry + 1) <= limit);
2351
2352 entry->index = index;
2353 entry->reserved = 0;
2354 entry->data = value;
2355 msrs->nmsrs++;
2356 }
2357
2358 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2359 {
2360 kvm_msr_buf_reset(cpu);
2361 kvm_msr_entry_add(cpu, index, value);
2362
2363 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2364 }
2365
2366 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2367 {
2368 int ret;
2369
2370 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2371 assert(ret == 1);
2372 }
2373
2374 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2375 {
2376 CPUX86State *env = &cpu->env;
2377 int ret;
2378
2379 if (!has_msr_tsc_deadline) {
2380 return 0;
2381 }
2382
2383 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2384 if (ret < 0) {
2385 return ret;
2386 }
2387
2388 assert(ret == 1);
2389 return 0;
2390 }
2391
2392 /*
2393 * Provide a separate write service for the feature control MSR in order to
2394 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2395 * before writing any other state because forcibly leaving nested mode
2396 * invalidates the VCPU state.
2397 */
2398 static int kvm_put_msr_feature_control(X86CPU *cpu)
2399 {
2400 int ret;
2401
2402 if (!has_msr_feature_control) {
2403 return 0;
2404 }
2405
2406 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2407 cpu->env.msr_ia32_feature_control);
2408 if (ret < 0) {
2409 return ret;
2410 }
2411
2412 assert(ret == 1);
2413 return 0;
2414 }
2415
2416 static int kvm_put_msrs(X86CPU *cpu, int level)
2417 {
2418 CPUX86State *env = &cpu->env;
2419 int i;
2420 int ret;
2421
2422 kvm_msr_buf_reset(cpu);
2423
2424 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2425 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2426 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2427 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2428 if (has_msr_star) {
2429 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2430 }
2431 if (has_msr_hsave_pa) {
2432 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2433 }
2434 if (has_msr_tsc_aux) {
2435 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2436 }
2437 if (has_msr_tsc_adjust) {
2438 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2439 }
2440 if (has_msr_misc_enable) {
2441 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2442 env->msr_ia32_misc_enable);
2443 }
2444 if (has_msr_smbase) {
2445 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2446 }
2447 if (has_msr_smi_count) {
2448 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2449 }
2450 if (has_msr_bndcfgs) {
2451 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2452 }
2453 if (has_msr_xss) {
2454 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2455 }
2456 if (has_msr_spec_ctrl) {
2457 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2458 }
2459 if (has_msr_virt_ssbd) {
2460 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2461 }
2462
2463 #ifdef TARGET_X86_64
2464 if (lm_capable_kernel) {
2465 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2466 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2467 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2468 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2469 }
2470 #endif
2471
2472 /* If host supports feature MSR, write down. */
2473 if (has_msr_arch_capabs) {
2474 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2475 env->features[FEAT_ARCH_CAPABILITIES]);
2476 }
2477
2478 if (has_msr_core_capabs) {
2479 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2480 env->features[FEAT_CORE_CAPABILITY]);
2481 }
2482
2483 /*
2484 * The following MSRs have side effects on the guest or are too heavy
2485 * for normal writeback. Limit them to reset or full state updates.
2486 */
2487 if (level >= KVM_PUT_RESET_STATE) {
2488 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2489 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2490 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2491 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2492 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2493 }
2494 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2495 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2496 }
2497 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2498 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2499 }
2500
2501 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2502 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2503 }
2504
2505 if (has_architectural_pmu_version > 0) {
2506 if (has_architectural_pmu_version > 1) {
2507 /* Stop the counter. */
2508 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2509 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2510 }
2511
2512 /* Set the counter values. */
2513 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2514 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2515 env->msr_fixed_counters[i]);
2516 }
2517 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2518 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2519 env->msr_gp_counters[i]);
2520 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2521 env->msr_gp_evtsel[i]);
2522 }
2523 if (has_architectural_pmu_version > 1) {
2524 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2525 env->msr_global_status);
2526 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2527 env->msr_global_ovf_ctrl);
2528
2529 /* Now start the PMU. */
2530 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2531 env->msr_fixed_ctr_ctrl);
2532 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2533 env->msr_global_ctrl);
2534 }
2535 }
2536 /*
2537 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2538 * only sync them to KVM on the first cpu
2539 */
2540 if (current_cpu == first_cpu) {
2541 if (has_msr_hv_hypercall) {
2542 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2543 env->msr_hv_guest_os_id);
2544 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2545 env->msr_hv_hypercall);
2546 }
2547 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2548 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2549 env->msr_hv_tsc);
2550 }
2551 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2552 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2553 env->msr_hv_reenlightenment_control);
2554 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2555 env->msr_hv_tsc_emulation_control);
2556 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2557 env->msr_hv_tsc_emulation_status);
2558 }
2559 }
2560 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2561 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2562 env->msr_hv_vapic);
2563 }
2564 if (has_msr_hv_crash) {
2565 int j;
2566
2567 for (j = 0; j < HV_CRASH_PARAMS; j++)
2568 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2569 env->msr_hv_crash_params[j]);
2570
2571 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2572 }
2573 if (has_msr_hv_runtime) {
2574 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2575 }
2576 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2577 && hv_vpindex_settable) {
2578 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2579 hyperv_vp_index(CPU(cpu)));
2580 }
2581 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2582 int j;
2583
2584 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2585
2586 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2587 env->msr_hv_synic_control);
2588 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2589 env->msr_hv_synic_evt_page);
2590 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2591 env->msr_hv_synic_msg_page);
2592
2593 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2594 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2595 env->msr_hv_synic_sint[j]);
2596 }
2597 }
2598 if (has_msr_hv_stimer) {
2599 int j;
2600
2601 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2602 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2603 env->msr_hv_stimer_config[j]);
2604 }
2605
2606 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2607 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2608 env->msr_hv_stimer_count[j]);
2609 }
2610 }
2611 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2612 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2613
2614 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2615 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2616 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2617 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2618 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2619 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2620 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2621 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2622 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2623 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2624 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2625 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2626 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2627 /* The CPU GPs if we write to a bit above the physical limit of
2628 * the host CPU (and KVM emulates that)
2629 */
2630 uint64_t mask = env->mtrr_var[i].mask;
2631 mask &= phys_mask;
2632
2633 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2634 env->mtrr_var[i].base);
2635 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2636 }
2637 }
2638 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2639 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2640 0x14, 1, R_EAX) & 0x7;
2641
2642 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2643 env->msr_rtit_ctrl);
2644 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2645 env->msr_rtit_status);
2646 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2647 env->msr_rtit_output_base);
2648 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2649 env->msr_rtit_output_mask);
2650 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2651 env->msr_rtit_cr3_match);
2652 for (i = 0; i < addr_num; i++) {
2653 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2654 env->msr_rtit_addrs[i]);
2655 }
2656 }
2657
2658 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2659 * kvm_put_msr_feature_control. */
2660 }
2661 if (env->mcg_cap) {
2662 int i;
2663
2664 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2665 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2666 if (has_msr_mcg_ext_ctl) {
2667 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2668 }
2669 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2670 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2671 }
2672 }
2673
2674 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2675 if (ret < 0) {
2676 return ret;
2677 }
2678
2679 if (ret < cpu->kvm_msr_buf->nmsrs) {
2680 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2681 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2682 (uint32_t)e->index, (uint64_t)e->data);
2683 }
2684
2685 assert(ret == cpu->kvm_msr_buf->nmsrs);
2686 return 0;
2687 }
2688
2689
2690 static int kvm_get_fpu(X86CPU *cpu)
2691 {
2692 CPUX86State *env = &cpu->env;
2693 struct kvm_fpu fpu;
2694 int i, ret;
2695
2696 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2697 if (ret < 0) {
2698 return ret;
2699 }
2700
2701 env->fpstt = (fpu.fsw >> 11) & 7;
2702 env->fpus = fpu.fsw;
2703 env->fpuc = fpu.fcw;
2704 env->fpop = fpu.last_opcode;
2705 env->fpip = fpu.last_ip;
2706 env->fpdp = fpu.last_dp;
2707 for (i = 0; i < 8; ++i) {
2708 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2709 }
2710 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2711 for (i = 0; i < CPU_NB_REGS; i++) {
2712 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2713 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2714 }
2715 env->mxcsr = fpu.mxcsr;
2716
2717 return 0;
2718 }
2719
2720 static int kvm_get_xsave(X86CPU *cpu)
2721 {
2722 CPUX86State *env = &cpu->env;
2723 X86XSaveArea *xsave = env->xsave_buf;
2724 int ret;
2725
2726 if (!has_xsave) {
2727 return kvm_get_fpu(cpu);
2728 }
2729
2730 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2731 if (ret < 0) {
2732 return ret;
2733 }
2734 x86_cpu_xrstor_all_areas(cpu, xsave);
2735
2736 return 0;
2737 }
2738
2739 static int kvm_get_xcrs(X86CPU *cpu)
2740 {
2741 CPUX86State *env = &cpu->env;
2742 int i, ret;
2743 struct kvm_xcrs xcrs;
2744
2745 if (!has_xcrs) {
2746 return 0;
2747 }
2748
2749 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2750 if (ret < 0) {
2751 return ret;
2752 }
2753
2754 for (i = 0; i < xcrs.nr_xcrs; i++) {
2755 /* Only support xcr0 now */
2756 if (xcrs.xcrs[i].xcr == 0) {
2757 env->xcr0 = xcrs.xcrs[i].value;
2758 break;
2759 }
2760 }
2761 return 0;
2762 }
2763
2764 static int kvm_get_sregs(X86CPU *cpu)
2765 {
2766 CPUX86State *env = &cpu->env;
2767 struct kvm_sregs sregs;
2768 int bit, i, ret;
2769
2770 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2771 if (ret < 0) {
2772 return ret;
2773 }
2774
2775 /* There can only be one pending IRQ set in the bitmap at a time, so try
2776 to find it and save its number instead (-1 for none). */
2777 env->interrupt_injected = -1;
2778 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2779 if (sregs.interrupt_bitmap[i]) {
2780 bit = ctz64(sregs.interrupt_bitmap[i]);
2781 env->interrupt_injected = i * 64 + bit;
2782 break;
2783 }
2784 }
2785
2786 get_seg(&env->segs[R_CS], &sregs.cs);
2787 get_seg(&env->segs[R_DS], &sregs.ds);
2788 get_seg(&env->segs[R_ES], &sregs.es);
2789 get_seg(&env->segs[R_FS], &sregs.fs);
2790 get_seg(&env->segs[R_GS], &sregs.gs);
2791 get_seg(&env->segs[R_SS], &sregs.ss);
2792
2793 get_seg(&env->tr, &sregs.tr);
2794 get_seg(&env->ldt, &sregs.ldt);
2795
2796 env->idt.limit = sregs.idt.limit;
2797 env->idt.base = sregs.idt.base;
2798 env->gdt.limit = sregs.gdt.limit;
2799 env->gdt.base = sregs.gdt.base;
2800
2801 env->cr[0] = sregs.cr0;
2802 env->cr[2] = sregs.cr2;
2803 env->cr[3] = sregs.cr3;
2804 env->cr[4] = sregs.cr4;
2805
2806 env->efer = sregs.efer;
2807
2808 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2809 x86_update_hflags(env);
2810
2811 return 0;
2812 }
2813
2814 static int kvm_get_msrs(X86CPU *cpu)
2815 {
2816 CPUX86State *env = &cpu->env;
2817 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2818 int ret, i;
2819 uint64_t mtrr_top_bits;
2820
2821 kvm_msr_buf_reset(cpu);
2822
2823 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2824 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2825 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2826 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2827 if (has_msr_star) {
2828 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2829 }
2830 if (has_msr_hsave_pa) {
2831 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2832 }
2833 if (has_msr_tsc_aux) {
2834 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2835 }
2836 if (has_msr_tsc_adjust) {
2837 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2838 }
2839 if (has_msr_tsc_deadline) {
2840 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2841 }
2842 if (has_msr_misc_enable) {
2843 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2844 }
2845 if (has_msr_smbase) {
2846 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2847 }
2848 if (has_msr_smi_count) {
2849 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2850 }
2851 if (has_msr_feature_control) {
2852 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2853 }
2854 if (has_msr_bndcfgs) {
2855 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2856 }
2857 if (has_msr_xss) {
2858 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2859 }
2860 if (has_msr_spec_ctrl) {
2861 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2862 }
2863 if (has_msr_virt_ssbd) {
2864 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2865 }
2866 if (!env->tsc_valid) {
2867 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2868 env->tsc_valid = !runstate_is_running();
2869 }
2870
2871 #ifdef TARGET_X86_64
2872 if (lm_capable_kernel) {
2873 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2874 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2875 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2876 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2877 }
2878 #endif
2879 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2880 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2881 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2882 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2883 }
2884 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2885 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2886 }
2887 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2888 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2889 }
2890 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2891 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
2892 }
2893 if (has_architectural_pmu_version > 0) {
2894 if (has_architectural_pmu_version > 1) {
2895 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2896 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2897 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2898 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2899 }
2900 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2901 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2902 }
2903 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2904 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2905 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2906 }
2907 }
2908
2909 if (env->mcg_cap) {
2910 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2911 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2912 if (has_msr_mcg_ext_ctl) {
2913 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2914 }
2915 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2916 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2917 }
2918 }
2919
2920 if (has_msr_hv_hypercall) {
2921 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2922 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2923 }
2924 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2925 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2926 }
2927 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2928 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2929 }
2930 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2931 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2932 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2933 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2934 }
2935 if (has_msr_hv_crash) {
2936 int j;
2937
2938 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2939 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2940 }
2941 }
2942 if (has_msr_hv_runtime) {
2943 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2944 }
2945 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2946 uint32_t msr;
2947
2948 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2949 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2950 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2951 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2952 kvm_msr_entry_add(cpu, msr, 0);
2953 }
2954 }
2955 if (has_msr_hv_stimer) {
2956 uint32_t msr;
2957
2958 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2959 msr++) {
2960 kvm_msr_entry_add(cpu, msr, 0);
2961 }
2962 }
2963 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2964 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2965 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2966 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2967 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2968 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2969 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2970 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2971 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2972 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2973 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2974 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2975 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2976 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2977 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2978 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2979 }
2980 }
2981
2982 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2983 int addr_num =
2984 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2985
2986 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2987 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2988 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2989 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2990 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2991 for (i = 0; i < addr_num; i++) {
2992 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2993 }
2994 }
2995
2996 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2997 if (ret < 0) {
2998 return ret;
2999 }
3000
3001 if (ret < cpu->kvm_msr_buf->nmsrs) {
3002 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3003 error_report("error: failed to get MSR 0x%" PRIx32,
3004 (uint32_t)e->index);
3005 }
3006
3007 assert(ret == cpu->kvm_msr_buf->nmsrs);
3008 /*
3009 * MTRR masks: Each mask consists of 5 parts
3010 * a 10..0: must be zero
3011 * b 11 : valid bit
3012 * c n-1.12: actual mask bits
3013 * d 51..n: reserved must be zero
3014 * e 63.52: reserved must be zero
3015 *
3016 * 'n' is the number of physical bits supported by the CPU and is
3017 * apparently always <= 52. We know our 'n' but don't know what
3018 * the destinations 'n' is; it might be smaller, in which case
3019 * it masks (c) on loading. It might be larger, in which case
3020 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3021 * we're migrating to.
3022 */
3023
3024 if (cpu->fill_mtrr_mask) {
3025 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3026 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3027 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3028 } else {
3029 mtrr_top_bits = 0;
3030 }
3031
3032 for (i = 0; i < ret; i++) {
3033 uint32_t index = msrs[i].index;
3034 switch (index) {
3035 case MSR_IA32_SYSENTER_CS:
3036 env->sysenter_cs = msrs[i].data;
3037 break;
3038 case MSR_IA32_SYSENTER_ESP:
3039 env->sysenter_esp = msrs[i].data;
3040 break;
3041 case MSR_IA32_SYSENTER_EIP:
3042 env->sysenter_eip = msrs[i].data;
3043 break;
3044 case MSR_PAT:
3045 env->pat = msrs[i].data;
3046 break;
3047 case MSR_STAR:
3048 env->star = msrs[i].data;
3049 break;
3050 #ifdef TARGET_X86_64
3051 case MSR_CSTAR:
3052 env->cstar = msrs[i].data;
3053 break;
3054 case MSR_KERNELGSBASE:
3055 env->kernelgsbase = msrs[i].data;
3056 break;
3057 case MSR_FMASK:
3058 env->fmask = msrs[i].data;
3059 break;
3060 case MSR_LSTAR:
3061 env->lstar = msrs[i].data;
3062 break;
3063 #endif
3064 case MSR_IA32_TSC:
3065 env->tsc = msrs[i].data;
3066 break;
3067 case MSR_TSC_AUX:
3068 env->tsc_aux = msrs[i].data;
3069 break;
3070 case MSR_TSC_ADJUST:
3071 env->tsc_adjust = msrs[i].data;
3072 break;
3073 case MSR_IA32_TSCDEADLINE:
3074 env->tsc_deadline = msrs[i].data;
3075 break;
3076 case MSR_VM_HSAVE_PA:
3077 env->vm_hsave = msrs[i].data;
3078 break;
3079 case MSR_KVM_SYSTEM_TIME:
3080 env->system_time_msr = msrs[i].data;
3081 break;
3082 case MSR_KVM_WALL_CLOCK:
3083 env->wall_clock_msr = msrs[i].data;
3084 break;
3085 case MSR_MCG_STATUS:
3086 env->mcg_status = msrs[i].data;
3087 break;
3088 case MSR_MCG_CTL:
3089 env->mcg_ctl = msrs[i].data;
3090 break;
3091 case MSR_MCG_EXT_CTL:
3092 env->mcg_ext_ctl = msrs[i].data;
3093 break;
3094 case MSR_IA32_MISC_ENABLE:
3095 env->msr_ia32_misc_enable = msrs[i].data;
3096 break;
3097 case MSR_IA32_SMBASE:
3098 env->smbase = msrs[i].data;
3099 break;
3100 case MSR_SMI_COUNT:
3101 env->msr_smi_count = msrs[i].data;
3102 break;
3103 case MSR_IA32_FEATURE_CONTROL:
3104 env->msr_ia32_feature_control = msrs[i].data;
3105 break;
3106 case MSR_IA32_BNDCFGS:
3107 env->msr_bndcfgs = msrs[i].data;
3108 break;
3109 case MSR_IA32_XSS:
3110 env->xss = msrs[i].data;
3111 break;
3112 default:
3113 if (msrs[i].index >= MSR_MC0_CTL &&
3114 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3115 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3116 }
3117 break;
3118 case MSR_KVM_ASYNC_PF_EN:
3119 env->async_pf_en_msr = msrs[i].data;
3120 break;
3121 case MSR_KVM_PV_EOI_EN:
3122 env->pv_eoi_en_msr = msrs[i].data;
3123 break;
3124 case MSR_KVM_STEAL_TIME:
3125 env->steal_time_msr = msrs[i].data;
3126 break;
3127 case MSR_KVM_POLL_CONTROL: {
3128 env->poll_control_msr = msrs[i].data;
3129 break;
3130 }
3131 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3132 env->msr_fixed_ctr_ctrl = msrs[i].data;
3133 break;
3134 case MSR_CORE_PERF_GLOBAL_CTRL:
3135 env->msr_global_ctrl = msrs[i].data;
3136 break;
3137 case MSR_CORE_PERF_GLOBAL_STATUS:
3138 env->msr_global_status = msrs[i].data;
3139 break;
3140 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3141 env->msr_global_ovf_ctrl = msrs[i].data;
3142 break;
3143 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3144 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3145 break;
3146 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3147 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3148 break;
3149 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3150 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3151 break;
3152 case HV_X64_MSR_HYPERCALL:
3153 env->msr_hv_hypercall = msrs[i].data;
3154 break;
3155 case HV_X64_MSR_GUEST_OS_ID:
3156 env->msr_hv_guest_os_id = msrs[i].data;
3157 break;
3158 case HV_X64_MSR_APIC_ASSIST_PAGE:
3159 env->msr_hv_vapic = msrs[i].data;
3160 break;
3161 case HV_X64_MSR_REFERENCE_TSC:
3162 env->msr_hv_tsc = msrs[i].data;
3163 break;
3164 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3165 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3166 break;
3167 case HV_X64_MSR_VP_RUNTIME:
3168 env->msr_hv_runtime = msrs[i].data;
3169 break;
3170 case HV_X64_MSR_SCONTROL:
3171 env->msr_hv_synic_control = msrs[i].data;
3172 break;
3173 case HV_X64_MSR_SIEFP:
3174 env->msr_hv_synic_evt_page = msrs[i].data;
3175 break;
3176 case HV_X64_MSR_SIMP:
3177 env->msr_hv_synic_msg_page = msrs[i].data;
3178 break;
3179 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3180 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3181 break;
3182 case HV_X64_MSR_STIMER0_CONFIG:
3183 case HV_X64_MSR_STIMER1_CONFIG:
3184 case HV_X64_MSR_STIMER2_CONFIG:
3185 case HV_X64_MSR_STIMER3_CONFIG:
3186 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3187 msrs[i].data;
3188 break;
3189 case HV_X64_MSR_STIMER0_COUNT:
3190 case HV_X64_MSR_STIMER1_COUNT:
3191 case HV_X64_MSR_STIMER2_COUNT:
3192 case HV_X64_MSR_STIMER3_COUNT:
3193 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3194 msrs[i].data;
3195 break;
3196 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3197 env->msr_hv_reenlightenment_control = msrs[i].data;
3198 break;
3199 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3200 env->msr_hv_tsc_emulation_control = msrs[i].data;
3201 break;
3202 case HV_X64_MSR_TSC_EMULATION_STATUS:
3203 env->msr_hv_tsc_emulation_status = msrs[i].data;
3204 break;
3205 case MSR_MTRRdefType:
3206 env->mtrr_deftype = msrs[i].data;
3207 break;
3208 case MSR_MTRRfix64K_00000:
3209 env->mtrr_fixed[0] = msrs[i].data;
3210 break;
3211 case MSR_MTRRfix16K_80000:
3212 env->mtrr_fixed[1] = msrs[i].data;
3213 break;
3214 case MSR_MTRRfix16K_A0000:
3215 env->mtrr_fixed[2] = msrs[i].data;
3216 break;
3217 case MSR_MTRRfix4K_C0000:
3218 env->mtrr_fixed[3] = msrs[i].data;
3219 break;
3220 case MSR_MTRRfix4K_C8000:
3221 env->mtrr_fixed[4] = msrs[i].data;
3222 break;
3223 case MSR_MTRRfix4K_D0000:
3224 env->mtrr_fixed[5] = msrs[i].data;
3225 break;
3226 case MSR_MTRRfix4K_D8000:
3227 env->mtrr_fixed[6] = msrs[i].data;
3228 break;
3229 case MSR_MTRRfix4K_E0000:
3230 env->mtrr_fixed[7] = msrs[i].data;
3231 break;
3232 case MSR_MTRRfix4K_E8000:
3233 env->mtrr_fixed[8] = msrs[i].data;
3234 break;
3235 case MSR_MTRRfix4K_F0000:
3236 env->mtrr_fixed[9] = msrs[i].data;
3237 break;
3238 case MSR_MTRRfix4K_F8000:
3239 env->mtrr_fixed[10] = msrs[i].data;
3240 break;
3241 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3242 if (index & 1) {
3243 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3244 mtrr_top_bits;
3245 } else {
3246 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3247 }
3248 break;
3249 case MSR_IA32_SPEC_CTRL:
3250 env->spec_ctrl = msrs[i].data;
3251 break;
3252 case MSR_VIRT_SSBD:
3253 env->virt_ssbd = msrs[i].data;
3254 break;
3255 case MSR_IA32_RTIT_CTL:
3256 env->msr_rtit_ctrl = msrs[i].data;
3257 break;
3258 case MSR_IA32_RTIT_STATUS:
3259 env->msr_rtit_status = msrs[i].data;
3260 break;
3261 case MSR_IA32_RTIT_OUTPUT_BASE:
3262 env->msr_rtit_output_base = msrs[i].data;
3263 break;
3264 case MSR_IA32_RTIT_OUTPUT_MASK:
3265 env->msr_rtit_output_mask = msrs[i].data;
3266 break;
3267 case MSR_IA32_RTIT_CR3_MATCH:
3268 env->msr_rtit_cr3_match = msrs[i].data;
3269 break;
3270 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3271 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3272 break;
3273 }
3274 }
3275
3276 return 0;
3277 }
3278
3279 static int kvm_put_mp_state(X86CPU *cpu)
3280 {
3281 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3282
3283 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3284 }
3285
3286 static int kvm_get_mp_state(X86CPU *cpu)
3287 {
3288 CPUState *cs = CPU(cpu);
3289 CPUX86State *env = &cpu->env;
3290 struct kvm_mp_state mp_state;
3291 int ret;
3292
3293 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3294 if (ret < 0) {
3295 return ret;
3296 }
3297 env->mp_state = mp_state.mp_state;
3298 if (kvm_irqchip_in_kernel()) {
3299 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3300 }
3301 return 0;
3302 }
3303
3304 static int kvm_get_apic(X86CPU *cpu)
3305 {
3306 DeviceState *apic = cpu->apic_state;
3307 struct kvm_lapic_state kapic;
3308 int ret;
3309
3310 if (apic && kvm_irqchip_in_kernel()) {
3311 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3312 if (ret < 0) {
3313 return ret;
3314 }
3315
3316 kvm_get_apic_state(apic, &kapic);
3317 }
3318 return 0;
3319 }
3320
3321 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3322 {
3323 CPUState *cs = CPU(cpu);
3324 CPUX86State *env = &cpu->env;
3325 struct kvm_vcpu_events events = {};
3326
3327 if (!kvm_has_vcpu_events()) {
3328 return 0;
3329 }
3330
3331 events.flags = 0;
3332
3333 if (has_exception_payload) {
3334 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3335 events.exception.pending = env->exception_pending;
3336 events.exception_has_payload = env->exception_has_payload;
3337 events.exception_payload = env->exception_payload;
3338 }
3339 events.exception.nr = env->exception_nr;
3340 events.exception.injected = env->exception_injected;
3341 events.exception.has_error_code = env->has_error_code;
3342 events.exception.error_code = env->error_code;
3343
3344 events.interrupt.injected = (env->interrupt_injected >= 0);
3345 events.interrupt.nr = env->interrupt_injected;
3346 events.interrupt.soft = env->soft_interrupt;
3347
3348 events.nmi.injected = env->nmi_injected;
3349 events.nmi.pending = env->nmi_pending;
3350 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3351
3352 events.sipi_vector = env->sipi_vector;
3353
3354 if (has_msr_smbase) {
3355 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3356 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3357 if (kvm_irqchip_in_kernel()) {
3358 /* As soon as these are moved to the kernel, remove them
3359 * from cs->interrupt_request.
3360 */
3361 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3362 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3363 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3364 } else {
3365 /* Keep these in cs->interrupt_request. */
3366 events.smi.pending = 0;
3367 events.smi.latched_init = 0;
3368 }
3369 /* Stop SMI delivery on old machine types to avoid a reboot
3370 * on an inward migration of an old VM.
3371 */
3372 if (!cpu->kvm_no_smi_migration) {
3373 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3374 }
3375 }
3376
3377 if (level >= KVM_PUT_RESET_STATE) {
3378 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3379 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3380 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3381 }
3382 }
3383
3384 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3385 }
3386
3387 static int kvm_get_vcpu_events(X86CPU *cpu)
3388 {
3389 CPUX86State *env = &cpu->env;
3390 struct kvm_vcpu_events events;
3391 int ret;
3392
3393 if (!kvm_has_vcpu_events()) {
3394 return 0;
3395 }
3396
3397 memset(&events, 0, sizeof(events));
3398 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3399 if (ret < 0) {
3400 return ret;
3401 }
3402
3403 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3404 env->exception_pending = events.exception.pending;
3405 env->exception_has_payload = events.exception_has_payload;
3406 env->exception_payload = events.exception_payload;
3407 } else {
3408 env->exception_pending = 0;
3409 env->exception_has_payload = false;
3410 }
3411 env->exception_injected = events.exception.injected;
3412 env->exception_nr =
3413 (env->exception_pending || env->exception_injected) ?
3414 events.exception.nr : -1;
3415 env->has_error_code = events.exception.has_error_code;
3416 env->error_code = events.exception.error_code;
3417
3418 env->interrupt_injected =
3419 events.interrupt.injected ? events.interrupt.nr : -1;
3420 env->soft_interrupt = events.interrupt.soft;
3421
3422 env->nmi_injected = events.nmi.injected;
3423 env->nmi_pending = events.nmi.pending;
3424 if (events.nmi.masked) {
3425 env->hflags2 |= HF2_NMI_MASK;
3426 } else {
3427 env->hflags2 &= ~HF2_NMI_MASK;
3428 }
3429
3430 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3431 if (events.smi.smm) {
3432 env->hflags |= HF_SMM_MASK;
3433 } else {
3434 env->hflags &= ~HF_SMM_MASK;
3435 }
3436 if (events.smi.pending) {
3437 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3438 } else {
3439 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3440 }
3441 if (events.smi.smm_inside_nmi) {
3442 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3443 } else {
3444 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3445 }
3446 if (events.smi.latched_init) {
3447 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3448 } else {
3449 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3450 }
3451 }
3452
3453 env->sipi_vector = events.sipi_vector;
3454
3455 return 0;
3456 }
3457
3458 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3459 {
3460 CPUState *cs = CPU(cpu);
3461 CPUX86State *env = &cpu->env;
3462 int ret = 0;
3463 unsigned long reinject_trap = 0;
3464
3465 if (!kvm_has_vcpu_events()) {
3466 if (env->exception_nr == EXCP01_DB) {
3467 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3468 } else if (env->exception_injected == EXCP03_INT3) {
3469 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3470 }
3471 kvm_reset_exception(env);
3472 }
3473
3474 /*
3475 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3476 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3477 * by updating the debug state once again if single-stepping is on.
3478 * Another reason to call kvm_update_guest_debug here is a pending debug
3479 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3480 * reinject them via SET_GUEST_DEBUG.
3481 */
3482 if (reinject_trap ||
3483 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3484 ret = kvm_update_guest_debug(cs, reinject_trap);
3485 }
3486 return ret;
3487 }
3488
3489 static int kvm_put_debugregs(X86CPU *cpu)
3490 {
3491 CPUX86State *env = &cpu->env;
3492 struct kvm_debugregs dbgregs;
3493 int i;
3494
3495 if (!kvm_has_debugregs()) {
3496 return 0;
3497 }
3498
3499 memset(&dbgregs, 0, sizeof(dbgregs));
3500 for (i = 0; i < 4; i++) {
3501 dbgregs.db[i] = env->dr[i];
3502 }
3503 dbgregs.dr6 = env->dr[6];
3504 dbgregs.dr7 = env->dr[7];
3505 dbgregs.flags = 0;
3506
3507 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3508 }
3509
3510 static int kvm_get_debugregs(X86CPU *cpu)
3511 {
3512 CPUX86State *env = &cpu->env;
3513 struct kvm_debugregs dbgregs;
3514 int i, ret;
3515
3516 if (!kvm_has_debugregs()) {
3517 return 0;
3518 }
3519
3520 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3521 if (ret < 0) {
3522 return ret;
3523 }
3524 for (i = 0; i < 4; i++) {
3525 env->dr[i] = dbgregs.db[i];
3526 }
3527 env->dr[4] = env->dr[6] = dbgregs.dr6;
3528 env->dr[5] = env->dr[7] = dbgregs.dr7;
3529
3530 return 0;
3531 }
3532
3533 static int kvm_put_nested_state(X86CPU *cpu)
3534 {
3535 CPUX86State *env = &cpu->env;
3536 int max_nested_state_len = kvm_max_nested_state_length();
3537
3538 if (!env->nested_state) {
3539 return 0;
3540 }
3541
3542 assert(env->nested_state->size <= max_nested_state_len);
3543 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3544 }
3545
3546 static int kvm_get_nested_state(X86CPU *cpu)
3547 {
3548 CPUX86State *env = &cpu->env;
3549 int max_nested_state_len = kvm_max_nested_state_length();
3550 int ret;
3551
3552 if (!env->nested_state) {
3553 return 0;
3554 }
3555
3556 /*
3557 * It is possible that migration restored a smaller size into
3558 * nested_state->hdr.size than what our kernel support.
3559 * We preserve migration origin nested_state->hdr.size for
3560 * call to KVM_SET_NESTED_STATE but wish that our next call
3561 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3562 */
3563 env->nested_state->size = max_nested_state_len;
3564
3565 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3566 if (ret < 0) {
3567 return ret;
3568 }
3569
3570 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3571 env->hflags |= HF_GUEST_MASK;
3572 } else {
3573 env->hflags &= ~HF_GUEST_MASK;
3574 }
3575
3576 return ret;
3577 }
3578
3579 int kvm_arch_put_registers(CPUState *cpu, int level)
3580 {
3581 X86CPU *x86_cpu = X86_CPU(cpu);
3582 int ret;
3583
3584 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3585
3586 if (level >= KVM_PUT_RESET_STATE) {
3587 ret = kvm_put_nested_state(x86_cpu);
3588 if (ret < 0) {
3589 return ret;
3590 }
3591
3592 ret = kvm_put_msr_feature_control(x86_cpu);
3593 if (ret < 0) {
3594 return ret;
3595 }
3596 }
3597
3598 if (level == KVM_PUT_FULL_STATE) {
3599 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3600 * because TSC frequency mismatch shouldn't abort migration,
3601 * unless the user explicitly asked for a more strict TSC
3602 * setting (e.g. using an explicit "tsc-freq" option).
3603 */
3604 kvm_arch_set_tsc_khz(cpu);
3605 }
3606
3607 ret = kvm_getput_regs(x86_cpu, 1);
3608 if (ret < 0) {
3609 return ret;
3610 }
3611 ret = kvm_put_xsave(x86_cpu);
3612 if (ret < 0) {
3613 return ret;
3614 }
3615 ret = kvm_put_xcrs(x86_cpu);
3616 if (ret < 0) {
3617 return ret;
3618 }
3619 ret = kvm_put_sregs(x86_cpu);
3620 if (ret < 0) {
3621 return ret;
3622 }
3623 /* must be before kvm_put_msrs */
3624 ret = kvm_inject_mce_oldstyle(x86_cpu);
3625 if (ret < 0) {
3626 return ret;
3627 }
3628 ret = kvm_put_msrs(x86_cpu, level);
3629 if (ret < 0) {
3630 return ret;
3631 }
3632 ret = kvm_put_vcpu_events(x86_cpu, level);
3633 if (ret < 0) {
3634 return ret;
3635 }
3636 if (level >= KVM_PUT_RESET_STATE) {
3637 ret = kvm_put_mp_state(x86_cpu);
3638 if (ret < 0) {
3639 return ret;
3640 }
3641 }
3642
3643 ret = kvm_put_tscdeadline_msr(x86_cpu);
3644 if (ret < 0) {
3645 return ret;
3646 }
3647 ret = kvm_put_debugregs(x86_cpu);
3648 if (ret < 0) {
3649 return ret;
3650 }
3651 /* must be last */
3652 ret = kvm_guest_debug_workarounds(x86_cpu);
3653 if (ret < 0) {
3654 return ret;
3655 }
3656 return 0;
3657 }
3658
3659 int kvm_arch_get_registers(CPUState *cs)
3660 {
3661 X86CPU *cpu = X86_CPU(cs);
3662 int ret;
3663
3664 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3665
3666 ret = kvm_get_vcpu_events(cpu);
3667 if (ret < 0) {
3668 goto out;
3669 }
3670 /*
3671 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3672 * KVM_GET_REGS and KVM_GET_SREGS.
3673 */
3674 ret = kvm_get_mp_state(cpu);
3675 if (ret < 0) {
3676 goto out;
3677 }
3678 ret = kvm_getput_regs(cpu, 0);
3679 if (ret < 0) {
3680 goto out;
3681 }
3682 ret = kvm_get_xsave(cpu);
3683 if (ret < 0) {
3684 goto out;
3685 }
3686 ret = kvm_get_xcrs(cpu);
3687 if (ret < 0) {
3688 goto out;
3689 }
3690 ret = kvm_get_sregs(cpu);
3691 if (ret < 0) {
3692 goto out;
3693 }
3694 ret = kvm_get_msrs(cpu);
3695 if (ret < 0) {
3696 goto out;
3697 }
3698 ret = kvm_get_apic(cpu);
3699 if (ret < 0) {
3700 goto out;
3701 }
3702 ret = kvm_get_debugregs(cpu);
3703 if (ret < 0) {
3704 goto out;
3705 }
3706 ret = kvm_get_nested_state(cpu);
3707 if (ret < 0) {
3708 goto out;
3709 }
3710 ret = 0;
3711 out:
3712 cpu_sync_bndcs_hflags(&cpu->env);
3713 return ret;
3714 }
3715
3716 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3717 {
3718 X86CPU *x86_cpu = X86_CPU(cpu);
3719 CPUX86State *env = &x86_cpu->env;
3720 int ret;
3721
3722 /* Inject NMI */
3723 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3724 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3725 qemu_mutex_lock_iothread();
3726 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3727 qemu_mutex_unlock_iothread();
3728 DPRINTF("injected NMI\n");
3729 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3730 if (ret < 0) {
3731 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3732 strerror(-ret));
3733 }
3734 }
3735 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3736 qemu_mutex_lock_iothread();
3737 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3738 qemu_mutex_unlock_iothread();
3739 DPRINTF("injected SMI\n");
3740 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3741 if (ret < 0) {
3742 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3743 strerror(-ret));
3744 }
3745 }
3746 }
3747
3748 if (!kvm_pic_in_kernel()) {
3749 qemu_mutex_lock_iothread();
3750 }
3751
3752 /* Force the VCPU out of its inner loop to process any INIT requests
3753 * or (for userspace APIC, but it is cheap to combine the checks here)
3754 * pending TPR access reports.
3755 */
3756 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3757 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3758 !(env->hflags & HF_SMM_MASK)) {
3759 cpu->exit_request = 1;
3760 }
3761 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3762 cpu->exit_request = 1;
3763 }
3764 }
3765
3766 if (!kvm_pic_in_kernel()) {
3767 /* Try to inject an interrupt if the guest can accept it */
3768 if (run->ready_for_interrupt_injection &&
3769 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3770 (env->eflags & IF_MASK)) {
3771 int irq;
3772
3773 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3774 irq = cpu_get_pic_interrupt(env);
3775 if (irq >= 0) {
3776 struct kvm_interrupt intr;
3777
3778 intr.irq = irq;
3779 DPRINTF("injected interrupt %d\n", irq);
3780 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3781 if (ret < 0) {
3782 fprintf(stderr,
3783 "KVM: injection failed, interrupt lost (%s)\n",
3784 strerror(-ret));
3785 }
3786 }
3787 }
3788
3789 /* If we have an interrupt but the guest is not ready to receive an
3790 * interrupt, request an interrupt window exit. This will
3791 * cause a return to userspace as soon as the guest is ready to
3792 * receive interrupts. */
3793 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3794 run->request_interrupt_window = 1;
3795 } else {
3796 run->request_interrupt_window = 0;
3797 }
3798
3799 DPRINTF("setting tpr\n");
3800 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3801
3802 qemu_mutex_unlock_iothread();
3803 }
3804 }
3805
3806 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3807 {
3808 X86CPU *x86_cpu = X86_CPU(cpu);
3809 CPUX86State *env = &x86_cpu->env;
3810
3811 if (run->flags & KVM_RUN_X86_SMM) {
3812 env->hflags |= HF_SMM_MASK;
3813 } else {
3814 env->hflags &= ~HF_SMM_MASK;
3815 }
3816 if (run->if_flag) {
3817 env->eflags |= IF_MASK;
3818 } else {
3819 env->eflags &= ~IF_MASK;
3820 }
3821
3822 /* We need to protect the apic state against concurrent accesses from
3823 * different threads in case the userspace irqchip is used. */
3824 if (!kvm_irqchip_in_kernel()) {
3825 qemu_mutex_lock_iothread();
3826 }
3827 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3828 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3829 if (!kvm_irqchip_in_kernel()) {
3830 qemu_mutex_unlock_iothread();
3831 }
3832 return cpu_get_mem_attrs(env);
3833 }
3834
3835 int kvm_arch_process_async_events(CPUState *cs)
3836 {
3837 X86CPU *cpu = X86_CPU(cs);
3838 CPUX86State *env = &cpu->env;
3839
3840 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3841 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3842 assert(env->mcg_cap);
3843
3844 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3845
3846 kvm_cpu_synchronize_state(cs);
3847
3848 if (env->exception_nr == EXCP08_DBLE) {
3849 /* this means triple fault */
3850 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3851 cs->exit_request = 1;
3852 return 0;
3853 }
3854 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
3855 env->has_error_code = 0;
3856
3857 cs->halted = 0;
3858 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3859 env->mp_state = KVM_MP_STATE_RUNNABLE;
3860 }
3861 }
3862
3863 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3864 !(env->hflags & HF_SMM_MASK)) {
3865 kvm_cpu_synchronize_state(cs);
3866 do_cpu_init(cpu);
3867 }
3868
3869 if (kvm_irqchip_in_kernel()) {
3870 return 0;
3871 }
3872
3873 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3874 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3875 apic_poll_irq(cpu->apic_state);
3876 }
3877 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3878 (env->eflags & IF_MASK)) ||
3879 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3880 cs->halted = 0;
3881 }
3882 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3883 kvm_cpu_synchronize_state(cs);
3884 do_cpu_sipi(cpu);
3885 }
3886 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3887 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3888 kvm_cpu_synchronize_state(cs);
3889 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3890 env->tpr_access_type);
3891 }
3892
3893 return cs->halted;
3894 }
3895
3896 static int kvm_handle_halt(X86CPU *cpu)
3897 {
3898 CPUState *cs = CPU(cpu);
3899 CPUX86State *env = &cpu->env;
3900
3901 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3902 (env->eflags & IF_MASK)) &&
3903 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3904 cs->halted = 1;
3905 return EXCP_HLT;
3906 }
3907
3908 return 0;
3909 }
3910
3911 static int kvm_handle_tpr_access(X86CPU *cpu)
3912 {
3913 CPUState *cs = CPU(cpu);
3914 struct kvm_run *run = cs->kvm_run;
3915
3916 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3917 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3918 : TPR_ACCESS_READ);
3919 return 1;
3920 }
3921
3922 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3923 {
3924 static const uint8_t int3 = 0xcc;
3925
3926 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3927 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3928 return -EINVAL;
3929 }
3930 return 0;
3931 }
3932
3933 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3934 {
3935 uint8_t int3;
3936
3937 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3938 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3939 return -EINVAL;
3940 }
3941 return 0;
3942 }
3943
3944 static struct {
3945 target_ulong addr;
3946 int len;
3947 int type;
3948 } hw_breakpoint[4];
3949
3950 static int nb_hw_breakpoint;
3951
3952 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3953 {
3954 int n;
3955
3956 for (n = 0; n < nb_hw_breakpoint; n++) {
3957 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3958 (hw_breakpoint[n].len == len || len == -1)) {
3959 return n;
3960 }
3961 }
3962 return -1;
3963 }
3964
3965 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3966 target_ulong len, int type)
3967 {
3968 switch (type) {
3969 case GDB_BREAKPOINT_HW:
3970 len = 1;
3971 break;
3972 case GDB_WATCHPOINT_WRITE:
3973 case GDB_WATCHPOINT_ACCESS:
3974 switch (len) {
3975 case 1:
3976 break;
3977 case 2:
3978 case 4:
3979 case 8:
3980 if (addr & (len - 1)) {
3981 return -EINVAL;
3982 }
3983 break;
3984 default:
3985 return -EINVAL;
3986 }
3987 break;
3988 default:
3989 return -ENOSYS;
3990 }
3991
3992 if (nb_hw_breakpoint == 4) {
3993 return -ENOBUFS;
3994 }
3995 if (find_hw_breakpoint(addr, len, type) >= 0) {
3996 return -EEXIST;
3997 }
3998 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3999 hw_breakpoint[nb_hw_breakpoint].len = len;
4000 hw_breakpoint[nb_hw_breakpoint].type = type;
4001 nb_hw_breakpoint++;
4002
4003 return 0;
4004 }
4005
4006 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4007 target_ulong len, int type)
4008 {
4009 int n;
4010
4011 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4012 if (n < 0) {
4013 return -ENOENT;
4014 }
4015 nb_hw_breakpoint--;
4016 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4017
4018 return 0;
4019 }
4020
4021 void kvm_arch_remove_all_hw_breakpoints(void)
4022 {
4023 nb_hw_breakpoint = 0;
4024 }
4025
4026 static CPUWatchpoint hw_watchpoint;
4027
4028 static int kvm_handle_debug(X86CPU *cpu,
4029 struct kvm_debug_exit_arch *arch_info)
4030 {
4031 CPUState *cs = CPU(cpu);
4032 CPUX86State *env = &cpu->env;
4033 int ret = 0;
4034 int n;
4035
4036 if (arch_info->exception == EXCP01_DB) {
4037 if (arch_info->dr6 & DR6_BS) {
4038 if (cs->singlestep_enabled) {
4039 ret = EXCP_DEBUG;
4040 }
4041 } else {
4042 for (n = 0; n < 4; n++) {
4043 if (arch_info->dr6 & (1 << n)) {
4044 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4045 case 0x0:
4046 ret = EXCP_DEBUG;
4047 break;
4048 case 0x1:
4049 ret = EXCP_DEBUG;
4050 cs->watchpoint_hit = &hw_watchpoint;
4051 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4052 hw_watchpoint.flags = BP_MEM_WRITE;
4053 break;
4054 case 0x3:
4055 ret = EXCP_DEBUG;
4056 cs->watchpoint_hit = &hw_watchpoint;
4057 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4058 hw_watchpoint.flags = BP_MEM_ACCESS;
4059 break;
4060 }
4061 }
4062 }
4063 }
4064 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4065 ret = EXCP_DEBUG;
4066 }
4067 if (ret == 0) {
4068 cpu_synchronize_state(cs);
4069 assert(env->exception_nr == -1);
4070
4071 /* pass to guest */
4072 kvm_queue_exception(env, arch_info->exception,
4073 arch_info->exception == EXCP01_DB,
4074 arch_info->dr6);
4075 env->has_error_code = 0;
4076 }
4077
4078 return ret;
4079 }
4080
4081 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4082 {
4083 const uint8_t type_code[] = {
4084 [GDB_BREAKPOINT_HW] = 0x0,
4085 [GDB_WATCHPOINT_WRITE] = 0x1,
4086 [GDB_WATCHPOINT_ACCESS] = 0x3
4087 };
4088 const uint8_t len_code[] = {
4089 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4090 };
4091 int n;
4092
4093 if (kvm_sw_breakpoints_active(cpu)) {
4094 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4095 }
4096 if (nb_hw_breakpoint > 0) {
4097 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4098 dbg->arch.debugreg[7] = 0x0600;
4099 for (n = 0; n < nb_hw_breakpoint; n++) {
4100 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4101 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4102 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4103 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4104 }
4105 }
4106 }
4107
4108 static bool host_supports_vmx(void)
4109 {
4110 uint32_t ecx, unused;
4111
4112 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4113 return ecx & CPUID_EXT_VMX;
4114 }
4115
4116 #define VMX_INVALID_GUEST_STATE 0x80000021
4117
4118 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4119 {
4120 X86CPU *cpu = X86_CPU(cs);
4121 uint64_t code;
4122 int ret;
4123
4124 switch (run->exit_reason) {
4125 case KVM_EXIT_HLT:
4126 DPRINTF("handle_hlt\n");
4127 qemu_mutex_lock_iothread();
4128 ret = kvm_handle_halt(cpu);
4129 qemu_mutex_unlock_iothread();
4130 break;
4131 case KVM_EXIT_SET_TPR:
4132 ret = 0;
4133 break;
4134 case KVM_EXIT_TPR_ACCESS:
4135 qemu_mutex_lock_iothread();
4136 ret = kvm_handle_tpr_access(cpu);
4137 qemu_mutex_unlock_iothread();
4138 break;
4139 case KVM_EXIT_FAIL_ENTRY:
4140 code = run->fail_entry.hardware_entry_failure_reason;
4141 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4142 code);
4143 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4144 fprintf(stderr,
4145 "\nIf you're running a guest on an Intel machine without "
4146 "unrestricted mode\n"
4147 "support, the failure can be most likely due to the guest "
4148 "entering an invalid\n"
4149 "state for Intel VT. For example, the guest maybe running "
4150 "in big real mode\n"
4151 "which is not supported on less recent Intel processors."
4152 "\n\n");
4153 }
4154 ret = -1;
4155 break;
4156 case KVM_EXIT_EXCEPTION:
4157 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4158 run->ex.exception, run->ex.error_code);
4159 ret = -1;
4160 break;
4161 case KVM_EXIT_DEBUG:
4162 DPRINTF("kvm_exit_debug\n");
4163 qemu_mutex_lock_iothread();
4164 ret = kvm_handle_debug(cpu, &run->debug.arch);
4165 qemu_mutex_unlock_iothread();
4166 break;
4167 case KVM_EXIT_HYPERV:
4168 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4169 break;
4170 case KVM_EXIT_IOAPIC_EOI:
4171 ioapic_eoi_broadcast(run->eoi.vector);
4172 ret = 0;
4173 break;
4174 default:
4175 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4176 ret = -1;
4177 break;
4178 }
4179
4180 return ret;
4181 }
4182
4183 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4184 {
4185 X86CPU *cpu = X86_CPU(cs);
4186 CPUX86State *env = &cpu->env;
4187
4188 kvm_cpu_synchronize_state(cs);
4189 return !(env->cr[0] & CR0_PE_MASK) ||
4190 ((env->segs[R_CS].selector & 3) != 3);
4191 }
4192
4193 void kvm_arch_init_irq_routing(KVMState *s)
4194 {
4195 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4196 /* If kernel can't do irq routing, interrupt source
4197 * override 0->2 cannot be set up as required by HPET.
4198 * So we have to disable it.
4199 */
4200 no_hpet = 1;
4201 }
4202 /* We know at this point that we're using the in-kernel
4203 * irqchip, so we can use irqfds, and on x86 we know
4204 * we can use msi via irqfd and GSI routing.
4205 */
4206 kvm_msi_via_irqfd_allowed = true;
4207 kvm_gsi_routing_allowed = true;
4208
4209 if (kvm_irqchip_is_split()) {
4210 int i;
4211
4212 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4213 MSI routes for signaling interrupts to the local apics. */
4214 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4215 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4216 error_report("Could not enable split IRQ mode.");
4217 exit(1);
4218 }
4219 }
4220 }
4221 }
4222
4223 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4224 {
4225 int ret;
4226 if (machine_kernel_irqchip_split(ms)) {
4227 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4228 if (ret) {
4229 error_report("Could not enable split irqchip mode: %s",
4230 strerror(-ret));
4231 exit(1);
4232 } else {
4233 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4234 kvm_split_irqchip = true;
4235 return 1;
4236 }
4237 } else {
4238 return 0;
4239 }
4240 }
4241
4242 /* Classic KVM device assignment interface. Will remain x86 only. */
4243 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4244 uint32_t flags, uint32_t *dev_id)
4245 {
4246 struct kvm_assigned_pci_dev dev_data = {
4247 .segnr = dev_addr->domain,
4248 .busnr = dev_addr->bus,
4249 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4250 .flags = flags,
4251 };
4252 int ret;
4253
4254 dev_data.assigned_dev_id =
4255 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4256
4257 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4258 if (ret < 0) {
4259 return ret;
4260 }
4261
4262 *dev_id = dev_data.assigned_dev_id;
4263
4264 return 0;
4265 }
4266
4267 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4268 {
4269 struct kvm_assigned_pci_dev dev_data = {
4270 .assigned_dev_id = dev_id,
4271 };
4272
4273 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4274 }
4275
4276 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4277 uint32_t irq_type, uint32_t guest_irq)
4278 {
4279 struct kvm_assigned_irq assigned_irq = {
4280 .assigned_dev_id = dev_id,
4281 .guest_irq = guest_irq,
4282 .flags = irq_type,
4283 };
4284
4285 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4286 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4287 } else {
4288 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4289 }
4290 }
4291
4292 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4293 uint32_t guest_irq)
4294 {
4295 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4296 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4297
4298 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4299 }
4300
4301 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4302 {
4303 struct kvm_assigned_pci_dev dev_data = {
4304 .assigned_dev_id = dev_id,
4305 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4306 };
4307
4308 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4309 }
4310
4311 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4312 uint32_t type)
4313 {
4314 struct kvm_assigned_irq assigned_irq = {
4315 .assigned_dev_id = dev_id,
4316 .flags = type,
4317 };
4318
4319 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4320 }
4321
4322 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4323 {
4324 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4325 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4326 }
4327
4328 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4329 {
4330 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4331 KVM_DEV_IRQ_GUEST_MSI, virq);
4332 }
4333
4334 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4335 {
4336 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4337 KVM_DEV_IRQ_HOST_MSI);
4338 }
4339
4340 bool kvm_device_msix_supported(KVMState *s)
4341 {
4342 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4343 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4344 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4345 }
4346
4347 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4348 uint32_t nr_vectors)
4349 {
4350 struct kvm_assigned_msix_nr msix_nr = {
4351 .assigned_dev_id = dev_id,
4352 .entry_nr = nr_vectors,
4353 };
4354
4355 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4356 }
4357
4358 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4359 int virq)
4360 {
4361 struct kvm_assigned_msix_entry msix_entry = {
4362 .assigned_dev_id = dev_id,
4363 .gsi = virq,
4364 .entry = vector,
4365 };
4366
4367 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4368 }
4369
4370 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4371 {
4372 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4373 KVM_DEV_IRQ_GUEST_MSIX, 0);
4374 }
4375
4376 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4377 {
4378 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4379 KVM_DEV_IRQ_HOST_MSIX);
4380 }
4381
4382 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4383 uint64_t address, uint32_t data, PCIDevice *dev)
4384 {
4385 X86IOMMUState *iommu = x86_iommu_get_default();
4386
4387 if (iommu) {
4388 int ret;
4389 MSIMessage src, dst;
4390 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4391
4392 if (!class->int_remap) {
4393 return 0;
4394 }
4395
4396 src.address = route->u.msi.address_hi;
4397 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4398 src.address |= route->u.msi.address_lo;
4399 src.data = route->u.msi.data;
4400
4401 ret = class->int_remap(iommu, &src, &dst, dev ? \
4402 pci_requester_id(dev) : \
4403 X86_IOMMU_SID_INVALID);
4404 if (ret) {
4405 trace_kvm_x86_fixup_msi_error(route->gsi);
4406 return 1;
4407 }
4408
4409 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4410 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4411 route->u.msi.data = dst.data;
4412 }
4413
4414 return 0;
4415 }
4416
4417 typedef struct MSIRouteEntry MSIRouteEntry;
4418
4419 struct MSIRouteEntry {
4420 PCIDevice *dev; /* Device pointer */
4421 int vector; /* MSI/MSIX vector index */
4422 int virq; /* Virtual IRQ index */
4423 QLIST_ENTRY(MSIRouteEntry) list;
4424 };
4425
4426 /* List of used GSI routes */
4427 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4428 QLIST_HEAD_INITIALIZER(msi_route_list);
4429
4430 static void kvm_update_msi_routes_all(void *private, bool global,
4431 uint32_t index, uint32_t mask)
4432 {
4433 int cnt = 0, vector;
4434 MSIRouteEntry *entry;
4435 MSIMessage msg;
4436 PCIDevice *dev;
4437
4438 /* TODO: explicit route update */
4439 QLIST_FOREACH(entry, &msi_route_list, list) {
4440 cnt++;
4441 vector = entry->vector;
4442 dev = entry->dev;
4443 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4444 msg = msix_get_message(dev, vector);
4445 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4446 msg = msi_get_message(dev, vector);
4447 } else {
4448 /*
4449 * Either MSI/MSIX is disabled for the device, or the
4450 * specific message was masked out. Skip this one.
4451 */
4452 continue;
4453 }
4454 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4455 }
4456 kvm_irqchip_commit_routes(kvm_state);
4457 trace_kvm_x86_update_msi_routes(cnt);
4458 }
4459
4460 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4461 int vector, PCIDevice *dev)
4462 {
4463 static bool notify_list_inited = false;
4464 MSIRouteEntry *entry;
4465
4466 if (!dev) {
4467 /* These are (possibly) IOAPIC routes only used for split
4468 * kernel irqchip mode, while what we are housekeeping are
4469 * PCI devices only. */
4470 return 0;
4471 }
4472
4473 entry = g_new0(MSIRouteEntry, 1);
4474 entry->dev = dev;
4475 entry->vector = vector;
4476 entry->virq = route->gsi;
4477 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4478
4479 trace_kvm_x86_add_msi_route(route->gsi);
4480
4481 if (!notify_list_inited) {
4482 /* For the first time we do add route, add ourselves into
4483 * IOMMU's IEC notify list if needed. */
4484 X86IOMMUState *iommu = x86_iommu_get_default();
4485 if (iommu) {
4486 x86_iommu_iec_register_notifier(iommu,
4487 kvm_update_msi_routes_all,
4488 NULL);
4489 }
4490 notify_list_inited = true;
4491 }
4492 return 0;
4493 }
4494
4495 int kvm_arch_release_virq_post(int virq)
4496 {
4497 MSIRouteEntry *entry, *next;
4498 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4499 if (entry->virq == virq) {
4500 trace_kvm_x86_remove_msi_route(virq);
4501 QLIST_REMOVE(entry, list);
4502 g_free(entry);
4503 break;
4504 }
4505 }
4506 return 0;
4507 }
4508
4509 int kvm_arch_msi_data_to_gsi(uint32_t data)
4510 {
4511 abort();
4512 }
AR7 emulation for QEMU