target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "hw/sh4/sh_intc.h"
  30 #endif
  31
  32 #if defined(CONFIG_USER_ONLY)
  33
  34 void superh_cpu_do_interrupt(CPUState *cs)
  35 {
  36     SuperHCPU *cpu = SUPERH_CPU(cs);
  37     CPUSH4State *env = &cpu->env;
  38
  39     env->exception_index = -1;
  40 }
  41
  42 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
  43                              int mmu_idx)
  44 {
  45     env->tea = address;
  46     env->exception_index = -1;
  47     switch (rw) {
  48     case 0:
  49         env->exception_index = 0x0a0;
  50         break;
  51     case 1:
  52         env->exception_index = 0x0c0;
  53         break;
  54     case 2:
  55         env->exception_index = 0x0a0;
  56         break;
  57     }
  58     return 1;
  59 }
  60
  61 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  62 {
  63     /* For user mode, only U0 area is cachable. */
  64     return !(addr & 0x80000000);
  65 }
  66
  67 #else /* !CONFIG_USER_ONLY */
  68
  69 #define MMU_OK                   0
  70 #define MMU_ITLB_MISS            (-1)
  71 #define MMU_ITLB_MULTIPLE        (-2)
  72 #define MMU_ITLB_VIOLATION       (-3)
  73 #define MMU_DTLB_MISS_READ       (-4)
  74 #define MMU_DTLB_MISS_WRITE      (-5)
  75 #define MMU_DTLB_INITIAL_WRITE   (-6)
  76 #define MMU_DTLB_VIOLATION_READ  (-7)
  77 #define MMU_DTLB_VIOLATION_WRITE (-8)
  78 #define MMU_DTLB_MULTIPLE        (-9)
  79 #define MMU_DTLB_MISS            (-10)
  80 #define MMU_IADDR_ERROR          (-11)
  81 #define MMU_DADDR_ERROR_READ     (-12)
  82 #define MMU_DADDR_ERROR_WRITE    (-13)
  83
  84 void superh_cpu_do_interrupt(CPUState *cs)
  85 {
  86     SuperHCPU *cpu = SUPERH_CPU(cs);
  87     CPUSH4State *env = &cpu->env;
  88     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
  89     int do_exp, irq_vector = env->exception_index;
  90
  91     /* prioritize exceptions over interrupts */
  92
  93     do_exp = env->exception_index != -1;
  94     do_irq = do_irq && (env->exception_index == -1);
  95
  96     if (env->sr & SR_BL) {
  97         if (do_exp && env->exception_index != 0x1e0) {
  98             env->exception_index = 0x000; /* masked exception -> reset */
  99         }
 100         if (do_irq && !env->in_sleep) {
 101             return; /* masked */
 102         }
 103     }
 104     env->in_sleep = 0;
 105
 106     if (do_irq) {
 107         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 108                                                 (env->sr >> 4) & 0xf);
 109         if (irq_vector == -1) {
 110             return; /* masked */
 111         }
 112     }
 113
 114     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 115         const char *expname;
 116         switch (env->exception_index) {
 117         case 0x0e0:
 118             expname = "addr_error";
 119             break;
 120         case 0x040:
 121             expname = "tlb_miss";
 122             break;
 123         case 0x0a0:
 124             expname = "tlb_violation";
 125             break;
 126         case 0x180:
 127             expname = "illegal_instruction";
 128             break;
 129         case 0x1a0:
 130             expname = "slot_illegal_instruction";
 131             break;
 132         case 0x800:
 133             expname = "fpu_disable";
 134             break;
 135         case 0x820:
 136             expname = "slot_fpu";
 137             break;
 138         case 0x100:
 139             expname = "data_write";
 140             break;
 141         case 0x060:
 142             expname = "dtlb_miss_write";
 143             break;
 144         case 0x0c0:
 145             expname = "dtlb_violation_write";
 146             break;
 147         case 0x120:
 148             expname = "fpu_exception";
 149             break;
 150         case 0x080:
 151             expname = "initial_page_write";
 152             break;
 153         case 0x160:
 154             expname = "trapa";
 155             break;
 156         default:
 157             expname = do_irq ? "interrupt" : "???";
 158             break;
 159         }
 160         qemu_log("exception 0x%03x [%s] raised\n",
 161                   irq_vector, expname);
 162         log_cpu_state(env, 0);
 163     }
 164
 165     env->ssr = env->sr;
 166     env->spc = env->pc;
 167     env->sgr = env->gregs[15];
 168     env->sr |= SR_BL | SR_MD | SR_RB;
 169
 170     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 171         /* Branch instruction should be executed again before delay slot. */
 172         env->spc -= 2;
 173         /* Clear flags for exception/interrupt routine. */
 174         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 175     }
 176     if (env->flags & DELAY_SLOT_CLEARME)
 177         env->flags = 0;
 178
 179     if (do_exp) {
 180         env->expevt = env->exception_index;
 181         switch (env->exception_index) {
 182         case 0x000:
 183         case 0x020:
 184         case 0x140:
 185             env->sr &= ~SR_FD;
 186             env->sr |= 0xf << 4; /* IMASK */
 187             env->pc = 0xa0000000;
 188             break;
 189         case 0x040:
 190         case 0x060:
 191             env->pc = env->vbr + 0x400;
 192             break;
 193         case 0x160:
 194             env->spc += 2; /* special case for TRAPA */
 195             /* fall through */
 196         default:
 197             env->pc = env->vbr + 0x100;
 198             break;
 199         }
 200         return;
 201     }
 202
 203     if (do_irq) {
 204         env->intevt = irq_vector;
 205         env->pc = env->vbr + 0x600;
 206         return;
 207     }
 208 }
 209
 210 static void update_itlb_use(CPUSH4State * env, int itlbnb)
 211 {
 212     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 213
 214     switch (itlbnb) {
 215     case 0:
 216         and_mask = 0x1f;
 217         break;
 218     case 1:
 219         and_mask = 0xe7;
 220         or_mask = 0x80;
 221         break;
 222     case 2:
 223         and_mask = 0xfb;
 224         or_mask = 0x50;
 225         break;
 226     case 3:
 227         or_mask = 0x2c;
 228         break;
 229     }
 230
 231     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 232     env->mmucr |= (or_mask << 24);
 233 }
 234
 235 static int itlb_replacement(CPUSH4State * env)
 236 {
 237     if ((env->mmucr & 0xe0000000) == 0xe0000000)
 238         return 0;
 239     if ((env->mmucr & 0x98000000) == 0x18000000)
 240         return 1;
 241     if ((env->mmucr & 0x54000000) == 0x04000000)
 242         return 2;
 243     if ((env->mmucr & 0x2c000000) == 0x00000000)
 244         return 3;
 245     cpu_abort(env, "Unhandled itlb_replacement");
 246 }
 247
 248 /* Find the corresponding entry in the right TLB
 249    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 250 */
 251 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
 252                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 253 {
 254     int match = MMU_DTLB_MISS;
 255     uint32_t start, end;
 256     uint8_t asid;
 257     int i;
 258
 259     asid = env->pteh & 0xff;
 260
 261     for (i = 0; i < nbtlb; i++) {
 262         if (!entries[i].v)
 263             continue;           /* Invalid entry */
 264         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 265             continue;           /* Bad ASID */
 266         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 267         end = start + entries[i].size - 1;
 268         if (address >= start && address <= end) {       /* Match */
 269             if (match != MMU_DTLB_MISS)
 270                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 271             match = i;
 272         }
 273     }
 274     return match;
 275 }
 276
 277 static void increment_urc(CPUSH4State * env)
 278 {
 279     uint8_t urb, urc;
 280
 281     /* Increment URC */
 282     urb = ((env->mmucr) >> 18) & 0x3f;
 283     urc = ((env->mmucr) >> 10) & 0x3f;
 284     urc++;
 285     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 286         urc = 0;
 287     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 288 }
 289
 290 /* Copy and utlb entry into itlb
 291    Return entry
 292 */
 293 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 294 {
 295     int itlb;
 296
 297     tlb_t * ientry;
 298     itlb = itlb_replacement(env);
 299     ientry = &env->itlb[itlb];
 300     if (ientry->v) {
 301         tlb_flush_page(env, ientry->vpn << 10);
 302     }
 303     *ientry = env->utlb[utlb];
 304     update_itlb_use(env, itlb);
 305     return itlb;
 306 }
 307
 308 /* Find itlb entry
 309    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 310 */
 311 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 312                            int use_asid)
 313 {
 314     int e;
 315
 316     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 317     if (e == MMU_DTLB_MULTIPLE) {
 318         e = MMU_ITLB_MULTIPLE;
 319     } else if (e == MMU_DTLB_MISS) {
 320         e = MMU_ITLB_MISS;
 321     } else if (e >= 0) {
 322         update_itlb_use(env, e);
 323     }
 324     return e;
 325 }
 326
 327 /* Find utlb entry
 328    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 329 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
 330 {
 331     /* per utlb access */
 332     increment_urc(env);
 333
 334     /* Return entry */
 335     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 336 }
 337
 338 /* Match address against MMU
 339    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 340    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 341    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 342    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 343    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 344 */
 345 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
 346                            int *prot, target_ulong address,
 347                            int rw, int access_type)
 348 {
 349     int use_asid, n;
 350     tlb_t *matching = NULL;
 351
 352     use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 353
 354     if (rw == 2) {
 355         n = find_itlb_entry(env, address, use_asid);
 356         if (n >= 0) {
 357             matching = &env->itlb[n];
 358             if (!(env->sr & SR_MD) && !(matching->pr & 2))
 359                 n = MMU_ITLB_VIOLATION;
 360             else
 361                 *prot = PAGE_EXEC;
 362         } else {
 363             n = find_utlb_entry(env, address, use_asid);
 364             if (n >= 0) {
 365                 n = copy_utlb_entry_itlb(env, n);
 366                 matching = &env->itlb[n];
 367                 if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 368                       n = MMU_ITLB_VIOLATION;
 369                 } else {
 370                     *prot = PAGE_READ | PAGE_EXEC;
 371                     if ((matching->pr & 1) && matching->d) {
 372                         *prot |= PAGE_WRITE;
 373                     }
 374                 }
 375             } else if (n == MMU_DTLB_MULTIPLE) {
 376                 n = MMU_ITLB_MULTIPLE;
 377             } else if (n == MMU_DTLB_MISS) {
 378                 n = MMU_ITLB_MISS;
 379             }
 380         }
 381     } else {
 382         n = find_utlb_entry(env, address, use_asid);
 383         if (n >= 0) {
 384             matching = &env->utlb[n];
 385             if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 386                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 387                     MMU_DTLB_VIOLATION_READ;
 388             } else if ((rw == 1) && !(matching->pr & 1)) {
 389                 n = MMU_DTLB_VIOLATION_WRITE;
 390             } else if ((rw == 1) && !matching->d) {
 391                 n = MMU_DTLB_INITIAL_WRITE;
 392             } else {
 393                 *prot = PAGE_READ;
 394                 if ((matching->pr & 1) && matching->d) {
 395                     *prot |= PAGE_WRITE;
 396                 }
 397             }
 398         } else if (n == MMU_DTLB_MISS) {
 399             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 400                 MMU_DTLB_MISS_READ;
 401         }
 402     }
 403     if (n >= 0) {
 404         n = MMU_OK;
 405         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 406             (address & (matching->size - 1));
 407     }
 408     return n;
 409 }
 410
 411 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 412                                 int *prot, target_ulong address,
 413                                 int rw, int access_type)
 414 {
 415     /* P1, P2 and P4 areas do not use translation */
 416     if ((address >= 0x80000000 && address < 0xc0000000) ||
 417         address >= 0xe0000000) {
 418         if (!(env->sr & SR_MD)
 419             && (address < 0xe0000000 || address >= 0xe4000000)) {
 420             /* Unauthorized access in user mode (only store queues are available) */
 421             fprintf(stderr, "Unauthorized access\n");
 422             if (rw == 0)
 423                 return MMU_DADDR_ERROR_READ;
 424             else if (rw == 1)
 425                 return MMU_DADDR_ERROR_WRITE;
 426             else
 427                 return MMU_IADDR_ERROR;
 428         }
 429         if (address >= 0x80000000 && address < 0xc0000000) {
 430             /* Mask upper 3 bits for P1 and P2 areas */
 431             *physical = address & 0x1fffffff;
 432         } else {
 433             *physical = address;
 434         }
 435         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 436         return MMU_OK;
 437     }
 438
 439     /* If MMU is disabled, return the corresponding physical page */
 440     if (!(env->mmucr & MMUCR_AT)) {
 441         *physical = address & 0x1FFFFFFF;
 442         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 443         return MMU_OK;
 444     }
 445
 446     /* We need to resort to the MMU */
 447     return get_mmu_address(env, physical, prot, address, rw, access_type);
 448 }
 449
 450 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
 451                              int mmu_idx)
 452 {
 453     target_ulong physical;
 454     int prot, ret, access_type;
 455
 456     access_type = ACCESS_INT;
 457     ret =
 458         get_physical_address(env, &physical, &prot, address, rw,
 459                              access_type);
 460
 461     if (ret != MMU_OK) {
 462         env->tea = address;
 463         if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
 464             env->pteh = (env->pteh & PTEH_ASID_MASK) |
 465                     (address & PTEH_VPN_MASK);
 466         }
 467         switch (ret) {
 468         case MMU_ITLB_MISS:
 469         case MMU_DTLB_MISS_READ:
 470             env->exception_index = 0x040;
 471             break;
 472         case MMU_DTLB_MULTIPLE:
 473         case MMU_ITLB_MULTIPLE:
 474             env->exception_index = 0x140;
 475             break;
 476         case MMU_ITLB_VIOLATION:
 477             env->exception_index = 0x0a0;
 478             break;
 479         case MMU_DTLB_MISS_WRITE:
 480             env->exception_index = 0x060;
 481             break;
 482         case MMU_DTLB_INITIAL_WRITE:
 483             env->exception_index = 0x080;
 484             break;
 485         case MMU_DTLB_VIOLATION_READ:
 486             env->exception_index = 0x0a0;
 487             break;
 488         case MMU_DTLB_VIOLATION_WRITE:
 489             env->exception_index = 0x0c0;
 490             break;
 491         case MMU_IADDR_ERROR:
 492         case MMU_DADDR_ERROR_READ:
 493             env->exception_index = 0x0e0;
 494             break;
 495         case MMU_DADDR_ERROR_WRITE:
 496             env->exception_index = 0x100;
 497             break;
 498         default:
 499             cpu_abort(env, "Unhandled MMU fault");
 500         }
 501         return 1;
 502     }
 503
 504     address &= TARGET_PAGE_MASK;
 505     physical &= TARGET_PAGE_MASK;
 506
 507     tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 508     return 0;
 509 }
 510
 511 hwaddr cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
 512 {
 513     target_ulong physical;
 514     int prot;
 515
 516     get_physical_address(env, &physical, &prot, addr, 0, 0);
 517     return physical;
 518 }
 519
 520 void cpu_load_tlb(CPUSH4State * env)
 521 {
 522     int n = cpu_mmucr_urc(env->mmucr);
 523     tlb_t * entry = &env->utlb[n];
 524
 525     if (entry->v) {
 526         /* Overwriting valid entry in utlb. */
 527         target_ulong address = entry->vpn << 10;
 528         tlb_flush_page(env, address);
 529     }
 530
 531     /* Take values into cpu status from registers. */
 532     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 533     entry->vpn  = cpu_pteh_vpn(env->pteh);
 534     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 535     entry->ppn  = cpu_ptel_ppn(env->ptel);
 536     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 537     switch (entry->sz) {
 538     case 0: /* 00 */
 539         entry->size = 1024; /* 1K */
 540         break;
 541     case 1: /* 01 */
 542         entry->size = 1024 * 4; /* 4K */
 543         break;
 544     case 2: /* 10 */
 545         entry->size = 1024 * 64; /* 64K */
 546         break;
 547     case 3: /* 11 */
 548         entry->size = 1024 * 1024; /* 1M */
 549         break;
 550     default:
 551         cpu_abort(env, "Unhandled load_tlb");
 552         break;
 553     }
 554     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 555     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 556     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 557     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 558     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 559     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 560     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 561 }
 562
 563  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 564 {
 565     int i;
 566
 567     /* UTLB */
 568     for (i = 0; i < UTLB_SIZE; i++) {
 569         tlb_t * entry = &s->utlb[i];
 570         entry->v = 0;
 571     }
 572     /* ITLB */
 573     for (i = 0; i < ITLB_SIZE; i++) {
 574         tlb_t * entry = &s->itlb[i];
 575         entry->v = 0;
 576     }
 577
 578     tlb_flush(s, 1);
 579 }
 580
 581 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 582                                        hwaddr addr)
 583 {
 584     int index = (addr & 0x00000300) >> 8;
 585     tlb_t * entry = &s->itlb[index];
 586
 587     return (entry->vpn  << 10) |
 588            (entry->v    <<  8) |
 589            (entry->asid);
 590 }
 591
 592 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 593                                     uint32_t mem_value)
 594 {
 595     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 596     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 597     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 598
 599     int index = (addr & 0x00000300) >> 8;
 600     tlb_t * entry = &s->itlb[index];
 601     if (entry->v) {
 602         /* Overwriting valid entry in itlb. */
 603         target_ulong address = entry->vpn << 10;
 604         tlb_flush_page(s, address);
 605     }
 606     entry->asid = asid;
 607     entry->vpn = vpn;
 608     entry->v = v;
 609 }
 610
 611 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 612                                        hwaddr addr)
 613 {
 614     int array = (addr & 0x00800000) >> 23;
 615     int index = (addr & 0x00000300) >> 8;
 616     tlb_t * entry = &s->itlb[index];
 617
 618     if (array == 0) {
 619         /* ITLB Data Array 1 */
 620         return (entry->ppn << 10) |
 621                (entry->v   <<  8) |
 622                (entry->pr  <<  5) |
 623                ((entry->sz & 1) <<  6) |
 624                ((entry->sz & 2) <<  4) |
 625                (entry->c   <<  3) |
 626                (entry->sh  <<  1);
 627     } else {
 628         /* ITLB Data Array 2 */
 629         return (entry->tc << 1) |
 630                (entry->sa);
 631     }
 632 }
 633
 634 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 635                                     uint32_t mem_value)
 636 {
 637     int array = (addr & 0x00800000) >> 23;
 638     int index = (addr & 0x00000300) >> 8;
 639     tlb_t * entry = &s->itlb[index];
 640
 641     if (array == 0) {
 642         /* ITLB Data Array 1 */
 643         if (entry->v) {
 644             /* Overwriting valid entry in utlb. */
 645             target_ulong address = entry->vpn << 10;
 646             tlb_flush_page(s, address);
 647         }
 648         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 649         entry->v   = (mem_value & 0x00000100) >> 8;
 650         entry->sz  = (mem_value & 0x00000080) >> 6 |
 651                      (mem_value & 0x00000010) >> 4;
 652         entry->pr  = (mem_value & 0x00000040) >> 5;
 653         entry->c   = (mem_value & 0x00000008) >> 3;
 654         entry->sh  = (mem_value & 0x00000002) >> 1;
 655     } else {
 656         /* ITLB Data Array 2 */
 657         entry->tc  = (mem_value & 0x00000008) >> 3;
 658         entry->sa  = (mem_value & 0x00000007);
 659     }
 660 }
 661
 662 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 663                                        hwaddr addr)
 664 {
 665     int index = (addr & 0x00003f00) >> 8;
 666     tlb_t * entry = &s->utlb[index];
 667
 668     increment_urc(s); /* per utlb access */
 669
 670     return (entry->vpn  << 10) |
 671            (entry->v    <<  8) |
 672            (entry->asid);
 673 }
 674
 675 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 676                                     uint32_t mem_value)
 677 {
 678     int associate = addr & 0x0000080;
 679     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 680     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 681     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 682     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 683     int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
 684
 685     if (associate) {
 686         int i;
 687         tlb_t * utlb_match_entry = NULL;
 688         int needs_tlb_flush = 0;
 689
 690         /* search UTLB */
 691         for (i = 0; i < UTLB_SIZE; i++) {
 692             tlb_t * entry = &s->utlb[i];
 693             if (!entry->v)
 694                 continue;
 695
 696             if (entry->vpn == vpn
 697                 && (!use_asid || entry->asid == asid || entry->sh)) {
 698                 if (utlb_match_entry) {
 699                     /* Multiple TLB Exception */
 700                     s->exception_index = 0x140;
 701                     s->tea = addr;
 702                     break;
 703                 }
 704                 if (entry->v && !v)
 705                     needs_tlb_flush = 1;
 706                 entry->v = v;
 707                 entry->d = d;
 708                 utlb_match_entry = entry;
 709             }
 710             increment_urc(s); /* per utlb access */
 711         }
 712
 713         /* search ITLB */
 714         for (i = 0; i < ITLB_SIZE; i++) {
 715             tlb_t * entry = &s->itlb[i];
 716             if (entry->vpn == vpn
 717                 && (!use_asid || entry->asid == asid || entry->sh)) {
 718                 if (entry->v && !v)
 719                     needs_tlb_flush = 1;
 720                 if (utlb_match_entry)
 721                     *entry = *utlb_match_entry;
 722                 else
 723                     entry->v = v;
 724                 break;
 725             }
 726         }
 727
 728         if (needs_tlb_flush)
 729             tlb_flush_page(s, vpn << 10);
 730
 731     } else {
 732         int index = (addr & 0x00003f00) >> 8;
 733         tlb_t * entry = &s->utlb[index];
 734         if (entry->v) {
 735             /* Overwriting valid entry in utlb. */
 736             target_ulong address = entry->vpn << 10;
 737             tlb_flush_page(s, address);
 738         }
 739         entry->asid = asid;
 740         entry->vpn = vpn;
 741         entry->d = d;
 742         entry->v = v;
 743         increment_urc(s);
 744     }
 745 }
 746
 747 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 748                                        hwaddr addr)
 749 {
 750     int array = (addr & 0x00800000) >> 23;
 751     int index = (addr & 0x00003f00) >> 8;
 752     tlb_t * entry = &s->utlb[index];
 753
 754     increment_urc(s); /* per utlb access */
 755
 756     if (array == 0) {
 757         /* ITLB Data Array 1 */
 758         return (entry->ppn << 10) |
 759                (entry->v   <<  8) |
 760                (entry->pr  <<  5) |
 761                ((entry->sz & 1) <<  6) |
 762                ((entry->sz & 2) <<  4) |
 763                (entry->c   <<  3) |
 764                (entry->d   <<  2) |
 765                (entry->sh  <<  1) |
 766                (entry->wt);
 767     } else {
 768         /* ITLB Data Array 2 */
 769         return (entry->tc << 1) |
 770                (entry->sa);
 771     }
 772 }
 773
 774 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 775                                     uint32_t mem_value)
 776 {
 777     int array = (addr & 0x00800000) >> 23;
 778     int index = (addr & 0x00003f00) >> 8;
 779     tlb_t * entry = &s->utlb[index];
 780
 781     increment_urc(s); /* per utlb access */
 782
 783     if (array == 0) {
 784         /* UTLB Data Array 1 */
 785         if (entry->v) {
 786             /* Overwriting valid entry in utlb. */
 787             target_ulong address = entry->vpn << 10;
 788             tlb_flush_page(s, address);
 789         }
 790         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 791         entry->v   = (mem_value & 0x00000100) >> 8;
 792         entry->sz  = (mem_value & 0x00000080) >> 6 |
 793                      (mem_value & 0x00000010) >> 4;
 794         entry->pr  = (mem_value & 0x00000060) >> 5;
 795         entry->c   = (mem_value & 0x00000008) >> 3;
 796         entry->d   = (mem_value & 0x00000004) >> 2;
 797         entry->sh  = (mem_value & 0x00000002) >> 1;
 798         entry->wt  = (mem_value & 0x00000001);
 799     } else {
 800         /* UTLB Data Array 2 */
 801         entry->tc = (mem_value & 0x00000008) >> 3;
 802         entry->sa = (mem_value & 0x00000007);
 803     }
 804 }
 805
 806 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 807 {
 808     int n;
 809     int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 810
 811     /* check area */
 812     if (env->sr & SR_MD) {
 813         /* For previledged mode, P2 and P4 area is not cachable. */
 814         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 815             return 0;
 816     } else {
 817         /* For user mode, only U0 area is cachable. */
 818         if (0x80000000 <= addr)
 819             return 0;
 820     }
 821
 822     /*
 823      * TODO : Evaluate CCR and check if the cache is on or off.
 824      *        Now CCR is not in CPUSH4State, but in SH7750State.
 825      *        When you move the ccr into CPUSH4State, the code will be
 826      *        as follows.
 827      */
 828 #if 0
 829     /* check if operand cache is enabled or not. */
 830     if (!(env->ccr & 1))
 831         return 0;
 832 #endif
 833
 834     /* if MMU is off, no check for TLB. */
 835     if (env->mmucr & MMUCR_AT)
 836         return 1;
 837
 838     /* check TLB */
 839     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 840     if (n >= 0)
 841         return env->itlb[n].c;
 842
 843     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 844     if (n >= 0)
 845         return env->utlb[n].c;
 846
 847     return 0;
 848 }
 849
 850 #endif