2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "disas/disas.h"
24 #include "qemu/host-utils.h"
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
41 # define LOG_DISAS(...) do { } while (0)
43 /*****************************************************************************/
44 /* Code translation helpers */
46 /* global register indexes */
47 static TCGv_ptr cpu_env
;
48 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 static TCGv cpu_gpr
[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh
[32];
59 static TCGv_i64 cpu_fpr
[32];
60 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
61 static TCGv_i32 cpu_crf
[8];
66 #if defined(TARGET_PPC64)
69 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
70 static TCGv cpu_reserve
;
71 static TCGv cpu_fpscr
;
72 static TCGv_i32 cpu_access_type
;
74 #include "exec/gen-icount.h"
76 void ppc_translate_init(void)
80 size_t cpu_reg_names_size
;
81 static int done_init
= 0;
86 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
89 cpu_reg_names_size
= sizeof(cpu_reg_names
);
91 for (i
= 0; i
< 8; i
++) {
92 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
93 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
94 offsetof(CPUPPCState
, crf
[i
]), p
);
96 cpu_reg_names_size
-= 5;
99 for (i
= 0; i
< 32; i
++) {
100 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
101 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
102 offsetof(CPUPPCState
, gpr
[i
]), p
);
103 p
+= (i
< 10) ? 3 : 4;
104 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
107 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
108 offsetof(CPUPPCState
, gprh
[i
]), p
);
109 p
+= (i
< 10) ? 4 : 5;
110 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
113 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
114 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUPPCState
, fpr
[i
]), p
);
116 p
+= (i
< 10) ? 4 : 5;
117 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
119 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
127 p
+= (i
< 10) ? 6 : 7;
128 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
130 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
138 p
+= (i
< 10) ? 6 : 7;
139 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
142 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
143 offsetof(CPUPPCState
, nip
), "nip");
145 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
146 offsetof(CPUPPCState
, msr
), "msr");
148 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
149 offsetof(CPUPPCState
, ctr
), "ctr");
151 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
152 offsetof(CPUPPCState
, lr
), "lr");
154 #if defined(TARGET_PPC64)
155 cpu_cfar
= tcg_global_mem_new(TCG_AREG0
,
156 offsetof(CPUPPCState
, cfar
), "cfar");
159 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
160 offsetof(CPUPPCState
, xer
), "xer");
161 cpu_so
= tcg_global_mem_new(TCG_AREG0
,
162 offsetof(CPUPPCState
, so
), "SO");
163 cpu_ov
= tcg_global_mem_new(TCG_AREG0
,
164 offsetof(CPUPPCState
, ov
), "OV");
165 cpu_ca
= tcg_global_mem_new(TCG_AREG0
,
166 offsetof(CPUPPCState
, ca
), "CA");
168 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
169 offsetof(CPUPPCState
, reserve_addr
),
172 cpu_fpscr
= tcg_global_mem_new(TCG_AREG0
,
173 offsetof(CPUPPCState
, fpscr
), "fpscr");
175 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
176 offsetof(CPUPPCState
, access_type
), "access_type");
178 /* register helpers */
185 /* internal defines */
186 typedef struct DisasContext
{
187 struct TranslationBlock
*tb
;
191 /* Routine used to access memory */
194 /* Translation flags */
196 #if defined(TARGET_PPC64)
203 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled
;
207 /* True when active word size < size of target_long. */
209 # define NARROW_MODE(C) (!(C)->sf_mode)
211 # define NARROW_MODE(C) 0
214 struct opc_handler_t
{
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
219 /* instruction type */
221 /* extended instruction type */
224 void (*handler
)(DisasContext
*ctx
);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
228 #if defined(DO_PPC_STATISTICS)
233 static inline void gen_reset_fpstatus(void)
235 gen_helper_reset_fpstatus(cpu_env
);
238 static inline void gen_compute_fprf(TCGv_i64 arg
, int set_fprf
, int set_rc
)
240 TCGv_i32 t0
= tcg_temp_new_i32();
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0
, 1);
245 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
246 if (unlikely(set_rc
)) {
247 tcg_gen_mov_i32(cpu_crf
[1], t0
);
249 gen_helper_float_check_status(cpu_env
);
250 } else if (unlikely(set_rc
)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0
, 0);
253 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
254 tcg_gen_mov_i32(cpu_crf
[1], t0
);
257 tcg_temp_free_i32(t0
);
260 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
262 if (ctx
->access_type
!= access_type
) {
263 tcg_gen_movi_i32(cpu_access_type
, access_type
);
264 ctx
->access_type
= access_type
;
268 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
270 if (NARROW_MODE(ctx
)) {
273 tcg_gen_movi_tl(cpu_nip
, nip
);
276 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
279 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
280 gen_update_nip(ctx
, ctx
->nip
);
282 t0
= tcg_const_i32(excp
);
283 t1
= tcg_const_i32(error
);
284 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
285 tcg_temp_free_i32(t0
);
286 tcg_temp_free_i32(t1
);
287 ctx
->exception
= (excp
);
290 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
293 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
294 gen_update_nip(ctx
, ctx
->nip
);
296 t0
= tcg_const_i32(excp
);
297 gen_helper_raise_exception(cpu_env
, t0
);
298 tcg_temp_free_i32(t0
);
299 ctx
->exception
= (excp
);
302 static inline void gen_debug_exception(DisasContext
*ctx
)
306 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
307 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
308 gen_update_nip(ctx
, ctx
->nip
);
310 t0
= tcg_const_i32(EXCP_DEBUG
);
311 gen_helper_raise_exception(cpu_env
, t0
);
312 tcg_temp_free_i32(t0
);
315 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
317 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext
*ctx
)
323 gen_update_nip(ctx
, ctx
->nip
);
324 ctx
->exception
= POWERPC_EXCP_STOP
;
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext
*ctx
)
330 ctx
->exception
= POWERPC_EXCP_SYNC
;
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
345 typedef struct opcode_t
{
346 unsigned char opc1
, opc2
, opc3
;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad
[5];
350 unsigned char pad
[1];
352 opc_handler_t handler
;
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
371 EXTRACT_HELPER(opc1
, 26, 6);
373 EXTRACT_HELPER(opc2
, 1, 5);
375 EXTRACT_HELPER(opc3
, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc
, 0, 1);
379 EXTRACT_HELPER(rD
, 21, 5);
381 EXTRACT_HELPER(rS
, 21, 5);
383 EXTRACT_HELPER(rA
, 16, 5);
385 EXTRACT_HELPER(rB
, 11, 5);
387 EXTRACT_HELPER(rC
, 6, 5);
389 EXTRACT_HELPER(crfD
, 23, 3);
390 EXTRACT_HELPER(crfS
, 18, 3);
391 EXTRACT_HELPER(crbD
, 21, 5);
392 EXTRACT_HELPER(crbA
, 16, 5);
393 EXTRACT_HELPER(crbB
, 11, 5);
395 EXTRACT_HELPER(_SPR
, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode
)
398 uint32_t sprn
= _SPR(opcode
);
400 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM
, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM
, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM
, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5
, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5
, 16, 5);
413 EXTRACT_HELPER(NB
, 11, 5);
415 EXTRACT_HELPER(SH
, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH
, 6, 4);
419 EXTRACT_HELPER(MB
, 6, 5);
421 EXTRACT_HELPER(ME
, 1, 5);
423 EXTRACT_HELPER(TO
, 21, 5);
425 EXTRACT_HELPER(CRM
, 12, 8);
426 EXTRACT_HELPER(FM
, 17, 8);
427 EXTRACT_HELPER(SR
, 16, 4);
428 EXTRACT_HELPER(FPIMM
, 12, 4);
430 /*** Jump target decoding ***/
432 EXTRACT_SHELPER(d
, 0, 16);
433 /* Immediate address */
434 static inline target_ulong
LI(uint32_t opcode
)
436 return (opcode
>> 0) & 0x03FFFFFC;
439 static inline uint32_t BD(uint32_t opcode
)
441 return (opcode
>> 0) & 0xFFFC;
444 EXTRACT_HELPER(BO
, 21, 5);
445 EXTRACT_HELPER(BI
, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA
, 1, 1);
449 EXTRACT_HELPER(LK
, 0, 1);
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
456 #if defined(TARGET_PPC64)
457 if (likely(start
== 0)) {
458 ret
= UINT64_MAX
<< (63 - end
);
459 } else if (likely(end
== 63)) {
460 ret
= UINT64_MAX
>> start
;
463 if (likely(start
== 0)) {
464 ret
= UINT32_MAX
<< (31 - end
);
465 } else if (likely(end
== 31)) {
466 ret
= UINT32_MAX
>> start
;
470 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
471 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
472 if (unlikely(start
> end
))
479 /*****************************************************************************/
480 /* PowerPC instructions table */
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
496 .oname = stringify(name), \
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
512 .oname = stringify(name), \
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
524 .handler = &gen_##name, \
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
540 .handler = &gen_##name, \
542 .oname = stringify(name), \
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
555 .handler = &gen_##name, \
557 .oname = stringify(name), \
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
569 .handler = &gen_##name, \
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t
, int reg
)
578 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
581 static inline void gen_store_spr(int reg
, TCGv t
)
583 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext
*ctx
)
589 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
592 static opc_handler_t invalid_handler
= {
593 .inval1
= 0xFFFFFFFF,
594 .inval2
= 0xFFFFFFFF,
597 .handler
= gen_invalid
,
600 /*** Integer comparison ***/
602 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
604 TCGv t0
= tcg_temp_new();
605 TCGv_i32 t1
= tcg_temp_new_i32();
607 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
609 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
610 tcg_gen_trunc_tl_i32(t1
, t0
);
611 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
612 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
614 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
615 tcg_gen_trunc_tl_i32(t1
, t0
);
616 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
617 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
619 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
620 tcg_gen_trunc_tl_i32(t1
, t0
);
621 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
622 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
625 tcg_temp_free_i32(t1
);
628 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
630 TCGv t0
= tcg_const_tl(arg1
);
631 gen_op_cmp(arg0
, t0
, s
, crf
);
635 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
641 tcg_gen_ext32s_tl(t0
, arg0
);
642 tcg_gen_ext32s_tl(t1
, arg1
);
644 tcg_gen_ext32u_tl(t0
, arg0
);
645 tcg_gen_ext32u_tl(t1
, arg1
);
647 gen_op_cmp(t0
, t1
, s
, crf
);
652 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
654 TCGv t0
= tcg_const_tl(arg1
);
655 gen_op_cmp32(arg0
, t0
, s
, crf
);
659 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
661 if (NARROW_MODE(ctx
)) {
662 gen_op_cmpi32(reg
, 0, 1, 0);
664 gen_op_cmpi(reg
, 0, 1, 0);
669 static void gen_cmp(DisasContext
*ctx
)
671 if (NARROW_MODE(ctx
) || !(ctx
->opcode
& 0x00200000)) {
672 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
673 1, crfD(ctx
->opcode
));
675 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
676 1, crfD(ctx
->opcode
));
681 static void gen_cmpi(DisasContext
*ctx
)
683 if (NARROW_MODE(ctx
) || !(ctx
->opcode
& 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
685 1, crfD(ctx
->opcode
));
687 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
688 1, crfD(ctx
->opcode
));
693 static void gen_cmpl(DisasContext
*ctx
)
695 if (NARROW_MODE(ctx
) || !(ctx
->opcode
& 0x00200000)) {
696 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
697 0, crfD(ctx
->opcode
));
699 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
700 0, crfD(ctx
->opcode
));
705 static void gen_cmpli(DisasContext
*ctx
)
707 if (NARROW_MODE(ctx
) || !(ctx
->opcode
& 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
709 0, crfD(ctx
->opcode
));
711 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
712 0, crfD(ctx
->opcode
));
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext
*ctx
)
720 uint32_t bi
= rC(ctx
->opcode
);
724 l1
= gen_new_label();
725 l2
= gen_new_label();
727 mask
= 1 << (3 - (bi
& 0x03));
728 t0
= tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
730 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
731 if (rA(ctx
->opcode
) == 0)
732 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
734 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
737 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
739 tcg_temp_free_i32(t0
);
742 /* cmpb: PowerPC 2.05 specification */
743 static void gen_cmpb(DisasContext
*ctx
)
745 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
746 cpu_gpr
[rB(ctx
->opcode
)]);
749 /*** Integer arithmetic ***/
751 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
752 TCGv arg1
, TCGv arg2
, int sub
)
754 TCGv t0
= tcg_temp_new();
756 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
757 tcg_gen_xor_tl(t0
, arg1
, arg2
);
759 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
761 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
764 if (NARROW_MODE(ctx
)) {
765 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
767 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
768 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
771 /* Common add function */
772 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
773 TCGv arg2
, bool add_ca
, bool compute_ca
,
774 bool compute_ov
, bool compute_rc0
)
778 if (compute_ca
|| compute_ov
) {
783 if (NARROW_MODE(ctx
)) {
784 /* Caution: a non-obvious corner case of the spec is that we
785 must produce the *entire* 64-bit addition, but produce the
786 carry into bit 32. */
787 TCGv t1
= tcg_temp_new();
788 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
789 tcg_gen_add_tl(t0
, arg1
, arg2
);
791 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
793 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
795 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
796 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
798 TCGv zero
= tcg_const_tl(0);
800 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
801 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
803 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
808 tcg_gen_add_tl(t0
, arg1
, arg2
);
810 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
815 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
817 if (unlikely(compute_rc0
)) {
818 gen_set_Rc0(ctx
, t0
);
821 if (!TCGV_EQUAL(t0
, ret
)) {
822 tcg_gen_mov_tl(ret
, t0
);
826 /* Add functions with two operands */
827 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
828 static void glue(gen_, name)(DisasContext *ctx) \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
834 /* Add functions with one operand and one immediate */
835 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
836 add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
839 TCGv t0 = tcg_const_tl(const_val); \
840 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
841 cpu_gpr[rA(ctx->opcode)], t0, \
842 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
846 /* add add. addo addo. */
847 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
848 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
849 /* addc addc. addco addco. */
850 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
851 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
852 /* adde adde. addeo addeo. */
853 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
854 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
855 /* addme addme. addmeo addmeo. */
856 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
857 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
858 /* addze addze. addzeo addzeo.*/
859 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
862 static void gen_addi(DisasContext
*ctx
)
864 target_long simm
= SIMM(ctx
->opcode
);
866 if (rA(ctx
->opcode
) == 0) {
868 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
870 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
871 cpu_gpr
[rA(ctx
->opcode
)], simm
);
875 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
877 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
878 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
879 c
, 0, 1, 0, compute_rc0
);
883 static void gen_addic(DisasContext
*ctx
)
885 gen_op_addic(ctx
, 0);
888 static void gen_addic_(DisasContext
*ctx
)
890 gen_op_addic(ctx
, 1);
894 static void gen_addis(DisasContext
*ctx
)
896 target_long simm
= SIMM(ctx
->opcode
);
898 if (rA(ctx
->opcode
) == 0) {
900 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
902 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
903 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
907 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
908 TCGv arg2
, int sign
, int compute_ov
)
910 int l1
= gen_new_label();
911 int l2
= gen_new_label();
912 TCGv_i32 t0
= tcg_temp_local_new_i32();
913 TCGv_i32 t1
= tcg_temp_local_new_i32();
915 tcg_gen_trunc_tl_i32(t0
, arg1
);
916 tcg_gen_trunc_tl_i32(t1
, arg2
);
917 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
919 int l3
= gen_new_label();
920 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
921 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
923 tcg_gen_div_i32(t0
, t0
, t1
);
925 tcg_gen_divu_i32(t0
, t0
, t1
);
928 tcg_gen_movi_tl(cpu_ov
, 0);
933 tcg_gen_sari_i32(t0
, t0
, 31);
935 tcg_gen_movi_i32(t0
, 0);
938 tcg_gen_movi_tl(cpu_ov
, 1);
939 tcg_gen_movi_tl(cpu_so
, 1);
942 tcg_gen_extu_i32_tl(ret
, t0
);
943 tcg_temp_free_i32(t0
);
944 tcg_temp_free_i32(t1
);
945 if (unlikely(Rc(ctx
->opcode
) != 0))
946 gen_set_Rc0(ctx
, ret
);
949 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
950 static void glue(gen_, name)(DisasContext *ctx) \
952 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
953 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
956 /* divwu divwu. divwuo divwuo. */
957 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
958 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
959 /* divw divw. divwo divwo. */
960 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
961 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
962 #if defined(TARGET_PPC64)
963 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
964 TCGv arg2
, int sign
, int compute_ov
)
966 int l1
= gen_new_label();
967 int l2
= gen_new_label();
969 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
971 int l3
= gen_new_label();
972 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
973 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
975 tcg_gen_div_i64(ret
, arg1
, arg2
);
977 tcg_gen_divu_i64(ret
, arg1
, arg2
);
980 tcg_gen_movi_tl(cpu_ov
, 0);
985 tcg_gen_sari_i64(ret
, arg1
, 63);
987 tcg_gen_movi_i64(ret
, 0);
990 tcg_gen_movi_tl(cpu_ov
, 1);
991 tcg_gen_movi_tl(cpu_so
, 1);
994 if (unlikely(Rc(ctx
->opcode
) != 0))
995 gen_set_Rc0(ctx
, ret
);
997 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
998 static void glue(gen_, name)(DisasContext *ctx) \
1000 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1002 sign, compute_ov); \
1004 /* divwu divwu. divwuo divwuo. */
1005 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1006 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1007 /* divw divw. divwo divwo. */
1008 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1009 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1013 static void gen_mulhw(DisasContext
*ctx
)
1015 TCGv_i32 t0
= tcg_temp_new_i32();
1016 TCGv_i32 t1
= tcg_temp_new_i32();
1018 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1019 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1020 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1021 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1022 tcg_temp_free_i32(t0
);
1023 tcg_temp_free_i32(t1
);
1024 if (unlikely(Rc(ctx
->opcode
) != 0))
1025 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1028 /* mulhwu mulhwu. */
1029 static void gen_mulhwu(DisasContext
*ctx
)
1031 TCGv_i32 t0
= tcg_temp_new_i32();
1032 TCGv_i32 t1
= tcg_temp_new_i32();
1034 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1035 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1036 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1037 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1038 tcg_temp_free_i32(t0
);
1039 tcg_temp_free_i32(t1
);
1040 if (unlikely(Rc(ctx
->opcode
) != 0))
1041 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1045 static void gen_mullw(DisasContext
*ctx
)
1047 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1048 cpu_gpr
[rB(ctx
->opcode
)]);
1049 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1050 if (unlikely(Rc(ctx
->opcode
) != 0))
1051 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1054 /* mullwo mullwo. */
1055 static void gen_mullwo(DisasContext
*ctx
)
1057 TCGv_i32 t0
= tcg_temp_new_i32();
1058 TCGv_i32 t1
= tcg_temp_new_i32();
1060 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1061 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1062 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1063 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1065 tcg_gen_sari_i32(t0
, t0
, 31);
1066 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1067 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1068 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1070 tcg_temp_free_i32(t0
);
1071 tcg_temp_free_i32(t1
);
1072 if (unlikely(Rc(ctx
->opcode
) != 0))
1073 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1077 static void gen_mulli(DisasContext
*ctx
)
1079 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1083 #if defined(TARGET_PPC64)
1085 static void gen_mulhd(DisasContext
*ctx
)
1087 TCGv lo
= tcg_temp_new();
1088 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1089 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1091 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1092 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1096 /* mulhdu mulhdu. */
1097 static void gen_mulhdu(DisasContext
*ctx
)
1099 TCGv lo
= tcg_temp_new();
1100 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1101 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1103 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1104 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1109 static void gen_mulld(DisasContext
*ctx
)
1111 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1112 cpu_gpr
[rB(ctx
->opcode
)]);
1113 if (unlikely(Rc(ctx
->opcode
) != 0))
1114 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1117 /* mulldo mulldo. */
1118 static void gen_mulldo(DisasContext
*ctx
)
1120 gen_helper_mulldo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
1121 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1122 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1123 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1128 /* Common subf function */
1129 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1130 TCGv arg2
, bool add_ca
, bool compute_ca
,
1131 bool compute_ov
, bool compute_rc0
)
1135 if (compute_ca
|| compute_ov
) {
1136 t0
= tcg_temp_new();
1140 /* dest = ~arg1 + arg2 [+ ca]. */
1141 if (NARROW_MODE(ctx
)) {
1142 /* Caution: a non-obvious corner case of the spec is that we
1143 must produce the *entire* 64-bit addition, but produce the
1144 carry into bit 32. */
1145 TCGv inv1
= tcg_temp_new();
1146 TCGv t1
= tcg_temp_new();
1147 tcg_gen_not_tl(inv1
, arg1
);
1149 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1151 tcg_gen_addi_tl(t0
, arg2
, 1);
1153 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1154 tcg_gen_add_tl(t0
, t0
, inv1
);
1155 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1157 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1158 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1159 } else if (add_ca
) {
1160 TCGv zero
, inv1
= tcg_temp_new();
1161 tcg_gen_not_tl(inv1
, arg1
);
1162 zero
= tcg_const_tl(0);
1163 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1164 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1165 tcg_temp_free(zero
);
1166 tcg_temp_free(inv1
);
1168 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1169 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1171 } else if (add_ca
) {
1172 /* Since we're ignoring carry-out, we can simplify the
1173 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1174 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1175 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1176 tcg_gen_subi_tl(t0
, t0
, 1);
1178 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1182 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1184 if (unlikely(compute_rc0
)) {
1185 gen_set_Rc0(ctx
, t0
);
1188 if (!TCGV_EQUAL(t0
, ret
)) {
1189 tcg_gen_mov_tl(ret
, t0
);
1193 /* Sub functions with Two operands functions */
1194 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1195 static void glue(gen_, name)(DisasContext *ctx) \
1197 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1198 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1199 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1201 /* Sub functions with one operand and one immediate */
1202 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1203 add_ca, compute_ca, compute_ov) \
1204 static void glue(gen_, name)(DisasContext *ctx) \
1206 TCGv t0 = tcg_const_tl(const_val); \
1207 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1208 cpu_gpr[rA(ctx->opcode)], t0, \
1209 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1210 tcg_temp_free(t0); \
1212 /* subf subf. subfo subfo. */
1213 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1214 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1215 /* subfc subfc. subfco subfco. */
1216 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1217 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1218 /* subfe subfe. subfeo subfo. */
1219 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1220 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1221 /* subfme subfme. subfmeo subfmeo. */
1222 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1223 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1224 /* subfze subfze. subfzeo subfzeo.*/
1225 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1226 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1229 static void gen_subfic(DisasContext
*ctx
)
1231 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1232 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1237 /* neg neg. nego nego. */
1238 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1240 TCGv zero
= tcg_const_tl(0);
1241 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1242 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1243 tcg_temp_free(zero
);
1246 static void gen_neg(DisasContext
*ctx
)
1248 gen_op_arith_neg(ctx
, 0);
1251 static void gen_nego(DisasContext
*ctx
)
1253 gen_op_arith_neg(ctx
, 1);
1256 /*** Integer logical ***/
1257 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1260 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1261 cpu_gpr[rB(ctx->opcode)]); \
1262 if (unlikely(Rc(ctx->opcode) != 0)) \
1263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1266 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1269 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1275 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1277 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1280 static void gen_andi_(DisasContext
*ctx
)
1282 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1283 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1287 static void gen_andis_(DisasContext
*ctx
)
1289 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1290 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1294 static void gen_cntlzw(DisasContext
*ctx
)
1296 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1297 if (unlikely(Rc(ctx
->opcode
) != 0))
1298 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1301 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1302 /* extsb & extsb. */
1303 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1304 /* extsh & extsh. */
1305 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1307 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1309 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1312 static void gen_or(DisasContext
*ctx
)
1316 rs
= rS(ctx
->opcode
);
1317 ra
= rA(ctx
->opcode
);
1318 rb
= rB(ctx
->opcode
);
1319 /* Optimisation for mr. ri case */
1320 if (rs
!= ra
|| rs
!= rb
) {
1322 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1324 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1325 if (unlikely(Rc(ctx
->opcode
) != 0))
1326 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1327 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1328 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1329 #if defined(TARGET_PPC64)
1335 /* Set process priority to low */
1339 /* Set process priority to medium-low */
1343 /* Set process priority to normal */
1346 #if !defined(CONFIG_USER_ONLY)
1348 if (ctx
->mem_idx
> 0) {
1349 /* Set process priority to very low */
1354 if (ctx
->mem_idx
> 0) {
1355 /* Set process priority to medium-hight */
1360 if (ctx
->mem_idx
> 0) {
1361 /* Set process priority to high */
1366 if (ctx
->mem_idx
> 1) {
1367 /* Set process priority to very high */
1377 TCGv t0
= tcg_temp_new();
1378 gen_load_spr(t0
, SPR_PPR
);
1379 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1380 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1381 gen_store_spr(SPR_PPR
, t0
);
1388 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1391 static void gen_xor(DisasContext
*ctx
)
1393 /* Optimisation for "set to zero" case */
1394 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1395 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1397 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1398 if (unlikely(Rc(ctx
->opcode
) != 0))
1399 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1403 static void gen_ori(DisasContext
*ctx
)
1405 target_ulong uimm
= UIMM(ctx
->opcode
);
1407 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1409 /* XXX: should handle special NOPs for POWER series */
1412 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1416 static void gen_oris(DisasContext
*ctx
)
1418 target_ulong uimm
= UIMM(ctx
->opcode
);
1420 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1424 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1428 static void gen_xori(DisasContext
*ctx
)
1430 target_ulong uimm
= UIMM(ctx
->opcode
);
1432 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1436 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1440 static void gen_xoris(DisasContext
*ctx
)
1442 target_ulong uimm
= UIMM(ctx
->opcode
);
1444 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1448 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1451 /* popcntb : PowerPC 2.03 specification */
1452 static void gen_popcntb(DisasContext
*ctx
)
1454 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1457 static void gen_popcntw(DisasContext
*ctx
)
1459 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1462 #if defined(TARGET_PPC64)
1463 /* popcntd: PowerPC 2.06 specification */
1464 static void gen_popcntd(DisasContext
*ctx
)
1466 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1470 /* prtyw: PowerPC 2.05 specification */
1471 static void gen_prtyw(DisasContext
*ctx
)
1473 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1474 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1475 TCGv t0
= tcg_temp_new();
1476 tcg_gen_shri_tl(t0
, rs
, 16);
1477 tcg_gen_xor_tl(ra
, rs
, t0
);
1478 tcg_gen_shri_tl(t0
, ra
, 8);
1479 tcg_gen_xor_tl(ra
, ra
, t0
);
1480 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1484 #if defined(TARGET_PPC64)
1485 /* prtyd: PowerPC 2.05 specification */
1486 static void gen_prtyd(DisasContext
*ctx
)
1488 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1489 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1490 TCGv t0
= tcg_temp_new();
1491 tcg_gen_shri_tl(t0
, rs
, 32);
1492 tcg_gen_xor_tl(ra
, rs
, t0
);
1493 tcg_gen_shri_tl(t0
, ra
, 16);
1494 tcg_gen_xor_tl(ra
, ra
, t0
);
1495 tcg_gen_shri_tl(t0
, ra
, 8);
1496 tcg_gen_xor_tl(ra
, ra
, t0
);
1497 tcg_gen_andi_tl(ra
, ra
, 1);
1502 #if defined(TARGET_PPC64)
1503 /* extsw & extsw. */
1504 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1507 static void gen_cntlzd(DisasContext
*ctx
)
1509 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1510 if (unlikely(Rc(ctx
->opcode
) != 0))
1511 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1515 /*** Integer rotate ***/
1517 /* rlwimi & rlwimi. */
1518 static void gen_rlwimi(DisasContext
*ctx
)
1520 uint32_t mb
, me
, sh
;
1522 mb
= MB(ctx
->opcode
);
1523 me
= ME(ctx
->opcode
);
1524 sh
= SH(ctx
->opcode
);
1525 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1526 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1530 TCGv t0
= tcg_temp_new();
1531 #if defined(TARGET_PPC64)
1532 TCGv_i32 t2
= tcg_temp_new_i32();
1533 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1534 tcg_gen_rotli_i32(t2
, t2
, sh
);
1535 tcg_gen_extu_i32_i64(t0
, t2
);
1536 tcg_temp_free_i32(t2
);
1538 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1540 #if defined(TARGET_PPC64)
1544 mask
= MASK(mb
, me
);
1545 t1
= tcg_temp_new();
1546 tcg_gen_andi_tl(t0
, t0
, mask
);
1547 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1548 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1552 if (unlikely(Rc(ctx
->opcode
) != 0))
1553 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1556 /* rlwinm & rlwinm. */
1557 static void gen_rlwinm(DisasContext
*ctx
)
1559 uint32_t mb
, me
, sh
;
1561 sh
= SH(ctx
->opcode
);
1562 mb
= MB(ctx
->opcode
);
1563 me
= ME(ctx
->opcode
);
1565 if (likely(mb
== 0 && me
== (31 - sh
))) {
1566 if (likely(sh
== 0)) {
1567 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1569 TCGv t0
= tcg_temp_new();
1570 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1571 tcg_gen_shli_tl(t0
, t0
, sh
);
1572 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1575 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1576 TCGv t0
= tcg_temp_new();
1577 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1578 tcg_gen_shri_tl(t0
, t0
, mb
);
1579 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1582 TCGv t0
= tcg_temp_new();
1583 #if defined(TARGET_PPC64)
1584 TCGv_i32 t1
= tcg_temp_new_i32();
1585 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1586 tcg_gen_rotli_i32(t1
, t1
, sh
);
1587 tcg_gen_extu_i32_i64(t0
, t1
);
1588 tcg_temp_free_i32(t1
);
1590 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1592 #if defined(TARGET_PPC64)
1596 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1599 if (unlikely(Rc(ctx
->opcode
) != 0))
1600 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1603 /* rlwnm & rlwnm. */
1604 static void gen_rlwnm(DisasContext
*ctx
)
1608 #if defined(TARGET_PPC64)
1612 mb
= MB(ctx
->opcode
);
1613 me
= ME(ctx
->opcode
);
1614 t0
= tcg_temp_new();
1615 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1616 #if defined(TARGET_PPC64)
1617 t1
= tcg_temp_new_i32();
1618 t2
= tcg_temp_new_i32();
1619 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1620 tcg_gen_trunc_i64_i32(t2
, t0
);
1621 tcg_gen_rotl_i32(t1
, t1
, t2
);
1622 tcg_gen_extu_i32_i64(t0
, t1
);
1623 tcg_temp_free_i32(t1
);
1624 tcg_temp_free_i32(t2
);
1626 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1628 if (unlikely(mb
!= 0 || me
!= 31)) {
1629 #if defined(TARGET_PPC64)
1633 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1635 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1638 if (unlikely(Rc(ctx
->opcode
) != 0))
1639 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1642 #if defined(TARGET_PPC64)
1643 #define GEN_PPC64_R2(name, opc1, opc2) \
1644 static void glue(gen_, name##0)(DisasContext *ctx) \
1646 gen_##name(ctx, 0); \
1649 static void glue(gen_, name##1)(DisasContext *ctx) \
1651 gen_##name(ctx, 1); \
1653 #define GEN_PPC64_R4(name, opc1, opc2) \
1654 static void glue(gen_, name##0)(DisasContext *ctx) \
1656 gen_##name(ctx, 0, 0); \
1659 static void glue(gen_, name##1)(DisasContext *ctx) \
1661 gen_##name(ctx, 0, 1); \
1664 static void glue(gen_, name##2)(DisasContext *ctx) \
1666 gen_##name(ctx, 1, 0); \
1669 static void glue(gen_, name##3)(DisasContext *ctx) \
1671 gen_##name(ctx, 1, 1); \
1674 static inline void gen_rldinm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1677 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1678 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1679 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1680 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1682 TCGv t0
= tcg_temp_new();
1683 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1684 if (likely(mb
== 0 && me
== 63)) {
1685 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1687 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1691 if (unlikely(Rc(ctx
->opcode
) != 0))
1692 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1694 /* rldicl - rldicl. */
1695 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1699 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1700 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1701 gen_rldinm(ctx
, mb
, 63, sh
);
1703 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1704 /* rldicr - rldicr. */
1705 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1709 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1710 me
= MB(ctx
->opcode
) | (men
<< 5);
1711 gen_rldinm(ctx
, 0, me
, sh
);
1713 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1714 /* rldic - rldic. */
1715 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1719 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1720 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1721 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1723 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1725 static inline void gen_rldnm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1729 mb
= MB(ctx
->opcode
);
1730 me
= ME(ctx
->opcode
);
1731 t0
= tcg_temp_new();
1732 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1733 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1734 if (unlikely(mb
!= 0 || me
!= 63)) {
1735 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1737 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1740 if (unlikely(Rc(ctx
->opcode
) != 0))
1741 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1744 /* rldcl - rldcl. */
1745 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1749 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1750 gen_rldnm(ctx
, mb
, 63);
1752 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1753 /* rldcr - rldcr. */
1754 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1758 me
= MB(ctx
->opcode
) | (men
<< 5);
1759 gen_rldnm(ctx
, 0, me
);
1761 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1762 /* rldimi - rldimi. */
1763 static inline void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1765 uint32_t sh
, mb
, me
;
1767 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1768 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1770 if (unlikely(sh
== 0 && mb
== 0)) {
1771 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1776 t0
= tcg_temp_new();
1777 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1778 t1
= tcg_temp_new();
1779 mask
= MASK(mb
, me
);
1780 tcg_gen_andi_tl(t0
, t0
, mask
);
1781 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1782 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1786 if (unlikely(Rc(ctx
->opcode
) != 0))
1787 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1789 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1792 /*** Integer shift ***/
1795 static void gen_slw(DisasContext
*ctx
)
1799 t0
= tcg_temp_new();
1800 /* AND rS with a mask that is 0 when rB >= 0x20 */
1801 #if defined(TARGET_PPC64)
1802 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1803 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1805 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1806 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1808 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1809 t1
= tcg_temp_new();
1810 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1811 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1814 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1815 if (unlikely(Rc(ctx
->opcode
) != 0))
1816 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1820 static void gen_sraw(DisasContext
*ctx
)
1822 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1823 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1824 if (unlikely(Rc(ctx
->opcode
) != 0))
1825 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1828 /* srawi & srawi. */
1829 static void gen_srawi(DisasContext
*ctx
)
1831 int sh
= SH(ctx
->opcode
);
1832 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1833 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1835 tcg_gen_mov_tl(dst
, src
);
1836 tcg_gen_movi_tl(cpu_ca
, 0);
1839 tcg_gen_ext32s_tl(dst
, src
);
1840 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
1841 t0
= tcg_temp_new();
1842 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
1843 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1845 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1846 tcg_gen_sari_tl(dst
, dst
, sh
);
1848 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1849 gen_set_Rc0(ctx
, dst
);
1854 static void gen_srw(DisasContext
*ctx
)
1858 t0
= tcg_temp_new();
1859 /* AND rS with a mask that is 0 when rB >= 0x20 */
1860 #if defined(TARGET_PPC64)
1861 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1862 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1864 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1865 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1867 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1868 tcg_gen_ext32u_tl(t0
, t0
);
1869 t1
= tcg_temp_new();
1870 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1871 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1874 if (unlikely(Rc(ctx
->opcode
) != 0))
1875 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1878 #if defined(TARGET_PPC64)
1880 static void gen_sld(DisasContext
*ctx
)
1884 t0
= tcg_temp_new();
1885 /* AND rS with a mask that is 0 when rB >= 0x40 */
1886 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1887 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1888 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1889 t1
= tcg_temp_new();
1890 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1891 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1894 if (unlikely(Rc(ctx
->opcode
) != 0))
1895 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1899 static void gen_srad(DisasContext
*ctx
)
1901 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1902 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1903 if (unlikely(Rc(ctx
->opcode
) != 0))
1904 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1906 /* sradi & sradi. */
1907 static inline void gen_sradi(DisasContext
*ctx
, int n
)
1909 int sh
= SH(ctx
->opcode
) + (n
<< 5);
1910 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1911 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1913 tcg_gen_mov_tl(dst
, src
);
1914 tcg_gen_movi_tl(cpu_ca
, 0);
1917 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
1918 t0
= tcg_temp_new();
1919 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
1920 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1922 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1923 tcg_gen_sari_tl(dst
, src
, sh
);
1925 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1926 gen_set_Rc0(ctx
, dst
);
1930 static void gen_sradi0(DisasContext
*ctx
)
1935 static void gen_sradi1(DisasContext
*ctx
)
1941 static void gen_srd(DisasContext
*ctx
)
1945 t0
= tcg_temp_new();
1946 /* AND rS with a mask that is 0 when rB >= 0x40 */
1947 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1948 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1949 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1950 t1
= tcg_temp_new();
1951 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1952 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1955 if (unlikely(Rc(ctx
->opcode
) != 0))
1956 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1960 /*** Floating-Point arithmetic ***/
1961 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1962 static void gen_f##name(DisasContext *ctx) \
1964 if (unlikely(!ctx->fpu_enabled)) { \
1965 gen_exception(ctx, POWERPC_EXCP_FPU); \
1968 /* NIP cannot be restored if the memory exception comes from an helper */ \
1969 gen_update_nip(ctx, ctx->nip - 4); \
1970 gen_reset_fpstatus(); \
1971 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1972 cpu_fpr[rA(ctx->opcode)], \
1973 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1975 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1976 cpu_fpr[rD(ctx->opcode)]); \
1978 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1979 Rc(ctx->opcode) != 0); \
1982 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1983 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1984 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1986 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1987 static void gen_f##name(DisasContext *ctx) \
1989 if (unlikely(!ctx->fpu_enabled)) { \
1990 gen_exception(ctx, POWERPC_EXCP_FPU); \
1993 /* NIP cannot be restored if the memory exception comes from an helper */ \
1994 gen_update_nip(ctx, ctx->nip - 4); \
1995 gen_reset_fpstatus(); \
1996 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1997 cpu_fpr[rA(ctx->opcode)], \
1998 cpu_fpr[rB(ctx->opcode)]); \
2000 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2001 cpu_fpr[rD(ctx->opcode)]); \
2003 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2004 set_fprf, Rc(ctx->opcode) != 0); \
2006 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2007 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2008 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2010 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2011 static void gen_f##name(DisasContext *ctx) \
2013 if (unlikely(!ctx->fpu_enabled)) { \
2014 gen_exception(ctx, POWERPC_EXCP_FPU); \
2017 /* NIP cannot be restored if the memory exception comes from an helper */ \
2018 gen_update_nip(ctx, ctx->nip - 4); \
2019 gen_reset_fpstatus(); \
2020 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2021 cpu_fpr[rA(ctx->opcode)], \
2022 cpu_fpr[rC(ctx->opcode)]); \
2024 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2025 cpu_fpr[rD(ctx->opcode)]); \
2027 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2028 set_fprf, Rc(ctx->opcode) != 0); \
2030 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2031 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2032 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2034 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2035 static void gen_f##name(DisasContext *ctx) \
2037 if (unlikely(!ctx->fpu_enabled)) { \
2038 gen_exception(ctx, POWERPC_EXCP_FPU); \
2041 /* NIP cannot be restored if the memory exception comes from an helper */ \
2042 gen_update_nip(ctx, ctx->nip - 4); \
2043 gen_reset_fpstatus(); \
2044 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2045 cpu_fpr[rB(ctx->opcode)]); \
2046 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2047 set_fprf, Rc(ctx->opcode) != 0); \
2050 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rB(ctx->opcode)]); \
2062 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2063 set_fprf, Rc(ctx->opcode) != 0); \
2067 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2069 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2071 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2074 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2077 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2080 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2083 static void gen_frsqrtes(DisasContext
*ctx
)
2085 if (unlikely(!ctx
->fpu_enabled
)) {
2086 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2089 /* NIP cannot be restored if the memory exception comes from an helper */
2090 gen_update_nip(ctx
, ctx
->nip
- 4);
2091 gen_reset_fpstatus();
2092 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2093 cpu_fpr
[rB(ctx
->opcode
)]);
2094 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2095 cpu_fpr
[rD(ctx
->opcode
)]);
2096 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2100 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2102 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2106 static void gen_fsqrt(DisasContext
*ctx
)
2108 if (unlikely(!ctx
->fpu_enabled
)) {
2109 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx
, ctx
->nip
- 4);
2114 gen_reset_fpstatus();
2115 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2116 cpu_fpr
[rB(ctx
->opcode
)]);
2117 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2120 static void gen_fsqrts(DisasContext
*ctx
)
2122 if (unlikely(!ctx
->fpu_enabled
)) {
2123 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2126 /* NIP cannot be restored if the memory exception comes from an helper */
2127 gen_update_nip(ctx
, ctx
->nip
- 4);
2128 gen_reset_fpstatus();
2129 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2130 cpu_fpr
[rB(ctx
->opcode
)]);
2131 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2132 cpu_fpr
[rD(ctx
->opcode
)]);
2133 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2136 /*** Floating-Point multiply-and-add ***/
2137 /* fmadd - fmadds */
2138 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2139 /* fmsub - fmsubs */
2140 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2141 /* fnmadd - fnmadds */
2142 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2143 /* fnmsub - fnmsubs */
2144 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2146 /*** Floating-Point round & convert ***/
2148 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2150 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2152 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2153 #if defined(TARGET_PPC64)
2155 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2157 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2159 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2163 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2165 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2167 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2169 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2171 /*** Floating-Point compare ***/
2174 static void gen_fcmpo(DisasContext
*ctx
)
2177 if (unlikely(!ctx
->fpu_enabled
)) {
2178 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2181 /* NIP cannot be restored if the memory exception comes from an helper */
2182 gen_update_nip(ctx
, ctx
->nip
- 4);
2183 gen_reset_fpstatus();
2184 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2185 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2186 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2187 tcg_temp_free_i32(crf
);
2188 gen_helper_float_check_status(cpu_env
);
2192 static void gen_fcmpu(DisasContext
*ctx
)
2195 if (unlikely(!ctx
->fpu_enabled
)) {
2196 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2199 /* NIP cannot be restored if the memory exception comes from an helper */
2200 gen_update_nip(ctx
, ctx
->nip
- 4);
2201 gen_reset_fpstatus();
2202 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2203 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2204 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2205 tcg_temp_free_i32(crf
);
2206 gen_helper_float_check_status(cpu_env
);
2209 /*** Floating-point move ***/
2211 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2212 static void gen_fabs(DisasContext
*ctx
)
2214 if (unlikely(!ctx
->fpu_enabled
)) {
2215 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2218 tcg_gen_andi_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2220 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2224 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2225 static void gen_fmr(DisasContext
*ctx
)
2227 if (unlikely(!ctx
->fpu_enabled
)) {
2228 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2231 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2232 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2236 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2237 static void gen_fnabs(DisasContext
*ctx
)
2239 if (unlikely(!ctx
->fpu_enabled
)) {
2240 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2243 tcg_gen_ori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2245 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2249 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2250 static void gen_fneg(DisasContext
*ctx
)
2252 if (unlikely(!ctx
->fpu_enabled
)) {
2253 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2256 tcg_gen_xori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2258 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2261 /* fcpsgn: PowerPC 2.05 specification */
2262 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2263 static void gen_fcpsgn(DisasContext
*ctx
)
2265 if (unlikely(!ctx
->fpu_enabled
)) {
2266 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2269 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2270 cpu_fpr
[rB(ctx
->opcode
)], 0, 63);
2271 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2274 /*** Floating-Point status & ctrl register ***/
2277 static void gen_mcrfs(DisasContext
*ctx
)
2279 TCGv tmp
= tcg_temp_new();
2282 if (unlikely(!ctx
->fpu_enabled
)) {
2283 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2286 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2287 tcg_gen_shri_tl(tmp
, cpu_fpscr
, bfa
);
2288 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2290 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2291 tcg_gen_andi_tl(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2295 static void gen_mffs(DisasContext
*ctx
)
2297 if (unlikely(!ctx
->fpu_enabled
)) {
2298 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2301 gen_reset_fpstatus();
2302 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2303 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2307 static void gen_mtfsb0(DisasContext
*ctx
)
2311 if (unlikely(!ctx
->fpu_enabled
)) {
2312 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2315 crb
= 31 - crbD(ctx
->opcode
);
2316 gen_reset_fpstatus();
2317 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx
, ctx
->nip
- 4);
2321 t0
= tcg_const_i32(crb
);
2322 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2323 tcg_temp_free_i32(t0
);
2325 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2326 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2327 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2332 static void gen_mtfsb1(DisasContext
*ctx
)
2336 if (unlikely(!ctx
->fpu_enabled
)) {
2337 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2340 crb
= 31 - crbD(ctx
->opcode
);
2341 gen_reset_fpstatus();
2342 /* XXX: we pretend we can only do IEEE floating-point computations */
2343 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2345 /* NIP cannot be restored if the memory exception comes from an helper */
2346 gen_update_nip(ctx
, ctx
->nip
- 4);
2347 t0
= tcg_const_i32(crb
);
2348 gen_helper_fpscr_setbit(cpu_env
, t0
);
2349 tcg_temp_free_i32(t0
);
2351 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2352 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2353 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2355 /* We can raise a differed exception */
2356 gen_helper_float_check_status(cpu_env
);
2360 static void gen_mtfsf(DisasContext
*ctx
)
2363 int L
= ctx
->opcode
& 0x02000000;
2365 if (unlikely(!ctx
->fpu_enabled
)) {
2366 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2369 /* NIP cannot be restored if the memory exception comes from an helper */
2370 gen_update_nip(ctx
, ctx
->nip
- 4);
2371 gen_reset_fpstatus();
2373 t0
= tcg_const_i32(0xff);
2375 t0
= tcg_const_i32(FM(ctx
->opcode
));
2376 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2377 tcg_temp_free_i32(t0
);
2378 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2379 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2380 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2382 /* We can raise a differed exception */
2383 gen_helper_float_check_status(cpu_env
);
2387 static void gen_mtfsfi(DisasContext
*ctx
)
2393 if (unlikely(!ctx
->fpu_enabled
)) {
2394 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2397 bf
= crbD(ctx
->opcode
) >> 2;
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx
, ctx
->nip
- 4);
2401 gen_reset_fpstatus();
2402 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2403 t1
= tcg_const_i32(1 << sh
);
2404 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2405 tcg_temp_free_i64(t0
);
2406 tcg_temp_free_i32(t1
);
2407 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2408 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2409 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2411 /* We can raise a differed exception */
2412 gen_helper_float_check_status(cpu_env
);
2415 /*** Addressing modes ***/
2416 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2417 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2420 target_long simm
= SIMM(ctx
->opcode
);
2423 if (rA(ctx
->opcode
) == 0) {
2424 if (NARROW_MODE(ctx
)) {
2425 simm
= (uint32_t)simm
;
2427 tcg_gen_movi_tl(EA
, simm
);
2428 } else if (likely(simm
!= 0)) {
2429 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2430 if (NARROW_MODE(ctx
)) {
2431 tcg_gen_ext32u_tl(EA
, EA
);
2434 if (NARROW_MODE(ctx
)) {
2435 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2437 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2442 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2444 if (rA(ctx
->opcode
) == 0) {
2445 if (NARROW_MODE(ctx
)) {
2446 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2448 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2451 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2452 if (NARROW_MODE(ctx
)) {
2453 tcg_gen_ext32u_tl(EA
, EA
);
2458 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2460 if (rA(ctx
->opcode
) == 0) {
2461 tcg_gen_movi_tl(EA
, 0);
2462 } else if (NARROW_MODE(ctx
)) {
2463 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2465 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2469 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2472 tcg_gen_addi_tl(ret
, arg1
, val
);
2473 if (NARROW_MODE(ctx
)) {
2474 tcg_gen_ext32u_tl(ret
, ret
);
2478 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2480 int l1
= gen_new_label();
2481 TCGv t0
= tcg_temp_new();
2483 /* NIP cannot be restored if the memory exception comes from an helper */
2484 gen_update_nip(ctx
, ctx
->nip
- 4);
2485 tcg_gen_andi_tl(t0
, EA
, mask
);
2486 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2487 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2488 t2
= tcg_const_i32(0);
2489 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2490 tcg_temp_free_i32(t1
);
2491 tcg_temp_free_i32(t2
);
2496 /*** Integer load ***/
2497 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2499 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2502 static inline void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2504 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2507 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2509 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2510 if (unlikely(ctx
->le_mode
)) {
2511 tcg_gen_bswap16_tl(arg1
, arg1
);
2515 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2517 if (unlikely(ctx
->le_mode
)) {
2518 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2519 tcg_gen_bswap16_tl(arg1
, arg1
);
2520 tcg_gen_ext16s_tl(arg1
, arg1
);
2522 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2526 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2528 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2529 if (unlikely(ctx
->le_mode
)) {
2530 tcg_gen_bswap32_tl(arg1
, arg1
);
2534 #if defined(TARGET_PPC64)
2535 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2537 if (unlikely(ctx
->le_mode
)) {
2538 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2539 tcg_gen_bswap32_tl(arg1
, arg1
);
2540 tcg_gen_ext32s_tl(arg1
, arg1
);
2542 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2546 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2548 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2549 if (unlikely(ctx
->le_mode
)) {
2550 tcg_gen_bswap64_i64(arg1
, arg1
);
2554 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2556 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2559 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2561 if (unlikely(ctx
->le_mode
)) {
2562 TCGv t0
= tcg_temp_new();
2563 tcg_gen_ext16u_tl(t0
, arg1
);
2564 tcg_gen_bswap16_tl(t0
, t0
);
2565 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2568 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2572 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2574 if (unlikely(ctx
->le_mode
)) {
2575 TCGv t0
= tcg_temp_new();
2576 tcg_gen_ext32u_tl(t0
, arg1
);
2577 tcg_gen_bswap32_tl(t0
, t0
);
2578 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2581 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2585 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2587 if (unlikely(ctx
->le_mode
)) {
2588 TCGv_i64 t0
= tcg_temp_new_i64();
2589 tcg_gen_bswap64_i64(t0
, arg1
);
2590 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2591 tcg_temp_free_i64(t0
);
2593 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2596 #define GEN_LD(name, ldop, opc, type) \
2597 static void glue(gen_, name)(DisasContext *ctx) \
2600 gen_set_access_type(ctx, ACCESS_INT); \
2601 EA = tcg_temp_new(); \
2602 gen_addr_imm_index(ctx, EA, 0); \
2603 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2604 tcg_temp_free(EA); \
2607 #define GEN_LDU(name, ldop, opc, type) \
2608 static void glue(gen_, name##u)(DisasContext *ctx) \
2611 if (unlikely(rA(ctx->opcode) == 0 || \
2612 rA(ctx->opcode) == rD(ctx->opcode))) { \
2613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2616 gen_set_access_type(ctx, ACCESS_INT); \
2617 EA = tcg_temp_new(); \
2618 if (type == PPC_64B) \
2619 gen_addr_imm_index(ctx, EA, 0x03); \
2621 gen_addr_imm_index(ctx, EA, 0); \
2622 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2623 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2624 tcg_temp_free(EA); \
2627 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2628 static void glue(gen_, name##ux)(DisasContext *ctx) \
2631 if (unlikely(rA(ctx->opcode) == 0 || \
2632 rA(ctx->opcode) == rD(ctx->opcode))) { \
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2636 gen_set_access_type(ctx, ACCESS_INT); \
2637 EA = tcg_temp_new(); \
2638 gen_addr_reg_index(ctx, EA); \
2639 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2640 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2641 tcg_temp_free(EA); \
2644 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2645 static void glue(gen_, name##x)(DisasContext *ctx) \
2648 gen_set_access_type(ctx, ACCESS_INT); \
2649 EA = tcg_temp_new(); \
2650 gen_addr_reg_index(ctx, EA); \
2651 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2652 tcg_temp_free(EA); \
2654 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2655 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2657 #define GEN_LDS(name, ldop, op, type) \
2658 GEN_LD(name, ldop, op | 0x20, type); \
2659 GEN_LDU(name, ldop, op | 0x21, type); \
2660 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2661 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2663 /* lbz lbzu lbzux lbzx */
2664 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2665 /* lha lhau lhaux lhax */
2666 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2667 /* lhz lhzu lhzux lhzx */
2668 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2669 /* lwz lwzu lwzux lwzx */
2670 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2671 #if defined(TARGET_PPC64)
2673 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2675 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2677 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2679 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2681 static void gen_ld(DisasContext
*ctx
)
2684 if (Rc(ctx
->opcode
)) {
2685 if (unlikely(rA(ctx
->opcode
) == 0 ||
2686 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2687 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2691 gen_set_access_type(ctx
, ACCESS_INT
);
2692 EA
= tcg_temp_new();
2693 gen_addr_imm_index(ctx
, EA
, 0x03);
2694 if (ctx
->opcode
& 0x02) {
2695 /* lwa (lwau is undefined) */
2696 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2699 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2701 if (Rc(ctx
->opcode
))
2702 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2707 static void gen_lq(DisasContext
*ctx
)
2709 #if defined(CONFIG_USER_ONLY)
2710 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2715 /* Restore CPU state */
2716 if (unlikely(ctx
->mem_idx
== 0)) {
2717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2720 ra
= rA(ctx
->opcode
);
2721 rd
= rD(ctx
->opcode
);
2722 if (unlikely((rd
& 1) || rd
== ra
)) {
2723 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2726 if (unlikely(ctx
->le_mode
)) {
2727 /* Little-endian mode is not handled */
2728 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2731 gen_set_access_type(ctx
, ACCESS_INT
);
2732 EA
= tcg_temp_new();
2733 gen_addr_imm_index(ctx
, EA
, 0x0F);
2734 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2735 gen_addr_add(ctx
, EA
, EA
, 8);
2736 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2742 /*** Integer store ***/
2743 #define GEN_ST(name, stop, opc, type) \
2744 static void glue(gen_, name)(DisasContext *ctx) \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_imm_index(ctx, EA, 0); \
2750 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2751 tcg_temp_free(EA); \
2754 #define GEN_STU(name, stop, opc, type) \
2755 static void glue(gen_, stop##u)(DisasContext *ctx) \
2758 if (unlikely(rA(ctx->opcode) == 0)) { \
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2762 gen_set_access_type(ctx, ACCESS_INT); \
2763 EA = tcg_temp_new(); \
2764 if (type == PPC_64B) \
2765 gen_addr_imm_index(ctx, EA, 0x03); \
2767 gen_addr_imm_index(ctx, EA, 0); \
2768 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2773 #define GEN_STUX(name, stop, opc2, opc3, type) \
2774 static void glue(gen_, name##ux)(DisasContext *ctx) \
2777 if (unlikely(rA(ctx->opcode) == 0)) { \
2778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2781 gen_set_access_type(ctx, ACCESS_INT); \
2782 EA = tcg_temp_new(); \
2783 gen_addr_reg_index(ctx, EA); \
2784 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2785 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2786 tcg_temp_free(EA); \
2789 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2790 static void glue(gen_, name##x)(DisasContext *ctx) \
2793 gen_set_access_type(ctx, ACCESS_INT); \
2794 EA = tcg_temp_new(); \
2795 gen_addr_reg_index(ctx, EA); \
2796 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2797 tcg_temp_free(EA); \
2799 #define GEN_STX(name, stop, opc2, opc3, type) \
2800 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2802 #define GEN_STS(name, stop, op, type) \
2803 GEN_ST(name, stop, op | 0x20, type); \
2804 GEN_STU(name, stop, op | 0x21, type); \
2805 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2806 GEN_STX(name, stop, 0x17, op | 0x00, type)
2808 /* stb stbu stbux stbx */
2809 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2810 /* sth sthu sthux sthx */
2811 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2812 /* stw stwu stwux stwx */
2813 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2814 #if defined(TARGET_PPC64)
2815 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2816 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2818 static void gen_std(DisasContext
*ctx
)
2823 rs
= rS(ctx
->opcode
);
2824 if ((ctx
->opcode
& 0x3) == 0x2) {
2825 #if defined(CONFIG_USER_ONLY)
2826 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2829 if (unlikely(ctx
->mem_idx
== 0)) {
2830 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2833 if (unlikely(rs
& 1)) {
2834 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2837 if (unlikely(ctx
->le_mode
)) {
2838 /* Little-endian mode is not handled */
2839 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2842 gen_set_access_type(ctx
, ACCESS_INT
);
2843 EA
= tcg_temp_new();
2844 gen_addr_imm_index(ctx
, EA
, 0x03);
2845 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2846 gen_addr_add(ctx
, EA
, EA
, 8);
2847 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2852 if (Rc(ctx
->opcode
)) {
2853 if (unlikely(rA(ctx
->opcode
) == 0)) {
2854 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2858 gen_set_access_type(ctx
, ACCESS_INT
);
2859 EA
= tcg_temp_new();
2860 gen_addr_imm_index(ctx
, EA
, 0x03);
2861 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2862 if (Rc(ctx
->opcode
))
2863 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2868 /*** Integer load and store with byte reverse ***/
2870 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2872 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2873 if (likely(!ctx
->le_mode
)) {
2874 tcg_gen_bswap16_tl(arg1
, arg1
);
2877 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2880 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2882 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2883 if (likely(!ctx
->le_mode
)) {
2884 tcg_gen_bswap32_tl(arg1
, arg1
);
2887 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2889 #if defined(TARGET_PPC64)
2891 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2893 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2894 if (likely(!ctx
->le_mode
)) {
2895 tcg_gen_bswap64_tl(arg1
, arg1
);
2898 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
2899 #endif /* TARGET_PPC64 */
2902 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2904 if (likely(!ctx
->le_mode
)) {
2905 TCGv t0
= tcg_temp_new();
2906 tcg_gen_ext16u_tl(t0
, arg1
);
2907 tcg_gen_bswap16_tl(t0
, t0
);
2908 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2911 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2914 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2917 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2919 if (likely(!ctx
->le_mode
)) {
2920 TCGv t0
= tcg_temp_new();
2921 tcg_gen_ext32u_tl(t0
, arg1
);
2922 tcg_gen_bswap32_tl(t0
, t0
);
2923 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2926 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2929 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2931 #if defined(TARGET_PPC64)
2933 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2935 if (likely(!ctx
->le_mode
)) {
2936 TCGv t0
= tcg_temp_new();
2937 tcg_gen_bswap64_tl(t0
, arg1
);
2938 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2941 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2944 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
2945 #endif /* TARGET_PPC64 */
2947 /*** Integer load and store multiple ***/
2950 static void gen_lmw(DisasContext
*ctx
)
2954 gen_set_access_type(ctx
, ACCESS_INT
);
2955 /* NIP cannot be restored if the memory exception comes from an helper */
2956 gen_update_nip(ctx
, ctx
->nip
- 4);
2957 t0
= tcg_temp_new();
2958 t1
= tcg_const_i32(rD(ctx
->opcode
));
2959 gen_addr_imm_index(ctx
, t0
, 0);
2960 gen_helper_lmw(cpu_env
, t0
, t1
);
2962 tcg_temp_free_i32(t1
);
2966 static void gen_stmw(DisasContext
*ctx
)
2970 gen_set_access_type(ctx
, ACCESS_INT
);
2971 /* NIP cannot be restored if the memory exception comes from an helper */
2972 gen_update_nip(ctx
, ctx
->nip
- 4);
2973 t0
= tcg_temp_new();
2974 t1
= tcg_const_i32(rS(ctx
->opcode
));
2975 gen_addr_imm_index(ctx
, t0
, 0);
2976 gen_helper_stmw(cpu_env
, t0
, t1
);
2978 tcg_temp_free_i32(t1
);
2981 /*** Integer load and store strings ***/
2984 /* PowerPC32 specification says we must generate an exception if
2985 * rA is in the range of registers to be loaded.
2986 * In an other hand, IBM says this is valid, but rA won't be loaded.
2987 * For now, I'll follow the spec...
2989 static void gen_lswi(DisasContext
*ctx
)
2993 int nb
= NB(ctx
->opcode
);
2994 int start
= rD(ctx
->opcode
);
2995 int ra
= rA(ctx
->opcode
);
3001 if (unlikely(((start
+ nr
) > 32 &&
3002 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3003 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3004 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3007 gen_set_access_type(ctx
, ACCESS_INT
);
3008 /* NIP cannot be restored if the memory exception comes from an helper */
3009 gen_update_nip(ctx
, ctx
->nip
- 4);
3010 t0
= tcg_temp_new();
3011 gen_addr_register(ctx
, t0
);
3012 t1
= tcg_const_i32(nb
);
3013 t2
= tcg_const_i32(start
);
3014 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3016 tcg_temp_free_i32(t1
);
3017 tcg_temp_free_i32(t2
);
3021 static void gen_lswx(DisasContext
*ctx
)
3024 TCGv_i32 t1
, t2
, t3
;
3025 gen_set_access_type(ctx
, ACCESS_INT
);
3026 /* NIP cannot be restored if the memory exception comes from an helper */
3027 gen_update_nip(ctx
, ctx
->nip
- 4);
3028 t0
= tcg_temp_new();
3029 gen_addr_reg_index(ctx
, t0
);
3030 t1
= tcg_const_i32(rD(ctx
->opcode
));
3031 t2
= tcg_const_i32(rA(ctx
->opcode
));
3032 t3
= tcg_const_i32(rB(ctx
->opcode
));
3033 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3035 tcg_temp_free_i32(t1
);
3036 tcg_temp_free_i32(t2
);
3037 tcg_temp_free_i32(t3
);
3041 static void gen_stswi(DisasContext
*ctx
)
3045 int nb
= NB(ctx
->opcode
);
3046 gen_set_access_type(ctx
, ACCESS_INT
);
3047 /* NIP cannot be restored if the memory exception comes from an helper */
3048 gen_update_nip(ctx
, ctx
->nip
- 4);
3049 t0
= tcg_temp_new();
3050 gen_addr_register(ctx
, t0
);
3053 t1
= tcg_const_i32(nb
);
3054 t2
= tcg_const_i32(rS(ctx
->opcode
));
3055 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3057 tcg_temp_free_i32(t1
);
3058 tcg_temp_free_i32(t2
);
3062 static void gen_stswx(DisasContext
*ctx
)
3066 gen_set_access_type(ctx
, ACCESS_INT
);
3067 /* NIP cannot be restored if the memory exception comes from an helper */
3068 gen_update_nip(ctx
, ctx
->nip
- 4);
3069 t0
= tcg_temp_new();
3070 gen_addr_reg_index(ctx
, t0
);
3071 t1
= tcg_temp_new_i32();
3072 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3073 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3074 t2
= tcg_const_i32(rS(ctx
->opcode
));
3075 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3077 tcg_temp_free_i32(t1
);
3078 tcg_temp_free_i32(t2
);
3081 /*** Memory synchronisation ***/
3083 static void gen_eieio(DisasContext
*ctx
)
3088 static void gen_isync(DisasContext
*ctx
)
3090 gen_stop_exception(ctx
);
3094 static void gen_lwarx(DisasContext
*ctx
)
3097 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3098 gen_set_access_type(ctx
, ACCESS_RES
);
3099 t0
= tcg_temp_local_new();
3100 gen_addr_reg_index(ctx
, t0
);
3101 gen_check_align(ctx
, t0
, 0x03);
3102 gen_qemu_ld32u(ctx
, gpr
, t0
);
3103 tcg_gen_mov_tl(cpu_reserve
, t0
);
3104 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3108 #if defined(CONFIG_USER_ONLY)
3109 static void gen_conditional_store (DisasContext
*ctx
, TCGv EA
,
3112 TCGv t0
= tcg_temp_new();
3113 uint32_t save_exception
= ctx
->exception
;
3115 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3116 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3117 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3119 gen_update_nip(ctx
, ctx
->nip
-4);
3120 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3121 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3122 ctx
->exception
= save_exception
;
3127 static void gen_stwcx_(DisasContext
*ctx
)
3130 gen_set_access_type(ctx
, ACCESS_RES
);
3131 t0
= tcg_temp_local_new();
3132 gen_addr_reg_index(ctx
, t0
);
3133 gen_check_align(ctx
, t0
, 0x03);
3134 #if defined(CONFIG_USER_ONLY)
3135 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 4);
3140 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3141 l1
= gen_new_label();
3142 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3143 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3144 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3146 tcg_gen_movi_tl(cpu_reserve
, -1);
3152 #if defined(TARGET_PPC64)
3154 static void gen_ldarx(DisasContext
*ctx
)
3157 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3158 gen_set_access_type(ctx
, ACCESS_RES
);
3159 t0
= tcg_temp_local_new();
3160 gen_addr_reg_index(ctx
, t0
);
3161 gen_check_align(ctx
, t0
, 0x07);
3162 gen_qemu_ld64(ctx
, gpr
, t0
);
3163 tcg_gen_mov_tl(cpu_reserve
, t0
);
3164 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3169 static void gen_stdcx_(DisasContext
*ctx
)
3172 gen_set_access_type(ctx
, ACCESS_RES
);
3173 t0
= tcg_temp_local_new();
3174 gen_addr_reg_index(ctx
, t0
);
3175 gen_check_align(ctx
, t0
, 0x07);
3176 #if defined(CONFIG_USER_ONLY)
3177 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 8);
3181 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3182 l1
= gen_new_label();
3183 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3184 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3185 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3187 tcg_gen_movi_tl(cpu_reserve
, -1);
3192 #endif /* defined(TARGET_PPC64) */
3195 static void gen_sync(DisasContext
*ctx
)
3200 static void gen_wait(DisasContext
*ctx
)
3202 TCGv_i32 t0
= tcg_temp_new_i32();
3203 tcg_gen_st_i32(t0
, cpu_env
,
3204 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3205 tcg_temp_free_i32(t0
);
3206 /* Stop translation, as the CPU is supposed to sleep from now */
3207 gen_exception_err(ctx
, EXCP_HLT
, 1);
3210 /*** Floating-point load ***/
3211 #define GEN_LDF(name, ldop, opc, type) \
3212 static void glue(gen_, name)(DisasContext *ctx) \
3215 if (unlikely(!ctx->fpu_enabled)) { \
3216 gen_exception(ctx, POWERPC_EXCP_FPU); \
3219 gen_set_access_type(ctx, ACCESS_FLOAT); \
3220 EA = tcg_temp_new(); \
3221 gen_addr_imm_index(ctx, EA, 0); \
3222 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3223 tcg_temp_free(EA); \
3226 #define GEN_LDUF(name, ldop, opc, type) \
3227 static void glue(gen_, name##u)(DisasContext *ctx) \
3230 if (unlikely(!ctx->fpu_enabled)) { \
3231 gen_exception(ctx, POWERPC_EXCP_FPU); \
3234 if (unlikely(rA(ctx->opcode) == 0)) { \
3235 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3238 gen_set_access_type(ctx, ACCESS_FLOAT); \
3239 EA = tcg_temp_new(); \
3240 gen_addr_imm_index(ctx, EA, 0); \
3241 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3242 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3243 tcg_temp_free(EA); \
3246 #define GEN_LDUXF(name, ldop, opc, type) \
3247 static void glue(gen_, name##ux)(DisasContext *ctx) \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3254 if (unlikely(rA(ctx->opcode) == 0)) { \
3255 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3258 gen_set_access_type(ctx, ACCESS_FLOAT); \
3259 EA = tcg_temp_new(); \
3260 gen_addr_reg_index(ctx, EA); \
3261 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3262 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3263 tcg_temp_free(EA); \
3266 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3267 static void glue(gen_, name##x)(DisasContext *ctx) \
3270 if (unlikely(!ctx->fpu_enabled)) { \
3271 gen_exception(ctx, POWERPC_EXCP_FPU); \
3274 gen_set_access_type(ctx, ACCESS_FLOAT); \
3275 EA = tcg_temp_new(); \
3276 gen_addr_reg_index(ctx, EA); \
3277 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3281 #define GEN_LDFS(name, ldop, op, type) \
3282 GEN_LDF(name, ldop, op | 0x20, type); \
3283 GEN_LDUF(name, ldop, op | 0x21, type); \
3284 GEN_LDUXF(name, ldop, op | 0x01, type); \
3285 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3287 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3289 TCGv t0
= tcg_temp_new();
3290 TCGv_i32 t1
= tcg_temp_new_i32();
3291 gen_qemu_ld32u(ctx
, t0
, arg2
);
3292 tcg_gen_trunc_tl_i32(t1
, t0
);
3294 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3295 tcg_temp_free_i32(t1
);
3298 /* lfd lfdu lfdux lfdx */
3299 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3300 /* lfs lfsu lfsux lfsx */
3301 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3304 static void gen_lfiwax(DisasContext
*ctx
)
3308 if (unlikely(!ctx
->fpu_enabled
)) {
3309 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3312 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3313 EA
= tcg_temp_new();
3314 t0
= tcg_temp_new();
3315 gen_addr_reg_index(ctx
, EA
);
3316 gen_qemu_ld32u(ctx
, t0
, EA
);
3317 tcg_gen_ext_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], t0
);
3318 tcg_gen_ext32s_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
3323 /*** Floating-point store ***/
3324 #define GEN_STF(name, stop, opc, type) \
3325 static void glue(gen_, name)(DisasContext *ctx) \
3328 if (unlikely(!ctx->fpu_enabled)) { \
3329 gen_exception(ctx, POWERPC_EXCP_FPU); \
3332 gen_set_access_type(ctx, ACCESS_FLOAT); \
3333 EA = tcg_temp_new(); \
3334 gen_addr_imm_index(ctx, EA, 0); \
3335 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
3339 #define GEN_STUF(name, stop, opc, type) \
3340 static void glue(gen_, name##u)(DisasContext *ctx) \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3347 if (unlikely(rA(ctx->opcode) == 0)) { \
3348 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3351 gen_set_access_type(ctx, ACCESS_FLOAT); \
3352 EA = tcg_temp_new(); \
3353 gen_addr_imm_index(ctx, EA, 0); \
3354 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3356 tcg_temp_free(EA); \
3359 #define GEN_STUXF(name, stop, opc, type) \
3360 static void glue(gen_, name##ux)(DisasContext *ctx) \
3363 if (unlikely(!ctx->fpu_enabled)) { \
3364 gen_exception(ctx, POWERPC_EXCP_FPU); \
3367 if (unlikely(rA(ctx->opcode) == 0)) { \
3368 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3371 gen_set_access_type(ctx, ACCESS_FLOAT); \
3372 EA = tcg_temp_new(); \
3373 gen_addr_reg_index(ctx, EA); \
3374 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3375 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3376 tcg_temp_free(EA); \
3379 #define GEN_STXF(name, stop, opc2, opc3, type) \
3380 static void glue(gen_, name##x)(DisasContext *ctx) \
3383 if (unlikely(!ctx->fpu_enabled)) { \
3384 gen_exception(ctx, POWERPC_EXCP_FPU); \
3387 gen_set_access_type(ctx, ACCESS_FLOAT); \
3388 EA = tcg_temp_new(); \
3389 gen_addr_reg_index(ctx, EA); \
3390 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3391 tcg_temp_free(EA); \
3394 #define GEN_STFS(name, stop, op, type) \
3395 GEN_STF(name, stop, op | 0x20, type); \
3396 GEN_STUF(name, stop, op | 0x21, type); \
3397 GEN_STUXF(name, stop, op | 0x01, type); \
3398 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3400 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3402 TCGv_i32 t0
= tcg_temp_new_i32();
3403 TCGv t1
= tcg_temp_new();
3404 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3405 tcg_gen_extu_i32_tl(t1
, t0
);
3406 tcg_temp_free_i32(t0
);
3407 gen_qemu_st32(ctx
, t1
, arg2
);
3411 /* stfd stfdu stfdux stfdx */
3412 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3413 /* stfs stfsu stfsux stfsx */
3414 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3417 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3419 TCGv t0
= tcg_temp_new();
3420 tcg_gen_trunc_i64_tl(t0
, arg1
),
3421 gen_qemu_st32(ctx
, t0
, arg2
);
3425 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3427 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3429 #if defined(TARGET_PPC64)
3431 tcg_gen_movi_tl(cpu_cfar
, nip
);
3436 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3438 TranslationBlock
*tb
;
3440 if (NARROW_MODE(ctx
)) {
3441 dest
= (uint32_t) dest
;
3443 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3444 likely(!ctx
->singlestep_enabled
)) {
3446 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3447 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
3449 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3450 if (unlikely(ctx
->singlestep_enabled
)) {
3451 if ((ctx
->singlestep_enabled
&
3452 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3453 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3454 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3455 target_ulong tmp
= ctx
->nip
;
3457 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3460 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3461 gen_debug_exception(ctx
);
3468 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3470 if (NARROW_MODE(ctx
)) {
3471 nip
= (uint32_t)nip
;
3473 tcg_gen_movi_tl(cpu_lr
, nip
);
3477 static void gen_b(DisasContext
*ctx
)
3479 target_ulong li
, target
;
3481 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3482 /* sign extend LI */
3483 li
= LI(ctx
->opcode
);
3484 li
= (li
^ 0x02000000) - 0x02000000;
3485 if (likely(AA(ctx
->opcode
) == 0)) {
3486 target
= ctx
->nip
+ li
- 4;
3490 if (LK(ctx
->opcode
)) {
3491 gen_setlr(ctx
, ctx
->nip
);
3493 gen_update_cfar(ctx
, ctx
->nip
);
3494 gen_goto_tb(ctx
, 0, target
);
3501 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3503 uint32_t bo
= BO(ctx
->opcode
);
3507 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3508 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3509 target
= tcg_temp_local_new();
3510 if (type
== BCOND_CTR
)
3511 tcg_gen_mov_tl(target
, cpu_ctr
);
3513 tcg_gen_mov_tl(target
, cpu_lr
);
3515 TCGV_UNUSED(target
);
3517 if (LK(ctx
->opcode
))
3518 gen_setlr(ctx
, ctx
->nip
);
3519 l1
= gen_new_label();
3520 if ((bo
& 0x4) == 0) {
3521 /* Decrement and test CTR */
3522 TCGv temp
= tcg_temp_new();
3523 if (unlikely(type
== BCOND_CTR
)) {
3524 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3527 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3528 if (NARROW_MODE(ctx
)) {
3529 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3531 tcg_gen_mov_tl(temp
, cpu_ctr
);
3534 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3536 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3538 tcg_temp_free(temp
);
3540 if ((bo
& 0x10) == 0) {
3542 uint32_t bi
= BI(ctx
->opcode
);
3543 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3544 TCGv_i32 temp
= tcg_temp_new_i32();
3547 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3548 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3550 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3551 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3553 tcg_temp_free_i32(temp
);
3555 gen_update_cfar(ctx
, ctx
->nip
);
3556 if (type
== BCOND_IM
) {
3557 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3558 if (likely(AA(ctx
->opcode
) == 0)) {
3559 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3561 gen_goto_tb(ctx
, 0, li
);
3564 gen_goto_tb(ctx
, 1, ctx
->nip
);
3566 if (NARROW_MODE(ctx
)) {
3567 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3569 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3573 gen_update_nip(ctx
, ctx
->nip
);
3578 static void gen_bc(DisasContext
*ctx
)
3580 gen_bcond(ctx
, BCOND_IM
);
3583 static void gen_bcctr(DisasContext
*ctx
)
3585 gen_bcond(ctx
, BCOND_CTR
);
3588 static void gen_bclr(DisasContext
*ctx
)
3590 gen_bcond(ctx
, BCOND_LR
);
3593 /*** Condition register logical ***/
3594 #define GEN_CRLOGIC(name, tcg_op, opc) \
3595 static void glue(gen_, name)(DisasContext *ctx) \
3600 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3601 t0 = tcg_temp_new_i32(); \
3603 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3605 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3607 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3608 t1 = tcg_temp_new_i32(); \
3609 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3611 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3613 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3615 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3616 tcg_op(t0, t0, t1); \
3617 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3618 tcg_gen_andi_i32(t0, t0, bitmask); \
3619 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3620 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3621 tcg_temp_free_i32(t0); \
3622 tcg_temp_free_i32(t1); \
3626 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3628 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3630 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3632 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3634 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3636 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3638 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3640 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3643 static void gen_mcrf(DisasContext
*ctx
)
3645 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3648 /*** System linkage ***/
3650 /* rfi (mem_idx only) */
3651 static void gen_rfi(DisasContext
*ctx
)
3653 #if defined(CONFIG_USER_ONLY)
3654 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3656 /* Restore CPU state */
3657 if (unlikely(!ctx
->mem_idx
)) {
3658 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3661 gen_update_cfar(ctx
, ctx
->nip
);
3662 gen_helper_rfi(cpu_env
);
3663 gen_sync_exception(ctx
);
3667 #if defined(TARGET_PPC64)
3668 static void gen_rfid(DisasContext
*ctx
)
3670 #if defined(CONFIG_USER_ONLY)
3671 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3673 /* Restore CPU state */
3674 if (unlikely(!ctx
->mem_idx
)) {
3675 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3678 gen_update_cfar(ctx
, ctx
->nip
);
3679 gen_helper_rfid(cpu_env
);
3680 gen_sync_exception(ctx
);
3684 static void gen_hrfid(DisasContext
*ctx
)
3686 #if defined(CONFIG_USER_ONLY)
3687 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3689 /* Restore CPU state */
3690 if (unlikely(ctx
->mem_idx
<= 1)) {
3691 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3694 gen_helper_hrfid(cpu_env
);
3695 gen_sync_exception(ctx
);
3701 #if defined(CONFIG_USER_ONLY)
3702 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3704 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3706 static void gen_sc(DisasContext
*ctx
)
3710 lev
= (ctx
->opcode
>> 5) & 0x7F;
3711 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3717 static void gen_tw(DisasContext
*ctx
)
3719 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3720 /* Update the nip since this might generate a trap exception */
3721 gen_update_nip(ctx
, ctx
->nip
);
3722 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3724 tcg_temp_free_i32(t0
);
3728 static void gen_twi(DisasContext
*ctx
)
3730 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3731 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3732 /* Update the nip since this might generate a trap exception */
3733 gen_update_nip(ctx
, ctx
->nip
);
3734 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3736 tcg_temp_free_i32(t1
);
3739 #if defined(TARGET_PPC64)
3741 static void gen_td(DisasContext
*ctx
)
3743 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3744 /* Update the nip since this might generate a trap exception */
3745 gen_update_nip(ctx
, ctx
->nip
);
3746 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3748 tcg_temp_free_i32(t0
);
3752 static void gen_tdi(DisasContext
*ctx
)
3754 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3755 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3756 /* Update the nip since this might generate a trap exception */
3757 gen_update_nip(ctx
, ctx
->nip
);
3758 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3760 tcg_temp_free_i32(t1
);
3764 /*** Processor control ***/
3766 static void gen_read_xer(TCGv dst
)
3768 TCGv t0
= tcg_temp_new();
3769 TCGv t1
= tcg_temp_new();
3770 TCGv t2
= tcg_temp_new();
3771 tcg_gen_mov_tl(dst
, cpu_xer
);
3772 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3773 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3774 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3775 tcg_gen_or_tl(t0
, t0
, t1
);
3776 tcg_gen_or_tl(dst
, dst
, t2
);
3777 tcg_gen_or_tl(dst
, dst
, t0
);
3783 static void gen_write_xer(TCGv src
)
3785 tcg_gen_andi_tl(cpu_xer
, src
,
3786 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
3787 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
3788 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
3789 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
3790 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
3791 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
3792 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
3796 static void gen_mcrxr(DisasContext
*ctx
)
3798 TCGv_i32 t0
= tcg_temp_new_i32();
3799 TCGv_i32 t1
= tcg_temp_new_i32();
3800 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3802 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3803 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3804 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3805 tcg_gen_shri_i32(t0
, t0
, 2);
3806 tcg_gen_shri_i32(t1
, t1
, 1);
3807 tcg_gen_or_i32(dst
, dst
, t0
);
3808 tcg_gen_or_i32(dst
, dst
, t1
);
3809 tcg_temp_free_i32(t0
);
3810 tcg_temp_free_i32(t1
);
3812 tcg_gen_movi_tl(cpu_so
, 0);
3813 tcg_gen_movi_tl(cpu_ov
, 0);
3814 tcg_gen_movi_tl(cpu_ca
, 0);
3818 static void gen_mfcr(DisasContext
*ctx
)
3822 if (likely(ctx
->opcode
& 0x00100000)) {
3823 crm
= CRM(ctx
->opcode
);
3824 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3826 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3827 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3828 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3831 TCGv_i32 t0
= tcg_temp_new_i32();
3832 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3833 tcg_gen_shli_i32(t0
, t0
, 4);
3834 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3835 tcg_gen_shli_i32(t0
, t0
, 4);
3836 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3837 tcg_gen_shli_i32(t0
, t0
, 4);
3838 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3839 tcg_gen_shli_i32(t0
, t0
, 4);
3840 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3841 tcg_gen_shli_i32(t0
, t0
, 4);
3842 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3843 tcg_gen_shli_i32(t0
, t0
, 4);
3844 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3845 tcg_gen_shli_i32(t0
, t0
, 4);
3846 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3847 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3848 tcg_temp_free_i32(t0
);
3853 static void gen_mfmsr(DisasContext
*ctx
)
3855 #if defined(CONFIG_USER_ONLY)
3856 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3858 if (unlikely(!ctx
->mem_idx
)) {
3859 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3862 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3866 static void spr_noaccess(void *opaque
, int gprn
, int sprn
)
3869 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3870 printf("ERROR: try to access SPR %d !\n", sprn
);
3873 #define SPR_NOACCESS (&spr_noaccess)
3876 static inline void gen_op_mfspr(DisasContext
*ctx
)
3878 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3879 uint32_t sprn
= SPR(ctx
->opcode
);
3881 #if !defined(CONFIG_USER_ONLY)
3882 if (ctx
->mem_idx
== 2)
3883 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3884 else if (ctx
->mem_idx
)
3885 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3888 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3889 if (likely(read_cb
!= NULL
)) {
3890 if (likely(read_cb
!= SPR_NOACCESS
)) {
3891 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3893 /* Privilege exception */
3894 /* This is a hack to avoid warnings when running Linux:
3895 * this OS breaks the PowerPC virtualisation model,
3896 * allowing userland application to read the PVR
3898 if (sprn
!= SPR_PVR
) {
3899 qemu_log("Trying to read privileged spr %d %03x at "
3900 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3901 printf("Trying to read privileged spr %d %03x at "
3902 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3904 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3908 qemu_log("Trying to read invalid spr %d %03x at "
3909 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3910 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx
"\n",
3911 sprn
, sprn
, ctx
->nip
);
3912 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3916 static void gen_mfspr(DisasContext
*ctx
)
3922 static void gen_mftb(DisasContext
*ctx
)
3928 static void gen_mtcrf(DisasContext
*ctx
)
3932 crm
= CRM(ctx
->opcode
);
3933 if (likely((ctx
->opcode
& 0x00100000))) {
3934 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3935 TCGv_i32 temp
= tcg_temp_new_i32();
3937 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3938 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3939 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3940 tcg_temp_free_i32(temp
);
3943 TCGv_i32 temp
= tcg_temp_new_i32();
3944 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3945 for (crn
= 0 ; crn
< 8 ; crn
++) {
3946 if (crm
& (1 << crn
)) {
3947 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3948 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3951 tcg_temp_free_i32(temp
);
3956 #if defined(TARGET_PPC64)
3957 static void gen_mtmsrd(DisasContext
*ctx
)
3959 #if defined(CONFIG_USER_ONLY)
3960 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3962 if (unlikely(!ctx
->mem_idx
)) {
3963 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3966 if (ctx
->opcode
& 0x00010000) {
3967 /* Special form that does not need any synchronisation */
3968 TCGv t0
= tcg_temp_new();
3969 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3970 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3971 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3974 /* XXX: we need to update nip before the store
3975 * if we enter power saving mode, we will exit the loop
3976 * directly from ppc_store_msr
3978 gen_update_nip(ctx
, ctx
->nip
);
3979 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
3980 /* Must stop the translation as machine state (may have) changed */
3981 /* Note that mtmsr is not always defined as context-synchronizing */
3982 gen_stop_exception(ctx
);
3988 static void gen_mtmsr(DisasContext
*ctx
)
3990 #if defined(CONFIG_USER_ONLY)
3991 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3993 if (unlikely(!ctx
->mem_idx
)) {
3994 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3997 if (ctx
->opcode
& 0x00010000) {
3998 /* Special form that does not need any synchronisation */
3999 TCGv t0
= tcg_temp_new();
4000 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4001 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4002 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4005 TCGv msr
= tcg_temp_new();
4007 /* XXX: we need to update nip before the store
4008 * if we enter power saving mode, we will exit the loop
4009 * directly from ppc_store_msr
4011 gen_update_nip(ctx
, ctx
->nip
);
4012 #if defined(TARGET_PPC64)
4013 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4015 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4017 gen_helper_store_msr(cpu_env
, msr
);
4018 /* Must stop the translation as machine state (may have) changed */
4019 /* Note that mtmsr is not always defined as context-synchronizing */
4020 gen_stop_exception(ctx
);
4026 static void gen_mtspr(DisasContext
*ctx
)
4028 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
4029 uint32_t sprn
= SPR(ctx
->opcode
);
4031 #if !defined(CONFIG_USER_ONLY)
4032 if (ctx
->mem_idx
== 2)
4033 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4034 else if (ctx
->mem_idx
)
4035 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4038 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4039 if (likely(write_cb
!= NULL
)) {
4040 if (likely(write_cb
!= SPR_NOACCESS
)) {
4041 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4043 /* Privilege exception */
4044 qemu_log("Trying to write privileged spr %d %03x at "
4045 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
4046 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4047 "\n", sprn
, sprn
, ctx
->nip
);
4048 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4052 qemu_log("Trying to write invalid spr %d %03x at "
4053 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
4054 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx
"\n",
4055 sprn
, sprn
, ctx
->nip
);
4056 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4060 /*** Cache management ***/
4063 static void gen_dcbf(DisasContext
*ctx
)
4065 /* XXX: specification says this is treated as a load by the MMU */
4067 gen_set_access_type(ctx
, ACCESS_CACHE
);
4068 t0
= tcg_temp_new();
4069 gen_addr_reg_index(ctx
, t0
);
4070 gen_qemu_ld8u(ctx
, t0
, t0
);
4074 /* dcbi (Supervisor only) */
4075 static void gen_dcbi(DisasContext
*ctx
)
4077 #if defined(CONFIG_USER_ONLY)
4078 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4081 if (unlikely(!ctx
->mem_idx
)) {
4082 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4085 EA
= tcg_temp_new();
4086 gen_set_access_type(ctx
, ACCESS_CACHE
);
4087 gen_addr_reg_index(ctx
, EA
);
4088 val
= tcg_temp_new();
4089 /* XXX: specification says this should be treated as a store by the MMU */
4090 gen_qemu_ld8u(ctx
, val
, EA
);
4091 gen_qemu_st8(ctx
, val
, EA
);
4098 static void gen_dcbst(DisasContext
*ctx
)
4100 /* XXX: specification say this is treated as a load by the MMU */
4102 gen_set_access_type(ctx
, ACCESS_CACHE
);
4103 t0
= tcg_temp_new();
4104 gen_addr_reg_index(ctx
, t0
);
4105 gen_qemu_ld8u(ctx
, t0
, t0
);
4110 static void gen_dcbt(DisasContext
*ctx
)
4112 /* interpreted as no-op */
4113 /* XXX: specification say this is treated as a load by the MMU
4114 * but does not generate any exception
4119 static void gen_dcbtst(DisasContext
*ctx
)
4121 /* interpreted as no-op */
4122 /* XXX: specification say this is treated as a load by the MMU
4123 * but does not generate any exception
4128 static void gen_dcbz(DisasContext
*ctx
)
4131 TCGv_i32 tcgv_is_dcbzl
;
4132 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4134 gen_set_access_type(ctx
, ACCESS_CACHE
);
4135 /* NIP cannot be restored if the memory exception comes from an helper */
4136 gen_update_nip(ctx
, ctx
->nip
- 4);
4137 tcgv_addr
= tcg_temp_new();
4138 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4140 gen_addr_reg_index(ctx
, tcgv_addr
);
4141 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4143 tcg_temp_free(tcgv_addr
);
4144 tcg_temp_free_i32(tcgv_is_dcbzl
);
4148 static void gen_dst(DisasContext
*ctx
)
4150 if (rA(ctx
->opcode
) == 0) {
4151 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4153 /* interpreted as no-op */
4158 static void gen_dstst(DisasContext
*ctx
)
4160 if (rA(ctx
->opcode
) == 0) {
4161 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4163 /* interpreted as no-op */
4169 static void gen_dss(DisasContext
*ctx
)
4171 /* interpreted as no-op */
4175 static void gen_icbi(DisasContext
*ctx
)
4178 gen_set_access_type(ctx
, ACCESS_CACHE
);
4179 /* NIP cannot be restored if the memory exception comes from an helper */
4180 gen_update_nip(ctx
, ctx
->nip
- 4);
4181 t0
= tcg_temp_new();
4182 gen_addr_reg_index(ctx
, t0
);
4183 gen_helper_icbi(cpu_env
, t0
);
4189 static void gen_dcba(DisasContext
*ctx
)
4191 /* interpreted as no-op */
4192 /* XXX: specification say this is treated as a store by the MMU
4193 * but does not generate any exception
4197 /*** Segment register manipulation ***/
4198 /* Supervisor only: */
4201 static void gen_mfsr(DisasContext
*ctx
)
4203 #if defined(CONFIG_USER_ONLY)
4204 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4207 if (unlikely(!ctx
->mem_idx
)) {
4208 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4211 t0
= tcg_const_tl(SR(ctx
->opcode
));
4212 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4218 static void gen_mfsrin(DisasContext
*ctx
)
4220 #if defined(CONFIG_USER_ONLY)
4221 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4224 if (unlikely(!ctx
->mem_idx
)) {
4225 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4228 t0
= tcg_temp_new();
4229 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4230 tcg_gen_andi_tl(t0
, t0
, 0xF);
4231 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4237 static void gen_mtsr(DisasContext
*ctx
)
4239 #if defined(CONFIG_USER_ONLY)
4240 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4243 if (unlikely(!ctx
->mem_idx
)) {
4244 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4247 t0
= tcg_const_tl(SR(ctx
->opcode
));
4248 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4254 static void gen_mtsrin(DisasContext
*ctx
)
4256 #if defined(CONFIG_USER_ONLY)
4257 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4260 if (unlikely(!ctx
->mem_idx
)) {
4261 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4264 t0
= tcg_temp_new();
4265 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4266 tcg_gen_andi_tl(t0
, t0
, 0xF);
4267 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4272 #if defined(TARGET_PPC64)
4273 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4276 static void gen_mfsr_64b(DisasContext
*ctx
)
4278 #if defined(CONFIG_USER_ONLY)
4279 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4282 if (unlikely(!ctx
->mem_idx
)) {
4283 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4286 t0
= tcg_const_tl(SR(ctx
->opcode
));
4287 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4293 static void gen_mfsrin_64b(DisasContext
*ctx
)
4295 #if defined(CONFIG_USER_ONLY)
4296 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4299 if (unlikely(!ctx
->mem_idx
)) {
4300 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4303 t0
= tcg_temp_new();
4304 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4305 tcg_gen_andi_tl(t0
, t0
, 0xF);
4306 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4312 static void gen_mtsr_64b(DisasContext
*ctx
)
4314 #if defined(CONFIG_USER_ONLY)
4315 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4318 if (unlikely(!ctx
->mem_idx
)) {
4319 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4322 t0
= tcg_const_tl(SR(ctx
->opcode
));
4323 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4329 static void gen_mtsrin_64b(DisasContext
*ctx
)
4331 #if defined(CONFIG_USER_ONLY)
4332 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4335 if (unlikely(!ctx
->mem_idx
)) {
4336 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4339 t0
= tcg_temp_new();
4340 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4341 tcg_gen_andi_tl(t0
, t0
, 0xF);
4342 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4348 static void gen_slbmte(DisasContext
*ctx
)
4350 #if defined(CONFIG_USER_ONLY)
4351 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4353 if (unlikely(!ctx
->mem_idx
)) {
4354 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4357 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4358 cpu_gpr
[rS(ctx
->opcode
)]);
4362 static void gen_slbmfee(DisasContext
*ctx
)
4364 #if defined(CONFIG_USER_ONLY)
4365 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4367 if (unlikely(!ctx
->mem_idx
)) {
4368 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4371 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4372 cpu_gpr
[rB(ctx
->opcode
)]);
4376 static void gen_slbmfev(DisasContext
*ctx
)
4378 #if defined(CONFIG_USER_ONLY)
4379 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4381 if (unlikely(!ctx
->mem_idx
)) {
4382 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4385 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4386 cpu_gpr
[rB(ctx
->opcode
)]);
4389 #endif /* defined(TARGET_PPC64) */
4391 /*** Lookaside buffer management ***/
4392 /* Optional & mem_idx only: */
4395 static void gen_tlbia(DisasContext
*ctx
)
4397 #if defined(CONFIG_USER_ONLY)
4398 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4400 if (unlikely(!ctx
->mem_idx
)) {
4401 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4404 gen_helper_tlbia(cpu_env
);
4409 static void gen_tlbiel(DisasContext
*ctx
)
4411 #if defined(CONFIG_USER_ONLY)
4412 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4414 if (unlikely(!ctx
->mem_idx
)) {
4415 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4418 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4423 static void gen_tlbie(DisasContext
*ctx
)
4425 #if defined(CONFIG_USER_ONLY)
4426 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4428 if (unlikely(!ctx
->mem_idx
)) {
4429 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4432 if (NARROW_MODE(ctx
)) {
4433 TCGv t0
= tcg_temp_new();
4434 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4435 gen_helper_tlbie(cpu_env
, t0
);
4438 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4444 static void gen_tlbsync(DisasContext
*ctx
)
4446 #if defined(CONFIG_USER_ONLY)
4447 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4449 if (unlikely(!ctx
->mem_idx
)) {
4450 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4453 /* This has no effect: it should ensure that all previous
4454 * tlbie have completed
4456 gen_stop_exception(ctx
);
4460 #if defined(TARGET_PPC64)
4462 static void gen_slbia(DisasContext
*ctx
)
4464 #if defined(CONFIG_USER_ONLY)
4465 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4467 if (unlikely(!ctx
->mem_idx
)) {
4468 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4471 gen_helper_slbia(cpu_env
);
4476 static void gen_slbie(DisasContext
*ctx
)
4478 #if defined(CONFIG_USER_ONLY)
4479 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4481 if (unlikely(!ctx
->mem_idx
)) {
4482 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4485 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4490 /*** External control ***/
4494 static void gen_eciwx(DisasContext
*ctx
)
4497 /* Should check EAR[E] ! */
4498 gen_set_access_type(ctx
, ACCESS_EXT
);
4499 t0
= tcg_temp_new();
4500 gen_addr_reg_index(ctx
, t0
);
4501 gen_check_align(ctx
, t0
, 0x03);
4502 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4507 static void gen_ecowx(DisasContext
*ctx
)
4510 /* Should check EAR[E] ! */
4511 gen_set_access_type(ctx
, ACCESS_EXT
);
4512 t0
= tcg_temp_new();
4513 gen_addr_reg_index(ctx
, t0
);
4514 gen_check_align(ctx
, t0
, 0x03);
4515 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4519 /* PowerPC 601 specific instructions */
4522 static void gen_abs(DisasContext
*ctx
)
4524 int l1
= gen_new_label();
4525 int l2
= gen_new_label();
4526 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4527 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4530 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4532 if (unlikely(Rc(ctx
->opcode
) != 0))
4533 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4537 static void gen_abso(DisasContext
*ctx
)
4539 int l1
= gen_new_label();
4540 int l2
= gen_new_label();
4541 int l3
= gen_new_label();
4542 /* Start with XER OV disabled, the most likely case */
4543 tcg_gen_movi_tl(cpu_ov
, 0);
4544 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4545 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4546 tcg_gen_movi_tl(cpu_ov
, 1);
4547 tcg_gen_movi_tl(cpu_so
, 1);
4550 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4553 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4555 if (unlikely(Rc(ctx
->opcode
) != 0))
4556 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4560 static void gen_clcs(DisasContext
*ctx
)
4562 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4563 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4564 tcg_temp_free_i32(t0
);
4565 /* Rc=1 sets CR0 to an undefined state */
4569 static void gen_div(DisasContext
*ctx
)
4571 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4572 cpu_gpr
[rB(ctx
->opcode
)]);
4573 if (unlikely(Rc(ctx
->opcode
) != 0))
4574 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4578 static void gen_divo(DisasContext
*ctx
)
4580 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4581 cpu_gpr
[rB(ctx
->opcode
)]);
4582 if (unlikely(Rc(ctx
->opcode
) != 0))
4583 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4587 static void gen_divs(DisasContext
*ctx
)
4589 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4590 cpu_gpr
[rB(ctx
->opcode
)]);
4591 if (unlikely(Rc(ctx
->opcode
) != 0))
4592 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4595 /* divso - divso. */
4596 static void gen_divso(DisasContext
*ctx
)
4598 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4599 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4600 if (unlikely(Rc(ctx
->opcode
) != 0))
4601 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4605 static void gen_doz(DisasContext
*ctx
)
4607 int l1
= gen_new_label();
4608 int l2
= gen_new_label();
4609 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4610 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4613 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4615 if (unlikely(Rc(ctx
->opcode
) != 0))
4616 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4620 static void gen_dozo(DisasContext
*ctx
)
4622 int l1
= gen_new_label();
4623 int l2
= gen_new_label();
4624 TCGv t0
= tcg_temp_new();
4625 TCGv t1
= tcg_temp_new();
4626 TCGv t2
= tcg_temp_new();
4627 /* Start with XER OV disabled, the most likely case */
4628 tcg_gen_movi_tl(cpu_ov
, 0);
4629 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4630 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4631 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4632 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4633 tcg_gen_andc_tl(t1
, t1
, t2
);
4634 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4635 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4636 tcg_gen_movi_tl(cpu_ov
, 1);
4637 tcg_gen_movi_tl(cpu_so
, 1);
4640 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4645 if (unlikely(Rc(ctx
->opcode
) != 0))
4646 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4650 static void gen_dozi(DisasContext
*ctx
)
4652 target_long simm
= SIMM(ctx
->opcode
);
4653 int l1
= gen_new_label();
4654 int l2
= gen_new_label();
4655 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4656 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4659 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4661 if (unlikely(Rc(ctx
->opcode
) != 0))
4662 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4665 /* lscbx - lscbx. */
4666 static void gen_lscbx(DisasContext
*ctx
)
4668 TCGv t0
= tcg_temp_new();
4669 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4670 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4671 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4673 gen_addr_reg_index(ctx
, t0
);
4674 /* NIP cannot be restored if the memory exception comes from an helper */
4675 gen_update_nip(ctx
, ctx
->nip
- 4);
4676 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4677 tcg_temp_free_i32(t1
);
4678 tcg_temp_free_i32(t2
);
4679 tcg_temp_free_i32(t3
);
4680 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4681 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4682 if (unlikely(Rc(ctx
->opcode
) != 0))
4683 gen_set_Rc0(ctx
, t0
);
4687 /* maskg - maskg. */
4688 static void gen_maskg(DisasContext
*ctx
)
4690 int l1
= gen_new_label();
4691 TCGv t0
= tcg_temp_new();
4692 TCGv t1
= tcg_temp_new();
4693 TCGv t2
= tcg_temp_new();
4694 TCGv t3
= tcg_temp_new();
4695 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4696 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4697 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4698 tcg_gen_addi_tl(t2
, t0
, 1);
4699 tcg_gen_shr_tl(t2
, t3
, t2
);
4700 tcg_gen_shr_tl(t3
, t3
, t1
);
4701 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4702 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4703 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4709 if (unlikely(Rc(ctx
->opcode
) != 0))
4710 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4713 /* maskir - maskir. */
4714 static void gen_maskir(DisasContext
*ctx
)
4716 TCGv t0
= tcg_temp_new();
4717 TCGv t1
= tcg_temp_new();
4718 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4719 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4720 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4723 if (unlikely(Rc(ctx
->opcode
) != 0))
4724 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4728 static void gen_mul(DisasContext
*ctx
)
4730 TCGv_i64 t0
= tcg_temp_new_i64();
4731 TCGv_i64 t1
= tcg_temp_new_i64();
4732 TCGv t2
= tcg_temp_new();
4733 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4734 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4735 tcg_gen_mul_i64(t0
, t0
, t1
);
4736 tcg_gen_trunc_i64_tl(t2
, t0
);
4737 gen_store_spr(SPR_MQ
, t2
);
4738 tcg_gen_shri_i64(t1
, t0
, 32);
4739 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4740 tcg_temp_free_i64(t0
);
4741 tcg_temp_free_i64(t1
);
4743 if (unlikely(Rc(ctx
->opcode
) != 0))
4744 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4748 static void gen_mulo(DisasContext
*ctx
)
4750 int l1
= gen_new_label();
4751 TCGv_i64 t0
= tcg_temp_new_i64();
4752 TCGv_i64 t1
= tcg_temp_new_i64();
4753 TCGv t2
= tcg_temp_new();
4754 /* Start with XER OV disabled, the most likely case */
4755 tcg_gen_movi_tl(cpu_ov
, 0);
4756 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4757 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4758 tcg_gen_mul_i64(t0
, t0
, t1
);
4759 tcg_gen_trunc_i64_tl(t2
, t0
);
4760 gen_store_spr(SPR_MQ
, t2
);
4761 tcg_gen_shri_i64(t1
, t0
, 32);
4762 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4763 tcg_gen_ext32s_i64(t1
, t0
);
4764 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4765 tcg_gen_movi_tl(cpu_ov
, 1);
4766 tcg_gen_movi_tl(cpu_so
, 1);
4768 tcg_temp_free_i64(t0
);
4769 tcg_temp_free_i64(t1
);
4771 if (unlikely(Rc(ctx
->opcode
) != 0))
4772 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4776 static void gen_nabs(DisasContext
*ctx
)
4778 int l1
= gen_new_label();
4779 int l2
= gen_new_label();
4780 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4781 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4784 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4786 if (unlikely(Rc(ctx
->opcode
) != 0))
4787 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4790 /* nabso - nabso. */
4791 static void gen_nabso(DisasContext
*ctx
)
4793 int l1
= gen_new_label();
4794 int l2
= gen_new_label();
4795 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4796 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4799 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4801 /* nabs never overflows */
4802 tcg_gen_movi_tl(cpu_ov
, 0);
4803 if (unlikely(Rc(ctx
->opcode
) != 0))
4804 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4808 static void gen_rlmi(DisasContext
*ctx
)
4810 uint32_t mb
= MB(ctx
->opcode
);
4811 uint32_t me
= ME(ctx
->opcode
);
4812 TCGv t0
= tcg_temp_new();
4813 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4814 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4815 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4816 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4817 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4819 if (unlikely(Rc(ctx
->opcode
) != 0))
4820 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4824 static void gen_rrib(DisasContext
*ctx
)
4826 TCGv t0
= tcg_temp_new();
4827 TCGv t1
= tcg_temp_new();
4828 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4829 tcg_gen_movi_tl(t1
, 0x80000000);
4830 tcg_gen_shr_tl(t1
, t1
, t0
);
4831 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4832 tcg_gen_and_tl(t0
, t0
, t1
);
4833 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4834 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4837 if (unlikely(Rc(ctx
->opcode
) != 0))
4838 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4842 static void gen_sle(DisasContext
*ctx
)
4844 TCGv t0
= tcg_temp_new();
4845 TCGv t1
= tcg_temp_new();
4846 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4847 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4848 tcg_gen_subfi_tl(t1
, 32, t1
);
4849 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4850 tcg_gen_or_tl(t1
, t0
, t1
);
4851 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4852 gen_store_spr(SPR_MQ
, t1
);
4855 if (unlikely(Rc(ctx
->opcode
) != 0))
4856 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4860 static void gen_sleq(DisasContext
*ctx
)
4862 TCGv t0
= tcg_temp_new();
4863 TCGv t1
= tcg_temp_new();
4864 TCGv t2
= tcg_temp_new();
4865 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4866 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4867 tcg_gen_shl_tl(t2
, t2
, t0
);
4868 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4869 gen_load_spr(t1
, SPR_MQ
);
4870 gen_store_spr(SPR_MQ
, t0
);
4871 tcg_gen_and_tl(t0
, t0
, t2
);
4872 tcg_gen_andc_tl(t1
, t1
, t2
);
4873 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4877 if (unlikely(Rc(ctx
->opcode
) != 0))
4878 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4882 static void gen_sliq(DisasContext
*ctx
)
4884 int sh
= SH(ctx
->opcode
);
4885 TCGv t0
= tcg_temp_new();
4886 TCGv t1
= tcg_temp_new();
4887 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4888 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4889 tcg_gen_or_tl(t1
, t0
, t1
);
4890 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4891 gen_store_spr(SPR_MQ
, t1
);
4894 if (unlikely(Rc(ctx
->opcode
) != 0))
4895 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4898 /* slliq - slliq. */
4899 static void gen_slliq(DisasContext
*ctx
)
4901 int sh
= SH(ctx
->opcode
);
4902 TCGv t0
= tcg_temp_new();
4903 TCGv t1
= tcg_temp_new();
4904 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4905 gen_load_spr(t1
, SPR_MQ
);
4906 gen_store_spr(SPR_MQ
, t0
);
4907 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4908 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4909 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4912 if (unlikely(Rc(ctx
->opcode
) != 0))
4913 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4917 static void gen_sllq(DisasContext
*ctx
)
4919 int l1
= gen_new_label();
4920 int l2
= gen_new_label();
4921 TCGv t0
= tcg_temp_local_new();
4922 TCGv t1
= tcg_temp_local_new();
4923 TCGv t2
= tcg_temp_local_new();
4924 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4925 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4926 tcg_gen_shl_tl(t1
, t1
, t2
);
4927 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4928 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4929 gen_load_spr(t0
, SPR_MQ
);
4930 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4933 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4934 gen_load_spr(t2
, SPR_MQ
);
4935 tcg_gen_andc_tl(t1
, t2
, t1
);
4936 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4941 if (unlikely(Rc(ctx
->opcode
) != 0))
4942 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4946 static void gen_slq(DisasContext
*ctx
)
4948 int l1
= gen_new_label();
4949 TCGv t0
= tcg_temp_new();
4950 TCGv t1
= tcg_temp_new();
4951 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4952 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4953 tcg_gen_subfi_tl(t1
, 32, t1
);
4954 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4955 tcg_gen_or_tl(t1
, t0
, t1
);
4956 gen_store_spr(SPR_MQ
, t1
);
4957 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4958 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4959 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4960 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4964 if (unlikely(Rc(ctx
->opcode
) != 0))
4965 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4968 /* sraiq - sraiq. */
4969 static void gen_sraiq(DisasContext
*ctx
)
4971 int sh
= SH(ctx
->opcode
);
4972 int l1
= gen_new_label();
4973 TCGv t0
= tcg_temp_new();
4974 TCGv t1
= tcg_temp_new();
4975 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4976 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4977 tcg_gen_or_tl(t0
, t0
, t1
);
4978 gen_store_spr(SPR_MQ
, t0
);
4979 tcg_gen_movi_tl(cpu_ca
, 0);
4980 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4981 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4982 tcg_gen_movi_tl(cpu_ca
, 1);
4984 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4987 if (unlikely(Rc(ctx
->opcode
) != 0))
4988 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4992 static void gen_sraq(DisasContext
*ctx
)
4994 int l1
= gen_new_label();
4995 int l2
= gen_new_label();
4996 TCGv t0
= tcg_temp_new();
4997 TCGv t1
= tcg_temp_local_new();
4998 TCGv t2
= tcg_temp_local_new();
4999 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5000 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5001 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5002 tcg_gen_subfi_tl(t2
, 32, t2
);
5003 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5004 tcg_gen_or_tl(t0
, t0
, t2
);
5005 gen_store_spr(SPR_MQ
, t0
);
5006 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5007 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5008 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5009 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5012 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5013 tcg_gen_movi_tl(cpu_ca
, 0);
5014 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5015 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5016 tcg_gen_movi_tl(cpu_ca
, 1);
5020 if (unlikely(Rc(ctx
->opcode
) != 0))
5021 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5025 static void gen_sre(DisasContext
*ctx
)
5027 TCGv t0
= tcg_temp_new();
5028 TCGv t1
= tcg_temp_new();
5029 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5030 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5031 tcg_gen_subfi_tl(t1
, 32, t1
);
5032 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5033 tcg_gen_or_tl(t1
, t0
, t1
);
5034 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5035 gen_store_spr(SPR_MQ
, t1
);
5038 if (unlikely(Rc(ctx
->opcode
) != 0))
5039 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5043 static void gen_srea(DisasContext
*ctx
)
5045 TCGv t0
= tcg_temp_new();
5046 TCGv t1
= tcg_temp_new();
5047 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5048 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5049 gen_store_spr(SPR_MQ
, t0
);
5050 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5053 if (unlikely(Rc(ctx
->opcode
) != 0))
5054 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5058 static void gen_sreq(DisasContext
*ctx
)
5060 TCGv t0
= tcg_temp_new();
5061 TCGv t1
= tcg_temp_new();
5062 TCGv t2
= tcg_temp_new();
5063 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5064 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5065 tcg_gen_shr_tl(t1
, t1
, t0
);
5066 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5067 gen_load_spr(t2
, SPR_MQ
);
5068 gen_store_spr(SPR_MQ
, t0
);
5069 tcg_gen_and_tl(t0
, t0
, t1
);
5070 tcg_gen_andc_tl(t2
, t2
, t1
);
5071 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5075 if (unlikely(Rc(ctx
->opcode
) != 0))
5076 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5080 static void gen_sriq(DisasContext
*ctx
)
5082 int sh
= SH(ctx
->opcode
);
5083 TCGv t0
= tcg_temp_new();
5084 TCGv t1
= tcg_temp_new();
5085 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5086 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5087 tcg_gen_or_tl(t1
, t0
, t1
);
5088 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5089 gen_store_spr(SPR_MQ
, t1
);
5092 if (unlikely(Rc(ctx
->opcode
) != 0))
5093 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5097 static void gen_srliq(DisasContext
*ctx
)
5099 int sh
= SH(ctx
->opcode
);
5100 TCGv t0
= tcg_temp_new();
5101 TCGv t1
= tcg_temp_new();
5102 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5103 gen_load_spr(t1
, SPR_MQ
);
5104 gen_store_spr(SPR_MQ
, t0
);
5105 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5106 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5107 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5110 if (unlikely(Rc(ctx
->opcode
) != 0))
5111 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5115 static void gen_srlq(DisasContext
*ctx
)
5117 int l1
= gen_new_label();
5118 int l2
= gen_new_label();
5119 TCGv t0
= tcg_temp_local_new();
5120 TCGv t1
= tcg_temp_local_new();
5121 TCGv t2
= tcg_temp_local_new();
5122 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5123 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5124 tcg_gen_shr_tl(t2
, t1
, t2
);
5125 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5126 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5127 gen_load_spr(t0
, SPR_MQ
);
5128 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5131 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5132 tcg_gen_and_tl(t0
, t0
, t2
);
5133 gen_load_spr(t1
, SPR_MQ
);
5134 tcg_gen_andc_tl(t1
, t1
, t2
);
5135 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5140 if (unlikely(Rc(ctx
->opcode
) != 0))
5141 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5145 static void gen_srq(DisasContext
*ctx
)
5147 int l1
= gen_new_label();
5148 TCGv t0
= tcg_temp_new();
5149 TCGv t1
= tcg_temp_new();
5150 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5151 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5152 tcg_gen_subfi_tl(t1
, 32, t1
);
5153 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5154 tcg_gen_or_tl(t1
, t0
, t1
);
5155 gen_store_spr(SPR_MQ
, t1
);
5156 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5157 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5158 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5159 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5163 if (unlikely(Rc(ctx
->opcode
) != 0))
5164 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5167 /* PowerPC 602 specific instructions */
5170 static void gen_dsa(DisasContext
*ctx
)
5173 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5177 static void gen_esa(DisasContext
*ctx
)
5180 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5184 static void gen_mfrom(DisasContext
*ctx
)
5186 #if defined(CONFIG_USER_ONLY)
5187 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5189 if (unlikely(!ctx
->mem_idx
)) {
5190 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5193 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5197 /* 602 - 603 - G2 TLB management */
5200 static void gen_tlbld_6xx(DisasContext
*ctx
)
5202 #if defined(CONFIG_USER_ONLY)
5203 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5205 if (unlikely(!ctx
->mem_idx
)) {
5206 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5209 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5214 static void gen_tlbli_6xx(DisasContext
*ctx
)
5216 #if defined(CONFIG_USER_ONLY)
5217 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5219 if (unlikely(!ctx
->mem_idx
)) {
5220 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5223 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5227 /* 74xx TLB management */
5230 static void gen_tlbld_74xx(DisasContext
*ctx
)
5232 #if defined(CONFIG_USER_ONLY)
5233 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5235 if (unlikely(!ctx
->mem_idx
)) {
5236 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5239 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5244 static void gen_tlbli_74xx(DisasContext
*ctx
)
5246 #if defined(CONFIG_USER_ONLY)
5247 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5249 if (unlikely(!ctx
->mem_idx
)) {
5250 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5253 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5257 /* POWER instructions not in PowerPC 601 */
5260 static void gen_clf(DisasContext
*ctx
)
5262 /* Cache line flush: implemented as no-op */
5266 static void gen_cli(DisasContext
*ctx
)
5268 /* Cache line invalidate: privileged and treated as no-op */
5269 #if defined(CONFIG_USER_ONLY)
5270 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5272 if (unlikely(!ctx
->mem_idx
)) {
5273 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5280 static void gen_dclst(DisasContext
*ctx
)
5282 /* Data cache line store: treated as no-op */
5285 static void gen_mfsri(DisasContext
*ctx
)
5287 #if defined(CONFIG_USER_ONLY)
5288 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5290 int ra
= rA(ctx
->opcode
);
5291 int rd
= rD(ctx
->opcode
);
5293 if (unlikely(!ctx
->mem_idx
)) {
5294 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5297 t0
= tcg_temp_new();
5298 gen_addr_reg_index(ctx
, t0
);
5299 tcg_gen_shri_tl(t0
, t0
, 28);
5300 tcg_gen_andi_tl(t0
, t0
, 0xF);
5301 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5303 if (ra
!= 0 && ra
!= rd
)
5304 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5308 static void gen_rac(DisasContext
*ctx
)
5310 #if defined(CONFIG_USER_ONLY)
5311 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5314 if (unlikely(!ctx
->mem_idx
)) {
5315 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5318 t0
= tcg_temp_new();
5319 gen_addr_reg_index(ctx
, t0
);
5320 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5325 static void gen_rfsvc(DisasContext
*ctx
)
5327 #if defined(CONFIG_USER_ONLY)
5328 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5330 if (unlikely(!ctx
->mem_idx
)) {
5331 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5334 gen_helper_rfsvc(cpu_env
);
5335 gen_sync_exception(ctx
);
5339 /* svc is not implemented for now */
5341 /* POWER2 specific instructions */
5342 /* Quad manipulation (load/store two floats at a time) */
5345 static void gen_lfq(DisasContext
*ctx
)
5347 int rd
= rD(ctx
->opcode
);
5349 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5350 t0
= tcg_temp_new();
5351 gen_addr_imm_index(ctx
, t0
, 0);
5352 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5353 gen_addr_add(ctx
, t0
, t0
, 8);
5354 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5359 static void gen_lfqu(DisasContext
*ctx
)
5361 int ra
= rA(ctx
->opcode
);
5362 int rd
= rD(ctx
->opcode
);
5364 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5365 t0
= tcg_temp_new();
5366 t1
= tcg_temp_new();
5367 gen_addr_imm_index(ctx
, t0
, 0);
5368 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5369 gen_addr_add(ctx
, t1
, t0
, 8);
5370 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5372 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5378 static void gen_lfqux(DisasContext
*ctx
)
5380 int ra
= rA(ctx
->opcode
);
5381 int rd
= rD(ctx
->opcode
);
5382 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5384 t0
= tcg_temp_new();
5385 gen_addr_reg_index(ctx
, t0
);
5386 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5387 t1
= tcg_temp_new();
5388 gen_addr_add(ctx
, t1
, t0
, 8);
5389 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5392 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5397 static void gen_lfqx(DisasContext
*ctx
)
5399 int rd
= rD(ctx
->opcode
);
5401 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5402 t0
= tcg_temp_new();
5403 gen_addr_reg_index(ctx
, t0
);
5404 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5405 gen_addr_add(ctx
, t0
, t0
, 8);
5406 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5411 static void gen_stfq(DisasContext
*ctx
)
5413 int rd
= rD(ctx
->opcode
);
5415 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5416 t0
= tcg_temp_new();
5417 gen_addr_imm_index(ctx
, t0
, 0);
5418 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5419 gen_addr_add(ctx
, t0
, t0
, 8);
5420 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5425 static void gen_stfqu(DisasContext
*ctx
)
5427 int ra
= rA(ctx
->opcode
);
5428 int rd
= rD(ctx
->opcode
);
5430 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5431 t0
= tcg_temp_new();
5432 gen_addr_imm_index(ctx
, t0
, 0);
5433 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5434 t1
= tcg_temp_new();
5435 gen_addr_add(ctx
, t1
, t0
, 8);
5436 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5439 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5444 static void gen_stfqux(DisasContext
*ctx
)
5446 int ra
= rA(ctx
->opcode
);
5447 int rd
= rD(ctx
->opcode
);
5449 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5450 t0
= tcg_temp_new();
5451 gen_addr_reg_index(ctx
, t0
);
5452 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5453 t1
= tcg_temp_new();
5454 gen_addr_add(ctx
, t1
, t0
, 8);
5455 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5458 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5463 static void gen_stfqx(DisasContext
*ctx
)
5465 int rd
= rD(ctx
->opcode
);
5467 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5468 t0
= tcg_temp_new();
5469 gen_addr_reg_index(ctx
, t0
);
5470 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5471 gen_addr_add(ctx
, t0
, t0
, 8);
5472 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5476 /* BookE specific instructions */
5478 /* XXX: not implemented on 440 ? */
5479 static void gen_mfapidi(DisasContext
*ctx
)
5482 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5485 /* XXX: not implemented on 440 ? */
5486 static void gen_tlbiva(DisasContext
*ctx
)
5488 #if defined(CONFIG_USER_ONLY)
5489 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5492 if (unlikely(!ctx
->mem_idx
)) {
5493 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5496 t0
= tcg_temp_new();
5497 gen_addr_reg_index(ctx
, t0
);
5498 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5503 /* All 405 MAC instructions are translated here */
5504 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5505 int ra
, int rb
, int rt
, int Rc
)
5509 t0
= tcg_temp_local_new();
5510 t1
= tcg_temp_local_new();
5512 switch (opc3
& 0x0D) {
5514 /* macchw - macchw. - macchwo - macchwo. */
5515 /* macchws - macchws. - macchwso - macchwso. */
5516 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5517 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5518 /* mulchw - mulchw. */
5519 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5520 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5521 tcg_gen_ext16s_tl(t1
, t1
);
5524 /* macchwu - macchwu. - macchwuo - macchwuo. */
5525 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5526 /* mulchwu - mulchwu. */
5527 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5528 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5529 tcg_gen_ext16u_tl(t1
, t1
);
5532 /* machhw - machhw. - machhwo - machhwo. */
5533 /* machhws - machhws. - machhwso - machhwso. */
5534 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5535 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5536 /* mulhhw - mulhhw. */
5537 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5538 tcg_gen_ext16s_tl(t0
, t0
);
5539 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5540 tcg_gen_ext16s_tl(t1
, t1
);
5543 /* machhwu - machhwu. - machhwuo - machhwuo. */
5544 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5545 /* mulhhwu - mulhhwu. */
5546 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5547 tcg_gen_ext16u_tl(t0
, t0
);
5548 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5549 tcg_gen_ext16u_tl(t1
, t1
);
5552 /* maclhw - maclhw. - maclhwo - maclhwo. */
5553 /* maclhws - maclhws. - maclhwso - maclhwso. */
5554 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5555 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5556 /* mullhw - mullhw. */
5557 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5558 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5561 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5562 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5563 /* mullhwu - mullhwu. */
5564 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5565 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5569 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5570 tcg_gen_mul_tl(t1
, t0
, t1
);
5572 /* nmultiply-and-accumulate (0x0E) */
5573 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5575 /* multiply-and-accumulate (0x0C) */
5576 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5580 /* Check overflow and/or saturate */
5581 int l1
= gen_new_label();
5584 /* Start with XER OV disabled, the most likely case */
5585 tcg_gen_movi_tl(cpu_ov
, 0);
5589 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5590 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5591 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5592 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5595 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5596 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5600 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5603 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5607 /* Check overflow */
5608 tcg_gen_movi_tl(cpu_ov
, 1);
5609 tcg_gen_movi_tl(cpu_so
, 1);
5612 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5615 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5619 if (unlikely(Rc
) != 0) {
5621 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5625 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5626 static void glue(gen_, name)(DisasContext *ctx) \
5628 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5629 rD(ctx->opcode), Rc(ctx->opcode)); \
5632 /* macchw - macchw. */
5633 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5634 /* macchwo - macchwo. */
5635 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5636 /* macchws - macchws. */
5637 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5638 /* macchwso - macchwso. */
5639 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5640 /* macchwsu - macchwsu. */
5641 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5642 /* macchwsuo - macchwsuo. */
5643 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5644 /* macchwu - macchwu. */
5645 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5646 /* macchwuo - macchwuo. */
5647 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5648 /* machhw - machhw. */
5649 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5650 /* machhwo - machhwo. */
5651 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5652 /* machhws - machhws. */
5653 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5654 /* machhwso - machhwso. */
5655 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5656 /* machhwsu - machhwsu. */
5657 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5658 /* machhwsuo - machhwsuo. */
5659 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5660 /* machhwu - machhwu. */
5661 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5662 /* machhwuo - machhwuo. */
5663 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5664 /* maclhw - maclhw. */
5665 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5666 /* maclhwo - maclhwo. */
5667 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5668 /* maclhws - maclhws. */
5669 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5670 /* maclhwso - maclhwso. */
5671 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5672 /* maclhwu - maclhwu. */
5673 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5674 /* maclhwuo - maclhwuo. */
5675 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5676 /* maclhwsu - maclhwsu. */
5677 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5678 /* maclhwsuo - maclhwsuo. */
5679 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5680 /* nmacchw - nmacchw. */
5681 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5682 /* nmacchwo - nmacchwo. */
5683 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5684 /* nmacchws - nmacchws. */
5685 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5686 /* nmacchwso - nmacchwso. */
5687 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5688 /* nmachhw - nmachhw. */
5689 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5690 /* nmachhwo - nmachhwo. */
5691 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5692 /* nmachhws - nmachhws. */
5693 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5694 /* nmachhwso - nmachhwso. */
5695 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5696 /* nmaclhw - nmaclhw. */
5697 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5698 /* nmaclhwo - nmaclhwo. */
5699 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5700 /* nmaclhws - nmaclhws. */
5701 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5702 /* nmaclhwso - nmaclhwso. */
5703 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5705 /* mulchw - mulchw. */
5706 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5707 /* mulchwu - mulchwu. */
5708 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5709 /* mulhhw - mulhhw. */
5710 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5711 /* mulhhwu - mulhhwu. */
5712 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5713 /* mullhw - mullhw. */
5714 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5715 /* mullhwu - mullhwu. */
5716 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5719 static void gen_mfdcr(DisasContext
*ctx
)
5721 #if defined(CONFIG_USER_ONLY)
5722 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5725 if (unlikely(!ctx
->mem_idx
)) {
5726 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5729 /* NIP cannot be restored if the memory exception comes from an helper */
5730 gen_update_nip(ctx
, ctx
->nip
- 4);
5731 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5732 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5733 tcg_temp_free(dcrn
);
5738 static void gen_mtdcr(DisasContext
*ctx
)
5740 #if defined(CONFIG_USER_ONLY)
5741 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5744 if (unlikely(!ctx
->mem_idx
)) {
5745 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5748 /* NIP cannot be restored if the memory exception comes from an helper */
5749 gen_update_nip(ctx
, ctx
->nip
- 4);
5750 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5751 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5752 tcg_temp_free(dcrn
);
5757 /* XXX: not implemented on 440 ? */
5758 static void gen_mfdcrx(DisasContext
*ctx
)
5760 #if defined(CONFIG_USER_ONLY)
5761 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5763 if (unlikely(!ctx
->mem_idx
)) {
5764 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5767 /* NIP cannot be restored if the memory exception comes from an helper */
5768 gen_update_nip(ctx
, ctx
->nip
- 4);
5769 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5770 cpu_gpr
[rA(ctx
->opcode
)]);
5771 /* Note: Rc update flag set leads to undefined state of Rc0 */
5776 /* XXX: not implemented on 440 ? */
5777 static void gen_mtdcrx(DisasContext
*ctx
)
5779 #if defined(CONFIG_USER_ONLY)
5780 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5782 if (unlikely(!ctx
->mem_idx
)) {
5783 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5786 /* NIP cannot be restored if the memory exception comes from an helper */
5787 gen_update_nip(ctx
, ctx
->nip
- 4);
5788 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5789 cpu_gpr
[rS(ctx
->opcode
)]);
5790 /* Note: Rc update flag set leads to undefined state of Rc0 */
5794 /* mfdcrux (PPC 460) : user-mode access to DCR */
5795 static void gen_mfdcrux(DisasContext
*ctx
)
5797 /* NIP cannot be restored if the memory exception comes from an helper */
5798 gen_update_nip(ctx
, ctx
->nip
- 4);
5799 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5800 cpu_gpr
[rA(ctx
->opcode
)]);
5801 /* Note: Rc update flag set leads to undefined state of Rc0 */
5804 /* mtdcrux (PPC 460) : user-mode access to DCR */
5805 static void gen_mtdcrux(DisasContext
*ctx
)
5807 /* NIP cannot be restored if the memory exception comes from an helper */
5808 gen_update_nip(ctx
, ctx
->nip
- 4);
5809 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5810 cpu_gpr
[rS(ctx
->opcode
)]);
5811 /* Note: Rc update flag set leads to undefined state of Rc0 */
5815 static void gen_dccci(DisasContext
*ctx
)
5817 #if defined(CONFIG_USER_ONLY)
5818 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5820 if (unlikely(!ctx
->mem_idx
)) {
5821 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5824 /* interpreted as no-op */
5829 static void gen_dcread(DisasContext
*ctx
)
5831 #if defined(CONFIG_USER_ONLY)
5832 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5835 if (unlikely(!ctx
->mem_idx
)) {
5836 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5839 gen_set_access_type(ctx
, ACCESS_CACHE
);
5840 EA
= tcg_temp_new();
5841 gen_addr_reg_index(ctx
, EA
);
5842 val
= tcg_temp_new();
5843 gen_qemu_ld32u(ctx
, val
, EA
);
5845 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5851 static void gen_icbt_40x(DisasContext
*ctx
)
5853 /* interpreted as no-op */
5854 /* XXX: specification say this is treated as a load by the MMU
5855 * but does not generate any exception
5860 static void gen_iccci(DisasContext
*ctx
)
5862 #if defined(CONFIG_USER_ONLY)
5863 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5865 if (unlikely(!ctx
->mem_idx
)) {
5866 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5869 /* interpreted as no-op */
5874 static void gen_icread(DisasContext
*ctx
)
5876 #if defined(CONFIG_USER_ONLY)
5877 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5879 if (unlikely(!ctx
->mem_idx
)) {
5880 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5883 /* interpreted as no-op */
5887 /* rfci (mem_idx only) */
5888 static void gen_rfci_40x(DisasContext
*ctx
)
5890 #if defined(CONFIG_USER_ONLY)
5891 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5893 if (unlikely(!ctx
->mem_idx
)) {
5894 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5897 /* Restore CPU state */
5898 gen_helper_40x_rfci(cpu_env
);
5899 gen_sync_exception(ctx
);
5903 static void gen_rfci(DisasContext
*ctx
)
5905 #if defined(CONFIG_USER_ONLY)
5906 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5908 if (unlikely(!ctx
->mem_idx
)) {
5909 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5912 /* Restore CPU state */
5913 gen_helper_rfci(cpu_env
);
5914 gen_sync_exception(ctx
);
5918 /* BookE specific */
5920 /* XXX: not implemented on 440 ? */
5921 static void gen_rfdi(DisasContext
*ctx
)
5923 #if defined(CONFIG_USER_ONLY)
5924 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5926 if (unlikely(!ctx
->mem_idx
)) {
5927 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5930 /* Restore CPU state */
5931 gen_helper_rfdi(cpu_env
);
5932 gen_sync_exception(ctx
);
5936 /* XXX: not implemented on 440 ? */
5937 static void gen_rfmci(DisasContext
*ctx
)
5939 #if defined(CONFIG_USER_ONLY)
5940 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5942 if (unlikely(!ctx
->mem_idx
)) {
5943 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5946 /* Restore CPU state */
5947 gen_helper_rfmci(cpu_env
);
5948 gen_sync_exception(ctx
);
5952 /* TLB management - PowerPC 405 implementation */
5955 static void gen_tlbre_40x(DisasContext
*ctx
)
5957 #if defined(CONFIG_USER_ONLY)
5958 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5960 if (unlikely(!ctx
->mem_idx
)) {
5961 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5964 switch (rB(ctx
->opcode
)) {
5966 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5967 cpu_gpr
[rA(ctx
->opcode
)]);
5970 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5971 cpu_gpr
[rA(ctx
->opcode
)]);
5974 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5980 /* tlbsx - tlbsx. */
5981 static void gen_tlbsx_40x(DisasContext
*ctx
)
5983 #if defined(CONFIG_USER_ONLY)
5984 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5987 if (unlikely(!ctx
->mem_idx
)) {
5988 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5991 t0
= tcg_temp_new();
5992 gen_addr_reg_index(ctx
, t0
);
5993 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5995 if (Rc(ctx
->opcode
)) {
5996 int l1
= gen_new_label();
5997 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5998 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5999 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6006 static void gen_tlbwe_40x(DisasContext
*ctx
)
6008 #if defined(CONFIG_USER_ONLY)
6009 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6011 if (unlikely(!ctx
->mem_idx
)) {
6012 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6015 switch (rB(ctx
->opcode
)) {
6017 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6018 cpu_gpr
[rS(ctx
->opcode
)]);
6021 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6022 cpu_gpr
[rS(ctx
->opcode
)]);
6025 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6031 /* TLB management - PowerPC 440 implementation */
6034 static void gen_tlbre_440(DisasContext
*ctx
)
6036 #if defined(CONFIG_USER_ONLY)
6037 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6039 if (unlikely(!ctx
->mem_idx
)) {
6040 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6043 switch (rB(ctx
->opcode
)) {
6048 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6049 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6050 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6051 tcg_temp_free_i32(t0
);
6055 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6061 /* tlbsx - tlbsx. */
6062 static void gen_tlbsx_440(DisasContext
*ctx
)
6064 #if defined(CONFIG_USER_ONLY)
6065 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6068 if (unlikely(!ctx
->mem_idx
)) {
6069 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6072 t0
= tcg_temp_new();
6073 gen_addr_reg_index(ctx
, t0
);
6074 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6076 if (Rc(ctx
->opcode
)) {
6077 int l1
= gen_new_label();
6078 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6079 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6080 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6087 static void gen_tlbwe_440(DisasContext
*ctx
)
6089 #if defined(CONFIG_USER_ONLY)
6090 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6092 if (unlikely(!ctx
->mem_idx
)) {
6093 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6096 switch (rB(ctx
->opcode
)) {
6101 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6102 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6103 cpu_gpr
[rS(ctx
->opcode
)]);
6104 tcg_temp_free_i32(t0
);
6108 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6114 /* TLB management - PowerPC BookE 2.06 implementation */
6117 static void gen_tlbre_booke206(DisasContext
*ctx
)
6119 #if defined(CONFIG_USER_ONLY)
6120 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6122 if (unlikely(!ctx
->mem_idx
)) {
6123 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6127 gen_helper_booke206_tlbre(cpu_env
);
6131 /* tlbsx - tlbsx. */
6132 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6134 #if defined(CONFIG_USER_ONLY)
6135 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6138 if (unlikely(!ctx
->mem_idx
)) {
6139 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6143 if (rA(ctx
->opcode
)) {
6144 t0
= tcg_temp_new();
6145 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6147 t0
= tcg_const_tl(0);
6150 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6151 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6156 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6158 #if defined(CONFIG_USER_ONLY)
6159 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6161 if (unlikely(!ctx
->mem_idx
)) {
6162 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6165 gen_update_nip(ctx
, ctx
->nip
- 4);
6166 gen_helper_booke206_tlbwe(cpu_env
);
6170 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6172 #if defined(CONFIG_USER_ONLY)
6173 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6176 if (unlikely(!ctx
->mem_idx
)) {
6177 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6181 t0
= tcg_temp_new();
6182 gen_addr_reg_index(ctx
, t0
);
6184 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6188 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6190 #if defined(CONFIG_USER_ONLY)
6191 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6194 if (unlikely(!ctx
->mem_idx
)) {
6195 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6199 t0
= tcg_temp_new();
6200 gen_addr_reg_index(ctx
, t0
);
6202 switch((ctx
->opcode
>> 21) & 0x3) {
6204 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6207 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6210 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6213 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6223 static void gen_wrtee(DisasContext
*ctx
)
6225 #if defined(CONFIG_USER_ONLY)
6226 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6229 if (unlikely(!ctx
->mem_idx
)) {
6230 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6233 t0
= tcg_temp_new();
6234 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6235 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6236 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6238 /* Stop translation to have a chance to raise an exception
6239 * if we just set msr_ee to 1
6241 gen_stop_exception(ctx
);
6246 static void gen_wrteei(DisasContext
*ctx
)
6248 #if defined(CONFIG_USER_ONLY)
6249 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6251 if (unlikely(!ctx
->mem_idx
)) {
6252 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6255 if (ctx
->opcode
& 0x00008000) {
6256 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6257 /* Stop translation to have a chance to raise an exception */
6258 gen_stop_exception(ctx
);
6260 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6265 /* PowerPC 440 specific instructions */
6268 static void gen_dlmzb(DisasContext
*ctx
)
6270 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6271 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6272 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6273 tcg_temp_free_i32(t0
);
6276 /* mbar replaces eieio on 440 */
6277 static void gen_mbar(DisasContext
*ctx
)
6279 /* interpreted as no-op */
6282 /* msync replaces sync on 440 */
6283 static void gen_msync_4xx(DisasContext
*ctx
)
6285 /* interpreted as no-op */
6289 static void gen_icbt_440(DisasContext
*ctx
)
6291 /* interpreted as no-op */
6292 /* XXX: specification say this is treated as a load by the MMU
6293 * but does not generate any exception
6297 /* Embedded.Processor Control */
6299 static void gen_msgclr(DisasContext
*ctx
)
6301 #if defined(CONFIG_USER_ONLY)
6302 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6304 if (unlikely(ctx
->mem_idx
== 0)) {
6305 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6309 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6313 static void gen_msgsnd(DisasContext
*ctx
)
6315 #if defined(CONFIG_USER_ONLY)
6316 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6318 if (unlikely(ctx
->mem_idx
== 0)) {
6319 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6323 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6327 /*** Altivec vector extension ***/
6328 /* Altivec registers moves */
6330 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6332 TCGv_ptr r
= tcg_temp_new_ptr();
6333 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6337 #define GEN_VR_LDX(name, opc2, opc3) \
6338 static void glue(gen_, name)(DisasContext *ctx) \
6341 if (unlikely(!ctx->altivec_enabled)) { \
6342 gen_exception(ctx, POWERPC_EXCP_VPU); \
6345 gen_set_access_type(ctx, ACCESS_INT); \
6346 EA = tcg_temp_new(); \
6347 gen_addr_reg_index(ctx, EA); \
6348 tcg_gen_andi_tl(EA, EA, ~0xf); \
6349 if (ctx->le_mode) { \
6350 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6351 tcg_gen_addi_tl(EA, EA, 8); \
6352 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6354 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6355 tcg_gen_addi_tl(EA, EA, 8); \
6356 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6358 tcg_temp_free(EA); \
6361 #define GEN_VR_STX(name, opc2, opc3) \
6362 static void gen_st##name(DisasContext *ctx) \
6365 if (unlikely(!ctx->altivec_enabled)) { \
6366 gen_exception(ctx, POWERPC_EXCP_VPU); \
6369 gen_set_access_type(ctx, ACCESS_INT); \
6370 EA = tcg_temp_new(); \
6371 gen_addr_reg_index(ctx, EA); \
6372 tcg_gen_andi_tl(EA, EA, ~0xf); \
6373 if (ctx->le_mode) { \
6374 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6375 tcg_gen_addi_tl(EA, EA, 8); \
6376 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6378 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6379 tcg_gen_addi_tl(EA, EA, 8); \
6380 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6382 tcg_temp_free(EA); \
6385 #define GEN_VR_LVE(name, opc2, opc3) \
6386 static void gen_lve##name(DisasContext *ctx) \
6390 if (unlikely(!ctx->altivec_enabled)) { \
6391 gen_exception(ctx, POWERPC_EXCP_VPU); \
6394 gen_set_access_type(ctx, ACCESS_INT); \
6395 EA = tcg_temp_new(); \
6396 gen_addr_reg_index(ctx, EA); \
6397 rs = gen_avr_ptr(rS(ctx->opcode)); \
6398 gen_helper_lve##name(cpu_env, rs, EA); \
6399 tcg_temp_free(EA); \
6400 tcg_temp_free_ptr(rs); \
6403 #define GEN_VR_STVE(name, opc2, opc3) \
6404 static void gen_stve##name(DisasContext *ctx) \
6408 if (unlikely(!ctx->altivec_enabled)) { \
6409 gen_exception(ctx, POWERPC_EXCP_VPU); \
6412 gen_set_access_type(ctx, ACCESS_INT); \
6413 EA = tcg_temp_new(); \
6414 gen_addr_reg_index(ctx, EA); \
6415 rs = gen_avr_ptr(rS(ctx->opcode)); \
6416 gen_helper_stve##name(cpu_env, rs, EA); \
6417 tcg_temp_free(EA); \
6418 tcg_temp_free_ptr(rs); \
6421 GEN_VR_LDX(lvx
, 0x07, 0x03);
6422 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6423 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6425 GEN_VR_LVE(bx
, 0x07, 0x00);
6426 GEN_VR_LVE(hx
, 0x07, 0x01);
6427 GEN_VR_LVE(wx
, 0x07, 0x02);
6429 GEN_VR_STX(svx
, 0x07, 0x07);
6430 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6431 GEN_VR_STX(svxl
, 0x07, 0x0F);
6433 GEN_VR_STVE(bx
, 0x07, 0x04);
6434 GEN_VR_STVE(hx
, 0x07, 0x05);
6435 GEN_VR_STVE(wx
, 0x07, 0x06);
6437 static void gen_lvsl(DisasContext
*ctx
)
6441 if (unlikely(!ctx
->altivec_enabled
)) {
6442 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6445 EA
= tcg_temp_new();
6446 gen_addr_reg_index(ctx
, EA
);
6447 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6448 gen_helper_lvsl(rd
, EA
);
6450 tcg_temp_free_ptr(rd
);
6453 static void gen_lvsr(DisasContext
*ctx
)
6457 if (unlikely(!ctx
->altivec_enabled
)) {
6458 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6461 EA
= tcg_temp_new();
6462 gen_addr_reg_index(ctx
, EA
);
6463 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6464 gen_helper_lvsr(rd
, EA
);
6466 tcg_temp_free_ptr(rd
);
6469 static void gen_mfvscr(DisasContext
*ctx
)
6472 if (unlikely(!ctx
->altivec_enabled
)) {
6473 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6476 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6477 t
= tcg_temp_new_i32();
6478 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6479 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6480 tcg_temp_free_i32(t
);
6483 static void gen_mtvscr(DisasContext
*ctx
)
6486 if (unlikely(!ctx
->altivec_enabled
)) {
6487 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6490 p
= gen_avr_ptr(rD(ctx
->opcode
));
6491 gen_helper_mtvscr(cpu_env
, p
);
6492 tcg_temp_free_ptr(p
);
6495 /* Logical operations */
6496 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6497 static void glue(gen_, name)(DisasContext *ctx) \
6499 if (unlikely(!ctx->altivec_enabled)) { \
6500 gen_exception(ctx, POWERPC_EXCP_VPU); \
6503 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6504 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6507 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6508 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6509 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6510 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6511 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6513 #define GEN_VXFORM(name, opc2, opc3) \
6514 static void glue(gen_, name)(DisasContext *ctx) \
6516 TCGv_ptr ra, rb, rd; \
6517 if (unlikely(!ctx->altivec_enabled)) { \
6518 gen_exception(ctx, POWERPC_EXCP_VPU); \
6521 ra = gen_avr_ptr(rA(ctx->opcode)); \
6522 rb = gen_avr_ptr(rB(ctx->opcode)); \
6523 rd = gen_avr_ptr(rD(ctx->opcode)); \
6524 gen_helper_##name (rd, ra, rb); \
6525 tcg_temp_free_ptr(ra); \
6526 tcg_temp_free_ptr(rb); \
6527 tcg_temp_free_ptr(rd); \
6530 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6531 static void glue(gen_, name)(DisasContext *ctx) \
6533 TCGv_ptr ra, rb, rd; \
6534 if (unlikely(!ctx->altivec_enabled)) { \
6535 gen_exception(ctx, POWERPC_EXCP_VPU); \
6538 ra = gen_avr_ptr(rA(ctx->opcode)); \
6539 rb = gen_avr_ptr(rB(ctx->opcode)); \
6540 rd = gen_avr_ptr(rD(ctx->opcode)); \
6541 gen_helper_##name(cpu_env, rd, ra, rb); \
6542 tcg_temp_free_ptr(ra); \
6543 tcg_temp_free_ptr(rb); \
6544 tcg_temp_free_ptr(rd); \
6547 GEN_VXFORM(vaddubm
, 0, 0);
6548 GEN_VXFORM(vadduhm
, 0, 1);
6549 GEN_VXFORM(vadduwm
, 0, 2);
6550 GEN_VXFORM(vsububm
, 0, 16);
6551 GEN_VXFORM(vsubuhm
, 0, 17);
6552 GEN_VXFORM(vsubuwm
, 0, 18);
6553 GEN_VXFORM(vmaxub
, 1, 0);
6554 GEN_VXFORM(vmaxuh
, 1, 1);
6555 GEN_VXFORM(vmaxuw
, 1, 2);
6556 GEN_VXFORM(vmaxsb
, 1, 4);
6557 GEN_VXFORM(vmaxsh
, 1, 5);
6558 GEN_VXFORM(vmaxsw
, 1, 6);
6559 GEN_VXFORM(vminub
, 1, 8);
6560 GEN_VXFORM(vminuh
, 1, 9);
6561 GEN_VXFORM(vminuw
, 1, 10);
6562 GEN_VXFORM(vminsb
, 1, 12);
6563 GEN_VXFORM(vminsh
, 1, 13);
6564 GEN_VXFORM(vminsw
, 1, 14);
6565 GEN_VXFORM(vavgub
, 1, 16);
6566 GEN_VXFORM(vavguh
, 1, 17);
6567 GEN_VXFORM(vavguw
, 1, 18);
6568 GEN_VXFORM(vavgsb
, 1, 20);
6569 GEN_VXFORM(vavgsh
, 1, 21);
6570 GEN_VXFORM(vavgsw
, 1, 22);
6571 GEN_VXFORM(vmrghb
, 6, 0);
6572 GEN_VXFORM(vmrghh
, 6, 1);
6573 GEN_VXFORM(vmrghw
, 6, 2);
6574 GEN_VXFORM(vmrglb
, 6, 4);
6575 GEN_VXFORM(vmrglh
, 6, 5);
6576 GEN_VXFORM(vmrglw
, 6, 6);
6577 GEN_VXFORM(vmuloub
, 4, 0);
6578 GEN_VXFORM(vmulouh
, 4, 1);
6579 GEN_VXFORM(vmulosb
, 4, 4);
6580 GEN_VXFORM(vmulosh
, 4, 5);
6581 GEN_VXFORM(vmuleub
, 4, 8);
6582 GEN_VXFORM(vmuleuh
, 4, 9);
6583 GEN_VXFORM(vmulesb
, 4, 12);
6584 GEN_VXFORM(vmulesh
, 4, 13);
6585 GEN_VXFORM(vslb
, 2, 4);
6586 GEN_VXFORM(vslh
, 2, 5);
6587 GEN_VXFORM(vslw
, 2, 6);
6588 GEN_VXFORM(vsrb
, 2, 8);
6589 GEN_VXFORM(vsrh
, 2, 9);
6590 GEN_VXFORM(vsrw
, 2, 10);
6591 GEN_VXFORM(vsrab
, 2, 12);
6592 GEN_VXFORM(vsrah
, 2, 13);
6593 GEN_VXFORM(vsraw
, 2, 14);
6594 GEN_VXFORM(vslo
, 6, 16);
6595 GEN_VXFORM(vsro
, 6, 17);
6596 GEN_VXFORM(vaddcuw
, 0, 6);
6597 GEN_VXFORM(vsubcuw
, 0, 22);
6598 GEN_VXFORM_ENV(vaddubs
, 0, 8);
6599 GEN_VXFORM_ENV(vadduhs
, 0, 9);
6600 GEN_VXFORM_ENV(vadduws
, 0, 10);
6601 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
6602 GEN_VXFORM_ENV(vaddshs
, 0, 13);
6603 GEN_VXFORM_ENV(vaddsws
, 0, 14);
6604 GEN_VXFORM_ENV(vsububs
, 0, 24);
6605 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
6606 GEN_VXFORM_ENV(vsubuws
, 0, 26);
6607 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
6608 GEN_VXFORM_ENV(vsubshs
, 0, 29);
6609 GEN_VXFORM_ENV(vsubsws
, 0, 30);
6610 GEN_VXFORM(vrlb
, 2, 0);
6611 GEN_VXFORM(vrlh
, 2, 1);
6612 GEN_VXFORM(vrlw
, 2, 2);
6613 GEN_VXFORM(vsl
, 2, 7);
6614 GEN_VXFORM(vsr
, 2, 11);
6615 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
6616 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
6617 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
6618 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
6619 GEN_VXFORM_ENV(vpkshus
, 7, 4);
6620 GEN_VXFORM_ENV(vpkswus
, 7, 5);
6621 GEN_VXFORM_ENV(vpkshss
, 7, 6);
6622 GEN_VXFORM_ENV(vpkswss
, 7, 7);
6623 GEN_VXFORM(vpkpx
, 7, 12);
6624 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
6625 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
6626 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
6627 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
6628 GEN_VXFORM_ENV(vsumsws
, 4, 30);
6629 GEN_VXFORM_ENV(vaddfp
, 5, 0);
6630 GEN_VXFORM_ENV(vsubfp
, 5, 1);
6631 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
6632 GEN_VXFORM_ENV(vminfp
, 5, 17);
6634 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6635 static void glue(gen_, name)(DisasContext *ctx) \
6637 TCGv_ptr ra, rb, rd; \
6638 if (unlikely(!ctx->altivec_enabled)) { \
6639 gen_exception(ctx, POWERPC_EXCP_VPU); \
6642 ra = gen_avr_ptr(rA(ctx->opcode)); \
6643 rb = gen_avr_ptr(rB(ctx->opcode)); \
6644 rd = gen_avr_ptr(rD(ctx->opcode)); \
6645 gen_helper_##opname(cpu_env, rd, ra, rb); \
6646 tcg_temp_free_ptr(ra); \
6647 tcg_temp_free_ptr(rb); \
6648 tcg_temp_free_ptr(rd); \
6651 #define GEN_VXRFORM(name, opc2, opc3) \
6652 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6653 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6655 GEN_VXRFORM(vcmpequb
, 3, 0)
6656 GEN_VXRFORM(vcmpequh
, 3, 1)
6657 GEN_VXRFORM(vcmpequw
, 3, 2)
6658 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6659 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6660 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6661 GEN_VXRFORM(vcmpgtub
, 3, 8)
6662 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6663 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6664 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6665 GEN_VXRFORM(vcmpgefp
, 3, 7)
6666 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6667 GEN_VXRFORM(vcmpbfp
, 3, 15)
6669 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6670 static void glue(gen_, name)(DisasContext *ctx) \
6674 if (unlikely(!ctx->altivec_enabled)) { \
6675 gen_exception(ctx, POWERPC_EXCP_VPU); \
6678 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6679 rd = gen_avr_ptr(rD(ctx->opcode)); \
6680 gen_helper_##name (rd, simm); \
6681 tcg_temp_free_i32(simm); \
6682 tcg_temp_free_ptr(rd); \
6685 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6686 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6687 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6689 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6690 static void glue(gen_, name)(DisasContext *ctx) \
6693 if (unlikely(!ctx->altivec_enabled)) { \
6694 gen_exception(ctx, POWERPC_EXCP_VPU); \
6697 rb = gen_avr_ptr(rB(ctx->opcode)); \
6698 rd = gen_avr_ptr(rD(ctx->opcode)); \
6699 gen_helper_##name (rd, rb); \
6700 tcg_temp_free_ptr(rb); \
6701 tcg_temp_free_ptr(rd); \
6704 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6705 static void glue(gen_, name)(DisasContext *ctx) \
6709 if (unlikely(!ctx->altivec_enabled)) { \
6710 gen_exception(ctx, POWERPC_EXCP_VPU); \
6713 rb = gen_avr_ptr(rB(ctx->opcode)); \
6714 rd = gen_avr_ptr(rD(ctx->opcode)); \
6715 gen_helper_##name(cpu_env, rd, rb); \
6716 tcg_temp_free_ptr(rb); \
6717 tcg_temp_free_ptr(rd); \
6720 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6721 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6722 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6723 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6724 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6725 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6726 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
6727 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
6728 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
6729 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
6730 GEN_VXFORM_NOA_ENV(vrfim
, 5, 8);
6731 GEN_VXFORM_NOA_ENV(vrfin
, 5, 9);
6732 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
6733 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 11);
6735 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6736 static void glue(gen_, name)(DisasContext *ctx) \
6740 if (unlikely(!ctx->altivec_enabled)) { \
6741 gen_exception(ctx, POWERPC_EXCP_VPU); \
6744 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6745 rd = gen_avr_ptr(rD(ctx->opcode)); \
6746 gen_helper_##name (rd, simm); \
6747 tcg_temp_free_i32(simm); \
6748 tcg_temp_free_ptr(rd); \
6751 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6752 static void glue(gen_, name)(DisasContext *ctx) \
6756 if (unlikely(!ctx->altivec_enabled)) { \
6757 gen_exception(ctx, POWERPC_EXCP_VPU); \
6760 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6761 rb = gen_avr_ptr(rB(ctx->opcode)); \
6762 rd = gen_avr_ptr(rD(ctx->opcode)); \
6763 gen_helper_##name (rd, rb, uimm); \
6764 tcg_temp_free_i32(uimm); \
6765 tcg_temp_free_ptr(rb); \
6766 tcg_temp_free_ptr(rd); \
6769 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6770 static void glue(gen_, name)(DisasContext *ctx) \
6775 if (unlikely(!ctx->altivec_enabled)) { \
6776 gen_exception(ctx, POWERPC_EXCP_VPU); \
6779 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6780 rb = gen_avr_ptr(rB(ctx->opcode)); \
6781 rd = gen_avr_ptr(rD(ctx->opcode)); \
6782 gen_helper_##name(cpu_env, rd, rb, uimm); \
6783 tcg_temp_free_i32(uimm); \
6784 tcg_temp_free_ptr(rb); \
6785 tcg_temp_free_ptr(rd); \
6788 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6789 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6790 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6791 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
6792 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
6793 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
6794 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
6796 static void gen_vsldoi(DisasContext
*ctx
)
6798 TCGv_ptr ra
, rb
, rd
;
6800 if (unlikely(!ctx
->altivec_enabled
)) {
6801 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6804 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6805 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6806 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6807 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6808 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6809 tcg_temp_free_ptr(ra
);
6810 tcg_temp_free_ptr(rb
);
6811 tcg_temp_free_ptr(rd
);
6812 tcg_temp_free_i32(sh
);
6815 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6816 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6818 TCGv_ptr ra, rb, rc, rd; \
6819 if (unlikely(!ctx->altivec_enabled)) { \
6820 gen_exception(ctx, POWERPC_EXCP_VPU); \
6823 ra = gen_avr_ptr(rA(ctx->opcode)); \
6824 rb = gen_avr_ptr(rB(ctx->opcode)); \
6825 rc = gen_avr_ptr(rC(ctx->opcode)); \
6826 rd = gen_avr_ptr(rD(ctx->opcode)); \
6827 if (Rc(ctx->opcode)) { \
6828 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6830 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6832 tcg_temp_free_ptr(ra); \
6833 tcg_temp_free_ptr(rb); \
6834 tcg_temp_free_ptr(rc); \
6835 tcg_temp_free_ptr(rd); \
6838 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6840 static void gen_vmladduhm(DisasContext
*ctx
)
6842 TCGv_ptr ra
, rb
, rc
, rd
;
6843 if (unlikely(!ctx
->altivec_enabled
)) {
6844 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6847 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6848 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6849 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6850 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6851 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6852 tcg_temp_free_ptr(ra
);
6853 tcg_temp_free_ptr(rb
);
6854 tcg_temp_free_ptr(rc
);
6855 tcg_temp_free_ptr(rd
);
6858 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6859 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6860 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6861 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6862 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6864 /*** SPE extension ***/
6865 /* Register moves */
6868 static inline void gen_evmra(DisasContext
*ctx
)
6871 if (unlikely(!ctx
->spe_enabled
)) {
6872 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
6876 #if defined(TARGET_PPC64)
6878 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6881 tcg_gen_st_i64(cpu_gpr
[rA(ctx
->opcode
)],
6883 offsetof(CPUPPCState
, spe_acc
));
6885 TCGv_i64 tmp
= tcg_temp_new_i64();
6887 /* tmp := rA_lo + rA_hi << 32 */
6888 tcg_gen_concat_i32_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6890 /* spe_acc := tmp */
6891 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
6892 tcg_temp_free_i64(tmp
);
6895 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6896 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6900 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
6902 #if defined(TARGET_PPC64)
6903 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6905 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6909 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
6911 #if defined(TARGET_PPC64)
6912 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6914 TCGv_i64 tmp
= tcg_temp_new_i64();
6915 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6916 tcg_gen_shri_i64(tmp
, t
, 32);
6917 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6918 tcg_temp_free_i64(tmp
);
6922 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6923 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6925 if (Rc(ctx->opcode)) \
6931 /* Handler for undefined SPE opcodes */
6932 static inline void gen_speundef(DisasContext
*ctx
)
6934 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6938 #if defined(TARGET_PPC64)
6939 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6940 static inline void gen_##name(DisasContext *ctx) \
6942 if (unlikely(!ctx->spe_enabled)) { \
6943 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6946 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6947 cpu_gpr[rB(ctx->opcode)]); \
6950 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6951 static inline void gen_##name(DisasContext *ctx) \
6953 if (unlikely(!ctx->spe_enabled)) { \
6954 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6957 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6958 cpu_gpr[rB(ctx->opcode)]); \
6959 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6960 cpu_gprh[rB(ctx->opcode)]); \
6964 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6965 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6966 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6967 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6968 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6969 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6970 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6971 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6973 /* SPE logic immediate */
6974 #if defined(TARGET_PPC64)
6975 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6976 static inline void gen_##name(DisasContext *ctx) \
6978 if (unlikely(!ctx->spe_enabled)) { \
6979 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6982 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6983 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6984 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6985 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6986 tcg_opi(t0, t0, rB(ctx->opcode)); \
6987 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6988 tcg_gen_trunc_i64_i32(t1, t2); \
6989 tcg_temp_free_i64(t2); \
6990 tcg_opi(t1, t1, rB(ctx->opcode)); \
6991 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6992 tcg_temp_free_i32(t0); \
6993 tcg_temp_free_i32(t1); \
6996 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6997 static inline void gen_##name(DisasContext *ctx) \
6999 if (unlikely(!ctx->spe_enabled)) { \
7000 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7003 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7005 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7009 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
7010 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
7011 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
7012 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
7014 /* SPE arithmetic */
7015 #if defined(TARGET_PPC64)
7016 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7017 static inline void gen_##name(DisasContext *ctx) \
7019 if (unlikely(!ctx->spe_enabled)) { \
7020 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7023 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7024 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7025 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7026 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7028 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7029 tcg_gen_trunc_i64_i32(t1, t2); \
7030 tcg_temp_free_i64(t2); \
7032 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7033 tcg_temp_free_i32(t0); \
7034 tcg_temp_free_i32(t1); \
7037 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7038 static inline void gen_##name(DisasContext *ctx) \
7040 if (unlikely(!ctx->spe_enabled)) { \
7041 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7044 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7045 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7049 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
7051 int l1
= gen_new_label();
7052 int l2
= gen_new_label();
7054 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
7055 tcg_gen_neg_i32(ret
, arg1
);
7058 tcg_gen_mov_i32(ret
, arg1
);
7061 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
7062 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
7063 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
7064 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
7065 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
7067 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
7068 tcg_gen_ext16u_i32(ret
, ret
);
7070 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
7071 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
7072 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
7074 #if defined(TARGET_PPC64)
7075 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7076 static inline void gen_##name(DisasContext *ctx) \
7078 if (unlikely(!ctx->spe_enabled)) { \
7079 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7082 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7083 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7084 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7085 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7086 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7087 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7088 tcg_op(t0, t0, t2); \
7089 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7090 tcg_gen_trunc_i64_i32(t1, t3); \
7091 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7092 tcg_gen_trunc_i64_i32(t2, t3); \
7093 tcg_temp_free_i64(t3); \
7094 tcg_op(t1, t1, t2); \
7095 tcg_temp_free_i32(t2); \
7096 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7097 tcg_temp_free_i32(t0); \
7098 tcg_temp_free_i32(t1); \
7101 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7102 static inline void gen_##name(DisasContext *ctx) \
7104 if (unlikely(!ctx->spe_enabled)) { \
7105 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7108 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7109 cpu_gpr[rB(ctx->opcode)]); \
7110 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7111 cpu_gprh[rB(ctx->opcode)]); \
7115 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7120 l1
= gen_new_label();
7121 l2
= gen_new_label();
7122 t0
= tcg_temp_local_new_i32();
7123 /* No error here: 6 bits are used */
7124 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7125 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7126 tcg_gen_shr_i32(ret
, arg1
, t0
);
7129 tcg_gen_movi_i32(ret
, 0);
7131 tcg_temp_free_i32(t0
);
7133 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
7134 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7139 l1
= gen_new_label();
7140 l2
= gen_new_label();
7141 t0
= tcg_temp_local_new_i32();
7142 /* No error here: 6 bits are used */
7143 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7144 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7145 tcg_gen_sar_i32(ret
, arg1
, t0
);
7148 tcg_gen_movi_i32(ret
, 0);
7150 tcg_temp_free_i32(t0
);
7152 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
7153 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7158 l1
= gen_new_label();
7159 l2
= gen_new_label();
7160 t0
= tcg_temp_local_new_i32();
7161 /* No error here: 6 bits are used */
7162 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7163 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7164 tcg_gen_shl_i32(ret
, arg1
, t0
);
7167 tcg_gen_movi_i32(ret
, 0);
7169 tcg_temp_free_i32(t0
);
7171 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
7172 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7174 TCGv_i32 t0
= tcg_temp_new_i32();
7175 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
7176 tcg_gen_rotl_i32(ret
, arg1
, t0
);
7177 tcg_temp_free_i32(t0
);
7179 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
7180 static inline void gen_evmergehi(DisasContext
*ctx
)
7182 if (unlikely(!ctx
->spe_enabled
)) {
7183 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7186 #if defined(TARGET_PPC64)
7187 TCGv t0
= tcg_temp_new();
7188 TCGv t1
= tcg_temp_new();
7189 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7190 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7191 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7195 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7196 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7199 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
7200 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7202 tcg_gen_sub_i32(ret
, arg2
, arg1
);
7204 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
7206 /* SPE arithmetic immediate */
7207 #if defined(TARGET_PPC64)
7208 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7209 static inline void gen_##name(DisasContext *ctx) \
7211 if (unlikely(!ctx->spe_enabled)) { \
7212 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7215 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7216 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7217 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7218 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7219 tcg_op(t0, t0, rA(ctx->opcode)); \
7220 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7221 tcg_gen_trunc_i64_i32(t1, t2); \
7222 tcg_temp_free_i64(t2); \
7223 tcg_op(t1, t1, rA(ctx->opcode)); \
7224 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7225 tcg_temp_free_i32(t0); \
7226 tcg_temp_free_i32(t1); \
7229 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7230 static inline void gen_##name(DisasContext *ctx) \
7232 if (unlikely(!ctx->spe_enabled)) { \
7233 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7236 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7238 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7242 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
7243 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
7245 /* SPE comparison */
7246 #if defined(TARGET_PPC64)
7247 #define GEN_SPEOP_COMP(name, tcg_cond) \
7248 static inline void gen_##name(DisasContext *ctx) \
7250 if (unlikely(!ctx->spe_enabled)) { \
7251 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7254 int l1 = gen_new_label(); \
7255 int l2 = gen_new_label(); \
7256 int l3 = gen_new_label(); \
7257 int l4 = gen_new_label(); \
7258 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7259 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7260 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7261 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7262 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7263 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7264 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7266 gen_set_label(l1); \
7267 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7268 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7269 gen_set_label(l2); \
7270 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7271 tcg_gen_trunc_i64_i32(t0, t2); \
7272 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7273 tcg_gen_trunc_i64_i32(t1, t2); \
7274 tcg_temp_free_i64(t2); \
7275 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7276 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7277 ~(CRF_CH | CRF_CH_AND_CL)); \
7279 gen_set_label(l3); \
7280 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7281 CRF_CH | CRF_CH_OR_CL); \
7282 gen_set_label(l4); \
7283 tcg_temp_free_i32(t0); \
7284 tcg_temp_free_i32(t1); \
7287 #define GEN_SPEOP_COMP(name, tcg_cond) \
7288 static inline void gen_##name(DisasContext *ctx) \
7290 if (unlikely(!ctx->spe_enabled)) { \
7291 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7294 int l1 = gen_new_label(); \
7295 int l2 = gen_new_label(); \
7296 int l3 = gen_new_label(); \
7297 int l4 = gen_new_label(); \
7299 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7300 cpu_gpr[rB(ctx->opcode)], l1); \
7301 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7303 gen_set_label(l1); \
7304 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7305 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7306 gen_set_label(l2); \
7307 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7308 cpu_gprh[rB(ctx->opcode)], l3); \
7309 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7310 ~(CRF_CH | CRF_CH_AND_CL)); \
7312 gen_set_label(l3); \
7313 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7314 CRF_CH | CRF_CH_OR_CL); \
7315 gen_set_label(l4); \
7318 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
7319 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
7320 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
7321 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
7322 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
7325 static inline void gen_brinc(DisasContext
*ctx
)
7327 /* Note: brinc is usable even if SPE is disabled */
7328 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
7329 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7331 static inline void gen_evmergelo(DisasContext
*ctx
)
7333 if (unlikely(!ctx
->spe_enabled
)) {
7334 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7337 #if defined(TARGET_PPC64)
7338 TCGv t0
= tcg_temp_new();
7339 TCGv t1
= tcg_temp_new();
7340 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7341 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7342 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7346 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7347 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7350 static inline void gen_evmergehilo(DisasContext
*ctx
)
7352 if (unlikely(!ctx
->spe_enabled
)) {
7353 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7356 #if defined(TARGET_PPC64)
7357 TCGv t0
= tcg_temp_new();
7358 TCGv t1
= tcg_temp_new();
7359 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7360 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7361 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7365 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7366 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7369 static inline void gen_evmergelohi(DisasContext
*ctx
)
7371 if (unlikely(!ctx
->spe_enabled
)) {
7372 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7375 #if defined(TARGET_PPC64)
7376 TCGv t0
= tcg_temp_new();
7377 TCGv t1
= tcg_temp_new();
7378 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7379 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7380 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7384 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
7385 TCGv_i32 tmp
= tcg_temp_new_i32();
7386 tcg_gen_mov_i32(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
7387 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7388 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
7389 tcg_temp_free_i32(tmp
);
7391 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7392 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7396 static inline void gen_evsplati(DisasContext
*ctx
)
7398 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
7400 #if defined(TARGET_PPC64)
7401 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7403 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7404 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7407 static inline void gen_evsplatfi(DisasContext
*ctx
)
7409 uint64_t imm
= rA(ctx
->opcode
) << 27;
7411 #if defined(TARGET_PPC64)
7412 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7414 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7415 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7419 static inline void gen_evsel(DisasContext
*ctx
)
7421 int l1
= gen_new_label();
7422 int l2
= gen_new_label();
7423 int l3
= gen_new_label();
7424 int l4
= gen_new_label();
7425 TCGv_i32 t0
= tcg_temp_local_new_i32();
7426 #if defined(TARGET_PPC64)
7427 TCGv t1
= tcg_temp_local_new();
7428 TCGv t2
= tcg_temp_local_new();
7430 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
7431 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
7432 #if defined(TARGET_PPC64)
7433 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7435 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7439 #if defined(TARGET_PPC64)
7440 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7442 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7445 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
7446 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
7447 #if defined(TARGET_PPC64)
7448 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)]);
7450 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7454 #if defined(TARGET_PPC64)
7455 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)]);
7457 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7460 tcg_temp_free_i32(t0
);
7461 #if defined(TARGET_PPC64)
7462 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
7468 static void gen_evsel0(DisasContext
*ctx
)
7473 static void gen_evsel1(DisasContext
*ctx
)
7478 static void gen_evsel2(DisasContext
*ctx
)
7483 static void gen_evsel3(DisasContext
*ctx
)
7490 static inline void gen_evmwumi(DisasContext
*ctx
)
7494 if (unlikely(!ctx
->spe_enabled
)) {
7495 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7499 t0
= tcg_temp_new_i64();
7500 t1
= tcg_temp_new_i64();
7502 /* t0 := rA; t1 := rB */
7503 #if defined(TARGET_PPC64)
7504 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7505 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7507 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7508 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7511 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7513 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7515 tcg_temp_free_i64(t0
);
7516 tcg_temp_free_i64(t1
);
7519 static inline void gen_evmwumia(DisasContext
*ctx
)
7523 if (unlikely(!ctx
->spe_enabled
)) {
7524 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7528 gen_evmwumi(ctx
); /* rD := rA * rB */
7530 tmp
= tcg_temp_new_i64();
7533 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7534 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7535 tcg_temp_free_i64(tmp
);
7538 static inline void gen_evmwumiaa(DisasContext
*ctx
)
7543 if (unlikely(!ctx
->spe_enabled
)) {
7544 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7548 gen_evmwumi(ctx
); /* rD := rA * rB */
7550 acc
= tcg_temp_new_i64();
7551 tmp
= tcg_temp_new_i64();
7554 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7557 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7559 /* acc := tmp + acc */
7560 tcg_gen_add_i64(acc
, acc
, tmp
);
7563 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7566 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7568 tcg_temp_free_i64(acc
);
7569 tcg_temp_free_i64(tmp
);
7572 static inline void gen_evmwsmi(DisasContext
*ctx
)
7576 if (unlikely(!ctx
->spe_enabled
)) {
7577 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7581 t0
= tcg_temp_new_i64();
7582 t1
= tcg_temp_new_i64();
7584 /* t0 := rA; t1 := rB */
7585 #if defined(TARGET_PPC64)
7586 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7587 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7589 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7590 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7593 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7595 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7597 tcg_temp_free_i64(t0
);
7598 tcg_temp_free_i64(t1
);
7601 static inline void gen_evmwsmia(DisasContext
*ctx
)
7605 gen_evmwsmi(ctx
); /* rD := rA * rB */
7607 tmp
= tcg_temp_new_i64();
7610 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7611 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7613 tcg_temp_free_i64(tmp
);
7616 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
7618 TCGv_i64 acc
= tcg_temp_new_i64();
7619 TCGv_i64 tmp
= tcg_temp_new_i64();
7621 gen_evmwsmi(ctx
); /* rD := rA * rB */
7623 acc
= tcg_temp_new_i64();
7624 tmp
= tcg_temp_new_i64();
7627 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7630 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7632 /* acc := tmp + acc */
7633 tcg_gen_add_i64(acc
, acc
, tmp
);
7636 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7639 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7641 tcg_temp_free_i64(acc
);
7642 tcg_temp_free_i64(tmp
);
7645 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7646 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7647 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7648 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7649 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7650 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7651 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7652 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
7653 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
7654 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7655 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7656 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7657 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7658 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7659 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7660 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
7661 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7662 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7663 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7664 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
7665 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7666 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7667 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
7668 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
7669 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7670 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7671 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7672 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7673 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
7675 /* SPE load and stores */
7676 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
7678 target_ulong uimm
= rB(ctx
->opcode
);
7680 if (rA(ctx
->opcode
) == 0) {
7681 tcg_gen_movi_tl(EA
, uimm
<< sh
);
7683 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
7684 if (NARROW_MODE(ctx
)) {
7685 tcg_gen_ext32u_tl(EA
, EA
);
7690 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
7692 #if defined(TARGET_PPC64)
7693 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7695 TCGv_i64 t0
= tcg_temp_new_i64();
7696 gen_qemu_ld64(ctx
, t0
, addr
);
7697 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7698 tcg_gen_shri_i64(t0
, t0
, 32);
7699 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7700 tcg_temp_free_i64(t0
);
7704 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
7706 #if defined(TARGET_PPC64)
7707 TCGv t0
= tcg_temp_new();
7708 gen_qemu_ld32u(ctx
, t0
, addr
);
7709 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7710 gen_addr_add(ctx
, addr
, addr
, 4);
7711 gen_qemu_ld32u(ctx
, t0
, addr
);
7712 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7715 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7716 gen_addr_add(ctx
, addr
, addr
, 4);
7717 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7721 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
7723 TCGv t0
= tcg_temp_new();
7724 #if defined(TARGET_PPC64)
7725 gen_qemu_ld16u(ctx
, t0
, addr
);
7726 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7727 gen_addr_add(ctx
, addr
, addr
, 2);
7728 gen_qemu_ld16u(ctx
, t0
, addr
);
7729 tcg_gen_shli_tl(t0
, t0
, 32);
7730 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7731 gen_addr_add(ctx
, addr
, addr
, 2);
7732 gen_qemu_ld16u(ctx
, t0
, addr
);
7733 tcg_gen_shli_tl(t0
, t0
, 16);
7734 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7735 gen_addr_add(ctx
, addr
, addr
, 2);
7736 gen_qemu_ld16u(ctx
, t0
, addr
);
7737 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7739 gen_qemu_ld16u(ctx
, t0
, addr
);
7740 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7741 gen_addr_add(ctx
, addr
, addr
, 2);
7742 gen_qemu_ld16u(ctx
, t0
, addr
);
7743 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7744 gen_addr_add(ctx
, addr
, addr
, 2);
7745 gen_qemu_ld16u(ctx
, t0
, addr
);
7746 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7747 gen_addr_add(ctx
, addr
, addr
, 2);
7748 gen_qemu_ld16u(ctx
, t0
, addr
);
7749 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7754 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
7756 TCGv t0
= tcg_temp_new();
7757 gen_qemu_ld16u(ctx
, t0
, addr
);
7758 #if defined(TARGET_PPC64)
7759 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7760 tcg_gen_shli_tl(t0
, t0
, 16);
7761 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7763 tcg_gen_shli_tl(t0
, t0
, 16);
7764 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7765 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7770 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
7772 TCGv t0
= tcg_temp_new();
7773 gen_qemu_ld16u(ctx
, t0
, addr
);
7774 #if defined(TARGET_PPC64)
7775 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7776 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7778 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7779 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7784 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
7786 TCGv t0
= tcg_temp_new();
7787 gen_qemu_ld16s(ctx
, t0
, addr
);
7788 #if defined(TARGET_PPC64)
7789 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7790 tcg_gen_ext32u_tl(t0
, t0
);
7791 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7793 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7794 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7799 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
7801 TCGv t0
= tcg_temp_new();
7802 #if defined(TARGET_PPC64)
7803 gen_qemu_ld16u(ctx
, t0
, addr
);
7804 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7805 gen_addr_add(ctx
, addr
, addr
, 2);
7806 gen_qemu_ld16u(ctx
, t0
, addr
);
7807 tcg_gen_shli_tl(t0
, t0
, 16);
7808 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7810 gen_qemu_ld16u(ctx
, t0
, addr
);
7811 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7812 gen_addr_add(ctx
, addr
, addr
, 2);
7813 gen_qemu_ld16u(ctx
, t0
, addr
);
7814 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7819 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
7821 #if defined(TARGET_PPC64)
7822 TCGv t0
= tcg_temp_new();
7823 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7824 gen_addr_add(ctx
, addr
, addr
, 2);
7825 gen_qemu_ld16u(ctx
, t0
, addr
);
7826 tcg_gen_shli_tl(t0
, t0
, 32);
7827 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7830 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7831 gen_addr_add(ctx
, addr
, addr
, 2);
7832 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7836 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
7838 #if defined(TARGET_PPC64)
7839 TCGv t0
= tcg_temp_new();
7840 gen_qemu_ld16s(ctx
, t0
, addr
);
7841 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7842 gen_addr_add(ctx
, addr
, addr
, 2);
7843 gen_qemu_ld16s(ctx
, t0
, addr
);
7844 tcg_gen_shli_tl(t0
, t0
, 32);
7845 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7848 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7849 gen_addr_add(ctx
, addr
, addr
, 2);
7850 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7854 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
7856 TCGv t0
= tcg_temp_new();
7857 gen_qemu_ld32u(ctx
, t0
, addr
);
7858 #if defined(TARGET_PPC64)
7859 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7860 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7862 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7863 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7868 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
7870 TCGv t0
= tcg_temp_new();
7871 #if defined(TARGET_PPC64)
7872 gen_qemu_ld16u(ctx
, t0
, addr
);
7873 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7874 tcg_gen_shli_tl(t0
, t0
, 32);
7875 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7876 gen_addr_add(ctx
, addr
, addr
, 2);
7877 gen_qemu_ld16u(ctx
, t0
, addr
);
7878 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7879 tcg_gen_shli_tl(t0
, t0
, 16);
7880 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7882 gen_qemu_ld16u(ctx
, t0
, addr
);
7883 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7884 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7885 gen_addr_add(ctx
, addr
, addr
, 2);
7886 gen_qemu_ld16u(ctx
, t0
, addr
);
7887 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7888 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7893 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
7895 #if defined(TARGET_PPC64)
7896 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7898 TCGv_i64 t0
= tcg_temp_new_i64();
7899 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
7900 gen_qemu_st64(ctx
, t0
, addr
);
7901 tcg_temp_free_i64(t0
);
7905 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
7907 #if defined(TARGET_PPC64)
7908 TCGv t0
= tcg_temp_new();
7909 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7910 gen_qemu_st32(ctx
, t0
, addr
);
7913 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7915 gen_addr_add(ctx
, addr
, addr
, 4);
7916 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7919 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
7921 TCGv t0
= tcg_temp_new();
7922 #if defined(TARGET_PPC64)
7923 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7925 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7927 gen_qemu_st16(ctx
, t0
, addr
);
7928 gen_addr_add(ctx
, addr
, addr
, 2);
7929 #if defined(TARGET_PPC64)
7930 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7931 gen_qemu_st16(ctx
, t0
, addr
);
7933 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7935 gen_addr_add(ctx
, addr
, addr
, 2);
7936 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7937 gen_qemu_st16(ctx
, t0
, addr
);
7939 gen_addr_add(ctx
, addr
, addr
, 2);
7940 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7943 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
7945 TCGv t0
= tcg_temp_new();
7946 #if defined(TARGET_PPC64)
7947 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7949 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7951 gen_qemu_st16(ctx
, t0
, addr
);
7952 gen_addr_add(ctx
, addr
, addr
, 2);
7953 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7954 gen_qemu_st16(ctx
, t0
, addr
);
7958 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7960 #if defined(TARGET_PPC64)
7961 TCGv t0
= tcg_temp_new();
7962 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7963 gen_qemu_st16(ctx
, t0
, addr
);
7966 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7968 gen_addr_add(ctx
, addr
, addr
, 2);
7969 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7972 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7974 #if defined(TARGET_PPC64)
7975 TCGv t0
= tcg_temp_new();
7976 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7977 gen_qemu_st32(ctx
, t0
, addr
);
7980 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7984 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7986 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7989 #define GEN_SPEOP_LDST(name, opc2, sh) \
7990 static void glue(gen_, name)(DisasContext *ctx) \
7993 if (unlikely(!ctx->spe_enabled)) { \
7994 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7997 gen_set_access_type(ctx, ACCESS_INT); \
7998 t0 = tcg_temp_new(); \
7999 if (Rc(ctx->opcode)) { \
8000 gen_addr_spe_imm_index(ctx, t0, sh); \
8002 gen_addr_reg_index(ctx, t0); \
8004 gen_op_##name(ctx, t0); \
8005 tcg_temp_free(t0); \
8008 GEN_SPEOP_LDST(evldd
, 0x00, 3);
8009 GEN_SPEOP_LDST(evldw
, 0x01, 3);
8010 GEN_SPEOP_LDST(evldh
, 0x02, 3);
8011 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
8012 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
8013 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
8014 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
8015 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
8016 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
8017 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
8018 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
8020 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
8021 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
8022 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
8023 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
8024 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
8025 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
8026 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
8028 /* Multiply and add - TODO */
8030 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
8031 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8032 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8033 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8034 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8035 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8036 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8037 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8038 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8039 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8040 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8041 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8043 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8044 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8045 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8046 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8047 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8048 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8049 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8050 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8051 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8052 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8053 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8054 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8056 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8057 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8058 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8059 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8060 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
8062 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8063 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8064 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8065 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8066 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8067 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8068 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8069 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8070 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8071 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8072 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8073 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8075 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8076 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8077 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8078 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8080 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8081 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8082 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8083 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8084 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8085 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8086 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8087 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8088 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8089 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8090 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8091 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8093 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8094 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8095 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8096 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8097 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8100 /*** SPE floating-point extension ***/
8101 #if defined(TARGET_PPC64)
8102 #define GEN_SPEFPUOP_CONV_32_32(name) \
8103 static inline void gen_##name(DisasContext *ctx) \
8107 t0 = tcg_temp_new_i32(); \
8108 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8109 gen_helper_##name(t0, cpu_env, t0); \
8110 t1 = tcg_temp_new(); \
8111 tcg_gen_extu_i32_tl(t1, t0); \
8112 tcg_temp_free_i32(t0); \
8113 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8114 0xFFFFFFFF00000000ULL); \
8115 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8116 tcg_temp_free(t1); \
8118 #define GEN_SPEFPUOP_CONV_32_64(name) \
8119 static inline void gen_##name(DisasContext *ctx) \
8123 t0 = tcg_temp_new_i32(); \
8124 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8125 t1 = tcg_temp_new(); \
8126 tcg_gen_extu_i32_tl(t1, t0); \
8127 tcg_temp_free_i32(t0); \
8128 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8129 0xFFFFFFFF00000000ULL); \
8130 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8131 tcg_temp_free(t1); \
8133 #define GEN_SPEFPUOP_CONV_64_32(name) \
8134 static inline void gen_##name(DisasContext *ctx) \
8136 TCGv_i32 t0 = tcg_temp_new_i32(); \
8137 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8138 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8139 tcg_temp_free_i32(t0); \
8141 #define GEN_SPEFPUOP_CONV_64_64(name) \
8142 static inline void gen_##name(DisasContext *ctx) \
8144 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8145 cpu_gpr[rB(ctx->opcode)]); \
8147 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8148 static inline void gen_##name(DisasContext *ctx) \
8152 if (unlikely(!ctx->spe_enabled)) { \
8153 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8156 t0 = tcg_temp_new_i32(); \
8157 t1 = tcg_temp_new_i32(); \
8158 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8159 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8160 gen_helper_##name(t0, cpu_env, t0, t1); \
8161 tcg_temp_free_i32(t1); \
8162 t2 = tcg_temp_new(); \
8163 tcg_gen_extu_i32_tl(t2, t0); \
8164 tcg_temp_free_i32(t0); \
8165 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8166 0xFFFFFFFF00000000ULL); \
8167 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8168 tcg_temp_free(t2); \
8170 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8171 static inline void gen_##name(DisasContext *ctx) \
8173 if (unlikely(!ctx->spe_enabled)) { \
8174 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8177 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8178 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8180 #define GEN_SPEFPUOP_COMP_32(name) \
8181 static inline void gen_##name(DisasContext *ctx) \
8184 if (unlikely(!ctx->spe_enabled)) { \
8185 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8188 t0 = tcg_temp_new_i32(); \
8189 t1 = tcg_temp_new_i32(); \
8190 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8191 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8192 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8193 tcg_temp_free_i32(t0); \
8194 tcg_temp_free_i32(t1); \
8196 #define GEN_SPEFPUOP_COMP_64(name) \
8197 static inline void gen_##name(DisasContext *ctx) \
8199 if (unlikely(!ctx->spe_enabled)) { \
8200 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8203 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8204 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8207 #define GEN_SPEFPUOP_CONV_32_32(name) \
8208 static inline void gen_##name(DisasContext *ctx) \
8210 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8211 cpu_gpr[rB(ctx->opcode)]); \
8213 #define GEN_SPEFPUOP_CONV_32_64(name) \
8214 static inline void gen_##name(DisasContext *ctx) \
8216 TCGv_i64 t0 = tcg_temp_new_i64(); \
8217 gen_load_gpr64(t0, rB(ctx->opcode)); \
8218 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8219 tcg_temp_free_i64(t0); \
8221 #define GEN_SPEFPUOP_CONV_64_32(name) \
8222 static inline void gen_##name(DisasContext *ctx) \
8224 TCGv_i64 t0 = tcg_temp_new_i64(); \
8225 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8226 gen_store_gpr64(rD(ctx->opcode), t0); \
8227 tcg_temp_free_i64(t0); \
8229 #define GEN_SPEFPUOP_CONV_64_64(name) \
8230 static inline void gen_##name(DisasContext *ctx) \
8232 TCGv_i64 t0 = tcg_temp_new_i64(); \
8233 gen_load_gpr64(t0, rB(ctx->opcode)); \
8234 gen_helper_##name(t0, cpu_env, t0); \
8235 gen_store_gpr64(rD(ctx->opcode), t0); \
8236 tcg_temp_free_i64(t0); \
8238 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8239 static inline void gen_##name(DisasContext *ctx) \
8241 if (unlikely(!ctx->spe_enabled)) { \
8242 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8245 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8246 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8248 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8249 static inline void gen_##name(DisasContext *ctx) \
8252 if (unlikely(!ctx->spe_enabled)) { \
8253 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8256 t0 = tcg_temp_new_i64(); \
8257 t1 = tcg_temp_new_i64(); \
8258 gen_load_gpr64(t0, rA(ctx->opcode)); \
8259 gen_load_gpr64(t1, rB(ctx->opcode)); \
8260 gen_helper_##name(t0, cpu_env, t0, t1); \
8261 gen_store_gpr64(rD(ctx->opcode), t0); \
8262 tcg_temp_free_i64(t0); \
8263 tcg_temp_free_i64(t1); \
8265 #define GEN_SPEFPUOP_COMP_32(name) \
8266 static inline void gen_##name(DisasContext *ctx) \
8268 if (unlikely(!ctx->spe_enabled)) { \
8269 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8272 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8275 #define GEN_SPEFPUOP_COMP_64(name) \
8276 static inline void gen_##name(DisasContext *ctx) \
8279 if (unlikely(!ctx->spe_enabled)) { \
8280 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8283 t0 = tcg_temp_new_i64(); \
8284 t1 = tcg_temp_new_i64(); \
8285 gen_load_gpr64(t0, rA(ctx->opcode)); \
8286 gen_load_gpr64(t1, rB(ctx->opcode)); \
8287 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8288 tcg_temp_free_i64(t0); \
8289 tcg_temp_free_i64(t1); \
8293 /* Single precision floating-point vectors operations */
8295 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
8296 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
8297 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
8298 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
8299 static inline void gen_evfsabs(DisasContext
*ctx
)
8301 if (unlikely(!ctx
->spe_enabled
)) {
8302 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8305 #if defined(TARGET_PPC64)
8306 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
8308 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
8309 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8312 static inline void gen_evfsnabs(DisasContext
*ctx
)
8314 if (unlikely(!ctx
->spe_enabled
)) {
8315 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8318 #if defined(TARGET_PPC64)
8319 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8321 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8322 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8325 static inline void gen_evfsneg(DisasContext
*ctx
)
8327 if (unlikely(!ctx
->spe_enabled
)) {
8328 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8331 #if defined(TARGET_PPC64)
8332 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8334 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8335 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8340 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
8341 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
8342 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
8343 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
8344 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
8345 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
8346 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
8347 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
8348 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
8349 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
8352 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
8353 GEN_SPEFPUOP_COMP_64(evfscmplt
);
8354 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
8355 GEN_SPEFPUOP_COMP_64(evfststgt
);
8356 GEN_SPEFPUOP_COMP_64(evfststlt
);
8357 GEN_SPEFPUOP_COMP_64(evfststeq
);
8359 /* Opcodes definitions */
8360 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8361 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8362 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8363 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8364 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8365 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8366 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8367 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8368 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8369 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8370 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8371 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8372 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8373 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8375 /* Single precision floating-point operations */
8377 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
8378 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
8379 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
8380 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
8381 static inline void gen_efsabs(DisasContext
*ctx
)
8383 if (unlikely(!ctx
->spe_enabled
)) {
8384 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8387 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
8389 static inline void gen_efsnabs(DisasContext
*ctx
)
8391 if (unlikely(!ctx
->spe_enabled
)) {
8392 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8395 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8397 static inline void gen_efsneg(DisasContext
*ctx
)
8399 if (unlikely(!ctx
->spe_enabled
)) {
8400 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8403 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8407 GEN_SPEFPUOP_CONV_32_32(efscfui
);
8408 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
8409 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
8410 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
8411 GEN_SPEFPUOP_CONV_32_32(efsctui
);
8412 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
8413 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
8414 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
8415 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
8416 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
8417 GEN_SPEFPUOP_CONV_32_64(efscfd
);
8420 GEN_SPEFPUOP_COMP_32(efscmpgt
);
8421 GEN_SPEFPUOP_COMP_32(efscmplt
);
8422 GEN_SPEFPUOP_COMP_32(efscmpeq
);
8423 GEN_SPEFPUOP_COMP_32(efststgt
);
8424 GEN_SPEFPUOP_COMP_32(efststlt
);
8425 GEN_SPEFPUOP_COMP_32(efststeq
);
8427 /* Opcodes definitions */
8428 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8429 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8430 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8431 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8432 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8433 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
8434 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8435 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8436 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8437 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8438 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8439 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8440 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8441 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8443 /* Double precision floating-point operations */
8445 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
8446 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
8447 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
8448 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
8449 static inline void gen_efdabs(DisasContext
*ctx
)
8451 if (unlikely(!ctx
->spe_enabled
)) {
8452 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8455 #if defined(TARGET_PPC64)
8456 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
8458 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8459 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8462 static inline void gen_efdnabs(DisasContext
*ctx
)
8464 if (unlikely(!ctx
->spe_enabled
)) {
8465 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8468 #if defined(TARGET_PPC64)
8469 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8471 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8472 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8475 static inline void gen_efdneg(DisasContext
*ctx
)
8477 if (unlikely(!ctx
->spe_enabled
)) {
8478 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8481 #if defined(TARGET_PPC64)
8482 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8484 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8485 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8490 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8491 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8492 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8493 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8494 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8495 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8496 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8497 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8498 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8499 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8500 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8501 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8502 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8503 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8504 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8507 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8508 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8509 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8510 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8511 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8512 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8514 /* Opcodes definitions */
8515 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8516 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8517 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
8518 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8519 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8520 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8521 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8522 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
8523 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8524 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8525 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8526 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8527 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8528 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8529 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8530 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8532 static opcode_t opcodes
[] = {
8533 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
8534 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
8535 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8536 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
8537 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8538 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
8539 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
8540 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8541 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8542 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8543 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8544 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
8545 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
8546 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
8547 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
8548 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8549 #if defined(TARGET_PPC64)
8550 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
8552 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
8553 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
8554 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8555 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8556 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8557 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
8558 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
8559 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
8560 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8561 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8562 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8563 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8564 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
),
8565 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
8566 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
8567 #if defined(TARGET_PPC64)
8568 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
8569 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
8570 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
8572 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8573 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8574 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8575 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
8576 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
8577 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
8578 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
8579 #if defined(TARGET_PPC64)
8580 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
8581 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
8582 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
8583 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
8584 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
8586 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
8587 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8588 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8589 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
8590 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
8591 GEN_HANDLER(fabs
, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT
),
8592 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
8593 GEN_HANDLER(fnabs
, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT
),
8594 GEN_HANDLER(fneg
, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT
),
8595 GEN_HANDLER_E(fcpsgn
, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE
, PPC2_ISA205
),
8596 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
8597 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
8598 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
8599 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
8600 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT
),
8601 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
),
8602 #if defined(TARGET_PPC64)
8603 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8604 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
8605 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8607 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8608 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8609 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
8610 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
8611 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
8612 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
8613 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
8614 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
8615 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
8616 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
8617 #if defined(TARGET_PPC64)
8618 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
8619 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
8621 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
8622 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
8623 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8624 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8625 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
8626 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
8627 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
8628 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
8629 #if defined(TARGET_PPC64)
8630 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
8631 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
8633 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
8634 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
8635 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8636 #if defined(TARGET_PPC64)
8637 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
8638 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8640 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
8641 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
8642 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
8643 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
8644 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
8645 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
8646 #if defined(TARGET_PPC64)
8647 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
8649 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
),
8650 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
),
8651 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
8652 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
8653 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
8654 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
),
8655 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
),
8656 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
8657 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
8658 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
8659 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
8660 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
8661 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
8662 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
8663 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
8664 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
8665 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
8666 #if defined(TARGET_PPC64)
8667 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
8668 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8670 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
8671 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8673 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
8674 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
8675 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
8677 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
8678 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
),
8679 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
),
8680 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
8681 #if defined(TARGET_PPC64)
8682 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
),
8683 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
8685 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
8686 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
8687 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
8688 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
8689 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
8690 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
8691 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
8692 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
8693 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
8694 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
8695 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
8696 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8697 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
8698 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
8699 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
8700 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
8701 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
8702 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
8703 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
8704 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8705 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
8706 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
8707 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
8708 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
8709 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
8710 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
8711 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
8712 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
8713 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
8714 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
8715 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
8716 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
8717 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
8718 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
8719 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
8720 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
8721 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
8722 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
8723 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
8724 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
8725 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
8726 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
8727 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
8728 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
8729 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
8730 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
8731 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
8732 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
8733 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
8734 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8735 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8736 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
8737 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
8738 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8739 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8740 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
8741 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
8742 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
8743 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
8744 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
8745 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
8746 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
8747 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
8748 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
8749 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
8750 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
8751 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
8752 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
8753 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
8754 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
8755 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
8756 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
8757 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
8758 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
8759 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
8760 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
8761 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
8762 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
8763 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
8764 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
8765 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8766 PPC_NONE
, PPC2_BOOKE206
),
8767 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8768 PPC_NONE
, PPC2_BOOKE206
),
8769 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8770 PPC_NONE
, PPC2_BOOKE206
),
8771 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8772 PPC_NONE
, PPC2_BOOKE206
),
8773 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8774 PPC_NONE
, PPC2_BOOKE206
),
8775 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8776 PPC_NONE
, PPC2_PRCNTL
),
8777 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8778 PPC_NONE
, PPC2_PRCNTL
),
8779 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
8780 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
8781 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
8782 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
8783 PPC_BOOKE
, PPC2_BOOKE206
),
8784 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
8785 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8786 PPC_BOOKE
, PPC2_BOOKE206
),
8787 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
8788 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
8789 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
8790 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
8791 GEN_HANDLER(vsldoi
, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC
),
8792 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
8793 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
8794 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
8795 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
8796 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
8798 #undef GEN_INT_ARITH_ADD
8799 #undef GEN_INT_ARITH_ADD_CONST
8800 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8801 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8802 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8803 add_ca, compute_ca, compute_ov) \
8804 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8805 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
8806 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
8807 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
8808 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
8809 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
8810 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
8811 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
8812 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
8813 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
8814 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
8816 #undef GEN_INT_ARITH_DIVW
8817 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8818 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8819 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
8820 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
8821 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
8822 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
8824 #if defined(TARGET_PPC64)
8825 #undef GEN_INT_ARITH_DIVD
8826 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8827 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8828 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
8829 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
8830 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
8831 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
8833 #undef GEN_INT_ARITH_MUL_HELPER
8834 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8835 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8836 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
8837 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
8838 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
8841 #undef GEN_INT_ARITH_SUBF
8842 #undef GEN_INT_ARITH_SUBF_CONST
8843 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8844 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8845 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8846 add_ca, compute_ca, compute_ov) \
8847 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8848 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
8849 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
8850 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
8851 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
8852 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
8853 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
8854 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
8855 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
8856 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
8857 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
8861 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8862 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8863 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8864 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8865 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
8866 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
8867 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
8868 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
8869 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
8870 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
8871 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
8872 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
8873 #if defined(TARGET_PPC64)
8874 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
8877 #if defined(TARGET_PPC64)
8880 #define GEN_PPC64_R2(name, opc1, opc2) \
8881 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8882 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8884 #define GEN_PPC64_R4(name, opc1, opc2) \
8885 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8886 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8888 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8890 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8892 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
8893 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
8894 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
8895 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
8896 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
8897 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
8900 #undef _GEN_FLOAT_ACB
8901 #undef GEN_FLOAT_ACB
8902 #undef _GEN_FLOAT_AB
8904 #undef _GEN_FLOAT_AC
8908 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8909 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8910 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8911 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8912 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8913 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8914 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8915 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8916 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8917 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8918 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8919 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8920 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8921 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8922 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8923 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8924 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8925 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8926 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8928 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
8929 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
8930 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
8931 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
8932 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
8933 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
8934 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
8935 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
8936 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
8937 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
8938 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
8939 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
8940 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
8941 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
8942 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
8943 #if defined(TARGET_PPC64)
8944 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
),
8945 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
),
8946 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
),
8948 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
8949 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
8950 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
8951 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
8958 #define GEN_LD(name, ldop, opc, type) \
8959 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8960 #define GEN_LDU(name, ldop, opc, type) \
8961 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8962 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8963 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8964 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8965 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8966 #define GEN_LDS(name, ldop, op, type) \
8967 GEN_LD(name, ldop, op | 0x20, type) \
8968 GEN_LDU(name, ldop, op | 0x21, type) \
8969 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8970 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8972 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
8973 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
8974 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
8975 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
8976 #if defined(TARGET_PPC64)
8977 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
8978 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
8979 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
8980 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
8981 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
8983 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
8984 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
8991 #define GEN_ST(name, stop, opc, type) \
8992 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8993 #define GEN_STU(name, stop, opc, type) \
8994 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8995 #define GEN_STUX(name, stop, opc2, opc3, type) \
8996 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8997 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8998 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8999 #define GEN_STS(name, stop, op, type) \
9000 GEN_ST(name, stop, op | 0x20, type) \
9001 GEN_STU(name, stop, op | 0x21, type) \
9002 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9003 GEN_STX(name, stop, 0x17, op | 0x00, type)
9005 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
9006 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
9007 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
9008 #if defined(TARGET_PPC64)
9009 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
9010 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
9011 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
9013 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
9014 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
9021 #define GEN_LDF(name, ldop, opc, type) \
9022 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9023 #define GEN_LDUF(name, ldop, opc, type) \
9024 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9025 #define GEN_LDUXF(name, ldop, opc, type) \
9026 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9027 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9028 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9029 #define GEN_LDFS(name, ldop, op, type) \
9030 GEN_LDF(name, ldop, op | 0x20, type) \
9031 GEN_LDUF(name, ldop, op | 0x21, type) \
9032 GEN_LDUXF(name, ldop, op | 0x01, type) \
9033 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9035 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
9036 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
9037 GEN_HANDLER_E(lfiwax
, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE
, PPC2_ISA205
),
9044 #define GEN_STF(name, stop, opc, type) \
9045 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9046 #define GEN_STUF(name, stop, opc, type) \
9047 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9048 #define GEN_STUXF(name, stop, opc, type) \
9049 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9050 #define GEN_STXF(name, stop, opc2, opc3, type) \
9051 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9052 #define GEN_STFS(name, stop, op, type) \
9053 GEN_STF(name, stop, op | 0x20, type) \
9054 GEN_STUF(name, stop, op | 0x21, type) \
9055 GEN_STUXF(name, stop, op | 0x01, type) \
9056 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9058 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
9059 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
9060 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
9063 #define GEN_CRLOGIC(name, tcg_op, opc) \
9064 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9065 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
9066 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
9067 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
9068 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
9069 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
9070 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
9071 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
9072 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
9074 #undef GEN_MAC_HANDLER
9075 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9076 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9077 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
9078 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
9079 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
9080 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
9081 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
9082 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
9083 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
9084 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
9085 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
9086 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
9087 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
9088 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
9089 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
9090 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
9091 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
9092 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
9093 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
9094 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
9095 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
9096 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
9097 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
9098 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
9099 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
9100 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
9101 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
9102 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
9103 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
9104 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
9105 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
9106 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
9107 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
9108 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
9109 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
9110 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
9111 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
9112 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
9113 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
9114 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
9115 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
9116 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
9117 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
9118 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
9124 #define GEN_VR_LDX(name, opc2, opc3) \
9125 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9126 #define GEN_VR_STX(name, opc2, opc3) \
9127 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9128 #define GEN_VR_LVE(name, opc2, opc3) \
9129 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9130 #define GEN_VR_STVE(name, opc2, opc3) \
9131 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9132 GEN_VR_LDX(lvx
, 0x07, 0x03),
9133 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
9134 GEN_VR_LVE(bx
, 0x07, 0x00),
9135 GEN_VR_LVE(hx
, 0x07, 0x01),
9136 GEN_VR_LVE(wx
, 0x07, 0x02),
9137 GEN_VR_STX(svx
, 0x07, 0x07),
9138 GEN_VR_STX(svxl
, 0x07, 0x0F),
9139 GEN_VR_STVE(bx
, 0x07, 0x04),
9140 GEN_VR_STVE(hx
, 0x07, 0x05),
9141 GEN_VR_STVE(wx
, 0x07, 0x06),
9143 #undef GEN_VX_LOGICAL
9144 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9145 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9146 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
9147 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
9148 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
9149 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
9150 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
9153 #define GEN_VXFORM(name, opc2, opc3) \
9154 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9155 GEN_VXFORM(vaddubm
, 0, 0),
9156 GEN_VXFORM(vadduhm
, 0, 1),
9157 GEN_VXFORM(vadduwm
, 0, 2),
9158 GEN_VXFORM(vsububm
, 0, 16),
9159 GEN_VXFORM(vsubuhm
, 0, 17),
9160 GEN_VXFORM(vsubuwm
, 0, 18),
9161 GEN_VXFORM(vmaxub
, 1, 0),
9162 GEN_VXFORM(vmaxuh
, 1, 1),
9163 GEN_VXFORM(vmaxuw
, 1, 2),
9164 GEN_VXFORM(vmaxsb
, 1, 4),
9165 GEN_VXFORM(vmaxsh
, 1, 5),
9166 GEN_VXFORM(vmaxsw
, 1, 6),
9167 GEN_VXFORM(vminub
, 1, 8),
9168 GEN_VXFORM(vminuh
, 1, 9),
9169 GEN_VXFORM(vminuw
, 1, 10),
9170 GEN_VXFORM(vminsb
, 1, 12),
9171 GEN_VXFORM(vminsh
, 1, 13),
9172 GEN_VXFORM(vminsw
, 1, 14),
9173 GEN_VXFORM(vavgub
, 1, 16),
9174 GEN_VXFORM(vavguh
, 1, 17),
9175 GEN_VXFORM(vavguw
, 1, 18),
9176 GEN_VXFORM(vavgsb
, 1, 20),
9177 GEN_VXFORM(vavgsh
, 1, 21),
9178 GEN_VXFORM(vavgsw
, 1, 22),
9179 GEN_VXFORM(vmrghb
, 6, 0),
9180 GEN_VXFORM(vmrghh
, 6, 1),
9181 GEN_VXFORM(vmrghw
, 6, 2),
9182 GEN_VXFORM(vmrglb
, 6, 4),
9183 GEN_VXFORM(vmrglh
, 6, 5),
9184 GEN_VXFORM(vmrglw
, 6, 6),
9185 GEN_VXFORM(vmuloub
, 4, 0),
9186 GEN_VXFORM(vmulouh
, 4, 1),
9187 GEN_VXFORM(vmulosb
, 4, 4),
9188 GEN_VXFORM(vmulosh
, 4, 5),
9189 GEN_VXFORM(vmuleub
, 4, 8),
9190 GEN_VXFORM(vmuleuh
, 4, 9),
9191 GEN_VXFORM(vmulesb
, 4, 12),
9192 GEN_VXFORM(vmulesh
, 4, 13),
9193 GEN_VXFORM(vslb
, 2, 4),
9194 GEN_VXFORM(vslh
, 2, 5),
9195 GEN_VXFORM(vslw
, 2, 6),
9196 GEN_VXFORM(vsrb
, 2, 8),
9197 GEN_VXFORM(vsrh
, 2, 9),
9198 GEN_VXFORM(vsrw
, 2, 10),
9199 GEN_VXFORM(vsrab
, 2, 12),
9200 GEN_VXFORM(vsrah
, 2, 13),
9201 GEN_VXFORM(vsraw
, 2, 14),
9202 GEN_VXFORM(vslo
, 6, 16),
9203 GEN_VXFORM(vsro
, 6, 17),
9204 GEN_VXFORM(vaddcuw
, 0, 6),
9205 GEN_VXFORM(vsubcuw
, 0, 22),
9206 GEN_VXFORM(vaddubs
, 0, 8),
9207 GEN_VXFORM(vadduhs
, 0, 9),
9208 GEN_VXFORM(vadduws
, 0, 10),
9209 GEN_VXFORM(vaddsbs
, 0, 12),
9210 GEN_VXFORM(vaddshs
, 0, 13),
9211 GEN_VXFORM(vaddsws
, 0, 14),
9212 GEN_VXFORM(vsububs
, 0, 24),
9213 GEN_VXFORM(vsubuhs
, 0, 25),
9214 GEN_VXFORM(vsubuws
, 0, 26),
9215 GEN_VXFORM(vsubsbs
, 0, 28),
9216 GEN_VXFORM(vsubshs
, 0, 29),
9217 GEN_VXFORM(vsubsws
, 0, 30),
9218 GEN_VXFORM(vrlb
, 2, 0),
9219 GEN_VXFORM(vrlh
, 2, 1),
9220 GEN_VXFORM(vrlw
, 2, 2),
9221 GEN_VXFORM(vsl
, 2, 7),
9222 GEN_VXFORM(vsr
, 2, 11),
9223 GEN_VXFORM(vpkuhum
, 7, 0),
9224 GEN_VXFORM(vpkuwum
, 7, 1),
9225 GEN_VXFORM(vpkuhus
, 7, 2),
9226 GEN_VXFORM(vpkuwus
, 7, 3),
9227 GEN_VXFORM(vpkshus
, 7, 4),
9228 GEN_VXFORM(vpkswus
, 7, 5),
9229 GEN_VXFORM(vpkshss
, 7, 6),
9230 GEN_VXFORM(vpkswss
, 7, 7),
9231 GEN_VXFORM(vpkpx
, 7, 12),
9232 GEN_VXFORM(vsum4ubs
, 4, 24),
9233 GEN_VXFORM(vsum4sbs
, 4, 28),
9234 GEN_VXFORM(vsum4shs
, 4, 25),
9235 GEN_VXFORM(vsum2sws
, 4, 26),
9236 GEN_VXFORM(vsumsws
, 4, 30),
9237 GEN_VXFORM(vaddfp
, 5, 0),
9238 GEN_VXFORM(vsubfp
, 5, 1),
9239 GEN_VXFORM(vmaxfp
, 5, 16),
9240 GEN_VXFORM(vminfp
, 5, 17),
9244 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9245 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9246 #define GEN_VXRFORM(name, opc2, opc3) \
9247 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9248 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9249 GEN_VXRFORM(vcmpequb
, 3, 0)
9250 GEN_VXRFORM(vcmpequh
, 3, 1)
9251 GEN_VXRFORM(vcmpequw
, 3, 2)
9252 GEN_VXRFORM(vcmpgtsb
, 3, 12)
9253 GEN_VXRFORM(vcmpgtsh
, 3, 13)
9254 GEN_VXRFORM(vcmpgtsw
, 3, 14)
9255 GEN_VXRFORM(vcmpgtub
, 3, 8)
9256 GEN_VXRFORM(vcmpgtuh
, 3, 9)
9257 GEN_VXRFORM(vcmpgtuw
, 3, 10)
9258 GEN_VXRFORM(vcmpeqfp
, 3, 3)
9259 GEN_VXRFORM(vcmpgefp
, 3, 7)
9260 GEN_VXRFORM(vcmpgtfp
, 3, 11)
9261 GEN_VXRFORM(vcmpbfp
, 3, 15)
9263 #undef GEN_VXFORM_SIMM
9264 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9265 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9266 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
9267 GEN_VXFORM_SIMM(vspltish
, 6, 13),
9268 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
9270 #undef GEN_VXFORM_NOA
9271 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9272 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9273 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
9274 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
9275 GEN_VXFORM_NOA(vupklsb
, 7, 10),
9276 GEN_VXFORM_NOA(vupklsh
, 7, 11),
9277 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
9278 GEN_VXFORM_NOA(vupklpx
, 7, 15),
9279 GEN_VXFORM_NOA(vrefp
, 5, 4),
9280 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
9281 GEN_VXFORM_NOA(vexptefp
, 5, 6),
9282 GEN_VXFORM_NOA(vlogefp
, 5, 7),
9283 GEN_VXFORM_NOA(vrfim
, 5, 8),
9284 GEN_VXFORM_NOA(vrfin
, 5, 9),
9285 GEN_VXFORM_NOA(vrfip
, 5, 10),
9286 GEN_VXFORM_NOA(vrfiz
, 5, 11),
9288 #undef GEN_VXFORM_UIMM
9289 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9290 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9291 GEN_VXFORM_UIMM(vspltb
, 6, 8),
9292 GEN_VXFORM_UIMM(vsplth
, 6, 9),
9293 GEN_VXFORM_UIMM(vspltw
, 6, 10),
9294 GEN_VXFORM_UIMM(vcfux
, 5, 12),
9295 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
9296 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
9297 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
9299 #undef GEN_VAFORM_PAIRED
9300 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9301 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9302 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
9303 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
9304 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
9305 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
9306 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
9307 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
9310 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9311 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9312 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9313 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9314 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9315 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9316 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9317 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9318 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9319 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
9320 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
9321 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9322 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9323 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9324 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9325 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9326 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9327 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
9328 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9329 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9330 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9331 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9332 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9333 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9334 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9335 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9336 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9337 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9338 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9339 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9340 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
9342 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9343 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9344 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9345 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9346 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9347 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9348 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9349 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9350 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9351 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9352 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9353 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9354 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9355 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9357 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9358 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9359 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9360 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9361 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9362 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
9363 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9364 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9365 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9366 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9367 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9368 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9369 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9370 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9372 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9373 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9374 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
9375 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9376 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9377 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9378 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9379 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
9380 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9381 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9382 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9383 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9384 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9385 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9386 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9387 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9389 #undef GEN_SPEOP_LDST
9390 #define GEN_SPEOP_LDST(name, opc2, sh) \
9391 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9392 GEN_SPEOP_LDST(evldd
, 0x00, 3),
9393 GEN_SPEOP_LDST(evldw
, 0x01, 3),
9394 GEN_SPEOP_LDST(evldh
, 0x02, 3),
9395 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
9396 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
9397 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
9398 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
9399 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
9400 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
9401 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
9402 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
9404 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
9405 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
9406 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
9407 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
9408 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
9409 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
9410 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
9413 #include "helper_regs.h"
9414 #include "translate_init.c"
9416 /*****************************************************************************/
9417 /* Misc PowerPC helpers */
9418 void cpu_dump_state (CPUPPCState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9426 cpu_synchronize_state(env
);
9428 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
9429 TARGET_FMT_lx
" XER " TARGET_FMT_lx
"\n",
9430 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
));
9431 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
9432 TARGET_FMT_lx
" idx %d\n", env
->msr
, env
->spr
[SPR_HID0
],
9433 env
->hflags
, env
->mmu_idx
);
9434 #if !defined(NO_TIMER_DUMP)
9435 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
9436 #if !defined(CONFIG_USER_ONLY)
9440 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
9441 #if !defined(CONFIG_USER_ONLY)
9442 , cpu_ppc_load_decr(env
)
9446 for (i
= 0; i
< 32; i
++) {
9447 if ((i
& (RGPL
- 1)) == 0)
9448 cpu_fprintf(f
, "GPR%02d", i
);
9449 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
9450 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
9451 cpu_fprintf(f
, "\n");
9453 cpu_fprintf(f
, "CR ");
9454 for (i
= 0; i
< 8; i
++)
9455 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
9456 cpu_fprintf(f
, " [");
9457 for (i
= 0; i
< 8; i
++) {
9459 if (env
->crf
[i
] & 0x08)
9461 else if (env
->crf
[i
] & 0x04)
9463 else if (env
->crf
[i
] & 0x02)
9465 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
9467 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
9469 for (i
= 0; i
< 32; i
++) {
9470 if ((i
& (RFPL
- 1)) == 0)
9471 cpu_fprintf(f
, "FPR%02d", i
);
9472 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
9473 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
9474 cpu_fprintf(f
, "\n");
9476 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
9477 #if !defined(CONFIG_USER_ONLY)
9478 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
9479 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
9480 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
9481 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
9483 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
9484 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
9485 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
9486 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
9488 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
9489 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
9490 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
9491 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
9493 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
9494 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
9495 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
9496 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
9497 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
9499 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
9500 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
9501 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
9502 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
9504 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
9505 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
9506 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
9507 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
9509 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
9510 " EPR " TARGET_FMT_lx
"\n",
9511 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
9512 env
->spr
[SPR_BOOKE_EPR
]);
9515 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
9516 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
9517 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
9518 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
9521 * IVORs are left out as they are large and do not change often --
9522 * they can be read with "p $ivor0", "p $ivor1", etc.
9526 #if defined(TARGET_PPC64)
9527 if (env
->flags
& POWERPC_FLAG_CFAR
) {
9528 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
9532 switch (env
->mmu_model
) {
9533 case POWERPC_MMU_32B
:
9534 case POWERPC_MMU_601
:
9535 case POWERPC_MMU_SOFT_6xx
:
9536 case POWERPC_MMU_SOFT_74xx
:
9537 #if defined(TARGET_PPC64)
9538 case POWERPC_MMU_64B
:
9540 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
]);
9542 case POWERPC_MMU_BOOKE206
:
9543 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
9544 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
9545 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
9546 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
9548 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
9549 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
9550 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
9551 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
9553 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
9554 " TLB1CFG " TARGET_FMT_lx
"\n",
9555 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
9556 env
->spr
[SPR_BOOKE_TLB1CFG
]);
9567 void cpu_dump_statistics (CPUPPCState
*env
, FILE*f
, fprintf_function cpu_fprintf
,
9570 #if defined(DO_PPC_STATISTICS)
9571 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
9575 for (op1
= 0; op1
< 64; op1
++) {
9577 if (is_indirect_opcode(handler
)) {
9578 t2
= ind_table(handler
);
9579 for (op2
= 0; op2
< 32; op2
++) {
9581 if (is_indirect_opcode(handler
)) {
9582 t3
= ind_table(handler
);
9583 for (op3
= 0; op3
< 32; op3
++) {
9585 if (handler
->count
== 0)
9587 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
9588 "%016" PRIx64
" %" PRId64
"\n",
9589 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
9591 handler
->count
, handler
->count
);
9594 if (handler
->count
== 0)
9596 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
9597 "%016" PRIx64
" %" PRId64
"\n",
9598 op1
, op2
, op1
, op2
, handler
->oname
,
9599 handler
->count
, handler
->count
);
9603 if (handler
->count
== 0)
9605 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
9607 op1
, op1
, handler
->oname
,
9608 handler
->count
, handler
->count
);
9614 /*****************************************************************************/
9615 static inline void gen_intermediate_code_internal(CPUPPCState
*env
,
9616 TranslationBlock
*tb
,
9619 DisasContext ctx
, *ctxp
= &ctx
;
9620 opc_handler_t
**table
, *handler
;
9621 target_ulong pc_start
;
9622 uint16_t *gen_opc_end
;
9629 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
9632 ctx
.exception
= POWERPC_EXCP_NONE
;
9633 ctx
.spr_cb
= env
->spr_cb
;
9634 ctx
.mem_idx
= env
->mmu_idx
;
9635 ctx
.access_type
= -1;
9636 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
9637 #if defined(TARGET_PPC64)
9638 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
9639 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
9641 ctx
.fpu_enabled
= msr_fp
;
9642 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
9643 ctx
.spe_enabled
= msr_spe
;
9645 ctx
.spe_enabled
= 0;
9646 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
9647 ctx
.altivec_enabled
= msr_vr
;
9649 ctx
.altivec_enabled
= 0;
9650 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
9651 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
9653 ctx
.singlestep_enabled
= 0;
9654 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
9655 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
9656 if (unlikely(env
->singlestep_enabled
))
9657 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
9658 #if defined (DO_SINGLE_STEP) && 0
9659 /* Single step trace mode */
9663 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9665 max_insns
= CF_COUNT_MASK
;
9668 /* Set env in case of segfault during code fetch */
9669 while (ctx
.exception
== POWERPC_EXCP_NONE
9670 && tcg_ctx
.gen_opc_ptr
< gen_opc_end
) {
9671 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9672 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9673 if (bp
->pc
== ctx
.nip
) {
9674 gen_debug_exception(ctxp
);
9679 if (unlikely(search_pc
)) {
9680 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9684 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9686 tcg_ctx
.gen_opc_pc
[lj
] = ctx
.nip
;
9687 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
9688 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
9690 LOG_DISAS("----------------\n");
9691 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
9692 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
9693 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9695 if (unlikely(ctx
.le_mode
)) {
9696 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
9698 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
9700 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9701 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9702 opc3(ctx
.opcode
), ctx
.le_mode
? "little" : "big");
9703 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
9704 tcg_gen_debug_insn_start(ctx
.nip
);
9707 table
= env
->opcodes
;
9709 handler
= table
[opc1(ctx
.opcode
)];
9710 if (is_indirect_opcode(handler
)) {
9711 table
= ind_table(handler
);
9712 handler
= table
[opc2(ctx
.opcode
)];
9713 if (is_indirect_opcode(handler
)) {
9714 table
= ind_table(handler
);
9715 handler
= table
[opc3(ctx
.opcode
)];
9718 /* Is opcode *REALLY* valid ? */
9719 if (unlikely(handler
->handler
== &gen_invalid
)) {
9720 if (qemu_log_enabled()) {
9721 qemu_log("invalid/unsupported opcode: "
9722 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
9723 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9724 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
9729 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
9730 inval
= handler
->inval2
;
9732 inval
= handler
->inval1
;
9735 if (unlikely((ctx
.opcode
& inval
) != 0)) {
9736 if (qemu_log_enabled()) {
9737 qemu_log("invalid bits: %08x for opcode: "
9738 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
9739 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
9740 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
9741 ctx
.opcode
, ctx
.nip
- 4);
9743 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
9747 (*(handler
->handler
))(&ctx
);
9748 #if defined(DO_PPC_STATISTICS)
9751 /* Check trace mode exceptions */
9752 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
9753 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
9754 ctx
.exception
!= POWERPC_SYSCALL
&&
9755 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
9756 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
9757 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
9758 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
9759 (env
->singlestep_enabled
) ||
9761 num_insns
>= max_insns
)) {
9762 /* if we reach a page boundary or are single stepping, stop
9768 if (tb
->cflags
& CF_LAST_IO
)
9770 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
9771 gen_goto_tb(&ctx
, 0, ctx
.nip
);
9772 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
9773 if (unlikely(env
->singlestep_enabled
)) {
9774 gen_debug_exception(ctxp
);
9776 /* Generate the return instruction */
9779 gen_tb_end(tb
, num_insns
);
9780 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
9781 if (unlikely(search_pc
)) {
9782 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9785 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9787 tb
->size
= ctx
.nip
- pc_start
;
9788 tb
->icount
= num_insns
;
9790 #if defined(DEBUG_DISAS)
9791 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9793 flags
= env
->bfd_mach
;
9794 flags
|= ctx
.le_mode
<< 16;
9795 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9796 log_target_disas(env
, pc_start
, ctx
.nip
- pc_start
, flags
);
9802 void gen_intermediate_code (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9804 gen_intermediate_code_internal(env
, tb
, 0);
9807 void gen_intermediate_code_pc (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9809 gen_intermediate_code_internal(env
, tb
, 1);
9812 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
, int pc_pos
)
9814 env
->nip
= tcg_ctx
.gen_opc_pc
[pc_pos
];