4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
14 #include "internals.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/host-utils.h"
17 #include "qemu/main-loop.h"
18 #include "qemu/timer.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
35 #include "exec/cpu_ldst.h"
36 #include "semihosting/common-semi.h"
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
42 static void switch_mode(CPUARMState
*env
, int mode
);
44 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
46 assert(ri
->fieldoffset
);
47 if (cpreg_field_is_64bit(ri
)) {
48 return CPREG_FIELD64(env
, ri
);
50 return CPREG_FIELD32(env
, ri
);
54 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
57 assert(ri
->fieldoffset
);
58 if (cpreg_field_is_64bit(ri
)) {
59 CPREG_FIELD64(env
, ri
) = value
;
61 CPREG_FIELD32(env
, ri
) = value
;
65 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
67 return (char *)env
+ ri
->fieldoffset
;
70 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
72 /* Raw read of a coprocessor register (as needed for migration, etc). */
73 if (ri
->type
& ARM_CP_CONST
) {
74 return ri
->resetvalue
;
75 } else if (ri
->raw_readfn
) {
76 return ri
->raw_readfn(env
, ri
);
77 } else if (ri
->readfn
) {
78 return ri
->readfn(env
, ri
);
80 return raw_read(env
, ri
);
84 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 /* Raw write of a coprocessor register (as needed for migration, etc).
88 * Note that constant registers are treated as write-ignored; the
89 * caller should check for success by whether a readback gives the
92 if (ri
->type
& ARM_CP_CONST
) {
94 } else if (ri
->raw_writefn
) {
95 ri
->raw_writefn(env
, ri
, v
);
96 } else if (ri
->writefn
) {
97 ri
->writefn(env
, ri
, v
);
99 raw_write(env
, ri
, v
);
103 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
105 /* Return true if the regdef would cause an assertion if you called
106 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
107 * program bug for it not to have the NO_RAW flag).
108 * NB that returning false here doesn't necessarily mean that calling
109 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
110 * read/write access functions which are safe for raw use" from "has
111 * read/write access functions which have side effects but has forgotten
112 * to provide raw access functions".
113 * The tests here line up with the conditions in read/write_raw_cp_reg()
114 * and assertions in raw_read()/raw_write().
116 if ((ri
->type
& ARM_CP_CONST
) ||
118 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
124 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
126 /* Write the coprocessor state from cpu->env to the (index,value) list. */
130 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
131 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
132 const ARMCPRegInfo
*ri
;
135 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
140 if (ri
->type
& ARM_CP_NO_RAW
) {
144 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
147 * Only sync if the previous list->cpustate sync succeeded.
148 * Rather than tracking the success/failure state for every
149 * item in the list, we just recheck "does the raw write we must
150 * have made in write_list_to_cpustate() read back OK" here.
152 uint64_t oldval
= cpu
->cpreg_values
[i
];
154 if (oldval
== newval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
159 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
163 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
165 cpu
->cpreg_values
[i
] = newval
;
170 bool write_list_to_cpustate(ARMCPU
*cpu
)
175 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
176 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
177 uint64_t v
= cpu
->cpreg_values
[i
];
178 const ARMCPRegInfo
*ri
;
180 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
185 if (ri
->type
& ARM_CP_NO_RAW
) {
188 /* Write value and confirm it reads back as written
189 * (to catch read-only registers and partially read-only
190 * registers where the incoming migration value doesn't match)
192 write_raw_cp_reg(&cpu
->env
, ri
, v
);
193 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
200 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
202 ARMCPU
*cpu
= opaque
;
203 uint32_t regidx
= (uintptr_t)key
;
204 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
206 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
207 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
208 /* The value array need not be initialized at this point */
209 cpu
->cpreg_array_len
++;
213 static void count_cpreg(gpointer key
, gpointer opaque
)
215 ARMCPU
*cpu
= opaque
;
216 const ARMCPRegInfo
*ri
;
218 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
220 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
221 cpu
->cpreg_array_len
++;
225 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
227 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
228 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
239 void init_cpreg_list(ARMCPU
*cpu
)
241 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
242 * Note that we require cpreg_tuples[] to be sorted by key ID.
247 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
248 keys
= g_list_sort(keys
, cpreg_key_compare
);
250 cpu
->cpreg_array_len
= 0;
252 g_list_foreach(keys
, count_cpreg
, cpu
);
254 arraylen
= cpu
->cpreg_array_len
;
255 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
257 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
258 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
259 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
260 cpu
->cpreg_array_len
= 0;
262 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
264 assert(cpu
->cpreg_array_len
== arraylen
);
270 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
272 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
273 const ARMCPRegInfo
*ri
,
276 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
277 arm_is_secure_below_el3(env
)) {
278 return CP_ACCESS_TRAP_UNCATEGORIZED
;
283 /* Some secure-only AArch32 registers trap to EL3 if used from
284 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
285 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
286 * We assume that the .access field is set to PL1_RW.
288 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
289 const ARMCPRegInfo
*ri
,
292 if (arm_current_el(env
) == 3) {
295 if (arm_is_secure_below_el3(env
)) {
296 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
297 return CP_ACCESS_TRAP_EL2
;
299 return CP_ACCESS_TRAP_EL3
;
301 /* This will be EL1 NS and EL2 NS, which just UNDEF */
302 return CP_ACCESS_TRAP_UNCATEGORIZED
;
305 static uint64_t arm_mdcr_el2_eff(CPUARMState
*env
)
307 return arm_is_el2_enabled(env
) ? env
->cp15
.mdcr_el2
: 0;
310 /* Check for traps to "powerdown debug" registers, which are controlled
313 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
316 int el
= arm_current_el(env
);
317 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
318 bool mdcr_el2_tdosa
= (mdcr_el2
& MDCR_TDOSA
) || (mdcr_el2
& MDCR_TDE
) ||
319 (arm_hcr_el2_eff(env
) & HCR_TGE
);
321 if (el
< 2 && mdcr_el2_tdosa
) {
322 return CP_ACCESS_TRAP_EL2
;
324 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
325 return CP_ACCESS_TRAP_EL3
;
330 /* Check for traps to "debug ROM" registers, which are controlled
331 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
333 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
336 int el
= arm_current_el(env
);
337 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
338 bool mdcr_el2_tdra
= (mdcr_el2
& MDCR_TDRA
) || (mdcr_el2
& MDCR_TDE
) ||
339 (arm_hcr_el2_eff(env
) & HCR_TGE
);
341 if (el
< 2 && mdcr_el2_tdra
) {
342 return CP_ACCESS_TRAP_EL2
;
344 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
345 return CP_ACCESS_TRAP_EL3
;
350 /* Check for traps to general debug registers, which are controlled
351 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
353 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
356 int el
= arm_current_el(env
);
357 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
358 bool mdcr_el2_tda
= (mdcr_el2
& MDCR_TDA
) || (mdcr_el2
& MDCR_TDE
) ||
359 (arm_hcr_el2_eff(env
) & HCR_TGE
);
361 if (el
< 2 && mdcr_el2_tda
) {
362 return CP_ACCESS_TRAP_EL2
;
364 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
365 return CP_ACCESS_TRAP_EL3
;
370 /* Check for traps to performance monitor registers, which are controlled
371 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
373 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
376 int el
= arm_current_el(env
);
377 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
379 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
380 return CP_ACCESS_TRAP_EL2
;
382 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
383 return CP_ACCESS_TRAP_EL3
;
388 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
389 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
392 if (arm_current_el(env
) == 1) {
393 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
394 if (arm_hcr_el2_eff(env
) & trap
) {
395 return CP_ACCESS_TRAP_EL2
;
401 /* Check for traps from EL1 due to HCR_EL2.TSW. */
402 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
405 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
406 return CP_ACCESS_TRAP_EL2
;
411 /* Check for traps from EL1 due to HCR_EL2.TACR. */
412 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
415 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
416 return CP_ACCESS_TRAP_EL2
;
421 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
422 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
425 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
426 return CP_ACCESS_TRAP_EL2
;
431 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
433 ARMCPU
*cpu
= env_archcpu(env
);
435 raw_write(env
, ri
, value
);
436 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
439 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
441 ARMCPU
*cpu
= env_archcpu(env
);
443 if (raw_read(env
, ri
) != value
) {
444 /* Unlike real hardware the qemu TLB uses virtual addresses,
445 * not modified virtual addresses, so this causes a TLB flush.
448 raw_write(env
, ri
, value
);
452 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 ARMCPU
*cpu
= env_archcpu(env
);
457 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
458 && !extended_addresses_enabled(env
)) {
459 /* For VMSA (when not using the LPAE long descriptor page table
460 * format) this register includes the ASID, so do a TLB flush.
461 * For PMSA it is purely a process ID and no action is needed.
465 raw_write(env
, ri
, value
);
468 /* IS variants of TLB operations must affect all cores */
469 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
472 CPUState
*cs
= env_cpu(env
);
474 tlb_flush_all_cpus_synced(cs
);
477 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
480 CPUState
*cs
= env_cpu(env
);
482 tlb_flush_all_cpus_synced(cs
);
485 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 CPUState
*cs
= env_cpu(env
);
490 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
493 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
496 CPUState
*cs
= env_cpu(env
);
498 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
502 * Non-IS variants of TLB operations are upgraded to
503 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
504 * force broadcast of these operations.
506 static bool tlb_force_broadcast(CPUARMState
*env
)
508 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
511 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
514 /* Invalidate all (TLBIALL) */
515 CPUState
*cs
= env_cpu(env
);
517 if (tlb_force_broadcast(env
)) {
518 tlb_flush_all_cpus_synced(cs
);
524 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
527 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
528 CPUState
*cs
= env_cpu(env
);
530 value
&= TARGET_PAGE_MASK
;
531 if (tlb_force_broadcast(env
)) {
532 tlb_flush_page_all_cpus_synced(cs
, value
);
534 tlb_flush_page(cs
, value
);
538 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 /* Invalidate by ASID (TLBIASID) */
542 CPUState
*cs
= env_cpu(env
);
544 if (tlb_force_broadcast(env
)) {
545 tlb_flush_all_cpus_synced(cs
);
551 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
554 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
555 CPUState
*cs
= env_cpu(env
);
557 value
&= TARGET_PAGE_MASK
;
558 if (tlb_force_broadcast(env
)) {
559 tlb_flush_page_all_cpus_synced(cs
, value
);
561 tlb_flush_page(cs
, value
);
565 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= env_cpu(env
);
570 tlb_flush_by_mmuidx(cs
,
572 ARMMMUIdxBit_E10_1_PAN
|
576 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
579 CPUState
*cs
= env_cpu(env
);
581 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
583 ARMMMUIdxBit_E10_1_PAN
|
588 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
591 CPUState
*cs
= env_cpu(env
);
593 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
596 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
599 CPUState
*cs
= env_cpu(env
);
601 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
604 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 CPUState
*cs
= env_cpu(env
);
608 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
610 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
613 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 CPUState
*cs
= env_cpu(env
);
617 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
619 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
623 static const ARMCPRegInfo cp_reginfo
[] = {
624 /* Define the secure and non-secure FCSE identifier CP registers
625 * separately because there is no secure bank in V8 (no _EL3). This allows
626 * the secure register to be properly reset and migrated. There is also no
627 * v8 EL1 version of the register so the non-secure instance stands alone.
630 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
631 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
633 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
634 { .name
= "FCSEIDR_S",
635 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
636 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
637 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
638 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
639 /* Define the secure and non-secure context identifier CP registers
640 * separately because there is no secure bank in V8 (no _EL3). This allows
641 * the secure register to be properly reset and migrated. In the
642 * non-secure case, the 32-bit register will have reset and migration
643 * disabled during registration as it is handled by the 64-bit instance.
645 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
646 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
647 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
648 .secure
= ARM_CP_SECSTATE_NS
,
649 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
650 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
651 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
652 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
653 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
654 .secure
= ARM_CP_SECSTATE_S
,
655 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
656 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
659 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
660 /* NB: Some of these registers exist in v8 but with more precise
661 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
663 /* MMU Domain access control / MPU write buffer control */
665 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
666 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
667 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
668 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
669 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
670 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
671 * For v6 and v5, these mappings are overly broad.
673 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
674 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
675 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
676 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
677 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
678 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
679 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
680 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
681 /* Cache maintenance ops; some of this space may be overridden later. */
682 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
683 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
684 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
687 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
688 /* Not all pre-v6 cores implemented this WFI, so this is slightly
691 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
692 .access
= PL1_W
, .type
= ARM_CP_WFI
},
695 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
696 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
697 * is UNPREDICTABLE; we choose to NOP as most implementations do).
699 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
700 .access
= PL1_W
, .type
= ARM_CP_WFI
},
701 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
702 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
703 * OMAPCP will override this space.
705 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
706 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
708 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
709 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
711 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
712 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
713 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
715 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
716 * implementing it as RAZ means the "debug architecture version" bits
717 * will read as a reserved value, which should cause Linux to not try
718 * to use the debug hardware.
720 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
721 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
722 /* MMU TLB control. Note that the wildcarding means we cover not just
723 * the unified TLB ops but also the dside/iside/inner-shareable variants.
725 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
726 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
727 .type
= ARM_CP_NO_RAW
},
728 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
729 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
730 .type
= ARM_CP_NO_RAW
},
731 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
732 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
733 .type
= ARM_CP_NO_RAW
},
734 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
735 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
736 .type
= ARM_CP_NO_RAW
},
737 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
738 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
739 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
740 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
743 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
748 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
749 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
750 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
751 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
752 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
754 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
755 /* VFP coprocessor: cp10 & cp11 [23:20] */
756 mask
|= R_CPACR_ASEDIS_MASK
|
757 R_CPACR_D32DIS_MASK
|
761 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
762 /* ASEDIS [31] bit is RAO/WI */
763 value
|= R_CPACR_ASEDIS_MASK
;
766 /* VFPv3 and upwards with NEON implement 32 double precision
767 * registers (D0-D31).
769 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
770 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
771 value
|= R_CPACR_D32DIS_MASK
;
778 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
779 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
781 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
782 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
783 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
784 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
787 env
->cp15
.cpacr_el1
= value
;
790 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
793 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
794 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
796 uint64_t value
= env
->cp15
.cpacr_el1
;
798 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
799 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
800 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
806 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
808 /* Call cpacr_write() so that we reset with the correct RAO bits set
809 * for our CPU features.
811 cpacr_write(env
, ri
, 0);
814 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 if (arm_feature(env
, ARM_FEATURE_V8
)) {
818 /* Check if CPACR accesses are to be trapped to EL2 */
819 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
820 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
821 return CP_ACCESS_TRAP_EL2
;
822 /* Check if CPACR accesses are to be trapped to EL3 */
823 } else if (arm_current_el(env
) < 3 &&
824 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
825 return CP_ACCESS_TRAP_EL3
;
832 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 /* Check if CPTR accesses are set to trap to EL3 */
836 if (arm_current_el(env
) == 2 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
844 static const ARMCPRegInfo v6_cp_reginfo
[] = {
845 /* prefetch by MVA in v6, NOP in v7 */
846 { .name
= "MVA_prefetch",
847 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
849 /* We need to break the TB after ISB to execute self-modifying code
850 * correctly and also to take any pending interrupts immediately.
851 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
853 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
854 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
855 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
856 .access
= PL0_W
, .type
= ARM_CP_NOP
},
857 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
858 .access
= PL0_W
, .type
= ARM_CP_NOP
},
859 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
860 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
861 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
862 offsetof(CPUARMState
, cp15
.ifar_ns
) },
864 /* Watchpoint Fault Address Register : should actually only be present
865 * for 1136, 1176, 11MPCore.
867 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
868 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
869 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
870 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
871 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
872 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
875 typedef struct pm_event
{
876 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
877 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
878 bool (*supported
)(CPUARMState
*);
880 * Retrieve the current count of the underlying event. The programmed
881 * counters hold a difference from the return value from this function
883 uint64_t (*get_count
)(CPUARMState
*);
885 * Return how many nanoseconds it will take (at a minimum) for count events
886 * to occur. A negative value indicates the counter will never overflow, or
887 * that the counter has otherwise arranged for the overflow bit to be set
888 * and the PMU interrupt to be raised on overflow.
890 int64_t (*ns_per_count
)(uint64_t);
893 static bool event_always_supported(CPUARMState
*env
)
898 static uint64_t swinc_get_count(CPUARMState
*env
)
901 * SW_INCR events are written directly to the pmevcntr's by writes to
902 * PMSWINC, so there is no underlying count maintained by the PMU itself
907 static int64_t swinc_ns_per(uint64_t ignored
)
913 * Return the underlying cycle count for the PMU cycle counters. If we're in
914 * usermode, simply return 0.
916 static uint64_t cycles_get_count(CPUARMState
*env
)
918 #ifndef CONFIG_USER_ONLY
919 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
920 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
922 return cpu_get_host_ticks();
926 #ifndef CONFIG_USER_ONLY
927 static int64_t cycles_ns_per(uint64_t cycles
)
929 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
932 static bool instructions_supported(CPUARMState
*env
)
934 return icount_enabled() == 1; /* Precise instruction counting */
937 static uint64_t instructions_get_count(CPUARMState
*env
)
939 return (uint64_t)icount_get_raw();
942 static int64_t instructions_ns_per(uint64_t icount
)
944 return icount_to_ns((int64_t)icount
);
948 static bool pmu_8_1_events_supported(CPUARMState
*env
)
950 /* For events which are supported in any v8.1 PMU */
951 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
954 static bool pmu_8_4_events_supported(CPUARMState
*env
)
956 /* For events which are supported in any v8.1 PMU */
957 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
960 static uint64_t zero_event_get_count(CPUARMState
*env
)
962 /* For events which on QEMU never fire, so their count is always zero */
966 static int64_t zero_event_ns_per(uint64_t cycles
)
968 /* An event which never fires can never overflow */
972 static const pm_event pm_events
[] = {
973 { .number
= 0x000, /* SW_INCR */
974 .supported
= event_always_supported
,
975 .get_count
= swinc_get_count
,
976 .ns_per_count
= swinc_ns_per
,
978 #ifndef CONFIG_USER_ONLY
979 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
980 .supported
= instructions_supported
,
981 .get_count
= instructions_get_count
,
982 .ns_per_count
= instructions_ns_per
,
984 { .number
= 0x011, /* CPU_CYCLES, Cycle */
985 .supported
= event_always_supported
,
986 .get_count
= cycles_get_count
,
987 .ns_per_count
= cycles_ns_per
,
990 { .number
= 0x023, /* STALL_FRONTEND */
991 .supported
= pmu_8_1_events_supported
,
992 .get_count
= zero_event_get_count
,
993 .ns_per_count
= zero_event_ns_per
,
995 { .number
= 0x024, /* STALL_BACKEND */
996 .supported
= pmu_8_1_events_supported
,
997 .get_count
= zero_event_get_count
,
998 .ns_per_count
= zero_event_ns_per
,
1000 { .number
= 0x03c, /* STALL */
1001 .supported
= pmu_8_4_events_supported
,
1002 .get_count
= zero_event_get_count
,
1003 .ns_per_count
= zero_event_ns_per
,
1008 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1009 * events (i.e. the statistical profiling extension), this implementation
1010 * should first be updated to something sparse instead of the current
1011 * supported_event_map[] array.
1013 #define MAX_EVENT_ID 0x3c
1014 #define UNSUPPORTED_EVENT UINT16_MAX
1015 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1018 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1019 * of ARM event numbers to indices in our pm_events array.
1021 * Note: Events in the 0x40XX range are not currently supported.
1023 void pmu_init(ARMCPU
*cpu
)
1028 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1031 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1032 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1037 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1038 const pm_event
*cnt
= &pm_events
[i
];
1039 assert(cnt
->number
<= MAX_EVENT_ID
);
1040 /* We do not currently support events in the 0x40xx range */
1041 assert(cnt
->number
<= 0x3f);
1043 if (cnt
->supported(&cpu
->env
)) {
1044 supported_event_map
[cnt
->number
] = i
;
1045 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1046 if (cnt
->number
& 0x20) {
1047 cpu
->pmceid1
|= event_mask
;
1049 cpu
->pmceid0
|= event_mask
;
1056 * Check at runtime whether a PMU event is supported for the current machine
1058 static bool event_supported(uint16_t number
)
1060 if (number
> MAX_EVENT_ID
) {
1063 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1066 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1069 /* Performance monitor registers user accessibility is controlled
1070 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1071 * trapping to EL2 or EL3 for other accesses.
1073 int el
= arm_current_el(env
);
1074 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1076 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1077 return CP_ACCESS_TRAP
;
1079 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1080 return CP_ACCESS_TRAP_EL2
;
1082 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1083 return CP_ACCESS_TRAP_EL3
;
1086 return CP_ACCESS_OK
;
1089 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1090 const ARMCPRegInfo
*ri
,
1093 /* ER: event counter read trap control */
1094 if (arm_feature(env
, ARM_FEATURE_V8
)
1095 && arm_current_el(env
) == 0
1096 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1098 return CP_ACCESS_OK
;
1101 return pmreg_access(env
, ri
, isread
);
1104 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1105 const ARMCPRegInfo
*ri
,
1108 /* SW: software increment write trap control */
1109 if (arm_feature(env
, ARM_FEATURE_V8
)
1110 && arm_current_el(env
) == 0
1111 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1113 return CP_ACCESS_OK
;
1116 return pmreg_access(env
, ri
, isread
);
1119 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1120 const ARMCPRegInfo
*ri
,
1123 /* ER: event counter read trap control */
1124 if (arm_feature(env
, ARM_FEATURE_V8
)
1125 && arm_current_el(env
) == 0
1126 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1127 return CP_ACCESS_OK
;
1130 return pmreg_access(env
, ri
, isread
);
1133 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1134 const ARMCPRegInfo
*ri
,
1137 /* CR: cycle counter read trap control */
1138 if (arm_feature(env
, ARM_FEATURE_V8
)
1139 && arm_current_el(env
) == 0
1140 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1142 return CP_ACCESS_OK
;
1145 return pmreg_access(env
, ri
, isread
);
1148 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1149 * the current EL, security state, and register configuration.
1151 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1154 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1155 bool enabled
, prohibited
, filtered
;
1156 bool secure
= arm_is_secure(env
);
1157 int el
= arm_current_el(env
);
1158 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1159 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1161 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1165 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1166 (counter
< hpmn
|| counter
== 31)) {
1167 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1169 e
= mdcr_el2
& MDCR_HPME
;
1171 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1174 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1175 prohibited
= mdcr_el2
& MDCR_HPMD
;
1180 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1181 !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1184 if (prohibited
&& counter
== 31) {
1185 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1188 if (counter
== 31) {
1189 filter
= env
->cp15
.pmccfiltr_el0
;
1191 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1194 p
= filter
& PMXEVTYPER_P
;
1195 u
= filter
& PMXEVTYPER_U
;
1196 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1197 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1198 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1199 m
= arm_el_is_aa64(env
, 1) &&
1200 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1203 filtered
= secure
? u
: u
!= nsu
;
1204 } else if (el
== 1) {
1205 filtered
= secure
? p
: p
!= nsk
;
1206 } else if (el
== 2) {
1212 if (counter
!= 31) {
1214 * If not checking PMCCNTR, ensure the counter is setup to an event we
1217 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1218 if (!event_supported(event
)) {
1223 return enabled
&& !prohibited
&& !filtered
;
1226 static void pmu_update_irq(CPUARMState
*env
)
1228 ARMCPU
*cpu
= env_archcpu(env
);
1229 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1230 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1234 * Ensure c15_ccnt is the guest-visible count so that operations such as
1235 * enabling/disabling the counter or filtering, modifying the count itself,
1236 * etc. can be done logically. This is essentially a no-op if the counter is
1237 * not enabled at the time of the call.
1239 static void pmccntr_op_start(CPUARMState
*env
)
1241 uint64_t cycles
= cycles_get_count(env
);
1243 if (pmu_counter_enabled(env
, 31)) {
1244 uint64_t eff_cycles
= cycles
;
1245 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1246 /* Increment once every 64 processor clock cycles */
1250 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1252 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1253 1ull << 63 : 1ull << 31;
1254 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1255 env
->cp15
.c9_pmovsr
|= (1 << 31);
1256 pmu_update_irq(env
);
1259 env
->cp15
.c15_ccnt
= new_pmccntr
;
1261 env
->cp15
.c15_ccnt_delta
= cycles
;
1265 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1266 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1269 static void pmccntr_op_finish(CPUARMState
*env
)
1271 if (pmu_counter_enabled(env
, 31)) {
1272 #ifndef CONFIG_USER_ONLY
1273 /* Calculate when the counter will next overflow */
1274 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1275 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1276 remaining_cycles
= (uint32_t)remaining_cycles
;
1278 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1280 if (overflow_in
> 0) {
1281 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1283 ARMCPU
*cpu
= env_archcpu(env
);
1284 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1288 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1289 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1290 /* Increment once every 64 processor clock cycles */
1293 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1297 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1300 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1302 if (event_supported(event
)) {
1303 uint16_t event_idx
= supported_event_map
[event
];
1304 count
= pm_events
[event_idx
].get_count(env
);
1307 if (pmu_counter_enabled(env
, counter
)) {
1308 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1310 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1311 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1312 pmu_update_irq(env
);
1314 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1316 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1319 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1321 if (pmu_counter_enabled(env
, counter
)) {
1322 #ifndef CONFIG_USER_ONLY
1323 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1324 uint16_t event_idx
= supported_event_map
[event
];
1325 uint64_t delta
= UINT32_MAX
-
1326 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1327 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1329 if (overflow_in
> 0) {
1330 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1332 ARMCPU
*cpu
= env_archcpu(env
);
1333 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1337 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1338 env
->cp15
.c14_pmevcntr
[counter
];
1342 void pmu_op_start(CPUARMState
*env
)
1345 pmccntr_op_start(env
);
1346 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1347 pmevcntr_op_start(env
, i
);
1351 void pmu_op_finish(CPUARMState
*env
)
1354 pmccntr_op_finish(env
);
1355 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1356 pmevcntr_op_finish(env
, i
);
1360 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1362 pmu_op_start(&cpu
->env
);
1365 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1367 pmu_op_finish(&cpu
->env
);
1370 void arm_pmu_timer_cb(void *opaque
)
1372 ARMCPU
*cpu
= opaque
;
1375 * Update all the counter values based on the current underlying counts,
1376 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1377 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1378 * counter may expire.
1380 pmu_op_start(&cpu
->env
);
1381 pmu_op_finish(&cpu
->env
);
1384 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1389 if (value
& PMCRC
) {
1390 /* The counter has been reset */
1391 env
->cp15
.c15_ccnt
= 0;
1394 if (value
& PMCRP
) {
1396 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1397 env
->cp15
.c14_pmevcntr
[i
] = 0;
1401 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1402 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1407 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1411 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1412 /* Increment a counter's count iff: */
1413 if ((value
& (1 << i
)) && /* counter's bit is set */
1414 /* counter is enabled and not filtered */
1415 pmu_counter_enabled(env
, i
) &&
1416 /* counter is SW_INCR */
1417 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1418 pmevcntr_op_start(env
, i
);
1421 * Detect if this write causes an overflow since we can't predict
1422 * PMSWINC overflows like we can for other events
1424 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1426 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1427 env
->cp15
.c9_pmovsr
|= (1 << i
);
1428 pmu_update_irq(env
);
1431 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1433 pmevcntr_op_finish(env
, i
);
1438 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1441 pmccntr_op_start(env
);
1442 ret
= env
->cp15
.c15_ccnt
;
1443 pmccntr_op_finish(env
);
1447 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1450 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1451 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1452 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1455 env
->cp15
.c9_pmselr
= value
& 0x1f;
1458 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1461 pmccntr_op_start(env
);
1462 env
->cp15
.c15_ccnt
= value
;
1463 pmccntr_op_finish(env
);
1466 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1469 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1471 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1474 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1477 pmccntr_op_start(env
);
1478 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1479 pmccntr_op_finish(env
);
1482 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1485 pmccntr_op_start(env
);
1486 /* M is not accessible from AArch32 */
1487 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1488 (value
& PMCCFILTR
);
1489 pmccntr_op_finish(env
);
1492 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1494 /* M is not visible in AArch32 */
1495 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1498 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1501 value
&= pmu_counter_mask(env
);
1502 env
->cp15
.c9_pmcnten
|= value
;
1505 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1508 value
&= pmu_counter_mask(env
);
1509 env
->cp15
.c9_pmcnten
&= ~value
;
1512 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1515 value
&= pmu_counter_mask(env
);
1516 env
->cp15
.c9_pmovsr
&= ~value
;
1517 pmu_update_irq(env
);
1520 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1523 value
&= pmu_counter_mask(env
);
1524 env
->cp15
.c9_pmovsr
|= value
;
1525 pmu_update_irq(env
);
1528 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1529 uint64_t value
, const uint8_t counter
)
1531 if (counter
== 31) {
1532 pmccfiltr_write(env
, ri
, value
);
1533 } else if (counter
< pmu_num_counters(env
)) {
1534 pmevcntr_op_start(env
, counter
);
1537 * If this counter's event type is changing, store the current
1538 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1539 * pmevcntr_op_finish has the correct baseline when it converts back to
1542 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1543 PMXEVTYPER_EVTCOUNT
;
1544 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1545 if (old_event
!= new_event
) {
1547 if (event_supported(new_event
)) {
1548 uint16_t event_idx
= supported_event_map
[new_event
];
1549 count
= pm_events
[event_idx
].get_count(env
);
1551 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1554 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1555 pmevcntr_op_finish(env
, counter
);
1557 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1558 * PMSELR value is equal to or greater than the number of implemented
1559 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1563 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1564 const uint8_t counter
)
1566 if (counter
== 31) {
1567 return env
->cp15
.pmccfiltr_el0
;
1568 } else if (counter
< pmu_num_counters(env
)) {
1569 return env
->cp15
.c14_pmevtyper
[counter
];
1572 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1573 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1579 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1582 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1583 pmevtyper_write(env
, ri
, value
, counter
);
1586 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1589 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1590 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1593 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1594 * pmu_op_finish calls when loading saved state for a migration. Because
1595 * we're potentially updating the type of event here, the value written to
1596 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1597 * different counter type. Therefore, we need to set this value to the
1598 * current count for the counter type we're writing so that pmu_op_finish
1599 * has the correct count for its calculation.
1601 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1602 if (event_supported(event
)) {
1603 uint16_t event_idx
= supported_event_map
[event
];
1604 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1605 pm_events
[event_idx
].get_count(env
);
1609 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1611 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1612 return pmevtyper_read(env
, ri
, counter
);
1615 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1618 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1621 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1623 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1626 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1627 uint64_t value
, uint8_t counter
)
1629 if (counter
< pmu_num_counters(env
)) {
1630 pmevcntr_op_start(env
, counter
);
1631 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1632 pmevcntr_op_finish(env
, counter
);
1635 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1636 * are CONSTRAINED UNPREDICTABLE.
1640 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1643 if (counter
< pmu_num_counters(env
)) {
1645 pmevcntr_op_start(env
, counter
);
1646 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1647 pmevcntr_op_finish(env
, counter
);
1650 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1651 * are CONSTRAINED UNPREDICTABLE. */
1656 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1659 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1660 pmevcntr_write(env
, ri
, value
, counter
);
1663 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1665 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1666 return pmevcntr_read(env
, ri
, counter
);
1669 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1672 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1673 assert(counter
< pmu_num_counters(env
));
1674 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1675 pmevcntr_write(env
, ri
, value
, counter
);
1678 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1680 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1681 assert(counter
< pmu_num_counters(env
));
1682 return env
->cp15
.c14_pmevcntr
[counter
];
1685 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1688 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1691 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1693 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1696 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1699 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1700 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1702 env
->cp15
.c9_pmuserenr
= value
& 1;
1706 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 /* We have no event counters so only the C bit can be changed */
1710 value
&= pmu_counter_mask(env
);
1711 env
->cp15
.c9_pminten
|= value
;
1712 pmu_update_irq(env
);
1715 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1718 value
&= pmu_counter_mask(env
);
1719 env
->cp15
.c9_pminten
&= ~value
;
1720 pmu_update_irq(env
);
1723 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1726 /* Note that even though the AArch64 view of this register has bits
1727 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1728 * architectural requirements for bits which are RES0 only in some
1729 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1730 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1732 raw_write(env
, ri
, value
& ~0x1FULL
);
1735 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1737 /* Begin with base v8.0 state. */
1738 uint32_t valid_mask
= 0x3fff;
1739 ARMCPU
*cpu
= env_archcpu(env
);
1741 if (ri
->state
== ARM_CP_STATE_AA64
) {
1742 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1743 !cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
1744 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1746 valid_mask
&= ~SCR_NET
;
1748 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1749 valid_mask
|= SCR_TERR
;
1751 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1752 valid_mask
|= SCR_TLOR
;
1754 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1755 valid_mask
|= SCR_API
| SCR_APK
;
1757 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1758 valid_mask
|= SCR_EEL2
;
1760 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1761 valid_mask
|= SCR_ATA
;
1763 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1764 valid_mask
|= SCR_ENSCXT
;
1766 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1767 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1770 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1771 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1772 valid_mask
|= SCR_TERR
;
1776 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1777 valid_mask
&= ~SCR_HCE
;
1779 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1780 * supported if EL2 exists. The bit is UNK/SBZP when
1781 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1782 * when EL2 is unavailable.
1783 * On ARMv8, this bit is always available.
1785 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1786 !arm_feature(env
, ARM_FEATURE_V8
)) {
1787 valid_mask
&= ~SCR_SMD
;
1791 /* Clear all-context RES0 bits. */
1792 value
&= valid_mask
;
1793 raw_write(env
, ri
, value
);
1796 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1799 * scr_write will set the RES1 bits on an AArch64-only CPU.
1800 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1802 scr_write(env
, ri
, 0);
1805 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1806 const ARMCPRegInfo
*ri
,
1809 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1810 return CP_ACCESS_TRAP_EL2
;
1813 return CP_ACCESS_OK
;
1816 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1818 ARMCPU
*cpu
= env_archcpu(env
);
1820 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1823 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1824 ri
->secure
& ARM_CP_SECSTATE_S
);
1826 return cpu
->ccsidr
[index
];
1829 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1832 raw_write(env
, ri
, value
& 0xf);
1835 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1837 CPUState
*cs
= env_cpu(env
);
1838 bool el1
= arm_current_el(env
) == 1;
1839 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1842 if (hcr_el2
& HCR_IMO
) {
1843 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1847 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1852 if (hcr_el2
& HCR_FMO
) {
1853 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1857 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1862 if (hcr_el2
& HCR_AMO
) {
1863 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1871 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1874 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1875 return CP_ACCESS_TRAP_EL2
;
1878 return CP_ACCESS_OK
;
1881 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1884 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1885 return access_aa64_tid1(env
, ri
, isread
);
1888 return CP_ACCESS_OK
;
1891 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1892 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1893 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1894 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1895 /* Performance monitors are implementation defined in v7,
1896 * but with an ARM recommended set of registers, which we
1899 * Performance registers fall into three categories:
1900 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1901 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1902 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1903 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1904 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1906 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1907 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1908 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1909 .writefn
= pmcntenset_write
,
1910 .accessfn
= pmreg_access
,
1911 .raw_writefn
= raw_write
},
1912 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1913 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1914 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1915 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1916 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1917 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1919 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1920 .accessfn
= pmreg_access
,
1921 .writefn
= pmcntenclr_write
,
1922 .type
= ARM_CP_ALIAS
},
1923 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1924 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1925 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1926 .type
= ARM_CP_ALIAS
,
1927 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1928 .writefn
= pmcntenclr_write
},
1929 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1930 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1931 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1932 .accessfn
= pmreg_access
,
1933 .writefn
= pmovsr_write
,
1934 .raw_writefn
= raw_write
},
1935 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1936 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1937 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1938 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1939 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1940 .writefn
= pmovsr_write
,
1941 .raw_writefn
= raw_write
},
1942 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1943 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1944 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1945 .writefn
= pmswinc_write
},
1946 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
1947 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
1948 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1949 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1950 .writefn
= pmswinc_write
},
1951 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1952 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1953 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1954 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1955 .raw_writefn
= raw_write
},
1956 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1957 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1958 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1959 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1960 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1961 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1962 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1963 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1964 .accessfn
= pmreg_access_ccntr
},
1965 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1966 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1967 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1969 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
1970 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
1971 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
1972 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
1973 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
1974 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1975 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1977 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1978 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1979 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
1980 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1982 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1984 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1985 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1986 .accessfn
= pmreg_access
,
1987 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1988 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1989 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1990 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1991 .accessfn
= pmreg_access
,
1992 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1993 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1994 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1995 .accessfn
= pmreg_access_xevcntr
,
1996 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
1997 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1998 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
1999 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2000 .accessfn
= pmreg_access_xevcntr
,
2001 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2002 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2003 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2004 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2006 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2007 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2008 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2009 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2010 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2012 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2013 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2014 .access
= PL1_RW
, .accessfn
= access_tpm
,
2015 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2016 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2018 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2019 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2020 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2021 .access
= PL1_RW
, .accessfn
= access_tpm
,
2023 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2024 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2025 .resetvalue
= 0x0 },
2026 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2027 .access
= PL1_RW
, .accessfn
= access_tpm
,
2028 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2029 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2030 .writefn
= pmintenclr_write
, },
2031 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2032 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2033 .access
= PL1_RW
, .accessfn
= access_tpm
,
2034 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2035 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2036 .writefn
= pmintenclr_write
},
2037 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2038 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2040 .accessfn
= access_aa64_tid2
,
2041 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2042 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2043 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2045 .accessfn
= access_aa64_tid2
,
2046 .writefn
= csselr_write
, .resetvalue
= 0,
2047 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2048 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2049 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2050 * just RAZ for all cores:
2052 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2053 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2054 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2055 .accessfn
= access_aa64_tid1
,
2057 /* Auxiliary fault status registers: these also are IMPDEF, and we
2058 * choose to RAZ/WI for all cores.
2060 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2061 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2062 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2063 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2064 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2065 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2066 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2067 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2068 /* MAIR can just read-as-written because we don't implement caches
2069 * and so don't need to care about memory attributes.
2071 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2072 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2073 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2074 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2076 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2077 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2078 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2080 /* For non-long-descriptor page tables these are PRRR and NMRR;
2081 * regardless they still act as reads-as-written for QEMU.
2083 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2084 * allows them to assign the correct fieldoffset based on the endianness
2085 * handled in the field definitions.
2087 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2088 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2089 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2090 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2091 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2092 .resetfn
= arm_cp_reset_ignore
},
2093 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2094 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2095 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2096 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2097 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2098 .resetfn
= arm_cp_reset_ignore
},
2099 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2100 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2101 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2102 /* 32 bit ITLB invalidates */
2103 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2104 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2105 .writefn
= tlbiall_write
},
2106 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2107 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2108 .writefn
= tlbimva_write
},
2109 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2110 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2111 .writefn
= tlbiasid_write
},
2112 /* 32 bit DTLB invalidates */
2113 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2114 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2115 .writefn
= tlbiall_write
},
2116 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2117 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2118 .writefn
= tlbimva_write
},
2119 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2120 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2121 .writefn
= tlbiasid_write
},
2122 /* 32 bit TLB invalidates */
2123 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2124 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2125 .writefn
= tlbiall_write
},
2126 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2127 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2128 .writefn
= tlbimva_write
},
2129 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2130 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2131 .writefn
= tlbiasid_write
},
2132 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2133 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2134 .writefn
= tlbimvaa_write
},
2137 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2138 /* 32 bit TLB invalidates, Inner Shareable */
2139 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2140 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2141 .writefn
= tlbiall_is_write
},
2142 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2143 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2144 .writefn
= tlbimva_is_write
},
2145 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2146 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2147 .writefn
= tlbiasid_is_write
},
2148 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2149 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2150 .writefn
= tlbimvaa_is_write
},
2153 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2154 /* PMOVSSET is not implemented in v7 before v7ve */
2155 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2156 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2157 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2158 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2159 .writefn
= pmovsset_write
,
2160 .raw_writefn
= raw_write
},
2161 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2162 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2163 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2164 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2165 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2166 .writefn
= pmovsset_write
,
2167 .raw_writefn
= raw_write
},
2170 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2177 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2181 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2182 * at all, so we don't need to check whether we're v8A.
2184 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2185 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2186 return CP_ACCESS_TRAP_EL2
;
2188 return CP_ACCESS_OK
;
2191 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2194 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2195 return CP_ACCESS_TRAP
;
2197 return teecr_access(env
, ri
, isread
);
2200 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2201 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2202 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2204 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2205 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2206 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2207 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2210 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2211 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2212 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2214 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2215 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2217 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2218 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2219 .resetfn
= arm_cp_reset_ignore
},
2220 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2221 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2222 .access
= PL0_R
|PL1_W
,
2223 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2225 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2226 .access
= PL0_R
|PL1_W
,
2227 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2228 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2229 .resetfn
= arm_cp_reset_ignore
},
2230 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2231 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2233 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2234 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2236 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2237 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2241 #ifndef CONFIG_USER_ONLY
2243 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2246 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2247 * Writable only at the highest implemented exception level.
2249 int el
= arm_current_el(env
);
2255 hcr
= arm_hcr_el2_eff(env
);
2256 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2257 cntkctl
= env
->cp15
.cnthctl_el2
;
2259 cntkctl
= env
->cp15
.c14_cntkctl
;
2261 if (!extract32(cntkctl
, 0, 2)) {
2262 return CP_ACCESS_TRAP
;
2266 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2267 arm_is_secure_below_el3(env
)) {
2268 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2269 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2277 if (!isread
&& el
< arm_highest_el(env
)) {
2278 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2281 return CP_ACCESS_OK
;
2284 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2287 unsigned int cur_el
= arm_current_el(env
);
2288 bool has_el2
= arm_is_el2_enabled(env
);
2289 uint64_t hcr
= arm_hcr_el2_eff(env
);
2293 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2294 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2295 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2296 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2299 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2300 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2301 return CP_ACCESS_TRAP
;
2304 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2305 if (hcr
& HCR_E2H
) {
2306 if (timeridx
== GTIMER_PHYS
&&
2307 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2308 return CP_ACCESS_TRAP_EL2
;
2311 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2312 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2313 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2314 return CP_ACCESS_TRAP_EL2
;
2320 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2321 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2323 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2324 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2325 return CP_ACCESS_TRAP_EL2
;
2329 return CP_ACCESS_OK
;
2332 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2335 unsigned int cur_el
= arm_current_el(env
);
2336 bool has_el2
= arm_is_el2_enabled(env
);
2337 uint64_t hcr
= arm_hcr_el2_eff(env
);
2341 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2342 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2343 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2344 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2348 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2349 * EL0 if EL0[PV]TEN is zero.
2351 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2352 return CP_ACCESS_TRAP
;
2357 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2358 if (hcr
& HCR_E2H
) {
2359 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2360 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2361 return CP_ACCESS_TRAP_EL2
;
2364 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2365 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2366 return CP_ACCESS_TRAP_EL2
;
2372 return CP_ACCESS_OK
;
2375 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2376 const ARMCPRegInfo
*ri
,
2379 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2382 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2383 const ARMCPRegInfo
*ri
,
2386 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2389 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2392 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2395 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2398 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2401 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2402 const ARMCPRegInfo
*ri
,
2405 /* The AArch64 register view of the secure physical timer is
2406 * always accessible from EL3, and configurably accessible from
2409 switch (arm_current_el(env
)) {
2411 if (!arm_is_secure(env
)) {
2412 return CP_ACCESS_TRAP
;
2414 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2415 return CP_ACCESS_TRAP_EL3
;
2417 return CP_ACCESS_OK
;
2420 return CP_ACCESS_TRAP
;
2422 return CP_ACCESS_OK
;
2424 g_assert_not_reached();
2428 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2430 ARMCPU
*cpu
= env_archcpu(env
);
2432 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2435 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2437 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2440 /* Timer enabled: calculate and set current ISTATUS, irq, and
2441 * reset timer to when ISTATUS next has to change
2443 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2444 cpu
->env
.cp15
.cntvoff_el2
: 0;
2445 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2446 /* Note that this must be unsigned 64 bit arithmetic: */
2447 int istatus
= count
- offset
>= gt
->cval
;
2451 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2453 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2454 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2457 /* Next transition is when count rolls back over to zero */
2458 nexttick
= UINT64_MAX
;
2460 /* Next transition is when we hit cval */
2461 nexttick
= gt
->cval
+ offset
;
2463 /* Note that the desired next expiry time might be beyond the
2464 * signed-64-bit range of a QEMUTimer -- in this case we just
2465 * set the timer for as far in the future as possible. When the
2466 * timer expires we will reset the timer for any remaining period.
2468 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2469 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2471 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2473 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2475 /* Timer disabled: ISTATUS and timer output always clear */
2477 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2478 timer_del(cpu
->gt_timer
[timeridx
]);
2479 trace_arm_gt_recalc_disabled(timeridx
);
2483 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2486 ARMCPU
*cpu
= env_archcpu(env
);
2488 timer_del(cpu
->gt_timer
[timeridx
]);
2491 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2493 return gt_get_countervalue(env
);
2496 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2500 switch (arm_current_el(env
)) {
2502 hcr
= arm_hcr_el2_eff(env
);
2503 if (hcr
& HCR_E2H
) {
2508 hcr
= arm_hcr_el2_eff(env
);
2509 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2515 return env
->cp15
.cntvoff_el2
;
2518 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2520 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2523 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2527 trace_arm_gt_cval_write(timeridx
, value
);
2528 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2529 gt_recalc_timer(env_archcpu(env
), timeridx
);
2532 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2535 uint64_t offset
= 0;
2539 case GTIMER_HYPVIRT
:
2540 offset
= gt_virt_cnt_offset(env
);
2544 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2545 (gt_get_countervalue(env
) - offset
));
2548 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2552 uint64_t offset
= 0;
2556 case GTIMER_HYPVIRT
:
2557 offset
= gt_virt_cnt_offset(env
);
2561 trace_arm_gt_tval_write(timeridx
, value
);
2562 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2563 sextract64(value
, 0, 32);
2564 gt_recalc_timer(env_archcpu(env
), timeridx
);
2567 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2571 ARMCPU
*cpu
= env_archcpu(env
);
2572 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2574 trace_arm_gt_ctl_write(timeridx
, value
);
2575 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2576 if ((oldval
^ value
) & 1) {
2577 /* Enable toggled */
2578 gt_recalc_timer(cpu
, timeridx
);
2579 } else if ((oldval
^ value
) & 2) {
2580 /* IMASK toggled: don't need to recalculate,
2581 * just set the interrupt line based on ISTATUS
2583 int irqstate
= (oldval
& 4) && !(value
& 2);
2585 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2586 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2590 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2592 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2595 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2598 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2601 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2603 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2606 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2609 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2612 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2615 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2618 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2620 switch (arm_mmu_idx(env
)) {
2621 case ARMMMUIdx_E20_0
:
2622 case ARMMMUIdx_E20_2
:
2623 case ARMMMUIdx_E20_2_PAN
:
2624 case ARMMMUIdx_SE20_0
:
2625 case ARMMMUIdx_SE20_2
:
2626 case ARMMMUIdx_SE20_2_PAN
:
2633 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2635 switch (arm_mmu_idx(env
)) {
2636 case ARMMMUIdx_E20_0
:
2637 case ARMMMUIdx_E20_2
:
2638 case ARMMMUIdx_E20_2_PAN
:
2639 case ARMMMUIdx_SE20_0
:
2640 case ARMMMUIdx_SE20_2
:
2641 case ARMMMUIdx_SE20_2_PAN
:
2642 return GTIMER_HYPVIRT
;
2648 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2649 const ARMCPRegInfo
*ri
)
2651 int timeridx
= gt_phys_redir_timeridx(env
);
2652 return env
->cp15
.c14_timer
[timeridx
].cval
;
2655 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2658 int timeridx
= gt_phys_redir_timeridx(env
);
2659 gt_cval_write(env
, ri
, timeridx
, value
);
2662 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2663 const ARMCPRegInfo
*ri
)
2665 int timeridx
= gt_phys_redir_timeridx(env
);
2666 return gt_tval_read(env
, ri
, timeridx
);
2669 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2672 int timeridx
= gt_phys_redir_timeridx(env
);
2673 gt_tval_write(env
, ri
, timeridx
, value
);
2676 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2677 const ARMCPRegInfo
*ri
)
2679 int timeridx
= gt_phys_redir_timeridx(env
);
2680 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2683 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2686 int timeridx
= gt_phys_redir_timeridx(env
);
2687 gt_ctl_write(env
, ri
, timeridx
, value
);
2690 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2692 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2695 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2698 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2701 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2703 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2706 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2709 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2712 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2715 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2718 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2721 ARMCPU
*cpu
= env_archcpu(env
);
2723 trace_arm_gt_cntvoff_write(value
);
2724 raw_write(env
, ri
, value
);
2725 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2728 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2729 const ARMCPRegInfo
*ri
)
2731 int timeridx
= gt_virt_redir_timeridx(env
);
2732 return env
->cp15
.c14_timer
[timeridx
].cval
;
2735 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2738 int timeridx
= gt_virt_redir_timeridx(env
);
2739 gt_cval_write(env
, ri
, timeridx
, value
);
2742 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2743 const ARMCPRegInfo
*ri
)
2745 int timeridx
= gt_virt_redir_timeridx(env
);
2746 return gt_tval_read(env
, ri
, timeridx
);
2749 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2752 int timeridx
= gt_virt_redir_timeridx(env
);
2753 gt_tval_write(env
, ri
, timeridx
, value
);
2756 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2757 const ARMCPRegInfo
*ri
)
2759 int timeridx
= gt_virt_redir_timeridx(env
);
2760 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2763 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2766 int timeridx
= gt_virt_redir_timeridx(env
);
2767 gt_ctl_write(env
, ri
, timeridx
, value
);
2770 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2772 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2775 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2778 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2781 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2783 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2786 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2789 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2792 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2795 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2798 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2800 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2803 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2806 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2809 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2811 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2814 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2817 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2820 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2823 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2826 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2828 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2831 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2834 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2837 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2839 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2842 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2845 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2848 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2851 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2854 void arm_gt_ptimer_cb(void *opaque
)
2856 ARMCPU
*cpu
= opaque
;
2858 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2861 void arm_gt_vtimer_cb(void *opaque
)
2863 ARMCPU
*cpu
= opaque
;
2865 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2868 void arm_gt_htimer_cb(void *opaque
)
2870 ARMCPU
*cpu
= opaque
;
2872 gt_recalc_timer(cpu
, GTIMER_HYP
);
2875 void arm_gt_stimer_cb(void *opaque
)
2877 ARMCPU
*cpu
= opaque
;
2879 gt_recalc_timer(cpu
, GTIMER_SEC
);
2882 void arm_gt_hvtimer_cb(void *opaque
)
2884 ARMCPU
*cpu
= opaque
;
2886 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
2889 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2891 ARMCPU
*cpu
= env_archcpu(env
);
2893 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
2896 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2897 /* Note that CNTFRQ is purely reads-as-written for the benefit
2898 * of software; writing it doesn't actually change the timer frequency.
2899 * Our reset value matches the fixed frequency we implement the timer at.
2901 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2902 .type
= ARM_CP_ALIAS
,
2903 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2904 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2906 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2907 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2908 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2909 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2910 .resetfn
= arm_gt_cntfrq_reset
,
2912 /* overall control: mostly access permissions */
2913 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2914 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2916 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2919 /* per-timer control */
2920 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2921 .secure
= ARM_CP_SECSTATE_NS
,
2922 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2923 .accessfn
= gt_ptimer_access
,
2924 .fieldoffset
= offsetoflow32(CPUARMState
,
2925 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2926 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2927 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2929 { .name
= "CNTP_CTL_S",
2930 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2931 .secure
= ARM_CP_SECSTATE_S
,
2932 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2933 .accessfn
= gt_ptimer_access
,
2934 .fieldoffset
= offsetoflow32(CPUARMState
,
2935 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2936 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2938 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2939 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2940 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2941 .accessfn
= gt_ptimer_access
,
2942 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2944 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2945 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2947 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2948 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2949 .accessfn
= gt_vtimer_access
,
2950 .fieldoffset
= offsetoflow32(CPUARMState
,
2951 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2952 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2953 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2955 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2956 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2957 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2958 .accessfn
= gt_vtimer_access
,
2959 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2961 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2962 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2964 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2965 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2966 .secure
= ARM_CP_SECSTATE_NS
,
2967 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2968 .accessfn
= gt_ptimer_access
,
2969 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2971 { .name
= "CNTP_TVAL_S",
2972 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2973 .secure
= ARM_CP_SECSTATE_S
,
2974 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2975 .accessfn
= gt_ptimer_access
,
2976 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2978 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2979 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2980 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2981 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2982 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2984 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2985 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2986 .accessfn
= gt_vtimer_access
,
2987 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
2989 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2990 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2991 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2992 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2993 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
2995 /* The counter itself */
2996 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2997 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2998 .accessfn
= gt_pct_access
,
2999 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3001 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3002 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3003 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3004 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3006 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3007 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3008 .accessfn
= gt_vct_access
,
3009 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3011 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3012 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3013 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3014 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3016 /* Comparison value, indicating when the timer goes off */
3017 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3018 .secure
= ARM_CP_SECSTATE_NS
,
3020 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3021 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3022 .accessfn
= gt_ptimer_access
,
3023 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3024 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3026 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3027 .secure
= ARM_CP_SECSTATE_S
,
3029 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3030 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3031 .accessfn
= gt_ptimer_access
,
3032 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3034 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3035 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3038 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3039 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3040 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3041 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3043 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3045 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3046 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3047 .accessfn
= gt_vtimer_access
,
3048 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3049 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3051 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3052 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3055 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3056 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3057 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3058 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3060 /* Secure timer -- this is actually restricted to only EL3
3061 * and configurably Secure-EL1 via the accessfn.
3063 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3064 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3065 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3066 .accessfn
= gt_stimer_access
,
3067 .readfn
= gt_sec_tval_read
,
3068 .writefn
= gt_sec_tval_write
,
3069 .resetfn
= gt_sec_timer_reset
,
3071 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3072 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3073 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3074 .accessfn
= gt_stimer_access
,
3075 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3077 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3079 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3080 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3081 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3082 .accessfn
= gt_stimer_access
,
3083 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3084 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3088 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3091 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3092 return CP_ACCESS_TRAP
;
3094 return CP_ACCESS_OK
;
3099 /* In user-mode most of the generic timer registers are inaccessible
3100 * however modern kernels (4.12+) allow access to cntvct_el0
3103 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3105 ARMCPU
*cpu
= env_archcpu(env
);
3107 /* Currently we have no support for QEMUTimer in linux-user so we
3108 * can't call gt_get_countervalue(env), instead we directly
3109 * call the lower level functions.
3111 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3114 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3115 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3116 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3117 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3119 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3121 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3122 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3123 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3124 .readfn
= gt_virt_cnt_read
,
3130 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3132 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3133 raw_write(env
, ri
, value
);
3134 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3135 raw_write(env
, ri
, value
& 0xfffff6ff);
3137 raw_write(env
, ri
, value
& 0xfffff1ff);
3141 #ifndef CONFIG_USER_ONLY
3142 /* get_phys_addr() isn't present for user-mode-only targets */
3144 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3148 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3149 * Secure EL1 (which can only happen if EL3 is AArch64).
3150 * They are simply UNDEF if executed from NS EL1.
3151 * They function normally from EL2 or EL3.
3153 if (arm_current_el(env
) == 1) {
3154 if (arm_is_secure_below_el3(env
)) {
3155 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3156 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3158 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3160 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3163 return CP_ACCESS_OK
;
3167 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3168 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3171 target_ulong page_size
;
3175 bool format64
= false;
3176 MemTxAttrs attrs
= {};
3177 ARMMMUFaultInfo fi
= {};
3178 ARMCacheAttrs cacheattrs
= {};
3180 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3181 &prot
, &page_size
, &fi
, &cacheattrs
);
3184 * ATS operations only do S1 or S1+S2 translations, so we never
3185 * have to deal with the ARMCacheAttrs format for S2 only.
3187 assert(!cacheattrs
.is_s2_format
);
3191 * Some kinds of translation fault must cause exceptions rather
3192 * than being reported in the PAR.
3194 int current_el
= arm_current_el(env
);
3196 uint32_t syn
, fsr
, fsc
;
3197 bool take_exc
= false;
3199 if (fi
.s1ptw
&& current_el
== 1
3200 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3202 * Synchronous stage 2 fault on an access made as part of the
3203 * translation table walk for AT S1E0* or AT S1E1* insn
3204 * executed from NS EL1. If this is a synchronous external abort
3205 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3206 * to EL3. Otherwise the fault is taken as an exception to EL2,
3207 * and HPFAR_EL2 holds the faulting IPA.
3209 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3210 (env
->cp15
.scr_el3
& SCR_EA
)) {
3213 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3214 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3215 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3220 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3222 * Synchronous external aborts during a translation table walk
3223 * are taken as Data Abort exceptions.
3226 if (current_el
== 3) {
3232 target_el
= exception_target_el(env
);
3238 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3239 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3240 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3241 fsr
= arm_fi_to_lfsc(&fi
);
3242 fsc
= extract32(fsr
, 0, 6);
3244 fsr
= arm_fi_to_sfsc(&fi
);
3248 * Report exception with ESR indicating a fault due to a
3249 * translation table walk for a cache maintenance instruction.
3251 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3252 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3253 env
->exception
.vaddress
= value
;
3254 env
->exception
.fsr
= fsr
;
3255 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3261 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3264 * * TTBCR.EAE determines whether the result is returned using the
3265 * 32-bit or the 64-bit PAR format
3266 * * Instructions executed in Hyp mode always use the 64bit format
3268 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3269 * * The Non-secure TTBCR.EAE bit is set to 1
3270 * * The implementation includes EL2, and the value of HCR.VM is 1
3272 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3274 * ATS1Hx always uses the 64bit format.
3276 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3278 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3279 if (mmu_idx
== ARMMMUIdx_E10_0
||
3280 mmu_idx
== ARMMMUIdx_E10_1
||
3281 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3282 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3284 format64
|= arm_current_el(env
) == 2;
3290 /* Create a 64-bit PAR */
3291 par64
= (1 << 11); /* LPAE bit always set */
3293 par64
|= phys_addr
& ~0xfffULL
;
3294 if (!attrs
.secure
) {
3295 par64
|= (1 << 9); /* NS */
3297 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3298 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3300 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3303 par64
|= (fsr
& 0x3f) << 1; /* FS */
3305 par64
|= (1 << 9); /* S */
3308 par64
|= (1 << 8); /* PTW */
3312 /* fsr is a DFSR/IFSR value for the short descriptor
3313 * translation table format (with WnR always clear).
3314 * Convert it to a 32-bit PAR.
3317 /* We do not set any attribute bits in the PAR */
3318 if (page_size
== (1 << 24)
3319 && arm_feature(env
, ARM_FEATURE_V7
)) {
3320 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3322 par64
= phys_addr
& 0xfffff000;
3324 if (!attrs
.secure
) {
3325 par64
|= (1 << 9); /* NS */
3328 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3330 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3331 ((fsr
& 0xf) << 1) | 1;
3336 #endif /* CONFIG_TCG */
3338 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3341 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3344 int el
= arm_current_el(env
);
3345 bool secure
= arm_is_secure_below_el3(env
);
3347 switch (ri
->opc2
& 6) {
3349 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3352 mmu_idx
= ARMMMUIdx_SE3
;
3355 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3358 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3359 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3360 : ARMMMUIdx_Stage1_E1_PAN
);
3362 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3366 g_assert_not_reached();
3370 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3373 mmu_idx
= ARMMMUIdx_SE10_0
;
3376 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3377 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3380 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3383 g_assert_not_reached();
3387 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3388 mmu_idx
= ARMMMUIdx_E10_1
;
3391 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3392 mmu_idx
= ARMMMUIdx_E10_0
;
3395 g_assert_not_reached();
3398 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3400 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3402 /* Handled by hardware accelerator. */
3403 g_assert_not_reached();
3404 #endif /* CONFIG_TCG */
3407 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3411 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3414 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3416 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3418 /* Handled by hardware accelerator. */
3419 g_assert_not_reached();
3420 #endif /* CONFIG_TCG */
3423 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3426 if (arm_current_el(env
) == 3 &&
3427 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3428 return CP_ACCESS_TRAP
;
3430 return CP_ACCESS_OK
;
3433 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3437 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3439 int secure
= arm_is_secure_below_el3(env
);
3441 switch (ri
->opc2
& 6) {
3444 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3445 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3446 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3447 : ARMMMUIdx_Stage1_E1_PAN
);
3449 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3452 case 4: /* AT S1E2R, AT S1E2W */
3453 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3455 case 6: /* AT S1E3R, AT S1E3W */
3456 mmu_idx
= ARMMMUIdx_SE3
;
3459 g_assert_not_reached();
3462 case 2: /* AT S1E0R, AT S1E0W */
3463 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3465 case 4: /* AT S12E1R, AT S12E1W */
3466 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3468 case 6: /* AT S12E0R, AT S12E0W */
3469 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3472 g_assert_not_reached();
3475 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3477 /* Handled by hardware accelerator. */
3478 g_assert_not_reached();
3479 #endif /* CONFIG_TCG */
3483 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3484 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3485 .access
= PL1_RW
, .resetvalue
= 0,
3486 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3487 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3488 .writefn
= par_write
},
3489 #ifndef CONFIG_USER_ONLY
3490 /* This underdecoding is safe because the reginfo is NO_RAW. */
3491 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3492 .access
= PL1_W
, .accessfn
= ats_access
,
3493 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3497 /* Return basic MPU access permission bits. */
3498 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3505 for (i
= 0; i
< 16; i
+= 2) {
3506 ret
|= (val
>> i
) & mask
;
3512 /* Pad basic MPU access permission bits to extended format. */
3513 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3520 for (i
= 0; i
< 16; i
+= 2) {
3521 ret
|= (val
& mask
) << i
;
3527 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3530 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3533 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3535 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3538 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3541 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3544 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3546 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3549 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3551 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3557 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3561 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3564 ARMCPU
*cpu
= env_archcpu(env
);
3565 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3571 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3572 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3576 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3579 ARMCPU
*cpu
= env_archcpu(env
);
3580 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3582 if (value
>= nrgs
) {
3583 qemu_log_mask(LOG_GUEST_ERROR
,
3584 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3585 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3589 raw_write(env
, ri
, value
);
3592 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3593 /* Reset for all these registers is handled in arm_cpu_reset(),
3594 * because the PMSAv7 is also used by M-profile CPUs, which do
3595 * not register cpregs but still need the state to be reset.
3597 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3598 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3599 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3600 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3601 .resetfn
= arm_cp_reset_ignore
},
3602 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3603 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3604 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3605 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3606 .resetfn
= arm_cp_reset_ignore
},
3607 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3608 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3609 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3610 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3611 .resetfn
= arm_cp_reset_ignore
},
3612 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3614 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3615 .writefn
= pmsav7_rgnr_write
,
3616 .resetfn
= arm_cp_reset_ignore
},
3619 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3620 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3621 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3622 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3623 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3624 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3625 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3626 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3627 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3628 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3630 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3632 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3634 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3636 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3638 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3639 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3641 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3642 /* Protection region base and size registers */
3643 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3644 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3645 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3646 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3647 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3648 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3649 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3650 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3651 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3652 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3653 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3654 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3655 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3656 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3657 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3658 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3659 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3660 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3661 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3662 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3663 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3664 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3665 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3666 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3669 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3672 TCR
*tcr
= raw_ptr(env
, ri
);
3673 int maskshift
= extract32(value
, 0, 3);
3675 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3676 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3677 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3678 * using Long-desciptor translation table format */
3679 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3680 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3681 /* In an implementation that includes the Security Extensions
3682 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3683 * Short-descriptor translation table format.
3685 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3691 /* Update the masks corresponding to the TCR bank being written
3692 * Note that we always calculate mask and base_mask, but
3693 * they are only used for short-descriptor tables (ie if EAE is 0);
3694 * for long-descriptor tables the TCR fields are used differently
3695 * and the mask and base_mask values are meaningless.
3697 tcr
->raw_tcr
= value
;
3698 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3699 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3702 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3705 ARMCPU
*cpu
= env_archcpu(env
);
3706 TCR
*tcr
= raw_ptr(env
, ri
);
3708 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3709 /* With LPAE the TTBCR could result in a change of ASID
3710 * via the TTBCR.A1 bit, so do a TLB flush.
3712 tlb_flush(CPU(cpu
));
3714 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3715 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3716 vmsa_ttbcr_raw_write(env
, ri
, value
);
3719 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3721 TCR
*tcr
= raw_ptr(env
, ri
);
3723 /* Reset both the TCR as well as the masks corresponding to the bank of
3724 * the TCR being reset.
3728 tcr
->base_mask
= 0xffffc000u
;
3731 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3734 ARMCPU
*cpu
= env_archcpu(env
);
3735 TCR
*tcr
= raw_ptr(env
, ri
);
3737 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3738 tlb_flush(CPU(cpu
));
3739 tcr
->raw_tcr
= value
;
3742 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3745 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3746 if (cpreg_field_is_64bit(ri
) &&
3747 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3748 ARMCPU
*cpu
= env_archcpu(env
);
3749 tlb_flush(CPU(cpu
));
3751 raw_write(env
, ri
, value
);
3754 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3758 * If we are running with E2&0 regime, then an ASID is active.
3759 * Flush if that might be changing. Note we're not checking
3760 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3761 * holds the active ASID, only checking the field that might.
3763 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3764 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3765 uint16_t mask
= ARMMMUIdxBit_E20_2
|
3766 ARMMMUIdxBit_E20_2_PAN
|
3769 if (arm_is_secure_below_el3(env
)) {
3770 mask
>>= ARM_MMU_IDX_A_NS
;
3773 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
3775 raw_write(env
, ri
, value
);
3778 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3781 ARMCPU
*cpu
= env_archcpu(env
);
3782 CPUState
*cs
= CPU(cpu
);
3785 * A change in VMID to the stage2 page table (Stage2) invalidates
3786 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3788 if (raw_read(env
, ri
) != value
) {
3789 uint16_t mask
= ARMMMUIdxBit_E10_1
|
3790 ARMMMUIdxBit_E10_1_PAN
|
3793 if (arm_is_secure_below_el3(env
)) {
3794 mask
>>= ARM_MMU_IDX_A_NS
;
3797 tlb_flush_by_mmuidx(cs
, mask
);
3798 raw_write(env
, ri
, value
);
3802 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3803 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3804 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
3805 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3806 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3807 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3808 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3809 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3810 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3811 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3812 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3813 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3814 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3815 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3816 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3817 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3818 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3822 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3823 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3824 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3825 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3826 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3827 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3828 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3829 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3830 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3831 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3832 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3833 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3834 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3835 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3836 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3837 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3838 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3839 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3840 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3841 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3842 .writefn
= vmsa_tcr_el12_write
,
3843 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3844 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3845 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3846 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3847 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3848 .raw_writefn
= vmsa_ttbcr_raw_write
,
3849 /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
3850 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.tcr_el
[3]),
3851 offsetof(CPUARMState
, cp15
.tcr_el
[1])} },
3854 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3855 * qemu tlbs nor adjusting cached masks.
3857 static const ARMCPRegInfo ttbcr2_reginfo
= {
3858 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3859 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3860 .type
= ARM_CP_ALIAS
,
3861 .bank_fieldoffsets
= {
3862 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3].raw_tcr
),
3863 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1].raw_tcr
),
3867 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3870 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3871 /* The OS_TYPE bit in this register changes the reported CPUID! */
3872 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3873 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3876 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3879 env
->cp15
.c15_threadid
= value
& 0xffff;
3882 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3885 /* Wait-for-interrupt (deprecated) */
3886 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3889 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3892 /* On OMAP there are registers indicating the max/min index of dcache lines
3893 * containing a dirty line; cache flush operations have to reset these.
3895 env
->cp15
.c15_i_max
= 0x000;
3896 env
->cp15
.c15_i_min
= 0xff0;
3899 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3900 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3901 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3902 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3904 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3905 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3906 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3908 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3909 .writefn
= omap_ticonfig_write
},
3910 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3912 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3913 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3914 .access
= PL1_RW
, .resetvalue
= 0xff0,
3915 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3916 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3918 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3919 .writefn
= omap_threadid_write
},
3920 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3921 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3922 .type
= ARM_CP_NO_RAW
,
3923 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3924 /* TODO: Peripheral port remap register:
3925 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3926 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3929 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3930 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3931 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3932 .writefn
= omap_cachemaint_write
},
3933 { .name
= "C9", .cp
= 15, .crn
= 9,
3934 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3935 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3938 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3941 env
->cp15
.c15_cpar
= value
& 0x3fff;
3944 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3945 { .name
= "XSCALE_CPAR",
3946 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3947 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3948 .writefn
= xscale_cpar_write
, },
3949 { .name
= "XSCALE_AUXCR",
3950 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3951 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3953 /* XScale specific cache-lockdown: since we have no cache we NOP these
3954 * and hope the guest does not really rely on cache behaviour.
3956 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3957 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3958 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3959 { .name
= "XSCALE_UNLOCK_ICACHE",
3960 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3961 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3962 { .name
= "XSCALE_DCACHE_LOCK",
3963 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3964 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3965 { .name
= "XSCALE_UNLOCK_DCACHE",
3966 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3967 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3970 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3971 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3972 * implementation of this implementation-defined space.
3973 * Ideally this should eventually disappear in favour of actually
3974 * implementing the correct behaviour for all cores.
3976 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3977 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3979 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3983 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3984 /* Cache status: RAZ because we have no cache so it's always clean */
3985 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3986 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3990 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3991 /* We never have a a block transfer operation in progress */
3992 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3993 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3995 /* The cache ops themselves: these all NOP for QEMU */
3996 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3997 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3998 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3999 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4000 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4001 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4002 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4003 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4004 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4005 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4006 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4007 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4010 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4011 /* The cache test-and-clean instructions always return (1 << 30)
4012 * to indicate that there are no dirty cache lines.
4014 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4015 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4016 .resetvalue
= (1 << 30) },
4017 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4018 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4019 .resetvalue
= (1 << 30) },
4022 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4023 /* Ignore ReadBuffer accesses */
4024 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4025 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4026 .access
= PL1_RW
, .resetvalue
= 0,
4027 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4030 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4032 unsigned int cur_el
= arm_current_el(env
);
4034 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4035 return env
->cp15
.vpidr_el2
;
4037 return raw_read(env
, ri
);
4040 static uint64_t mpidr_read_val(CPUARMState
*env
)
4042 ARMCPU
*cpu
= env_archcpu(env
);
4043 uint64_t mpidr
= cpu
->mp_affinity
;
4045 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4046 mpidr
|= (1U << 31);
4047 /* Cores which are uniprocessor (non-coherent)
4048 * but still implement the MP extensions set
4049 * bit 30. (For instance, Cortex-R5).
4051 if (cpu
->mp_is_up
) {
4052 mpidr
|= (1u << 30);
4058 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4060 unsigned int cur_el
= arm_current_el(env
);
4062 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4063 return env
->cp15
.vmpidr_el2
;
4065 return mpidr_read_val(env
);
4068 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4070 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4071 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4072 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4073 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4074 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4075 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4076 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4077 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4078 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4079 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4080 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4081 offsetof(CPUARMState
, cp15
.par_ns
)} },
4082 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4083 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4084 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4085 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4086 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4087 .writefn
= vmsa_ttbr_write
, },
4088 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4089 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4090 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4091 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4092 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4093 .writefn
= vmsa_ttbr_write
, },
4096 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4098 return vfp_get_fpcr(env
);
4101 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4104 vfp_set_fpcr(env
, value
);
4107 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4109 return vfp_get_fpsr(env
);
4112 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4115 vfp_set_fpsr(env
, value
);
4118 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4121 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4122 return CP_ACCESS_TRAP
;
4124 return CP_ACCESS_OK
;
4127 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4130 env
->daif
= value
& PSTATE_DAIF
;
4133 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4135 return env
->pstate
& PSTATE_PAN
;
4138 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4141 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4144 static const ARMCPRegInfo pan_reginfo
= {
4145 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4146 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4147 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4148 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4151 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4153 return env
->pstate
& PSTATE_UAO
;
4156 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4159 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4162 static const ARMCPRegInfo uao_reginfo
= {
4163 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4164 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4165 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4166 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4169 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4171 return env
->pstate
& PSTATE_DIT
;
4174 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4177 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4180 static const ARMCPRegInfo dit_reginfo
= {
4181 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4182 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4183 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4184 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4187 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4189 return env
->pstate
& PSTATE_SSBS
;
4192 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4195 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4198 static const ARMCPRegInfo ssbs_reginfo
= {
4199 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4200 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4201 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4202 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4205 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4206 const ARMCPRegInfo
*ri
,
4209 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4210 switch (arm_current_el(env
)) {
4212 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4213 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4214 return CP_ACCESS_TRAP
;
4218 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4219 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4220 return CP_ACCESS_TRAP_EL2
;
4224 return CP_ACCESS_OK
;
4227 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4228 const ARMCPRegInfo
*ri
,
4231 /* Cache invalidate/clean to Point of Unification... */
4232 switch (arm_current_el(env
)) {
4234 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4235 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4236 return CP_ACCESS_TRAP
;
4240 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4241 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4242 return CP_ACCESS_TRAP_EL2
;
4246 return CP_ACCESS_OK
;
4249 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4250 * Page D4-1736 (DDI0487A.b)
4253 static int vae1_tlbmask(CPUARMState
*env
)
4255 uint64_t hcr
= arm_hcr_el2_eff(env
);
4258 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4259 mask
= ARMMMUIdxBit_E20_2
|
4260 ARMMMUIdxBit_E20_2_PAN
|
4263 mask
= ARMMMUIdxBit_E10_1
|
4264 ARMMMUIdxBit_E10_1_PAN
|
4268 if (arm_is_secure_below_el3(env
)) {
4269 mask
>>= ARM_MMU_IDX_A_NS
;
4275 /* Return 56 if TBI is enabled, 64 otherwise. */
4276 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4279 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
4280 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4281 int select
= extract64(addr
, 55, 1);
4283 return (tbi
>> select
) & 1 ? 56 : 64;
4286 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4288 uint64_t hcr
= arm_hcr_el2_eff(env
);
4291 /* Only the regime of the mmu_idx below is significant. */
4292 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4293 mmu_idx
= ARMMMUIdx_E20_0
;
4295 mmu_idx
= ARMMMUIdx_E10_0
;
4298 if (arm_is_secure_below_el3(env
)) {
4299 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4302 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4305 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4308 CPUState
*cs
= env_cpu(env
);
4309 int mask
= vae1_tlbmask(env
);
4311 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4314 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4317 CPUState
*cs
= env_cpu(env
);
4318 int mask
= vae1_tlbmask(env
);
4320 if (tlb_force_broadcast(env
)) {
4321 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4323 tlb_flush_by_mmuidx(cs
, mask
);
4327 static int alle1_tlbmask(CPUARMState
*env
)
4330 * Note that the 'ALL' scope must invalidate both stage 1 and
4331 * stage 2 translations, whereas most other scopes only invalidate
4332 * stage 1 translations.
4334 if (arm_is_secure_below_el3(env
)) {
4335 return ARMMMUIdxBit_SE10_1
|
4336 ARMMMUIdxBit_SE10_1_PAN
|
4337 ARMMMUIdxBit_SE10_0
;
4339 return ARMMMUIdxBit_E10_1
|
4340 ARMMMUIdxBit_E10_1_PAN
|
4345 static int e2_tlbmask(CPUARMState
*env
)
4347 if (arm_is_secure_below_el3(env
)) {
4348 return ARMMMUIdxBit_SE20_0
|
4349 ARMMMUIdxBit_SE20_2
|
4350 ARMMMUIdxBit_SE20_2_PAN
|
4353 return ARMMMUIdxBit_E20_0
|
4354 ARMMMUIdxBit_E20_2
|
4355 ARMMMUIdxBit_E20_2_PAN
|
4360 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4363 CPUState
*cs
= env_cpu(env
);
4364 int mask
= alle1_tlbmask(env
);
4366 tlb_flush_by_mmuidx(cs
, mask
);
4369 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4372 CPUState
*cs
= env_cpu(env
);
4373 int mask
= e2_tlbmask(env
);
4375 tlb_flush_by_mmuidx(cs
, mask
);
4378 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4381 ARMCPU
*cpu
= env_archcpu(env
);
4382 CPUState
*cs
= CPU(cpu
);
4384 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4387 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4390 CPUState
*cs
= env_cpu(env
);
4391 int mask
= alle1_tlbmask(env
);
4393 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4396 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4399 CPUState
*cs
= env_cpu(env
);
4400 int mask
= e2_tlbmask(env
);
4402 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4405 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4408 CPUState
*cs
= env_cpu(env
);
4410 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4413 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4416 /* Invalidate by VA, EL2
4417 * Currently handles both VAE2 and VALE2, since we don't support
4418 * flush-last-level-only.
4420 CPUState
*cs
= env_cpu(env
);
4421 int mask
= e2_tlbmask(env
);
4422 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4424 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4427 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4430 /* Invalidate by VA, EL3
4431 * Currently handles both VAE3 and VALE3, since we don't support
4432 * flush-last-level-only.
4434 ARMCPU
*cpu
= env_archcpu(env
);
4435 CPUState
*cs
= CPU(cpu
);
4436 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4438 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4441 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4444 CPUState
*cs
= env_cpu(env
);
4445 int mask
= vae1_tlbmask(env
);
4446 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4447 int bits
= vae1_tlbbits(env
, pageaddr
);
4449 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4452 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4455 /* Invalidate by VA, EL1&0 (AArch64 version).
4456 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4457 * since we don't support flush-for-specific-ASID-only or
4458 * flush-last-level-only.
4460 CPUState
*cs
= env_cpu(env
);
4461 int mask
= vae1_tlbmask(env
);
4462 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4463 int bits
= vae1_tlbbits(env
, pageaddr
);
4465 if (tlb_force_broadcast(env
)) {
4466 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4468 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4472 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4475 CPUState
*cs
= env_cpu(env
);
4476 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4477 bool secure
= arm_is_secure_below_el3(env
);
4478 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4479 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
,
4482 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4485 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4488 CPUState
*cs
= env_cpu(env
);
4489 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4490 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4492 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4493 ARMMMUIdxBit_SE3
, bits
);
4496 #ifdef TARGET_AARCH64
4502 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4505 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4506 /* Extract one bit to represent the va selector in use. */
4507 uint64_t select
= sextract64(value
, 36, 1);
4508 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4509 TLBIRange ret
= { };
4511 page_size_granule
= extract64(value
, 46, 2);
4513 /* The granule encoded in value must match the granule in use. */
4514 if (page_size_granule
!= (param
.using64k
? 3 : param
.using16k
? 2 : 1)) {
4515 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4520 page_shift
= (page_size_granule
- 1) * 2 + 12;
4521 num
= extract64(value
, 39, 5);
4522 scale
= extract64(value
, 44, 2);
4523 exponent
= (5 * scale
) + 1;
4525 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4528 ret
.base
= sextract64(value
, 0, 37);
4530 ret
.base
= extract64(value
, 0, 37);
4534 * With DS=1, BaseADDR is always shifted 16 so that it is able
4535 * to address all 52 va bits. The input address is perforce
4536 * aligned on a 64k boundary regardless of translation granule.
4540 ret
.base
<<= page_shift
;
4545 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4546 int idxmap
, bool synced
)
4548 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4552 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4553 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4556 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4562 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4563 range
.length
, idxmap
, bits
);
4567 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4568 const ARMCPRegInfo
*ri
,
4572 * Invalidate by VA range, EL1&0.
4573 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4574 * since we don't support flush-for-specific-ASID-only or
4575 * flush-last-level-only.
4578 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4579 tlb_force_broadcast(env
));
4582 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4583 const ARMCPRegInfo
*ri
,
4587 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4588 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4589 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4590 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4591 * shareable specific flushes.
4594 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4597 static int vae2_tlbmask(CPUARMState
*env
)
4599 return (arm_is_secure_below_el3(env
)
4600 ? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
);
4603 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4604 const ARMCPRegInfo
*ri
,
4608 * Invalidate by VA range, EL2.
4609 * Currently handles all of RVAE2 and RVALE2,
4610 * since we don't support flush-for-specific-ASID-only or
4611 * flush-last-level-only.
4614 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4615 tlb_force_broadcast(env
));
4620 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4621 const ARMCPRegInfo
*ri
,
4625 * Invalidate by VA range, Inner/Outer Shareable, EL2.
4626 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
4627 * since we don't support flush-for-specific-ASID-only,
4628 * flush-last-level-only or inner/outer shareable specific flushes.
4631 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
4635 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
4636 const ARMCPRegInfo
*ri
,
4640 * Invalidate by VA range, EL3.
4641 * Currently handles all of RVAE3 and RVALE3,
4642 * since we don't support flush-for-specific-ASID-only or
4643 * flush-last-level-only.
4646 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
,
4647 tlb_force_broadcast(env
));
4650 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
4651 const ARMCPRegInfo
*ri
,
4655 * Invalidate by VA range, EL3, Inner/Outer Shareable.
4656 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
4657 * since we don't support flush-for-specific-ASID-only,
4658 * flush-last-level-only or inner/outer specific flushes.
4661 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
, true);
4665 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4668 int cur_el
= arm_current_el(env
);
4671 uint64_t hcr
= arm_hcr_el2_eff(env
);
4674 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4675 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4676 return CP_ACCESS_TRAP_EL2
;
4679 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4680 return CP_ACCESS_TRAP
;
4682 if (hcr
& HCR_TDZ
) {
4683 return CP_ACCESS_TRAP_EL2
;
4686 } else if (hcr
& HCR_TDZ
) {
4687 return CP_ACCESS_TRAP_EL2
;
4690 return CP_ACCESS_OK
;
4693 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4695 ARMCPU
*cpu
= env_archcpu(env
);
4696 int dzp_bit
= 1 << 4;
4698 /* DZP indicates whether DC ZVA access is allowed */
4699 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4702 return cpu
->dcz_blocksize
| dzp_bit
;
4705 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4708 if (!(env
->pstate
& PSTATE_SP
)) {
4709 /* Access to SP_EL0 is undefined if it's being used as
4710 * the stack pointer.
4712 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4714 return CP_ACCESS_OK
;
4717 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4719 return env
->pstate
& PSTATE_SP
;
4722 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4724 update_spsel(env
, val
);
4727 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4730 ARMCPU
*cpu
= env_archcpu(env
);
4732 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4733 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4737 /* ??? Lots of these bits are not implemented. */
4739 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4740 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4741 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4743 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4744 SCTLR_ATA0
| SCTLR_ATA
);
4748 if (raw_read(env
, ri
) == value
) {
4749 /* Skip the TLB flush if nothing actually changed; Linux likes
4750 * to do a lot of pointless SCTLR writes.
4755 raw_write(env
, ri
, value
);
4757 /* This may enable/disable the MMU, so do a TLB flush. */
4758 tlb_flush(CPU(cpu
));
4760 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4762 * Normally we would always end the TB on an SCTLR write; see the
4763 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4764 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4765 * of hflags from the translator, so do it here.
4767 arm_rebuild_hflags(env
);
4771 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4774 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4777 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4778 /* Minimal set of EL0-visible registers. This will need to be expanded
4779 * significantly for system emulation of AArch64 CPUs.
4781 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4782 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4783 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4784 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4785 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4786 .type
= ARM_CP_NO_RAW
,
4787 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4788 .fieldoffset
= offsetof(CPUARMState
, daif
),
4789 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4790 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4791 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4792 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4793 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4794 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4795 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4796 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4797 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4798 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4799 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4800 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4801 .readfn
= aa64_dczid_read
},
4802 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4803 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4804 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4805 #ifndef CONFIG_USER_ONLY
4806 /* Avoid overhead of an access check that always passes in user-mode */
4807 .accessfn
= aa64_zva_access
,
4810 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4811 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4812 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4813 /* Cache ops: all NOPs since we don't emulate caches */
4814 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4815 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4816 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4817 .accessfn
= aa64_cacheop_pou_access
},
4818 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4819 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4820 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4821 .accessfn
= aa64_cacheop_pou_access
},
4822 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4823 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4824 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4825 .accessfn
= aa64_cacheop_pou_access
},
4826 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4827 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4828 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4829 .type
= ARM_CP_NOP
},
4830 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4831 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4832 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4833 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4834 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4835 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4836 .accessfn
= aa64_cacheop_poc_access
},
4837 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4838 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4839 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4840 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4841 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4842 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4843 .accessfn
= aa64_cacheop_pou_access
},
4844 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4845 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4846 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4847 .accessfn
= aa64_cacheop_poc_access
},
4848 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4849 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4850 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4851 /* TLBI operations */
4852 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4853 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4854 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4855 .writefn
= tlbi_aa64_vmalle1is_write
},
4856 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4857 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4858 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4859 .writefn
= tlbi_aa64_vae1is_write
},
4860 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4861 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4862 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4863 .writefn
= tlbi_aa64_vmalle1is_write
},
4864 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4865 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4866 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4867 .writefn
= tlbi_aa64_vae1is_write
},
4868 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4869 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4870 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4871 .writefn
= tlbi_aa64_vae1is_write
},
4872 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4873 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4874 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4875 .writefn
= tlbi_aa64_vae1is_write
},
4876 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4877 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4878 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4879 .writefn
= tlbi_aa64_vmalle1_write
},
4880 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4881 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4882 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4883 .writefn
= tlbi_aa64_vae1_write
},
4884 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4885 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4886 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4887 .writefn
= tlbi_aa64_vmalle1_write
},
4888 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4889 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4890 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4891 .writefn
= tlbi_aa64_vae1_write
},
4892 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4893 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4894 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4895 .writefn
= tlbi_aa64_vae1_write
},
4896 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4897 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4898 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4899 .writefn
= tlbi_aa64_vae1_write
},
4900 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4901 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4902 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4903 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4904 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4905 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4906 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4907 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4908 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4909 .writefn
= tlbi_aa64_alle1is_write
},
4910 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4911 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4912 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4913 .writefn
= tlbi_aa64_alle1is_write
},
4914 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4915 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4916 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4917 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4918 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4919 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4920 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4921 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4922 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4923 .writefn
= tlbi_aa64_alle1_write
},
4924 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4925 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4926 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4927 .writefn
= tlbi_aa64_alle1is_write
},
4928 #ifndef CONFIG_USER_ONLY
4929 /* 64 bit address translation operations */
4930 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4931 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4932 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4933 .writefn
= ats_write64
},
4934 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4935 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4936 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4937 .writefn
= ats_write64
},
4938 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4939 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4940 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4941 .writefn
= ats_write64
},
4942 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4943 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4944 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4945 .writefn
= ats_write64
},
4946 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4947 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4948 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4949 .writefn
= ats_write64
},
4950 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4951 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4952 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4953 .writefn
= ats_write64
},
4954 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4955 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4956 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4957 .writefn
= ats_write64
},
4958 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4959 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4960 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4961 .writefn
= ats_write64
},
4962 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4963 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4964 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4965 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4966 .writefn
= ats_write64
},
4967 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4968 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4969 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4970 .writefn
= ats_write64
},
4971 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4972 .type
= ARM_CP_ALIAS
,
4973 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4974 .access
= PL1_RW
, .resetvalue
= 0,
4975 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4976 .writefn
= par_write
},
4978 /* TLB invalidate last level of translation table walk */
4979 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4980 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4981 .writefn
= tlbimva_is_write
},
4982 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4983 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4984 .writefn
= tlbimvaa_is_write
},
4985 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4986 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4987 .writefn
= tlbimva_write
},
4988 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4989 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4990 .writefn
= tlbimvaa_write
},
4991 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4992 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4993 .writefn
= tlbimva_hyp_write
},
4994 { .name
= "TLBIMVALHIS",
4995 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4996 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4997 .writefn
= tlbimva_hyp_is_write
},
4998 { .name
= "TLBIIPAS2",
4999 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5000 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5001 { .name
= "TLBIIPAS2IS",
5002 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5003 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5004 { .name
= "TLBIIPAS2L",
5005 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5006 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5007 { .name
= "TLBIIPAS2LIS",
5008 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5009 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5010 /* 32 bit cache operations */
5011 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5012 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5013 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5014 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5015 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5016 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5017 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5018 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5019 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5020 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5021 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5022 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5023 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5024 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5025 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5026 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5027 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5028 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5029 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5030 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5031 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5032 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5033 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5034 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5035 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5036 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5037 /* MMU Domain access control / MPU write buffer control */
5038 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5039 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5040 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5041 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5042 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5043 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5044 .type
= ARM_CP_ALIAS
,
5045 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5047 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5048 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5049 .type
= ARM_CP_ALIAS
,
5050 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5052 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5053 /* We rely on the access checks not allowing the guest to write to the
5054 * state field when SPSel indicates that it's being used as the stack
5057 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5058 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5059 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5060 .type
= ARM_CP_ALIAS
,
5061 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5062 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5063 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5064 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5065 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5066 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5067 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5068 .type
= ARM_CP_NO_RAW
,
5069 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5070 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5071 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5073 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5074 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5075 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5076 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5077 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5078 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5079 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5080 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5081 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5082 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5083 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5084 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5085 .type
= ARM_CP_ALIAS
,
5086 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5088 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5089 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5090 .type
= ARM_CP_ALIAS
,
5091 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5093 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5094 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5095 .type
= ARM_CP_ALIAS
,
5096 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5098 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5099 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5100 .type
= ARM_CP_ALIAS
,
5101 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5103 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5104 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5105 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5107 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5108 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5109 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5110 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5111 .writefn
= sdcr_write
,
5112 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5115 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5117 ARMCPU
*cpu
= env_archcpu(env
);
5119 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5120 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5122 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5125 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5126 valid_mask
&= ~HCR_HCD
;
5127 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5128 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5129 * However, if we're using the SMC PSCI conduit then QEMU is
5130 * effectively acting like EL3 firmware and so the guest at
5131 * EL2 should retain the ability to prevent EL1 from being
5132 * able to make SMC calls into the ersatz firmware, so in
5133 * that case HCR.TSC should be read/write.
5135 valid_mask
&= ~HCR_TSC
;
5138 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5139 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5140 valid_mask
|= HCR_E2H
;
5142 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5143 valid_mask
|= HCR_TERR
| HCR_TEA
;
5145 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5146 valid_mask
|= HCR_TLOR
;
5148 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5149 valid_mask
|= HCR_API
| HCR_APK
;
5151 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5152 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5154 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5155 valid_mask
|= HCR_ENSCXT
;
5157 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5158 valid_mask
|= HCR_FWB
;
5162 /* Clear RES0 bits. */
5163 value
&= valid_mask
;
5166 * These bits change the MMU setup:
5167 * HCR_VM enables stage 2 translation
5168 * HCR_PTW forbids certain page-table setups
5169 * HCR_DC disables stage1 and enables stage2 translation
5170 * HCR_DCT enables tagging on (disabled) stage1 translation
5171 * HCR_FWB changes the interpretation of stage2 descriptor bits
5173 if ((env
->cp15
.hcr_el2
^ value
) &
5174 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5175 tlb_flush(CPU(cpu
));
5177 env
->cp15
.hcr_el2
= value
;
5180 * Updates to VI and VF require us to update the status of
5181 * virtual interrupts, which are the logical OR of these bits
5182 * and the state of the input lines from the GIC. (This requires
5183 * that we have the iothread lock, which is done by marking the
5184 * reginfo structs as ARM_CP_IO.)
5185 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5186 * possible for it to be taken immediately, because VIRQ and
5187 * VFIQ are masked unless running at EL0 or EL1, and HCR
5188 * can only be written at EL2.
5190 g_assert(qemu_mutex_iothread_locked());
5191 arm_cpu_update_virq(cpu
);
5192 arm_cpu_update_vfiq(cpu
);
5193 arm_cpu_update_vserr(cpu
);
5196 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5198 do_hcr_write(env
, value
, 0);
5201 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5204 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5205 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5206 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5209 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5212 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5213 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5214 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5218 * Return the effective value of HCR_EL2.
5219 * Bits that are not included here:
5220 * RW (read from SCR_EL3.RW as needed)
5222 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5224 uint64_t ret
= env
->cp15
.hcr_el2
;
5226 if (!arm_is_el2_enabled(env
)) {
5228 * "This register has no effect if EL2 is not enabled in the
5229 * current Security state". This is ARMv8.4-SecEL2 speak for
5230 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5232 * Prior to that, the language was "In an implementation that
5233 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5234 * as if this field is 0 for all purposes other than a direct
5235 * read or write access of HCR_EL2". With lots of enumeration
5236 * on a per-field basis. In current QEMU, this is condition
5237 * is arm_is_secure_below_el3.
5239 * Since the v8.4 language applies to the entire register, and
5240 * appears to be backward compatible, use that.
5246 * For a cpu that supports both aarch64 and aarch32, we can set bits
5247 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5248 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5250 if (!arm_el_is_aa64(env
, 2)) {
5251 uint64_t aa32_valid
;
5254 * These bits are up-to-date as of ARMv8.6.
5255 * For HCR, it's easiest to list just the 2 bits that are invalid.
5256 * For HCR2, list those that are valid.
5258 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5259 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5260 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5264 if (ret
& HCR_TGE
) {
5265 /* These bits are up-to-date as of ARMv8.6. */
5266 if (ret
& HCR_E2H
) {
5267 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5268 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5269 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5270 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5271 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5272 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5274 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5276 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5277 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5278 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5286 * Corresponds to ARM pseudocode function ELIsInHost().
5288 bool el_is_in_host(CPUARMState
*env
, int el
)
5293 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5294 * Perform the simplest bit tests first, and validate EL2 afterward.
5297 return false; /* EL1 or EL3 */
5301 * Note that hcr_write() checks isar_feature_aa64_vh(),
5302 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5304 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5305 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5309 /* TGE and/or E2H set: double check those bits are currently legal. */
5310 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5313 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5316 uint64_t valid_mask
= 0;
5318 /* No features adding bits to HCRX are implemented. */
5320 /* Clear RES0 bits. */
5321 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5324 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5327 if (arm_current_el(env
) < 3
5328 && arm_feature(env
, ARM_FEATURE_EL3
)
5329 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5330 return CP_ACCESS_TRAP_EL3
;
5332 return CP_ACCESS_OK
;
5335 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5336 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5337 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5338 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5339 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5342 /* Return the effective value of HCRX_EL2. */
5343 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5346 * The bits in this register behave as 0 for all purposes other than
5347 * direct reads of the register if:
5348 * - EL2 is not enabled in the current security state,
5349 * - SCR_EL3.HXEn is 0.
5351 if (!arm_is_el2_enabled(env
)
5352 || (arm_feature(env
, ARM_FEATURE_EL3
)
5353 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5356 return env
->cp15
.hcrx_el2
;
5359 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5363 * For A-profile AArch32 EL3, if NSACR.CP10
5364 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5366 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5367 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5368 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5369 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5371 env
->cp15
.cptr_el
[2] = value
;
5374 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5377 * For A-profile AArch32 EL3, if NSACR.CP10
5378 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5380 uint64_t value
= env
->cp15
.cptr_el
[2];
5382 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5383 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5384 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5389 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5390 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5392 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5393 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5394 .writefn
= hcr_write
},
5395 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5396 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5397 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5398 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5399 .writefn
= hcr_writelow
},
5400 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5401 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5402 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5403 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5404 .type
= ARM_CP_ALIAS
,
5405 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5407 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5408 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5409 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5410 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5411 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5412 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5413 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5414 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5415 .type
= ARM_CP_ALIAS
,
5416 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5418 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5419 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5420 .type
= ARM_CP_ALIAS
,
5421 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5423 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5424 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5425 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5426 .access
= PL2_RW
, .writefn
= vbar_write
,
5427 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5429 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5430 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5431 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5432 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5433 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5434 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5435 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5436 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5437 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5438 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5439 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5440 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5442 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5443 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5444 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5445 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5446 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5447 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5448 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5450 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5451 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5452 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5453 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5455 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5456 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5457 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5459 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5460 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5461 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5463 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5464 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5465 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5466 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5467 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5468 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5469 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5470 .type
= ARM_CP_ALIAS
,
5471 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5472 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5473 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5474 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5476 /* no .writefn needed as this can't cause an ASID change;
5477 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5479 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5480 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5481 .cp
= 15, .opc1
= 6, .crm
= 2,
5482 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5483 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5484 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5485 .writefn
= vttbr_write
},
5486 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5487 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5488 .access
= PL2_RW
, .writefn
= vttbr_write
,
5489 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5490 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5491 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5492 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5493 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5494 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5495 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5496 .access
= PL2_RW
, .resetvalue
= 0,
5497 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5498 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5499 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5500 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5501 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5502 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5503 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5504 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5505 { .name
= "TLBIALLNSNH",
5506 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5507 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5508 .writefn
= tlbiall_nsnh_write
},
5509 { .name
= "TLBIALLNSNHIS",
5510 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5511 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5512 .writefn
= tlbiall_nsnh_is_write
},
5513 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5514 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5515 .writefn
= tlbiall_hyp_write
},
5516 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5517 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5518 .writefn
= tlbiall_hyp_is_write
},
5519 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5520 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5521 .writefn
= tlbimva_hyp_write
},
5522 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5523 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5524 .writefn
= tlbimva_hyp_is_write
},
5525 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5526 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5527 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5528 .writefn
= tlbi_aa64_alle2_write
},
5529 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5530 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5531 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5532 .writefn
= tlbi_aa64_vae2_write
},
5533 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5534 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5535 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5536 .writefn
= tlbi_aa64_vae2_write
},
5537 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5538 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5539 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5540 .writefn
= tlbi_aa64_alle2is_write
},
5541 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5542 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5543 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5544 .writefn
= tlbi_aa64_vae2is_write
},
5545 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5546 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5547 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5548 .writefn
= tlbi_aa64_vae2is_write
},
5549 #ifndef CONFIG_USER_ONLY
5550 /* Unlike the other EL2-related AT operations, these must
5551 * UNDEF from EL3 if EL2 is not implemented, which is why we
5552 * define them here rather than with the rest of the AT ops.
5554 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5555 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5556 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5557 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5558 .writefn
= ats_write64
},
5559 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5560 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5561 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5562 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5563 .writefn
= ats_write64
},
5564 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5565 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5566 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5567 * to behave as if SCR.NS was 1.
5569 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5571 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5572 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5574 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5575 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5576 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5577 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5578 * reset values as IMPDEF. We choose to reset to 3 to comply with
5579 * both ARMv7 and ARMv8.
5581 .access
= PL2_RW
, .resetvalue
= 3,
5582 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5583 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5584 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5585 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5586 .writefn
= gt_cntvoff_write
,
5587 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5588 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5589 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5590 .writefn
= gt_cntvoff_write
,
5591 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5592 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5593 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5594 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5595 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5596 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5597 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5598 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5599 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5600 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5601 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5602 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5603 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5604 .resetfn
= gt_hyp_timer_reset
,
5605 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5606 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5608 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5610 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5612 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5614 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5615 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5616 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5617 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5618 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5619 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5621 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5622 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5623 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5625 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5628 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5629 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5630 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5631 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5633 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5634 .writefn
= hcr_writehigh
},
5637 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5640 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5641 return CP_ACCESS_OK
;
5643 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5646 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5647 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5648 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5649 .access
= PL2_RW
, .accessfn
= sel2_access
,
5650 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5651 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5652 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5653 .access
= PL2_RW
, .accessfn
= sel2_access
,
5654 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5657 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5660 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5661 * At Secure EL1 it traps to EL3 or EL2.
5663 if (arm_current_el(env
) == 3) {
5664 return CP_ACCESS_OK
;
5666 if (arm_is_secure_below_el3(env
)) {
5667 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5668 return CP_ACCESS_TRAP_EL2
;
5670 return CP_ACCESS_TRAP_EL3
;
5672 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5674 return CP_ACCESS_OK
;
5676 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5679 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5680 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5681 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5682 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5683 .resetfn
= scr_reset
, .writefn
= scr_write
},
5684 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5685 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5686 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5687 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5688 .writefn
= scr_write
},
5689 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5690 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5691 .access
= PL3_RW
, .resetvalue
= 0,
5692 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5694 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5695 .access
= PL3_RW
, .resetvalue
= 0,
5696 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5697 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5698 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5699 .writefn
= vbar_write
, .resetvalue
= 0,
5700 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5701 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5702 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5703 .access
= PL3_RW
, .resetvalue
= 0,
5704 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5705 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5706 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5708 /* no .writefn needed as this can't cause an ASID change;
5709 * we must provide a .raw_writefn and .resetfn because we handle
5710 * reset and migration for the AArch32 TTBCR(S), which might be
5711 * using mask and base_mask.
5713 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5714 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5715 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5716 .type
= ARM_CP_ALIAS
,
5717 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5719 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5720 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5721 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5722 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5723 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5724 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5725 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5726 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5727 .type
= ARM_CP_ALIAS
,
5728 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5730 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5731 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5732 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5733 .access
= PL3_RW
, .writefn
= vbar_write
,
5734 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5736 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5737 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5738 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5739 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5740 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5741 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5742 .access
= PL3_RW
, .resetvalue
= 0,
5743 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5744 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5745 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5746 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5748 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5749 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5750 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5752 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5753 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5754 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5756 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5757 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5758 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5759 .writefn
= tlbi_aa64_alle3is_write
},
5760 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5761 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5762 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5763 .writefn
= tlbi_aa64_vae3is_write
},
5764 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5765 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5766 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5767 .writefn
= tlbi_aa64_vae3is_write
},
5768 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5769 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5770 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5771 .writefn
= tlbi_aa64_alle3_write
},
5772 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5773 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5774 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5775 .writefn
= tlbi_aa64_vae3_write
},
5776 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5777 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5778 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5779 .writefn
= tlbi_aa64_vae3_write
},
5782 #ifndef CONFIG_USER_ONLY
5783 /* Test if system register redirection is to occur in the current state. */
5784 static bool redirect_for_e2h(CPUARMState
*env
)
5786 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5789 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5793 if (redirect_for_e2h(env
)) {
5794 /* Switch to the saved EL2 version of the register. */
5796 readfn
= ri
->readfn
;
5798 readfn
= ri
->orig_readfn
;
5800 if (readfn
== NULL
) {
5803 return readfn(env
, ri
);
5806 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5811 if (redirect_for_e2h(env
)) {
5812 /* Switch to the saved EL2 version of the register. */
5814 writefn
= ri
->writefn
;
5816 writefn
= ri
->orig_writefn
;
5818 if (writefn
== NULL
) {
5819 writefn
= raw_write
;
5821 writefn(env
, ri
, value
);
5824 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5827 uint32_t src_key
, dst_key
, new_key
;
5828 const char *src_name
, *dst_name
, *new_name
;
5829 bool (*feature
)(const ARMISARegisters
*id
);
5832 #define K(op0, op1, crn, crm, op2) \
5833 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5835 static const struct E2HAlias aliases
[] = {
5836 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5837 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5838 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5839 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5840 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5841 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5842 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5843 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5844 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5845 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5846 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5847 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5848 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5849 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5850 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5851 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5852 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5853 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5854 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5855 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5856 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5857 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5858 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5859 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5860 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5861 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5862 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5863 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5864 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5865 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5866 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5867 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5870 * Note that redirection of ZCR is mentioned in the description
5871 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5872 * not in the summary table.
5874 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5875 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5877 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5878 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5880 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
5881 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
5882 isar_feature_aa64_scxtnum
},
5884 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5885 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5891 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5892 const struct E2HAlias
*a
= &aliases
[i
];
5893 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
5896 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5900 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5901 (gpointer
)(uintptr_t)a
->src_key
);
5902 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5903 (gpointer
)(uintptr_t)a
->dst_key
);
5904 g_assert(src_reg
!= NULL
);
5905 g_assert(dst_reg
!= NULL
);
5907 /* Cross-compare names to detect typos in the keys. */
5908 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5909 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5911 /* None of the core system registers use opaque; we will. */
5912 g_assert(src_reg
->opaque
== NULL
);
5914 /* Create alias before redirection so we dup the right data. */
5915 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5917 new_reg
->name
= a
->new_name
;
5918 new_reg
->type
|= ARM_CP_ALIAS
;
5919 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5920 new_reg
->access
&= PL2_RW
| PL3_RW
;
5922 ok
= g_hash_table_insert(cpu
->cp_regs
,
5923 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
5926 src_reg
->opaque
= dst_reg
;
5927 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5928 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5929 if (!src_reg
->raw_readfn
) {
5930 src_reg
->raw_readfn
= raw_read
;
5932 if (!src_reg
->raw_writefn
) {
5933 src_reg
->raw_writefn
= raw_write
;
5935 src_reg
->readfn
= el2_e2h_read
;
5936 src_reg
->writefn
= el2_e2h_write
;
5941 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5944 int cur_el
= arm_current_el(env
);
5947 uint64_t hcr
= arm_hcr_el2_eff(env
);
5950 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5951 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5952 return CP_ACCESS_TRAP_EL2
;
5955 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5956 return CP_ACCESS_TRAP
;
5958 if (hcr
& HCR_TID2
) {
5959 return CP_ACCESS_TRAP_EL2
;
5962 } else if (hcr
& HCR_TID2
) {
5963 return CP_ACCESS_TRAP_EL2
;
5967 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5968 return CP_ACCESS_TRAP_EL2
;
5971 return CP_ACCESS_OK
;
5974 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5977 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5978 * read via a bit in OSLSR_EL1.
5982 if (ri
->state
== ARM_CP_STATE_AA32
) {
5983 oslock
= (value
== 0xC5ACCE55);
5988 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5991 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5992 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5993 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5994 * unlike DBGDRAR it is never accessible from EL0.
5995 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5998 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5999 .access
= PL0_R
, .accessfn
= access_tdra
,
6000 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6001 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
6002 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6003 .access
= PL1_R
, .accessfn
= access_tdra
,
6004 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6005 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
6006 .access
= PL0_R
, .accessfn
= access_tdra
,
6007 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6008 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6009 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
6010 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6011 .access
= PL1_RW
, .accessfn
= access_tda
,
6012 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
6015 * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external
6016 * Debug Communication Channel is not implemented.
6018 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_AA64
,
6019 .opc0
= 2, .opc1
= 3, .crn
= 0, .crm
= 1, .opc2
= 0,
6020 .access
= PL0_R
, .accessfn
= access_tda
,
6021 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6023 * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
6024 * it is unlikely a guest will care.
6025 * We don't implement the configurable EL0 access.
6027 { .name
= "DBGDSCRint", .state
= ARM_CP_STATE_AA32
,
6028 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6029 .type
= ARM_CP_ALIAS
,
6030 .access
= PL1_R
, .accessfn
= access_tda
,
6031 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
6032 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
6033 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
6034 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6035 .accessfn
= access_tdosa
,
6036 .writefn
= oslar_write
},
6037 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
6038 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
6039 .access
= PL1_R
, .resetvalue
= 10,
6040 .accessfn
= access_tdosa
,
6041 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
6042 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6043 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6044 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
6045 .access
= PL1_RW
, .accessfn
= access_tdosa
,
6046 .type
= ARM_CP_NOP
},
6047 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6048 * implement vector catch debug events yet.
6051 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6052 .access
= PL1_RW
, .accessfn
= access_tda
,
6053 .type
= ARM_CP_NOP
},
6054 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6055 * to save and restore a 32-bit guest's DBGVCR)
6057 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
6058 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
6059 .access
= PL2_RW
, .accessfn
= access_tda
,
6060 .type
= ARM_CP_NOP
| ARM_CP_EL3_NO_EL2_KEEP
},
6061 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6062 * Channel but Linux may try to access this register. The 32-bit
6063 * alias is DBGDCCINT.
6065 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
6066 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6067 .access
= PL1_RW
, .accessfn
= access_tda
,
6068 .type
= ARM_CP_NOP
},
6071 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
6072 /* 64 bit access versions of the (dummy) debug registers */
6073 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
6074 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6075 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
6076 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6080 * Check for traps to RAS registers, which are controlled
6081 * by HCR_EL2.TERR and SCR_EL3.TERR.
6083 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6086 int el
= arm_current_el(env
);
6088 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6089 return CP_ACCESS_TRAP_EL2
;
6091 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6092 return CP_ACCESS_TRAP_EL3
;
6094 return CP_ACCESS_OK
;
6097 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6099 int el
= arm_current_el(env
);
6101 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6102 return env
->cp15
.vdisr_el2
;
6104 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6105 return 0; /* RAZ/WI */
6107 return env
->cp15
.disr_el1
;
6110 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6112 int el
= arm_current_el(env
);
6114 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6115 env
->cp15
.vdisr_el2
= val
;
6118 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6119 return; /* RAZ/WI */
6121 env
->cp15
.disr_el1
= val
;
6125 * Minimal RAS implementation with no Error Records.
6126 * Which means that all of the Error Record registers:
6134 * ERXPFGCDN_EL1 (RASv1p1)
6135 * ERXPFGCTL_EL1 (RASv1p1)
6136 * ERXPFGF_EL1 (RASv1p1)
6140 * may generate UNDEFINED, which is the effect we get by not
6141 * listing them at all.
6143 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6144 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6145 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6146 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6147 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6148 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6149 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6150 .access
= PL1_R
, .accessfn
= access_terr
,
6151 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6152 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6153 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6154 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6155 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6156 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6157 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6161 * Return the exception level to which exceptions should be taken
6162 * via SVEAccessTrap. This excludes the check for whether the exception
6163 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6164 * be found by testing 0 < fp_exception_el < sve_exception_el.
6166 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6167 * pseudocode does *not* separate out the FP trap checks, but has them
6168 * all in one function.
6170 int sve_exception_el(CPUARMState
*env
, int el
)
6172 #ifndef CONFIG_USER_ONLY
6173 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
6175 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6176 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6189 * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE).
6192 if (hcr_el2
& HCR_E2H
) {
6193 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6195 if (el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
6203 } else if (arm_is_el2_enabled(env
)) {
6204 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6210 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6211 if (arm_feature(env
, ARM_FEATURE_EL3
)
6212 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6219 uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
6223 start_len
= MIN(start_len
, ARM_MAX_VQ
- 1);
6224 end_len
= start_len
;
6226 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
6227 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
6228 assert(end_len
< start_len
);
6234 * Given that SVE is enabled, return the vector length for EL.
6236 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
6238 ARMCPU
*cpu
= env_archcpu(env
);
6239 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
6242 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6243 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
6245 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6246 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
6248 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6249 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
6252 return aarch64_sve_zcr_get_valid_len(cpu
, zcr_len
);
6255 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6258 int cur_el
= arm_current_el(env
);
6259 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
6262 /* Bits other than [3:0] are RAZ/WI. */
6263 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6264 raw_write(env
, ri
, value
& 0xf);
6267 * Because we arrived here, we know both FP and SVE are enabled;
6268 * otherwise we would have trapped access to the ZCR_ELn register.
6270 new_len
= sve_zcr_len_for_el(env
, cur_el
);
6271 if (new_len
< old_len
) {
6272 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6276 static const ARMCPRegInfo zcr_reginfo
[] = {
6277 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6278 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6279 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6280 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6281 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6282 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6283 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6284 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6285 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6286 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6287 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6288 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6289 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6290 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6291 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6294 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6296 CPUARMState
*env
= &cpu
->env
;
6298 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6299 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6301 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6303 if (env
->cpu_watchpoint
[n
]) {
6304 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6305 env
->cpu_watchpoint
[n
] = NULL
;
6308 if (!FIELD_EX64(wcr
, DBGWCR
, E
)) {
6309 /* E bit clear : watchpoint disabled */
6313 switch (FIELD_EX64(wcr
, DBGWCR
, LSC
)) {
6315 /* LSC 00 is reserved and must behave as if the wp is disabled */
6318 flags
|= BP_MEM_READ
;
6321 flags
|= BP_MEM_WRITE
;
6324 flags
|= BP_MEM_ACCESS
;
6328 /* Attempts to use both MASK and BAS fields simultaneously are
6329 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6330 * thus generating a watchpoint for every byte in the masked region.
6332 mask
= FIELD_EX64(wcr
, DBGWCR
, MASK
);
6333 if (mask
== 1 || mask
== 2) {
6334 /* Reserved values of MASK; we must act as if the mask value was
6335 * some non-reserved value, or as if the watchpoint were disabled.
6336 * We choose the latter.
6340 /* Watchpoint covers an aligned area up to 2GB in size */
6342 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6343 * whether the watchpoint fires when the unmasked bits match; we opt
6344 * to generate the exceptions.
6348 /* Watchpoint covers bytes defined by the byte address select bits */
6349 int bas
= FIELD_EX64(wcr
, DBGWCR
, BAS
);
6352 if (extract64(wvr
, 2, 1)) {
6353 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6354 * ignored, and BAS[3:0] define which bytes to watch.
6360 /* This must act as if the watchpoint is disabled */
6364 /* The BAS bits are supposed to be programmed to indicate a contiguous
6365 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6366 * we fire for each byte in the word/doubleword addressed by the WVR.
6367 * We choose to ignore any non-zero bits after the first range of 1s.
6369 basstart
= ctz32(bas
);
6370 len
= cto32(bas
>> basstart
);
6374 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6375 &env
->cpu_watchpoint
[n
]);
6378 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6381 CPUARMState
*env
= &cpu
->env
;
6383 /* Completely clear out existing QEMU watchpoints and our array, to
6384 * avoid possible stale entries following migration load.
6386 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6387 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6389 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6390 hw_watchpoint_update(cpu
, i
);
6394 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6397 ARMCPU
*cpu
= env_archcpu(env
);
6401 * Bits [1:0] are RES0.
6403 * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
6404 * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
6405 * they contain the value written. It is CONSTRAINED UNPREDICTABLE
6406 * whether the RESS bits are ignored when comparing an address.
6408 * Therefore we are allowed to compare the entire register, which lets
6409 * us avoid considering whether or not FEAT_LVA is actually enabled.
6413 raw_write(env
, ri
, value
);
6414 hw_watchpoint_update(cpu
, i
);
6417 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6420 ARMCPU
*cpu
= env_archcpu(env
);
6423 raw_write(env
, ri
, value
);
6424 hw_watchpoint_update(cpu
, i
);
6427 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6429 CPUARMState
*env
= &cpu
->env
;
6430 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6431 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6436 if (env
->cpu_breakpoint
[n
]) {
6437 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6438 env
->cpu_breakpoint
[n
] = NULL
;
6441 if (!extract64(bcr
, 0, 1)) {
6442 /* E bit clear : watchpoint disabled */
6446 bt
= extract64(bcr
, 20, 4);
6449 case 4: /* unlinked address mismatch (reserved if AArch64) */
6450 case 5: /* linked address mismatch (reserved if AArch64) */
6451 qemu_log_mask(LOG_UNIMP
,
6452 "arm: address mismatch breakpoint types not implemented\n");
6454 case 0: /* unlinked address match */
6455 case 1: /* linked address match */
6458 * Bits [1:0] are RES0.
6460 * It is IMPLEMENTATION DEFINED whether bits [63:49]
6461 * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
6462 * of the VA field ([48] or [52] for FEAT_LVA), or whether the
6463 * value is read as written. It is CONSTRAINED UNPREDICTABLE
6464 * whether the RESS bits are ignored when comparing an address.
6465 * Therefore we are allowed to compare the entire register, which
6466 * lets us avoid considering whether FEAT_LVA is actually enabled.
6468 * The BAS field is used to allow setting breakpoints on 16-bit
6469 * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6470 * a bp will fire if the addresses covered by the bp and the addresses
6471 * covered by the insn overlap but the insn doesn't start at the
6472 * start of the bp address range. We choose to require the insn and
6473 * the bp to have the same address. The constraints on writing to
6474 * BAS enforced in dbgbcr_write mean we have only four cases:
6475 * 0b0000 => no breakpoint
6476 * 0b0011 => breakpoint on addr
6477 * 0b1100 => breakpoint on addr + 2
6478 * 0b1111 => breakpoint on addr
6479 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6481 int bas
= extract64(bcr
, 5, 4);
6491 case 2: /* unlinked context ID match */
6492 case 8: /* unlinked VMID match (reserved if no EL2) */
6493 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6494 qemu_log_mask(LOG_UNIMP
,
6495 "arm: unlinked context breakpoint types not implemented\n");
6497 case 9: /* linked VMID match (reserved if no EL2) */
6498 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6499 case 3: /* linked context ID match */
6501 /* We must generate no events for Linked context matches (unless
6502 * they are linked to by some other bp/wp, which is handled in
6503 * updates for the linking bp/wp). We choose to also generate no events
6504 * for reserved values.
6509 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6512 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6515 CPUARMState
*env
= &cpu
->env
;
6517 /* Completely clear out existing QEMU breakpoints and our array, to
6518 * avoid possible stale entries following migration load.
6520 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6521 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6523 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6524 hw_breakpoint_update(cpu
, i
);
6528 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6531 ARMCPU
*cpu
= env_archcpu(env
);
6534 raw_write(env
, ri
, value
);
6535 hw_breakpoint_update(cpu
, i
);
6538 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6541 ARMCPU
*cpu
= env_archcpu(env
);
6544 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6547 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6548 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6550 raw_write(env
, ri
, value
);
6551 hw_breakpoint_update(cpu
, i
);
6554 static void define_debug_regs(ARMCPU
*cpu
)
6556 /* Define v7 and v8 architectural debug registers.
6557 * These are just dummy implementations for now.
6560 int wrps
, brps
, ctx_cmps
;
6563 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
6564 * use AArch32. Given that bit 15 is RES1, if the value is 0 then
6565 * the register must not exist for this cpu.
6567 if (cpu
->isar
.dbgdidr
!= 0) {
6568 ARMCPRegInfo dbgdidr
= {
6569 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0,
6570 .opc1
= 0, .opc2
= 0,
6571 .access
= PL0_R
, .accessfn
= access_tda
,
6572 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6574 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6577 brps
= arm_num_brps(cpu
);
6578 wrps
= arm_num_wrps(cpu
);
6579 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6581 assert(ctx_cmps
<= brps
);
6583 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6585 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6586 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6589 for (i
= 0; i
< brps
; i
++) {
6590 char *dbgbvr_el1_name
= g_strdup_printf("DBGBVR%d_EL1", i
);
6591 char *dbgbcr_el1_name
= g_strdup_printf("DBGBCR%d_EL1", i
);
6592 ARMCPRegInfo dbgregs
[] = {
6593 { .name
= dbgbvr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6594 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6595 .access
= PL1_RW
, .accessfn
= access_tda
,
6596 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6597 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6599 { .name
= dbgbcr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6600 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6601 .access
= PL1_RW
, .accessfn
= access_tda
,
6602 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6603 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6606 define_arm_cp_regs(cpu
, dbgregs
);
6607 g_free(dbgbvr_el1_name
);
6608 g_free(dbgbcr_el1_name
);
6611 for (i
= 0; i
< wrps
; i
++) {
6612 char *dbgwvr_el1_name
= g_strdup_printf("DBGWVR%d_EL1", i
);
6613 char *dbgwcr_el1_name
= g_strdup_printf("DBGWCR%d_EL1", i
);
6614 ARMCPRegInfo dbgregs
[] = {
6615 { .name
= dbgwvr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6616 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6617 .access
= PL1_RW
, .accessfn
= access_tda
,
6618 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6619 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6621 { .name
= dbgwcr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6622 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6623 .access
= PL1_RW
, .accessfn
= access_tda
,
6624 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6625 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6628 define_arm_cp_regs(cpu
, dbgregs
);
6629 g_free(dbgwvr_el1_name
);
6630 g_free(dbgwcr_el1_name
);
6634 static void define_pmu_regs(ARMCPU
*cpu
)
6637 * v7 performance monitor control register: same implementor
6638 * field as main ID register, and we implement four counters in
6639 * addition to the cycle count register.
6641 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6642 ARMCPRegInfo pmcr
= {
6643 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6645 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6646 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6647 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6648 .raw_writefn
= raw_write
,
6650 ARMCPRegInfo pmcr64
= {
6651 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6652 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6653 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6655 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6656 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6657 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6660 define_one_arm_cp_reg(cpu
, &pmcr
);
6661 define_one_arm_cp_reg(cpu
, &pmcr64
);
6662 for (i
= 0; i
< pmcrn
; i
++) {
6663 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6664 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6665 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6666 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6667 ARMCPRegInfo pmev_regs
[] = {
6668 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6669 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6670 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6671 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6672 .accessfn
= pmreg_access_xevcntr
},
6673 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6674 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6675 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6677 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6678 .raw_readfn
= pmevcntr_rawread
,
6679 .raw_writefn
= pmevcntr_rawwrite
},
6680 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6681 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6682 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6683 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6684 .accessfn
= pmreg_access
},
6685 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6686 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6687 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6689 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6690 .raw_writefn
= pmevtyper_rawwrite
},
6692 define_arm_cp_regs(cpu
, pmev_regs
);
6693 g_free(pmevcntr_name
);
6694 g_free(pmevcntr_el0_name
);
6695 g_free(pmevtyper_name
);
6696 g_free(pmevtyper_el0_name
);
6698 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6699 ARMCPRegInfo v81_pmu_regs
[] = {
6700 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6701 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6702 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6703 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6704 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6705 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6706 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6707 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6709 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6711 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6712 static const ARMCPRegInfo v84_pmmir
= {
6713 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6714 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6715 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6718 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6722 /* We don't know until after realize whether there's a GICv3
6723 * attached, and that is what registers the gicv3 sysregs.
6724 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6727 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6729 ARMCPU
*cpu
= env_archcpu(env
);
6730 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6732 if (env
->gicv3state
) {
6738 #ifndef CONFIG_USER_ONLY
6739 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6741 ARMCPU
*cpu
= env_archcpu(env
);
6742 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6744 if (env
->gicv3state
) {
6751 /* Shared logic between LORID and the rest of the LOR* registers.
6752 * Secure state exclusion has already been dealt with.
6754 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6755 const ARMCPRegInfo
*ri
, bool isread
)
6757 int el
= arm_current_el(env
);
6759 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6760 return CP_ACCESS_TRAP_EL2
;
6762 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6763 return CP_ACCESS_TRAP_EL3
;
6765 return CP_ACCESS_OK
;
6768 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6769 const ARMCPRegInfo
*ri
, bool isread
)
6771 if (arm_is_secure_below_el3(env
)) {
6772 /* Access denied in secure mode. */
6773 return CP_ACCESS_TRAP
;
6775 return access_lor_ns(env
, ri
, isread
);
6779 * A trivial implementation of ARMv8.1-LOR leaves all of these
6780 * registers fixed at 0, which indicates that there are zero
6781 * supported Limited Ordering regions.
6783 static const ARMCPRegInfo lor_reginfo
[] = {
6784 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6785 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6786 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6787 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6788 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6789 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6790 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6791 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6792 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6793 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6794 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6795 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6796 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6797 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6798 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6799 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6800 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6801 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6802 .access
= PL1_R
, .accessfn
= access_lor_ns
,
6803 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6806 #ifdef TARGET_AARCH64
6807 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6810 int el
= arm_current_el(env
);
6813 arm_is_el2_enabled(env
) &&
6814 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6815 return CP_ACCESS_TRAP_EL2
;
6818 arm_feature(env
, ARM_FEATURE_EL3
) &&
6819 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6820 return CP_ACCESS_TRAP_EL3
;
6822 return CP_ACCESS_OK
;
6825 static const ARMCPRegInfo pauth_reginfo
[] = {
6826 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6827 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6828 .access
= PL1_RW
, .accessfn
= access_pauth
,
6829 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6830 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6831 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6832 .access
= PL1_RW
, .accessfn
= access_pauth
,
6833 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6834 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6835 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6836 .access
= PL1_RW
, .accessfn
= access_pauth
,
6837 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6838 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6839 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6840 .access
= PL1_RW
, .accessfn
= access_pauth
,
6841 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6842 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6843 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6844 .access
= PL1_RW
, .accessfn
= access_pauth
,
6845 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6846 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6847 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6848 .access
= PL1_RW
, .accessfn
= access_pauth
,
6849 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6850 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6851 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6852 .access
= PL1_RW
, .accessfn
= access_pauth
,
6853 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6854 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6855 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6856 .access
= PL1_RW
, .accessfn
= access_pauth
,
6857 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6858 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6859 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6860 .access
= PL1_RW
, .accessfn
= access_pauth
,
6861 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6862 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6863 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6864 .access
= PL1_RW
, .accessfn
= access_pauth
,
6865 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6868 static const ARMCPRegInfo tlbirange_reginfo
[] = {
6869 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
6870 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
6871 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6872 .writefn
= tlbi_aa64_rvae1is_write
},
6873 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
6874 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
6875 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6876 .writefn
= tlbi_aa64_rvae1is_write
},
6877 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
6878 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
6879 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6880 .writefn
= tlbi_aa64_rvae1is_write
},
6881 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
6882 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
6883 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6884 .writefn
= tlbi_aa64_rvae1is_write
},
6885 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
6886 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
6887 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6888 .writefn
= tlbi_aa64_rvae1is_write
},
6889 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
6890 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
6891 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6892 .writefn
= tlbi_aa64_rvae1is_write
},
6893 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
6894 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
6895 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6896 .writefn
= tlbi_aa64_rvae1is_write
},
6897 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
6898 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
6899 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6900 .writefn
= tlbi_aa64_rvae1is_write
},
6901 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
6902 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
6903 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6904 .writefn
= tlbi_aa64_rvae1_write
},
6905 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
6906 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
6907 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6908 .writefn
= tlbi_aa64_rvae1_write
},
6909 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
6910 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
6911 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6912 .writefn
= tlbi_aa64_rvae1_write
},
6913 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
6914 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
6915 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6916 .writefn
= tlbi_aa64_rvae1_write
},
6917 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
6918 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
6919 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6920 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
6921 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
6922 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6923 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
6924 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
6925 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6926 .writefn
= tlbi_aa64_rvae2is_write
},
6927 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
6928 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
6929 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6930 .writefn
= tlbi_aa64_rvae2is_write
},
6931 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
6932 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
6933 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6934 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
6935 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
6936 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6937 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
6938 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
6939 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6940 .writefn
= tlbi_aa64_rvae2is_write
},
6941 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
6942 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
6943 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6944 .writefn
= tlbi_aa64_rvae2is_write
},
6945 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
6946 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
6947 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6948 .writefn
= tlbi_aa64_rvae2_write
},
6949 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
6950 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
6951 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6952 .writefn
= tlbi_aa64_rvae2_write
},
6953 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
6954 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
6955 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6956 .writefn
= tlbi_aa64_rvae3is_write
},
6957 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
6958 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
6959 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6960 .writefn
= tlbi_aa64_rvae3is_write
},
6961 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
6962 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
6963 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6964 .writefn
= tlbi_aa64_rvae3is_write
},
6965 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
6966 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
6967 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6968 .writefn
= tlbi_aa64_rvae3is_write
},
6969 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
6970 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
6971 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6972 .writefn
= tlbi_aa64_rvae3_write
},
6973 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
6974 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
6975 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6976 .writefn
= tlbi_aa64_rvae3_write
},
6979 static const ARMCPRegInfo tlbios_reginfo
[] = {
6980 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
6981 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
6982 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6983 .writefn
= tlbi_aa64_vmalle1is_write
},
6984 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
6985 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
6986 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6987 .writefn
= tlbi_aa64_vae1is_write
},
6988 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
6989 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
6990 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6991 .writefn
= tlbi_aa64_vmalle1is_write
},
6992 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
6993 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
6994 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6995 .writefn
= tlbi_aa64_vae1is_write
},
6996 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
6997 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
6998 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6999 .writefn
= tlbi_aa64_vae1is_write
},
7000 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7001 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7002 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7003 .writefn
= tlbi_aa64_vae1is_write
},
7004 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7005 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7006 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7007 .writefn
= tlbi_aa64_alle2is_write
},
7008 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7009 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7010 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7011 .writefn
= tlbi_aa64_vae2is_write
},
7012 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7013 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7014 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7015 .writefn
= tlbi_aa64_alle1is_write
},
7016 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7017 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7018 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7019 .writefn
= tlbi_aa64_vae2is_write
},
7020 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7021 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7022 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7023 .writefn
= tlbi_aa64_alle1is_write
},
7024 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7025 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7026 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7027 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7028 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7029 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7030 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7031 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7032 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7033 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7034 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7035 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7036 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7037 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7038 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7039 .writefn
= tlbi_aa64_alle3is_write
},
7040 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7041 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7042 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7043 .writefn
= tlbi_aa64_vae3is_write
},
7044 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7045 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7046 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7047 .writefn
= tlbi_aa64_vae3is_write
},
7050 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7055 /* Success sets NZCV = 0000. */
7056 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7058 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7060 * ??? Failed, for unknown reasons in the crypto subsystem.
7061 * The best we can do is log the reason and return the
7062 * timed-out indication to the guest. There is no reason
7063 * we know to expect this failure to be transitory, so the
7064 * guest may well hang retrying the operation.
7066 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7067 ri
->name
, error_get_pretty(err
));
7070 env
->ZF
= 0; /* NZCF = 0100 */
7076 /* We do not support re-seeding, so the two registers operate the same. */
7077 static const ARMCPRegInfo rndr_reginfo
[] = {
7078 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7079 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7080 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7081 .access
= PL0_R
, .readfn
= rndr_readfn
},
7082 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7083 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7084 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7085 .access
= PL0_R
, .readfn
= rndr_readfn
},
7088 #ifndef CONFIG_USER_ONLY
7089 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7092 ARMCPU
*cpu
= env_archcpu(env
);
7093 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7094 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7095 uint64_t vaddr_in
= (uint64_t) value
;
7096 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7098 int mem_idx
= cpu_mmu_index(env
, false);
7100 /* This won't be crossing page boundaries */
7101 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7107 /* RCU lock is already being held */
7108 mr
= memory_region_from_host(haddr
, &offset
);
7111 memory_region_writeback(mr
, offset
, dline_size
);
7116 static const ARMCPRegInfo dcpop_reg
[] = {
7117 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7118 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7119 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7120 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7123 static const ARMCPRegInfo dcpodp_reg
[] = {
7124 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7125 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7126 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7127 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7129 #endif /*CONFIG_USER_ONLY*/
7131 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7134 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7135 return CP_ACCESS_TRAP_EL2
;
7138 return CP_ACCESS_OK
;
7141 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7144 int el
= arm_current_el(env
);
7146 if (el
< 2 && arm_is_el2_enabled(env
)) {
7147 uint64_t hcr
= arm_hcr_el2_eff(env
);
7148 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7149 return CP_ACCESS_TRAP_EL2
;
7153 arm_feature(env
, ARM_FEATURE_EL3
) &&
7154 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7155 return CP_ACCESS_TRAP_EL3
;
7157 return CP_ACCESS_OK
;
7160 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7162 return env
->pstate
& PSTATE_TCO
;
7165 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7167 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7170 static const ARMCPRegInfo mte_reginfo
[] = {
7171 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7172 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7173 .access
= PL1_RW
, .accessfn
= access_mte
,
7174 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7175 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7176 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7177 .access
= PL1_RW
, .accessfn
= access_mte
,
7178 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7179 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7180 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7181 .access
= PL2_RW
, .accessfn
= access_mte
,
7182 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7183 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7184 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7186 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7187 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7188 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7189 .access
= PL1_RW
, .accessfn
= access_mte
,
7190 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7191 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7192 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7193 .access
= PL1_RW
, .accessfn
= access_mte
,
7194 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7195 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7196 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7197 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7198 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7199 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7200 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7201 .type
= ARM_CP_NO_RAW
,
7202 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7203 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7204 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7205 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7206 .accessfn
= aa64_cacheop_poc_access
},
7207 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7208 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7209 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7210 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7211 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7212 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7213 .accessfn
= aa64_cacheop_poc_access
},
7214 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7215 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7216 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7217 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7218 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7219 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7220 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7221 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7222 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7223 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7224 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7225 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7226 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7227 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7228 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7231 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7232 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7233 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7234 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7237 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7238 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7239 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7240 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7241 .accessfn
= aa64_cacheop_poc_access
},
7242 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7243 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7244 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7245 .accessfn
= aa64_cacheop_poc_access
},
7246 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7247 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7248 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7249 .accessfn
= aa64_cacheop_poc_access
},
7250 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7251 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7252 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7253 .accessfn
= aa64_cacheop_poc_access
},
7254 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7255 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7256 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7257 .accessfn
= aa64_cacheop_poc_access
},
7258 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7259 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7260 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7261 .accessfn
= aa64_cacheop_poc_access
},
7262 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7263 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7264 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7265 .accessfn
= aa64_cacheop_poc_access
},
7266 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7267 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7268 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7269 .accessfn
= aa64_cacheop_poc_access
},
7270 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7271 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7272 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7273 #ifndef CONFIG_USER_ONLY
7274 /* Avoid overhead of an access check that always passes in user-mode */
7275 .accessfn
= aa64_zva_access
,
7278 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7279 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7280 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7281 #ifndef CONFIG_USER_ONLY
7282 /* Avoid overhead of an access check that always passes in user-mode */
7283 .accessfn
= aa64_zva_access
,
7288 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7291 uint64_t hcr
= arm_hcr_el2_eff(env
);
7292 int el
= arm_current_el(env
);
7294 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7295 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7296 if (hcr
& HCR_TGE
) {
7297 return CP_ACCESS_TRAP_EL2
;
7299 return CP_ACCESS_TRAP
;
7301 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7302 return CP_ACCESS_TRAP_EL2
;
7304 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7305 return CP_ACCESS_TRAP_EL2
;
7308 && arm_feature(env
, ARM_FEATURE_EL3
)
7309 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7310 return CP_ACCESS_TRAP_EL3
;
7312 return CP_ACCESS_OK
;
7315 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7316 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7317 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7318 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7319 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7320 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7321 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7322 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7323 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7324 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7325 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7326 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7327 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7328 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7329 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7331 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7333 #endif /* TARGET_AARCH64 */
7335 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7338 int el
= arm_current_el(env
);
7341 uint64_t sctlr
= arm_sctlr(env
, el
);
7342 if (!(sctlr
& SCTLR_EnRCTX
)) {
7343 return CP_ACCESS_TRAP
;
7345 } else if (el
== 1) {
7346 uint64_t hcr
= arm_hcr_el2_eff(env
);
7348 return CP_ACCESS_TRAP_EL2
;
7351 return CP_ACCESS_OK
;
7354 static const ARMCPRegInfo predinv_reginfo
[] = {
7355 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7356 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7357 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7358 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7359 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7360 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7361 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7362 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7363 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7365 * Note the AArch32 opcodes have a different OPC1.
7367 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7368 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7369 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7370 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7371 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7372 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7373 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7374 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7375 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7378 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7380 /* Read the high 32 bits of the current CCSIDR */
7381 return extract64(ccsidr_read(env
, ri
), 32, 32);
7384 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7385 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7386 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7388 .accessfn
= access_aa64_tid2
,
7389 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7392 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7395 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7396 return CP_ACCESS_TRAP_EL2
;
7399 return CP_ACCESS_OK
;
7402 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7405 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7406 return access_aa64_tid3(env
, ri
, isread
);
7409 return CP_ACCESS_OK
;
7412 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7415 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7416 return CP_ACCESS_TRAP_EL2
;
7419 return CP_ACCESS_OK
;
7422 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7423 const ARMCPRegInfo
*ri
, bool isread
)
7426 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7427 * in v7A, not in v8A.
7429 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7430 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7431 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7432 return CP_ACCESS_TRAP_EL2
;
7434 return CP_ACCESS_OK
;
7437 static const ARMCPRegInfo jazelle_regs
[] = {
7439 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7440 .access
= PL1_R
, .accessfn
= access_jazelle
,
7441 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7443 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7444 .accessfn
= access_joscr_jmcr
,
7445 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7447 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7448 .accessfn
= access_joscr_jmcr
,
7449 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7452 static const ARMCPRegInfo contextidr_el2
= {
7453 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7454 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7456 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7459 static const ARMCPRegInfo vhe_reginfo
[] = {
7460 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7461 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7462 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7463 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7464 #ifndef CONFIG_USER_ONLY
7465 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7466 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7468 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7469 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7470 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7471 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7472 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7473 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7474 .resetfn
= gt_hv_timer_reset
,
7475 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7476 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7478 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7480 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7481 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7482 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7483 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7484 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7485 .access
= PL2_RW
, .accessfn
= e2h_access
,
7486 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7487 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7488 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7489 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7490 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7491 .access
= PL2_RW
, .accessfn
= e2h_access
,
7492 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7493 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7494 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7495 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7496 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7497 .access
= PL2_RW
, .accessfn
= e2h_access
,
7498 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7499 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7500 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7501 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7502 .access
= PL2_RW
, .accessfn
= e2h_access
,
7503 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7504 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7505 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7506 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7507 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7508 .access
= PL2_RW
, .accessfn
= e2h_access
,
7509 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7510 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7511 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7512 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7513 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7514 .access
= PL2_RW
, .accessfn
= e2h_access
,
7515 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7519 #ifndef CONFIG_USER_ONLY
7520 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7521 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7522 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7523 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7524 .writefn
= ats_write64
},
7525 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7526 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7527 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7528 .writefn
= ats_write64
},
7531 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7532 { .name
= "ATS1CPRP",
7533 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7534 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7535 .writefn
= ats_write
},
7536 { .name
= "ATS1CPWP",
7537 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7538 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7539 .writefn
= ats_write
},
7544 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7545 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7546 * is non-zero, which is never for ARMv7, optionally in ARMv8
7547 * and mandatorily for ARMv8.2 and up.
7548 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7549 * implementation is RAZ/WI we can ignore this detail, as we
7552 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7553 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7554 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7555 .access
= PL1_RW
, .accessfn
= access_tacr
,
7556 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7557 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7558 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7559 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7563 void register_cp_regs_for_features(ARMCPU
*cpu
)
7565 /* Register all the coprocessor registers based on feature bits */
7566 CPUARMState
*env
= &cpu
->env
;
7567 if (arm_feature(env
, ARM_FEATURE_M
)) {
7568 /* M profile has no coprocessor registers */
7572 define_arm_cp_regs(cpu
, cp_reginfo
);
7573 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7574 /* Must go early as it is full of wildcards that may be
7575 * overridden by later definitions.
7577 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7580 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7581 /* The ID registers all have impdef reset values */
7582 ARMCPRegInfo v6_idregs
[] = {
7583 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7584 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7585 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7586 .accessfn
= access_aa32_tid3
,
7587 .resetvalue
= cpu
->isar
.id_pfr0
},
7588 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7589 * the value of the GIC field until after we define these regs.
7591 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7592 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7593 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7594 .accessfn
= access_aa32_tid3
,
7595 .readfn
= id_pfr1_read
,
7596 .writefn
= arm_cp_write_ignore
},
7597 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7598 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7599 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7600 .accessfn
= access_aa32_tid3
,
7601 .resetvalue
= cpu
->isar
.id_dfr0
},
7602 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7603 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7604 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7605 .accessfn
= access_aa32_tid3
,
7606 .resetvalue
= cpu
->id_afr0
},
7607 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7608 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7609 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7610 .accessfn
= access_aa32_tid3
,
7611 .resetvalue
= cpu
->isar
.id_mmfr0
},
7612 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7613 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7614 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7615 .accessfn
= access_aa32_tid3
,
7616 .resetvalue
= cpu
->isar
.id_mmfr1
},
7617 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7618 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7619 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7620 .accessfn
= access_aa32_tid3
,
7621 .resetvalue
= cpu
->isar
.id_mmfr2
},
7622 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7623 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7624 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7625 .accessfn
= access_aa32_tid3
,
7626 .resetvalue
= cpu
->isar
.id_mmfr3
},
7627 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7628 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7629 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7630 .accessfn
= access_aa32_tid3
,
7631 .resetvalue
= cpu
->isar
.id_isar0
},
7632 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7633 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7634 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7635 .accessfn
= access_aa32_tid3
,
7636 .resetvalue
= cpu
->isar
.id_isar1
},
7637 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7638 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7639 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7640 .accessfn
= access_aa32_tid3
,
7641 .resetvalue
= cpu
->isar
.id_isar2
},
7642 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7643 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7644 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7645 .accessfn
= access_aa32_tid3
,
7646 .resetvalue
= cpu
->isar
.id_isar3
},
7647 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7648 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7649 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7650 .accessfn
= access_aa32_tid3
,
7651 .resetvalue
= cpu
->isar
.id_isar4
},
7652 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7653 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7654 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7655 .accessfn
= access_aa32_tid3
,
7656 .resetvalue
= cpu
->isar
.id_isar5
},
7657 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7658 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7659 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7660 .accessfn
= access_aa32_tid3
,
7661 .resetvalue
= cpu
->isar
.id_mmfr4
},
7662 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7663 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7664 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7665 .accessfn
= access_aa32_tid3
,
7666 .resetvalue
= cpu
->isar
.id_isar6
},
7668 define_arm_cp_regs(cpu
, v6_idregs
);
7669 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7671 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7673 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7674 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7676 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7677 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7678 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7680 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7681 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7683 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7684 ARMCPRegInfo clidr
= {
7685 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7686 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7687 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7688 .accessfn
= access_aa64_tid2
,
7689 .resetvalue
= cpu
->clidr
7691 define_one_arm_cp_reg(cpu
, &clidr
);
7692 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7693 define_debug_regs(cpu
);
7694 define_pmu_regs(cpu
);
7696 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7698 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7699 /* AArch64 ID registers, which all have impdef reset values.
7700 * Note that within the ID register ranges the unused slots
7701 * must all RAZ, not UNDEF; future architecture versions may
7702 * define new registers here.
7704 ARMCPRegInfo v8_idregs
[] = {
7706 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7707 * emulation because we don't know the right value for the
7708 * GIC field until after we define these regs.
7710 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7711 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7713 #ifdef CONFIG_USER_ONLY
7714 .type
= ARM_CP_CONST
,
7715 .resetvalue
= cpu
->isar
.id_aa64pfr0
7717 .type
= ARM_CP_NO_RAW
,
7718 .accessfn
= access_aa64_tid3
,
7719 .readfn
= id_aa64pfr0_read
,
7720 .writefn
= arm_cp_write_ignore
7723 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7724 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7725 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7726 .accessfn
= access_aa64_tid3
,
7727 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7728 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7729 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7730 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7731 .accessfn
= access_aa64_tid3
,
7733 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7734 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7735 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7736 .accessfn
= access_aa64_tid3
,
7738 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7739 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7740 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7741 .accessfn
= access_aa64_tid3
,
7742 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
7743 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7744 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7745 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7746 .accessfn
= access_aa64_tid3
,
7748 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7749 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7750 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7751 .accessfn
= access_aa64_tid3
,
7753 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7754 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7755 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7756 .accessfn
= access_aa64_tid3
,
7758 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7759 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7760 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7761 .accessfn
= access_aa64_tid3
,
7762 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7763 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7764 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7765 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7766 .accessfn
= access_aa64_tid3
,
7767 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7768 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7769 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7770 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7771 .accessfn
= access_aa64_tid3
,
7773 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7774 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7775 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7776 .accessfn
= access_aa64_tid3
,
7778 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7779 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7780 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7781 .accessfn
= access_aa64_tid3
,
7782 .resetvalue
= cpu
->id_aa64afr0
},
7783 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7784 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7785 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7786 .accessfn
= access_aa64_tid3
,
7787 .resetvalue
= cpu
->id_aa64afr1
},
7788 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7789 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7790 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7791 .accessfn
= access_aa64_tid3
,
7793 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7794 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7795 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7796 .accessfn
= access_aa64_tid3
,
7798 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7799 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7800 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7801 .accessfn
= access_aa64_tid3
,
7802 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7803 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7804 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7805 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7806 .accessfn
= access_aa64_tid3
,
7807 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7808 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7809 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7810 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7811 .accessfn
= access_aa64_tid3
,
7813 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7814 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7815 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7816 .accessfn
= access_aa64_tid3
,
7818 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7819 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7820 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7821 .accessfn
= access_aa64_tid3
,
7823 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7824 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7825 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7826 .accessfn
= access_aa64_tid3
,
7828 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7829 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7830 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7831 .accessfn
= access_aa64_tid3
,
7833 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7834 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7835 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7836 .accessfn
= access_aa64_tid3
,
7838 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7839 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7840 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7841 .accessfn
= access_aa64_tid3
,
7842 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7843 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7844 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7845 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7846 .accessfn
= access_aa64_tid3
,
7847 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7848 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7849 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7850 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7851 .accessfn
= access_aa64_tid3
,
7852 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7853 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7854 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7855 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7856 .accessfn
= access_aa64_tid3
,
7858 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7859 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7860 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7861 .accessfn
= access_aa64_tid3
,
7863 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7864 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7865 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7866 .accessfn
= access_aa64_tid3
,
7868 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7869 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7870 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7871 .accessfn
= access_aa64_tid3
,
7873 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7874 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7875 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7876 .accessfn
= access_aa64_tid3
,
7878 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7879 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7880 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7881 .accessfn
= access_aa64_tid3
,
7882 .resetvalue
= cpu
->isar
.mvfr0
},
7883 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7884 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7885 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7886 .accessfn
= access_aa64_tid3
,
7887 .resetvalue
= cpu
->isar
.mvfr1
},
7888 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7889 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7890 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7891 .accessfn
= access_aa64_tid3
,
7892 .resetvalue
= cpu
->isar
.mvfr2
},
7893 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7894 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7895 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7896 .accessfn
= access_aa64_tid3
,
7898 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
7899 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7900 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7901 .accessfn
= access_aa64_tid3
,
7902 .resetvalue
= cpu
->isar
.id_pfr2
},
7903 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7904 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7905 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7906 .accessfn
= access_aa64_tid3
,
7908 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7909 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7910 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7911 .accessfn
= access_aa64_tid3
,
7913 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7914 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7915 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7916 .accessfn
= access_aa64_tid3
,
7918 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7919 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7920 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7921 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7922 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7923 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7924 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7925 .resetvalue
= cpu
->pmceid0
},
7926 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7927 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7928 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7929 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7930 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7931 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7932 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7933 .resetvalue
= cpu
->pmceid1
},
7935 #ifdef CONFIG_USER_ONLY
7936 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7937 { .name
= "ID_AA64PFR0_EL1",
7938 .exported_bits
= 0x000f000f00ff0000,
7939 .fixed_bits
= 0x0000000000000011 },
7940 { .name
= "ID_AA64PFR1_EL1",
7941 .exported_bits
= 0x00000000000000f0 },
7942 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7944 { .name
= "ID_AA64ZFR0_EL1" },
7945 { .name
= "ID_AA64MMFR0_EL1",
7946 .fixed_bits
= 0x00000000ff000000 },
7947 { .name
= "ID_AA64MMFR1_EL1" },
7948 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7950 { .name
= "ID_AA64DFR0_EL1",
7951 .fixed_bits
= 0x0000000000000006 },
7952 { .name
= "ID_AA64DFR1_EL1" },
7953 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7955 { .name
= "ID_AA64AFR*",
7957 { .name
= "ID_AA64ISAR0_EL1",
7958 .exported_bits
= 0x00fffffff0fffff0 },
7959 { .name
= "ID_AA64ISAR1_EL1",
7960 .exported_bits
= 0x000000f0ffffffff },
7961 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7964 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7966 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7967 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7968 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7969 ARMCPRegInfo rvbar
= {
7970 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7971 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7973 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7975 define_one_arm_cp_reg(cpu
, &rvbar
);
7977 define_arm_cp_regs(cpu
, v8_idregs
);
7978 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7982 * Register the base EL2 cpregs.
7983 * Pre v8, these registers are implemented only as part of the
7984 * Virtualization Extensions (EL2 present). Beginning with v8,
7985 * if EL2 is missing but EL3 is enabled, mostly these become
7986 * RES0 from EL3, with some specific exceptions.
7988 if (arm_feature(env
, ARM_FEATURE_EL2
)
7989 || (arm_feature(env
, ARM_FEATURE_EL3
)
7990 && arm_feature(env
, ARM_FEATURE_V8
))) {
7991 uint64_t vmpidr_def
= mpidr_read_val(env
);
7992 ARMCPRegInfo vpidr_regs
[] = {
7993 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7994 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7995 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7996 .resetvalue
= cpu
->midr
,
7997 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7998 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7999 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8000 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8001 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8002 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8003 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8004 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8005 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8006 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8007 .resetvalue
= vmpidr_def
,
8008 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8009 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8010 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8011 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8012 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8013 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8014 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8017 * The only field of MDCR_EL2 that has a defined architectural reset
8018 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8020 ARMCPRegInfo mdcr_el2
= {
8021 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
8022 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8023 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8024 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8026 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8027 define_arm_cp_regs(cpu
, vpidr_regs
);
8028 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8029 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8030 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8032 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8033 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8035 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
8036 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8037 ARMCPRegInfo rvbar
= {
8038 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8039 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8041 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8043 define_one_arm_cp_reg(cpu
, &rvbar
);
8047 /* Register the base EL3 cpregs. */
8048 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8049 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8050 ARMCPRegInfo el3_regs
[] = {
8051 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8052 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8054 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8056 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8057 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8059 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8060 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8061 .resetvalue
= cpu
->reset_sctlr
},
8064 define_arm_cp_regs(cpu
, el3_regs
);
8066 /* The behaviour of NSACR is sufficiently various that we don't
8067 * try to describe it in a single reginfo:
8068 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8069 * reads as constant 0xc00 from NS EL1 and NS EL2
8070 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8071 * if v7 without EL3, register doesn't exist
8072 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8074 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8075 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8076 static const ARMCPRegInfo nsacr
= {
8077 .name
= "NSACR", .type
= ARM_CP_CONST
,
8078 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8079 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8082 define_one_arm_cp_reg(cpu
, &nsacr
);
8084 static const ARMCPRegInfo nsacr
= {
8086 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8087 .access
= PL3_RW
| PL1_R
,
8089 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8091 define_one_arm_cp_reg(cpu
, &nsacr
);
8094 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8095 static const ARMCPRegInfo nsacr
= {
8096 .name
= "NSACR", .type
= ARM_CP_CONST
,
8097 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8101 define_one_arm_cp_reg(cpu
, &nsacr
);
8105 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8106 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8107 /* PMSAv6 not implemented */
8108 assert(arm_feature(env
, ARM_FEATURE_V7
));
8109 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8110 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8112 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8115 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8116 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8117 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8118 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8119 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8122 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8123 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8125 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8126 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8128 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8129 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8131 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8132 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8134 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8135 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8137 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8138 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8140 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8141 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8143 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8144 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8146 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8147 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8149 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8150 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8152 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8153 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8155 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8156 define_arm_cp_regs(cpu
, jazelle_regs
);
8158 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
8159 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8160 * be read-only (ie write causes UNDEF exception).
8163 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8164 /* Pre-v8 MIDR space.
8165 * Note that the MIDR isn't a simple constant register because
8166 * of the TI925 behaviour where writes to another register can
8167 * cause the MIDR value to change.
8169 * Unimplemented registers in the c15 0 0 0 space default to
8170 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8171 * and friends override accordingly.
8174 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8175 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8176 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8177 .readfn
= midr_read
,
8178 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8179 .type
= ARM_CP_OVERRIDE
},
8180 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8182 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8183 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8185 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8186 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8188 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8189 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8191 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8192 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8194 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8195 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8197 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8198 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8199 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8200 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8201 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8202 .readfn
= midr_read
},
8203 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
8204 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8205 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8206 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8207 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8208 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8209 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8210 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8211 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8213 .accessfn
= access_aa64_tid1
,
8214 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8216 ARMCPRegInfo id_cp_reginfo
[] = {
8217 /* These are common to v8 and pre-v8 */
8219 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8220 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8221 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8222 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8223 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8224 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8225 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8226 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8228 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8230 .accessfn
= access_aa32_tid1
,
8231 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8233 /* TLBTR is specific to VMSA */
8234 ARMCPRegInfo id_tlbtr_reginfo
= {
8236 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8238 .accessfn
= access_aa32_tid1
,
8239 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8241 /* MPUIR is specific to PMSA V6+ */
8242 ARMCPRegInfo id_mpuir_reginfo
= {
8244 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8245 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8246 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8248 static const ARMCPRegInfo crn0_wi_reginfo
= {
8249 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8250 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8251 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8253 #ifdef CONFIG_USER_ONLY
8254 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8255 { .name
= "MIDR_EL1",
8256 .exported_bits
= 0x00000000ffffffff },
8257 { .name
= "REVIDR_EL1" },
8259 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8261 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8262 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8264 /* Register the blanket "writes ignored" value first to cover the
8265 * whole space. Then update the specific ID registers to allow write
8266 * access, so that they ignore writes rather than causing them to
8269 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8270 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8271 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8273 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8274 id_cp_reginfo
[i
].access
= PL1_RW
;
8276 id_mpuir_reginfo
.access
= PL1_RW
;
8277 id_tlbtr_reginfo
.access
= PL1_RW
;
8279 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8280 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8282 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8284 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8285 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8286 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8287 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8288 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8292 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8293 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8294 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8295 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8296 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8298 #ifdef CONFIG_USER_ONLY
8299 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8300 { .name
= "MPIDR_EL1",
8301 .fixed_bits
= 0x0000000080000000 },
8303 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8305 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8308 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8309 ARMCPRegInfo auxcr_reginfo
[] = {
8310 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8311 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8312 .access
= PL1_RW
, .accessfn
= access_tacr
,
8313 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8314 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8315 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8316 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8318 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8319 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8320 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8323 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8324 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8325 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8329 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8331 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8332 * There are two flavours:
8333 * (1) older 32-bit only cores have a simple 32-bit CBAR
8334 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8335 * 32-bit register visible to AArch32 at a different encoding
8336 * to the "flavour 1" register and with the bits rearranged to
8337 * be able to squash a 64-bit address into the 32-bit view.
8338 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8339 * in future if we support AArch32-only configs of some of the
8340 * AArch64 cores we might need to add a specific feature flag
8341 * to indicate cores with "flavour 2" CBAR.
8343 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8344 /* 32 bit view is [31:18] 0...0 [43:32]. */
8345 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8346 | extract64(cpu
->reset_cbar
, 32, 12);
8347 ARMCPRegInfo cbar_reginfo
[] = {
8349 .type
= ARM_CP_CONST
,
8350 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8351 .access
= PL1_R
, .resetvalue
= cbar32
},
8352 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8353 .type
= ARM_CP_CONST
,
8354 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8355 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8357 /* We don't implement a r/w 64 bit CBAR currently */
8358 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8359 define_arm_cp_regs(cpu
, cbar_reginfo
);
8361 ARMCPRegInfo cbar
= {
8363 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8364 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8365 .fieldoffset
= offsetof(CPUARMState
,
8366 cp15
.c15_config_base_address
)
8368 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8369 cbar
.access
= PL1_R
;
8370 cbar
.fieldoffset
= 0;
8371 cbar
.type
= ARM_CP_CONST
;
8373 define_one_arm_cp_reg(cpu
, &cbar
);
8377 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8378 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
8379 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8380 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8381 .access
= PL1_RW
, .writefn
= vbar_write
,
8382 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8383 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8386 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8389 /* Generic registers whose values depend on the implementation */
8391 ARMCPRegInfo sctlr
= {
8392 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8393 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8394 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8395 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8396 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8397 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8398 .raw_writefn
= raw_write
,
8400 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8401 /* Normally we would always end the TB on an SCTLR write, but Linux
8402 * arch/arm/mach-pxa/sleep.S expects two instructions following
8403 * an MMU enable to execute from cache. Imitate this behaviour.
8405 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8407 define_one_arm_cp_reg(cpu
, &sctlr
);
8410 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8411 define_arm_cp_regs(cpu
, lor_reginfo
);
8413 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8414 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8416 #ifndef CONFIG_USER_ONLY
8417 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8418 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8420 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8421 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8424 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8425 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8428 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8429 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8431 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8432 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8434 if (cpu_isar_feature(any_ras
, cpu
)) {
8435 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
8438 if (cpu_isar_feature(aa64_vh
, cpu
) ||
8439 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
8440 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
8442 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8443 define_arm_cp_regs(cpu
, vhe_reginfo
);
8446 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8447 define_arm_cp_regs(cpu
, zcr_reginfo
);
8450 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
8451 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
8454 #ifdef TARGET_AARCH64
8455 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8456 define_arm_cp_regs(cpu
, pauth_reginfo
);
8458 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8459 define_arm_cp_regs(cpu
, rndr_reginfo
);
8461 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8462 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8464 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8465 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8467 #ifndef CONFIG_USER_ONLY
8468 /* Data Cache clean instructions up to PoP */
8469 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8470 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8472 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8473 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8476 #endif /*CONFIG_USER_ONLY*/
8479 * If full MTE is enabled, add all of the system registers.
8480 * If only "instructions available at EL0" are enabled,
8481 * then define only a RAZ/WI version of PSTATE.TCO.
8483 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8484 define_arm_cp_regs(cpu
, mte_reginfo
);
8485 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8486 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8487 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8488 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8491 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
8492 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
8496 if (cpu_isar_feature(any_predinv
, cpu
)) {
8497 define_arm_cp_regs(cpu
, predinv_reginfo
);
8500 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8501 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8504 #ifndef CONFIG_USER_ONLY
8506 * Register redirections and aliases must be done last,
8507 * after the registers from the other extensions have been defined.
8509 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8510 define_arm_vh_e2h_redirects_aliases(cpu
);
8515 /* Sort alphabetically by type name, except for "any". */
8516 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8518 ObjectClass
*class_a
= (ObjectClass
*)a
;
8519 ObjectClass
*class_b
= (ObjectClass
*)b
;
8520 const char *name_a
, *name_b
;
8522 name_a
= object_class_get_name(class_a
);
8523 name_b
= object_class_get_name(class_b
);
8524 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8526 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8529 return strcmp(name_a
, name_b
);
8533 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8535 ObjectClass
*oc
= data
;
8536 const char *typename
;
8539 typename
= object_class_get_name(oc
);
8540 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8541 qemu_printf(" %s\n", name
);
8545 void arm_cpu_list(void)
8549 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8550 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8551 qemu_printf("Available CPUs:\n");
8552 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8556 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8558 ObjectClass
*oc
= data
;
8559 CpuDefinitionInfoList
**cpu_list
= user_data
;
8560 CpuDefinitionInfo
*info
;
8561 const char *typename
;
8563 typename
= object_class_get_name(oc
);
8564 info
= g_malloc0(sizeof(*info
));
8565 info
->name
= g_strndup(typename
,
8566 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8567 info
->q_typename
= g_strdup(typename
);
8569 QAPI_LIST_PREPEND(*cpu_list
, info
);
8572 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8574 CpuDefinitionInfoList
*cpu_list
= NULL
;
8577 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8578 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8585 * Private utility function for define_one_arm_cp_reg_with_opaque():
8586 * add a single reginfo struct to the hash table.
8588 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8589 void *opaque
, CPState state
,
8590 CPSecureState secstate
,
8591 int crm
, int opc1
, int opc2
,
8594 CPUARMState
*env
= &cpu
->env
;
8597 bool is64
= r
->type
& ARM_CP_64BIT
;
8598 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
8604 case ARM_CP_STATE_AA32
:
8605 /* We assume it is a cp15 register if the .cp field is left unset. */
8606 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
8609 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
8611 case ARM_CP_STATE_AA64
:
8613 * To allow abbreviation of ARMCPRegInfo definitions, we treat
8614 * cp == 0 as equivalent to the value for "standard guest-visible
8615 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
8616 * in their AArch64 view (the .cp value may be non-zero for the
8617 * benefit of the AArch32 view).
8619 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8620 cp
= CP_REG_ARM64_SYSREG_CP
;
8622 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
8625 g_assert_not_reached();
8628 /* Overriding of an existing definition must be explicitly requested. */
8629 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8630 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
8632 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
8637 * Eliminate registers that are not present because the EL is missing.
8638 * Doing this here makes it easier to put all registers for a given
8639 * feature into the same ARMCPRegInfo array and define them all at once.
8642 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8644 * An EL2 register without EL2 but with EL3 is (usually) RES0.
8645 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
8647 int min_el
= ctz32(r
->access
) / 2;
8648 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
8649 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
8652 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
8655 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
8657 if ((r
->access
& max_el
) == 0) {
8662 /* Combine cpreg and name into one allocation. */
8663 name_len
= strlen(name
) + 1;
8664 r2
= g_malloc(sizeof(*r2
) + name_len
);
8666 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
8669 * Update fields to match the instantiation, overwiting wildcards
8670 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
8677 r2
->secure
= secstate
;
8679 r2
->opaque
= opaque
;
8683 /* This should not have been a very special register to begin. */
8684 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
8685 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
8687 * Set the special function to CONST, retaining the other flags.
8688 * This is important for e.g. ARM_CP_SVE so that we still
8689 * take the SVE trap if CPTR_EL3.EZ == 0.
8691 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
8693 * Usually, these registers become RES0, but there are a few
8694 * special cases like VPIDR_EL2 which have a constant non-zero
8695 * value with writes ignored.
8697 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
8701 * ARM_CP_CONST has precedence, so removing the callbacks and
8702 * offsets are not strictly necessary, but it is potentially
8703 * less confusing to debug later.
8707 r2
->raw_readfn
= NULL
;
8708 r2
->raw_writefn
= NULL
;
8710 r2
->fieldoffset
= 0;
8711 r2
->bank_fieldoffsets
[0] = 0;
8712 r2
->bank_fieldoffsets
[1] = 0;
8714 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
8718 * Register is banked (using both entries in array).
8719 * Overwriting fieldoffset as the array is only used to define
8720 * banked registers but later only fieldoffset is used.
8722 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8724 if (state
== ARM_CP_STATE_AA32
) {
8727 * If the register is banked then we don't need to migrate or
8728 * reset the 32-bit instance in certain cases:
8730 * 1) If the register has both 32-bit and 64-bit instances
8731 * then we can count on the 64-bit instance taking care
8732 * of the non-secure bank.
8733 * 2) If ARMv8 is enabled then we can count on a 64-bit
8734 * version taking care of the secure bank. This requires
8735 * that separate 32 and 64-bit definitions are provided.
8737 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8738 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
8739 r2
->type
|= ARM_CP_ALIAS
;
8741 } else if ((secstate
!= r
->secure
) && !ns
) {
8743 * The register is not banked so we only want to allow
8744 * migration of the non-secure instance.
8746 r2
->type
|= ARM_CP_ALIAS
;
8749 if (HOST_BIG_ENDIAN
&&
8750 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
8751 r2
->fieldoffset
+= sizeof(uint32_t);
8757 * By convention, for wildcarded registers only the first
8758 * entry is used for migration; the others are marked as
8759 * ALIAS so we don't try to transfer the register
8760 * multiple times. Special registers (ie NOP/WFI) are
8761 * never migratable and not even raw-accessible.
8763 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
8764 r2
->type
|= ARM_CP_NO_RAW
;
8766 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8767 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8768 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8769 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8773 * Check that raw accesses are either forbidden or handled. Note that
8774 * we can't assert this earlier because the setup of fieldoffset for
8775 * banked registers has to be done first.
8777 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8778 assert(!raw_accessors_invalid(r2
));
8781 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
8785 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8786 const ARMCPRegInfo
*r
, void *opaque
)
8788 /* Define implementations of coprocessor registers.
8789 * We store these in a hashtable because typically
8790 * there are less than 150 registers in a space which
8791 * is 16*16*16*8*8 = 262144 in size.
8792 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8793 * If a register is defined twice then the second definition is
8794 * used, so this can be used to define some generic registers and
8795 * then override them with implementation specific variations.
8796 * At least one of the original and the second definition should
8797 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8798 * against accidental use.
8800 * The state field defines whether the register is to be
8801 * visible in the AArch32 or AArch64 execution state. If the
8802 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8803 * reginfo structure for the AArch32 view, which sees the lower
8804 * 32 bits of the 64 bit register.
8806 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8807 * be wildcarded. AArch64 registers are always considered to be 64
8808 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8809 * the register, if any.
8811 int crm
, opc1
, opc2
;
8812 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8813 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8814 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8815 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8816 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8817 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8820 /* 64 bit registers have only CRm and Opc1 fields */
8821 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8822 /* op0 only exists in the AArch64 encodings */
8823 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8824 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8825 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8827 * This API is only for Arm's system coprocessors (14 and 15) or
8828 * (M-profile or v7A-and-earlier only) for implementation defined
8829 * coprocessors in the range 0..7. Our decode assumes this, since
8830 * 8..13 can be used for other insns including VFP and Neon. See
8831 * valid_cp() in translate.c. Assert here that we haven't tried
8832 * to use an invalid coprocessor number.
8835 case ARM_CP_STATE_BOTH
:
8836 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8841 case ARM_CP_STATE_AA32
:
8842 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8843 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8844 assert(r
->cp
>= 14 && r
->cp
<= 15);
8846 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8849 case ARM_CP_STATE_AA64
:
8850 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8853 g_assert_not_reached();
8855 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8856 * encodes a minimum access level for the register. We roll this
8857 * runtime check into our general permission check code, so check
8858 * here that the reginfo's specified permissions are strict enough
8859 * to encompass the generic architectural permission check.
8861 if (r
->state
!= ARM_CP_STATE_AA32
) {
8862 CPAccessRights mask
;
8865 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8866 mask
= PL0U_R
| PL1_RW
;
8886 /* min_EL EL1, secure mode only (we don't check the latter) */
8890 /* broken reginfo with out-of-range opc1 */
8891 g_assert_not_reached();
8893 /* assert our permissions are not too lax (stricter is fine) */
8894 assert((r
->access
& ~mask
) == 0);
8897 /* Check that the register definition has enough info to handle
8898 * reads and writes if they are permitted.
8900 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
8901 if (r
->access
& PL3_R
) {
8902 assert((r
->fieldoffset
||
8903 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8906 if (r
->access
& PL3_W
) {
8907 assert((r
->fieldoffset
||
8908 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8913 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8914 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8915 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8916 for (state
= ARM_CP_STATE_AA32
;
8917 state
<= ARM_CP_STATE_AA64
; state
++) {
8918 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8921 if (state
== ARM_CP_STATE_AA32
) {
8922 /* Under AArch32 CP registers can be common
8923 * (same for secure and non-secure world) or banked.
8927 switch (r
->secure
) {
8928 case ARM_CP_SECSTATE_S
:
8929 case ARM_CP_SECSTATE_NS
:
8930 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8931 r
->secure
, crm
, opc1
, opc2
,
8934 case ARM_CP_SECSTATE_BOTH
:
8935 name
= g_strdup_printf("%s_S", r
->name
);
8936 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8938 crm
, opc1
, opc2
, name
);
8940 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8942 crm
, opc1
, opc2
, r
->name
);
8945 g_assert_not_reached();
8948 /* AArch64 registers get mapped to non-secure instance
8950 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8952 crm
, opc1
, opc2
, r
->name
);
8960 /* Define a whole list of registers */
8961 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
8962 void *opaque
, size_t len
)
8965 for (i
= 0; i
< len
; ++i
) {
8966 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
8971 * Modify ARMCPRegInfo for access from userspace.
8973 * This is a data driven modification directed by
8974 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8975 * user-space cannot alter any values and dynamic values pertaining to
8976 * execution state are hidden from user space view anyway.
8978 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
8979 const ARMCPRegUserSpaceInfo
*mods
,
8982 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
8983 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
8984 GPatternSpec
*pat
= NULL
;
8987 pat
= g_pattern_spec_new(m
->name
);
8989 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
8990 ARMCPRegInfo
*r
= regs
+ ri
;
8992 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8993 r
->type
= ARM_CP_CONST
;
8997 } else if (strcmp(r
->name
, m
->name
) == 0) {
8998 r
->type
= ARM_CP_CONST
;
9000 r
->resetvalue
&= m
->exported_bits
;
9001 r
->resetvalue
|= m
->fixed_bits
;
9006 g_pattern_spec_free(pat
);
9011 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9013 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9016 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9019 /* Helper coprocessor write function for write-ignore registers */
9022 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9024 /* Helper coprocessor write function for read-as-zero registers */
9028 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9030 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9033 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9035 /* Return true if it is not valid for us to switch to
9036 * this CPU mode (ie all the UNPREDICTABLE cases in
9037 * the ARM ARM CPSRWriteByInstr pseudocode).
9040 /* Changes to or from Hyp via MSR and CPS are illegal. */
9041 if (write_type
== CPSRWriteByInstr
&&
9042 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9043 mode
== ARM_CPU_MODE_HYP
)) {
9048 case ARM_CPU_MODE_USR
:
9050 case ARM_CPU_MODE_SYS
:
9051 case ARM_CPU_MODE_SVC
:
9052 case ARM_CPU_MODE_ABT
:
9053 case ARM_CPU_MODE_UND
:
9054 case ARM_CPU_MODE_IRQ
:
9055 case ARM_CPU_MODE_FIQ
:
9056 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
9057 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9059 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9060 * and CPS are treated as illegal mode changes.
9062 if (write_type
== CPSRWriteByInstr
&&
9063 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9064 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9068 case ARM_CPU_MODE_HYP
:
9069 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9070 case ARM_CPU_MODE_MON
:
9071 return arm_current_el(env
) < 3;
9077 uint32_t cpsr_read(CPUARMState
*env
)
9080 ZF
= (env
->ZF
== 0);
9081 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9082 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9083 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9084 | ((env
->condexec_bits
& 0xfc) << 8)
9085 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9088 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9089 CPSRWriteType write_type
)
9091 uint32_t changed_daif
;
9092 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9093 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9095 if (mask
& CPSR_NZCV
) {
9096 env
->ZF
= (~val
) & CPSR_Z
;
9098 env
->CF
= (val
>> 29) & 1;
9099 env
->VF
= (val
<< 3) & 0x80000000;
9102 env
->QF
= ((val
& CPSR_Q
) != 0);
9104 env
->thumb
= ((val
& CPSR_T
) != 0);
9105 if (mask
& CPSR_IT_0_1
) {
9106 env
->condexec_bits
&= ~3;
9107 env
->condexec_bits
|= (val
>> 25) & 3;
9109 if (mask
& CPSR_IT_2_7
) {
9110 env
->condexec_bits
&= 3;
9111 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9113 if (mask
& CPSR_GE
) {
9114 env
->GE
= (val
>> 16) & 0xf;
9117 /* In a V7 implementation that includes the security extensions but does
9118 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9119 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9120 * bits respectively.
9122 * In a V8 implementation, it is permitted for privileged software to
9123 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9125 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9126 arm_feature(env
, ARM_FEATURE_EL3
) &&
9127 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9128 !arm_is_secure(env
)) {
9130 changed_daif
= (env
->daif
^ val
) & mask
;
9132 if (changed_daif
& CPSR_A
) {
9133 /* Check to see if we are allowed to change the masking of async
9134 * abort exceptions from a non-secure state.
9136 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9137 qemu_log_mask(LOG_GUEST_ERROR
,
9138 "Ignoring attempt to switch CPSR_A flag from "
9139 "non-secure world with SCR.AW bit clear\n");
9144 if (changed_daif
& CPSR_F
) {
9145 /* Check to see if we are allowed to change the masking of FIQ
9146 * exceptions from a non-secure state.
9148 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9149 qemu_log_mask(LOG_GUEST_ERROR
,
9150 "Ignoring attempt to switch CPSR_F flag from "
9151 "non-secure world with SCR.FW bit clear\n");
9155 /* Check whether non-maskable FIQ (NMFI) support is enabled.
9156 * If this bit is set software is not allowed to mask
9157 * FIQs, but is allowed to set CPSR_F to 0.
9159 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9161 qemu_log_mask(LOG_GUEST_ERROR
,
9162 "Ignoring attempt to enable CPSR_F flag "
9163 "(non-maskable FIQ [NMFI] support enabled)\n");
9169 env
->daif
&= ~(CPSR_AIF
& mask
);
9170 env
->daif
|= val
& CPSR_AIF
& mask
;
9172 if (write_type
!= CPSRWriteRaw
&&
9173 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9174 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9175 /* Note that we can only get here in USR mode if this is a
9176 * gdb stub write; for this case we follow the architectural
9177 * behaviour for guest writes in USR mode of ignoring an attempt
9178 * to switch mode. (Those are caught by translate.c for writes
9179 * triggered by guest instructions.)
9182 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9183 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9184 * v7, and has defined behaviour in v8:
9185 * + leave CPSR.M untouched
9186 * + allow changes to the other CPSR fields
9188 * For user changes via the GDB stub, we don't set PSTATE.IL,
9189 * as this would be unnecessarily harsh for a user error.
9192 if (write_type
!= CPSRWriteByGDBStub
&&
9193 arm_feature(env
, ARM_FEATURE_V8
)) {
9197 qemu_log_mask(LOG_GUEST_ERROR
,
9198 "Illegal AArch32 mode switch attempt from %s to %s\n",
9199 aarch32_mode_name(env
->uncached_cpsr
),
9200 aarch32_mode_name(val
));
9202 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9203 write_type
== CPSRWriteExceptionReturn
?
9204 "Exception return from AArch32" :
9205 "AArch32 mode switch from",
9206 aarch32_mode_name(env
->uncached_cpsr
),
9207 aarch32_mode_name(val
), env
->regs
[15]);
9208 switch_mode(env
, val
& CPSR_M
);
9211 mask
&= ~CACHED_CPSR_BITS
;
9212 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9213 if (rebuild_hflags
) {
9214 arm_rebuild_hflags(env
);
9218 /* Sign/zero extend */
9219 uint32_t HELPER(sxtb16
)(uint32_t x
)
9222 res
= (uint16_t)(int8_t)x
;
9223 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9227 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9230 * Take a division-by-zero exception if necessary; otherwise return
9231 * to get the usual non-trapping division behaviour (result of 0)
9233 if (arm_feature(env
, ARM_FEATURE_M
)
9234 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9235 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9239 uint32_t HELPER(uxtb16
)(uint32_t x
)
9242 res
= (uint16_t)(uint8_t)x
;
9243 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9247 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9250 handle_possible_div0_trap(env
, GETPC());
9253 if (num
== INT_MIN
&& den
== -1) {
9259 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9262 handle_possible_div0_trap(env
, GETPC());
9268 uint32_t HELPER(rbit
)(uint32_t x
)
9273 #ifdef CONFIG_USER_ONLY
9275 static void switch_mode(CPUARMState
*env
, int mode
)
9277 ARMCPU
*cpu
= env_archcpu(env
);
9279 if (mode
!= ARM_CPU_MODE_USR
) {
9280 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9284 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9285 uint32_t cur_el
, bool secure
)
9290 void aarch64_sync_64_to_32(CPUARMState
*env
)
9292 g_assert_not_reached();
9297 static void switch_mode(CPUARMState
*env
, int mode
)
9302 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9303 if (mode
== old_mode
)
9306 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9307 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9308 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9309 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9310 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9311 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9314 i
= bank_number(old_mode
);
9315 env
->banked_r13
[i
] = env
->regs
[13];
9316 env
->banked_spsr
[i
] = env
->spsr
;
9318 i
= bank_number(mode
);
9319 env
->regs
[13] = env
->banked_r13
[i
];
9320 env
->spsr
= env
->banked_spsr
[i
];
9322 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9323 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9326 /* Physical Interrupt Target EL Lookup Table
9328 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9330 * The below multi-dimensional table is used for looking up the target
9331 * exception level given numerous condition criteria. Specifically, the
9332 * target EL is based on SCR and HCR routing controls as well as the
9333 * currently executing EL and secure state.
9336 * target_el_table[2][2][2][2][2][4]
9337 * | | | | | +--- Current EL
9338 * | | | | +------ Non-secure(0)/Secure(1)
9339 * | | | +--------- HCR mask override
9340 * | | +------------ SCR exec state control
9341 * | +--------------- SCR mask override
9342 * +------------------ 32-bit(0)/64-bit(1) EL3
9344 * The table values are as such:
9348 * The ARM ARM target EL table includes entries indicating that an "exception
9349 * is not taken". The two cases where this is applicable are:
9350 * 1) An exception is taken from EL3 but the SCR does not have the exception
9352 * 2) An exception is taken from EL2 but the HCR does not have the exception
9354 * In these two cases, the below table contain a target of EL1. This value is
9355 * returned as it is expected that the consumer of the table data will check
9356 * for "target EL >= current EL" to ensure the exception is not taken.
9360 * BIT IRQ IMO Non-secure Secure
9361 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9363 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9364 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9365 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9366 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9367 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9368 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9369 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9370 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9371 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9372 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9373 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9374 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9375 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9376 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9377 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9378 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9379 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9383 * Determine the target EL for physical exceptions
9385 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9386 uint32_t cur_el
, bool secure
)
9388 CPUARMState
*env
= cs
->env_ptr
;
9393 /* Is the highest EL AArch64? */
9394 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9397 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9398 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9400 /* Either EL2 is the highest EL (and so the EL2 register width
9401 * is given by is64); or there is no EL2 or EL3, in which case
9402 * the value of 'rw' does not affect the table lookup anyway.
9407 hcr_el2
= arm_hcr_el2_eff(env
);
9410 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9411 hcr
= hcr_el2
& HCR_IMO
;
9414 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9415 hcr
= hcr_el2
& HCR_FMO
;
9418 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9419 hcr
= hcr_el2
& HCR_AMO
;
9424 * For these purposes, TGE and AMO/IMO/FMO both force the
9425 * interrupt to EL2. Fold TGE into the bit extracted above.
9427 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9429 /* Perform a table-lookup for the target EL given the current state */
9430 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9432 assert(target_el
> 0);
9437 void arm_log_exception(CPUState
*cs
)
9439 int idx
= cs
->exception_index
;
9441 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9442 const char *exc
= NULL
;
9443 static const char * const excnames
[] = {
9444 [EXCP_UDEF
] = "Undefined Instruction",
9446 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9447 [EXCP_DATA_ABORT
] = "Data Abort",
9450 [EXCP_BKPT
] = "Breakpoint",
9451 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9452 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9453 [EXCP_HVC
] = "Hypervisor Call",
9454 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9455 [EXCP_SMC
] = "Secure Monitor Call",
9456 [EXCP_VIRQ
] = "Virtual IRQ",
9457 [EXCP_VFIQ
] = "Virtual FIQ",
9458 [EXCP_SEMIHOST
] = "Semihosting call",
9459 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9460 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9461 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9462 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9463 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9464 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9465 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
9466 [EXCP_VSERR
] = "Virtual SERR",
9469 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9470 exc
= excnames
[idx
];
9475 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
9476 idx
, exc
, cs
->cpu_index
);
9481 * Function used to synchronize QEMU's AArch64 register set with AArch32
9482 * register set. This is necessary when switching between AArch32 and AArch64
9485 void aarch64_sync_32_to_64(CPUARMState
*env
)
9488 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9490 /* We can blanket copy R[0:7] to X[0:7] */
9491 for (i
= 0; i
< 8; i
++) {
9492 env
->xregs
[i
] = env
->regs
[i
];
9496 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9497 * Otherwise, they come from the banked user regs.
9499 if (mode
== ARM_CPU_MODE_FIQ
) {
9500 for (i
= 8; i
< 13; i
++) {
9501 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9504 for (i
= 8; i
< 13; i
++) {
9505 env
->xregs
[i
] = env
->regs
[i
];
9510 * Registers x13-x23 are the various mode SP and FP registers. Registers
9511 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9512 * from the mode banked register.
9514 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9515 env
->xregs
[13] = env
->regs
[13];
9516 env
->xregs
[14] = env
->regs
[14];
9518 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9519 /* HYP is an exception in that it is copied from r14 */
9520 if (mode
== ARM_CPU_MODE_HYP
) {
9521 env
->xregs
[14] = env
->regs
[14];
9523 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9527 if (mode
== ARM_CPU_MODE_HYP
) {
9528 env
->xregs
[15] = env
->regs
[13];
9530 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9533 if (mode
== ARM_CPU_MODE_IRQ
) {
9534 env
->xregs
[16] = env
->regs
[14];
9535 env
->xregs
[17] = env
->regs
[13];
9537 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9538 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9541 if (mode
== ARM_CPU_MODE_SVC
) {
9542 env
->xregs
[18] = env
->regs
[14];
9543 env
->xregs
[19] = env
->regs
[13];
9545 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9546 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9549 if (mode
== ARM_CPU_MODE_ABT
) {
9550 env
->xregs
[20] = env
->regs
[14];
9551 env
->xregs
[21] = env
->regs
[13];
9553 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9554 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9557 if (mode
== ARM_CPU_MODE_UND
) {
9558 env
->xregs
[22] = env
->regs
[14];
9559 env
->xregs
[23] = env
->regs
[13];
9561 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9562 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9566 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9567 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9568 * FIQ bank for r8-r14.
9570 if (mode
== ARM_CPU_MODE_FIQ
) {
9571 for (i
= 24; i
< 31; i
++) {
9572 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9575 for (i
= 24; i
< 29; i
++) {
9576 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9578 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9579 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9582 env
->pc
= env
->regs
[15];
9586 * Function used to synchronize QEMU's AArch32 register set with AArch64
9587 * register set. This is necessary when switching between AArch32 and AArch64
9590 void aarch64_sync_64_to_32(CPUARMState
*env
)
9593 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9595 /* We can blanket copy X[0:7] to R[0:7] */
9596 for (i
= 0; i
< 8; i
++) {
9597 env
->regs
[i
] = env
->xregs
[i
];
9601 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9602 * Otherwise, we copy x8-x12 into the banked user regs.
9604 if (mode
== ARM_CPU_MODE_FIQ
) {
9605 for (i
= 8; i
< 13; i
++) {
9606 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9609 for (i
= 8; i
< 13; i
++) {
9610 env
->regs
[i
] = env
->xregs
[i
];
9615 * Registers r13 & r14 depend on the current mode.
9616 * If we are in a given mode, we copy the corresponding x registers to r13
9617 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9620 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9621 env
->regs
[13] = env
->xregs
[13];
9622 env
->regs
[14] = env
->xregs
[14];
9624 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9627 * HYP is an exception in that it does not have its own banked r14 but
9628 * shares the USR r14
9630 if (mode
== ARM_CPU_MODE_HYP
) {
9631 env
->regs
[14] = env
->xregs
[14];
9633 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9637 if (mode
== ARM_CPU_MODE_HYP
) {
9638 env
->regs
[13] = env
->xregs
[15];
9640 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9643 if (mode
== ARM_CPU_MODE_IRQ
) {
9644 env
->regs
[14] = env
->xregs
[16];
9645 env
->regs
[13] = env
->xregs
[17];
9647 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9648 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9651 if (mode
== ARM_CPU_MODE_SVC
) {
9652 env
->regs
[14] = env
->xregs
[18];
9653 env
->regs
[13] = env
->xregs
[19];
9655 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9656 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9659 if (mode
== ARM_CPU_MODE_ABT
) {
9660 env
->regs
[14] = env
->xregs
[20];
9661 env
->regs
[13] = env
->xregs
[21];
9663 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9664 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9667 if (mode
== ARM_CPU_MODE_UND
) {
9668 env
->regs
[14] = env
->xregs
[22];
9669 env
->regs
[13] = env
->xregs
[23];
9671 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9672 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9675 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9676 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9677 * FIQ bank for r8-r14.
9679 if (mode
== ARM_CPU_MODE_FIQ
) {
9680 for (i
= 24; i
< 31; i
++) {
9681 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9684 for (i
= 24; i
< 29; i
++) {
9685 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9687 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9688 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9691 env
->regs
[15] = env
->pc
;
9694 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9695 uint32_t mask
, uint32_t offset
,
9700 /* Change the CPU state so as to actually take the exception. */
9701 switch_mode(env
, new_mode
);
9704 * For exceptions taken to AArch32 we must clear the SS bit in both
9705 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9707 env
->pstate
&= ~PSTATE_SS
;
9708 env
->spsr
= cpsr_read(env
);
9709 /* Clear IT bits. */
9710 env
->condexec_bits
= 0;
9711 /* Switch to the new mode, and to the correct instruction set. */
9712 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9714 /* This must be after mode switching. */
9715 new_el
= arm_current_el(env
);
9717 /* Set new mode endianness */
9718 env
->uncached_cpsr
&= ~CPSR_E
;
9719 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9720 env
->uncached_cpsr
|= CPSR_E
;
9722 /* J and IL must always be cleared for exception entry */
9723 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9726 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
9727 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
9728 env
->uncached_cpsr
|= CPSR_SSBS
;
9730 env
->uncached_cpsr
&= ~CPSR_SSBS
;
9734 if (new_mode
== ARM_CPU_MODE_HYP
) {
9735 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9736 env
->elr_el
[2] = env
->regs
[15];
9738 /* CPSR.PAN is normally preserved preserved unless... */
9739 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9742 if (!arm_is_secure_below_el3(env
)) {
9743 /* ... the target is EL3, from non-secure state. */
9744 env
->uncached_cpsr
&= ~CPSR_PAN
;
9747 /* ... the target is EL3, from secure state ... */
9750 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9751 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9752 env
->uncached_cpsr
|= CPSR_PAN
;
9758 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9759 * and we should just guard the thumb mode on V4
9761 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9763 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9765 env
->regs
[14] = env
->regs
[15] + offset
;
9767 env
->regs
[15] = newpc
;
9768 arm_rebuild_hflags(env
);
9771 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9774 * Handle exception entry to Hyp mode; this is sufficiently
9775 * different to entry to other AArch32 modes that we handle it
9778 * The vector table entry used is always the 0x14 Hyp mode entry point,
9779 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
9780 * The offset applied to the preferred return address is always zero
9781 * (see DDI0487C.a section G1.12.3).
9782 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9784 uint32_t addr
, mask
;
9785 ARMCPU
*cpu
= ARM_CPU(cs
);
9786 CPUARMState
*env
= &cpu
->env
;
9788 switch (cs
->exception_index
) {
9796 /* Fall through to prefetch abort. */
9797 case EXCP_PREFETCH_ABORT
:
9798 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9799 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9800 (uint32_t)env
->exception
.vaddress
);
9803 case EXCP_DATA_ABORT
:
9804 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9805 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9806 (uint32_t)env
->exception
.vaddress
);
9822 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9825 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9826 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9828 * QEMU syndrome values are v8-style. v7 has the IL bit
9829 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9830 * If this is a v7 CPU, squash the IL bit in those cases.
9832 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9833 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9834 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9835 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9836 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9839 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9842 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9847 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9850 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9853 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9857 addr
+= env
->cp15
.hvbar
;
9859 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9862 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9864 ARMCPU
*cpu
= ARM_CPU(cs
);
9865 CPUARMState
*env
= &cpu
->env
;
9872 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9873 switch (syn_get_ec(env
->exception
.syndrome
)) {
9875 case EC_BREAKPOINT_SAME_EL
:
9879 case EC_WATCHPOINT_SAME_EL
:
9885 case EC_VECTORCATCH
:
9894 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9897 if (env
->exception
.target_el
== 2) {
9898 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9902 switch (cs
->exception_index
) {
9904 new_mode
= ARM_CPU_MODE_UND
;
9913 new_mode
= ARM_CPU_MODE_SVC
;
9916 /* The PC already points to the next instruction. */
9920 /* Fall through to prefetch abort. */
9921 case EXCP_PREFETCH_ABORT
:
9922 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9923 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9924 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9925 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9926 new_mode
= ARM_CPU_MODE_ABT
;
9928 mask
= CPSR_A
| CPSR_I
;
9931 case EXCP_DATA_ABORT
:
9932 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9933 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9934 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9936 (uint32_t)env
->exception
.vaddress
);
9937 new_mode
= ARM_CPU_MODE_ABT
;
9939 mask
= CPSR_A
| CPSR_I
;
9943 new_mode
= ARM_CPU_MODE_IRQ
;
9945 /* Disable IRQ and imprecise data aborts. */
9946 mask
= CPSR_A
| CPSR_I
;
9948 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9949 /* IRQ routed to monitor mode */
9950 new_mode
= ARM_CPU_MODE_MON
;
9955 new_mode
= ARM_CPU_MODE_FIQ
;
9957 /* Disable FIQ, IRQ and imprecise data aborts. */
9958 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9959 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9960 /* FIQ routed to monitor mode */
9961 new_mode
= ARM_CPU_MODE_MON
;
9966 new_mode
= ARM_CPU_MODE_IRQ
;
9968 /* Disable IRQ and imprecise data aborts. */
9969 mask
= CPSR_A
| CPSR_I
;
9973 new_mode
= ARM_CPU_MODE_FIQ
;
9975 /* Disable FIQ, IRQ and imprecise data aborts. */
9976 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9982 * Note that this is reported as a data abort, but the DFAR
9983 * has an UNKNOWN value. Construct the SError syndrome from
9984 * AET and ExT fields.
9986 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
9988 if (extended_addresses_enabled(env
)) {
9989 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
9991 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
9993 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
9994 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9995 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
9996 env
->exception
.fsr
);
9998 new_mode
= ARM_CPU_MODE_ABT
;
10000 mask
= CPSR_A
| CPSR_I
;
10005 new_mode
= ARM_CPU_MODE_MON
;
10007 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10011 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10012 return; /* Never happens. Keep compiler happy. */
10015 if (new_mode
== ARM_CPU_MODE_MON
) {
10016 addr
+= env
->cp15
.mvbar
;
10017 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10018 /* High vectors. When enabled, base address cannot be remapped. */
10019 addr
+= 0xffff0000;
10021 /* ARM v7 architectures provide a vector base address register to remap
10022 * the interrupt vector table.
10023 * This register is only followed in non-monitor mode, and is banked.
10024 * Note: only bits 31:5 are valid.
10026 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10029 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10030 env
->cp15
.scr_el3
&= ~SCR_NS
;
10033 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10036 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10039 * Return the register number of the AArch64 view of the AArch32
10040 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10041 * be that of the AArch32 mode the exception came from.
10043 int mode
= env
->uncached_cpsr
& CPSR_M
;
10045 switch (aarch32_reg
) {
10047 return aarch32_reg
;
10049 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10052 case ARM_CPU_MODE_USR
:
10053 case ARM_CPU_MODE_SYS
:
10055 case ARM_CPU_MODE_HYP
:
10057 case ARM_CPU_MODE_IRQ
:
10059 case ARM_CPU_MODE_SVC
:
10061 case ARM_CPU_MODE_ABT
:
10063 case ARM_CPU_MODE_UND
:
10065 case ARM_CPU_MODE_FIQ
:
10068 g_assert_not_reached();
10072 case ARM_CPU_MODE_USR
:
10073 case ARM_CPU_MODE_SYS
:
10074 case ARM_CPU_MODE_HYP
:
10076 case ARM_CPU_MODE_IRQ
:
10078 case ARM_CPU_MODE_SVC
:
10080 case ARM_CPU_MODE_ABT
:
10082 case ARM_CPU_MODE_UND
:
10084 case ARM_CPU_MODE_FIQ
:
10087 g_assert_not_reached();
10092 g_assert_not_reached();
10096 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10098 uint32_t ret
= cpsr_read(env
);
10100 /* Move DIT to the correct location for SPSR_ELx */
10101 if (ret
& CPSR_DIT
) {
10105 /* Merge PSTATE.SS into SPSR_ELx */
10106 ret
|= env
->pstate
& PSTATE_SS
;
10111 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
10113 /* Return true if this syndrome value is a synchronous external abort */
10114 switch (syn_get_ec(syndrome
)) {
10116 case EC_INSNABORT_SAME_EL
:
10118 case EC_DATAABORT_SAME_EL
:
10119 /* Look at fault status code for all the synchronous ext abort cases */
10120 switch (syndrome
& 0x3f) {
10136 /* Handle exception entry to a target EL which is using AArch64 */
10137 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10139 ARMCPU
*cpu
= ARM_CPU(cs
);
10140 CPUARMState
*env
= &cpu
->env
;
10141 unsigned int new_el
= env
->exception
.target_el
;
10142 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10143 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10144 unsigned int old_mode
;
10145 unsigned int cur_el
= arm_current_el(env
);
10149 * Note that new_el can never be 0. If cur_el is 0, then
10150 * el0_a64 is is_a64(), else el0_a64 is ignored.
10152 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10154 if (cur_el
< new_el
) {
10155 /* Entry vector offset depends on whether the implemented EL
10156 * immediately lower than the target level is using AArch32 or AArch64
10163 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10166 hcr
= arm_hcr_el2_eff(env
);
10167 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10168 is_aa64
= (hcr
& HCR_RW
) != 0;
10173 is_aa64
= is_a64(env
);
10176 g_assert_not_reached();
10184 } else if (pstate_read(env
) & PSTATE_SP
) {
10188 switch (cs
->exception_index
) {
10189 case EXCP_PREFETCH_ABORT
:
10190 case EXCP_DATA_ABORT
:
10192 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
10193 * to be taken to the SError vector entrypoint.
10195 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
10196 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
10199 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10200 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10201 env
->cp15
.far_el
[new_el
]);
10207 case EXCP_HYP_TRAP
:
10209 switch (syn_get_ec(env
->exception
.syndrome
)) {
10210 case EC_ADVSIMDFPACCESSTRAP
:
10212 * QEMU internal FP/SIMD syndromes from AArch32 include the
10213 * TA and coproc fields which are only exposed if the exception
10214 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10215 * AArch64 format syndrome.
10217 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10219 case EC_CP14RTTRAP
:
10220 case EC_CP15RTTRAP
:
10221 case EC_CP14DTTRAP
:
10223 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10224 * the raw register field from the insn; when taking this to
10225 * AArch64 we must convert it to the AArch64 view of the register
10226 * number. Notice that we read a 4-bit AArch32 register number and
10227 * write back a 5-bit AArch64 one.
10229 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10230 rt
= aarch64_regnum(env
, rt
);
10231 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10234 case EC_CP15RRTTRAP
:
10235 case EC_CP14RRTTRAP
:
10236 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10237 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10238 rt
= aarch64_regnum(env
, rt
);
10239 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10241 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10242 rt
= aarch64_regnum(env
, rt
);
10243 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10247 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10259 /* Construct the SError syndrome from IDS and ISS fields. */
10260 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10261 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10264 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10268 old_mode
= pstate_read(env
);
10269 aarch64_save_sp(env
, arm_current_el(env
));
10270 env
->elr_el
[new_el
] = env
->pc
;
10272 old_mode
= cpsr_read_for_spsr_elx(env
);
10273 env
->elr_el
[new_el
] = env
->regs
[15];
10275 aarch64_sync_32_to_64(env
);
10277 env
->condexec_bits
= 0;
10279 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10281 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10282 env
->elr_el
[new_el
]);
10284 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10285 /* The value of PSTATE.PAN is normally preserved, except when ... */
10286 new_mode
|= old_mode
& PSTATE_PAN
;
10289 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10290 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10291 != (HCR_E2H
| HCR_TGE
)) {
10296 /* ... the target is EL1 ... */
10297 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10298 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10299 new_mode
|= PSTATE_PAN
;
10304 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10305 new_mode
|= PSTATE_TCO
;
10308 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10309 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10310 new_mode
|= PSTATE_SSBS
;
10312 new_mode
&= ~PSTATE_SSBS
;
10316 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10317 env
->aarch64
= true;
10318 aarch64_restore_sp(env
, new_el
);
10319 helper_rebuild_hflags_a64(env
, new_el
);
10323 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10324 new_el
, env
->pc
, pstate_read(env
));
10328 * Do semihosting call and set the appropriate return value. All the
10329 * permission and validity checks have been done at translate time.
10331 * We only see semihosting exceptions in TCG only as they are not
10332 * trapped to the hypervisor in KVM.
10335 static void handle_semihosting(CPUState
*cs
)
10337 ARMCPU
*cpu
= ARM_CPU(cs
);
10338 CPUARMState
*env
= &cpu
->env
;
10341 qemu_log_mask(CPU_LOG_INT
,
10342 "...handling as semihosting call 0x%" PRIx64
"\n",
10344 env
->xregs
[0] = do_common_semihosting(cs
);
10347 qemu_log_mask(CPU_LOG_INT
,
10348 "...handling as semihosting call 0x%x\n",
10350 env
->regs
[0] = do_common_semihosting(cs
);
10351 env
->regs
[15] += env
->thumb
? 2 : 4;
10356 /* Handle a CPU exception for A and R profile CPUs.
10357 * Do any appropriate logging, handle PSCI calls, and then hand off
10358 * to the AArch64-entry or AArch32-entry function depending on the
10359 * target exception level's register width.
10361 * Note: this is used for both TCG (as the do_interrupt tcg op),
10362 * and KVM to re-inject guest debug exceptions, and to
10363 * inject a Synchronous-External-Abort.
10365 void arm_cpu_do_interrupt(CPUState
*cs
)
10367 ARMCPU
*cpu
= ARM_CPU(cs
);
10368 CPUARMState
*env
= &cpu
->env
;
10369 unsigned int new_el
= env
->exception
.target_el
;
10371 assert(!arm_feature(env
, ARM_FEATURE_M
));
10373 arm_log_exception(cs
);
10374 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10376 if (qemu_loglevel_mask(CPU_LOG_INT
)
10377 && !excp_is_internal(cs
->exception_index
)) {
10378 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10379 syn_get_ec(env
->exception
.syndrome
),
10380 env
->exception
.syndrome
);
10383 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10384 arm_handle_psci_call(cpu
);
10385 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10390 * Semihosting semantics depend on the register width of the code
10391 * that caused the exception, not the target exception level, so
10392 * must be handled here.
10395 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10396 handle_semihosting(cs
);
10401 /* Hooks may change global state so BQL should be held, also the
10402 * BQL needs to be held for any modification of
10403 * cs->interrupt_request.
10405 g_assert(qemu_mutex_iothread_locked());
10407 arm_call_pre_el_change_hook(cpu
);
10409 assert(!excp_is_internal(cs
->exception_index
));
10410 if (arm_el_is_aa64(env
, new_el
)) {
10411 arm_cpu_do_interrupt_aarch64(cs
);
10413 arm_cpu_do_interrupt_aarch32(cs
);
10416 arm_call_el_change_hook(cpu
);
10418 if (!kvm_enabled()) {
10419 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10422 #endif /* !CONFIG_USER_ONLY */
10424 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10426 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10428 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10429 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10432 return env
->cp15
.sctlr_el
[el
];
10435 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10437 if (regime_has_2_ranges(mmu_idx
)) {
10438 return extract64(tcr
, 37, 2);
10439 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10440 return 0; /* VTCR_EL2 */
10442 /* Replicate the single TBI bit so we always have 2 bits. */
10443 return extract32(tcr
, 20, 1) * 3;
10447 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10449 if (regime_has_2_ranges(mmu_idx
)) {
10450 return extract64(tcr
, 51, 2);
10451 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10452 return 0; /* VTCR_EL2 */
10454 /* Replicate the single TBID bit so we always have 2 bits. */
10455 return extract32(tcr
, 29, 1) * 3;
10459 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10461 if (regime_has_2_ranges(mmu_idx
)) {
10462 return extract64(tcr
, 57, 2);
10464 /* Replicate the single TCMA bit so we always have 2 bits. */
10465 return extract32(tcr
, 30, 1) * 3;
10469 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10470 ARMMMUIdx mmu_idx
, bool data
)
10472 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10473 bool epd
, hpd
, using16k
, using64k
, tsz_oob
, ds
;
10474 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
10475 ARMCPU
*cpu
= env_archcpu(env
);
10477 if (!regime_has_2_ranges(mmu_idx
)) {
10479 tsz
= extract32(tcr
, 0, 6);
10480 using64k
= extract32(tcr
, 14, 1);
10481 using16k
= extract32(tcr
, 15, 1);
10482 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10486 hpd
= extract32(tcr
, 24, 1);
10489 sh
= extract32(tcr
, 12, 2);
10490 ps
= extract32(tcr
, 16, 3);
10491 ds
= extract64(tcr
, 32, 1);
10494 * Bit 55 is always between the two regions, and is canonical for
10495 * determining if address tagging is enabled.
10497 select
= extract64(va
, 55, 1);
10499 tsz
= extract32(tcr
, 0, 6);
10500 epd
= extract32(tcr
, 7, 1);
10501 sh
= extract32(tcr
, 12, 2);
10502 using64k
= extract32(tcr
, 14, 1);
10503 using16k
= extract32(tcr
, 15, 1);
10504 hpd
= extract64(tcr
, 41, 1);
10506 int tg
= extract32(tcr
, 30, 2);
10507 using16k
= tg
== 1;
10508 using64k
= tg
== 3;
10509 tsz
= extract32(tcr
, 16, 6);
10510 epd
= extract32(tcr
, 23, 1);
10511 sh
= extract32(tcr
, 28, 2);
10512 hpd
= extract64(tcr
, 42, 1);
10514 ps
= extract64(tcr
, 32, 3);
10515 ds
= extract64(tcr
, 59, 1);
10518 if (cpu_isar_feature(aa64_st
, cpu
)) {
10519 max_tsz
= 48 - using64k
;
10525 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
10526 * adjust the effective value of DS, as documented.
10530 if (cpu_isar_feature(aa64_lva
, cpu
)) {
10536 case ARMMMUIdx_Stage2
:
10537 case ARMMMUIdx_Stage2_S
:
10539 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
10541 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
10546 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
10548 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
10557 if (tsz
> max_tsz
) {
10560 } else if (tsz
< min_tsz
) {
10567 /* Present TBI as a composite with TBID. */
10568 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10570 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10572 tbi
= (tbi
>> select
) & 1;
10574 return (ARMVAParameters
) {
10582 .using16k
= using16k
,
10583 .using64k
= using64k
,
10584 .tsz_oob
= tsz_oob
,
10589 /* Note that signed overflow is undefined in C. The following routines are
10590 careful to use unsigned types where modulo arithmetic is required.
10591 Failure to do so _will_ break on newer gcc. */
10593 /* Signed saturating arithmetic. */
10595 /* Perform 16-bit signed saturating addition. */
10596 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10601 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10610 /* Perform 8-bit signed saturating addition. */
10611 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10616 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10625 /* Perform 16-bit signed saturating subtraction. */
10626 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10631 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10640 /* Perform 8-bit signed saturating subtraction. */
10641 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10646 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10655 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10656 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10657 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10658 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10661 #include "op_addsub.h"
10663 /* Unsigned saturating arithmetic. */
10664 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10673 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10681 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10690 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10698 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10699 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10700 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10701 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10704 #include "op_addsub.h"
10706 /* Signed modulo arithmetic. */
10707 #define SARITH16(a, b, n, op) do { \
10709 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10710 RESULT(sum, n, 16); \
10712 ge |= 3 << (n * 2); \
10715 #define SARITH8(a, b, n, op) do { \
10717 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10718 RESULT(sum, n, 8); \
10724 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10725 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10726 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10727 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10731 #include "op_addsub.h"
10733 /* Unsigned modulo arithmetic. */
10734 #define ADD16(a, b, n) do { \
10736 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10737 RESULT(sum, n, 16); \
10738 if ((sum >> 16) == 1) \
10739 ge |= 3 << (n * 2); \
10742 #define ADD8(a, b, n) do { \
10744 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10745 RESULT(sum, n, 8); \
10746 if ((sum >> 8) == 1) \
10750 #define SUB16(a, b, n) do { \
10752 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10753 RESULT(sum, n, 16); \
10754 if ((sum >> 16) == 0) \
10755 ge |= 3 << (n * 2); \
10758 #define SUB8(a, b, n) do { \
10760 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10761 RESULT(sum, n, 8); \
10762 if ((sum >> 8) == 0) \
10769 #include "op_addsub.h"
10771 /* Halved signed arithmetic. */
10772 #define ADD16(a, b, n) \
10773 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10774 #define SUB16(a, b, n) \
10775 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10776 #define ADD8(a, b, n) \
10777 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10778 #define SUB8(a, b, n) \
10779 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10782 #include "op_addsub.h"
10784 /* Halved unsigned arithmetic. */
10785 #define ADD16(a, b, n) \
10786 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10787 #define SUB16(a, b, n) \
10788 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10789 #define ADD8(a, b, n) \
10790 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10791 #define SUB8(a, b, n) \
10792 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10795 #include "op_addsub.h"
10797 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10805 /* Unsigned sum of absolute byte differences. */
10806 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10809 sum
= do_usad(a
, b
);
10810 sum
+= do_usad(a
>> 8, b
>> 8);
10811 sum
+= do_usad(a
>> 16, b
>> 16);
10812 sum
+= do_usad(a
>> 24, b
>> 24);
10816 /* For ARMv6 SEL instruction. */
10817 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10829 mask
|= 0xff000000;
10830 return (a
& mask
) | (b
& ~mask
);
10834 * The upper bytes of val (above the number specified by 'bytes') must have
10835 * been zeroed out by the caller.
10837 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10841 stl_le_p(buf
, val
);
10843 /* zlib crc32 converts the accumulator and output to one's complement. */
10844 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
10847 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10851 stl_le_p(buf
, val
);
10853 /* Linux crc32c converts the output to one's complement. */
10854 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
10857 /* Return the exception level to which FP-disabled exceptions should
10858 * be taken, or 0 if FP is enabled.
10860 int fp_exception_el(CPUARMState
*env
, int cur_el
)
10862 #ifndef CONFIG_USER_ONLY
10865 /* CPACR and the CPTR registers don't exist before v6, so FP is
10866 * always accessible
10868 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
10872 if (arm_feature(env
, ARM_FEATURE_M
)) {
10873 /* CPACR can cause a NOCP UsageFault taken to current security state */
10874 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
10878 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
10879 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
10880 /* FP insns cause a NOCP UsageFault taken to Secure */
10888 hcr_el2
= arm_hcr_el2_eff(env
);
10890 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
10891 * 0, 2 : trap EL0 and EL1/PL1 accesses
10892 * 1 : trap only EL0 accesses
10893 * 3 : trap no accesses
10894 * This register is ignored if E2H+TGE are both set.
10896 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10897 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
10902 if (cur_el
== 0 || cur_el
== 1) {
10903 /* Trap to PL1, which might be EL1 or EL3 */
10904 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
10909 if (cur_el
== 3 && !is_a64(env
)) {
10910 /* Secure PL1 running at EL3 */
10925 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
10926 * to control non-secure access to the FPU. It doesn't have any
10927 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
10929 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
10930 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
10931 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
10932 /* FP insns act as UNDEF */
10933 return cur_el
== 2 ? 2 : 1;
10938 * CPTR_EL2 is present in v7VE or v8, and changes format
10939 * with HCR_EL2.E2H (regardless of TGE).
10942 if (hcr_el2
& HCR_E2H
) {
10943 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
10945 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
10953 } else if (arm_is_el2_enabled(env
)) {
10954 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
10960 /* CPTR_EL3 : present in v8 */
10961 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
10962 /* Trap all FP ops to EL3 */
10969 /* Return the exception level we're running at if this is our mmu_idx */
10970 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
10972 if (mmu_idx
& ARM_MMU_IDX_M
) {
10973 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
10977 case ARMMMUIdx_E10_0
:
10978 case ARMMMUIdx_E20_0
:
10979 case ARMMMUIdx_SE10_0
:
10980 case ARMMMUIdx_SE20_0
:
10982 case ARMMMUIdx_E10_1
:
10983 case ARMMMUIdx_E10_1_PAN
:
10984 case ARMMMUIdx_SE10_1
:
10985 case ARMMMUIdx_SE10_1_PAN
:
10988 case ARMMMUIdx_E20_2
:
10989 case ARMMMUIdx_E20_2_PAN
:
10990 case ARMMMUIdx_SE2
:
10991 case ARMMMUIdx_SE20_2
:
10992 case ARMMMUIdx_SE20_2_PAN
:
10994 case ARMMMUIdx_SE3
:
10997 g_assert_not_reached();
11002 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11004 g_assert_not_reached();
11008 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11013 if (arm_feature(env
, ARM_FEATURE_M
)) {
11014 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11017 /* See ARM pseudo-function ELIsInHost. */
11020 hcr
= arm_hcr_el2_eff(env
);
11021 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
11022 idx
= ARMMMUIdx_E20_0
;
11024 idx
= ARMMMUIdx_E10_0
;
11028 if (env
->pstate
& PSTATE_PAN
) {
11029 idx
= ARMMMUIdx_E10_1_PAN
;
11031 idx
= ARMMMUIdx_E10_1
;
11035 /* Note that TGE does not apply at EL2. */
11036 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
11037 if (env
->pstate
& PSTATE_PAN
) {
11038 idx
= ARMMMUIdx_E20_2_PAN
;
11040 idx
= ARMMMUIdx_E20_2
;
11043 idx
= ARMMMUIdx_E2
;
11047 return ARMMMUIdx_SE3
;
11049 g_assert_not_reached();
11052 if (arm_is_secure_below_el3(env
)) {
11053 idx
&= ~ARM_MMU_IDX_A_NS
;
11059 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11061 return arm_mmu_idx_el(env
, arm_current_el(env
));
11064 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11066 CPUARMTBFlags flags
)
11068 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
11069 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
11071 if (arm_singlestep_active(env
)) {
11072 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
11077 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11079 CPUARMTBFlags flags
)
11081 bool sctlr_b
= arm_sctlr_b(env
);
11084 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
11086 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11087 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11089 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
11091 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11094 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11097 CPUARMTBFlags flags
= {};
11098 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
11100 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
11101 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
11102 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11105 if (arm_v7m_is_handler_mode(env
)) {
11106 DP_TBFLAG_M32(flags
, HANDLER
, 1);
11110 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11111 * is suppressing them because the requested execution priority
11114 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11115 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11116 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11117 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
11120 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11123 static CPUARMTBFlags
rebuild_hflags_aprofile(CPUARMState
*env
)
11125 CPUARMTBFlags flags
= {};
11127 DP_TBFLAG_ANY(flags
, DEBUG_TARGET_EL
, arm_debug_target_el(env
));
11131 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11134 CPUARMTBFlags flags
= rebuild_hflags_aprofile(env
);
11135 int el
= arm_current_el(env
);
11137 if (arm_sctlr(env
, el
) & SCTLR_A
) {
11138 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11141 if (arm_el_is_aa64(env
, 1)) {
11142 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11145 if (el
< 2 && env
->cp15
.hstr_el2
&&
11146 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11147 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
11150 if (env
->uncached_cpsr
& CPSR_IL
) {
11151 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11154 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11157 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11160 CPUARMTBFlags flags
= rebuild_hflags_aprofile(env
);
11161 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11162 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11166 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
11168 /* Get control bits for tagged addresses. */
11169 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11170 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11172 DP_TBFLAG_A64(flags
, TBII
, tbii
);
11173 DP_TBFLAG_A64(flags
, TBID
, tbid
);
11175 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11176 int sve_el
= sve_exception_el(env
, el
);
11179 * If either FP or SVE are disabled, translator does not need len.
11180 * If SVE EL > FP EL, FP exception has precedence, and translator
11181 * does not need SVE EL. Save potential re-translations by forcing
11182 * the unneeded data to zero.
11185 if (sve_el
> fp_el
) {
11188 } else if (sve_el
== 0) {
11189 DP_TBFLAG_A64(flags
, VL
, sve_zcr_len_for_el(env
, el
));
11191 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
11194 sctlr
= regime_sctlr(env
, stage1
);
11196 if (sctlr
& SCTLR_A
) {
11197 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11200 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
11201 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11204 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
11206 * In order to save space in flags, we record only whether
11207 * pauth is "inactive", meaning all insns are implemented as
11208 * a nop, or "active" when some action must be performed.
11209 * The decision of which action to take is left to a helper.
11211 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
11212 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
11216 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11217 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
11218 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
11219 DP_TBFLAG_A64(flags
, BT
, 1);
11223 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
11224 if (!(env
->pstate
& PSTATE_UAO
)) {
11226 case ARMMMUIdx_E10_1
:
11227 case ARMMMUIdx_E10_1_PAN
:
11228 case ARMMMUIdx_SE10_1
:
11229 case ARMMMUIdx_SE10_1_PAN
:
11230 /* TODO: ARMv8.3-NV */
11231 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11233 case ARMMMUIdx_E20_2
:
11234 case ARMMMUIdx_E20_2_PAN
:
11235 case ARMMMUIdx_SE20_2
:
11236 case ARMMMUIdx_SE20_2_PAN
:
11238 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
11239 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
11241 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
11242 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11250 if (env
->pstate
& PSTATE_IL
) {
11251 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11254 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
11256 * Set MTE_ACTIVE if any access may be Checked, and leave clear
11257 * if all accesses must be Unchecked:
11258 * 1) If no TBI, then there are no tags in the address to check,
11259 * 2) If Tag Check Override, then all accesses are Unchecked,
11260 * 3) If Tag Check Fail == 0, then Checked access have no effect,
11261 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
11263 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
11264 DP_TBFLAG_A64(flags
, ATA
, 1);
11266 && !(env
->pstate
& PSTATE_TCO
)
11267 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
11268 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
11271 /* And again for unprivileged accesses, if required. */
11272 if (EX_TBFLAG_A64(flags
, UNPRIV
)
11274 && !(env
->pstate
& PSTATE_TCO
)
11275 && (sctlr
& SCTLR_TCF0
)
11276 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
11277 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
11279 /* Cache TCMA as well as TBI. */
11280 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
11283 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11286 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
11288 int el
= arm_current_el(env
);
11289 int fp_el
= fp_exception_el(env
, el
);
11290 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11293 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11294 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
11295 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11297 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11301 void arm_rebuild_hflags(CPUARMState
*env
)
11303 env
->hflags
= rebuild_hflags_internal(env
);
11307 * If we have triggered a EL state change we can't rely on the
11308 * translator having passed it to us, we need to recompute.
11310 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
11312 int el
= arm_current_el(env
);
11313 int fp_el
= fp_exception_el(env
, el
);
11314 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11316 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11319 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
11321 int fp_el
= fp_exception_el(env
, el
);
11322 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11324 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11328 * If we have triggered a EL state change we can't rely on the
11329 * translator having passed it to us, we need to recompute.
11331 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
11333 int el
= arm_current_el(env
);
11334 int fp_el
= fp_exception_el(env
, el
);
11335 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11336 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11339 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
11341 int fp_el
= fp_exception_el(env
, el
);
11342 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11344 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11347 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
11349 int fp_el
= fp_exception_el(env
, el
);
11350 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11352 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11355 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
11357 #ifdef CONFIG_DEBUG_TCG
11358 CPUARMTBFlags c
= env
->hflags
;
11359 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
11361 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
11362 fprintf(stderr
, "TCG hflags mismatch "
11363 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
11364 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
11365 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
11371 static bool mve_no_pred(CPUARMState
*env
)
11374 * Return true if there is definitely no predication of MVE
11375 * instructions by VPR or LTPSIZE. (Returning false even if there
11376 * isn't any predication is OK; generated code will just be
11378 * If the CPU does not implement MVE then this TB flag is always 0.
11380 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
11381 * logic in gen_update_fp_context() needs to be updated to match.
11383 * We do not include the effect of the ECI bits here -- they are
11384 * tracked in other TB flags. This simplifies the logic for
11385 * "when did we emit code that changes the MVE_NO_PRED TB flag
11386 * and thus need to end the TB?".
11388 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
11391 if (env
->v7m
.vpr
) {
11394 if (env
->v7m
.ltpsize
< 4) {
11400 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11401 target_ulong
*cs_base
, uint32_t *pflags
)
11403 CPUARMTBFlags flags
;
11405 assert_hflags_rebuild_correctly(env
);
11406 flags
= env
->hflags
;
11408 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
11410 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11411 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
11414 *pc
= env
->regs
[15];
11416 if (arm_feature(env
, ARM_FEATURE_M
)) {
11417 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11418 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
11419 != env
->v7m
.secure
) {
11420 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
11423 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
11424 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
11425 (env
->v7m
.secure
&&
11426 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
11428 * ASPEN is set, but FPCA/SFPA indicate that there is no
11429 * active FP context; we must create a new FP context before
11430 * executing any FP insn.
11432 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
11435 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
11436 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
11437 DP_TBFLAG_M32(flags
, LSPACT
, 1);
11440 if (mve_no_pred(env
)) {
11441 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
11445 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
11446 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
11448 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11449 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
11451 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
11452 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
11454 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
11455 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11459 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
11460 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
11464 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11465 * states defined in the ARM ARM for software singlestep:
11466 * SS_ACTIVE PSTATE.SS State
11467 * 0 x Inactive (the TB flag for SS is always 0)
11468 * 1 0 Active-pending
11469 * 1 1 Active-not-pending
11470 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
11472 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
11473 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
11476 *pflags
= flags
.flags
;
11477 *cs_base
= flags
.flags2
;
11480 #ifdef TARGET_AARCH64
11482 * The manual says that when SVE is enabled and VQ is widened the
11483 * implementation is allowed to zero the previously inaccessible
11484 * portion of the registers. The corollary to that is that when
11485 * SVE is enabled and VQ is narrowed we are also allowed to zero
11486 * the now inaccessible portion of the registers.
11488 * The intent of this is that no predicate bit beyond VQ is ever set.
11489 * Which means that some operations on predicate registers themselves
11490 * may operate on full uint64_t or even unrolled across the maximum
11491 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
11492 * may well be cheaper than conditionals to restrict the operation
11493 * to the relevant portion of a uint16_t[16].
11495 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
11500 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
11501 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
11503 /* Zap the high bits of the zregs. */
11504 for (i
= 0; i
< 32; i
++) {
11505 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
11508 /* Zap the high bits of the pregs and ffr. */
11511 pmask
= ~(-1ULL << (16 * (vq
& 3)));
11513 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
11514 for (i
= 0; i
< 17; ++i
) {
11515 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
11522 * Notice a change in SVE vector size when changing EL.
11524 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
11525 int new_el
, bool el0_a64
)
11527 ARMCPU
*cpu
= env_archcpu(env
);
11528 int old_len
, new_len
;
11529 bool old_a64
, new_a64
;
11531 /* Nothing to do if no SVE. */
11532 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
11536 /* Nothing to do if FP is disabled in either EL. */
11537 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
11542 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
11543 * at ELx, or not available because the EL is in AArch32 state, then
11544 * for all purposes other than a direct read, the ZCR_ELx.LEN field
11545 * has an effective value of 0".
11547 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
11548 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
11549 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
11550 * we already have the correct register contents when encountering the
11551 * vq0->vq0 transition between EL0->EL1.
11553 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
11554 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
11555 ? sve_zcr_len_for_el(env
, old_el
) : 0);
11556 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
11557 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
11558 ? sve_zcr_len_for_el(env
, new_el
) : 0);
11560 /* When changing vector length, clear inaccessible state. */
11561 if (new_len
< old_len
) {
11562 aarch64_sve_narrow_vq(env
, new_len
+ 1);