2 * UniCore32 translation
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
14 #include "disas/disas.h"
17 #include "exec/cpu_ldst.h"
19 #include "exec/helper-proto.h"
20 #include "exec/helper-gen.h"
22 #include "trace-tcg.h"
25 /* internal defines */
26 typedef struct DisasContext
{
29 /* Nonzero if this instruction has been conditionally skipped. */
31 /* The label that will be jumped to when the instruction is skipped. */
33 struct TranslationBlock
*tb
;
34 int singlestep_enabled
;
35 #ifndef CONFIG_USER_ONLY
40 #ifndef CONFIG_USER_ONLY
41 #define IS_USER(s) (s->user)
46 /* These instructions trap after executing, so defer them until after the
47 conditional executions state has been updated. */
48 #define DISAS_SYSCALL 5
50 static TCGv_ptr cpu_env
;
51 static TCGv_i32 cpu_R
[32];
53 /* FIXME: These should be removed. */
54 static TCGv cpu_F0s
, cpu_F1s
;
55 static TCGv_i64 cpu_F0d
, cpu_F1d
;
57 #include "exec/gen-icount.h"
59 static const char *regnames
[] = {
60 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
61 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
62 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
63 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
65 /* initialize TCG globals. */
66 void uc32_translate_init(void)
70 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
72 for (i
= 0; i
< 32; i
++) {
73 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
74 offsetof(CPUUniCore32State
, regs
[i
]), regnames
[i
]);
80 /* Allocate a temporary variable. */
81 static TCGv_i32
new_tmp(void)
84 return tcg_temp_new_i32();
87 /* Release a temporary variable. */
88 static void dead_tmp(TCGv tmp
)
94 static inline TCGv
load_cpu_offset(int offset
)
97 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
101 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
103 static inline void store_cpu_offset(TCGv var
, int offset
)
105 tcg_gen_st_i32(var
, cpu_env
, offset
);
109 #define store_cpu_field(var, name) \
110 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
112 /* Set a variable to the value of a CPU register. */
113 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
117 /* normaly, since we updated PC */
119 tcg_gen_movi_i32(var
, addr
);
121 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
125 /* Create a new temporary and set it to the value of a CPU register. */
126 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
128 TCGv tmp
= new_tmp();
129 load_reg_var(s
, tmp
, reg
);
133 /* Set a CPU register. The source must be a temporary and will be
135 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
138 tcg_gen_andi_i32(var
, var
, ~3);
139 s
->is_jmp
= DISAS_JUMP
;
141 tcg_gen_mov_i32(cpu_R
[reg
], var
);
145 /* Value extensions. */
146 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
147 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
148 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
149 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
151 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
152 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
153 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
154 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
155 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
156 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
157 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
158 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
159 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
160 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
161 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
162 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
163 #define UCOP_COND (((insn) >> 25) & 0x0f)
164 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
165 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
166 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
167 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
168 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
170 #define UCOP_SET(i) ((insn) & (1 << (i)))
171 #define UCOP_SET_P UCOP_SET(28)
172 #define UCOP_SET_U UCOP_SET(27)
173 #define UCOP_SET_B UCOP_SET(26)
174 #define UCOP_SET_W UCOP_SET(25)
175 #define UCOP_SET_L UCOP_SET(24)
176 #define UCOP_SET_S UCOP_SET(24)
178 #define ILLEGAL cpu_abort(CPU(cpu), \
179 "Illegal UniCore32 instruction %x at line %d!", \
182 #ifndef CONFIG_USER_ONLY
183 static void disas_cp0_insn(CPUUniCore32State
*env
, DisasContext
*s
,
186 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
187 TCGv tmp
, tmp2
, tmp3
;
188 if ((insn
& 0xfe000000) == 0xe0000000) {
191 tcg_gen_movi_i32(tmp2
, UCOP_REG_N
);
192 tcg_gen_movi_i32(tmp3
, UCOP_IMM10
);
195 gen_helper_cp0_get(tmp
, cpu_env
, tmp2
, tmp3
);
196 store_reg(s
, UCOP_REG_D
, tmp
);
198 tmp
= load_reg(s
, UCOP_REG_D
);
199 gen_helper_cp0_set(cpu_env
, tmp
, tmp2
, tmp3
);
209 static void disas_ocd_insn(CPUUniCore32State
*env
, DisasContext
*s
,
212 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
215 if ((insn
& 0xff003fff) == 0xe1000400) {
217 * movc rd, pp.nn, #imm9
219 * nn: UCOP_REG_N (must be 0)
222 if (UCOP_REG_N
== 0) {
224 tcg_gen_movi_i32(tmp
, 0);
225 store_reg(s
, UCOP_REG_D
, tmp
);
231 if ((insn
& 0xff003fff) == 0xe0000401) {
233 * movc pp.nn, rn, #imm9
235 * nn: UCOP_REG_N (must be 1)
238 if (UCOP_REG_N
== 1) {
239 tmp
= load_reg(s
, UCOP_REG_D
);
240 gen_helper_cp1_putc(tmp
);
251 static inline void gen_set_asr(TCGv var
, uint32_t mask
)
253 TCGv tmp_mask
= tcg_const_i32(mask
);
254 gen_helper_asr_write(cpu_env
, var
, tmp_mask
);
255 tcg_temp_free_i32(tmp_mask
);
257 /* Set NZCV flags from the high 4 bits of var. */
258 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
260 static void gen_exception(int excp
)
262 TCGv tmp
= new_tmp();
263 tcg_gen_movi_i32(tmp
, excp
);
264 gen_helper_exception(cpu_env
, tmp
);
268 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
270 /* Set CF to the top bit of var. */
271 static void gen_set_CF_bit31(TCGv var
)
273 TCGv tmp
= new_tmp();
274 tcg_gen_shri_i32(tmp
, var
, 31);
279 /* Set N and Z flags from var. */
280 static inline void gen_logic_CC(TCGv var
)
282 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, NF
));
283 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, ZF
));
286 /* dest = T0 + T1 + CF. */
287 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
290 tcg_gen_add_i32(dest
, t0
, t1
);
291 tmp
= load_cpu_field(CF
);
292 tcg_gen_add_i32(dest
, dest
, tmp
);
296 /* dest = T0 - T1 + CF - 1. */
297 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
300 tcg_gen_sub_i32(dest
, t0
, t1
);
301 tmp
= load_cpu_field(CF
);
302 tcg_gen_add_i32(dest
, dest
, tmp
);
303 tcg_gen_subi_i32(dest
, dest
, 1);
307 static void shifter_out_im(TCGv var
, int shift
)
309 TCGv tmp
= new_tmp();
311 tcg_gen_andi_i32(tmp
, var
, 1);
313 tcg_gen_shri_i32(tmp
, var
, shift
);
315 tcg_gen_andi_i32(tmp
, tmp
, 1);
322 /* Shift by immediate. Includes special handling for shift == 0. */
323 static inline void gen_uc32_shift_im(TCGv var
, int shiftop
, int shift
,
330 shifter_out_im(var
, 32 - shift
);
332 tcg_gen_shli_i32(var
, var
, shift
);
338 tcg_gen_shri_i32(var
, var
, 31);
341 tcg_gen_movi_i32(var
, 0);
344 shifter_out_im(var
, shift
- 1);
346 tcg_gen_shri_i32(var
, var
, shift
);
354 shifter_out_im(var
, shift
- 1);
359 tcg_gen_sari_i32(var
, var
, shift
);
361 case 3: /* ROR/RRX */
364 shifter_out_im(var
, shift
- 1);
366 tcg_gen_rotri_i32(var
, var
, shift
); break;
368 TCGv tmp
= load_cpu_field(CF
);
370 shifter_out_im(var
, 0);
372 tcg_gen_shri_i32(var
, var
, 1);
373 tcg_gen_shli_i32(tmp
, tmp
, 31);
374 tcg_gen_or_i32(var
, var
, tmp
);
380 static inline void gen_uc32_shift_reg(TCGv var
, int shiftop
,
381 TCGv shift
, int flags
)
386 gen_helper_shl_cc(var
, cpu_env
, var
, shift
);
389 gen_helper_shr_cc(var
, cpu_env
, var
, shift
);
392 gen_helper_sar_cc(var
, cpu_env
, var
, shift
);
395 gen_helper_ror_cc(var
, cpu_env
, var
, shift
);
401 gen_helper_shl(var
, var
, shift
);
404 gen_helper_shr(var
, var
, shift
);
407 gen_helper_sar(var
, var
, shift
);
410 tcg_gen_andi_i32(shift
, shift
, 0x1f);
411 tcg_gen_rotr_i32(var
, var
, shift
);
418 static void gen_test_cc(int cc
, TCGLabel
*label
)
426 tmp
= load_cpu_field(ZF
);
427 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
430 tmp
= load_cpu_field(ZF
);
431 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
434 tmp
= load_cpu_field(CF
);
435 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
438 tmp
= load_cpu_field(CF
);
439 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
442 tmp
= load_cpu_field(NF
);
443 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
446 tmp
= load_cpu_field(NF
);
447 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
450 tmp
= load_cpu_field(VF
);
451 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
454 tmp
= load_cpu_field(VF
);
455 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
457 case 8: /* hi: C && !Z */
458 inv
= gen_new_label();
459 tmp
= load_cpu_field(CF
);
460 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
462 tmp
= load_cpu_field(ZF
);
463 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
466 case 9: /* ls: !C || Z */
467 tmp
= load_cpu_field(CF
);
468 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
470 tmp
= load_cpu_field(ZF
);
471 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
473 case 10: /* ge: N == V -> N ^ V == 0 */
474 tmp
= load_cpu_field(VF
);
475 tmp2
= load_cpu_field(NF
);
476 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
478 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
480 case 11: /* lt: N != V -> N ^ V != 0 */
481 tmp
= load_cpu_field(VF
);
482 tmp2
= load_cpu_field(NF
);
483 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
485 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
487 case 12: /* gt: !Z && N == V */
488 inv
= gen_new_label();
489 tmp
= load_cpu_field(ZF
);
490 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
492 tmp
= load_cpu_field(VF
);
493 tmp2
= load_cpu_field(NF
);
494 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
496 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
499 case 13: /* le: Z || N != V */
500 tmp
= load_cpu_field(ZF
);
501 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
503 tmp
= load_cpu_field(VF
);
504 tmp2
= load_cpu_field(NF
);
505 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
507 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
510 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
516 static const uint8_t table_logic_cc
[16] = {
517 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
518 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
519 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
520 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
523 /* Set PC state from an immediate address. */
524 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
526 s
->is_jmp
= DISAS_UPDATE
;
527 tcg_gen_movi_i32(cpu_R
[31], addr
& ~3);
530 /* Set PC state from var. var is marked as dead. */
531 static inline void gen_bx(DisasContext
*s
, TCGv var
)
533 s
->is_jmp
= DISAS_UPDATE
;
534 tcg_gen_andi_i32(cpu_R
[31], var
, ~3);
538 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv var
)
540 store_reg(s
, reg
, var
);
543 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
545 TCGv tmp
= new_tmp();
546 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
550 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
552 TCGv tmp
= new_tmp();
553 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
557 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
559 TCGv tmp
= new_tmp();
560 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
564 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
566 TCGv tmp
= new_tmp();
567 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
571 static inline TCGv
gen_ld32(TCGv addr
, int index
)
573 TCGv tmp
= new_tmp();
574 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
578 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
580 tcg_gen_qemu_st8(val
, addr
, index
);
584 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
586 tcg_gen_qemu_st16(val
, addr
, index
);
590 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
592 tcg_gen_qemu_st32(val
, addr
, index
);
596 static inline void gen_set_pc_im(uint32_t val
)
598 tcg_gen_movi_i32(cpu_R
[31], val
);
601 /* Force a TB lookup after an instruction that changes the CPU state. */
602 static inline void gen_lookup_tb(DisasContext
*s
)
604 tcg_gen_movi_i32(cpu_R
[31], s
->pc
& ~1);
605 s
->is_jmp
= DISAS_UPDATE
;
608 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
621 tcg_gen_addi_i32(var
, var
, val
);
625 offset
= load_reg(s
, UCOP_REG_M
);
626 gen_uc32_shift_im(offset
, UCOP_SH_OP
, UCOP_SH_IM
, 0);
628 tcg_gen_sub_i32(var
, var
, offset
);
630 tcg_gen_add_i32(var
, var
, offset
);
636 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
644 val
= (insn
& 0x1f) | ((insn
>> 4) & 0x3e0);
649 tcg_gen_addi_i32(var
, var
, val
);
653 offset
= load_reg(s
, UCOP_REG_M
);
655 tcg_gen_sub_i32(var
, var
, offset
);
657 tcg_gen_add_i32(var
, var
, offset
);
663 static inline long ucf64_reg_offset(int reg
)
666 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
667 + offsetof(CPU_DoubleU
, l
.upper
);
669 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
670 + offsetof(CPU_DoubleU
, l
.lower
);
674 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
675 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
677 /* UniCore-F64 single load/store I_offset */
678 static void do_ucf64_ldst_i(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
680 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
685 addr
= load_reg(s
, UCOP_REG_N
);
686 if (!UCOP_SET_P
&& !UCOP_SET_W
) {
691 offset
= UCOP_IMM10
<< 2;
696 tcg_gen_addi_i32(addr
, addr
, offset
);
700 if (UCOP_SET_L
) { /* load */
701 tmp
= gen_ld32(addr
, IS_USER(s
));
702 ucf64_gen_st32(tmp
, UCOP_REG_D
);
704 tmp
= ucf64_gen_ld32(UCOP_REG_D
);
705 gen_st32(tmp
, addr
, IS_USER(s
));
709 offset
= UCOP_IMM10
<< 2;
714 tcg_gen_addi_i32(addr
, addr
, offset
);
718 store_reg(s
, UCOP_REG_N
, addr
);
724 /* UniCore-F64 load/store multiple words */
725 static void do_ucf64_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
727 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
733 if (UCOP_REG_D
!= 0) {
736 if (UCOP_REG_N
== 31) {
739 if ((insn
<< 24) == 0) {
743 addr
= load_reg(s
, UCOP_REG_N
);
746 for (i
= 0; i
< 8; i
++) {
753 if (UCOP_SET_P
) { /* pre increment */
754 tcg_gen_addi_i32(addr
, addr
, 4);
755 } /* unnecessary to do anything when post increment */
757 if (UCOP_SET_P
) { /* pre decrement */
758 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
759 } else { /* post decrement */
761 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
766 freg
= ((insn
>> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
768 for (i
= 0, j
= 0; i
< 8; i
++, freg
++) {
773 if (UCOP_SET_L
) { /* load */
774 tmp
= gen_ld32(addr
, IS_USER(s
));
775 ucf64_gen_st32(tmp
, freg
);
777 tmp
= ucf64_gen_ld32(freg
);
778 gen_st32(tmp
, addr
, IS_USER(s
));
782 /* unnecessary to add after the last transfer */
784 tcg_gen_addi_i32(addr
, addr
, 4);
788 if (UCOP_SET_W
) { /* write back */
790 if (!UCOP_SET_P
) { /* post increment */
791 tcg_gen_addi_i32(addr
, addr
, 4);
792 } /* unnecessary to do anything when pre increment */
797 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
801 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
804 store_reg(s
, UCOP_REG_N
, addr
);
810 /* UniCore-F64 mrc/mcr */
811 static void do_ucf64_trans(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
813 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
816 if ((insn
& 0xfe0003ff) == 0xe2000000) {
817 /* control register */
818 if ((UCOP_REG_N
!= UC32_UCF64_FPSCR
) || (UCOP_REG_D
== 31)) {
824 gen_helper_ucf64_get_fpscr(tmp
, cpu_env
);
825 store_reg(s
, UCOP_REG_D
, tmp
);
828 tmp
= load_reg(s
, UCOP_REG_D
);
829 gen_helper_ucf64_set_fpscr(cpu_env
, tmp
);
835 if ((insn
& 0xfe0003ff) == 0xe0000000) {
836 /* general register */
837 if (UCOP_REG_D
== 31) {
840 if (UCOP_SET(24)) { /* MFF */
841 tmp
= ucf64_gen_ld32(UCOP_REG_N
);
842 store_reg(s
, UCOP_REG_D
, tmp
);
844 tmp
= load_reg(s
, UCOP_REG_D
);
845 ucf64_gen_st32(tmp
, UCOP_REG_N
);
849 if ((insn
& 0xfb000000) == 0xe9000000) {
851 if (UCOP_REG_D
!= 31) {
854 if (UCOP_UCF64_COND
& 0x8) {
859 tcg_gen_movi_i32(tmp
, UCOP_UCF64_COND
);
861 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
862 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
863 gen_helper_ucf64_cmpd(cpu_F0d
, cpu_F1d
, tmp
, cpu_env
);
865 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
866 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
867 gen_helper_ucf64_cmps(cpu_F0s
, cpu_F1s
, tmp
, cpu_env
);
875 /* UniCore-F64 convert instructions */
876 static void do_ucf64_fcvt(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
878 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
880 if (UCOP_UCF64_FMT
== 3) {
883 if (UCOP_REG_N
!= 0) {
886 switch (UCOP_UCF64_FUNC
) {
888 switch (UCOP_UCF64_FMT
) {
890 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
891 gen_helper_ucf64_df2sf(cpu_F0s
, cpu_F0d
, cpu_env
);
892 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
895 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
896 gen_helper_ucf64_si2sf(cpu_F0s
, cpu_F0s
, cpu_env
);
897 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
905 switch (UCOP_UCF64_FMT
) {
907 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
908 gen_helper_ucf64_sf2df(cpu_F0d
, cpu_F0s
, cpu_env
);
909 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
912 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
913 gen_helper_ucf64_si2df(cpu_F0d
, cpu_F0s
, cpu_env
);
914 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
922 switch (UCOP_UCF64_FMT
) {
924 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
925 gen_helper_ucf64_sf2si(cpu_F0s
, cpu_F0s
, cpu_env
);
926 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
929 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
930 gen_helper_ucf64_df2si(cpu_F0s
, cpu_F0d
, cpu_env
);
931 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
943 /* UniCore-F64 compare instructions */
944 static void do_ucf64_fcmp(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
946 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
951 if (UCOP_REG_D
!= 0) {
957 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
958 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
959 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
961 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
962 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
963 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
967 #define gen_helper_ucf64_movs(x, y) do { } while (0)
968 #define gen_helper_ucf64_movd(x, y) do { } while (0)
970 #define UCF64_OP1(name) do { \
971 if (UCOP_REG_N != 0) { \
974 switch (UCOP_UCF64_FMT) { \
976 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
977 ucf64_reg_offset(UCOP_REG_M)); \
978 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
979 tcg_gen_st_i32(cpu_F0s, cpu_env, \
980 ucf64_reg_offset(UCOP_REG_D)); \
983 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
984 ucf64_reg_offset(UCOP_REG_M)); \
985 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
986 tcg_gen_st_i64(cpu_F0d, cpu_env, \
987 ucf64_reg_offset(UCOP_REG_D)); \
995 #define UCF64_OP2(name) do { \
996 switch (UCOP_UCF64_FMT) { \
998 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
999 ucf64_reg_offset(UCOP_REG_N)); \
1000 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1001 ucf64_reg_offset(UCOP_REG_M)); \
1002 gen_helper_ucf64_##name##s(cpu_F0s, \
1003 cpu_F0s, cpu_F1s, cpu_env); \
1004 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1005 ucf64_reg_offset(UCOP_REG_D)); \
1008 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1009 ucf64_reg_offset(UCOP_REG_N)); \
1010 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1011 ucf64_reg_offset(UCOP_REG_M)); \
1012 gen_helper_ucf64_##name##d(cpu_F0d, \
1013 cpu_F0d, cpu_F1d, cpu_env); \
1014 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1015 ucf64_reg_offset(UCOP_REG_D)); \
1023 /* UniCore-F64 data processing */
1024 static void do_ucf64_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1026 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1028 if (UCOP_UCF64_FMT
== 3) {
1031 switch (UCOP_UCF64_FUNC
) {
1058 /* Disassemble an F64 instruction */
1059 static void disas_ucf64_insn(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1061 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1063 if (!UCOP_SET(29)) {
1065 do_ucf64_ldst_m(env
, s
, insn
);
1067 do_ucf64_ldst_i(env
, s
, insn
);
1071 switch ((insn
>> 26) & 0x3) {
1073 do_ucf64_datap(env
, s
, insn
);
1079 do_ucf64_fcvt(env
, s
, insn
);
1082 do_ucf64_fcmp(env
, s
, insn
);
1086 do_ucf64_trans(env
, s
, insn
);
1091 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
1093 TranslationBlock
*tb
;
1096 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1098 gen_set_pc_im(dest
);
1099 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
1101 gen_set_pc_im(dest
);
1106 static inline void gen_jmp(DisasContext
*s
, uint32_t dest
)
1108 if (unlikely(s
->singlestep_enabled
)) {
1109 /* An indirect jump so that we still trigger the debug exception. */
1112 gen_goto_tb(s
, 0, dest
);
1113 s
->is_jmp
= DISAS_TB_JUMP
;
1117 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1118 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int bsr
, TCGv t0
)
1122 /* ??? This is also undefined in system mode. */
1127 tmp
= load_cpu_field(bsr
);
1128 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
1129 tcg_gen_andi_i32(t0
, t0
, mask
);
1130 tcg_gen_or_i32(tmp
, tmp
, t0
);
1131 store_cpu_field(tmp
, bsr
);
1133 gen_set_asr(t0
, mask
);
1140 /* Generate an old-style exception return. Marks pc as dead. */
1141 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
1144 store_reg(s
, 31, pc
);
1145 tmp
= load_cpu_field(bsr
);
1146 gen_set_asr(tmp
, 0xffffffff);
1148 s
->is_jmp
= DISAS_UPDATE
;
1151 static void disas_coproc_insn(CPUUniCore32State
*env
, DisasContext
*s
,
1154 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1156 switch (UCOP_CPNUM
) {
1157 #ifndef CONFIG_USER_ONLY
1159 disas_cp0_insn(env
, s
, insn
);
1162 disas_ocd_insn(env
, s
, insn
);
1166 disas_ucf64_insn(env
, s
, insn
);
1169 /* Unknown coprocessor. */
1170 cpu_abort(CPU(cpu
), "Unknown coprocessor!");
1174 /* data processing instructions */
1175 static void do_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1177 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1182 if (UCOP_OPCODES
== 0x0f || UCOP_OPCODES
== 0x0d) {
1183 if (UCOP_SET(23)) { /* CMOV instructions */
1184 if ((UCOP_CMOV_COND
== 0xe) || (UCOP_CMOV_COND
== 0xf)) {
1187 /* if not always execute, we generate a conditional jump to
1189 s
->condlabel
= gen_new_label();
1190 gen_test_cc(UCOP_CMOV_COND
^ 1, s
->condlabel
);
1195 logic_cc
= table_logic_cc
[UCOP_OPCODES
] & (UCOP_SET_S
>> 24);
1199 /* immediate operand */
1202 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1205 tcg_gen_movi_i32(tmp2
, val
);
1206 if (logic_cc
&& UCOP_SH_IM
) {
1207 gen_set_CF_bit31(tmp2
);
1211 tmp2
= load_reg(s
, UCOP_REG_M
);
1213 tmp
= load_reg(s
, UCOP_REG_S
);
1214 gen_uc32_shift_reg(tmp2
, UCOP_SH_OP
, tmp
, logic_cc
);
1216 gen_uc32_shift_im(tmp2
, UCOP_SH_OP
, UCOP_SH_IM
, logic_cc
);
1220 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1221 tmp
= load_reg(s
, UCOP_REG_N
);
1226 switch (UCOP_OPCODES
) {
1228 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1232 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1235 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1239 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1242 if (UCOP_SET_S
&& UCOP_REG_D
== 31) {
1243 /* SUBS r31, ... is used for exception return. */
1247 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1248 gen_exception_return(s
, tmp
);
1251 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1253 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
1255 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1260 gen_helper_sub_cc(tmp
, cpu_env
, tmp2
, tmp
);
1262 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
1264 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1268 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1270 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1272 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1276 gen_helper_adc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1278 gen_add_carry(tmp
, tmp
, tmp2
);
1280 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1284 gen_helper_sbc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1286 gen_sub_carry(tmp
, tmp
, tmp2
);
1288 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1292 gen_helper_sbc_cc(tmp
, cpu_env
, tmp2
, tmp
);
1294 gen_sub_carry(tmp
, tmp2
, tmp
);
1296 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1300 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1307 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1314 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1320 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1325 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1329 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1332 if (logic_cc
&& UCOP_REG_D
== 31) {
1333 /* MOVS r31, ... is used for exception return. */
1337 gen_exception_return(s
, tmp2
);
1342 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1346 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1350 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1354 tcg_gen_not_i32(tmp2
, tmp2
);
1358 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1361 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1367 static void do_mult(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1369 TCGv tmp
, tmp2
, tmp3
, tmp4
;
1373 tmp
= load_reg(s
, UCOP_REG_M
);
1374 tmp2
= load_reg(s
, UCOP_REG_N
);
1376 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
1378 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
1380 if (UCOP_SET(25)) { /* mult accumulate */
1381 tmp3
= load_reg(s
, UCOP_REG_LO
);
1382 tmp4
= load_reg(s
, UCOP_REG_HI
);
1383 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, tmp3
, tmp4
);
1387 store_reg(s
, UCOP_REG_LO
, tmp
);
1388 store_reg(s
, UCOP_REG_HI
, tmp2
);
1391 tmp
= load_reg(s
, UCOP_REG_M
);
1392 tmp2
= load_reg(s
, UCOP_REG_N
);
1393 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
1397 tmp2
= load_reg(s
, UCOP_REG_S
);
1398 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1404 store_reg(s
, UCOP_REG_D
, tmp
);
1408 /* miscellaneous instructions */
1409 static void do_misc(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1411 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1415 if ((insn
& 0xffffffe0) == 0x10ffc120) {
1416 /* Trivial implementation equivalent to bx. */
1417 tmp
= load_reg(s
, UCOP_REG_M
);
1422 if ((insn
& 0xfbffc000) == 0x30ffc000) {
1423 /* PSR = immediate */
1426 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1429 tcg_gen_movi_i32(tmp
, val
);
1430 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1436 if ((insn
& 0xfbffffe0) == 0x12ffc020) {
1437 /* PSR.flag = reg */
1438 tmp
= load_reg(s
, UCOP_REG_M
);
1439 if (gen_set_psr(s
, ASR_NZCV
, UCOP_SET_B
, tmp
)) {
1445 if ((insn
& 0xfbffffe0) == 0x10ffc020) {
1447 tmp
= load_reg(s
, UCOP_REG_M
);
1448 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1454 if ((insn
& 0xfbf83fff) == 0x10f80000) {
1460 tmp
= load_cpu_field(bsr
);
1463 gen_helper_asr_read(tmp
, cpu_env
);
1465 store_reg(s
, UCOP_REG_D
, tmp
);
1469 if ((insn
& 0xfbf83fe0) == 0x12f80120) {
1471 tmp
= load_reg(s
, UCOP_REG_M
);
1473 gen_helper_clo(tmp
, tmp
);
1475 gen_helper_clz(tmp
, tmp
);
1477 store_reg(s
, UCOP_REG_D
, tmp
);
1485 /* load/store I_offset and R_offset */
1486 static void do_ldst_ir(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1488 unsigned int mmu_idx
;
1492 tmp2
= load_reg(s
, UCOP_REG_N
);
1493 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1497 gen_add_data_offset(s
, insn
, tmp2
);
1503 tmp
= gen_ld8u(tmp2
, mmu_idx
);
1505 tmp
= gen_ld32(tmp2
, mmu_idx
);
1509 tmp
= load_reg(s
, UCOP_REG_D
);
1511 gen_st8(tmp
, tmp2
, mmu_idx
);
1513 gen_st32(tmp
, tmp2
, mmu_idx
);
1517 gen_add_data_offset(s
, insn
, tmp2
);
1518 store_reg(s
, UCOP_REG_N
, tmp2
);
1519 } else if (UCOP_SET_W
) {
1520 store_reg(s
, UCOP_REG_N
, tmp2
);
1525 /* Complete the load. */
1526 if (UCOP_REG_D
== 31) {
1529 store_reg(s
, UCOP_REG_D
, tmp
);
1534 /* SWP instruction */
1535 static void do_swap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1537 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1542 if ((insn
& 0xff003fe0) != 0x40000120) {
1546 /* ??? This is not really atomic. However we know
1547 we never have multiple CPUs running in parallel,
1548 so it is good enough. */
1549 addr
= load_reg(s
, UCOP_REG_N
);
1550 tmp
= load_reg(s
, UCOP_REG_M
);
1552 tmp2
= gen_ld8u(addr
, IS_USER(s
));
1553 gen_st8(tmp
, addr
, IS_USER(s
));
1555 tmp2
= gen_ld32(addr
, IS_USER(s
));
1556 gen_st32(tmp
, addr
, IS_USER(s
));
1559 store_reg(s
, UCOP_REG_D
, tmp2
);
1562 /* load/store hw/sb */
1563 static void do_ldst_hwsb(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1565 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1569 if (UCOP_SH_OP
== 0) {
1570 do_swap(env
, s
, insn
);
1574 addr
= load_reg(s
, UCOP_REG_N
);
1576 gen_add_datah_offset(s
, insn
, addr
);
1579 if (UCOP_SET_L
) { /* load */
1580 switch (UCOP_SH_OP
) {
1582 tmp
= gen_ld16u(addr
, IS_USER(s
));
1585 tmp
= gen_ld8s(addr
, IS_USER(s
));
1587 default: /* see do_swap */
1589 tmp
= gen_ld16s(addr
, IS_USER(s
));
1592 } else { /* store */
1593 if (UCOP_SH_OP
!= 1) {
1596 tmp
= load_reg(s
, UCOP_REG_D
);
1597 gen_st16(tmp
, addr
, IS_USER(s
));
1599 /* Perform base writeback before the loaded value to
1600 ensure correct behavior with overlapping index registers. */
1602 gen_add_datah_offset(s
, insn
, addr
);
1603 store_reg(s
, UCOP_REG_N
, addr
);
1604 } else if (UCOP_SET_W
) {
1605 store_reg(s
, UCOP_REG_N
, addr
);
1610 /* Complete the load. */
1611 store_reg(s
, UCOP_REG_D
, tmp
);
1615 /* load/store multiple words */
1616 static void do_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1618 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1619 unsigned int val
, i
, mmu_idx
;
1620 int j
, n
, reg
, user
, loaded_base
;
1629 /* XXX: store correct base if write back */
1631 if (UCOP_SET_B
) { /* S bit in instruction table */
1633 ILLEGAL
; /* only usable in supervisor mode */
1635 if (UCOP_SET(18) == 0) { /* pc reg */
1640 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1641 addr
= load_reg(s
, UCOP_REG_N
);
1643 /* compute total size */
1645 TCGV_UNUSED(loaded_var
);
1647 for (i
= 0; i
< 6; i
++) {
1652 for (i
= 9; i
< 19; i
++) {
1657 /* XXX: test invalid n == 0 case ? */
1661 tcg_gen_addi_i32(addr
, addr
, 4);
1663 /* post increment */
1668 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1670 /* post decrement */
1672 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1678 reg
= UCOP_SET(6) ? 16 : 0;
1679 for (i
= 0; i
< 19; i
++, reg
++) {
1684 if (UCOP_SET_L
) { /* load */
1685 tmp
= gen_ld32(addr
, mmu_idx
);
1689 tmp2
= tcg_const_i32(reg
);
1690 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
1691 tcg_temp_free_i32(tmp2
);
1693 } else if (reg
== UCOP_REG_N
) {
1697 store_reg(s
, reg
, tmp
);
1699 } else { /* store */
1701 /* special case: r31 = PC + 4 */
1704 tcg_gen_movi_i32(tmp
, val
);
1707 tmp2
= tcg_const_i32(reg
);
1708 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
1709 tcg_temp_free_i32(tmp2
);
1711 tmp
= load_reg(s
, reg
);
1713 gen_st32(tmp
, addr
, mmu_idx
);
1716 /* no need to add after the last transfer */
1718 tcg_gen_addi_i32(addr
, addr
, 4);
1722 if (UCOP_SET_W
) { /* write back */
1727 /* post increment */
1728 tcg_gen_addi_i32(addr
, addr
, 4);
1734 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1737 /* post decrement */
1738 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1741 store_reg(s
, UCOP_REG_N
, addr
);
1746 store_reg(s
, UCOP_REG_N
, loaded_var
);
1748 if (UCOP_SET_B
&& !user
) {
1749 /* Restore ASR from BSR. */
1750 tmp
= load_cpu_field(bsr
);
1751 gen_set_asr(tmp
, 0xffffffff);
1753 s
->is_jmp
= DISAS_UPDATE
;
1757 /* branch (and link) */
1758 static void do_branch(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1760 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1765 if (UCOP_COND
== 0xf) {
1769 if (UCOP_COND
!= 0xe) {
1770 /* if not always execute, we generate a conditional jump to
1772 s
->condlabel
= gen_new_label();
1773 gen_test_cc(UCOP_COND
^ 1, s
->condlabel
);
1777 val
= (int32_t)s
->pc
;
1780 tcg_gen_movi_i32(tmp
, val
);
1781 store_reg(s
, 30, tmp
);
1783 offset
= (((int32_t)insn
<< 8) >> 8);
1784 val
+= (offset
<< 2); /* unicore is pc+4 */
1788 static void disas_uc32_insn(CPUUniCore32State
*env
, DisasContext
*s
)
1790 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1793 insn
= cpu_ldl_code(env
, s
->pc
);
1796 /* UniCore instructions class:
1797 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1798 * AAA : see switch case
1799 * BBBB : opcodes or cond or PUBW
1804 switch (insn
>> 29) {
1806 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1807 do_mult(env
, s
, insn
);
1812 do_misc(env
, s
, insn
);
1816 if (((UCOP_OPCODES
>> 2) == 2) && !UCOP_SET_S
) {
1817 do_misc(env
, s
, insn
);
1820 do_datap(env
, s
, insn
);
1824 if (UCOP_SET(8) && UCOP_SET(5)) {
1825 do_ldst_hwsb(env
, s
, insn
);
1828 if (UCOP_SET(8) || UCOP_SET(5)) {
1832 do_ldst_ir(env
, s
, insn
);
1837 ILLEGAL
; /* extended instructions */
1839 do_ldst_m(env
, s
, insn
);
1842 do_branch(env
, s
, insn
);
1846 disas_coproc_insn(env
, s
, insn
);
1849 if (!UCOP_SET(28)) {
1850 disas_coproc_insn(env
, s
, insn
);
1853 if ((insn
& 0xff000000) == 0xff000000) { /* syscall */
1854 gen_set_pc_im(s
->pc
);
1855 s
->is_jmp
= DISAS_SYSCALL
;
1862 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
1863 basic block 'tb'. */
1864 void gen_intermediate_code(CPUUniCore32State
*env
, TranslationBlock
*tb
)
1866 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1867 CPUState
*cs
= CPU(cpu
);
1868 DisasContext dc1
, *dc
= &dc1
;
1869 target_ulong pc_start
;
1870 uint32_t next_page_start
;
1874 /* generate intermediate code */
1881 dc
->is_jmp
= DISAS_NEXT
;
1883 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1885 cpu_F0s
= tcg_temp_new_i32();
1886 cpu_F1s
= tcg_temp_new_i32();
1887 cpu_F0d
= tcg_temp_new_i64();
1888 cpu_F1d
= tcg_temp_new_i64();
1889 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1891 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1892 if (max_insns
== 0) {
1893 max_insns
= CF_COUNT_MASK
;
1895 if (max_insns
> TCG_MAX_INSNS
) {
1896 max_insns
= TCG_MAX_INSNS
;
1899 #ifndef CONFIG_USER_ONLY
1900 if ((env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
) {
1909 tcg_gen_insn_start(dc
->pc
);
1912 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
1913 gen_set_pc_im(dc
->pc
);
1914 gen_exception(EXCP_DEBUG
);
1915 dc
->is_jmp
= DISAS_JUMP
;
1916 /* The address covered by the breakpoint must be included in
1917 [tb->pc, tb->pc + tb->size) in order to for it to be
1918 properly cleared -- thus we increment the PC here so that
1919 the logic setting tb->size below does the right thing. */
1921 goto done_generating
;
1924 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
1928 disas_uc32_insn(env
, dc
);
1931 fprintf(stderr
, "Internal resource leak before %08x\n", dc
->pc
);
1935 if (dc
->condjmp
&& !dc
->is_jmp
) {
1936 gen_set_label(dc
->condlabel
);
1939 /* Translation stops when a conditional branch is encountered.
1940 * Otherwise the subsequent code could get translated several times.
1941 * Also stop translation when a page boundary is reached. This
1942 * ensures prefetch aborts occur at the right place. */
1943 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
1944 !cs
->singlestep_enabled
&&
1946 dc
->pc
< next_page_start
&&
1947 num_insns
< max_insns
);
1949 if (tb
->cflags
& CF_LAST_IO
) {
1951 /* FIXME: This can theoretically happen with self-modifying
1953 cpu_abort(cs
, "IO on conditional branch instruction");
1958 /* At this stage dc->condjmp will only be set when the skipped
1959 instruction was a conditional branch or trap, and the PC has
1960 already been written. */
1961 if (unlikely(cs
->singlestep_enabled
)) {
1962 /* Make sure the pc is updated, and raise a debug exception. */
1964 if (dc
->is_jmp
== DISAS_SYSCALL
) {
1965 gen_exception(UC32_EXCP_PRIV
);
1967 gen_exception(EXCP_DEBUG
);
1969 gen_set_label(dc
->condlabel
);
1971 if (dc
->condjmp
|| !dc
->is_jmp
) {
1972 gen_set_pc_im(dc
->pc
);
1975 if (dc
->is_jmp
== DISAS_SYSCALL
&& !dc
->condjmp
) {
1976 gen_exception(UC32_EXCP_PRIV
);
1978 gen_exception(EXCP_DEBUG
);
1981 /* While branches must always occur at the end of an IT block,
1982 there are a few other things that can cause us to terminate
1983 the TB in the middel of an IT block:
1984 - Exception generating instructions (bkpt, swi, undefined).
1986 - Hardware watchpoints.
1987 Hardware breakpoints have already been handled and skip this code.
1989 switch (dc
->is_jmp
) {
1991 gen_goto_tb(dc
, 1, dc
->pc
);
1996 /* indicate that the hash table must be used to find the next TB */
2000 /* nothing more to generate */
2003 gen_exception(UC32_EXCP_PRIV
);
2007 gen_set_label(dc
->condlabel
);
2008 gen_goto_tb(dc
, 1, dc
->pc
);
2014 gen_tb_end(tb
, num_insns
);
2017 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
2018 qemu_log("----------------\n");
2019 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2020 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
2024 tb
->size
= dc
->pc
- pc_start
;
2025 tb
->icount
= num_insns
;
2028 static const char *cpu_mode_names
[16] = {
2029 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2030 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2033 #undef UCF64_DUMP_STATE
2034 #ifdef UCF64_DUMP_STATE
2035 static void cpu_dump_state_ucf64(CPUUniCore32State
*env
, FILE *f
,
2036 fprintf_function cpu_fprintf
, int flags
)
2044 /* ??? This assumes float64 and double have the same layout.
2045 Oh well, it's only debug dumps. */
2051 for (i
= 0; i
< 16; i
++) {
2052 d
.d
= env
->ucf64
.regs
[i
];
2056 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2057 i
* 2, (int)s0
.i
, s0
.s
,
2058 i
* 2 + 1, (int)s1
.i
, s1
.s
);
2059 cpu_fprintf(f
, " d%02d=%" PRIx64
"(%8g)\n",
2060 i
, (uint64_t)d0
.f64
, d0
.d
);
2062 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->ucf64
.xregs
[UC32_UCF64_FPSCR
]);
2065 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2068 void uc32_cpu_dump_state(CPUState
*cs
, FILE *f
,
2069 fprintf_function cpu_fprintf
, int flags
)
2071 UniCore32CPU
*cpu
= UNICORE32_CPU(cs
);
2072 CPUUniCore32State
*env
= &cpu
->env
;
2076 for (i
= 0; i
< 32; i
++) {
2077 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
2079 cpu_fprintf(f
, "\n");
2081 cpu_fprintf(f
, " ");
2084 psr
= cpu_asr_read(env
);
2085 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %s\n",
2087 psr
& (1 << 31) ? 'N' : '-',
2088 psr
& (1 << 30) ? 'Z' : '-',
2089 psr
& (1 << 29) ? 'C' : '-',
2090 psr
& (1 << 28) ? 'V' : '-',
2091 cpu_mode_names
[psr
& 0xf]);
2093 cpu_dump_state_ucf64(env
, f
, cpu_fprintf
, flags
);
2096 void restore_state_to_opc(CPUUniCore32State
*env
, TranslationBlock
*tb
,
2099 env
->regs
[31] = data
[0];