hw/timer/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "qemu/timer.h"
  27 #include "sysemu/sysemu.h"
  28 #include "hw/timer/mc146818rtc.h"
  29 #include "qapi/visitor.h"
  30 #include "qapi-event.h"
  31 #include "qmp-commands.h"
  32
  33 #ifdef TARGET_I386
  34 #include "hw/i386/apic.h"
  35 #endif
  36
  37 //#define DEBUG_CMOS
  38 //#define DEBUG_COALESCED
  39
  40 #ifdef DEBUG_CMOS
  41 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  42 #else
  43 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  44 #endif
  45
  46 #ifdef DEBUG_COALESCED
  47 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  48 #else
  49 # define DPRINTF_C(format, ...)      do { } while (0)
  50 #endif
  51
  52 #define SEC_PER_MIN     60
  53 #define MIN_PER_HOUR    60
  54 #define SEC_PER_HOUR    3600
  55 #define HOUR_PER_DAY    24
  56 #define SEC_PER_DAY     86400
  57
  58 #define RTC_REINJECT_ON_ACK_COUNT 20
  59 #define RTC_CLOCK_RATE            32768
  60 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
  61
  62 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
  63
  64 typedef struct RTCState {
  65     ISADevice parent_obj;
  66
  67     MemoryRegion io;
  68     uint8_t cmos_data[128];
  69     uint8_t cmos_index;
  70     int32_t base_year;
  71     uint64_t base_rtc;
  72     uint64_t last_update;
  73     int64_t offset;
  74     qemu_irq irq;
  75     int it_shift;
  76     /* periodic timer */
  77     QEMUTimer *periodic_timer;
  78     int64_t next_periodic_time;
  79     /* update-ended timer */
  80     QEMUTimer *update_timer;
  81     uint64_t next_alarm_time;
  82     uint16_t irq_reinject_on_ack_count;
  83     uint32_t irq_coalesced;
  84     uint32_t period;
  85     QEMUTimer *coalesced_timer;
  86     Notifier clock_reset_notifier;
  87     LostTickPolicy lost_tick_policy;
  88     Notifier suspend_notifier;
  89     QLIST_ENTRY(RTCState) link;
  90 } RTCState;
  91
  92 static void rtc_set_time(RTCState *s);
  93 static void rtc_update_time(RTCState *s);
  94 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  95 static inline int rtc_from_bcd(RTCState *s, int a);
  96 static uint64_t get_next_alarm(RTCState *s);
  97
  98 static inline bool rtc_running(RTCState *s)
  99 {
 100     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 101             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
 102 }
 103
 104 static uint64_t get_guest_rtc_ns(RTCState *s)
 105 {
 106     uint64_t guest_rtc;
 107     uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
 108
 109     guest_rtc = s->base_rtc * NANOSECONDS_PER_SECOND
 110                  + guest_clock - s->last_update + s->offset;
 111     return guest_rtc;
 112 }
 113
 114 #ifdef TARGET_I386
 115 static void rtc_coalesced_timer_update(RTCState *s)
 116 {
 117     if (s->irq_coalesced == 0) {
 118         timer_del(s->coalesced_timer);
 119     } else {
 120         /* divide each RTC interval to 2 - 8 smaller intervals */
 121         int c = MIN(s->irq_coalesced, 7) + 1;
 122         int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
 123             muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
 124         timer_mod(s->coalesced_timer, next_clock);
 125     }
 126 }
 127
 128 static void rtc_coalesced_timer(void *opaque)
 129 {
 130     RTCState *s = opaque;
 131
 132     if (s->irq_coalesced != 0) {
 133         apic_reset_irq_delivered();
 134         s->cmos_data[RTC_REG_C] |= 0xc0;
 135         DPRINTF_C("cmos: injecting from timer\n");
 136         qemu_irq_raise(s->irq);
 137         if (apic_get_irq_delivered()) {
 138             s->irq_coalesced--;
 139             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 140                       s->irq_coalesced);
 141         }
 142     }
 143
 144     rtc_coalesced_timer_update(s);
 145 }
 146 #endif
 147
 148 /* handle periodic timer */
 149 static void periodic_timer_update(RTCState *s, int64_t current_time)
 150 {
 151     int period_code, period;
 152     int64_t cur_clock, next_irq_clock;
 153
 154     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 155     if (period_code != 0
 156         && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
 157         if (period_code <= 2)
 158             period_code += 7;
 159         /* period in 32 Khz cycles */
 160         period = 1 << (period_code - 1);
 161 #ifdef TARGET_I386
 162         if (period != s->period) {
 163             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 164             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 165         }
 166         s->period = period;
 167 #endif
 168         /* compute 32 khz clock */
 169         cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
 170         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 171         s->next_periodic_time =
 172             muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
 173         timer_mod(s->periodic_timer, s->next_periodic_time);
 174     } else {
 175 #ifdef TARGET_I386
 176         s->irq_coalesced = 0;
 177 #endif
 178         timer_del(s->periodic_timer);
 179     }
 180 }
 181
 182 static void rtc_periodic_timer(void *opaque)
 183 {
 184     RTCState *s = opaque;
 185
 186     periodic_timer_update(s, s->next_periodic_time);
 187     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 188     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 189         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 190 #ifdef TARGET_I386
 191         if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 192             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 193                 s->irq_reinject_on_ack_count = 0;
 194             apic_reset_irq_delivered();
 195             qemu_irq_raise(s->irq);
 196             if (!apic_get_irq_delivered()) {
 197                 s->irq_coalesced++;
 198                 rtc_coalesced_timer_update(s);
 199                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 200                           s->irq_coalesced);
 201             }
 202         } else
 203 #endif
 204         qemu_irq_raise(s->irq);
 205     }
 206 }
 207
 208 /* handle update-ended timer */
 209 static void check_update_timer(RTCState *s)
 210 {
 211     uint64_t next_update_time;
 212     uint64_t guest_nsec;
 213     int next_alarm_sec;
 214
 215     /* From the data sheet: "Holding the dividers in reset prevents
 216      * interrupts from operating, while setting the SET bit allows"
 217      * them to occur.  However, it will prevent an alarm interrupt
 218      * from occurring, because the time of day is not updated.
 219      */
 220     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 221         timer_del(s->update_timer);
 222         return;
 223     }
 224     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 225         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 226         timer_del(s->update_timer);
 227         return;
 228     }
 229     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 230         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 231         timer_del(s->update_timer);
 232         return;
 233     }
 234
 235     guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
 236     /* if UF is clear, reprogram to next second */
 237     next_update_time = qemu_clock_get_ns(rtc_clock)
 238         + NANOSECONDS_PER_SECOND - guest_nsec;
 239
 240     /* Compute time of next alarm.  One second is already accounted
 241      * for in next_update_time.
 242      */
 243     next_alarm_sec = get_next_alarm(s);
 244     s->next_alarm_time = next_update_time +
 245                          (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND;
 246
 247     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 248         /* UF is set, but AF is clear.  Program the timer to target
 249          * the alarm time.  */
 250         next_update_time = s->next_alarm_time;
 251     }
 252     if (next_update_time != timer_expire_time_ns(s->update_timer)) {
 253         timer_mod(s->update_timer, next_update_time);
 254     }
 255 }
 256
 257 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 258 {
 259     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 260         hour %= 12;
 261         if (s->cmos_data[RTC_HOURS] & 0x80) {
 262             hour += 12;
 263         }
 264     }
 265     return hour;
 266 }
 267
 268 static uint64_t get_next_alarm(RTCState *s)
 269 {
 270     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 271     int32_t hour, min, sec;
 272
 273     rtc_update_time(s);
 274
 275     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 276     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 277     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 278     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 279
 280     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 281     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 282     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 283     cur_hour = convert_hour(s, cur_hour);
 284
 285     if (alarm_hour == -1) {
 286         alarm_hour = cur_hour;
 287         if (alarm_min == -1) {
 288             alarm_min = cur_min;
 289             if (alarm_sec == -1) {
 290                 alarm_sec = cur_sec + 1;
 291             } else if (cur_sec > alarm_sec) {
 292                 alarm_min++;
 293             }
 294         } else if (cur_min == alarm_min) {
 295             if (alarm_sec == -1) {
 296                 alarm_sec = cur_sec + 1;
 297             } else {
 298                 if (cur_sec > alarm_sec) {
 299                     alarm_hour++;
 300                 }
 301             }
 302             if (alarm_sec == SEC_PER_MIN) {
 303                 /* wrap to next hour, minutes is not in don't care mode */
 304                 alarm_sec = 0;
 305                 alarm_hour++;
 306             }
 307         } else if (cur_min > alarm_min) {
 308             alarm_hour++;
 309         }
 310     } else if (cur_hour == alarm_hour) {
 311         if (alarm_min == -1) {
 312             alarm_min = cur_min;
 313             if (alarm_sec == -1) {
 314                 alarm_sec = cur_sec + 1;
 315             } else if (cur_sec > alarm_sec) {
 316                 alarm_min++;
 317             }
 318
 319             if (alarm_sec == SEC_PER_MIN) {
 320                 alarm_sec = 0;
 321                 alarm_min++;
 322             }
 323             /* wrap to next day, hour is not in don't care mode */
 324             alarm_min %= MIN_PER_HOUR;
 325         } else if (cur_min == alarm_min) {
 326             if (alarm_sec == -1) {
 327                 alarm_sec = cur_sec + 1;
 328             }
 329             /* wrap to next day, hours+minutes not in don't care mode */
 330             alarm_sec %= SEC_PER_MIN;
 331         }
 332     }
 333
 334     /* values that are still don't care fire at the next min/sec */
 335     if (alarm_min == -1) {
 336         alarm_min = 0;
 337     }
 338     if (alarm_sec == -1) {
 339         alarm_sec = 0;
 340     }
 341
 342     /* keep values in range */
 343     if (alarm_sec == SEC_PER_MIN) {
 344         alarm_sec = 0;
 345         alarm_min++;
 346     }
 347     if (alarm_min == MIN_PER_HOUR) {
 348         alarm_min = 0;
 349         alarm_hour++;
 350     }
 351     alarm_hour %= HOUR_PER_DAY;
 352
 353     hour = alarm_hour - cur_hour;
 354     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 355     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 356     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 357 }
 358
 359 static void rtc_update_timer(void *opaque)
 360 {
 361     RTCState *s = opaque;
 362     int32_t irqs = REG_C_UF;
 363     int32_t new_irqs;
 364
 365     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 366
 367     /* UIP might have been latched, update time and clear it.  */
 368     rtc_update_time(s);
 369     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 370
 371     if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
 372         irqs |= REG_C_AF;
 373         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 374             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 375         }
 376     }
 377
 378     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 379     s->cmos_data[RTC_REG_C] |= irqs;
 380     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 381         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 382         qemu_irq_raise(s->irq);
 383     }
 384     check_update_timer(s);
 385 }
 386
 387 static void cmos_ioport_write(void *opaque, hwaddr addr,
 388                               uint64_t data, unsigned size)
 389 {
 390     RTCState *s = opaque;
 391
 392     if ((addr & 1) == 0) {
 393         s->cmos_index = data & 0x7f;
 394     } else {
 395         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
 396                      s->cmos_index, data);
 397         switch(s->cmos_index) {
 398         case RTC_SECONDS_ALARM:
 399         case RTC_MINUTES_ALARM:
 400         case RTC_HOURS_ALARM:
 401             s->cmos_data[s->cmos_index] = data;
 402             check_update_timer(s);
 403             break;
 404         case RTC_IBM_PS2_CENTURY_BYTE:
 405             s->cmos_index = RTC_CENTURY;
 406             /* fall through */
 407         case RTC_CENTURY:
 408         case RTC_SECONDS:
 409         case RTC_MINUTES:
 410         case RTC_HOURS:
 411         case RTC_DAY_OF_WEEK:
 412         case RTC_DAY_OF_MONTH:
 413         case RTC_MONTH:
 414         case RTC_YEAR:
 415             s->cmos_data[s->cmos_index] = data;
 416             /* if in set mode, do not update the time */
 417             if (rtc_running(s)) {
 418                 rtc_set_time(s);
 419                 check_update_timer(s);
 420             }
 421             break;
 422         case RTC_REG_A:
 423             if ((data & 0x60) == 0x60) {
 424                 if (rtc_running(s)) {
 425                     rtc_update_time(s);
 426                 }
 427                 /* What happens to UIP when divider reset is enabled is
 428                  * unclear from the datasheet.  Shouldn't matter much
 429                  * though.
 430                  */
 431                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 432             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 433                     (data & 0x70)  <= 0x20) {
 434                 /* when the divider reset is removed, the first update cycle
 435                  * begins one-half second later*/
 436                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 437                     s->offset = 500000000;
 438                     rtc_set_time(s);
 439                 }
 440                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 441             }
 442             /* UIP bit is read only */
 443             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 444                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 445             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 446             check_update_timer(s);
 447             break;
 448         case RTC_REG_B:
 449             if (data & REG_B_SET) {
 450                 /* update cmos to when the rtc was stopping */
 451                 if (rtc_running(s)) {
 452                     rtc_update_time(s);
 453                 }
 454                 /* set mode: reset UIP mode */
 455                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 456                 data &= ~REG_B_UIE;
 457             } else {
 458                 /* if disabling set mode, update the time */
 459                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 460                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 461                     s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
 462                     rtc_set_time(s);
 463                 }
 464             }
 465             /* if an interrupt flag is already set when the interrupt
 466              * becomes enabled, raise an interrupt immediately.  */
 467             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 468                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 469                 qemu_irq_raise(s->irq);
 470             } else {
 471                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 472                 qemu_irq_lower(s->irq);
 473             }
 474             s->cmos_data[RTC_REG_B] = data;
 475             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 476             check_update_timer(s);
 477             break;
 478         case RTC_REG_C:
 479         case RTC_REG_D:
 480             /* cannot write to them */
 481             break;
 482         default:
 483             s->cmos_data[s->cmos_index] = data;
 484             break;
 485         }
 486     }
 487 }
 488
 489 static inline int rtc_to_bcd(RTCState *s, int a)
 490 {
 491     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 492         return a;
 493     } else {
 494         return ((a / 10) << 4) | (a % 10);
 495     }
 496 }
 497
 498 static inline int rtc_from_bcd(RTCState *s, int a)
 499 {
 500     if ((a & 0xc0) == 0xc0) {
 501         return -1;
 502     }
 503     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 504         return a;
 505     } else {
 506         return ((a >> 4) * 10) + (a & 0x0f);
 507     }
 508 }
 509
 510 static void rtc_get_time(RTCState *s, struct tm *tm)
 511 {
 512     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 513     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 514     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 515     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 516         tm->tm_hour %= 12;
 517         if (s->cmos_data[RTC_HOURS] & 0x80) {
 518             tm->tm_hour += 12;
 519         }
 520     }
 521     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 522     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 523     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 524     tm->tm_year =
 525         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 526         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 527 }
 528
 529 static QLIST_HEAD(, RTCState) rtc_devices =
 530     QLIST_HEAD_INITIALIZER(rtc_devices);
 531
 532 #ifdef TARGET_I386
 533 void qmp_rtc_reset_reinjection(Error **errp)
 534 {
 535     RTCState *s;
 536
 537     QLIST_FOREACH(s, &rtc_devices, link) {
 538         s->irq_coalesced = 0;
 539     }
 540 }
 541 #endif
 542
 543 static void rtc_set_time(RTCState *s)
 544 {
 545     struct tm tm;
 546
 547     rtc_get_time(s, &tm);
 548     s->base_rtc = mktimegm(&tm);
 549     s->last_update = qemu_clock_get_ns(rtc_clock);
 550
 551     qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort);
 552 }
 553
 554 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 555 {
 556     int year;
 557
 558     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 559     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 560     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 561         /* 24 hour format */
 562         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 563     } else {
 564         /* 12 hour format */
 565         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 566         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 567         if (tm->tm_hour >= 12)
 568             s->cmos_data[RTC_HOURS] |= 0x80;
 569     }
 570     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 571     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 572     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 573     year = tm->tm_year + 1900 - s->base_year;
 574     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 575     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 576 }
 577
 578 static void rtc_update_time(RTCState *s)
 579 {
 580     struct tm ret;
 581     time_t guest_sec;
 582     int64_t guest_nsec;
 583
 584     guest_nsec = get_guest_rtc_ns(s);
 585     guest_sec = guest_nsec / NANOSECONDS_PER_SECOND;
 586     gmtime_r(&guest_sec, &ret);
 587
 588     /* Is SET flag of Register B disabled? */
 589     if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
 590         rtc_set_cmos(s, &ret);
 591     }
 592 }
 593
 594 static int update_in_progress(RTCState *s)
 595 {
 596     int64_t guest_nsec;
 597
 598     if (!rtc_running(s)) {
 599         return 0;
 600     }
 601     if (timer_pending(s->update_timer)) {
 602         int64_t next_update_time = timer_expire_time_ns(s->update_timer);
 603         /* Latch UIP until the timer expires.  */
 604         if (qemu_clock_get_ns(rtc_clock) >=
 605             (next_update_time - UIP_HOLD_LENGTH)) {
 606             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 607             return 1;
 608         }
 609     }
 610
 611     guest_nsec = get_guest_rtc_ns(s);
 612     /* UIP bit will be set at last 244us of every second. */
 613     if ((guest_nsec % NANOSECONDS_PER_SECOND) >=
 614         (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) {
 615         return 1;
 616     }
 617     return 0;
 618 }
 619
 620 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 621                                  unsigned size)
 622 {
 623     RTCState *s = opaque;
 624     int ret;
 625     if ((addr & 1) == 0) {
 626         return 0xff;
 627     } else {
 628         switch(s->cmos_index) {
 629         case RTC_IBM_PS2_CENTURY_BYTE:
 630             s->cmos_index = RTC_CENTURY;
 631             /* fall through */
 632         case RTC_CENTURY:
 633         case RTC_SECONDS:
 634         case RTC_MINUTES:
 635         case RTC_HOURS:
 636         case RTC_DAY_OF_WEEK:
 637         case RTC_DAY_OF_MONTH:
 638         case RTC_MONTH:
 639         case RTC_YEAR:
 640             /* if not in set mode, calibrate cmos before
 641              * reading*/
 642             if (rtc_running(s)) {
 643                 rtc_update_time(s);
 644             }
 645             ret = s->cmos_data[s->cmos_index];
 646             break;
 647         case RTC_REG_A:
 648             if (update_in_progress(s)) {
 649                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 650             } else {
 651                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 652             }
 653             ret = s->cmos_data[s->cmos_index];
 654             break;
 655         case RTC_REG_C:
 656             ret = s->cmos_data[s->cmos_index];
 657             qemu_irq_lower(s->irq);
 658             s->cmos_data[RTC_REG_C] = 0x00;
 659             if (ret & (REG_C_UF | REG_C_AF)) {
 660                 check_update_timer(s);
 661             }
 662 #ifdef TARGET_I386
 663             if(s->irq_coalesced &&
 664                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 665                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 666                 s->irq_reinject_on_ack_count++;
 667                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 668                 apic_reset_irq_delivered();
 669                 DPRINTF_C("cmos: injecting on ack\n");
 670                 qemu_irq_raise(s->irq);
 671                 if (apic_get_irq_delivered()) {
 672                     s->irq_coalesced--;
 673                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 674                               s->irq_coalesced);
 675                 }
 676             }
 677 #endif
 678             break;
 679         default:
 680             ret = s->cmos_data[s->cmos_index];
 681             break;
 682         }
 683         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 684                      s->cmos_index, ret);
 685         return ret;
 686     }
 687 }
 688
 689 void rtc_set_memory(ISADevice *dev, int addr, int val)
 690 {
 691     RTCState *s = MC146818_RTC(dev);
 692     if (addr >= 0 && addr <= 127)
 693         s->cmos_data[addr] = val;
 694 }
 695
 696 int rtc_get_memory(ISADevice *dev, int addr)
 697 {
 698     RTCState *s = MC146818_RTC(dev);
 699     assert(addr >= 0 && addr <= 127);
 700     return s->cmos_data[addr];
 701 }
 702
 703 static void rtc_set_date_from_host(ISADevice *dev)
 704 {
 705     RTCState *s = MC146818_RTC(dev);
 706     struct tm tm;
 707
 708     qemu_get_timedate(&tm, 0);
 709
 710     s->base_rtc = mktimegm(&tm);
 711     s->last_update = qemu_clock_get_ns(rtc_clock);
 712     s->offset = 0;
 713
 714     /* set the CMOS date */
 715     rtc_set_cmos(s, &tm);
 716 }
 717
 718 static int rtc_post_load(void *opaque, int version_id)
 719 {
 720     RTCState *s = opaque;
 721
 722     if (version_id <= 2) {
 723         rtc_set_time(s);
 724         s->offset = 0;
 725         check_update_timer(s);
 726     }
 727
 728     uint64_t now = qemu_clock_get_ns(rtc_clock);
 729     if (now < s->next_periodic_time ||
 730         now > (s->next_periodic_time + get_max_clock_jump())) {
 731         periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 732     }
 733
 734 #ifdef TARGET_I386
 735     if (version_id >= 2) {
 736         if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 737             rtc_coalesced_timer_update(s);
 738         }
 739     }
 740 #endif
 741     return 0;
 742 }
 743
 744 static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
 745 {
 746     RTCState *s = (RTCState *)opaque;
 747     return s->irq_reinject_on_ack_count != 0;
 748 }
 749
 750 static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
 751     .name = "mc146818rtc/irq_reinject_on_ack_count",
 752     .version_id = 1,
 753     .minimum_version_id = 1,
 754     .needed = rtc_irq_reinject_on_ack_count_needed,
 755     .fields = (VMStateField[]) {
 756         VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
 757         VMSTATE_END_OF_LIST()
 758     }
 759 };
 760
 761 static const VMStateDescription vmstate_rtc = {
 762     .name = "mc146818rtc",
 763     .version_id = 3,
 764     .minimum_version_id = 1,
 765     .post_load = rtc_post_load,
 766     .fields = (VMStateField[]) {
 767         VMSTATE_BUFFER(cmos_data, RTCState),
 768         VMSTATE_UINT8(cmos_index, RTCState),
 769         VMSTATE_UNUSED(7*4),
 770         VMSTATE_TIMER_PTR(periodic_timer, RTCState),
 771         VMSTATE_INT64(next_periodic_time, RTCState),
 772         VMSTATE_UNUSED(3*8),
 773         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 774         VMSTATE_UINT32_V(period, RTCState, 2),
 775         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 776         VMSTATE_UINT64_V(last_update, RTCState, 3),
 777         VMSTATE_INT64_V(offset, RTCState, 3),
 778         VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
 779         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 780         VMSTATE_END_OF_LIST()
 781     },
 782     .subsections = (const VMStateDescription*[]) {
 783         &vmstate_rtc_irq_reinject_on_ack_count,
 784         NULL
 785     }
 786 };
 787
 788 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 789 {
 790     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 791     int64_t now = *(int64_t *)data;
 792
 793     rtc_set_date_from_host(ISA_DEVICE(s));
 794     periodic_timer_update(s, now);
 795     check_update_timer(s);
 796 #ifdef TARGET_I386
 797     if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 798         rtc_coalesced_timer_update(s);
 799     }
 800 #endif
 801 }
 802
 803 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 804    BIOS will read it and start S3 resume at POST Entry */
 805 static void rtc_notify_suspend(Notifier *notifier, void *data)
 806 {
 807     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 808     rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 809 }
 810
 811 static void rtc_reset(void *opaque)
 812 {
 813     RTCState *s = opaque;
 814
 815     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 816     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 817     check_update_timer(s);
 818
 819     qemu_irq_lower(s->irq);
 820
 821 #ifdef TARGET_I386
 822     if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 823         s->irq_coalesced = 0;
 824         s->irq_reinject_on_ack_count = 0;
 825     }
 826 #endif
 827 }
 828
 829 static const MemoryRegionOps cmos_ops = {
 830     .read = cmos_ioport_read,
 831     .write = cmos_ioport_write,
 832     .impl = {
 833         .min_access_size = 1,
 834         .max_access_size = 1,
 835     },
 836     .endianness = DEVICE_LITTLE_ENDIAN,
 837 };
 838
 839 static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
 840 {
 841     RTCState *s = MC146818_RTC(obj);
 842
 843     rtc_update_time(s);
 844     rtc_get_time(s, current_tm);
 845 }
 846
 847 static void rtc_realizefn(DeviceState *dev, Error **errp)
 848 {
 849     ISADevice *isadev = ISA_DEVICE(dev);
 850     RTCState *s = MC146818_RTC(dev);
 851     int base = 0x70;
 852
 853     s->cmos_data[RTC_REG_A] = 0x26;
 854     s->cmos_data[RTC_REG_B] = 0x02;
 855     s->cmos_data[RTC_REG_C] = 0x00;
 856     s->cmos_data[RTC_REG_D] = 0x80;
 857
 858     /* This is for historical reasons.  The default base year qdev property
 859      * was set to 2000 for most machine types before the century byte was
 860      * implemented.
 861      *
 862      * This if statement means that the century byte will be always 0
 863      * (at least until 2079...) for base_year = 1980, but will be set
 864      * correctly for base_year = 2000.
 865      */
 866     if (s->base_year == 2000) {
 867         s->base_year = 0;
 868     }
 869
 870     rtc_set_date_from_host(isadev);
 871
 872 #ifdef TARGET_I386
 873     switch (s->lost_tick_policy) {
 874     case LOST_TICK_POLICY_SLEW:
 875         s->coalesced_timer =
 876             timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
 877         break;
 878     case LOST_TICK_POLICY_DISCARD:
 879         break;
 880     default:
 881         error_setg(errp, "Invalid lost tick policy.");
 882         return;
 883     }
 884 #endif
 885
 886     s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
 887     s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
 888     check_update_timer(s);
 889
 890     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 891     qemu_clock_register_reset_notifier(rtc_clock,
 892                                        &s->clock_reset_notifier);
 893
 894     s->suspend_notifier.notify = rtc_notify_suspend;
 895     qemu_register_suspend_notifier(&s->suspend_notifier);
 896
 897     memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
 898     isa_register_ioport(isadev, &s->io, base);
 899
 900     qdev_set_legacy_instance_id(dev, base, 3);
 901     qemu_register_reset(rtc_reset, s);
 902
 903     object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
 904
 905     object_property_add_alias(qdev_get_machine(), "rtc-time",
 906                               OBJECT(s), "date", NULL);
 907 }
 908
 909 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 910 {
 911     DeviceState *dev;
 912     ISADevice *isadev;
 913     RTCState *s;
 914
 915     isadev = isa_create(bus, TYPE_MC146818_RTC);
 916     dev = DEVICE(isadev);
 917     s = MC146818_RTC(isadev);
 918     qdev_prop_set_int32(dev, "base_year", base_year);
 919     qdev_init_nofail(dev);
 920     if (intercept_irq) {
 921         s->irq = intercept_irq;
 922     } else {
 923         isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
 924     }
 925     QLIST_INSERT_HEAD(&rtc_devices, s, link);
 926
 927     return isadev;
 928 }
 929
 930 static Property mc146818rtc_properties[] = {
 931     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 932     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 933                                lost_tick_policy, LOST_TICK_POLICY_DISCARD),
 934     DEFINE_PROP_END_OF_LIST(),
 935 };
 936
 937 static void rtc_class_initfn(ObjectClass *klass, void *data)
 938 {
 939     DeviceClass *dc = DEVICE_CLASS(klass);
 940
 941     dc->realize = rtc_realizefn;
 942     dc->vmsd = &vmstate_rtc;
 943     dc->props = mc146818rtc_properties;
 944     /* Reason: needs to be wired up by rtc_init() */
 945     dc->cannot_instantiate_with_device_add_yet = true;
 946 }
 947
 948 static void rtc_finalize(Object *obj)
 949 {
 950     object_property_del(qdev_get_machine(), "rtc", NULL);
 951 }
 952
 953 static const TypeInfo mc146818rtc_info = {
 954     .name          = TYPE_MC146818_RTC,
 955     .parent        = TYPE_ISA_DEVICE,
 956     .instance_size = sizeof(RTCState),
 957     .class_init    = rtc_class_initfn,
 958     .instance_finalize = rtc_finalize,
 959 };
 960
 961 static void mc146818rtc_register_types(void)
 962 {
 963     type_register_static(&mc146818rtc_info);
 964 }
 965
 966 type_init(mc146818rtc_register_types)