hw/timer/imx_gpt.c

   1 /*
   2  * IMX GPT Timer
   3  *
   4  * Copyright (c) 2008 OK Labs
   5  * Copyright (c) 2011 NICTA Pty Ltd
   6  * Originally written by Hans Jiang
   7  * Updated by Peter Chubb
   8  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   9  *
  10  * This code is licensed under GPL version 2 or later.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "hw/timer/imx_gpt.h"
  17 #include "hw/misc/imx_ccm.h"
  18 #include "qemu/main-loop.h"
  19
  20 #ifndef DEBUG_IMX_GPT
  21 #define DEBUG_IMX_GPT 0
  22 #endif
  23
  24 #define DPRINTF(fmt, args...) \
  25     do { \
  26         if (DEBUG_IMX_GPT) { \
  27             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
  28                                              __func__, ##args); \
  29         } \
  30     } while (0)
  31
  32 static char const *imx_gpt_reg_name(uint32_t reg)
  33 {
  34     switch (reg) {
  35     case 0:
  36         return "CR";
  37     case 1:
  38         return "PR";
  39     case 2:
  40         return "SR";
  41     case 3:
  42         return "IR";
  43     case 4:
  44         return "OCR1";
  45     case 5:
  46         return "OCR2";
  47     case 6:
  48         return "OCR3";
  49     case 7:
  50         return "ICR1";
  51     case 8:
  52         return "ICR2";
  53     case 9:
  54         return "CNT";
  55     default:
  56         return "[?]";
  57     }
  58 }
  59
  60 static const VMStateDescription vmstate_imx_timer_gpt = {
  61     .name = TYPE_IMX_GPT,
  62     .version_id = 3,
  63     .minimum_version_id = 3,
  64     .fields = (VMStateField[]) {
  65         VMSTATE_UINT32(cr, IMXGPTState),
  66         VMSTATE_UINT32(pr, IMXGPTState),
  67         VMSTATE_UINT32(sr, IMXGPTState),
  68         VMSTATE_UINT32(ir, IMXGPTState),
  69         VMSTATE_UINT32(ocr1, IMXGPTState),
  70         VMSTATE_UINT32(ocr2, IMXGPTState),
  71         VMSTATE_UINT32(ocr3, IMXGPTState),
  72         VMSTATE_UINT32(icr1, IMXGPTState),
  73         VMSTATE_UINT32(icr2, IMXGPTState),
  74         VMSTATE_UINT32(cnt, IMXGPTState),
  75         VMSTATE_UINT32(next_timeout, IMXGPTState),
  76         VMSTATE_UINT32(next_int, IMXGPTState),
  77         VMSTATE_UINT32(freq, IMXGPTState),
  78         VMSTATE_PTIMER(timer, IMXGPTState),
  79         VMSTATE_END_OF_LIST()
  80     }
  81 };
  82
  83 static const IMXClk imx_gpt_clocks[] = {
  84     NOCLK,    /* 000 No clock source */
  85     CLK_IPG,  /* 001 ipg_clk, 532MHz*/
  86     CLK_IPG,  /* 010 ipg_clk_highfreq */
  87     NOCLK,    /* 011 not defined */
  88     CLK_32k,  /* 100 ipg_clk_32k */
  89     NOCLK,    /* 101 not defined */
  90     NOCLK,    /* 110 not defined */
  91     NOCLK,    /* 111 not defined */
  92 };
  93
  94 static void imx_gpt_set_freq(IMXGPTState *s)
  95 {
  96     uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
  97
  98     s->freq = imx_ccm_get_clock_frequency(s->ccm,
  99                                 imx_gpt_clocks[clksrc]) / (1 + s->pr);
 100
 101     DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
 102
 103     if (s->freq) {
 104         ptimer_set_freq(s->timer, s->freq);
 105     }
 106 }
 107
 108 static void imx_gpt_update_int(IMXGPTState *s)
 109 {
 110     if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
 111         qemu_irq_raise(s->irq);
 112     } else {
 113         qemu_irq_lower(s->irq);
 114     }
 115 }
 116
 117 static uint32_t imx_gpt_update_count(IMXGPTState *s)
 118 {
 119     s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
 120
 121     return s->cnt;
 122 }
 123
 124 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
 125                                           uint32_t timeout)
 126 {
 127     if ((count < reg) && (timeout > reg)) {
 128         timeout = reg;
 129     }
 130
 131     return timeout;
 132 }
 133
 134 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
 135 {
 136     uint32_t timeout = GPT_TIMER_MAX;
 137     uint32_t count = 0;
 138     long long limit;
 139
 140     if (!(s->cr & GPT_CR_EN)) {
 141         /* if not enabled just return */
 142         return;
 143     }
 144
 145     if (event) {
 146         /* This is a timer event  */
 147
 148         if ((s->cr & GPT_CR_FRR)  && (s->next_timeout != GPT_TIMER_MAX)) {
 149             /*
 150              * if we are in free running mode and we have not reached
 151              * the GPT_TIMER_MAX limit, then update the count
 152              */
 153             count = imx_gpt_update_count(s);
 154         }
 155     } else {
 156         /* not a timer event, then just update the count */
 157
 158         count = imx_gpt_update_count(s);
 159     }
 160
 161     /* now, find the next timeout related to count */
 162
 163     if (s->ir & GPT_IR_OF1IE) {
 164         timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
 165     }
 166     if (s->ir & GPT_IR_OF2IE) {
 167         timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
 168     }
 169     if (s->ir & GPT_IR_OF3IE) {
 170         timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
 171     }
 172
 173     /* find the next set of interrupts to raise for next timer event */
 174
 175     s->next_int = 0;
 176     if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
 177         s->next_int |= GPT_SR_OF1;
 178     }
 179     if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
 180         s->next_int |= GPT_SR_OF2;
 181     }
 182     if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
 183         s->next_int |= GPT_SR_OF3;
 184     }
 185     if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
 186         s->next_int |= GPT_SR_ROV;
 187     }
 188
 189     /* the new range to count down from */
 190     limit = timeout - imx_gpt_update_count(s);
 191
 192     if (limit < 0) {
 193         /*
 194          * if we reach here, then QEMU is running too slow and we pass the
 195          * timeout limit while computing it. Let's deliver the interrupt
 196          * and compute a new limit.
 197          */
 198         s->sr |= s->next_int;
 199
 200         imx_gpt_compute_next_timeout(s, event);
 201
 202         imx_gpt_update_int(s);
 203     } else {
 204         /* New timeout value */
 205         s->next_timeout = timeout;
 206
 207         /* reset the limit to the computed range */
 208         ptimer_set_limit(s->timer, limit, 1);
 209     }
 210 }
 211
 212 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
 213 {
 214     IMXGPTState *s = IMX_GPT(opaque);
 215     uint32_t reg_value = 0;
 216
 217     switch (offset >> 2) {
 218     case 0: /* Control Register */
 219         reg_value = s->cr;
 220         break;
 221
 222     case 1: /* prescaler */
 223         reg_value = s->pr;
 224         break;
 225
 226     case 2: /* Status Register */
 227         reg_value = s->sr;
 228         break;
 229
 230     case 3: /* Interrupt Register */
 231         reg_value = s->ir;
 232         break;
 233
 234     case 4: /* Output Compare Register 1 */
 235         reg_value = s->ocr1;
 236         break;
 237
 238     case 5: /* Output Compare Register 2 */
 239         reg_value = s->ocr2;
 240         break;
 241
 242     case 6: /* Output Compare Register 3 */
 243         reg_value = s->ocr3;
 244         break;
 245
 246     case 7: /* input Capture Register 1 */
 247         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
 248                       TYPE_IMX_GPT, __func__);
 249         reg_value = s->icr1;
 250         break;
 251
 252     case 8: /* input Capture Register 2 */
 253         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
 254                       TYPE_IMX_GPT, __func__);
 255         reg_value = s->icr2;
 256         break;
 257
 258     case 9: /* cnt */
 259         imx_gpt_update_count(s);
 260         reg_value = s->cnt;
 261         break;
 262
 263     default:
 264         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 265                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
 266         break;
 267     }
 268
 269     DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
 270
 271     return reg_value;
 272 }
 273
 274 static void imx_gpt_reset(DeviceState *dev)
 275 {
 276     IMXGPTState *s = IMX_GPT(dev);
 277
 278     /* stop timer */
 279     ptimer_stop(s->timer);
 280
 281     /*
 282      * Soft reset doesn't touch some bits; hard reset clears them
 283      */
 284     s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
 285                GPT_CR_WAITEN|GPT_CR_DBGEN);
 286     s->sr = 0;
 287     s->pr = 0;
 288     s->ir = 0;
 289     s->cnt = 0;
 290     s->ocr1 = GPT_TIMER_MAX;
 291     s->ocr2 = GPT_TIMER_MAX;
 292     s->ocr3 = GPT_TIMER_MAX;
 293     s->icr1 = 0;
 294     s->icr2 = 0;
 295
 296     s->next_timeout = GPT_TIMER_MAX;
 297     s->next_int = 0;
 298
 299     /* compute new freq */
 300     imx_gpt_set_freq(s);
 301
 302     /* reset the limit to GPT_TIMER_MAX */
 303     ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 304
 305     /* if the timer is still enabled, restart it */
 306     if (s->freq && (s->cr & GPT_CR_EN)) {
 307         ptimer_run(s->timer, 1);
 308     }
 309 }
 310
 311 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
 312                           unsigned size)
 313 {
 314     IMXGPTState *s = IMX_GPT(opaque);
 315     uint32_t oldreg;
 316
 317     DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
 318             (uint32_t)value);
 319
 320     switch (offset >> 2) {
 321     case 0:
 322         oldreg = s->cr;
 323         s->cr = value & ~0x7c14;
 324         if (s->cr & GPT_CR_SWR) { /* force reset */
 325             /* handle the reset */
 326             imx_gpt_reset(DEVICE(s));
 327         } else {
 328             /* set our freq, as the source might have changed */
 329             imx_gpt_set_freq(s);
 330
 331             if ((oldreg ^ s->cr) & GPT_CR_EN) {
 332                 if (s->cr & GPT_CR_EN) {
 333                     if (s->cr & GPT_CR_ENMOD) {
 334                         s->next_timeout = GPT_TIMER_MAX;
 335                         ptimer_set_count(s->timer, GPT_TIMER_MAX);
 336                         imx_gpt_compute_next_timeout(s, false);
 337                     }
 338                     ptimer_run(s->timer, 1);
 339                 } else {
 340                     /* stop timer */
 341                     ptimer_stop(s->timer);
 342                 }
 343             }
 344         }
 345         break;
 346
 347     case 1: /* Prescaler */
 348         s->pr = value & 0xfff;
 349         imx_gpt_set_freq(s);
 350         break;
 351
 352     case 2: /* SR */
 353         s->sr &= ~(value & 0x3f);
 354         imx_gpt_update_int(s);
 355         break;
 356
 357     case 3: /* IR -- interrupt register */
 358         s->ir = value & 0x3f;
 359         imx_gpt_update_int(s);
 360
 361         imx_gpt_compute_next_timeout(s, false);
 362
 363         break;
 364
 365     case 4: /* OCR1 -- output compare register */
 366         s->ocr1 = value;
 367
 368         /* In non-freerun mode, reset count when this register is written */
 369         if (!(s->cr & GPT_CR_FRR)) {
 370             s->next_timeout = GPT_TIMER_MAX;
 371             ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 372         }
 373
 374         /* compute the new timeout */
 375         imx_gpt_compute_next_timeout(s, false);
 376
 377         break;
 378
 379     case 5: /* OCR2 -- output compare register */
 380         s->ocr2 = value;
 381
 382         /* compute the new timeout */
 383         imx_gpt_compute_next_timeout(s, false);
 384
 385         break;
 386
 387     case 6: /* OCR3 -- output compare register */
 388         s->ocr3 = value;
 389
 390         /* compute the new timeout */
 391         imx_gpt_compute_next_timeout(s, false);
 392
 393         break;
 394
 395     default:
 396         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 397                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
 398         break;
 399     }
 400 }
 401
 402 static void imx_gpt_timeout(void *opaque)
 403 {
 404     IMXGPTState *s = IMX_GPT(opaque);
 405
 406     DPRINTF("\n");
 407
 408     s->sr |= s->next_int;
 409     s->next_int = 0;
 410
 411     imx_gpt_compute_next_timeout(s, true);
 412
 413     imx_gpt_update_int(s);
 414
 415     if (s->freq && (s->cr & GPT_CR_EN)) {
 416         ptimer_run(s->timer, 1);
 417     }
 418 }
 419
 420 static const MemoryRegionOps imx_gpt_ops = {
 421     .read = imx_gpt_read,
 422     .write = imx_gpt_write,
 423     .endianness = DEVICE_NATIVE_ENDIAN,
 424 };
 425
 426
 427 static void imx_gpt_realize(DeviceState *dev, Error **errp)
 428 {
 429     IMXGPTState *s = IMX_GPT(dev);
 430     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 431     QEMUBH *bh;
 432
 433     sysbus_init_irq(sbd, &s->irq);
 434     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
 435                           0x00001000);
 436     sysbus_init_mmio(sbd, &s->iomem);
 437
 438     bh = qemu_bh_new(imx_gpt_timeout, s);
 439     s->timer = ptimer_init(bh);
 440 }
 441
 442 static void imx_gpt_class_init(ObjectClass *klass, void *data)
 443 {
 444     DeviceClass *dc = DEVICE_CLASS(klass);
 445
 446     dc->realize = imx_gpt_realize;
 447     dc->reset = imx_gpt_reset;
 448     dc->vmsd = &vmstate_imx_timer_gpt;
 449     dc->desc = "i.MX general timer";
 450 }
 451
 452 static const TypeInfo imx_gpt_info = {
 453     .name = TYPE_IMX_GPT,
 454     .parent = TYPE_SYS_BUS_DEVICE,
 455     .instance_size = sizeof(IMXGPTState),
 456     .class_init = imx_gpt_class_init,
 457 };
 458
 459 static void imx_gpt_register_types(void)
 460 {
 461     type_register_static(&imx_gpt_info);
 462 }
 463
 464 type_init(imx_gpt_register_types)