hw/pci-host/prep.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/pci/pci_bus.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "hw/i386/pc.h"
  32 #include "hw/loader.h"
  33 #include "exec/address-spaces.h"
  34 #include "elf.h"
  35
  36 #define TYPE_RAVEN_PCI_DEVICE "raven"
  37 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  38
  39 #define RAVEN_PCI_DEVICE(obj) \
  40     OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
  41
  42 typedef struct RavenPCIState {
  43     PCIDevice dev;
  44
  45     uint32_t elf_machine;
  46     char *bios_name;
  47     MemoryRegion bios;
  48 } RavenPCIState;
  49
  50 #define RAVEN_PCI_HOST_BRIDGE(obj) \
  51     OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
  52
  53 typedef struct PRePPCIState {
  54     PCIHostState parent_obj;
  55
  56     qemu_irq irq[PCI_NUM_PINS];
  57     PCIBus pci_bus;
  58     AddressSpace pci_io_as;
  59     MemoryRegion pci_io;
  60     MemoryRegion pci_io_non_contiguous;
  61     MemoryRegion pci_memory;
  62     MemoryRegion pci_intack;
  63     MemoryRegion bm;
  64     MemoryRegion bm_ram_alias;
  65     MemoryRegion bm_pci_memory_alias;
  66     AddressSpace bm_as;
  67     RavenPCIState pci_dev;
  68
  69     int contiguous_map;
  70 } PREPPCIState;
  71
  72 #define BIOS_SIZE (1024 * 1024)
  73
  74 static inline uint32_t raven_pci_io_config(hwaddr addr)
  75 {
  76     int i;
  77
  78     for (i = 0; i < 11; i++) {
  79         if ((addr & (1 << (11 + i))) != 0) {
  80             break;
  81         }
  82     }
  83     return (addr & 0x7ff) |  (i << 11);
  84 }
  85
  86 static void raven_pci_io_write(void *opaque, hwaddr addr,
  87                                uint64_t val, unsigned int size)
  88 {
  89     PREPPCIState *s = opaque;
  90     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  91     pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
  92 }
  93
  94 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
  95                                   unsigned int size)
  96 {
  97     PREPPCIState *s = opaque;
  98     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  99     return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
 100 }
 101
 102 static const MemoryRegionOps raven_pci_io_ops = {
 103     .read = raven_pci_io_read,
 104     .write = raven_pci_io_write,
 105     .endianness = DEVICE_LITTLE_ENDIAN,
 106 };
 107
 108 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
 109                                   unsigned int size)
 110 {
 111     return pic_read_irq(isa_pic);
 112 }
 113
 114 static const MemoryRegionOps raven_intack_ops = {
 115     .read = raven_intack_read,
 116     .valid = {
 117         .max_access_size = 1,
 118     },
 119 };
 120
 121 static inline hwaddr raven_io_address(PREPPCIState *s,
 122                                       hwaddr addr)
 123 {
 124     if (s->contiguous_map == 0) {
 125         /* 64 KB contiguous space for IOs */
 126         addr &= 0xFFFF;
 127     } else {
 128         /* 8 MB non-contiguous space for IOs */
 129         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 130     }
 131
 132     /* FIXME: handle endianness switch */
 133
 134     return addr;
 135 }
 136
 137 static uint64_t raven_io_read(void *opaque, hwaddr addr,
 138                               unsigned int size)
 139 {
 140     PREPPCIState *s = opaque;
 141     uint8_t buf[4];
 142
 143     addr = raven_io_address(s, addr);
 144     address_space_read(&s->pci_io_as, addr + 0x80000000,
 145                        MEMTXATTRS_UNSPECIFIED, buf, size);
 146
 147     if (size == 1) {
 148         return buf[0];
 149     } else if (size == 2) {
 150         return lduw_le_p(buf);
 151     } else if (size == 4) {
 152         return ldl_le_p(buf);
 153     } else {
 154         g_assert_not_reached();
 155     }
 156 }
 157
 158 static void raven_io_write(void *opaque, hwaddr addr,
 159                            uint64_t val, unsigned int size)
 160 {
 161     PREPPCIState *s = opaque;
 162     uint8_t buf[4];
 163
 164     addr = raven_io_address(s, addr);
 165
 166     if (size == 1) {
 167         buf[0] = val;
 168     } else if (size == 2) {
 169         stw_le_p(buf, val);
 170     } else if (size == 4) {
 171         stl_le_p(buf, val);
 172     } else {
 173         g_assert_not_reached();
 174     }
 175
 176     address_space_write(&s->pci_io_as, addr + 0x80000000,
 177                         MEMTXATTRS_UNSPECIFIED, buf, size);
 178 }
 179
 180 static const MemoryRegionOps raven_io_ops = {
 181     .read = raven_io_read,
 182     .write = raven_io_write,
 183     .endianness = DEVICE_LITTLE_ENDIAN,
 184     .impl.max_access_size = 4,
 185     .valid.unaligned = true,
 186 };
 187
 188 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
 189 {
 190     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 191 }
 192
 193 static void raven_set_irq(void *opaque, int irq_num, int level)
 194 {
 195     qemu_irq *pic = opaque;
 196
 197     qemu_set_irq(pic[irq_num] , level);
 198 }
 199
 200 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
 201                                              int devfn)
 202 {
 203     PREPPCIState *s = opaque;
 204
 205     return &s->bm_as;
 206 }
 207
 208 static void raven_change_gpio(void *opaque, int n, int level)
 209 {
 210     PREPPCIState *s = opaque;
 211
 212     s->contiguous_map = level;
 213 }
 214
 215 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 216 {
 217     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 218     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 219     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 220     MemoryRegion *address_space_mem = get_system_memory();
 221     int i;
 222
 223     for (i = 0; i < PCI_NUM_PINS; i++) {
 224         sysbus_init_irq(dev, &s->irq[i]);
 225     }
 226
 227     qdev_init_gpio_in(d, raven_change_gpio, 1);
 228
 229     pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
 230                  PCI_NUM_PINS);
 231
 232     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
 233                           "pci-conf-idx", 4);
 234     memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
 235
 236     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
 237                           "pci-conf-data", 4);
 238     memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
 239
 240     memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
 241                           "pciio", 0x00400000);
 242     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 243
 244     memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
 245                           "pci-intack", 1);
 246     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
 247
 248     /* TODO Remove once realize propagates to child devices. */
 249     object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
 250 }
 251
 252 static void raven_pcihost_initfn(Object *obj)
 253 {
 254     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 255     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 256     MemoryRegion *address_space_mem = get_system_memory();
 257     DeviceState *pci_dev;
 258
 259     memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
 260     memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
 261                           "pci-io-non-contiguous", 0x00800000);
 262     memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
 263     address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
 264
 265     /* CPU address space */
 266     memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
 267     memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
 268                                         &s->pci_io_non_contiguous, 1);
 269     memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
 270     pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
 271                         &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
 272
 273     /* Bus master address space */
 274     memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
 275     memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
 276                              &s->pci_memory, 0,
 277                              memory_region_size(&s->pci_memory));
 278     memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
 279                              get_system_memory(), 0, 0x80000000);
 280     memory_region_add_subregion(&s->bm, 0         , &s->bm_pci_memory_alias);
 281     memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
 282     address_space_init(&s->bm_as, &s->bm, "raven-bm");
 283     pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
 284
 285     h->bus = &s->pci_bus;
 286
 287     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
 288     pci_dev = DEVICE(&s->pci_dev);
 289     qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
 290     object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
 291                             NULL);
 292     qdev_prop_set_bit(pci_dev, "multifunction", false);
 293 }
 294
 295 static void raven_realize(PCIDevice *d, Error **errp)
 296 {
 297     RavenPCIState *s = RAVEN_PCI_DEVICE(d);
 298     char *filename;
 299     int bios_size = -1;
 300
 301     d->config[0x0C] = 0x08; // cache_line_size
 302     d->config[0x0D] = 0x10; // latency_timer
 303     d->config[0x34] = 0x00; // capabilities_pointer
 304
 305     memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
 306                            &error_fatal);
 307     memory_region_set_readonly(&s->bios, true);
 308     memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
 309                                 &s->bios);
 310     vmstate_register_ram_global(&s->bios);
 311     if (s->bios_name) {
 312         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
 313         if (filename) {
 314             if (s->elf_machine != EM_NONE) {
 315                 bios_size = load_elf(filename, NULL, NULL, NULL,
 316                                      NULL, NULL, 1, s->elf_machine, 0);
 317             }
 318             if (bios_size < 0) {
 319                 bios_size = get_image_size(filename);
 320                 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 321                     hwaddr bios_addr;
 322                     bios_size = (bios_size + 0xfff) & ~0xfff;
 323                     bios_addr = (uint32_t)(-BIOS_SIZE);
 324                     bios_size = load_image_targphys(filename, bios_addr,
 325                                                     bios_size);
 326                 }
 327             }
 328         }
 329         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 330             /* FIXME should error_setg() */
 331             hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
 332         }
 333         g_free(filename);
 334     }
 335 }
 336
 337 static const VMStateDescription vmstate_raven = {
 338     .name = "raven",
 339     .version_id = 0,
 340     .minimum_version_id = 0,
 341     .fields = (VMStateField[]) {
 342         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 343         VMSTATE_END_OF_LIST()
 344     },
 345 };
 346
 347 static void raven_class_init(ObjectClass *klass, void *data)
 348 {
 349     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 350     DeviceClass *dc = DEVICE_CLASS(klass);
 351
 352     k->realize = raven_realize;
 353     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 354     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 355     k->revision = 0x00;
 356     k->class_id = PCI_CLASS_BRIDGE_HOST;
 357     dc->desc = "PReP Host Bridge - Motorola Raven";
 358     dc->vmsd = &vmstate_raven;
 359     /*
 360      * Reason: PCI-facing part of the host bridge, not usable without
 361      * the host-facing part, which can't be device_add'ed, yet.
 362      * Reason: realize() method uses hw_error().
 363      */
 364     dc->cannot_instantiate_with_device_add_yet = true;
 365 }
 366
 367 static const TypeInfo raven_info = {
 368     .name = TYPE_RAVEN_PCI_DEVICE,
 369     .parent = TYPE_PCI_DEVICE,
 370     .instance_size = sizeof(RavenPCIState),
 371     .class_init = raven_class_init,
 372 };
 373
 374 static Property raven_pcihost_properties[] = {
 375     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
 376                        EM_NONE),
 377     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
 378     DEFINE_PROP_END_OF_LIST()
 379 };
 380
 381 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 382 {
 383     DeviceClass *dc = DEVICE_CLASS(klass);
 384
 385     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 386     dc->realize = raven_pcihost_realizefn;
 387     dc->props = raven_pcihost_properties;
 388     dc->fw_name = "pci";
 389 }
 390
 391 static const TypeInfo raven_pcihost_info = {
 392     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 393     .parent = TYPE_PCI_HOST_BRIDGE,
 394     .instance_size = sizeof(PREPPCIState),
 395     .instance_init = raven_pcihost_initfn,
 396     .class_init = raven_pcihost_class_init,
 397 };
 398
 399 static void raven_register_types(void)
 400 {
 401     type_register_static(&raven_pcihost_info);
 402     type_register_static(&raven_info);
 403 }
 404
 405 type_init(raven_register_types)