hw/cpu/realview_mpcore.c

   1 /*
   2  * RealView ARM11MPCore internal peripheral emulation
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  * Written by Paul Brook and Andreas Färber
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "hw/cpu/arm11mpcore.h"
  13 #include "hw/intc/realview_gic.h"
  14
  15 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
  16 #define REALVIEW_MPCORE_RIRQ(obj) \
  17     OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
  18
  19 /* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
  20    controllers.  The output of these, plus some of the raw input lines
  21    are fed into a single SMP-aware interrupt controller on the CPU.  */
  22 typedef struct {
  23     SysBusDevice parent_obj;
  24
  25     qemu_irq cpuic[32];
  26     qemu_irq rvic[4][64];
  27     uint32_t num_cpu;
  28
  29     ARM11MPCorePriveState priv;
  30     RealViewGICState gic[4];
  31 } mpcore_rirq_state;
  32
  33 /* Map baseboard IRQs onto CPU IRQ lines.  */
  34 static const int mpcore_irq_map[32] = {
  35     -1, -1, -1, -1,  1,  2, -1, -1,
  36     -1, -1,  6, -1,  4,  5, -1, -1,
  37     -1, 14, 15,  0,  7,  8, -1, -1,
  38     -1, -1, -1, -1,  9,  3, -1, -1,
  39 };
  40
  41 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
  42 {
  43     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
  44     int i;
  45
  46     for (i = 0; i < 4; i++) {
  47         qemu_set_irq(s->rvic[i][irq], level);
  48     }
  49     if (irq < 32) {
  50         irq = mpcore_irq_map[irq];
  51         if (irq >= 0) {
  52             qemu_set_irq(s->cpuic[irq], level);
  53         }
  54     }
  55 }
  56
  57 static void realview_mpcore_realize(DeviceState *dev, Error **errp)
  58 {
  59     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  60     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
  61     DeviceState *priv = DEVICE(&s->priv);
  62     DeviceState *gic;
  63     SysBusDevice *gicbusdev;
  64     Error *err = NULL;
  65     int n;
  66     int i;
  67
  68     qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
  69     object_property_set_bool(OBJECT(&s->priv), true, "realized", &err);
  70     if (err != NULL) {
  71         error_propagate(errp, err);
  72         return;
  73     }
  74     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv));
  75     for (i = 0; i < 32; i++) {
  76         s->cpuic[i] = qdev_get_gpio_in(priv, i);
  77     }
  78     /* ??? IRQ routing is hardcoded to "normal" mode.  */
  79     for (n = 0; n < 4; n++) {
  80         object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err);
  81         if (err != NULL) {
  82             error_propagate(errp, err);
  83             return;
  84         }
  85         gic = DEVICE(&s->gic[n]);
  86         gicbusdev = SYS_BUS_DEVICE(&s->gic[n]);
  87         sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000);
  88         sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]);
  89         for (i = 0; i < 64; i++) {
  90             s->rvic[n][i] = qdev_get_gpio_in(gic, i);
  91         }
  92     }
  93     qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
  94 }
  95
  96 static void mpcore_rirq_init(Object *obj)
  97 {
  98     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  99     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
 100     SysBusDevice *privbusdev;
 101     int i;
 102
 103     object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV);
 104     qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default());
 105     privbusdev = SYS_BUS_DEVICE(&s->priv);
 106     sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
 107
 108     for (i = 0; i < 4; i++) {
 109         object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_GIC);
 110         qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default());
 111     }
 112 }
 113
 114 static Property mpcore_rirq_properties[] = {
 115     DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
 116     DEFINE_PROP_END_OF_LIST(),
 117 };
 118
 119 static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
 120 {
 121     DeviceClass *dc = DEVICE_CLASS(klass);
 122
 123     dc->realize = realview_mpcore_realize;
 124     dc->props = mpcore_rirq_properties;
 125 }
 126
 127 static const TypeInfo mpcore_rirq_info = {
 128     .name          = TYPE_REALVIEW_MPCORE_RIRQ,
 129     .parent        = TYPE_SYS_BUS_DEVICE,
 130     .instance_size = sizeof(mpcore_rirq_state),
 131     .instance_init = mpcore_rirq_init,
 132     .class_init    = mpcore_rirq_class_init,
 133 };
 134
 135 static void realview_mpcore_register_types(void)
 136 {
 137     type_register_static(&mpcore_rirq_info);
 138 }
 139
 140 type_init(realview_mpcore_register_types)