2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
16 #include "hw/sysbus.h"
17 #include "migration/vmstate.h"
18 #include "qemu/timer.h"
19 #include "hw/intc/armv7m_nvic.h"
21 #include "hw/qdev-properties.h"
22 #include "sysemu/runstate.h"
23 #include "target/arm/cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/memop.h"
27 #include "qemu/module.h"
30 /* IRQ number counting:
32 * the num-irq property counts the number of external IRQ lines
34 * NVICState::num_irq counts the total number of exceptions
35 * (external IRQs, the 15 internal exceptions including reset,
36 * and one for the unused exception number 0).
38 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
40 * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
42 * Iterating through all exceptions should typically be done with
43 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
45 * The external qemu_irq lines are the NVIC's external IRQ lines,
46 * so line 0 is exception 16.
48 * In the terminology of the architecture manual, "interrupts" are
49 * a subcategory of exception referring to the external interrupts
50 * (which are exception numbers NVIC_FIRST_IRQ and upward).
51 * For historical reasons QEMU tends to use "interrupt" and
52 * "exception" more or less interchangeably.
54 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
55 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
57 /* Effective running priority of the CPU when no exception is active
58 * (higher than the highest possible priority value)
60 #define NVIC_NOEXC_PRIO 0x100
61 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
62 #define NVIC_NS_PRIO_LIMIT 0x80
64 static const uint8_t nvic_id
[] = {
65 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
68 static void signal_sysresetreq(NVICState
*s
)
70 if (qemu_irq_is_connected(s
->sysresetreq
)) {
71 qemu_irq_pulse(s
->sysresetreq
);
74 * Default behaviour if the SoC doesn't need to wire up
75 * SYSRESETREQ (eg to a system reset controller of some kind):
76 * perform a system reset via the usual QEMU API.
78 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
82 static int nvic_pending_prio(NVICState
*s
)
84 /* return the group priority of the current pending interrupt,
85 * or NVIC_NOEXC_PRIO if no interrupt is pending
87 return s
->vectpending_prio
;
90 /* Return the value of the ISCR RETTOBASE bit:
91 * 1 if there is exactly one active exception
92 * 0 if there is more than one active exception
93 * UNKNOWN if there are no active exceptions (we choose 1,
94 * which matches the choice Cortex-M3 is documented as making).
96 * NB: some versions of the documentation talk about this
97 * counting "active exceptions other than the one shown by IPSR";
98 * this is only different in the obscure corner case where guest
99 * code has manually deactivated an exception and is about
100 * to fail an exception-return integrity check. The definition
101 * above is the one from the v8M ARM ARM and is also in line
102 * with the behaviour documented for the Cortex-M3.
104 static bool nvic_rettobase(NVICState
*s
)
107 bool check_sec
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
109 for (irq
= ARMV7M_EXCP_RESET
; irq
< s
->num_irq
; irq
++) {
110 if (s
->vectors
[irq
].active
||
111 (check_sec
&& irq
< NVIC_INTERNAL_VECTORS
&&
112 s
->sec_vectors
[irq
].active
)) {
123 /* Return the value of the ISCR ISRPENDING bit:
124 * 1 if an external interrupt is pending
125 * 0 if no external interrupt is pending
127 static bool nvic_isrpending(NVICState
*s
)
131 /* We can shortcut if the highest priority pending interrupt
132 * happens to be external or if there is nothing pending.
134 if (s
->vectpending
> NVIC_FIRST_IRQ
) {
137 if (s
->vectpending
== 0) {
141 for (irq
= NVIC_FIRST_IRQ
; irq
< s
->num_irq
; irq
++) {
142 if (s
->vectors
[irq
].pending
) {
149 static bool exc_is_banked(int exc
)
151 /* Return true if this is one of the limited set of exceptions which
152 * are banked (and thus have state in sec_vectors[])
154 return exc
== ARMV7M_EXCP_HARD
||
155 exc
== ARMV7M_EXCP_MEM
||
156 exc
== ARMV7M_EXCP_USAGE
||
157 exc
== ARMV7M_EXCP_SVC
||
158 exc
== ARMV7M_EXCP_PENDSV
||
159 exc
== ARMV7M_EXCP_SYSTICK
;
162 /* Return a mask word which clears the subpriority bits from
163 * a priority value for an M-profile exception, leaving only
164 * the group priority.
166 static inline uint32_t nvic_gprio_mask(NVICState
*s
, bool secure
)
168 return ~0U << (s
->prigroup
[secure
] + 1);
171 static bool exc_targets_secure(NVICState
*s
, int exc
)
173 /* Return true if this non-banked exception targets Secure state. */
174 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
178 if (exc
>= NVIC_FIRST_IRQ
) {
179 return !s
->itns
[exc
];
182 /* Function shouldn't be called for banked exceptions. */
183 assert(!exc_is_banked(exc
));
186 case ARMV7M_EXCP_NMI
:
187 case ARMV7M_EXCP_BUS
:
188 return !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
189 case ARMV7M_EXCP_SECURE
:
191 case ARMV7M_EXCP_DEBUG
:
192 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
195 /* reset, and reserved (unused) low exception numbers.
196 * We'll get called by code that loops through all the exception
197 * numbers, but it doesn't matter what we return here as these
198 * non-existent exceptions will never be pended or active.
204 static int exc_group_prio(NVICState
*s
, int rawprio
, bool targets_secure
)
206 /* Return the group priority for this exception, given its raw
207 * (group-and-subgroup) priority value and whether it is targeting
208 * secure state or not.
213 rawprio
&= nvic_gprio_mask(s
, targets_secure
);
214 /* AIRCR.PRIS causes us to squash all NS priorities into the
215 * lower half of the total range
217 if (!targets_secure
&&
218 (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
)) {
219 rawprio
= (rawprio
>> 1) + NVIC_NS_PRIO_LIMIT
;
224 /* Recompute vectpending and exception_prio for a CPU which implements
225 * the Security extension
227 static void nvic_recompute_state_secure(NVICState
*s
)
230 int pend_prio
= NVIC_NOEXC_PRIO
;
231 int active_prio
= NVIC_NOEXC_PRIO
;
233 bool pending_is_s_banked
= false;
234 int pend_subprio
= 0;
236 /* R_CQRV: precedence is by:
237 * - lowest group priority; if both the same then
238 * - lowest subpriority; if both the same then
239 * - lowest exception number; if both the same (ie banked) then
240 * - secure exception takes precedence
241 * Compare pseudocode RawExecutionPriority.
242 * Annoyingly, now we have two prigroup values (for S and NS)
243 * we can't do the loop comparison on raw priority values.
245 for (i
= 1; i
< s
->num_irq
; i
++) {
246 for (bank
= M_REG_S
; bank
>= M_REG_NS
; bank
--) {
251 if (bank
== M_REG_S
) {
252 if (!exc_is_banked(i
)) {
255 vec
= &s
->sec_vectors
[i
];
256 targets_secure
= true;
258 vec
= &s
->vectors
[i
];
259 targets_secure
= !exc_is_banked(i
) && exc_targets_secure(s
, i
);
262 prio
= exc_group_prio(s
, vec
->prio
, targets_secure
);
263 subprio
= vec
->prio
& ~nvic_gprio_mask(s
, targets_secure
);
264 if (vec
->enabled
&& vec
->pending
&&
265 ((prio
< pend_prio
) ||
266 (prio
== pend_prio
&& prio
>= 0 && subprio
< pend_subprio
))) {
268 pend_subprio
= subprio
;
270 pending_is_s_banked
= (bank
== M_REG_S
);
272 if (vec
->active
&& prio
< active_prio
) {
278 s
->vectpending_is_s_banked
= pending_is_s_banked
;
279 s
->vectpending
= pend_irq
;
280 s
->vectpending_prio
= pend_prio
;
281 s
->exception_prio
= active_prio
;
283 trace_nvic_recompute_state_secure(s
->vectpending
,
284 s
->vectpending_is_s_banked
,
289 /* Recompute vectpending and exception_prio */
290 static void nvic_recompute_state(NVICState
*s
)
293 int pend_prio
= NVIC_NOEXC_PRIO
;
294 int active_prio
= NVIC_NOEXC_PRIO
;
297 /* In theory we could write one function that handled both
298 * the "security extension present" and "not present"; however
299 * the security related changes significantly complicate the
300 * recomputation just by themselves and mixing both cases together
301 * would be even worse, so we retain a separate non-secure-only
302 * version for CPUs which don't implement the security extension.
304 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
305 nvic_recompute_state_secure(s
);
309 for (i
= 1; i
< s
->num_irq
; i
++) {
310 VecInfo
*vec
= &s
->vectors
[i
];
312 if (vec
->enabled
&& vec
->pending
&& vec
->prio
< pend_prio
) {
313 pend_prio
= vec
->prio
;
316 if (vec
->active
&& vec
->prio
< active_prio
) {
317 active_prio
= vec
->prio
;
321 if (active_prio
> 0) {
322 active_prio
&= nvic_gprio_mask(s
, false);
326 pend_prio
&= nvic_gprio_mask(s
, false);
329 s
->vectpending
= pend_irq
;
330 s
->vectpending_prio
= pend_prio
;
331 s
->exception_prio
= active_prio
;
333 trace_nvic_recompute_state(s
->vectpending
,
338 /* Return the current execution priority of the CPU
339 * (equivalent to the pseudocode ExecutionPriority function).
340 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
342 static inline int nvic_exec_prio(NVICState
*s
)
344 CPUARMState
*env
= &s
->cpu
->env
;
345 int running
= NVIC_NOEXC_PRIO
;
347 if (env
->v7m
.basepri
[M_REG_NS
] > 0) {
348 running
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_NS
], M_REG_NS
);
351 if (env
->v7m
.basepri
[M_REG_S
] > 0) {
352 int basepri
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_S
], M_REG_S
);
353 if (running
> basepri
) {
358 if (env
->v7m
.primask
[M_REG_NS
]) {
359 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
360 if (running
> NVIC_NS_PRIO_LIMIT
) {
361 running
= NVIC_NS_PRIO_LIMIT
;
368 if (env
->v7m
.primask
[M_REG_S
]) {
372 if (env
->v7m
.faultmask
[M_REG_NS
]) {
373 if (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
376 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
377 if (running
> NVIC_NS_PRIO_LIMIT
) {
378 running
= NVIC_NS_PRIO_LIMIT
;
386 if (env
->v7m
.faultmask
[M_REG_S
]) {
387 running
= (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) ? -3 : -1;
390 /* consider priority of active handler */
391 return MIN(running
, s
->exception_prio
);
394 bool armv7m_nvic_neg_prio_requested(void *opaque
, bool secure
)
396 /* Return true if the requested execution priority is negative
397 * for the specified security state, ie that security state
398 * has an active NMI or HardFault or has set its FAULTMASK.
399 * Note that this is not the same as whether the execution
400 * priority is actually negative (for instance AIRCR.PRIS may
401 * mean we don't allow FAULTMASK_NS to actually make the execution
402 * priority negative). Compare pseudocode IsReqExcPriNeg().
404 NVICState
*s
= opaque
;
406 if (s
->cpu
->env
.v7m
.faultmask
[secure
]) {
410 if (secure
? s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
:
411 s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
415 if (s
->vectors
[ARMV7M_EXCP_NMI
].active
&&
416 exc_targets_secure(s
, ARMV7M_EXCP_NMI
) == secure
) {
423 bool armv7m_nvic_can_take_pending_exception(void *opaque
)
425 NVICState
*s
= opaque
;
427 return nvic_exec_prio(s
) > nvic_pending_prio(s
);
430 int armv7m_nvic_raw_execution_priority(void *opaque
)
432 NVICState
*s
= opaque
;
434 return s
->exception_prio
;
437 /* caller must call nvic_irq_update() after this.
438 * secure indicates the bank to use for banked exceptions (we assert if
439 * we are passed secure=true for a non-banked exception).
441 static void set_prio(NVICState
*s
, unsigned irq
, bool secure
, uint8_t prio
)
443 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
444 assert(irq
< s
->num_irq
);
446 prio
&= MAKE_64BIT_MASK(8 - s
->num_prio_bits
, s
->num_prio_bits
);
449 assert(exc_is_banked(irq
));
450 s
->sec_vectors
[irq
].prio
= prio
;
452 s
->vectors
[irq
].prio
= prio
;
455 trace_nvic_set_prio(irq
, secure
, prio
);
458 /* Return the current raw priority register value.
459 * secure indicates the bank to use for banked exceptions (we assert if
460 * we are passed secure=true for a non-banked exception).
462 static int get_prio(NVICState
*s
, unsigned irq
, bool secure
)
464 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
465 assert(irq
< s
->num_irq
);
468 assert(exc_is_banked(irq
));
469 return s
->sec_vectors
[irq
].prio
;
471 return s
->vectors
[irq
].prio
;
475 /* Recompute state and assert irq line accordingly.
476 * Must be called after changes to:
477 * vec->active, vec->enabled, vec->pending or vec->prio for any vector
480 static void nvic_irq_update(NVICState
*s
)
485 nvic_recompute_state(s
);
486 pend_prio
= nvic_pending_prio(s
);
488 /* Raise NVIC output if this IRQ would be taken, except that we
489 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
490 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
491 * to those CPU registers don't cause us to recalculate the NVIC
494 lvl
= (pend_prio
< s
->exception_prio
);
495 trace_nvic_irq_update(s
->vectpending
, pend_prio
, s
->exception_prio
, lvl
);
496 qemu_set_irq(s
->excpout
, lvl
);
500 * armv7m_nvic_clear_pending: mark the specified exception as not pending
502 * @irq: the exception number to mark as not pending
503 * @secure: false for non-banked exceptions or for the nonsecure
504 * version of a banked exception, true for the secure version of a banked
507 * Marks the specified exception as not pending. Note that we will assert()
508 * if @secure is true and @irq does not specify one of the fixed set
509 * of architecturally banked exceptions.
511 static void armv7m_nvic_clear_pending(void *opaque
, int irq
, bool secure
)
513 NVICState
*s
= (NVICState
*)opaque
;
516 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
519 assert(exc_is_banked(irq
));
520 vec
= &s
->sec_vectors
[irq
];
522 vec
= &s
->vectors
[irq
];
524 trace_nvic_clear_pending(irq
, secure
, vec
->enabled
, vec
->prio
);
531 static void do_armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
,
534 /* Pend an exception, including possibly escalating it to HardFault.
536 * This function handles both "normal" pending of interrupts and
537 * exceptions, and also derived exceptions (ones which occur as
538 * a result of trying to take some other exception).
540 * If derived == true, the caller guarantees that we are part way through
541 * trying to take an exception (but have not yet called
542 * armv7m_nvic_acknowledge_irq() to make it active), and so:
543 * - s->vectpending is the "original exception" we were trying to take
544 * - irq is the "derived exception"
545 * - nvic_exec_prio(s) gives the priority before exception entry
546 * Here we handle the prioritization logic which the pseudocode puts
547 * in the DerivedLateArrival() function.
550 NVICState
*s
= (NVICState
*)opaque
;
551 bool banked
= exc_is_banked(irq
);
555 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
556 assert(!secure
|| banked
);
558 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
560 targets_secure
= banked
? secure
: exc_targets_secure(s
, irq
);
562 trace_nvic_set_pending(irq
, secure
, targets_secure
,
563 derived
, vec
->enabled
, vec
->prio
);
566 /* Derived exceptions are always synchronous. */
567 assert(irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
);
569 if (irq
== ARMV7M_EXCP_DEBUG
&&
570 exc_group_prio(s
, vec
->prio
, secure
) >= nvic_exec_prio(s
)) {
571 /* DebugMonitorFault, but its priority is lower than the
572 * preempted exception priority: just ignore it.
577 if (irq
== ARMV7M_EXCP_HARD
&& vec
->prio
>= s
->vectpending_prio
) {
578 /* If this is a terminal exception (one which means we cannot
579 * take the original exception, like a failure to read its
580 * vector table entry), then we must take the derived exception.
581 * If the derived exception can't take priority over the
582 * original exception, then we go into Lockup.
584 * For QEMU, we rely on the fact that a derived exception is
585 * terminal if and only if it's reported to us as HardFault,
586 * which saves having to have an extra argument is_terminal
587 * that we'd only use in one place.
589 cpu_abort(&s
->cpu
->parent_obj
,
590 "Lockup: can't take terminal derived exception "
591 "(original exception priority %d)\n",
592 s
->vectpending_prio
);
594 /* We now continue with the same code as for a normal pending
595 * exception, which will cause us to pend the derived exception.
596 * We'll then take either the original or the derived exception
597 * based on which is higher priority by the usual mechanism
598 * for selecting the highest priority pending interrupt.
602 if (irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
) {
603 /* If a synchronous exception is pending then it may be
604 * escalated to HardFault if:
605 * * it is equal or lower priority to current execution
607 * (ie we need to take it immediately but we can't do so).
608 * Asynchronous exceptions (and interrupts) simply remain pending.
610 * For QEMU, we don't have any imprecise (asynchronous) faults,
611 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
613 * Debug exceptions are awkward because only Debug exceptions
614 * resulting from the BKPT instruction should be escalated,
615 * but we don't currently implement any Debug exceptions other
616 * than those that result from BKPT, so we treat all debug exceptions
617 * as needing escalation.
619 * This all means we can identify whether to escalate based only on
620 * the exception number and don't (yet) need the caller to explicitly
621 * tell us whether this exception is synchronous or not.
623 int running
= nvic_exec_prio(s
);
624 bool escalate
= false;
626 if (exc_group_prio(s
, vec
->prio
, secure
) >= running
) {
627 trace_nvic_escalate_prio(irq
, vec
->prio
, running
);
629 } else if (!vec
->enabled
) {
630 trace_nvic_escalate_disabled(irq
);
636 /* We need to escalate this exception to a synchronous HardFault.
637 * If BFHFNMINS is set then we escalate to the banked HF for
638 * the target security state of the original exception; otherwise
639 * we take a Secure HardFault.
641 irq
= ARMV7M_EXCP_HARD
;
642 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
) &&
644 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))) {
645 vec
= &s
->sec_vectors
[irq
];
647 vec
= &s
->vectors
[irq
];
649 if (running
<= vec
->prio
) {
650 /* We want to escalate to HardFault but we can't take the
651 * synchronous HardFault at this point either. This is a
652 * Lockup condition due to a guest bug. We don't model
653 * Lockup, so report via cpu_abort() instead.
655 cpu_abort(&s
->cpu
->parent_obj
,
656 "Lockup: can't escalate %d to HardFault "
657 "(current priority %d)\n", irq
, running
);
660 /* HF may be banked but there is only one shared HFSR */
661 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
671 void armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
)
673 do_armv7m_nvic_set_pending(opaque
, irq
, secure
, false);
676 void armv7m_nvic_set_pending_derived(void *opaque
, int irq
, bool secure
)
678 do_armv7m_nvic_set_pending(opaque
, irq
, secure
, true);
681 void armv7m_nvic_set_pending_lazyfp(void *opaque
, int irq
, bool secure
)
684 * Pend an exception during lazy FP stacking. This differs
685 * from the usual exception pending because the logic for
686 * whether we should escalate depends on the saved context
687 * in the FPCCR register, not on the current state of the CPU/NVIC.
689 NVICState
*s
= (NVICState
*)opaque
;
690 bool banked
= exc_is_banked(irq
);
693 bool escalate
= false;
695 * We will only look at bits in fpccr if this is a banked exception
696 * (in which case 'secure' tells us whether it is the S or NS version).
697 * All the bits for the non-banked exceptions are in fpccr_s.
699 uint32_t fpccr_s
= s
->cpu
->env
.v7m
.fpccr
[M_REG_S
];
700 uint32_t fpccr
= s
->cpu
->env
.v7m
.fpccr
[secure
];
702 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
703 assert(!secure
|| banked
);
705 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
707 targets_secure
= banked
? secure
: exc_targets_secure(s
, irq
);
710 case ARMV7M_EXCP_DEBUG
:
711 if (!(fpccr_s
& R_V7M_FPCCR_MONRDY_MASK
)) {
712 /* Ignore DebugMonitor exception */
716 case ARMV7M_EXCP_MEM
:
717 escalate
= !(fpccr
& R_V7M_FPCCR_MMRDY_MASK
);
719 case ARMV7M_EXCP_USAGE
:
720 escalate
= !(fpccr
& R_V7M_FPCCR_UFRDY_MASK
);
722 case ARMV7M_EXCP_BUS
:
723 escalate
= !(fpccr_s
& R_V7M_FPCCR_BFRDY_MASK
);
725 case ARMV7M_EXCP_SECURE
:
726 escalate
= !(fpccr_s
& R_V7M_FPCCR_SFRDY_MASK
);
729 g_assert_not_reached();
734 * Escalate to HardFault: faults that initially targeted Secure
735 * continue to do so, even if HF normally targets NonSecure.
737 irq
= ARMV7M_EXCP_HARD
;
738 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
) &&
740 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))) {
741 vec
= &s
->sec_vectors
[irq
];
743 vec
= &s
->vectors
[irq
];
748 nvic_exec_prio(s
) <= exc_group_prio(s
, vec
->prio
, secure
)) {
749 if (!(fpccr_s
& R_V7M_FPCCR_HFRDY_MASK
)) {
751 * We want to escalate to HardFault but the context the
752 * FP state belongs to prevents the exception pre-empting.
754 cpu_abort(&s
->cpu
->parent_obj
,
755 "Lockup: can't escalate to HardFault during "
756 "lazy FP register stacking\n");
761 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
766 * We do not call nvic_irq_update(), because we know our caller
767 * is going to handle causing us to take the exception by
768 * raising EXCP_LAZYFP, so raising the IRQ line would be
769 * pointless extra work. We just need to recompute the
770 * priorities so that armv7m_nvic_can_take_pending_exception()
771 * returns the right answer.
773 nvic_recompute_state(s
);
777 /* Make pending IRQ active. */
778 void armv7m_nvic_acknowledge_irq(void *opaque
)
780 NVICState
*s
= (NVICState
*)opaque
;
781 CPUARMState
*env
= &s
->cpu
->env
;
782 const int pending
= s
->vectpending
;
783 const int running
= nvic_exec_prio(s
);
786 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
788 if (s
->vectpending_is_s_banked
) {
789 vec
= &s
->sec_vectors
[pending
];
791 vec
= &s
->vectors
[pending
];
794 assert(vec
->enabled
);
795 assert(vec
->pending
);
797 assert(s
->vectpending_prio
< running
);
799 trace_nvic_acknowledge_irq(pending
, s
->vectpending_prio
);
804 write_v7m_exception(env
, s
->vectpending
);
809 void armv7m_nvic_get_pending_irq_info(void *opaque
,
810 int *pirq
, bool *ptargets_secure
)
812 NVICState
*s
= (NVICState
*)opaque
;
813 const int pending
= s
->vectpending
;
816 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
818 if (s
->vectpending_is_s_banked
) {
819 targets_secure
= true;
821 targets_secure
= !exc_is_banked(pending
) &&
822 exc_targets_secure(s
, pending
);
825 trace_nvic_get_pending_irq_info(pending
, targets_secure
);
827 *ptargets_secure
= targets_secure
;
831 int armv7m_nvic_complete_irq(void *opaque
, int irq
, bool secure
)
833 NVICState
*s
= (NVICState
*)opaque
;
837 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
839 trace_nvic_complete_irq(irq
, secure
);
841 if (secure
&& exc_is_banked(irq
)) {
842 vec
= &s
->sec_vectors
[irq
];
844 vec
= &s
->vectors
[irq
];
848 * Identify illegal exception return cases. We can't immediately
849 * return at this point because we still need to deactivate
850 * (either this exception or NMI/HardFault) first.
852 if (!exc_is_banked(irq
) && exc_targets_secure(s
, irq
) != secure
) {
854 * Return from a configurable exception targeting the opposite
855 * security state from the one we're trying to complete it for.
856 * Clear vec because it's not really the VecInfo for this
857 * (irq, secstate) so we mustn't deactivate it.
861 } else if (!vec
->active
) {
862 /* Return from an inactive interrupt */
865 /* Legal return, we will return the RETTOBASE bit value to the caller */
866 ret
= nvic_rettobase(s
);
870 * For negative priorities, v8M will forcibly deactivate the appropriate
871 * NMI or HardFault regardless of what interrupt we're being asked to
872 * deactivate (compare the DeActivate() pseudocode). This is a guard
873 * against software returning from NMI or HardFault with a corrupted
874 * IPSR and leaving the CPU in a negative-priority state.
875 * v7M does not do this, but simply deactivates the requested interrupt.
877 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
878 switch (armv7m_nvic_raw_execution_priority(s
)) {
880 if (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
881 vec
= &s
->vectors
[ARMV7M_EXCP_HARD
];
883 vec
= &s
->sec_vectors
[ARMV7M_EXCP_HARD
];
887 vec
= &s
->vectors
[ARMV7M_EXCP_NMI
];
890 vec
= &s
->sec_vectors
[ARMV7M_EXCP_HARD
];
903 /* Re-pend the exception if it's still held high; only
904 * happens for extenal IRQs
906 assert(irq
>= NVIC_FIRST_IRQ
);
915 bool armv7m_nvic_get_ready_status(void *opaque
, int irq
, bool secure
)
918 * Return whether an exception is "ready", i.e. it is enabled and is
919 * configured at a priority which would allow it to interrupt the
920 * current execution priority.
922 * irq and secure have the same semantics as for armv7m_nvic_set_pending():
923 * for non-banked exceptions secure is always false; for banked exceptions
924 * it indicates which of the exceptions is required.
926 NVICState
*s
= (NVICState
*)opaque
;
927 bool banked
= exc_is_banked(irq
);
929 int running
= nvic_exec_prio(s
);
931 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
932 assert(!secure
|| banked
);
935 * HardFault is an odd special case: we always check against -1,
936 * even if we're secure and HardFault has priority -3; we never
937 * need to check for enabled state.
939 if (irq
== ARMV7M_EXCP_HARD
) {
943 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
945 return vec
->enabled
&&
946 exc_group_prio(s
, vec
->prio
, secure
) < running
;
949 /* callback when external interrupt line is changed */
950 static void set_irq_level(void *opaque
, int n
, int level
)
952 NVICState
*s
= opaque
;
957 assert(n
>= NVIC_FIRST_IRQ
&& n
< s
->num_irq
);
959 trace_nvic_set_irq_level(n
, level
);
961 /* The pending status of an external interrupt is
962 * latched on rising edge and exception handler return.
964 * Pulsing the IRQ will always run the handler
965 * once, and the handler will re-run until the
966 * level is low when the handler completes.
968 vec
= &s
->vectors
[n
];
969 if (level
!= vec
->level
) {
972 armv7m_nvic_set_pending(s
, n
, false);
977 /* callback when external NMI line is changed */
978 static void nvic_nmi_trigger(void *opaque
, int n
, int level
)
980 NVICState
*s
= opaque
;
982 trace_nvic_set_nmi_level(level
);
985 * The architecture doesn't specify whether NMI should share
986 * the normal-interrupt behaviour of being resampled on
987 * exception handler return. We choose not to, so just
988 * set NMI pending here and don't track the current level.
991 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
995 static uint32_t nvic_readl(NVICState
*s
, uint32_t offset
, MemTxAttrs attrs
)
997 ARMCPU
*cpu
= s
->cpu
;
1001 case 4: /* Interrupt Control Type. */
1002 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1005 return ((s
->num_irq
- NVIC_FIRST_IRQ
) / 32) - 1;
1006 case 0xc: /* CPPWR */
1007 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1010 /* We make the IMPDEF choice that nothing can ever go into a
1011 * non-retentive power state, which allows us to RAZ/WI this.
1014 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
1016 int startvec
= 8 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
1019 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1022 if (!attrs
.secure
) {
1026 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
1027 if (s
->itns
[startvec
+ i
]) {
1034 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8_1M
)) {
1038 case 0xd00: /* CPUID Base. */
1040 case 0xd04: /* Interrupt Control State (ICSR) */
1042 val
= cpu
->env
.v7m
.exception
;
1044 val
|= (s
->vectpending
& 0xff) << 12;
1045 /* ISRPENDING - set if any external IRQ is pending */
1046 if (nvic_isrpending(s
)) {
1049 /* RETTOBASE - set if only one handler is active */
1050 if (nvic_rettobase(s
)) {
1055 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
1059 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
1064 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
1068 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
1073 if ((attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))
1074 && s
->vectors
[ARMV7M_EXCP_NMI
].pending
) {
1077 /* ISRPREEMPT: RES0 when halting debug not implemented */
1078 /* STTNS: RES0 for the Main Extension */
1080 case 0xd08: /* Vector Table Offset. */
1081 return cpu
->env
.v7m
.vecbase
[attrs
.secure
];
1082 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
1083 val
= 0xfa050000 | (s
->prigroup
[attrs
.secure
] << 8);
1085 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
1086 val
|= cpu
->env
.v7m
.aircr
;
1088 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1089 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
1090 * security isn't supported then BFHFNMINS is RAO (and
1091 * the bit in env.v7m.aircr is always set).
1093 val
|= cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
;
1097 case 0xd10: /* System Control. */
1098 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1101 return cpu
->env
.v7m
.scr
[attrs
.secure
];
1102 case 0xd14: /* Configuration Control. */
1104 * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
1105 * and TRD (stored in the S copy of the register)
1107 val
= cpu
->env
.v7m
.ccr
[attrs
.secure
];
1108 val
|= cpu
->env
.v7m
.ccr
[M_REG_NS
] & R_V7M_CCR_BFHFNMIGN_MASK
;
1110 case 0xd24: /* System Handler Control and State (SHCSR) */
1111 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1116 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
) {
1119 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
) {
1122 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
) {
1125 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
) {
1128 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
) {
1131 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
1134 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
) {
1137 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
) {
1140 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
) {
1143 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
) {
1146 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
1149 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
) {
1152 /* SecureFault is not banked but is always RAZ/WI to NS */
1153 if (s
->vectors
[ARMV7M_EXCP_SECURE
].active
) {
1156 if (s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
) {
1159 if (s
->vectors
[ARMV7M_EXCP_SECURE
].pending
) {
1163 if (s
->vectors
[ARMV7M_EXCP_MEM
].active
) {
1166 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1167 /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
1168 if (s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
1171 if (s
->vectors
[ARMV7M_EXCP_HARD
].pending
) {
1175 if (s
->vectors
[ARMV7M_EXCP_USAGE
].active
) {
1178 if (s
->vectors
[ARMV7M_EXCP_SVC
].active
) {
1181 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].active
) {
1184 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
1187 if (s
->vectors
[ARMV7M_EXCP_USAGE
].pending
) {
1190 if (s
->vectors
[ARMV7M_EXCP_MEM
].pending
) {
1193 if (s
->vectors
[ARMV7M_EXCP_SVC
].pending
) {
1196 if (s
->vectors
[ARMV7M_EXCP_MEM
].enabled
) {
1199 if (s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
1203 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1204 if (s
->vectors
[ARMV7M_EXCP_BUS
].active
) {
1207 if (s
->vectors
[ARMV7M_EXCP_BUS
].pending
) {
1210 if (s
->vectors
[ARMV7M_EXCP_BUS
].enabled
) {
1213 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
1214 s
->vectors
[ARMV7M_EXCP_NMI
].active
) {
1215 /* NMIACT is not present in v7M */
1220 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1221 if (s
->vectors
[ARMV7M_EXCP_DEBUG
].active
) {
1225 case 0xd2c: /* Hard Fault Status. */
1226 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1229 return cpu
->env
.v7m
.hfsr
;
1230 case 0xd30: /* Debug Fault Status. */
1231 return cpu
->env
.v7m
.dfsr
;
1232 case 0xd34: /* MMFAR MemManage Fault Address */
1233 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1236 return cpu
->env
.v7m
.mmfar
[attrs
.secure
];
1237 case 0xd38: /* Bus Fault Address. */
1238 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1241 if (!attrs
.secure
&&
1242 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1245 return cpu
->env
.v7m
.bfar
;
1246 case 0xd3c: /* Aux Fault Status. */
1247 /* TODO: Implement fault status registers. */
1248 qemu_log_mask(LOG_UNIMP
,
1249 "Aux Fault status registers unimplemented\n");
1251 case 0xd40: /* PFR0. */
1252 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1255 return cpu
->isar
.id_pfr0
;
1256 case 0xd44: /* PFR1. */
1257 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1260 return cpu
->isar
.id_pfr1
;
1261 case 0xd48: /* DFR0. */
1262 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1265 return cpu
->isar
.id_dfr0
;
1266 case 0xd4c: /* AFR0. */
1267 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1270 return cpu
->id_afr0
;
1271 case 0xd50: /* MMFR0. */
1272 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1275 return cpu
->isar
.id_mmfr0
;
1276 case 0xd54: /* MMFR1. */
1277 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1280 return cpu
->isar
.id_mmfr1
;
1281 case 0xd58: /* MMFR2. */
1282 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1285 return cpu
->isar
.id_mmfr2
;
1286 case 0xd5c: /* MMFR3. */
1287 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1290 return cpu
->isar
.id_mmfr3
;
1291 case 0xd60: /* ISAR0. */
1292 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1295 return cpu
->isar
.id_isar0
;
1296 case 0xd64: /* ISAR1. */
1297 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1300 return cpu
->isar
.id_isar1
;
1301 case 0xd68: /* ISAR2. */
1302 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1305 return cpu
->isar
.id_isar2
;
1306 case 0xd6c: /* ISAR3. */
1307 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1310 return cpu
->isar
.id_isar3
;
1311 case 0xd70: /* ISAR4. */
1312 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1315 return cpu
->isar
.id_isar4
;
1316 case 0xd74: /* ISAR5. */
1317 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1320 return cpu
->isar
.id_isar5
;
1321 case 0xd78: /* CLIDR */
1323 case 0xd7c: /* CTR */
1325 case 0xd80: /* CSSIDR */
1327 int idx
= cpu
->env
.v7m
.csselr
[attrs
.secure
] & R_V7M_CSSELR_INDEX_MASK
;
1328 return cpu
->ccsidr
[idx
];
1330 case 0xd84: /* CSSELR */
1331 return cpu
->env
.v7m
.csselr
[attrs
.secure
];
1332 case 0xd88: /* CPACR */
1333 if (!cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1336 return cpu
->env
.v7m
.cpacr
[attrs
.secure
];
1337 case 0xd8c: /* NSACR */
1338 if (!attrs
.secure
|| !cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1341 return cpu
->env
.v7m
.nsacr
;
1342 /* TODO: Implement debug registers. */
1343 case 0xd90: /* MPU_TYPE */
1344 /* Unified MPU; if the MPU is not present this value is zero */
1345 return cpu
->pmsav7_dregion
<< 8;
1346 case 0xd94: /* MPU_CTRL */
1347 return cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
];
1348 case 0xd98: /* MPU_RNR */
1349 return cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1350 case 0xd9c: /* MPU_RBAR */
1351 case 0xda4: /* MPU_RBAR_A1 */
1352 case 0xdac: /* MPU_RBAR_A2 */
1353 case 0xdb4: /* MPU_RBAR_A3 */
1355 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1357 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1358 /* PMSAv8M handling of the aliases is different from v7M:
1359 * aliases A1, A2, A3 override the low two bits of the region
1360 * number in MPU_RNR, and there is no 'region' field in the
1363 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1365 region
= deposit32(region
, 0, 2, aliasno
);
1367 if (region
>= cpu
->pmsav7_dregion
) {
1370 return cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
];
1373 if (region
>= cpu
->pmsav7_dregion
) {
1376 return (cpu
->env
.pmsav7
.drbar
[region
] & ~0x1f) | (region
& 0xf);
1378 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1379 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1380 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1381 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1383 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1385 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1386 /* PMSAv8M handling of the aliases is different from v7M:
1387 * aliases A1, A2, A3 override the low two bits of the region
1388 * number in MPU_RNR.
1390 int aliasno
= (offset
- 0xda0) / 8; /* 0..3 */
1392 region
= deposit32(region
, 0, 2, aliasno
);
1394 if (region
>= cpu
->pmsav7_dregion
) {
1397 return cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
];
1400 if (region
>= cpu
->pmsav7_dregion
) {
1403 return ((cpu
->env
.pmsav7
.dracr
[region
] & 0xffff) << 16) |
1404 (cpu
->env
.pmsav7
.drsr
[region
] & 0xffff);
1406 case 0xdc0: /* MPU_MAIR0 */
1407 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1410 return cpu
->env
.pmsav8
.mair0
[attrs
.secure
];
1411 case 0xdc4: /* MPU_MAIR1 */
1412 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1415 return cpu
->env
.pmsav8
.mair1
[attrs
.secure
];
1416 case 0xdd0: /* SAU_CTRL */
1417 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1420 if (!attrs
.secure
) {
1423 return cpu
->env
.sau
.ctrl
;
1424 case 0xdd4: /* SAU_TYPE */
1425 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1428 if (!attrs
.secure
) {
1431 return cpu
->sau_sregion
;
1432 case 0xdd8: /* SAU_RNR */
1433 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1436 if (!attrs
.secure
) {
1439 return cpu
->env
.sau
.rnr
;
1440 case 0xddc: /* SAU_RBAR */
1442 int region
= cpu
->env
.sau
.rnr
;
1444 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1447 if (!attrs
.secure
) {
1450 if (region
>= cpu
->sau_sregion
) {
1453 return cpu
->env
.sau
.rbar
[region
];
1455 case 0xde0: /* SAU_RLAR */
1457 int region
= cpu
->env
.sau
.rnr
;
1459 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1462 if (!attrs
.secure
) {
1465 if (region
>= cpu
->sau_sregion
) {
1468 return cpu
->env
.sau
.rlar
[region
];
1470 case 0xde4: /* SFSR */
1471 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1474 if (!attrs
.secure
) {
1477 return cpu
->env
.v7m
.sfsr
;
1478 case 0xde8: /* SFAR */
1479 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1482 if (!attrs
.secure
) {
1485 return cpu
->env
.v7m
.sfar
;
1486 case 0xf34: /* FPCCR */
1487 if (!cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1491 return cpu
->env
.v7m
.fpccr
[M_REG_S
];
1494 * NS can read LSPEN, CLRONRET and MONRDY. It can read
1495 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0;
1496 * other non-banked bits RAZ.
1497 * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set.
1499 uint32_t value
= cpu
->env
.v7m
.fpccr
[M_REG_S
];
1500 uint32_t mask
= R_V7M_FPCCR_LSPEN_MASK
|
1501 R_V7M_FPCCR_CLRONRET_MASK
|
1502 R_V7M_FPCCR_MONRDY_MASK
;
1504 if (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1505 mask
|= R_V7M_FPCCR_BFRDY_MASK
| R_V7M_FPCCR_HFRDY_MASK
;
1510 value
|= cpu
->env
.v7m
.fpccr
[M_REG_NS
];
1513 case 0xf38: /* FPCAR */
1514 if (!cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1517 return cpu
->env
.v7m
.fpcar
[attrs
.secure
];
1518 case 0xf3c: /* FPDSCR */
1519 if (!cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1522 return cpu
->env
.v7m
.fpdscr
[attrs
.secure
];
1523 case 0xf40: /* MVFR0 */
1524 return cpu
->isar
.mvfr0
;
1525 case 0xf44: /* MVFR1 */
1526 return cpu
->isar
.mvfr1
;
1527 case 0xf48: /* MVFR2 */
1528 return cpu
->isar
.mvfr2
;
1531 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
1536 static void nvic_writel(NVICState
*s
, uint32_t offset
, uint32_t value
,
1539 ARMCPU
*cpu
= s
->cpu
;
1542 case 0xc: /* CPPWR */
1543 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1546 /* Make the IMPDEF choice to RAZ/WI this. */
1548 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
1550 int startvec
= 8 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
1553 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1556 if (!attrs
.secure
) {
1559 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
1560 s
->itns
[startvec
+ i
] = (value
>> i
) & 1;
1565 case 0xd04: /* Interrupt Control State (ICSR) */
1566 if (attrs
.secure
|| cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1567 if (value
& (1 << 31)) {
1568 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
1569 } else if (value
& (1 << 30) &&
1570 arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1571 /* PENDNMICLR didn't exist in v7M */
1572 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_NMI
, false);
1575 if (value
& (1 << 28)) {
1576 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1577 } else if (value
& (1 << 27)) {
1578 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1580 if (value
& (1 << 26)) {
1581 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1582 } else if (value
& (1 << 25)) {
1583 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1586 case 0xd08: /* Vector Table Offset. */
1587 cpu
->env
.v7m
.vecbase
[attrs
.secure
] = value
& 0xffffff80;
1589 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
1590 if ((value
>> R_V7M_AIRCR_VECTKEY_SHIFT
) == 0x05fa) {
1591 if (value
& R_V7M_AIRCR_SYSRESETREQ_MASK
) {
1593 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_SYSRESETREQS_MASK
)) {
1594 signal_sysresetreq(s
);
1597 if (value
& R_V7M_AIRCR_VECTCLRACTIVE_MASK
) {
1598 qemu_log_mask(LOG_GUEST_ERROR
,
1599 "Setting VECTCLRACTIVE when not in DEBUG mode "
1600 "is UNPREDICTABLE\n");
1602 if (value
& R_V7M_AIRCR_VECTRESET_MASK
) {
1603 /* NB: this bit is RES0 in v8M */
1604 qemu_log_mask(LOG_GUEST_ERROR
,
1605 "Setting VECTRESET when not in DEBUG mode "
1606 "is UNPREDICTABLE\n");
1608 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1609 s
->prigroup
[attrs
.secure
] =
1611 R_V7M_AIRCR_PRIGROUP_SHIFT
,
1612 R_V7M_AIRCR_PRIGROUP_LENGTH
);
1615 /* These bits are only writable by secure */
1616 cpu
->env
.v7m
.aircr
= value
&
1617 (R_V7M_AIRCR_SYSRESETREQS_MASK
|
1618 R_V7M_AIRCR_BFHFNMINS_MASK
|
1619 R_V7M_AIRCR_PRIS_MASK
);
1620 /* BFHFNMINS changes the priority of Secure HardFault, and
1621 * allows a pending Non-secure HardFault to preempt (which
1622 * we implement by marking it enabled).
1624 if (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1625 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -3;
1626 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1628 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1629 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
1635 case 0xd10: /* System Control. */
1636 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1639 /* We don't implement deep-sleep so these bits are RAZ/WI.
1640 * The other bits in the register are banked.
1641 * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which
1642 * is architecturally permitted.
1644 value
&= ~(R_V7M_SCR_SLEEPDEEP_MASK
| R_V7M_SCR_SLEEPDEEPS_MASK
);
1645 cpu
->env
.v7m
.scr
[attrs
.secure
] = value
;
1647 case 0xd14: /* Configuration Control. */
1651 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1655 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
1656 mask
= R_V7M_CCR_STKALIGN_MASK
|
1657 R_V7M_CCR_BFHFNMIGN_MASK
|
1658 R_V7M_CCR_DIV_0_TRP_MASK
|
1659 R_V7M_CCR_UNALIGN_TRP_MASK
|
1660 R_V7M_CCR_USERSETMPEND_MASK
|
1661 R_V7M_CCR_NONBASETHRDENA_MASK
;
1662 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8_1M
) && attrs
.secure
) {
1663 /* TRD is always RAZ/WI from NS */
1664 mask
|= R_V7M_CCR_TRD_MASK
;
1668 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1669 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
1670 value
|= R_V7M_CCR_NONBASETHRDENA_MASK
1671 | R_V7M_CCR_STKALIGN_MASK
;
1674 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
1675 cpu
->env
.v7m
.ccr
[M_REG_NS
] =
1676 (cpu
->env
.v7m
.ccr
[M_REG_NS
] & ~R_V7M_CCR_BFHFNMIGN_MASK
)
1677 | (value
& R_V7M_CCR_BFHFNMIGN_MASK
);
1678 value
&= ~R_V7M_CCR_BFHFNMIGN_MASK
;
1681 cpu
->env
.v7m
.ccr
[attrs
.secure
] = value
;
1684 case 0xd24: /* System Handler Control and State (SHCSR) */
1685 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1689 s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1690 /* Secure HardFault active bit cannot be written */
1691 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1692 s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1693 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
=
1694 (value
& (1 << 10)) != 0;
1695 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
=
1696 (value
& (1 << 11)) != 0;
1697 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
=
1698 (value
& (1 << 12)) != 0;
1699 s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1700 s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1701 s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1702 s
->sec_vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1703 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
=
1704 (value
& (1 << 18)) != 0;
1705 s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1706 /* SecureFault not banked, but RAZ/WI to NS */
1707 s
->vectors
[ARMV7M_EXCP_SECURE
].active
= (value
& (1 << 4)) != 0;
1708 s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
= (value
& (1 << 19)) != 0;
1709 s
->vectors
[ARMV7M_EXCP_SECURE
].pending
= (value
& (1 << 20)) != 0;
1711 s
->vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1712 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1713 /* HARDFAULTPENDED is not present in v7M */
1714 s
->vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1716 s
->vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1717 s
->vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1718 s
->vectors
[ARMV7M_EXCP_PENDSV
].active
= (value
& (1 << 10)) != 0;
1719 s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
= (value
& (1 << 11)) != 0;
1720 s
->vectors
[ARMV7M_EXCP_USAGE
].pending
= (value
& (1 << 12)) != 0;
1721 s
->vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1722 s
->vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1723 s
->vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1724 s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
1726 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1727 s
->vectors
[ARMV7M_EXCP_BUS
].active
= (value
& (1 << 1)) != 0;
1728 s
->vectors
[ARMV7M_EXCP_BUS
].pending
= (value
& (1 << 14)) != 0;
1729 s
->vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1731 /* NMIACT can only be written if the write is of a zero, with
1732 * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
1734 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1735 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1736 (value
& (1 << 5)) == 0) {
1737 s
->vectors
[ARMV7M_EXCP_NMI
].active
= 0;
1739 /* HARDFAULTACT can only be written if the write is of a zero
1740 * to the non-secure HardFault state by the CPU in secure state.
1741 * The only case where we can be targeting the non-secure HF state
1742 * when in secure state is if this is a write via the NS alias
1743 * and BFHFNMINS is 1.
1745 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1746 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1747 (value
& (1 << 2)) == 0) {
1748 s
->vectors
[ARMV7M_EXCP_HARD
].active
= 0;
1751 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1752 s
->vectors
[ARMV7M_EXCP_DEBUG
].active
= (value
& (1 << 8)) != 0;
1755 case 0xd2c: /* Hard Fault Status. */
1756 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1759 cpu
->env
.v7m
.hfsr
&= ~value
; /* W1C */
1761 case 0xd30: /* Debug Fault Status. */
1762 cpu
->env
.v7m
.dfsr
&= ~value
; /* W1C */
1764 case 0xd34: /* Mem Manage Address. */
1765 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1768 cpu
->env
.v7m
.mmfar
[attrs
.secure
] = value
;
1770 case 0xd38: /* Bus Fault Address. */
1771 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1774 if (!attrs
.secure
&&
1775 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1778 cpu
->env
.v7m
.bfar
= value
;
1780 case 0xd3c: /* Aux Fault Status. */
1781 qemu_log_mask(LOG_UNIMP
,
1782 "NVIC: Aux fault status registers unimplemented\n");
1784 case 0xd84: /* CSSELR */
1785 if (!arm_v7m_csselr_razwi(cpu
)) {
1786 cpu
->env
.v7m
.csselr
[attrs
.secure
] = value
& R_V7M_CSSELR_INDEX_MASK
;
1789 case 0xd88: /* CPACR */
1790 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1791 /* We implement only the Floating Point extension's CP10/CP11 */
1792 cpu
->env
.v7m
.cpacr
[attrs
.secure
] = value
& (0xf << 20);
1795 case 0xd8c: /* NSACR */
1796 if (attrs
.secure
&& cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1797 /* We implement only the Floating Point extension's CP10/CP11 */
1798 cpu
->env
.v7m
.nsacr
= value
& (3 << 10);
1801 case 0xd90: /* MPU_TYPE */
1803 case 0xd94: /* MPU_CTRL */
1805 (R_V7M_MPU_CTRL_HFNMIENA_MASK
| R_V7M_MPU_CTRL_ENABLE_MASK
))
1806 == R_V7M_MPU_CTRL_HFNMIENA_MASK
) {
1807 qemu_log_mask(LOG_GUEST_ERROR
, "MPU_CTRL: HFNMIENA and !ENABLE is "
1810 cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
]
1811 = value
& (R_V7M_MPU_CTRL_ENABLE_MASK
|
1812 R_V7M_MPU_CTRL_HFNMIENA_MASK
|
1813 R_V7M_MPU_CTRL_PRIVDEFENA_MASK
);
1814 tlb_flush(CPU(cpu
));
1816 case 0xd98: /* MPU_RNR */
1817 if (value
>= cpu
->pmsav7_dregion
) {
1818 qemu_log_mask(LOG_GUEST_ERROR
, "MPU region out of range %"
1819 PRIu32
"/%" PRIu32
"\n",
1820 value
, cpu
->pmsav7_dregion
);
1822 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = value
;
1825 case 0xd9c: /* MPU_RBAR */
1826 case 0xda4: /* MPU_RBAR_A1 */
1827 case 0xdac: /* MPU_RBAR_A2 */
1828 case 0xdb4: /* MPU_RBAR_A3 */
1832 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1833 /* PMSAv8M handling of the aliases is different from v7M:
1834 * aliases A1, A2, A3 override the low two bits of the region
1835 * number in MPU_RNR, and there is no 'region' field in the
1838 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1840 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1842 region
= deposit32(region
, 0, 2, aliasno
);
1844 if (region
>= cpu
->pmsav7_dregion
) {
1847 cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
] = value
;
1848 tlb_flush(CPU(cpu
));
1852 if (value
& (1 << 4)) {
1853 /* VALID bit means use the region number specified in this
1854 * value and also update MPU_RNR.REGION with that value.
1856 region
= extract32(value
, 0, 4);
1857 if (region
>= cpu
->pmsav7_dregion
) {
1858 qemu_log_mask(LOG_GUEST_ERROR
,
1859 "MPU region out of range %u/%" PRIu32
"\n",
1860 region
, cpu
->pmsav7_dregion
);
1863 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = region
;
1865 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1868 if (region
>= cpu
->pmsav7_dregion
) {
1872 cpu
->env
.pmsav7
.drbar
[region
] = value
& ~0x1f;
1873 tlb_flush(CPU(cpu
));
1876 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1877 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1878 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1879 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1881 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1883 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1884 /* PMSAv8M handling of the aliases is different from v7M:
1885 * aliases A1, A2, A3 override the low two bits of the region
1886 * number in MPU_RNR.
1888 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1890 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1892 region
= deposit32(region
, 0, 2, aliasno
);
1894 if (region
>= cpu
->pmsav7_dregion
) {
1897 cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
] = value
;
1898 tlb_flush(CPU(cpu
));
1902 if (region
>= cpu
->pmsav7_dregion
) {
1906 cpu
->env
.pmsav7
.drsr
[region
] = value
& 0xff3f;
1907 cpu
->env
.pmsav7
.dracr
[region
] = (value
>> 16) & 0x173f;
1908 tlb_flush(CPU(cpu
));
1911 case 0xdc0: /* MPU_MAIR0 */
1912 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1915 if (cpu
->pmsav7_dregion
) {
1916 /* Register is RES0 if no MPU regions are implemented */
1917 cpu
->env
.pmsav8
.mair0
[attrs
.secure
] = value
;
1919 /* We don't need to do anything else because memory attributes
1920 * only affect cacheability, and we don't implement caching.
1923 case 0xdc4: /* MPU_MAIR1 */
1924 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1927 if (cpu
->pmsav7_dregion
) {
1928 /* Register is RES0 if no MPU regions are implemented */
1929 cpu
->env
.pmsav8
.mair1
[attrs
.secure
] = value
;
1931 /* We don't need to do anything else because memory attributes
1932 * only affect cacheability, and we don't implement caching.
1935 case 0xdd0: /* SAU_CTRL */
1936 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1939 if (!attrs
.secure
) {
1942 cpu
->env
.sau
.ctrl
= value
& 3;
1944 case 0xdd4: /* SAU_TYPE */
1945 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1949 case 0xdd8: /* SAU_RNR */
1950 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1953 if (!attrs
.secure
) {
1956 if (value
>= cpu
->sau_sregion
) {
1957 qemu_log_mask(LOG_GUEST_ERROR
, "SAU region out of range %"
1958 PRIu32
"/%" PRIu32
"\n",
1959 value
, cpu
->sau_sregion
);
1961 cpu
->env
.sau
.rnr
= value
;
1964 case 0xddc: /* SAU_RBAR */
1966 int region
= cpu
->env
.sau
.rnr
;
1968 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1971 if (!attrs
.secure
) {
1974 if (region
>= cpu
->sau_sregion
) {
1977 cpu
->env
.sau
.rbar
[region
] = value
& ~0x1f;
1978 tlb_flush(CPU(cpu
));
1981 case 0xde0: /* SAU_RLAR */
1983 int region
= cpu
->env
.sau
.rnr
;
1985 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1988 if (!attrs
.secure
) {
1991 if (region
>= cpu
->sau_sregion
) {
1994 cpu
->env
.sau
.rlar
[region
] = value
& ~0x1c;
1995 tlb_flush(CPU(cpu
));
1998 case 0xde4: /* SFSR */
1999 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
2002 if (!attrs
.secure
) {
2005 cpu
->env
.v7m
.sfsr
&= ~value
; /* W1C */
2007 case 0xde8: /* SFAR */
2008 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
2011 if (!attrs
.secure
) {
2014 cpu
->env
.v7m
.sfsr
= value
;
2016 case 0xf00: /* Software Triggered Interrupt Register */
2018 int excnum
= (value
& 0x1ff) + NVIC_FIRST_IRQ
;
2020 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2024 if (excnum
< s
->num_irq
) {
2025 armv7m_nvic_set_pending(s
, excnum
, false);
2029 case 0xf34: /* FPCCR */
2030 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
2031 /* Not all bits here are banked. */
2034 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
2035 /* Don't allow setting of bits not present in v7M */
2036 value
&= (R_V7M_FPCCR_LSPACT_MASK
|
2037 R_V7M_FPCCR_USER_MASK
|
2038 R_V7M_FPCCR_THREAD_MASK
|
2039 R_V7M_FPCCR_HFRDY_MASK
|
2040 R_V7M_FPCCR_MMRDY_MASK
|
2041 R_V7M_FPCCR_BFRDY_MASK
|
2042 R_V7M_FPCCR_MONRDY_MASK
|
2043 R_V7M_FPCCR_LSPEN_MASK
|
2044 R_V7M_FPCCR_ASPEN_MASK
);
2046 value
&= ~R_V7M_FPCCR_RES0_MASK
;
2048 if (!attrs
.secure
) {
2049 /* Some non-banked bits are configurably writable by NS */
2050 fpccr_s
= cpu
->env
.v7m
.fpccr
[M_REG_S
];
2051 if (!(fpccr_s
& R_V7M_FPCCR_LSPENS_MASK
)) {
2052 uint32_t lspen
= FIELD_EX32(value
, V7M_FPCCR
, LSPEN
);
2053 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, LSPEN
, lspen
);
2055 if (!(fpccr_s
& R_V7M_FPCCR_CLRONRETS_MASK
)) {
2056 uint32_t cor
= FIELD_EX32(value
, V7M_FPCCR
, CLRONRET
);
2057 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, CLRONRET
, cor
);
2059 if ((s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2060 uint32_t hfrdy
= FIELD_EX32(value
, V7M_FPCCR
, HFRDY
);
2061 uint32_t bfrdy
= FIELD_EX32(value
, V7M_FPCCR
, BFRDY
);
2062 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, HFRDY
, hfrdy
);
2063 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, BFRDY
, bfrdy
);
2065 /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */
2067 uint32_t monrdy
= FIELD_EX32(value
, V7M_FPCCR
, MONRDY
);
2068 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, MONRDY
, monrdy
);
2072 * All other non-banked bits are RAZ/WI from NS; write
2073 * just the banked bits to fpccr[M_REG_NS].
2075 value
&= R_V7M_FPCCR_BANKED_MASK
;
2076 cpu
->env
.v7m
.fpccr
[M_REG_NS
] = value
;
2080 cpu
->env
.v7m
.fpccr
[M_REG_S
] = fpccr_s
;
2083 case 0xf38: /* FPCAR */
2084 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
2086 cpu
->env
.v7m
.fpcar
[attrs
.secure
] = value
;
2089 case 0xf3c: /* FPDSCR */
2090 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
2091 uint32_t mask
= FPCR_AHP
| FPCR_DN
| FPCR_FZ
| FPCR_RMODE_MASK
;
2092 if (cpu_isar_feature(any_fp16
, cpu
)) {
2096 if (cpu_isar_feature(aa32_lob
, cpu
)) {
2097 value
|= 4 << FPCR_LTPSIZE_SHIFT
;
2099 cpu
->env
.v7m
.fpdscr
[attrs
.secure
] = value
;
2102 case 0xf50: /* ICIALLU */
2103 case 0xf58: /* ICIMVAU */
2104 case 0xf5c: /* DCIMVAC */
2105 case 0xf60: /* DCISW */
2106 case 0xf64: /* DCCMVAU */
2107 case 0xf68: /* DCCMVAC */
2108 case 0xf6c: /* DCCSW */
2109 case 0xf70: /* DCCIMVAC */
2110 case 0xf74: /* DCCISW */
2111 case 0xf78: /* BPIALL */
2112 /* Cache and branch predictor maintenance: for QEMU these always NOP */
2116 qemu_log_mask(LOG_GUEST_ERROR
,
2117 "NVIC: Bad write offset 0x%x\n", offset
);
2121 static bool nvic_user_access_ok(NVICState
*s
, hwaddr offset
, MemTxAttrs attrs
)
2123 /* Return true if unprivileged access to this register is permitted. */
2125 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
2126 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
2127 * controls access even though the CPU is in Secure state (I_QDKX).
2129 return s
->cpu
->env
.v7m
.ccr
[attrs
.secure
] & R_V7M_CCR_USERSETMPEND_MASK
;
2131 /* All other user accesses cause a BusFault unconditionally */
2136 static int shpr_bank(NVICState
*s
, int exc
, MemTxAttrs attrs
)
2138 /* Behaviour for the SHPR register field for this exception:
2139 * return M_REG_NS to use the nonsecure vector (including for
2140 * non-banked exceptions), M_REG_S for the secure version of
2141 * a banked exception, and -1 if this field should RAZ/WI.
2144 case ARMV7M_EXCP_MEM
:
2145 case ARMV7M_EXCP_USAGE
:
2146 case ARMV7M_EXCP_SVC
:
2147 case ARMV7M_EXCP_PENDSV
:
2148 case ARMV7M_EXCP_SYSTICK
:
2149 /* Banked exceptions */
2150 return attrs
.secure
;
2151 case ARMV7M_EXCP_BUS
:
2152 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
2153 if (!attrs
.secure
&&
2154 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2158 case ARMV7M_EXCP_SECURE
:
2159 /* Not banked, RAZ/WI from nonsecure */
2160 if (!attrs
.secure
) {
2164 case ARMV7M_EXCP_DEBUG
:
2165 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
2172 /* Not reachable due to decode of SHPR register addresses */
2173 g_assert_not_reached();
2177 static MemTxResult
nvic_sysreg_read(void *opaque
, hwaddr addr
,
2178 uint64_t *data
, unsigned size
,
2181 NVICState
*s
= (NVICState
*)opaque
;
2182 uint32_t offset
= addr
;
2183 unsigned i
, startvec
, end
;
2186 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
2187 /* Generate BusFault for unprivileged accesses */
2192 /* reads of set and clear both return the status */
2193 case 0x100 ... 0x13f: /* NVIC Set enable */
2196 case 0x180 ... 0x1bf: /* NVIC Clear enable */
2198 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
; /* vector # */
2200 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2201 if (s
->vectors
[startvec
+ i
].enabled
&&
2202 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2207 case 0x200 ... 0x23f: /* NVIC Set pend */
2210 case 0x280 ... 0x2bf: /* NVIC Clear pend */
2212 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
2213 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2214 if (s
->vectors
[startvec
+ i
].pending
&&
2215 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2220 case 0x300 ... 0x33f: /* NVIC Active */
2223 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_V7
)) {
2227 startvec
= 8 * (offset
- 0x300) + NVIC_FIRST_IRQ
; /* vector # */
2229 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2230 if (s
->vectors
[startvec
+ i
].active
&&
2231 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2236 case 0x400 ... 0x5ef: /* NVIC Priority */
2238 startvec
= offset
- 0x400 + NVIC_FIRST_IRQ
; /* vector # */
2240 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
2241 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
2242 val
|= s
->vectors
[startvec
+ i
].prio
<< (8 * i
);
2246 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
2247 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2252 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
2254 for (i
= 0; i
< size
; i
++) {
2255 unsigned hdlidx
= (offset
- 0xd14) + i
;
2256 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
2261 val
= deposit32(val
, i
* 8, 8, get_prio(s
, hdlidx
, sbank
));
2264 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
2265 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2270 * The BFSR bits [15:8] are shared between security states
2271 * and we store them in the NS copy. They are RAZ/WI for
2272 * NS code if AIRCR.BFHFNMINS is 0.
2274 val
= s
->cpu
->env
.v7m
.cfsr
[attrs
.secure
];
2275 if (!attrs
.secure
&&
2276 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2277 val
&= ~R_V7M_CFSR_BFSR_MASK
;
2279 val
|= s
->cpu
->env
.v7m
.cfsr
[M_REG_NS
] & R_V7M_CFSR_BFSR_MASK
;
2281 val
= extract32(val
, (offset
- 0xd28) * 8, size
* 8);
2283 case 0xfe0 ... 0xfff: /* ID. */
2287 val
= nvic_id
[(offset
- 0xfe0) >> 2];
2292 val
= nvic_readl(s
, offset
, attrs
);
2294 qemu_log_mask(LOG_GUEST_ERROR
,
2295 "NVIC: Bad read of size %d at offset 0x%x\n",
2301 trace_nvic_sysreg_read(addr
, val
, size
);
2306 static MemTxResult
nvic_sysreg_write(void *opaque
, hwaddr addr
,
2307 uint64_t value
, unsigned size
,
2310 NVICState
*s
= (NVICState
*)opaque
;
2311 uint32_t offset
= addr
;
2312 unsigned i
, startvec
, end
;
2313 unsigned setval
= 0;
2315 trace_nvic_sysreg_write(addr
, value
, size
);
2317 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
2318 /* Generate BusFault for unprivileged accesses */
2323 case 0x100 ... 0x13f: /* NVIC Set enable */
2327 case 0x180 ... 0x1bf: /* NVIC Clear enable */
2328 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
;
2330 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2331 if (value
& (1 << i
) &&
2332 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2333 s
->vectors
[startvec
+ i
].enabled
= setval
;
2338 case 0x200 ... 0x23f: /* NVIC Set pend */
2339 /* the special logic in armv7m_nvic_set_pending()
2340 * is not needed since IRQs are never escalated
2345 case 0x280 ... 0x2bf: /* NVIC Clear pend */
2346 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
2348 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2349 if (value
& (1 << i
) &&
2350 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2351 s
->vectors
[startvec
+ i
].pending
= setval
;
2356 case 0x300 ... 0x33f: /* NVIC Active */
2357 goto exit_ok
; /* R/O */
2358 case 0x400 ... 0x5ef: /* NVIC Priority */
2359 startvec
= (offset
- 0x400) + NVIC_FIRST_IRQ
; /* vector # */
2361 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
2362 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
2363 set_prio(s
, startvec
+ i
, false, (value
>> (i
* 8)) & 0xff);
2368 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
2369 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2373 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
2374 for (i
= 0; i
< size
; i
++) {
2375 unsigned hdlidx
= (offset
- 0xd14) + i
;
2376 int newprio
= extract32(value
, i
* 8, 8);
2377 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
2382 set_prio(s
, hdlidx
, sbank
, newprio
);
2386 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
2387 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2390 /* All bits are W1C, so construct 32 bit value with 0s in
2391 * the parts not written by the access size
2393 value
<<= ((offset
- 0xd28) * 8);
2395 if (!attrs
.secure
&&
2396 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2397 /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */
2398 value
&= ~R_V7M_CFSR_BFSR_MASK
;
2401 s
->cpu
->env
.v7m
.cfsr
[attrs
.secure
] &= ~value
;
2403 /* The BFSR bits [15:8] are shared between security states
2404 * and we store them in the NS copy.
2406 s
->cpu
->env
.v7m
.cfsr
[M_REG_NS
] &= ~(value
& R_V7M_CFSR_BFSR_MASK
);
2411 nvic_writel(s
, offset
, value
, attrs
);
2414 qemu_log_mask(LOG_GUEST_ERROR
,
2415 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
2416 /* This is UNPREDICTABLE; treat as RAZ/WI */
2419 /* Ensure any changes made are reflected in the cached hflags. */
2420 arm_rebuild_hflags(&s
->cpu
->env
);
2424 static const MemoryRegionOps nvic_sysreg_ops
= {
2425 .read_with_attrs
= nvic_sysreg_read
,
2426 .write_with_attrs
= nvic_sysreg_write
,
2427 .endianness
= DEVICE_NATIVE_ENDIAN
,
2430 static MemTxResult
nvic_sysreg_ns_write(void *opaque
, hwaddr addr
,
2431 uint64_t value
, unsigned size
,
2434 MemoryRegion
*mr
= opaque
;
2437 /* S accesses to the alias act like NS accesses to the real region */
2439 return memory_region_dispatch_write(mr
, addr
, value
,
2440 size_memop(size
) | MO_TE
, attrs
);
2442 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
2450 static MemTxResult
nvic_sysreg_ns_read(void *opaque
, hwaddr addr
,
2451 uint64_t *data
, unsigned size
,
2454 MemoryRegion
*mr
= opaque
;
2457 /* S accesses to the alias act like NS accesses to the real region */
2459 return memory_region_dispatch_read(mr
, addr
, data
,
2460 size_memop(size
) | MO_TE
, attrs
);
2462 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
2471 static const MemoryRegionOps nvic_sysreg_ns_ops
= {
2472 .read_with_attrs
= nvic_sysreg_ns_read
,
2473 .write_with_attrs
= nvic_sysreg_ns_write
,
2474 .endianness
= DEVICE_NATIVE_ENDIAN
,
2477 static MemTxResult
nvic_systick_write(void *opaque
, hwaddr addr
,
2478 uint64_t value
, unsigned size
,
2481 NVICState
*s
= opaque
;
2484 /* Direct the access to the correct systick */
2485 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->systick
[attrs
.secure
]), 0);
2486 return memory_region_dispatch_write(mr
, addr
, value
,
2487 size_memop(size
) | MO_TE
, attrs
);
2490 static MemTxResult
nvic_systick_read(void *opaque
, hwaddr addr
,
2491 uint64_t *data
, unsigned size
,
2494 NVICState
*s
= opaque
;
2497 /* Direct the access to the correct systick */
2498 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->systick
[attrs
.secure
]), 0);
2499 return memory_region_dispatch_read(mr
, addr
, data
, size_memop(size
) | MO_TE
,
2503 static const MemoryRegionOps nvic_systick_ops
= {
2504 .read_with_attrs
= nvic_systick_read
,
2505 .write_with_attrs
= nvic_systick_write
,
2506 .endianness
= DEVICE_NATIVE_ENDIAN
,
2510 * Unassigned portions of the PPB space are RAZ/WI for privileged
2511 * accesses, and fault for non-privileged accesses.
2513 static MemTxResult
ppb_default_read(void *opaque
, hwaddr addr
,
2514 uint64_t *data
, unsigned size
,
2517 qemu_log_mask(LOG_UNIMP
, "Read of unassigned area of PPB: offset 0x%x\n",
2526 static MemTxResult
ppb_default_write(void *opaque
, hwaddr addr
,
2527 uint64_t value
, unsigned size
,
2530 qemu_log_mask(LOG_UNIMP
, "Write of unassigned area of PPB: offset 0x%x\n",
2538 static const MemoryRegionOps ppb_default_ops
= {
2539 .read_with_attrs
= ppb_default_read
,
2540 .write_with_attrs
= ppb_default_write
,
2541 .endianness
= DEVICE_NATIVE_ENDIAN
,
2542 .valid
.min_access_size
= 1,
2543 .valid
.max_access_size
= 8,
2546 static int nvic_post_load(void *opaque
, int version_id
)
2548 NVICState
*s
= opaque
;
2552 /* Check for out of range priority settings */
2553 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
2555 if (s
->vectors
[ARMV7M_EXCP_RESET
].prio
!= resetprio
||
2556 s
->vectors
[ARMV7M_EXCP_NMI
].prio
!= -2 ||
2557 s
->vectors
[ARMV7M_EXCP_HARD
].prio
!= -1) {
2560 for (i
= ARMV7M_EXCP_MEM
; i
< s
->num_irq
; i
++) {
2561 if (s
->vectors
[i
].prio
& ~0xff) {
2566 nvic_recompute_state(s
);
2571 static const VMStateDescription vmstate_VecInfo
= {
2572 .name
= "armv7m_nvic_info",
2574 .minimum_version_id
= 1,
2575 .fields
= (VMStateField
[]) {
2576 VMSTATE_INT16(prio
, VecInfo
),
2577 VMSTATE_UINT8(enabled
, VecInfo
),
2578 VMSTATE_UINT8(pending
, VecInfo
),
2579 VMSTATE_UINT8(active
, VecInfo
),
2580 VMSTATE_UINT8(level
, VecInfo
),
2581 VMSTATE_END_OF_LIST()
2585 static bool nvic_security_needed(void *opaque
)
2587 NVICState
*s
= opaque
;
2589 return arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
2592 static int nvic_security_post_load(void *opaque
, int version_id
)
2594 NVICState
*s
= opaque
;
2597 /* Check for out of range priority settings */
2598 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -1
2599 && s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -3) {
2600 /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
2601 * if the CPU state has been migrated yet; a mismatch won't
2602 * cause the emulation to blow up, though.
2606 for (i
= ARMV7M_EXCP_MEM
; i
< ARRAY_SIZE(s
->sec_vectors
); i
++) {
2607 if (s
->sec_vectors
[i
].prio
& ~0xff) {
2614 static const VMStateDescription vmstate_nvic_security
= {
2615 .name
= "armv7m_nvic/m-security",
2617 .minimum_version_id
= 1,
2618 .needed
= nvic_security_needed
,
2619 .post_load
= &nvic_security_post_load
,
2620 .fields
= (VMStateField
[]) {
2621 VMSTATE_STRUCT_ARRAY(sec_vectors
, NVICState
, NVIC_INTERNAL_VECTORS
, 1,
2622 vmstate_VecInfo
, VecInfo
),
2623 VMSTATE_UINT32(prigroup
[M_REG_S
], NVICState
),
2624 VMSTATE_BOOL_ARRAY(itns
, NVICState
, NVIC_MAX_VECTORS
),
2625 VMSTATE_END_OF_LIST()
2629 static const VMStateDescription vmstate_nvic
= {
2630 .name
= "armv7m_nvic",
2632 .minimum_version_id
= 4,
2633 .post_load
= &nvic_post_load
,
2634 .fields
= (VMStateField
[]) {
2635 VMSTATE_STRUCT_ARRAY(vectors
, NVICState
, NVIC_MAX_VECTORS
, 1,
2636 vmstate_VecInfo
, VecInfo
),
2637 VMSTATE_UINT32(prigroup
[M_REG_NS
], NVICState
),
2638 VMSTATE_END_OF_LIST()
2640 .subsections
= (const VMStateDescription
*[]) {
2641 &vmstate_nvic_security
,
2646 static Property props_nvic
[] = {
2647 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
2648 DEFINE_PROP_UINT32("num-irq", NVICState
, num_irq
, 64),
2649 DEFINE_PROP_END_OF_LIST()
2652 static void armv7m_nvic_reset(DeviceState
*dev
)
2655 NVICState
*s
= NVIC(dev
);
2657 memset(s
->vectors
, 0, sizeof(s
->vectors
));
2658 memset(s
->sec_vectors
, 0, sizeof(s
->sec_vectors
));
2659 s
->prigroup
[M_REG_NS
] = 0;
2660 s
->prigroup
[M_REG_S
] = 0;
2662 s
->vectors
[ARMV7M_EXCP_NMI
].enabled
= 1;
2663 /* MEM, BUS, and USAGE are enabled through
2664 * the System Handler Control register
2666 s
->vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
2667 s
->vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
2668 s
->vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
2670 /* DebugMonitor is enabled via DEMCR.MON_EN */
2671 s
->vectors
[ARMV7M_EXCP_DEBUG
].enabled
= 0;
2673 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
2674 s
->vectors
[ARMV7M_EXCP_RESET
].prio
= resetprio
;
2675 s
->vectors
[ARMV7M_EXCP_NMI
].prio
= -2;
2676 s
->vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
2678 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2679 s
->sec_vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
2680 s
->sec_vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
2681 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
2682 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
2684 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
2685 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
2686 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
2687 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
2689 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
2692 /* Strictly speaking the reset handler should be enabled.
2693 * However, we don't simulate soft resets through the NVIC,
2694 * and the reset vector should never be pended.
2695 * So we leave it disabled to catch logic errors.
2698 s
->exception_prio
= NVIC_NOEXC_PRIO
;
2700 s
->vectpending_is_s_banked
= false;
2701 s
->vectpending_prio
= NVIC_NOEXC_PRIO
;
2703 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2704 memset(s
->itns
, 0, sizeof(s
->itns
));
2706 /* This state is constant and not guest accessible in a non-security
2707 * NVIC; we set the bits to true to avoid having to do a feature
2708 * bit check in the NVIC enable/pend/etc register accessors.
2712 for (i
= NVIC_FIRST_IRQ
; i
< ARRAY_SIZE(s
->itns
); i
++) {
2718 * We updated state that affects the CPU's MMUidx and thus its hflags;
2719 * and we can't guarantee that we run before the CPU reset function.
2721 arm_rebuild_hflags(&s
->cpu
->env
);
2724 static void nvic_systick_trigger(void *opaque
, int n
, int level
)
2726 NVICState
*s
= opaque
;
2729 /* SysTick just asked us to pend its exception.
2730 * (This is different from an external interrupt line's
2732 * n == 0 : NonSecure systick
2733 * n == 1 : Secure systick
2735 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, n
);
2739 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
2741 NVICState
*s
= NVIC(dev
);
2743 /* The armv7m container object will have set our CPU pointer */
2744 if (!s
->cpu
|| !arm_feature(&s
->cpu
->env
, ARM_FEATURE_M
)) {
2745 error_setg(errp
, "The NVIC can only be used with a Cortex-M CPU");
2749 if (s
->num_irq
> NVIC_MAX_IRQ
) {
2750 error_setg(errp
, "num-irq %d exceeds NVIC maximum", s
->num_irq
);
2754 qdev_init_gpio_in(dev
, set_irq_level
, s
->num_irq
);
2756 /* include space for internal exception vectors */
2757 s
->num_irq
+= NVIC_FIRST_IRQ
;
2759 s
->num_prio_bits
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V7
) ? 8 : 2;
2761 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->systick
[M_REG_NS
]), errp
)) {
2764 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->systick
[M_REG_NS
]), 0,
2765 qdev_get_gpio_in_named(dev
, "systick-trigger",
2768 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2769 /* We couldn't init the secure systick device in instance_init
2770 * as we didn't know then if the CPU had the security extensions;
2771 * so we have to do it here.
2773 object_initialize_child(OBJECT(dev
), "systick-reg-s",
2774 &s
->systick
[M_REG_S
], TYPE_SYSTICK
);
2776 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->systick
[M_REG_S
]), errp
)) {
2779 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->systick
[M_REG_S
]), 0,
2780 qdev_get_gpio_in_named(dev
, "systick-trigger",
2785 * This device provides a single sysbus memory region which
2786 * represents the whole of the "System PPB" space. This is the
2787 * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
2788 * the System Control Space (system registers), the systick timer,
2789 * and for CPUs with the Security extension an NS banked version
2792 * The default behaviour for unimplemented registers/ranges
2793 * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
2794 * is to RAZ/WI for privileged access and BusFault for non-privileged
2797 * The NVIC and System Control Space (SCS) starts at 0xe000e000
2798 * and looks like this:
2800 * 0x010 - 0xff - systick
2801 * 0x100..0x7ec - NVIC
2802 * 0x7f0..0xcff - Reserved
2803 * 0xd00..0xd3c - SCS registers
2804 * 0xd40..0xeff - Reserved or Not implemented
2807 * Some registers within this space are banked between security states.
2808 * In v8M there is a second range 0xe002e000..0xe002efff which is the
2809 * NonSecure alias SCS; secure accesses to this behave like NS accesses
2810 * to the main SCS range, and non-secure accesses (including when
2811 * the security extension is not implemented) are RAZ/WI.
2812 * Note that both the main SCS range and the alias range are defined
2813 * to be exempt from memory attribution (R_BLJT) and so the memory
2814 * transaction attribute always matches the current CPU security
2815 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
2816 * wrappers we change attrs.secure to indicate the NS access; so
2817 * generally code determining which banked register to use should
2818 * use attrs.secure; code determining actual behaviour of the system
2819 * should use env->v7m.secure.
2821 * The container covers the whole PPB space. Within it the priority
2822 * of overlapping regions is:
2823 * - default region (for RAZ/WI and BusFault) : -1
2824 * - system register regions : 0
2826 * This is because the systick device is a small block of registers
2827 * in the middle of the other system control registers.
2829 memory_region_init(&s
->container
, OBJECT(s
), "nvic", 0x100000);
2830 memory_region_init_io(&s
->defaultmem
, OBJECT(s
), &ppb_default_ops
, s
,
2831 "nvic-default", 0x100000);
2832 memory_region_add_subregion_overlap(&s
->container
, 0, &s
->defaultmem
, -1);
2833 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
2834 "nvic_sysregs", 0x1000);
2835 memory_region_add_subregion(&s
->container
, 0xe000, &s
->sysregmem
);
2837 memory_region_init_io(&s
->systickmem
, OBJECT(s
),
2838 &nvic_systick_ops
, s
,
2839 "nvic_systick", 0xe0);
2841 memory_region_add_subregion_overlap(&s
->container
, 0xe010,
2844 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
2845 memory_region_init_io(&s
->sysreg_ns_mem
, OBJECT(s
),
2846 &nvic_sysreg_ns_ops
, &s
->sysregmem
,
2847 "nvic_sysregs_ns", 0x1000);
2848 memory_region_add_subregion(&s
->container
, 0x2e000, &s
->sysreg_ns_mem
);
2849 memory_region_init_io(&s
->systick_ns_mem
, OBJECT(s
),
2850 &nvic_sysreg_ns_ops
, &s
->systickmem
,
2851 "nvic_systick_ns", 0xe0);
2852 memory_region_add_subregion_overlap(&s
->container
, 0x2e010,
2853 &s
->systick_ns_mem
, 1);
2856 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->container
);
2859 static void armv7m_nvic_instance_init(Object
*obj
)
2861 /* We have a different default value for the num-irq property
2862 * than our superclass. This function runs after qdev init
2863 * has set the defaults from the Property array and before
2864 * any user-specified property setting, so just modify the
2865 * value in the GICState struct.
2867 DeviceState
*dev
= DEVICE(obj
);
2868 NVICState
*nvic
= NVIC(obj
);
2869 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
2871 object_initialize_child(obj
, "systick-reg-ns", &nvic
->systick
[M_REG_NS
],
2873 /* We can't initialize the secure systick here, as we don't know
2874 * yet if we need it.
2877 sysbus_init_irq(sbd
, &nvic
->excpout
);
2878 qdev_init_gpio_out_named(dev
, &nvic
->sysresetreq
, "SYSRESETREQ", 1);
2879 qdev_init_gpio_in_named(dev
, nvic_systick_trigger
, "systick-trigger",
2881 qdev_init_gpio_in_named(dev
, nvic_nmi_trigger
, "NMI", 1);
2884 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
2886 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2888 dc
->vmsd
= &vmstate_nvic
;
2889 device_class_set_props(dc
, props_nvic
);
2890 dc
->reset
= armv7m_nvic_reset
;
2891 dc
->realize
= armv7m_nvic_realize
;
2894 static const TypeInfo armv7m_nvic_info
= {
2896 .parent
= TYPE_SYS_BUS_DEVICE
,
2897 .instance_init
= armv7m_nvic_instance_init
,
2898 .instance_size
= sizeof(NVICState
),
2899 .class_init
= armv7m_nvic_class_init
,
2900 .class_size
= sizeof(SysBusDeviceClass
),
2903 static void armv7m_nvic_register_types(void)
2905 type_register_static(&armv7m_nvic_info
);
2908 type_init(armv7m_nvic_register_types
)