disas/riscv.c

   1 /*
   2  * QEMU RISC-V Disassembler
   3  *
   4  * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "disas/dis-asm.h"
  22
  23
  24 /* types */
  25
  26 typedef uint64_t rv_inst;
  27 typedef uint16_t rv_opcode;
  28
  29 /* enums */
  30
  31 typedef enum {
  32     rv32,
  33     rv64,
  34     rv128
  35 } rv_isa;
  36
  37 typedef enum {
  38     rv_rm_rne = 0,
  39     rv_rm_rtz = 1,
  40     rv_rm_rdn = 2,
  41     rv_rm_rup = 3,
  42     rv_rm_rmm = 4,
  43     rv_rm_dyn = 7,
  44 } rv_rm;
  45
  46 typedef enum {
  47     rv_fence_i = 8,
  48     rv_fence_o = 4,
  49     rv_fence_r = 2,
  50     rv_fence_w = 1,
  51 } rv_fence;
  52
  53 typedef enum {
  54     rv_ireg_zero,
  55     rv_ireg_ra,
  56     rv_ireg_sp,
  57     rv_ireg_gp,
  58     rv_ireg_tp,
  59     rv_ireg_t0,
  60     rv_ireg_t1,
  61     rv_ireg_t2,
  62     rv_ireg_s0,
  63     rv_ireg_s1,
  64     rv_ireg_a0,
  65     rv_ireg_a1,
  66     rv_ireg_a2,
  67     rv_ireg_a3,
  68     rv_ireg_a4,
  69     rv_ireg_a5,
  70     rv_ireg_a6,
  71     rv_ireg_a7,
  72     rv_ireg_s2,
  73     rv_ireg_s3,
  74     rv_ireg_s4,
  75     rv_ireg_s5,
  76     rv_ireg_s6,
  77     rv_ireg_s7,
  78     rv_ireg_s8,
  79     rv_ireg_s9,
  80     rv_ireg_s10,
  81     rv_ireg_s11,
  82     rv_ireg_t3,
  83     rv_ireg_t4,
  84     rv_ireg_t5,
  85     rv_ireg_t6,
  86 } rv_ireg;
  87
  88 typedef enum {
  89     rvc_end,
  90     rvc_rd_eq_ra,
  91     rvc_rd_eq_x0,
  92     rvc_rs1_eq_x0,
  93     rvc_rs2_eq_x0,
  94     rvc_rs2_eq_rs1,
  95     rvc_rs1_eq_ra,
  96     rvc_imm_eq_zero,
  97     rvc_imm_eq_n1,
  98     rvc_imm_eq_p1,
  99     rvc_csr_eq_0x001,
 100     rvc_csr_eq_0x002,
 101     rvc_csr_eq_0x003,
 102     rvc_csr_eq_0xc00,
 103     rvc_csr_eq_0xc01,
 104     rvc_csr_eq_0xc02,
 105     rvc_csr_eq_0xc80,
 106     rvc_csr_eq_0xc81,
 107     rvc_csr_eq_0xc82,
 108 } rvc_constraint;
 109
 110 typedef enum {
 111     rv_codec_illegal,
 112     rv_codec_none,
 113     rv_codec_u,
 114     rv_codec_uj,
 115     rv_codec_i,
 116     rv_codec_i_sh5,
 117     rv_codec_i_sh6,
 118     rv_codec_i_sh7,
 119     rv_codec_i_csr,
 120     rv_codec_s,
 121     rv_codec_sb,
 122     rv_codec_r,
 123     rv_codec_r_m,
 124     rv_codec_r4_m,
 125     rv_codec_r_a,
 126     rv_codec_r_l,
 127     rv_codec_r_f,
 128     rv_codec_cb,
 129     rv_codec_cb_imm,
 130     rv_codec_cb_sh5,
 131     rv_codec_cb_sh6,
 132     rv_codec_ci,
 133     rv_codec_ci_sh5,
 134     rv_codec_ci_sh6,
 135     rv_codec_ci_16sp,
 136     rv_codec_ci_lwsp,
 137     rv_codec_ci_ldsp,
 138     rv_codec_ci_lqsp,
 139     rv_codec_ci_li,
 140     rv_codec_ci_lui,
 141     rv_codec_ci_none,
 142     rv_codec_ciw_4spn,
 143     rv_codec_cj,
 144     rv_codec_cj_jal,
 145     rv_codec_cl_lw,
 146     rv_codec_cl_ld,
 147     rv_codec_cl_lq,
 148     rv_codec_cr,
 149     rv_codec_cr_mv,
 150     rv_codec_cr_jalr,
 151     rv_codec_cr_jr,
 152     rv_codec_cs,
 153     rv_codec_cs_sw,
 154     rv_codec_cs_sd,
 155     rv_codec_cs_sq,
 156     rv_codec_css_swsp,
 157     rv_codec_css_sdsp,
 158     rv_codec_css_sqsp,
 159     rv_codec_k_bs,
 160     rv_codec_k_rnum,
 161     rv_codec_v_r,
 162     rv_codec_v_ldst,
 163     rv_codec_v_i,
 164     rv_codec_vsetvli,
 165     rv_codec_vsetivli,
 166 } rv_codec;
 167
 168 typedef enum {
 169     rv_op_illegal = 0,
 170     rv_op_lui = 1,
 171     rv_op_auipc = 2,
 172     rv_op_jal = 3,
 173     rv_op_jalr = 4,
 174     rv_op_beq = 5,
 175     rv_op_bne = 6,
 176     rv_op_blt = 7,
 177     rv_op_bge = 8,
 178     rv_op_bltu = 9,
 179     rv_op_bgeu = 10,
 180     rv_op_lb = 11,
 181     rv_op_lh = 12,
 182     rv_op_lw = 13,
 183     rv_op_lbu = 14,
 184     rv_op_lhu = 15,
 185     rv_op_sb = 16,
 186     rv_op_sh = 17,
 187     rv_op_sw = 18,
 188     rv_op_addi = 19,
 189     rv_op_slti = 20,
 190     rv_op_sltiu = 21,
 191     rv_op_xori = 22,
 192     rv_op_ori = 23,
 193     rv_op_andi = 24,
 194     rv_op_slli = 25,
 195     rv_op_srli = 26,
 196     rv_op_srai = 27,
 197     rv_op_add = 28,
 198     rv_op_sub = 29,
 199     rv_op_sll = 30,
 200     rv_op_slt = 31,
 201     rv_op_sltu = 32,
 202     rv_op_xor = 33,
 203     rv_op_srl = 34,
 204     rv_op_sra = 35,
 205     rv_op_or = 36,
 206     rv_op_and = 37,
 207     rv_op_fence = 38,
 208     rv_op_fence_i = 39,
 209     rv_op_lwu = 40,
 210     rv_op_ld = 41,
 211     rv_op_sd = 42,
 212     rv_op_addiw = 43,
 213     rv_op_slliw = 44,
 214     rv_op_srliw = 45,
 215     rv_op_sraiw = 46,
 216     rv_op_addw = 47,
 217     rv_op_subw = 48,
 218     rv_op_sllw = 49,
 219     rv_op_srlw = 50,
 220     rv_op_sraw = 51,
 221     rv_op_ldu = 52,
 222     rv_op_lq = 53,
 223     rv_op_sq = 54,
 224     rv_op_addid = 55,
 225     rv_op_sllid = 56,
 226     rv_op_srlid = 57,
 227     rv_op_sraid = 58,
 228     rv_op_addd = 59,
 229     rv_op_subd = 60,
 230     rv_op_slld = 61,
 231     rv_op_srld = 62,
 232     rv_op_srad = 63,
 233     rv_op_mul = 64,
 234     rv_op_mulh = 65,
 235     rv_op_mulhsu = 66,
 236     rv_op_mulhu = 67,
 237     rv_op_div = 68,
 238     rv_op_divu = 69,
 239     rv_op_rem = 70,
 240     rv_op_remu = 71,
 241     rv_op_mulw = 72,
 242     rv_op_divw = 73,
 243     rv_op_divuw = 74,
 244     rv_op_remw = 75,
 245     rv_op_remuw = 76,
 246     rv_op_muld = 77,
 247     rv_op_divd = 78,
 248     rv_op_divud = 79,
 249     rv_op_remd = 80,
 250     rv_op_remud = 81,
 251     rv_op_lr_w = 82,
 252     rv_op_sc_w = 83,
 253     rv_op_amoswap_w = 84,
 254     rv_op_amoadd_w = 85,
 255     rv_op_amoxor_w = 86,
 256     rv_op_amoor_w = 87,
 257     rv_op_amoand_w = 88,
 258     rv_op_amomin_w = 89,
 259     rv_op_amomax_w = 90,
 260     rv_op_amominu_w = 91,
 261     rv_op_amomaxu_w = 92,
 262     rv_op_lr_d = 93,
 263     rv_op_sc_d = 94,
 264     rv_op_amoswap_d = 95,
 265     rv_op_amoadd_d = 96,
 266     rv_op_amoxor_d = 97,
 267     rv_op_amoor_d = 98,
 268     rv_op_amoand_d = 99,
 269     rv_op_amomin_d = 100,
 270     rv_op_amomax_d = 101,
 271     rv_op_amominu_d = 102,
 272     rv_op_amomaxu_d = 103,
 273     rv_op_lr_q = 104,
 274     rv_op_sc_q = 105,
 275     rv_op_amoswap_q = 106,
 276     rv_op_amoadd_q = 107,
 277     rv_op_amoxor_q = 108,
 278     rv_op_amoor_q = 109,
 279     rv_op_amoand_q = 110,
 280     rv_op_amomin_q = 111,
 281     rv_op_amomax_q = 112,
 282     rv_op_amominu_q = 113,
 283     rv_op_amomaxu_q = 114,
 284     rv_op_ecall = 115,
 285     rv_op_ebreak = 116,
 286     rv_op_uret = 117,
 287     rv_op_sret = 118,
 288     rv_op_hret = 119,
 289     rv_op_mret = 120,
 290     rv_op_dret = 121,
 291     rv_op_sfence_vm = 122,
 292     rv_op_sfence_vma = 123,
 293     rv_op_wfi = 124,
 294     rv_op_csrrw = 125,
 295     rv_op_csrrs = 126,
 296     rv_op_csrrc = 127,
 297     rv_op_csrrwi = 128,
 298     rv_op_csrrsi = 129,
 299     rv_op_csrrci = 130,
 300     rv_op_flw = 131,
 301     rv_op_fsw = 132,
 302     rv_op_fmadd_s = 133,
 303     rv_op_fmsub_s = 134,
 304     rv_op_fnmsub_s = 135,
 305     rv_op_fnmadd_s = 136,
 306     rv_op_fadd_s = 137,
 307     rv_op_fsub_s = 138,
 308     rv_op_fmul_s = 139,
 309     rv_op_fdiv_s = 140,
 310     rv_op_fsgnj_s = 141,
 311     rv_op_fsgnjn_s = 142,
 312     rv_op_fsgnjx_s = 143,
 313     rv_op_fmin_s = 144,
 314     rv_op_fmax_s = 145,
 315     rv_op_fsqrt_s = 146,
 316     rv_op_fle_s = 147,
 317     rv_op_flt_s = 148,
 318     rv_op_feq_s = 149,
 319     rv_op_fcvt_w_s = 150,
 320     rv_op_fcvt_wu_s = 151,
 321     rv_op_fcvt_s_w = 152,
 322     rv_op_fcvt_s_wu = 153,
 323     rv_op_fmv_x_s = 154,
 324     rv_op_fclass_s = 155,
 325     rv_op_fmv_s_x = 156,
 326     rv_op_fcvt_l_s = 157,
 327     rv_op_fcvt_lu_s = 158,
 328     rv_op_fcvt_s_l = 159,
 329     rv_op_fcvt_s_lu = 160,
 330     rv_op_fld = 161,
 331     rv_op_fsd = 162,
 332     rv_op_fmadd_d = 163,
 333     rv_op_fmsub_d = 164,
 334     rv_op_fnmsub_d = 165,
 335     rv_op_fnmadd_d = 166,
 336     rv_op_fadd_d = 167,
 337     rv_op_fsub_d = 168,
 338     rv_op_fmul_d = 169,
 339     rv_op_fdiv_d = 170,
 340     rv_op_fsgnj_d = 171,
 341     rv_op_fsgnjn_d = 172,
 342     rv_op_fsgnjx_d = 173,
 343     rv_op_fmin_d = 174,
 344     rv_op_fmax_d = 175,
 345     rv_op_fcvt_s_d = 176,
 346     rv_op_fcvt_d_s = 177,
 347     rv_op_fsqrt_d = 178,
 348     rv_op_fle_d = 179,
 349     rv_op_flt_d = 180,
 350     rv_op_feq_d = 181,
 351     rv_op_fcvt_w_d = 182,
 352     rv_op_fcvt_wu_d = 183,
 353     rv_op_fcvt_d_w = 184,
 354     rv_op_fcvt_d_wu = 185,
 355     rv_op_fclass_d = 186,
 356     rv_op_fcvt_l_d = 187,
 357     rv_op_fcvt_lu_d = 188,
 358     rv_op_fmv_x_d = 189,
 359     rv_op_fcvt_d_l = 190,
 360     rv_op_fcvt_d_lu = 191,
 361     rv_op_fmv_d_x = 192,
 362     rv_op_flq = 193,
 363     rv_op_fsq = 194,
 364     rv_op_fmadd_q = 195,
 365     rv_op_fmsub_q = 196,
 366     rv_op_fnmsub_q = 197,
 367     rv_op_fnmadd_q = 198,
 368     rv_op_fadd_q = 199,
 369     rv_op_fsub_q = 200,
 370     rv_op_fmul_q = 201,
 371     rv_op_fdiv_q = 202,
 372     rv_op_fsgnj_q = 203,
 373     rv_op_fsgnjn_q = 204,
 374     rv_op_fsgnjx_q = 205,
 375     rv_op_fmin_q = 206,
 376     rv_op_fmax_q = 207,
 377     rv_op_fcvt_s_q = 208,
 378     rv_op_fcvt_q_s = 209,
 379     rv_op_fcvt_d_q = 210,
 380     rv_op_fcvt_q_d = 211,
 381     rv_op_fsqrt_q = 212,
 382     rv_op_fle_q = 213,
 383     rv_op_flt_q = 214,
 384     rv_op_feq_q = 215,
 385     rv_op_fcvt_w_q = 216,
 386     rv_op_fcvt_wu_q = 217,
 387     rv_op_fcvt_q_w = 218,
 388     rv_op_fcvt_q_wu = 219,
 389     rv_op_fclass_q = 220,
 390     rv_op_fcvt_l_q = 221,
 391     rv_op_fcvt_lu_q = 222,
 392     rv_op_fcvt_q_l = 223,
 393     rv_op_fcvt_q_lu = 224,
 394     rv_op_fmv_x_q = 225,
 395     rv_op_fmv_q_x = 226,
 396     rv_op_c_addi4spn = 227,
 397     rv_op_c_fld = 228,
 398     rv_op_c_lw = 229,
 399     rv_op_c_flw = 230,
 400     rv_op_c_fsd = 231,
 401     rv_op_c_sw = 232,
 402     rv_op_c_fsw = 233,
 403     rv_op_c_nop = 234,
 404     rv_op_c_addi = 235,
 405     rv_op_c_jal = 236,
 406     rv_op_c_li = 237,
 407     rv_op_c_addi16sp = 238,
 408     rv_op_c_lui = 239,
 409     rv_op_c_srli = 240,
 410     rv_op_c_srai = 241,
 411     rv_op_c_andi = 242,
 412     rv_op_c_sub = 243,
 413     rv_op_c_xor = 244,
 414     rv_op_c_or = 245,
 415     rv_op_c_and = 246,
 416     rv_op_c_subw = 247,
 417     rv_op_c_addw = 248,
 418     rv_op_c_j = 249,
 419     rv_op_c_beqz = 250,
 420     rv_op_c_bnez = 251,
 421     rv_op_c_slli = 252,
 422     rv_op_c_fldsp = 253,
 423     rv_op_c_lwsp = 254,
 424     rv_op_c_flwsp = 255,
 425     rv_op_c_jr = 256,
 426     rv_op_c_mv = 257,
 427     rv_op_c_ebreak = 258,
 428     rv_op_c_jalr = 259,
 429     rv_op_c_add = 260,
 430     rv_op_c_fsdsp = 261,
 431     rv_op_c_swsp = 262,
 432     rv_op_c_fswsp = 263,
 433     rv_op_c_ld = 264,
 434     rv_op_c_sd = 265,
 435     rv_op_c_addiw = 266,
 436     rv_op_c_ldsp = 267,
 437     rv_op_c_sdsp = 268,
 438     rv_op_c_lq = 269,
 439     rv_op_c_sq = 270,
 440     rv_op_c_lqsp = 271,
 441     rv_op_c_sqsp = 272,
 442     rv_op_nop = 273,
 443     rv_op_mv = 274,
 444     rv_op_not = 275,
 445     rv_op_neg = 276,
 446     rv_op_negw = 277,
 447     rv_op_sext_w = 278,
 448     rv_op_seqz = 279,
 449     rv_op_snez = 280,
 450     rv_op_sltz = 281,
 451     rv_op_sgtz = 282,
 452     rv_op_fmv_s = 283,
 453     rv_op_fabs_s = 284,
 454     rv_op_fneg_s = 285,
 455     rv_op_fmv_d = 286,
 456     rv_op_fabs_d = 287,
 457     rv_op_fneg_d = 288,
 458     rv_op_fmv_q = 289,
 459     rv_op_fabs_q = 290,
 460     rv_op_fneg_q = 291,
 461     rv_op_beqz = 292,
 462     rv_op_bnez = 293,
 463     rv_op_blez = 294,
 464     rv_op_bgez = 295,
 465     rv_op_bltz = 296,
 466     rv_op_bgtz = 297,
 467     rv_op_ble = 298,
 468     rv_op_bleu = 299,
 469     rv_op_bgt = 300,
 470     rv_op_bgtu = 301,
 471     rv_op_j = 302,
 472     rv_op_ret = 303,
 473     rv_op_jr = 304,
 474     rv_op_rdcycle = 305,
 475     rv_op_rdtime = 306,
 476     rv_op_rdinstret = 307,
 477     rv_op_rdcycleh = 308,
 478     rv_op_rdtimeh = 309,
 479     rv_op_rdinstreth = 310,
 480     rv_op_frcsr = 311,
 481     rv_op_frrm = 312,
 482     rv_op_frflags = 313,
 483     rv_op_fscsr = 314,
 484     rv_op_fsrm = 315,
 485     rv_op_fsflags = 316,
 486     rv_op_fsrmi = 317,
 487     rv_op_fsflagsi = 318,
 488     rv_op_bseti = 319,
 489     rv_op_bclri = 320,
 490     rv_op_binvi = 321,
 491     rv_op_bexti = 322,
 492     rv_op_rori = 323,
 493     rv_op_clz = 324,
 494     rv_op_ctz = 325,
 495     rv_op_cpop = 326,
 496     rv_op_sext_h = 327,
 497     rv_op_sext_b = 328,
 498     rv_op_xnor = 329,
 499     rv_op_orn = 330,
 500     rv_op_andn = 331,
 501     rv_op_rol = 332,
 502     rv_op_ror = 333,
 503     rv_op_sh1add = 334,
 504     rv_op_sh2add = 335,
 505     rv_op_sh3add = 336,
 506     rv_op_sh1add_uw = 337,
 507     rv_op_sh2add_uw = 338,
 508     rv_op_sh3add_uw = 339,
 509     rv_op_clmul = 340,
 510     rv_op_clmulr = 341,
 511     rv_op_clmulh = 342,
 512     rv_op_min = 343,
 513     rv_op_minu = 344,
 514     rv_op_max = 345,
 515     rv_op_maxu = 346,
 516     rv_op_clzw = 347,
 517     rv_op_ctzw = 348,
 518     rv_op_cpopw = 349,
 519     rv_op_slli_uw = 350,
 520     rv_op_add_uw = 351,
 521     rv_op_rolw = 352,
 522     rv_op_rorw = 353,
 523     rv_op_rev8 = 354,
 524     rv_op_zext_h = 355,
 525     rv_op_roriw = 356,
 526     rv_op_orc_b = 357,
 527     rv_op_bset = 358,
 528     rv_op_bclr = 359,
 529     rv_op_binv = 360,
 530     rv_op_bext = 361,
 531     rv_op_aes32esmi = 362,
 532     rv_op_aes32esi = 363,
 533     rv_op_aes32dsmi = 364,
 534     rv_op_aes32dsi = 365,
 535     rv_op_aes64ks1i = 366,
 536     rv_op_aes64ks2 = 367,
 537     rv_op_aes64im = 368,
 538     rv_op_aes64esm = 369,
 539     rv_op_aes64es = 370,
 540     rv_op_aes64dsm = 371,
 541     rv_op_aes64ds = 372,
 542     rv_op_sha256sig0 = 373,
 543     rv_op_sha256sig1 = 374,
 544     rv_op_sha256sum0 = 375,
 545     rv_op_sha256sum1 = 376,
 546     rv_op_sha512sig0 = 377,
 547     rv_op_sha512sig1 = 378,
 548     rv_op_sha512sum0 = 379,
 549     rv_op_sha512sum1 = 380,
 550     rv_op_sha512sum0r = 381,
 551     rv_op_sha512sum1r = 382,
 552     rv_op_sha512sig0l = 383,
 553     rv_op_sha512sig0h = 384,
 554     rv_op_sha512sig1l = 385,
 555     rv_op_sha512sig1h = 386,
 556     rv_op_sm3p0 = 387,
 557     rv_op_sm3p1 = 388,
 558     rv_op_sm4ed = 389,
 559     rv_op_sm4ks = 390,
 560     rv_op_brev8 = 391,
 561     rv_op_pack = 392,
 562     rv_op_packh = 393,
 563     rv_op_packw = 394,
 564     rv_op_unzip = 395,
 565     rv_op_zip = 396,
 566     rv_op_xperm4 = 397,
 567     rv_op_xperm8 = 398,
 568     rv_op_vle8_v = 399,
 569     rv_op_vle16_v = 400,
 570     rv_op_vle32_v = 401,
 571     rv_op_vle64_v = 402,
 572     rv_op_vse8_v = 403,
 573     rv_op_vse16_v = 404,
 574     rv_op_vse32_v = 405,
 575     rv_op_vse64_v = 406,
 576     rv_op_vlm_v = 407,
 577     rv_op_vsm_v = 408,
 578     rv_op_vlse8_v = 409,
 579     rv_op_vlse16_v = 410,
 580     rv_op_vlse32_v = 411,
 581     rv_op_vlse64_v = 412,
 582     rv_op_vsse8_v = 413,
 583     rv_op_vsse16_v = 414,
 584     rv_op_vsse32_v = 415,
 585     rv_op_vsse64_v = 416,
 586     rv_op_vluxei8_v = 417,
 587     rv_op_vluxei16_v = 418,
 588     rv_op_vluxei32_v = 419,
 589     rv_op_vluxei64_v = 420,
 590     rv_op_vloxei8_v = 421,
 591     rv_op_vloxei16_v = 422,
 592     rv_op_vloxei32_v = 423,
 593     rv_op_vloxei64_v = 424,
 594     rv_op_vsuxei8_v = 425,
 595     rv_op_vsuxei16_v = 426,
 596     rv_op_vsuxei32_v = 427,
 597     rv_op_vsuxei64_v = 428,
 598     rv_op_vsoxei8_v = 429,
 599     rv_op_vsoxei16_v = 430,
 600     rv_op_vsoxei32_v = 431,
 601     rv_op_vsoxei64_v = 432,
 602     rv_op_vle8ff_v = 433,
 603     rv_op_vle16ff_v = 434,
 604     rv_op_vle32ff_v = 435,
 605     rv_op_vle64ff_v = 436,
 606     rv_op_vl1re8_v = 437,
 607     rv_op_vl1re16_v = 438,
 608     rv_op_vl1re32_v = 439,
 609     rv_op_vl1re64_v = 440,
 610     rv_op_vl2re8_v = 441,
 611     rv_op_vl2re16_v = 442,
 612     rv_op_vl2re32_v = 443,
 613     rv_op_vl2re64_v = 444,
 614     rv_op_vl4re8_v = 445,
 615     rv_op_vl4re16_v = 446,
 616     rv_op_vl4re32_v = 447,
 617     rv_op_vl4re64_v = 448,
 618     rv_op_vl8re8_v = 449,
 619     rv_op_vl8re16_v = 450,
 620     rv_op_vl8re32_v = 451,
 621     rv_op_vl8re64_v = 452,
 622     rv_op_vs1r_v = 453,
 623     rv_op_vs2r_v = 454,
 624     rv_op_vs4r_v = 455,
 625     rv_op_vs8r_v = 456,
 626     rv_op_vadd_vv = 457,
 627     rv_op_vadd_vx = 458,
 628     rv_op_vadd_vi = 459,
 629     rv_op_vsub_vv = 460,
 630     rv_op_vsub_vx = 461,
 631     rv_op_vrsub_vx = 462,
 632     rv_op_vrsub_vi = 463,
 633     rv_op_vwaddu_vv = 464,
 634     rv_op_vwaddu_vx = 465,
 635     rv_op_vwadd_vv = 466,
 636     rv_op_vwadd_vx = 467,
 637     rv_op_vwsubu_vv = 468,
 638     rv_op_vwsubu_vx = 469,
 639     rv_op_vwsub_vv = 470,
 640     rv_op_vwsub_vx = 471,
 641     rv_op_vwaddu_wv = 472,
 642     rv_op_vwaddu_wx = 473,
 643     rv_op_vwadd_wv = 474,
 644     rv_op_vwadd_wx = 475,
 645     rv_op_vwsubu_wv = 476,
 646     rv_op_vwsubu_wx = 477,
 647     rv_op_vwsub_wv = 478,
 648     rv_op_vwsub_wx = 479,
 649     rv_op_vadc_vvm = 480,
 650     rv_op_vadc_vxm = 481,
 651     rv_op_vadc_vim = 482,
 652     rv_op_vmadc_vvm = 483,
 653     rv_op_vmadc_vxm = 484,
 654     rv_op_vmadc_vim = 485,
 655     rv_op_vsbc_vvm = 486,
 656     rv_op_vsbc_vxm = 487,
 657     rv_op_vmsbc_vvm = 488,
 658     rv_op_vmsbc_vxm = 489,
 659     rv_op_vand_vv = 490,
 660     rv_op_vand_vx = 491,
 661     rv_op_vand_vi = 492,
 662     rv_op_vor_vv = 493,
 663     rv_op_vor_vx = 494,
 664     rv_op_vor_vi = 495,
 665     rv_op_vxor_vv = 496,
 666     rv_op_vxor_vx = 497,
 667     rv_op_vxor_vi = 498,
 668     rv_op_vsll_vv = 499,
 669     rv_op_vsll_vx = 500,
 670     rv_op_vsll_vi = 501,
 671     rv_op_vsrl_vv = 502,
 672     rv_op_vsrl_vx = 503,
 673     rv_op_vsrl_vi = 504,
 674     rv_op_vsra_vv = 505,
 675     rv_op_vsra_vx = 506,
 676     rv_op_vsra_vi = 507,
 677     rv_op_vnsrl_wv = 508,
 678     rv_op_vnsrl_wx = 509,
 679     rv_op_vnsrl_wi = 510,
 680     rv_op_vnsra_wv = 511,
 681     rv_op_vnsra_wx = 512,
 682     rv_op_vnsra_wi = 513,
 683     rv_op_vmseq_vv = 514,
 684     rv_op_vmseq_vx = 515,
 685     rv_op_vmseq_vi = 516,
 686     rv_op_vmsne_vv = 517,
 687     rv_op_vmsne_vx = 518,
 688     rv_op_vmsne_vi = 519,
 689     rv_op_vmsltu_vv = 520,
 690     rv_op_vmsltu_vx = 521,
 691     rv_op_vmslt_vv = 522,
 692     rv_op_vmslt_vx = 523,
 693     rv_op_vmsleu_vv = 524,
 694     rv_op_vmsleu_vx = 525,
 695     rv_op_vmsleu_vi = 526,
 696     rv_op_vmsle_vv = 527,
 697     rv_op_vmsle_vx = 528,
 698     rv_op_vmsle_vi = 529,
 699     rv_op_vmsgtu_vx = 530,
 700     rv_op_vmsgtu_vi = 531,
 701     rv_op_vmsgt_vx = 532,
 702     rv_op_vmsgt_vi = 533,
 703     rv_op_vminu_vv = 534,
 704     rv_op_vminu_vx = 535,
 705     rv_op_vmin_vv = 536,
 706     rv_op_vmin_vx = 537,
 707     rv_op_vmaxu_vv = 538,
 708     rv_op_vmaxu_vx = 539,
 709     rv_op_vmax_vv = 540,
 710     rv_op_vmax_vx = 541,
 711     rv_op_vmul_vv = 542,
 712     rv_op_vmul_vx = 543,
 713     rv_op_vmulh_vv = 544,
 714     rv_op_vmulh_vx = 545,
 715     rv_op_vmulhu_vv = 546,
 716     rv_op_vmulhu_vx = 547,
 717     rv_op_vmulhsu_vv = 548,
 718     rv_op_vmulhsu_vx = 549,
 719     rv_op_vdivu_vv = 550,
 720     rv_op_vdivu_vx = 551,
 721     rv_op_vdiv_vv = 552,
 722     rv_op_vdiv_vx = 553,
 723     rv_op_vremu_vv = 554,
 724     rv_op_vremu_vx = 555,
 725     rv_op_vrem_vv = 556,
 726     rv_op_vrem_vx = 557,
 727     rv_op_vwmulu_vv = 558,
 728     rv_op_vwmulu_vx = 559,
 729     rv_op_vwmulsu_vv = 560,
 730     rv_op_vwmulsu_vx = 561,
 731     rv_op_vwmul_vv = 562,
 732     rv_op_vwmul_vx = 563,
 733     rv_op_vmacc_vv = 564,
 734     rv_op_vmacc_vx = 565,
 735     rv_op_vnmsac_vv = 566,
 736     rv_op_vnmsac_vx = 567,
 737     rv_op_vmadd_vv = 568,
 738     rv_op_vmadd_vx = 569,
 739     rv_op_vnmsub_vv = 570,
 740     rv_op_vnmsub_vx = 571,
 741     rv_op_vwmaccu_vv = 572,
 742     rv_op_vwmaccu_vx = 573,
 743     rv_op_vwmacc_vv = 574,
 744     rv_op_vwmacc_vx = 575,
 745     rv_op_vwmaccsu_vv = 576,
 746     rv_op_vwmaccsu_vx = 577,
 747     rv_op_vwmaccus_vx = 578,
 748     rv_op_vmv_v_v = 579,
 749     rv_op_vmv_v_x = 580,
 750     rv_op_vmv_v_i = 581,
 751     rv_op_vmerge_vvm = 582,
 752     rv_op_vmerge_vxm = 583,
 753     rv_op_vmerge_vim = 584,
 754     rv_op_vsaddu_vv = 585,
 755     rv_op_vsaddu_vx = 586,
 756     rv_op_vsaddu_vi = 587,
 757     rv_op_vsadd_vv = 588,
 758     rv_op_vsadd_vx = 589,
 759     rv_op_vsadd_vi = 590,
 760     rv_op_vssubu_vv = 591,
 761     rv_op_vssubu_vx = 592,
 762     rv_op_vssub_vv = 593,
 763     rv_op_vssub_vx = 594,
 764     rv_op_vaadd_vv = 595,
 765     rv_op_vaadd_vx = 596,
 766     rv_op_vaaddu_vv = 597,
 767     rv_op_vaaddu_vx = 598,
 768     rv_op_vasub_vv = 599,
 769     rv_op_vasub_vx = 600,
 770     rv_op_vasubu_vv = 601,
 771     rv_op_vasubu_vx = 602,
 772     rv_op_vsmul_vv = 603,
 773     rv_op_vsmul_vx = 604,
 774     rv_op_vssrl_vv = 605,
 775     rv_op_vssrl_vx = 606,
 776     rv_op_vssrl_vi = 607,
 777     rv_op_vssra_vv = 608,
 778     rv_op_vssra_vx = 609,
 779     rv_op_vssra_vi = 610,
 780     rv_op_vnclipu_wv = 611,
 781     rv_op_vnclipu_wx = 612,
 782     rv_op_vnclipu_wi = 613,
 783     rv_op_vnclip_wv = 614,
 784     rv_op_vnclip_wx = 615,
 785     rv_op_vnclip_wi = 616,
 786     rv_op_vfadd_vv = 617,
 787     rv_op_vfadd_vf = 618,
 788     rv_op_vfsub_vv = 619,
 789     rv_op_vfsub_vf = 620,
 790     rv_op_vfrsub_vf = 621,
 791     rv_op_vfwadd_vv = 622,
 792     rv_op_vfwadd_vf = 623,
 793     rv_op_vfwadd_wv = 624,
 794     rv_op_vfwadd_wf = 625,
 795     rv_op_vfwsub_vv = 626,
 796     rv_op_vfwsub_vf = 627,
 797     rv_op_vfwsub_wv = 628,
 798     rv_op_vfwsub_wf = 629,
 799     rv_op_vfmul_vv = 630,
 800     rv_op_vfmul_vf = 631,
 801     rv_op_vfdiv_vv = 632,
 802     rv_op_vfdiv_vf = 633,
 803     rv_op_vfrdiv_vf = 634,
 804     rv_op_vfwmul_vv = 635,
 805     rv_op_vfwmul_vf = 636,
 806     rv_op_vfmacc_vv = 637,
 807     rv_op_vfmacc_vf = 638,
 808     rv_op_vfnmacc_vv = 639,
 809     rv_op_vfnmacc_vf = 640,
 810     rv_op_vfmsac_vv = 641,
 811     rv_op_vfmsac_vf = 642,
 812     rv_op_vfnmsac_vv = 643,
 813     rv_op_vfnmsac_vf = 644,
 814     rv_op_vfmadd_vv = 645,
 815     rv_op_vfmadd_vf = 646,
 816     rv_op_vfnmadd_vv = 647,
 817     rv_op_vfnmadd_vf = 648,
 818     rv_op_vfmsub_vv = 649,
 819     rv_op_vfmsub_vf = 650,
 820     rv_op_vfnmsub_vv = 651,
 821     rv_op_vfnmsub_vf = 652,
 822     rv_op_vfwmacc_vv = 653,
 823     rv_op_vfwmacc_vf = 654,
 824     rv_op_vfwnmacc_vv = 655,
 825     rv_op_vfwnmacc_vf = 656,
 826     rv_op_vfwmsac_vv = 657,
 827     rv_op_vfwmsac_vf = 658,
 828     rv_op_vfwnmsac_vv = 659,
 829     rv_op_vfwnmsac_vf = 660,
 830     rv_op_vfsqrt_v = 661,
 831     rv_op_vfrsqrt7_v = 662,
 832     rv_op_vfrec7_v = 663,
 833     rv_op_vfmin_vv = 664,
 834     rv_op_vfmin_vf = 665,
 835     rv_op_vfmax_vv = 666,
 836     rv_op_vfmax_vf = 667,
 837     rv_op_vfsgnj_vv = 668,
 838     rv_op_vfsgnj_vf = 669,
 839     rv_op_vfsgnjn_vv = 670,
 840     rv_op_vfsgnjn_vf = 671,
 841     rv_op_vfsgnjx_vv = 672,
 842     rv_op_vfsgnjx_vf = 673,
 843     rv_op_vfslide1up_vf = 674,
 844     rv_op_vfslide1down_vf = 675,
 845     rv_op_vmfeq_vv = 676,
 846     rv_op_vmfeq_vf = 677,
 847     rv_op_vmfne_vv = 678,
 848     rv_op_vmfne_vf = 679,
 849     rv_op_vmflt_vv = 680,
 850     rv_op_vmflt_vf = 681,
 851     rv_op_vmfle_vv = 682,
 852     rv_op_vmfle_vf = 683,
 853     rv_op_vmfgt_vf = 684,
 854     rv_op_vmfge_vf = 685,
 855     rv_op_vfclass_v = 686,
 856     rv_op_vfmerge_vfm = 687,
 857     rv_op_vfmv_v_f = 688,
 858     rv_op_vfcvt_xu_f_v = 689,
 859     rv_op_vfcvt_x_f_v = 690,
 860     rv_op_vfcvt_f_xu_v = 691,
 861     rv_op_vfcvt_f_x_v = 692,
 862     rv_op_vfcvt_rtz_xu_f_v = 693,
 863     rv_op_vfcvt_rtz_x_f_v = 694,
 864     rv_op_vfwcvt_xu_f_v = 695,
 865     rv_op_vfwcvt_x_f_v = 696,
 866     rv_op_vfwcvt_f_xu_v = 697,
 867     rv_op_vfwcvt_f_x_v = 698,
 868     rv_op_vfwcvt_f_f_v = 699,
 869     rv_op_vfwcvt_rtz_xu_f_v = 700,
 870     rv_op_vfwcvt_rtz_x_f_v = 701,
 871     rv_op_vfncvt_xu_f_w = 702,
 872     rv_op_vfncvt_x_f_w = 703,
 873     rv_op_vfncvt_f_xu_w = 704,
 874     rv_op_vfncvt_f_x_w = 705,
 875     rv_op_vfncvt_f_f_w = 706,
 876     rv_op_vfncvt_rod_f_f_w = 707,
 877     rv_op_vfncvt_rtz_xu_f_w = 708,
 878     rv_op_vfncvt_rtz_x_f_w = 709,
 879     rv_op_vredsum_vs = 710,
 880     rv_op_vredand_vs = 711,
 881     rv_op_vredor_vs = 712,
 882     rv_op_vredxor_vs = 713,
 883     rv_op_vredminu_vs = 714,
 884     rv_op_vredmin_vs = 715,
 885     rv_op_vredmaxu_vs = 716,
 886     rv_op_vredmax_vs = 717,
 887     rv_op_vwredsumu_vs = 718,
 888     rv_op_vwredsum_vs = 719,
 889     rv_op_vfredusum_vs = 720,
 890     rv_op_vfredosum_vs = 721,
 891     rv_op_vfredmin_vs = 722,
 892     rv_op_vfredmax_vs = 723,
 893     rv_op_vfwredusum_vs = 724,
 894     rv_op_vfwredosum_vs = 725,
 895     rv_op_vmand_mm = 726,
 896     rv_op_vmnand_mm = 727,
 897     rv_op_vmandn_mm = 728,
 898     rv_op_vmxor_mm = 729,
 899     rv_op_vmor_mm = 730,
 900     rv_op_vmnor_mm = 731,
 901     rv_op_vmorn_mm = 732,
 902     rv_op_vmxnor_mm = 733,
 903     rv_op_vcpop_m = 734,
 904     rv_op_vfirst_m = 735,
 905     rv_op_vmsbf_m = 736,
 906     rv_op_vmsif_m = 737,
 907     rv_op_vmsof_m = 738,
 908     rv_op_viota_m = 739,
 909     rv_op_vid_v = 740,
 910     rv_op_vmv_x_s = 741,
 911     rv_op_vmv_s_x = 742,
 912     rv_op_vfmv_f_s = 743,
 913     rv_op_vfmv_s_f = 744,
 914     rv_op_vslideup_vx = 745,
 915     rv_op_vslideup_vi = 746,
 916     rv_op_vslide1up_vx = 747,
 917     rv_op_vslidedown_vx = 748,
 918     rv_op_vslidedown_vi = 749,
 919     rv_op_vslide1down_vx = 750,
 920     rv_op_vrgather_vv = 751,
 921     rv_op_vrgatherei16_vv = 752,
 922     rv_op_vrgather_vx = 753,
 923     rv_op_vrgather_vi = 754,
 924     rv_op_vcompress_vm = 755,
 925     rv_op_vmv1r_v = 756,
 926     rv_op_vmv2r_v = 757,
 927     rv_op_vmv4r_v = 758,
 928     rv_op_vmv8r_v = 759,
 929     rv_op_vzext_vf2 = 760,
 930     rv_op_vzext_vf4 = 761,
 931     rv_op_vzext_vf8 = 762,
 932     rv_op_vsext_vf2 = 763,
 933     rv_op_vsext_vf4 = 764,
 934     rv_op_vsext_vf8 = 765,
 935     rv_op_vsetvli = 766,
 936     rv_op_vsetivli = 767,
 937     rv_op_vsetvl = 768,
 938 } rv_op;
 939
 940 /* structures */
 941
 942 typedef struct {
 943     uint64_t  pc;
 944     uint64_t  inst;
 945     int32_t   imm;
 946     uint16_t  op;
 947     uint8_t   codec;
 948     uint8_t   rd;
 949     uint8_t   rs1;
 950     uint8_t   rs2;
 951     uint8_t   rs3;
 952     uint8_t   rm;
 953     uint8_t   pred;
 954     uint8_t   succ;
 955     uint8_t   aq;
 956     uint8_t   rl;
 957     uint8_t   bs;
 958     uint8_t   rnum;
 959     uint8_t   vm;
 960     uint32_t  vzimm;
 961 } rv_decode;
 962
 963 typedef struct {
 964     const int op;
 965     const rvc_constraint *constraints;
 966 } rv_comp_data;
 967
 968 enum {
 969     rvcd_imm_nz = 0x1
 970 };
 971
 972 typedef struct {
 973     const char * const name;
 974     const rv_codec codec;
 975     const char * const format;
 976     const rv_comp_data *pseudo;
 977     const short decomp_rv32;
 978     const short decomp_rv64;
 979     const short decomp_rv128;
 980     const short decomp_data;
 981 } rv_opcode_data;
 982
 983 /* register names */
 984
 985 static const char rv_ireg_name_sym[32][5] = {
 986     "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
 987     "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
 988     "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
 989     "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
 990 };
 991
 992 static const char rv_freg_name_sym[32][5] = {
 993     "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
 994     "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
 995     "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
 996     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
 997 };
 998
 999 static const char rv_vreg_name_sym[32][4] = {
1000     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
1001     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
1002     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1003     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
1004 };
1005
1006 /* instruction formats */
1007
1008 #define rv_fmt_none                   "O\t"
1009 #define rv_fmt_rs1                    "O\t1"
1010 #define rv_fmt_offset                 "O\to"
1011 #define rv_fmt_pred_succ              "O\tp,s"
1012 #define rv_fmt_rs1_rs2                "O\t1,2"
1013 #define rv_fmt_rd_imm                 "O\t0,i"
1014 #define rv_fmt_rd_offset              "O\t0,o"
1015 #define rv_fmt_rd_rs1_rs2             "O\t0,1,2"
1016 #define rv_fmt_frd_rs1                "O\t3,1"
1017 #define rv_fmt_rd_frs1                "O\t0,4"
1018 #define rv_fmt_rd_frs1_frs2           "O\t0,4,5"
1019 #define rv_fmt_frd_frs1_frs2          "O\t3,4,5"
1020 #define rv_fmt_rm_frd_frs1            "O\tr,3,4"
1021 #define rv_fmt_rm_frd_rs1             "O\tr,3,1"
1022 #define rv_fmt_rm_rd_frs1             "O\tr,0,4"
1023 #define rv_fmt_rm_frd_frs1_frs2       "O\tr,3,4,5"
1024 #define rv_fmt_rm_frd_frs1_frs2_frs3  "O\tr,3,4,5,6"
1025 #define rv_fmt_rd_rs1_imm             "O\t0,1,i"
1026 #define rv_fmt_rd_rs1_offset          "O\t0,1,i"
1027 #define rv_fmt_rd_offset_rs1          "O\t0,i(1)"
1028 #define rv_fmt_frd_offset_rs1         "O\t3,i(1)"
1029 #define rv_fmt_rd_csr_rs1             "O\t0,c,1"
1030 #define rv_fmt_rd_csr_zimm            "O\t0,c,7"
1031 #define rv_fmt_rs2_offset_rs1         "O\t2,i(1)"
1032 #define rv_fmt_frs2_offset_rs1        "O\t5,i(1)"
1033 #define rv_fmt_rs1_rs2_offset         "O\t1,2,o"
1034 #define rv_fmt_rs2_rs1_offset         "O\t2,1,o"
1035 #define rv_fmt_aqrl_rd_rs2_rs1        "OAR\t0,2,(1)"
1036 #define rv_fmt_aqrl_rd_rs1            "OAR\t0,(1)"
1037 #define rv_fmt_rd                     "O\t0"
1038 #define rv_fmt_rd_zimm                "O\t0,7"
1039 #define rv_fmt_rd_rs1                 "O\t0,1"
1040 #define rv_fmt_rd_rs2                 "O\t0,2"
1041 #define rv_fmt_rs1_offset             "O\t1,o"
1042 #define rv_fmt_rs2_offset             "O\t2,o"
1043 #define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
1044 #define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
1045 #define rv_fmt_ldst_vd_rs1_vm         "O\tD,(1)m"
1046 #define rv_fmt_ldst_vd_rs1_rs2_vm     "O\tD,(1),2m"
1047 #define rv_fmt_ldst_vd_rs1_vs2_vm     "O\tD,(1),Fm"
1048 #define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
1049 #define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
1050 #define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
1051 #define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
1052 #define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
1053 #define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
1054 #define rv_fmt_vd_vs2_fs1_vm          "O\tD,F,4m"
1055 #define rv_fmt_vd_vs2_imm_vl          "O\tD,F,il"
1056 #define rv_fmt_vd_vs2_imm_vm          "O\tD,F,im"
1057 #define rv_fmt_vd_vs2_uimm_vm         "O\tD,F,um"
1058 #define rv_fmt_vd_vs1_vs2_vm          "O\tD,E,Fm"
1059 #define rv_fmt_vd_rs1_vs2_vm          "O\tD,1,Fm"
1060 #define rv_fmt_vd_fs1_vs2_vm          "O\tD,4,Fm"
1061 #define rv_fmt_vd_vs1                 "O\tD,E"
1062 #define rv_fmt_vd_rs1                 "O\tD,1"
1063 #define rv_fmt_vd_fs1                 "O\tD,4"
1064 #define rv_fmt_vd_imm                 "O\tD,i"
1065 #define rv_fmt_vd_vs2                 "O\tD,F"
1066 #define rv_fmt_vd_vs2_vm              "O\tD,Fm"
1067 #define rv_fmt_rd_vs2_vm              "O\t0,Fm"
1068 #define rv_fmt_rd_vs2                 "O\t0,F"
1069 #define rv_fmt_fd_vs2                 "O\t3,F"
1070 #define rv_fmt_vd_vm                  "O\tDm"
1071 #define rv_fmt_vsetvli                "O\t0,1,v"
1072 #define rv_fmt_vsetivli               "O\t0,u,v"
1073
1074 /* pseudo-instruction constraints */
1075
1076 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
1077 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
1078 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
1079 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
1080 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
1081 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
1082 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
1083 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
1084 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
1085 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
1086 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
1087 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end };
1088 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end };
1089 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end };
1090 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end };
1091 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end };
1092 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end };
1093 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end };
1094 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end };
1095 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end };
1096 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end };
1097 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end };
1098 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end };
1099 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
1100 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
1101 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
1102 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
1103 static const rvc_constraint rvcc_ble[] = { rvc_end };
1104 static const rvc_constraint rvcc_bleu[] = { rvc_end };
1105 static const rvc_constraint rvcc_bgt[] = { rvc_end };
1106 static const rvc_constraint rvcc_bgtu[] = { rvc_end };
1107 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
1108 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
1109 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
1110 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
1111 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
1112 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
1113 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
1114 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
1115 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
1116                                                   rvc_csr_eq_0xc82, rvc_end };
1117 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
1118 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
1119 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
1120 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
1121 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
1122 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
1123 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
1124 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
1125
1126 /* pseudo-instruction metadata */
1127
1128 static const rv_comp_data rvcp_jal[] = {
1129     { rv_op_j, rvcc_j },
1130     { rv_op_jal, rvcc_jal },
1131     { rv_op_illegal, NULL }
1132 };
1133
1134 static const rv_comp_data rvcp_jalr[] = {
1135     { rv_op_ret, rvcc_ret },
1136     { rv_op_jr, rvcc_jr },
1137     { rv_op_jalr, rvcc_jalr },
1138     { rv_op_illegal, NULL }
1139 };
1140
1141 static const rv_comp_data rvcp_beq[] = {
1142     { rv_op_beqz, rvcc_beqz },
1143     { rv_op_illegal, NULL }
1144 };
1145
1146 static const rv_comp_data rvcp_bne[] = {
1147     { rv_op_bnez, rvcc_bnez },
1148     { rv_op_illegal, NULL }
1149 };
1150
1151 static const rv_comp_data rvcp_blt[] = {
1152     { rv_op_bltz, rvcc_bltz },
1153     { rv_op_bgtz, rvcc_bgtz },
1154     { rv_op_bgt, rvcc_bgt },
1155     { rv_op_illegal, NULL }
1156 };
1157
1158 static const rv_comp_data rvcp_bge[] = {
1159     { rv_op_blez, rvcc_blez },
1160     { rv_op_bgez, rvcc_bgez },
1161     { rv_op_ble, rvcc_ble },
1162     { rv_op_illegal, NULL }
1163 };
1164
1165 static const rv_comp_data rvcp_bltu[] = {
1166     { rv_op_bgtu, rvcc_bgtu },
1167     { rv_op_illegal, NULL }
1168 };
1169
1170 static const rv_comp_data rvcp_bgeu[] = {
1171     { rv_op_bleu, rvcc_bleu },
1172     { rv_op_illegal, NULL }
1173 };
1174
1175 static const rv_comp_data rvcp_addi[] = {
1176     { rv_op_nop, rvcc_nop },
1177     { rv_op_mv, rvcc_mv },
1178     { rv_op_illegal, NULL }
1179 };
1180
1181 static const rv_comp_data rvcp_sltiu[] = {
1182     { rv_op_seqz, rvcc_seqz },
1183     { rv_op_illegal, NULL }
1184 };
1185
1186 static const rv_comp_data rvcp_xori[] = {
1187     { rv_op_not, rvcc_not },
1188     { rv_op_illegal, NULL }
1189 };
1190
1191 static const rv_comp_data rvcp_sub[] = {
1192     { rv_op_neg, rvcc_neg },
1193     { rv_op_illegal, NULL }
1194 };
1195
1196 static const rv_comp_data rvcp_slt[] = {
1197     { rv_op_sltz, rvcc_sltz },
1198     { rv_op_sgtz, rvcc_sgtz },
1199     { rv_op_illegal, NULL }
1200 };
1201
1202 static const rv_comp_data rvcp_sltu[] = {
1203     { rv_op_snez, rvcc_snez },
1204     { rv_op_illegal, NULL }
1205 };
1206
1207 static const rv_comp_data rvcp_addiw[] = {
1208     { rv_op_sext_w, rvcc_sext_w },
1209     { rv_op_illegal, NULL }
1210 };
1211
1212 static const rv_comp_data rvcp_subw[] = {
1213     { rv_op_negw, rvcc_negw },
1214     { rv_op_illegal, NULL }
1215 };
1216
1217 static const rv_comp_data rvcp_csrrw[] = {
1218     { rv_op_fscsr, rvcc_fscsr },
1219     { rv_op_fsrm, rvcc_fsrm },
1220     { rv_op_fsflags, rvcc_fsflags },
1221     { rv_op_illegal, NULL }
1222 };
1223
1224
1225 static const rv_comp_data rvcp_csrrs[] = {
1226     { rv_op_rdcycle, rvcc_rdcycle },
1227     { rv_op_rdtime, rvcc_rdtime },
1228     { rv_op_rdinstret, rvcc_rdinstret },
1229     { rv_op_rdcycleh, rvcc_rdcycleh },
1230     { rv_op_rdtimeh, rvcc_rdtimeh },
1231     { rv_op_rdinstreth, rvcc_rdinstreth },
1232     { rv_op_frcsr, rvcc_frcsr },
1233     { rv_op_frrm, rvcc_frrm },
1234     { rv_op_frflags, rvcc_frflags },
1235     { rv_op_illegal, NULL }
1236 };
1237
1238 static const rv_comp_data rvcp_csrrwi[] = {
1239     { rv_op_fsrmi, rvcc_fsrmi },
1240     { rv_op_fsflagsi, rvcc_fsflagsi },
1241     { rv_op_illegal, NULL }
1242 };
1243
1244 static const rv_comp_data rvcp_fsgnj_s[] = {
1245     { rv_op_fmv_s, rvcc_fmv_s },
1246     { rv_op_illegal, NULL }
1247 };
1248
1249 static const rv_comp_data rvcp_fsgnjn_s[] = {
1250     { rv_op_fneg_s, rvcc_fneg_s },
1251     { rv_op_illegal, NULL }
1252 };
1253
1254 static const rv_comp_data rvcp_fsgnjx_s[] = {
1255     { rv_op_fabs_s, rvcc_fabs_s },
1256     { rv_op_illegal, NULL }
1257 };
1258
1259 static const rv_comp_data rvcp_fsgnj_d[] = {
1260     { rv_op_fmv_d, rvcc_fmv_d },
1261     { rv_op_illegal, NULL }
1262 };
1263
1264 static const rv_comp_data rvcp_fsgnjn_d[] = {
1265     { rv_op_fneg_d, rvcc_fneg_d },
1266     { rv_op_illegal, NULL }
1267 };
1268
1269 static const rv_comp_data rvcp_fsgnjx_d[] = {
1270     { rv_op_fabs_d, rvcc_fabs_d },
1271     { rv_op_illegal, NULL }
1272 };
1273
1274 static const rv_comp_data rvcp_fsgnj_q[] = {
1275     { rv_op_fmv_q, rvcc_fmv_q },
1276     { rv_op_illegal, NULL }
1277 };
1278
1279 static const rv_comp_data rvcp_fsgnjn_q[] = {
1280     { rv_op_fneg_q, rvcc_fneg_q },
1281     { rv_op_illegal, NULL }
1282 };
1283
1284 static const rv_comp_data rvcp_fsgnjx_q[] = {
1285     { rv_op_fabs_q, rvcc_fabs_q },
1286     { rv_op_illegal, NULL }
1287 };
1288
1289 /* instruction metadata */
1290
1291 const rv_opcode_data opcode_data[] = {
1292     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1293     { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
1294     { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
1295     { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
1296     { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
1297     { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
1298     { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
1299     { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
1300     { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
1301     { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
1302     { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
1303     { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1304     { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1305     { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1306     { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1307     { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1308     { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1309     { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1310     { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1311     { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
1312     { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1313     { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
1314     { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
1315     { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1316     { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1317     { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1318     { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1319     { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1320     { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1321     { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
1322     { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1323     { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
1324     { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
1325     { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1326     { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1327     { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1328     { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1329     { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1330     { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
1331     { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1332     { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1333     { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1334     { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1335     { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
1336     { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1337     { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1338     { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1339     { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1340     { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
1341     { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1342     { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1343     { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1344     { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1345     { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1346     { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1347     { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1348     { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1349     { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1350     { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1351     { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1352     { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1353     { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1354     { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1355     { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1356     { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1357     { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1358     { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1359     { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1360     { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1361     { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1362     { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1363     { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1364     { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1365     { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1366     { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1367     { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1368     { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1369     { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1370     { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1371     { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1372     { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1373     { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1374     { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1375     { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1376     { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1377     { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1378     { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1379     { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1380     { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1381     { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1382     { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1383     { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1384     { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1385     { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1386     { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1387     { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1388     { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1389     { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1390     { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1391     { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1392     { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1393     { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1394     { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1395     { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1396     { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1397     { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1398     { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1399     { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1400     { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1401     { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1402     { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1403     { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1404     { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1405     { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1406     { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1407     { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1408     { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1409     { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1410     { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1411     { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1412     { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1413     { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1414     { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
1415     { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
1416     { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1417     { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
1418     { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
1419     { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
1420     { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
1421     { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1422     { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1423     { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1424     { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1425     { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1426     { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1427     { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1428     { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1429     { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1430     { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1431     { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1432     { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1433     { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
1434     { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
1435     { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
1436     { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1437     { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1438     { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1439     { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1440     { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1441     { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1442     { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1443     { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1444     { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1445     { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1446     { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1447     { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1448     { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1449     { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1450     { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1451     { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1452     { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1453     { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1454     { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1455     { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1456     { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1457     { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1458     { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1459     { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1460     { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1461     { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1462     { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1463     { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
1464     { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
1465     { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
1466     { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1467     { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1468     { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1469     { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1470     { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1471     { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1472     { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1473     { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1474     { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1475     { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1476     { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1477     { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1478     { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1479     { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1480     { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1481     { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1482     { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1483     { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1484     { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1485     { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1486     { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1487     { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1488     { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1489     { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1490     { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1491     { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1492     { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1493     { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1494     { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1495     { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
1496     { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
1497     { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
1498     { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1499     { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1500     { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1501     { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1502     { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1503     { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1504     { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1505     { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1506     { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1507     { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1508     { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1509     { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1510     { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1511     { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1512     { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1513     { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1514     { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1515     { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1516     { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1517     { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1518     { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1519     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1520       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1521     { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
1522     { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
1523     { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1524     { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
1525     { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
1526     { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1527     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1528     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1529       rv_op_addi, rvcd_imm_nz },
1530     { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
1531     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1532     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1533       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1534     { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
1535       rv_op_lui, rvcd_imm_nz },
1536     { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
1537       rv_op_srli, rv_op_srli, rvcd_imm_nz },
1538     { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
1539       rv_op_srai, rv_op_srai, rvcd_imm_nz },
1540     { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
1541       rv_op_andi, rv_op_andi },
1542     { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
1543     { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
1544     { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
1545     { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
1546     { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
1547     { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
1548     { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
1549     { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
1550     { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
1551     { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
1552       rv_op_slli, rv_op_slli, rvcd_imm_nz },
1553     { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
1554     { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
1555     { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1556     { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
1557     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1558     { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
1559     { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
1560     { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
1561     { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
1562     { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
1563     { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1564     { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
1565     { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
1566     { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
1567     { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
1568     { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
1569     { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1570     { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1571     { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1572     { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1573     { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1574     { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1575     { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1576     { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1577     { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1578     { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1579     { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1580     { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1581     { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1582     { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1583     { "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1584     { "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1585     { "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1586     { "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1587     { "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1588     { "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1589     { "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1590     { "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1591     { "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1592     { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1593     { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1594     { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1595     { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1596     { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1597     { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1598     { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1599     { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1600     { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1601     { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1602     { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
1603     { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1604     { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
1605     { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1606     { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1607     { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1608     { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1609     { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1610     { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1611     { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1612     { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1613     { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1614     { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1615     { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1616     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1617     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1618     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1619     { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1620     { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1621     { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1622     { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1623     { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1624     { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1625     { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1626     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1627     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1628     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1629     { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1630     { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1631     { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1632     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1633     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1634     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1635     { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1636     { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1637     { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1638     { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1639     { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1640     { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1641     { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1642     { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1643     { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1644     { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1645     { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1646     { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1647     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1648     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1649     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1650     { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1651     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1652     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1653     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1654     { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1655     { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1656     { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1657     { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1658     { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1659     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1660     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1661     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1662     { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1663     { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1664     { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1665     { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1666     { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
1667     { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1668     { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1669     { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1670     { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1671     { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1672     { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1673     { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1674     { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1675     { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1676     { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1677     { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1678     { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1679     { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1680     { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1681     { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1682     { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1683     { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1684     { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1685     { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1686     { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1687     { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1688     { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1689     { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1690     { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1691     { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1692     { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1693     { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1694     { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1695     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1696     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1697     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1698     { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1699     { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 },
1700     { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 },
1701     { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 },
1702     { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 },
1703     { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 },
1704     { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 },
1705     { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 },
1706     { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 },
1707     { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 },
1708     { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 },
1709     { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 },
1710     { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 },
1711     { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 },
1712     { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 },
1713     { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 },
1714     { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 },
1715     { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 },
1716     { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 },
1717     { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 },
1718     { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 },
1719     { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 },
1720     { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 },
1721     { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 },
1722     { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 },
1723     { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 },
1724     { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 },
1725     { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 },
1726     { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 },
1727     { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 },
1728     { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 },
1729     { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 },
1730     { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 },
1731     { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 },
1732     { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 },
1733     { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 },
1734     { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 },
1735     { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 },
1736     { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 },
1737     { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 },
1738     { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 },
1739     { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 },
1740     { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 },
1741     { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 },
1742     { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 },
1743     { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 },
1744     { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 },
1745     { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 },
1746     { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 },
1747     { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 },
1748     { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 },
1749     { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 },
1750     { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 },
1751     { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 },
1752     { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 },
1753     { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 },
1754     { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 },
1755     { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 },
1756     { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 },
1757     { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 },
1758     { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 },
1759     { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 },
1760     { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 },
1761     { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 },
1762     { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 },
1763     { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 },
1764     { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 },
1765     { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 },
1766     { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 },
1767     { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 },
1768     { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 },
1769     { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 },
1770     { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 },
1771     { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 },
1772     { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 },
1773     { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 },
1774     { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 },
1775     { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 },
1776     { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 },
1777     { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 },
1778     { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 },
1779     { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 },
1780     { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 },
1781     { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 },
1782     { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 },
1783     { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 },
1784     { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 },
1785     { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 },
1786     { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 },
1787     { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 },
1788     { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 },
1789     { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 },
1790     { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 },
1791     { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 },
1792     { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 },
1793     { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 },
1794     { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 },
1795     { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 },
1796     { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 },
1797     { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 },
1798     { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 },
1799     { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 },
1800     { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 },
1801     { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 },
1802     { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 },
1803     { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 },
1804     { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 },
1805     { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 },
1806     { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 },
1807     { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 },
1808     { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 },
1809     { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 },
1810     { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 },
1811     { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 },
1812     { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 },
1813     { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 },
1814     { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 },
1815     { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 },
1816     { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 },
1817     { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 },
1818     { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 },
1819     { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 },
1820     { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 },
1821     { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 },
1822     { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 },
1823     { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 },
1824     { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 },
1825     { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 },
1826     { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 },
1827     { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 },
1828     { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 },
1829     { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 },
1830     { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 },
1831     { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 },
1832     { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 },
1833     { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 },
1834     { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 },
1835     { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 },
1836     { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 },
1837     { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 },
1838     { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 },
1839     { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 },
1840     { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 },
1841     { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 },
1842     { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 },
1843     { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 },
1844     { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 },
1845     { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 },
1846     { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 },
1847     { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 },
1848     { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 },
1849     { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 },
1850     { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 },
1851     { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 },
1852     { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 },
1853     { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 },
1854     { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 },
1855     { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 },
1856     { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 },
1857     { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 },
1858     { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 },
1859     { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 },
1860     { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 },
1861     { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 },
1862     { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 },
1863     { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 },
1864     { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 },
1865     { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 },
1866     { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 },
1867     { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 },
1868     { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 },
1869     { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 },
1870     { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 },
1871     { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 },
1872     { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 },
1873     { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 },
1874     { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 },
1875     { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 },
1876     { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 },
1877     { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 },
1878     { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 },
1879     { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 },
1880     { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 },
1881     { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 },
1882     { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 },
1883     { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 },
1884     { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 },
1885     { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 },
1886     { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 },
1887     { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 },
1888     { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 },
1889     { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 },
1890     { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 },
1891     { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 },
1892     { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 },
1893     { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 },
1894     { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 },
1895     { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 },
1896     { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 },
1897     { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 },
1898     { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 },
1899     { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 },
1900     { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 },
1901     { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 },
1902     { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 },
1903     { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 },
1904     { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 },
1905     { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 },
1906     { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 },
1907     { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 },
1908     { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 },
1909     { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 },
1910     { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 },
1911     { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 },
1912     { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 },
1913     { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 },
1914     { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 },
1915     { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 },
1916     { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 },
1917     { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 },
1918     { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 },
1919     { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 },
1920     { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 },
1921     { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 },
1922     { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 },
1923     { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 },
1924     { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 },
1925     { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 },
1926     { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 },
1927     { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 },
1928     { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 },
1929     { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 },
1930     { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 },
1931     { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 },
1932     { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 },
1933     { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 },
1934     { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 },
1935     { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 },
1936     { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 },
1937     { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 },
1938     { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 },
1939     { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 },
1940     { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 },
1941     { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 },
1942     { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 },
1943     { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 },
1944     { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 },
1945     { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 },
1946     { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 },
1947     { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 },
1948     { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 },
1949     { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 },
1950     { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 },
1951     { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 },
1952     { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 },
1953     { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 },
1954     { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 },
1955     { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 },
1956     { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 },
1957     { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 },
1958     { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 },
1959     { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 },
1960     { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 },
1961     { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 },
1962     { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 },
1963     { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 },
1964     { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 },
1965     { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 },
1966     { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 },
1967     { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 },
1968     { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 },
1969     { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 },
1970     { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 },
1971     { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 },
1972     { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 },
1973     { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 },
1974     { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 },
1975     { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 },
1976     { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 },
1977     { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 },
1978     { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 },
1979     { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 },
1980     { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 },
1981     { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 },
1982     { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 },
1983     { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 },
1984     { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 },
1985     { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 },
1986     { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 },
1987     { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 },
1988     { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 },
1989     { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 },
1990     { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 },
1991     { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 },
1992     { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 },
1993     { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 },
1994     { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 },
1995     { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 },
1996     { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 },
1997     { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 },
1998     { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 },
1999     { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 },
2000     { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 },
2001     { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 },
2002     { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 },
2003     { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 },
2004     { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 },
2005     { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 },
2006     { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 },
2007     { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 },
2008     { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 },
2009     { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 },
2010     { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 },
2011     { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 },
2012     { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 },
2013     { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 },
2014     { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 },
2015     { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 },
2016     { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 },
2017     { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 },
2018     { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 },
2019     { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 },
2020     { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 },
2021     { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 },
2022     { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 },
2023     { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 },
2024     { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 },
2025     { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 },
2026     { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 },
2027     { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 },
2028     { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 },
2029     { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 },
2030     { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 },
2031     { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 },
2032     { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 },
2033     { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 },
2034     { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 },
2035     { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 },
2036     { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 },
2037     { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 },
2038     { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 },
2039     { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 },
2040     { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 },
2041     { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 },
2042     { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 },
2043     { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 },
2044     { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 },
2045     { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 },
2046     { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 },
2047     { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 },
2048     { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 },
2049     { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 },
2050     { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 },
2051     { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 },
2052     { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 },
2053     { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 },
2054     { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 },
2055     { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 },
2056     { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 },
2057     { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 },
2058     { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 },
2059     { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 },
2060     { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 },
2061     { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 },
2062     { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 },
2063     { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 },
2064     { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 },
2065     { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
2066     { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
2067     { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
2068     { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }
2069 };
2070
2071 /* CSR names */
2072
2073 static const char *csr_name(int csrno)
2074 {
2075     switch (csrno) {
2076     case 0x0000: return "ustatus";
2077     case 0x0001: return "fflags";
2078     case 0x0002: return "frm";
2079     case 0x0003: return "fcsr";
2080     case 0x0004: return "uie";
2081     case 0x0005: return "utvec";
2082     case 0x0008: return "vstart";
2083     case 0x0009: return "vxsat";
2084     case 0x000a: return "vxrm";
2085     case 0x000f: return "vcsr";
2086     case 0x0015: return "seed";
2087     case 0x0040: return "uscratch";
2088     case 0x0041: return "uepc";
2089     case 0x0042: return "ucause";
2090     case 0x0043: return "utval";
2091     case 0x0044: return "uip";
2092     case 0x0100: return "sstatus";
2093     case 0x0104: return "sie";
2094     case 0x0105: return "stvec";
2095     case 0x0106: return "scounteren";
2096     case 0x0140: return "sscratch";
2097     case 0x0141: return "sepc";
2098     case 0x0142: return "scause";
2099     case 0x0143: return "stval";
2100     case 0x0144: return "sip";
2101     case 0x0180: return "satp";
2102     case 0x0200: return "hstatus";
2103     case 0x0202: return "hedeleg";
2104     case 0x0203: return "hideleg";
2105     case 0x0204: return "hie";
2106     case 0x0205: return "htvec";
2107     case 0x0240: return "hscratch";
2108     case 0x0241: return "hepc";
2109     case 0x0242: return "hcause";
2110     case 0x0243: return "hbadaddr";
2111     case 0x0244: return "hip";
2112     case 0x0300: return "mstatus";
2113     case 0x0301: return "misa";
2114     case 0x0302: return "medeleg";
2115     case 0x0303: return "mideleg";
2116     case 0x0304: return "mie";
2117     case 0x0305: return "mtvec";
2118     case 0x0306: return "mcounteren";
2119     case 0x0320: return "mucounteren";
2120     case 0x0321: return "mscounteren";
2121     case 0x0322: return "mhcounteren";
2122     case 0x0323: return "mhpmevent3";
2123     case 0x0324: return "mhpmevent4";
2124     case 0x0325: return "mhpmevent5";
2125     case 0x0326: return "mhpmevent6";
2126     case 0x0327: return "mhpmevent7";
2127     case 0x0328: return "mhpmevent8";
2128     case 0x0329: return "mhpmevent9";
2129     case 0x032a: return "mhpmevent10";
2130     case 0x032b: return "mhpmevent11";
2131     case 0x032c: return "mhpmevent12";
2132     case 0x032d: return "mhpmevent13";
2133     case 0x032e: return "mhpmevent14";
2134     case 0x032f: return "mhpmevent15";
2135     case 0x0330: return "mhpmevent16";
2136     case 0x0331: return "mhpmevent17";
2137     case 0x0332: return "mhpmevent18";
2138     case 0x0333: return "mhpmevent19";
2139     case 0x0334: return "mhpmevent20";
2140     case 0x0335: return "mhpmevent21";
2141     case 0x0336: return "mhpmevent22";
2142     case 0x0337: return "mhpmevent23";
2143     case 0x0338: return "mhpmevent24";
2144     case 0x0339: return "mhpmevent25";
2145     case 0x033a: return "mhpmevent26";
2146     case 0x033b: return "mhpmevent27";
2147     case 0x033c: return "mhpmevent28";
2148     case 0x033d: return "mhpmevent29";
2149     case 0x033e: return "mhpmevent30";
2150     case 0x033f: return "mhpmevent31";
2151     case 0x0340: return "mscratch";
2152     case 0x0341: return "mepc";
2153     case 0x0342: return "mcause";
2154     case 0x0343: return "mtval";
2155     case 0x0344: return "mip";
2156     case 0x0380: return "mbase";
2157     case 0x0381: return "mbound";
2158     case 0x0382: return "mibase";
2159     case 0x0383: return "mibound";
2160     case 0x0384: return "mdbase";
2161     case 0x0385: return "mdbound";
2162     case 0x03a0: return "pmpcfg3";
2163     case 0x03b0: return "pmpaddr0";
2164     case 0x03b1: return "pmpaddr1";
2165     case 0x03b2: return "pmpaddr2";
2166     case 0x03b3: return "pmpaddr3";
2167     case 0x03b4: return "pmpaddr4";
2168     case 0x03b5: return "pmpaddr5";
2169     case 0x03b6: return "pmpaddr6";
2170     case 0x03b7: return "pmpaddr7";
2171     case 0x03b8: return "pmpaddr8";
2172     case 0x03b9: return "pmpaddr9";
2173     case 0x03ba: return "pmpaddr10";
2174     case 0x03bb: return "pmpaddr11";
2175     case 0x03bc: return "pmpaddr12";
2176     case 0x03bd: return "pmpaddr14";
2177     case 0x03be: return "pmpaddr13";
2178     case 0x03bf: return "pmpaddr15";
2179     case 0x0780: return "mtohost";
2180     case 0x0781: return "mfromhost";
2181     case 0x0782: return "mreset";
2182     case 0x0783: return "mipi";
2183     case 0x0784: return "miobase";
2184     case 0x07a0: return "tselect";
2185     case 0x07a1: return "tdata1";
2186     case 0x07a2: return "tdata2";
2187     case 0x07a3: return "tdata3";
2188     case 0x07b0: return "dcsr";
2189     case 0x07b1: return "dpc";
2190     case 0x07b2: return "dscratch";
2191     case 0x0b00: return "mcycle";
2192     case 0x0b01: return "mtime";
2193     case 0x0b02: return "minstret";
2194     case 0x0b03: return "mhpmcounter3";
2195     case 0x0b04: return "mhpmcounter4";
2196     case 0x0b05: return "mhpmcounter5";
2197     case 0x0b06: return "mhpmcounter6";
2198     case 0x0b07: return "mhpmcounter7";
2199     case 0x0b08: return "mhpmcounter8";
2200     case 0x0b09: return "mhpmcounter9";
2201     case 0x0b0a: return "mhpmcounter10";
2202     case 0x0b0b: return "mhpmcounter11";
2203     case 0x0b0c: return "mhpmcounter12";
2204     case 0x0b0d: return "mhpmcounter13";
2205     case 0x0b0e: return "mhpmcounter14";
2206     case 0x0b0f: return "mhpmcounter15";
2207     case 0x0b10: return "mhpmcounter16";
2208     case 0x0b11: return "mhpmcounter17";
2209     case 0x0b12: return "mhpmcounter18";
2210     case 0x0b13: return "mhpmcounter19";
2211     case 0x0b14: return "mhpmcounter20";
2212     case 0x0b15: return "mhpmcounter21";
2213     case 0x0b16: return "mhpmcounter22";
2214     case 0x0b17: return "mhpmcounter23";
2215     case 0x0b18: return "mhpmcounter24";
2216     case 0x0b19: return "mhpmcounter25";
2217     case 0x0b1a: return "mhpmcounter26";
2218     case 0x0b1b: return "mhpmcounter27";
2219     case 0x0b1c: return "mhpmcounter28";
2220     case 0x0b1d: return "mhpmcounter29";
2221     case 0x0b1e: return "mhpmcounter30";
2222     case 0x0b1f: return "mhpmcounter31";
2223     case 0x0b80: return "mcycleh";
2224     case 0x0b81: return "mtimeh";
2225     case 0x0b82: return "minstreth";
2226     case 0x0b83: return "mhpmcounter3h";
2227     case 0x0b84: return "mhpmcounter4h";
2228     case 0x0b85: return "mhpmcounter5h";
2229     case 0x0b86: return "mhpmcounter6h";
2230     case 0x0b87: return "mhpmcounter7h";
2231     case 0x0b88: return "mhpmcounter8h";
2232     case 0x0b89: return "mhpmcounter9h";
2233     case 0x0b8a: return "mhpmcounter10h";
2234     case 0x0b8b: return "mhpmcounter11h";
2235     case 0x0b8c: return "mhpmcounter12h";
2236     case 0x0b8d: return "mhpmcounter13h";
2237     case 0x0b8e: return "mhpmcounter14h";
2238     case 0x0b8f: return "mhpmcounter15h";
2239     case 0x0b90: return "mhpmcounter16h";
2240     case 0x0b91: return "mhpmcounter17h";
2241     case 0x0b92: return "mhpmcounter18h";
2242     case 0x0b93: return "mhpmcounter19h";
2243     case 0x0b94: return "mhpmcounter20h";
2244     case 0x0b95: return "mhpmcounter21h";
2245     case 0x0b96: return "mhpmcounter22h";
2246     case 0x0b97: return "mhpmcounter23h";
2247     case 0x0b98: return "mhpmcounter24h";
2248     case 0x0b99: return "mhpmcounter25h";
2249     case 0x0b9a: return "mhpmcounter26h";
2250     case 0x0b9b: return "mhpmcounter27h";
2251     case 0x0b9c: return "mhpmcounter28h";
2252     case 0x0b9d: return "mhpmcounter29h";
2253     case 0x0b9e: return "mhpmcounter30h";
2254     case 0x0b9f: return "mhpmcounter31h";
2255     case 0x0c00: return "cycle";
2256     case 0x0c01: return "time";
2257     case 0x0c02: return "instret";
2258     case 0x0c20: return "vl";
2259     case 0x0c21: return "vtype";
2260     case 0x0c22: return "vlenb";
2261     case 0x0c80: return "cycleh";
2262     case 0x0c81: return "timeh";
2263     case 0x0c82: return "instreth";
2264     case 0x0d00: return "scycle";
2265     case 0x0d01: return "stime";
2266     case 0x0d02: return "sinstret";
2267     case 0x0d80: return "scycleh";
2268     case 0x0d81: return "stimeh";
2269     case 0x0d82: return "sinstreth";
2270     case 0x0e00: return "hcycle";
2271     case 0x0e01: return "htime";
2272     case 0x0e02: return "hinstret";
2273     case 0x0e80: return "hcycleh";
2274     case 0x0e81: return "htimeh";
2275     case 0x0e82: return "hinstreth";
2276     case 0x0f11: return "mvendorid";
2277     case 0x0f12: return "marchid";
2278     case 0x0f13: return "mimpid";
2279     case 0x0f14: return "mhartid";
2280     default: return NULL;
2281     }
2282 }
2283
2284 /* decode opcode */
2285
2286 static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2287 {
2288     rv_inst inst = dec->inst;
2289     rv_opcode op = rv_op_illegal;
2290     switch (((inst >> 0) & 0b11)) {
2291     case 0:
2292         switch (((inst >> 13) & 0b111)) {
2293         case 0: op = rv_op_c_addi4spn; break;
2294         case 1:
2295             if (isa == rv128) {
2296                 op = rv_op_c_lq;
2297             } else {
2298                 op = rv_op_c_fld;
2299             }
2300             break;
2301         case 2: op = rv_op_c_lw; break;
2302         case 3:
2303             if (isa == rv32) {
2304                 op = rv_op_c_flw;
2305             } else {
2306                 op = rv_op_c_ld;
2307             }
2308             break;
2309         case 5:
2310             if (isa == rv128) {
2311                 op = rv_op_c_sq;
2312             } else {
2313                 op = rv_op_c_fsd;
2314             }
2315             break;
2316         case 6: op = rv_op_c_sw; break;
2317         case 7:
2318             if (isa == rv32) {
2319                 op = rv_op_c_fsw;
2320             } else {
2321                 op = rv_op_c_sd;
2322             }
2323             break;
2324         }
2325         break;
2326     case 1:
2327         switch (((inst >> 13) & 0b111)) {
2328         case 0:
2329             switch (((inst >> 2) & 0b11111111111)) {
2330             case 0: op = rv_op_c_nop; break;
2331             default: op = rv_op_c_addi; break;
2332             }
2333             break;
2334         case 1:
2335             if (isa == rv32) {
2336                 op = rv_op_c_jal;
2337             } else {
2338                 op = rv_op_c_addiw;
2339             }
2340             break;
2341         case 2: op = rv_op_c_li; break;
2342         case 3:
2343             switch (((inst >> 7) & 0b11111)) {
2344             case 2: op = rv_op_c_addi16sp; break;
2345             default: op = rv_op_c_lui; break;
2346             }
2347             break;
2348         case 4:
2349             switch (((inst >> 10) & 0b11)) {
2350             case 0:
2351                 op = rv_op_c_srli;
2352                 break;
2353             case 1:
2354                 op = rv_op_c_srai;
2355                 break;
2356             case 2: op = rv_op_c_andi; break;
2357             case 3:
2358                 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
2359                 case 0: op = rv_op_c_sub; break;
2360                 case 1: op = rv_op_c_xor; break;
2361                 case 2: op = rv_op_c_or; break;
2362                 case 3: op = rv_op_c_and; break;
2363                 case 4: op = rv_op_c_subw; break;
2364                 case 5: op = rv_op_c_addw; break;
2365                 }
2366                 break;
2367             }
2368             break;
2369         case 5: op = rv_op_c_j; break;
2370         case 6: op = rv_op_c_beqz; break;
2371         case 7: op = rv_op_c_bnez; break;
2372         }
2373         break;
2374     case 2:
2375         switch (((inst >> 13) & 0b111)) {
2376         case 0:
2377             op = rv_op_c_slli;
2378             break;
2379         case 1:
2380             if (isa == rv128) {
2381                 op = rv_op_c_lqsp;
2382             } else {
2383                 op = rv_op_c_fldsp;
2384             }
2385             break;
2386         case 2: op = rv_op_c_lwsp; break;
2387         case 3:
2388             if (isa == rv32) {
2389                 op = rv_op_c_flwsp;
2390             } else {
2391                 op = rv_op_c_ldsp;
2392             }
2393             break;
2394         case 4:
2395             switch (((inst >> 12) & 0b1)) {
2396             case 0:
2397                 switch (((inst >> 2) & 0b11111)) {
2398                 case 0: op = rv_op_c_jr; break;
2399                 default: op = rv_op_c_mv; break;
2400                 }
2401                 break;
2402             case 1:
2403                 switch (((inst >> 2) & 0b11111)) {
2404                 case 0:
2405                     switch (((inst >> 7) & 0b11111)) {
2406                     case 0: op = rv_op_c_ebreak; break;
2407                     default: op = rv_op_c_jalr; break;
2408                     }
2409                     break;
2410                 default: op = rv_op_c_add; break;
2411                 }
2412                 break;
2413             }
2414             break;
2415         case 5:
2416             if (isa == rv128) {
2417                 op = rv_op_c_sqsp;
2418             } else {
2419                 op = rv_op_c_fsdsp;
2420             }
2421             break;
2422         case 6: op = rv_op_c_swsp; break;
2423         case 7:
2424             if (isa == rv32) {
2425                 op = rv_op_c_fswsp;
2426             } else {
2427                 op = rv_op_c_sdsp;
2428             }
2429             break;
2430         }
2431         break;
2432     case 3:
2433         switch (((inst >> 2) & 0b11111)) {
2434         case 0:
2435             switch (((inst >> 12) & 0b111)) {
2436             case 0: op = rv_op_lb; break;
2437             case 1: op = rv_op_lh; break;
2438             case 2: op = rv_op_lw; break;
2439             case 3: op = rv_op_ld; break;
2440             case 4: op = rv_op_lbu; break;
2441             case 5: op = rv_op_lhu; break;
2442             case 6: op = rv_op_lwu; break;
2443             case 7: op = rv_op_ldu; break;
2444             }
2445             break;
2446         case 1:
2447             switch (((inst >> 12) & 0b111)) {
2448             case 0:
2449                 switch (((inst >> 20) & 0b111111111111)) {
2450                 case 40: op = rv_op_vl1re8_v; break;
2451                 case 552: op = rv_op_vl2re8_v; break;
2452                 case 1576: op = rv_op_vl4re8_v; break;
2453                 case 3624: op = rv_op_vl8re8_v; break;
2454                 }
2455                 switch (((inst >> 26) & 0b111)) {
2456                 case 0:
2457                     switch (((inst >> 20) & 0b11111)) {
2458                     case 0: op = rv_op_vle8_v; break;
2459                     case 11: op = rv_op_vlm_v; break;
2460                     case 16: op = rv_op_vle8ff_v; break;
2461                     }
2462                     break;
2463                 case 1: op = rv_op_vluxei8_v; break;
2464                 case 2: op = rv_op_vlse8_v; break;
2465                 case 3: op = rv_op_vloxei8_v; break;
2466                 }
2467                 break;
2468             case 2: op = rv_op_flw; break;
2469             case 3: op = rv_op_fld; break;
2470             case 4: op = rv_op_flq; break;
2471             case 5:
2472                 switch (((inst >> 20) & 0b111111111111)) {
2473                 case 40: op = rv_op_vl1re16_v; break;
2474                 case 552: op = rv_op_vl2re16_v; break;
2475                 case 1576: op = rv_op_vl4re16_v; break;
2476                 case 3624: op = rv_op_vl8re16_v; break;
2477                 }
2478                 switch (((inst >> 26) & 0b111)) {
2479                 case 0:
2480                     switch (((inst >> 20) & 0b11111)) {
2481                     case 0: op = rv_op_vle16_v; break;
2482                     case 16: op = rv_op_vle16ff_v; break;
2483                     }
2484                     break;
2485                 case 1: op = rv_op_vluxei16_v; break;
2486                 case 2: op = rv_op_vlse16_v; break;
2487                 case 3: op = rv_op_vloxei16_v; break;
2488                 }
2489                 break;
2490             case 6:
2491                 switch (((inst >> 20) & 0b111111111111)) {
2492                 case 40: op = rv_op_vl1re32_v; break;
2493                 case 552: op = rv_op_vl2re32_v; break;
2494                 case 1576: op = rv_op_vl4re32_v; break;
2495                 case 3624: op = rv_op_vl8re32_v; break;
2496                 }
2497                 switch (((inst >> 26) & 0b111)) {
2498                 case 0:
2499                     switch (((inst >> 20) & 0b11111)) {
2500                     case 0: op = rv_op_vle32_v; break;
2501                     case 16: op = rv_op_vle32ff_v; break;
2502                     }
2503                     break;
2504                 case 1: op = rv_op_vluxei32_v; break;
2505                 case 2: op = rv_op_vlse32_v; break;
2506                 case 3: op = rv_op_vloxei32_v; break;
2507                 }
2508                 break;
2509             case 7:
2510                 switch (((inst >> 20) & 0b111111111111)) {
2511                 case 40: op = rv_op_vl1re64_v; break;
2512                 case 552: op = rv_op_vl2re64_v; break;
2513                 case 1576: op = rv_op_vl4re64_v; break;
2514                 case 3624: op = rv_op_vl8re64_v; break;
2515                 }
2516                 switch (((inst >> 26) & 0b111)) {
2517                 case 0:
2518                     switch (((inst >> 20) & 0b11111)) {
2519                     case 0: op = rv_op_vle64_v; break;
2520                     case 16: op = rv_op_vle64ff_v; break;
2521                     }
2522                     break;
2523                 case 1: op = rv_op_vluxei64_v; break;
2524                 case 2: op = rv_op_vlse64_v; break;
2525                 case 3: op = rv_op_vloxei64_v; break;
2526                 }
2527                 break;
2528             }
2529             break;
2530         case 3:
2531             switch (((inst >> 12) & 0b111)) {
2532             case 0: op = rv_op_fence; break;
2533             case 1: op = rv_op_fence_i; break;
2534             case 2: op = rv_op_lq; break;
2535             }
2536             break;
2537         case 4:
2538             switch (((inst >> 12) & 0b111)) {
2539             case 0: op = rv_op_addi; break;
2540             case 1:
2541                 switch (((inst >> 27) & 0b11111)) {
2542                 case 0b00000: op = rv_op_slli; break;
2543                 case 0b00001:
2544                     switch (((inst >> 20) & 0b1111111)) {
2545                     case 0b0001111: op = rv_op_zip; break;
2546                     }
2547                     break;
2548                 case 0b00010:
2549                     switch (((inst >> 20) & 0b1111111)) {
2550                     case 0b0000000: op = rv_op_sha256sum0; break;
2551                     case 0b0000001: op = rv_op_sha256sum1; break;
2552                     case 0b0000010: op = rv_op_sha256sig0; break;
2553                     case 0b0000011: op = rv_op_sha256sig1; break;
2554                     case 0b0000100: op = rv_op_sha512sum0; break;
2555                     case 0b0000101: op = rv_op_sha512sum1; break;
2556                     case 0b0000110: op = rv_op_sha512sig0; break;
2557                     case 0b0000111: op = rv_op_sha512sig1; break;
2558                     case 0b0001000: op = rv_op_sm3p0; break;
2559                     case 0b0001001: op = rv_op_sm3p1; break;
2560                     }
2561                     break;
2562                 case 0b00101: op = rv_op_bseti; break;
2563                 case 0b00110:
2564                     switch (((inst >> 20) & 0b1111111)) {
2565                     case 0b0000000: op = rv_op_aes64im; break;
2566                     default:
2567                         if (((inst >> 24) & 0b0111) == 0b001) {
2568                             op = rv_op_aes64ks1i;
2569                         }
2570                         break;
2571                      }
2572                      break;
2573                 case 0b01001: op = rv_op_bclri; break;
2574                 case 0b01101: op = rv_op_binvi; break;
2575                 case 0b01100:
2576                     switch (((inst >> 20) & 0b1111111)) {
2577                     case 0b0000000: op = rv_op_clz; break;
2578                     case 0b0000001: op = rv_op_ctz; break;
2579                     case 0b0000010: op = rv_op_cpop; break;
2580                       /* 0b0000011 */
2581                     case 0b0000100: op = rv_op_sext_b; break;
2582                     case 0b0000101: op = rv_op_sext_h; break;
2583                     }
2584                     break;
2585                 }
2586                 break;
2587             case 2: op = rv_op_slti; break;
2588             case 3: op = rv_op_sltiu; break;
2589             case 4: op = rv_op_xori; break;
2590             case 5:
2591                 switch (((inst >> 27) & 0b11111)) {
2592                 case 0b00000: op = rv_op_srli; break;
2593                 case 0b00001:
2594                     switch (((inst >> 20) & 0b1111111)) {
2595                     case 0b0001111: op = rv_op_unzip; break;
2596                     }
2597                     break;
2598                 case 0b00101: op = rv_op_orc_b; break;
2599                 case 0b01000: op = rv_op_srai; break;
2600                 case 0b01001: op = rv_op_bexti; break;
2601                 case 0b01100: op = rv_op_rori; break;
2602                 case 0b01101:
2603                     switch ((inst >> 20) & 0b1111111) {
2604                     case 0b0011000: op = rv_op_rev8; break;
2605                     case 0b0111000: op = rv_op_rev8; break;
2606                     case 0b0000111: op = rv_op_brev8; break;
2607                     }
2608                     break;
2609                 }
2610                 break;
2611             case 6: op = rv_op_ori; break;
2612             case 7: op = rv_op_andi; break;
2613             }
2614             break;
2615         case 5: op = rv_op_auipc; break;
2616         case 6:
2617             switch (((inst >> 12) & 0b111)) {
2618             case 0: op = rv_op_addiw; break;
2619             case 1:
2620                 switch (((inst >> 25) & 0b1111111)) {
2621                 case 0: op = rv_op_slliw; break;
2622                 case 4: op = rv_op_slli_uw; break;
2623                 case 48:
2624                     switch ((inst >> 20) & 0b11111) {
2625                     case 0b00000: op = rv_op_clzw; break;
2626                     case 0b00001: op = rv_op_ctzw; break;
2627                     case 0b00010: op = rv_op_cpopw; break;
2628                     }
2629                     break;
2630                 }
2631                 break;
2632             case 5:
2633                 switch (((inst >> 25) & 0b1111111)) {
2634                 case 0: op = rv_op_srliw; break;
2635                 case 32: op = rv_op_sraiw; break;
2636                 case 48: op = rv_op_roriw; break;
2637                 }
2638                 break;
2639             }
2640             break;
2641         case 8:
2642             switch (((inst >> 12) & 0b111)) {
2643             case 0: op = rv_op_sb; break;
2644             case 1: op = rv_op_sh; break;
2645             case 2: op = rv_op_sw; break;
2646             case 3: op = rv_op_sd; break;
2647             case 4: op = rv_op_sq; break;
2648             }
2649             break;
2650         case 9:
2651             switch (((inst >> 12) & 0b111)) {
2652             case 0:
2653                 switch (((inst >> 20) & 0b111111111111)) {
2654                 case 40: op = rv_op_vs1r_v; break;
2655                 case 552: op = rv_op_vs2r_v; break;
2656                 case 1576: op = rv_op_vs4r_v; break;
2657                 case 3624: op = rv_op_vs8r_v; break;
2658                 }
2659                 switch (((inst >> 26) & 0b111)) {
2660                 case 0:
2661                     switch (((inst >> 20) & 0b11111)) {
2662                     case 0: op = rv_op_vse8_v; break;
2663                     case 11: op = rv_op_vsm_v; break;
2664                     }
2665                     break;
2666                 case 1: op = rv_op_vsuxei8_v; break;
2667                 case 2: op = rv_op_vsse8_v; break;
2668                 case 3: op = rv_op_vsoxei8_v; break;
2669                 }
2670                 break;
2671             case 2: op = rv_op_fsw; break;
2672             case 3: op = rv_op_fsd; break;
2673             case 4: op = rv_op_fsq; break;
2674             case 5:
2675                 switch (((inst >> 26) & 0b111)) {
2676                 case 0:
2677                     switch (((inst >> 20) & 0b11111)) {
2678                     case 0: op = rv_op_vse16_v; break;
2679                     }
2680                     break;
2681                 case 1: op = rv_op_vsuxei16_v; break;
2682                 case 2: op = rv_op_vsse16_v; break;
2683                 case 3: op = rv_op_vsoxei16_v; break;
2684                 }
2685                 break;
2686             case 6:
2687                 switch (((inst >> 26) & 0b111)) {
2688                 case 0:
2689                     switch (((inst >> 20) & 0b11111)) {
2690                     case 0: op = rv_op_vse32_v; break;
2691                     }
2692                     break;
2693                 case 1: op = rv_op_vsuxei32_v; break;
2694                 case 2: op = rv_op_vsse32_v; break;
2695                 case 3: op = rv_op_vsoxei32_v; break;
2696                 }
2697                 break;
2698             case 7:
2699                 switch (((inst >> 26) & 0b111)) {
2700                 case 0:
2701                     switch (((inst >> 20) & 0b11111)) {
2702                     case 0: op = rv_op_vse64_v; break;
2703                     }
2704                     break;
2705                 case 1: op = rv_op_vsuxei64_v; break;
2706                 case 2: op = rv_op_vsse64_v; break;
2707                 case 3: op = rv_op_vsoxei64_v; break;
2708                 }
2709                 break;
2710             }
2711             break;
2712         case 11:
2713             switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
2714             case 2: op = rv_op_amoadd_w; break;
2715             case 3: op = rv_op_amoadd_d; break;
2716             case 4: op = rv_op_amoadd_q; break;
2717             case 10: op = rv_op_amoswap_w; break;
2718             case 11: op = rv_op_amoswap_d; break;
2719             case 12: op = rv_op_amoswap_q; break;
2720             case 18:
2721                 switch (((inst >> 20) & 0b11111)) {
2722                 case 0: op = rv_op_lr_w; break;
2723                 }
2724                 break;
2725             case 19:
2726                 switch (((inst >> 20) & 0b11111)) {
2727                 case 0: op = rv_op_lr_d; break;
2728                 }
2729                 break;
2730             case 20:
2731                 switch (((inst >> 20) & 0b11111)) {
2732                 case 0: op = rv_op_lr_q; break;
2733                 }
2734                 break;
2735             case 26: op = rv_op_sc_w; break;
2736             case 27: op = rv_op_sc_d; break;
2737             case 28: op = rv_op_sc_q; break;
2738             case 34: op = rv_op_amoxor_w; break;
2739             case 35: op = rv_op_amoxor_d; break;
2740             case 36: op = rv_op_amoxor_q; break;
2741             case 66: op = rv_op_amoor_w; break;
2742             case 67: op = rv_op_amoor_d; break;
2743             case 68: op = rv_op_amoor_q; break;
2744             case 98: op = rv_op_amoand_w; break;
2745             case 99: op = rv_op_amoand_d; break;
2746             case 100: op = rv_op_amoand_q; break;
2747             case 130: op = rv_op_amomin_w; break;
2748             case 131: op = rv_op_amomin_d; break;
2749             case 132: op = rv_op_amomin_q; break;
2750             case 162: op = rv_op_amomax_w; break;
2751             case 163: op = rv_op_amomax_d; break;
2752             case 164: op = rv_op_amomax_q; break;
2753             case 194: op = rv_op_amominu_w; break;
2754             case 195: op = rv_op_amominu_d; break;
2755             case 196: op = rv_op_amominu_q; break;
2756             case 226: op = rv_op_amomaxu_w; break;
2757             case 227: op = rv_op_amomaxu_d; break;
2758             case 228: op = rv_op_amomaxu_q; break;
2759             }
2760             break;
2761         case 12:
2762             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
2763             case 0: op = rv_op_add; break;
2764             case 1: op = rv_op_sll; break;
2765             case 2: op = rv_op_slt; break;
2766             case 3: op = rv_op_sltu; break;
2767             case 4: op = rv_op_xor; break;
2768             case 5: op = rv_op_srl; break;
2769             case 6: op = rv_op_or; break;
2770             case 7: op = rv_op_and; break;
2771             case 8: op = rv_op_mul; break;
2772             case 9: op = rv_op_mulh; break;
2773             case 10: op = rv_op_mulhsu; break;
2774             case 11: op = rv_op_mulhu; break;
2775             case 12: op = rv_op_div; break;
2776             case 13: op = rv_op_divu; break;
2777             case 14: op = rv_op_rem; break;
2778             case 15: op = rv_op_remu; break;
2779             case 36:
2780                 switch ((inst >> 20) & 0b11111) {
2781                 case 0: op = rv_op_zext_h; break;
2782                 default: op = rv_op_pack; break;
2783                 }
2784                 break;
2785             case 39: op = rv_op_packh; break;
2786
2787             case 41: op = rv_op_clmul; break;
2788             case 42: op = rv_op_clmulr; break;
2789             case 43: op = rv_op_clmulh; break;
2790             case 44: op = rv_op_min; break;
2791             case 45: op = rv_op_minu; break;
2792             case 46: op = rv_op_max; break;
2793             case 47: op = rv_op_maxu; break;
2794             case 130: op = rv_op_sh1add; break;
2795             case 132: op = rv_op_sh2add; break;
2796             case 134: op = rv_op_sh3add; break;
2797             case 161: op = rv_op_bset; break;
2798             case 162: op = rv_op_xperm4; break;
2799             case 164: op = rv_op_xperm8; break;
2800             case 200: op = rv_op_aes64es; break;
2801             case 216: op = rv_op_aes64esm; break;
2802             case 232: op = rv_op_aes64ds; break;
2803             case 248: op = rv_op_aes64dsm; break;
2804             case 256: op = rv_op_sub; break;
2805             case 260: op = rv_op_xnor; break;
2806             case 261: op = rv_op_sra; break;
2807             case 262: op = rv_op_orn; break;
2808             case 263: op = rv_op_andn; break;
2809             case 289: op = rv_op_bclr; break;
2810             case 293: op = rv_op_bext; break;
2811             case 320: op = rv_op_sha512sum0r; break;
2812             case 328: op = rv_op_sha512sum1r; break;
2813             case 336: op = rv_op_sha512sig0l; break;
2814             case 344: op = rv_op_sha512sig1l; break;
2815             case 368: op = rv_op_sha512sig0h; break;
2816             case 376: op = rv_op_sha512sig1h; break;
2817             case 385: op = rv_op_rol; break;
2818             case 389: op = rv_op_ror; break;
2819             case 417: op = rv_op_binv; break;
2820             case 504: op = rv_op_aes64ks2; break;
2821             }
2822             switch ((inst >> 25) & 0b0011111) {
2823             case 17: op = rv_op_aes32esi; break;
2824             case 19: op = rv_op_aes32esmi; break;
2825             case 21: op = rv_op_aes32dsi; break;
2826             case 23: op = rv_op_aes32dsmi; break;
2827             case 24: op = rv_op_sm4ed; break;
2828             case 26: op = rv_op_sm4ks; break;
2829             }
2830             break;
2831         case 13: op = rv_op_lui; break;
2832         case 14:
2833             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
2834             case 0: op = rv_op_addw; break;
2835             case 1: op = rv_op_sllw; break;
2836             case 5: op = rv_op_srlw; break;
2837             case 8: op = rv_op_mulw; break;
2838             case 12: op = rv_op_divw; break;
2839             case 13: op = rv_op_divuw; break;
2840             case 14: op = rv_op_remw; break;
2841             case 15: op = rv_op_remuw; break;
2842             case 32: op = rv_op_add_uw; break;
2843             case 36:
2844                 switch ((inst >> 20) & 0b11111) {
2845                 case 0: op = rv_op_zext_h; break;
2846                 default: op = rv_op_packw; break;
2847                 }
2848                 break;
2849             case 130: op = rv_op_sh1add_uw; break;
2850             case 132: op = rv_op_sh2add_uw; break;
2851             case 134: op = rv_op_sh3add_uw; break;
2852             case 256: op = rv_op_subw; break;
2853             case 261: op = rv_op_sraw; break;
2854             case 385: op = rv_op_rolw; break;
2855             case 389: op = rv_op_rorw; break;
2856             }
2857             break;
2858         case 16:
2859             switch (((inst >> 25) & 0b11)) {
2860             case 0: op = rv_op_fmadd_s; break;
2861             case 1: op = rv_op_fmadd_d; break;
2862             case 3: op = rv_op_fmadd_q; break;
2863             }
2864             break;
2865         case 17:
2866             switch (((inst >> 25) & 0b11)) {
2867             case 0: op = rv_op_fmsub_s; break;
2868             case 1: op = rv_op_fmsub_d; break;
2869             case 3: op = rv_op_fmsub_q; break;
2870             }
2871             break;
2872         case 18:
2873             switch (((inst >> 25) & 0b11)) {
2874             case 0: op = rv_op_fnmsub_s; break;
2875             case 1: op = rv_op_fnmsub_d; break;
2876             case 3: op = rv_op_fnmsub_q; break;
2877             }
2878             break;
2879         case 19:
2880             switch (((inst >> 25) & 0b11)) {
2881             case 0: op = rv_op_fnmadd_s; break;
2882             case 1: op = rv_op_fnmadd_d; break;
2883             case 3: op = rv_op_fnmadd_q; break;
2884             }
2885             break;
2886         case 20:
2887             switch (((inst >> 25) & 0b1111111)) {
2888             case 0: op = rv_op_fadd_s; break;
2889             case 1: op = rv_op_fadd_d; break;
2890             case 3: op = rv_op_fadd_q; break;
2891             case 4: op = rv_op_fsub_s; break;
2892             case 5: op = rv_op_fsub_d; break;
2893             case 7: op = rv_op_fsub_q; break;
2894             case 8: op = rv_op_fmul_s; break;
2895             case 9: op = rv_op_fmul_d; break;
2896             case 11: op = rv_op_fmul_q; break;
2897             case 12: op = rv_op_fdiv_s; break;
2898             case 13: op = rv_op_fdiv_d; break;
2899             case 15: op = rv_op_fdiv_q; break;
2900             case 16:
2901                 switch (((inst >> 12) & 0b111)) {
2902                 case 0: op = rv_op_fsgnj_s; break;
2903                 case 1: op = rv_op_fsgnjn_s; break;
2904                 case 2: op = rv_op_fsgnjx_s; break;
2905                 }
2906                 break;
2907             case 17:
2908                 switch (((inst >> 12) & 0b111)) {
2909                 case 0: op = rv_op_fsgnj_d; break;
2910                 case 1: op = rv_op_fsgnjn_d; break;
2911                 case 2: op = rv_op_fsgnjx_d; break;
2912                 }
2913                 break;
2914             case 19:
2915                 switch (((inst >> 12) & 0b111)) {
2916                 case 0: op = rv_op_fsgnj_q; break;
2917                 case 1: op = rv_op_fsgnjn_q; break;
2918                 case 2: op = rv_op_fsgnjx_q; break;
2919                 }
2920                 break;
2921             case 20:
2922                 switch (((inst >> 12) & 0b111)) {
2923                 case 0: op = rv_op_fmin_s; break;
2924                 case 1: op = rv_op_fmax_s; break;
2925                 }
2926                 break;
2927             case 21:
2928                 switch (((inst >> 12) & 0b111)) {
2929                 case 0: op = rv_op_fmin_d; break;
2930                 case 1: op = rv_op_fmax_d; break;
2931                 }
2932                 break;
2933             case 23:
2934                 switch (((inst >> 12) & 0b111)) {
2935                 case 0: op = rv_op_fmin_q; break;
2936                 case 1: op = rv_op_fmax_q; break;
2937                 }
2938                 break;
2939             case 32:
2940                 switch (((inst >> 20) & 0b11111)) {
2941                 case 1: op = rv_op_fcvt_s_d; break;
2942                 case 3: op = rv_op_fcvt_s_q; break;
2943                 }
2944                 break;
2945             case 33:
2946                 switch (((inst >> 20) & 0b11111)) {
2947                 case 0: op = rv_op_fcvt_d_s; break;
2948                 case 3: op = rv_op_fcvt_d_q; break;
2949                 }
2950                 break;
2951             case 35:
2952                 switch (((inst >> 20) & 0b11111)) {
2953                 case 0: op = rv_op_fcvt_q_s; break;
2954                 case 1: op = rv_op_fcvt_q_d; break;
2955                 }
2956                 break;
2957             case 44:
2958                 switch (((inst >> 20) & 0b11111)) {
2959                 case 0: op = rv_op_fsqrt_s; break;
2960                 }
2961                 break;
2962             case 45:
2963                 switch (((inst >> 20) & 0b11111)) {
2964                 case 0: op = rv_op_fsqrt_d; break;
2965                 }
2966                 break;
2967             case 47:
2968                 switch (((inst >> 20) & 0b11111)) {
2969                 case 0: op = rv_op_fsqrt_q; break;
2970                 }
2971                 break;
2972             case 80:
2973                 switch (((inst >> 12) & 0b111)) {
2974                 case 0: op = rv_op_fle_s; break;
2975                 case 1: op = rv_op_flt_s; break;
2976                 case 2: op = rv_op_feq_s; break;
2977                 }
2978                 break;
2979             case 81:
2980                 switch (((inst >> 12) & 0b111)) {
2981                 case 0: op = rv_op_fle_d; break;
2982                 case 1: op = rv_op_flt_d; break;
2983                 case 2: op = rv_op_feq_d; break;
2984                 }
2985                 break;
2986             case 83:
2987                 switch (((inst >> 12) & 0b111)) {
2988                 case 0: op = rv_op_fle_q; break;
2989                 case 1: op = rv_op_flt_q; break;
2990                 case 2: op = rv_op_feq_q; break;
2991                 }
2992                 break;
2993             case 96:
2994                 switch (((inst >> 20) & 0b11111)) {
2995                 case 0: op = rv_op_fcvt_w_s; break;
2996                 case 1: op = rv_op_fcvt_wu_s; break;
2997                 case 2: op = rv_op_fcvt_l_s; break;
2998                 case 3: op = rv_op_fcvt_lu_s; break;
2999                 }
3000                 break;
3001             case 97:
3002                 switch (((inst >> 20) & 0b11111)) {
3003                 case 0: op = rv_op_fcvt_w_d; break;
3004                 case 1: op = rv_op_fcvt_wu_d; break;
3005                 case 2: op = rv_op_fcvt_l_d; break;
3006                 case 3: op = rv_op_fcvt_lu_d; break;
3007                 }
3008                 break;
3009             case 99:
3010                 switch (((inst >> 20) & 0b11111)) {
3011                 case 0: op = rv_op_fcvt_w_q; break;
3012                 case 1: op = rv_op_fcvt_wu_q; break;
3013                 case 2: op = rv_op_fcvt_l_q; break;
3014                 case 3: op = rv_op_fcvt_lu_q; break;
3015                 }
3016                 break;
3017             case 104:
3018                 switch (((inst >> 20) & 0b11111)) {
3019                 case 0: op = rv_op_fcvt_s_w; break;
3020                 case 1: op = rv_op_fcvt_s_wu; break;
3021                 case 2: op = rv_op_fcvt_s_l; break;
3022                 case 3: op = rv_op_fcvt_s_lu; break;
3023                 }
3024                 break;
3025             case 105:
3026                 switch (((inst >> 20) & 0b11111)) {
3027                 case 0: op = rv_op_fcvt_d_w; break;
3028                 case 1: op = rv_op_fcvt_d_wu; break;
3029                 case 2: op = rv_op_fcvt_d_l; break;
3030                 case 3: op = rv_op_fcvt_d_lu; break;
3031                 }
3032                 break;
3033             case 107:
3034                 switch (((inst >> 20) & 0b11111)) {
3035                 case 0: op = rv_op_fcvt_q_w; break;
3036                 case 1: op = rv_op_fcvt_q_wu; break;
3037                 case 2: op = rv_op_fcvt_q_l; break;
3038                 case 3: op = rv_op_fcvt_q_lu; break;
3039                 }
3040                 break;
3041             case 112:
3042                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3043                 case 0: op = rv_op_fmv_x_s; break;
3044                 case 1: op = rv_op_fclass_s; break;
3045                 }
3046                 break;
3047             case 113:
3048                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3049                 case 0: op = rv_op_fmv_x_d; break;
3050                 case 1: op = rv_op_fclass_d; break;
3051                 }
3052                 break;
3053             case 115:
3054                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3055                 case 0: op = rv_op_fmv_x_q; break;
3056                 case 1: op = rv_op_fclass_q; break;
3057                 }
3058                 break;
3059             case 120:
3060                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3061                 case 0: op = rv_op_fmv_s_x; break;
3062                 }
3063                 break;
3064             case 121:
3065                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3066                 case 0: op = rv_op_fmv_d_x; break;
3067                 }
3068                 break;
3069             case 123:
3070                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3071                 case 0: op = rv_op_fmv_q_x; break;
3072                 }
3073                 break;
3074             }
3075             break;
3076         case 21:
3077             switch (((inst >> 12) & 0b111)) {
3078             case 0:
3079                 switch (((inst >> 26) & 0b111111)) {
3080                 case 0: op = rv_op_vadd_vv; break;
3081                 case 2: op = rv_op_vsub_vv; break;
3082                 case 4: op = rv_op_vminu_vv; break;
3083                 case 5: op = rv_op_vmin_vv; break;
3084                 case 6: op = rv_op_vmaxu_vv; break;
3085                 case 7: op = rv_op_vmax_vv; break;
3086                 case 9: op = rv_op_vand_vv; break;
3087                 case 10: op = rv_op_vor_vv; break;
3088                 case 11: op = rv_op_vxor_vv; break;
3089                 case 12: op = rv_op_vrgather_vv; break;
3090                 case 14: op = rv_op_vrgatherei16_vv; break;
3091                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
3092                 case 17: op = rv_op_vmadc_vvm; break;
3093                 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
3094                 case 19: op = rv_op_vmsbc_vvm; break;
3095                 case 23:
3096                     if (((inst >> 20) & 0b111111) == 32)
3097                         op = rv_op_vmv_v_v;
3098                     else if (((inst >> 25) & 1) == 0)
3099                         op = rv_op_vmerge_vvm;
3100                     break;
3101                 case 24: op = rv_op_vmseq_vv; break;
3102                 case 25: op = rv_op_vmsne_vv; break;
3103                 case 26: op = rv_op_vmsltu_vv; break;
3104                 case 27: op = rv_op_vmslt_vv; break;
3105                 case 28: op = rv_op_vmsleu_vv; break;
3106                 case 29: op = rv_op_vmsle_vv; break;
3107                 case 32: op = rv_op_vsaddu_vv; break;
3108                 case 33: op = rv_op_vsadd_vv; break;
3109                 case 34: op = rv_op_vssubu_vv; break;
3110                 case 35: op = rv_op_vssub_vv; break;
3111                 case 37: op = rv_op_vsll_vv; break;
3112                 case 39: op = rv_op_vsmul_vv; break;
3113                 case 40: op = rv_op_vsrl_vv; break;
3114                 case 41: op = rv_op_vsra_vv; break;
3115                 case 42: op = rv_op_vssrl_vv; break;
3116                 case 43: op = rv_op_vssra_vv; break;
3117                 case 44: op = rv_op_vnsrl_wv; break;
3118                 case 45: op = rv_op_vnsra_wv; break;
3119                 case 46: op = rv_op_vnclipu_wv; break;
3120                 case 47: op = rv_op_vnclip_wv; break;
3121                 case 48: op = rv_op_vwredsumu_vs; break;
3122                 case 49: op = rv_op_vwredsum_vs; break;
3123                 }
3124                 break;
3125             case 1:
3126                 switch (((inst >> 26) & 0b111111)) {
3127                 case 0: op = rv_op_vfadd_vv; break;
3128                 case 1: op = rv_op_vfredusum_vs; break;
3129                 case 2: op = rv_op_vfsub_vv; break;
3130                 case 3: op = rv_op_vfredosum_vs; break;
3131                 case 4: op = rv_op_vfmin_vv; break;
3132                 case 5: op = rv_op_vfredmin_vs; break;
3133                 case 6: op = rv_op_vfmax_vv; break;
3134                 case 7: op = rv_op_vfredmax_vs; break;
3135                 case 8: op = rv_op_vfsgnj_vv; break;
3136                 case 9: op = rv_op_vfsgnjn_vv; break;
3137                 case 10: op = rv_op_vfsgnjx_vv; break;
3138                 case 16:
3139                     switch (((inst >> 15) & 0b11111)) {
3140                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
3141                     }
3142                     break;
3143                 case 18:
3144                     switch (((inst >> 15) & 0b11111)) {
3145                     case 0: op = rv_op_vfcvt_xu_f_v; break;
3146                     case 1: op = rv_op_vfcvt_x_f_v; break;
3147                     case 2: op = rv_op_vfcvt_f_xu_v; break;
3148                     case 3: op = rv_op_vfcvt_f_x_v; break;
3149                     case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
3150                     case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
3151                     case 8: op = rv_op_vfwcvt_xu_f_v; break;
3152                     case 9: op = rv_op_vfwcvt_x_f_v; break;
3153                     case 10: op = rv_op_vfwcvt_f_xu_v; break;
3154                     case 11: op = rv_op_vfwcvt_f_x_v; break;
3155                     case 12: op = rv_op_vfwcvt_f_f_v; break;
3156                     case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
3157                     case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
3158                     case 16: op = rv_op_vfncvt_xu_f_w; break;
3159                     case 17: op = rv_op_vfncvt_x_f_w; break;
3160                     case 18: op = rv_op_vfncvt_f_xu_w; break;
3161                     case 19: op = rv_op_vfncvt_f_x_w; break;
3162                     case 20: op = rv_op_vfncvt_f_f_w; break;
3163                     case 21: op = rv_op_vfncvt_rod_f_f_w; break;
3164                     case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
3165                     case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
3166                     }
3167                     break;
3168                 case 19:
3169                     switch (((inst >> 15) & 0b11111)) {
3170                     case 0: op = rv_op_vfsqrt_v; break;
3171                     case 4: op = rv_op_vfrsqrt7_v; break;
3172                     case 5: op = rv_op_vfrec7_v; break;
3173                     case 16: op = rv_op_vfclass_v; break;
3174                     }
3175                     break;
3176                 case 24: op = rv_op_vmfeq_vv; break;
3177                 case 25: op = rv_op_vmfle_vv; break;
3178                 case 27: op = rv_op_vmflt_vv; break;
3179                 case 28: op = rv_op_vmfne_vv; break;
3180                 case 32: op = rv_op_vfdiv_vv; break;
3181                 case 36: op = rv_op_vfmul_vv; break;
3182                 case 40: op = rv_op_vfmadd_vv; break;
3183                 case 41: op = rv_op_vfnmadd_vv; break;
3184                 case 42: op = rv_op_vfmsub_vv; break;
3185                 case 43: op = rv_op_vfnmsub_vv; break;
3186                 case 44: op = rv_op_vfmacc_vv; break;
3187                 case 45: op = rv_op_vfnmacc_vv; break;
3188                 case 46: op = rv_op_vfmsac_vv; break;
3189                 case 47: op = rv_op_vfnmsac_vv; break;
3190                 case 48: op = rv_op_vfwadd_vv; break;
3191                 case 49: op = rv_op_vfwredusum_vs; break;
3192                 case 50: op = rv_op_vfwsub_vv; break;
3193                 case 51: op = rv_op_vfwredosum_vs; break;
3194                 case 52: op = rv_op_vfwadd_wv; break;
3195                 case 54: op = rv_op_vfwsub_wv; break;
3196                 case 56: op = rv_op_vfwmul_vv; break;
3197                 case 60: op = rv_op_vfwmacc_vv; break;
3198                 case 61: op = rv_op_vfwnmacc_vv; break;
3199                 case 62: op = rv_op_vfwmsac_vv; break;
3200                 case 63: op = rv_op_vfwnmsac_vv; break;
3201                 }
3202                 break;
3203             case 2:
3204                 switch (((inst >> 26) & 0b111111)) {
3205                 case 0: op = rv_op_vredsum_vs; break;
3206                 case 1: op = rv_op_vredand_vs; break;
3207                 case 2: op = rv_op_vredor_vs; break;
3208                 case 3: op = rv_op_vredxor_vs; break;
3209                 case 4: op = rv_op_vredminu_vs; break;
3210                 case 5: op = rv_op_vredmin_vs; break;
3211                 case 6: op = rv_op_vredmaxu_vs; break;
3212                 case 7: op = rv_op_vredmax_vs; break;
3213                 case 8: op = rv_op_vaaddu_vv; break;
3214                 case 9: op = rv_op_vaadd_vv; break;
3215                 case 10: op = rv_op_vasubu_vv; break;
3216                 case 11: op = rv_op_vasub_vv; break;
3217                 case 16:
3218                     switch (((inst >> 15) & 0b11111)) {
3219                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
3220                     case 16: op = rv_op_vcpop_m; break;
3221                     case 17: op = rv_op_vfirst_m; break;
3222                     }
3223                     break;
3224                 case 18:
3225                     switch (((inst >> 15) & 0b11111)) {
3226                     case 2: op = rv_op_vzext_vf8; break;
3227                     case 3: op = rv_op_vsext_vf8; break;
3228                     case 4: op = rv_op_vzext_vf4; break;
3229                     case 5: op = rv_op_vsext_vf4; break;
3230                     case 6: op = rv_op_vzext_vf2; break;
3231                     case 7: op = rv_op_vsext_vf2; break;
3232                     }
3233                     break;
3234                 case 20:
3235                     switch (((inst >> 15) & 0b11111)) {
3236                     case 1: op = rv_op_vmsbf_m;  break;
3237                     case 2: op = rv_op_vmsof_m; break;
3238                     case 3: op = rv_op_vmsif_m; break;
3239                     case 16: op = rv_op_viota_m; break;
3240                     case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
3241                     }
3242                     break;
3243                 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
3244                 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
3245                 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
3246                 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
3247                 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
3248                 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
3249                 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
3250                 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
3251                 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
3252                 case 32: op = rv_op_vdivu_vv; break;
3253                 case 33: op = rv_op_vdiv_vv; break;
3254                 case 34: op = rv_op_vremu_vv; break;
3255                 case 35: op = rv_op_vrem_vv; break;
3256                 case 36: op = rv_op_vmulhu_vv; break;
3257                 case 37: op = rv_op_vmul_vv; break;
3258                 case 38: op = rv_op_vmulhsu_vv; break;
3259                 case 39: op = rv_op_vmulh_vv; break;
3260                 case 41: op = rv_op_vmadd_vv; break;
3261                 case 43: op = rv_op_vnmsub_vv; break;
3262                 case 45: op = rv_op_vmacc_vv; break;
3263                 case 47: op = rv_op_vnmsac_vv; break;
3264                 case 48: op = rv_op_vwaddu_vv; break;
3265                 case 49: op = rv_op_vwadd_vv; break;
3266                 case 50: op = rv_op_vwsubu_vv; break;
3267                 case 51: op = rv_op_vwsub_vv; break;
3268                 case 52: op = rv_op_vwaddu_wv; break;
3269                 case 53: op = rv_op_vwadd_wv; break;
3270                 case 54: op = rv_op_vwsubu_wv; break;
3271                 case 55: op = rv_op_vwsub_wv; break;
3272                 case 56: op = rv_op_vwmulu_vv; break;
3273                 case 58: op = rv_op_vwmulsu_vv; break;
3274                 case 59: op = rv_op_vwmul_vv; break;
3275                 case 60: op = rv_op_vwmaccu_vv; break;
3276                 case 61: op = rv_op_vwmacc_vv; break;
3277                 case 63: op = rv_op_vwmaccsu_vv; break;
3278                 }
3279                 break;
3280             case 3:
3281                 switch (((inst >> 26) & 0b111111)) {
3282                 case 0: op = rv_op_vadd_vi; break;
3283                 case 3: op = rv_op_vrsub_vi; break;
3284                 case 9: op = rv_op_vand_vi; break;
3285                 case 10: op = rv_op_vor_vi; break;
3286                 case 11: op = rv_op_vxor_vi; break;
3287                 case 12: op = rv_op_vrgather_vi; break;
3288                 case 14: op = rv_op_vslideup_vi; break;
3289                 case 15: op = rv_op_vslidedown_vi; break;
3290                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
3291                 case 17: op = rv_op_vmadc_vim; break;
3292                 case 23:
3293                     if (((inst >> 20) & 0b111111) == 32)
3294                         op = rv_op_vmv_v_i;
3295                     else if (((inst >> 25) & 1) == 0)
3296                         op = rv_op_vmerge_vim;
3297                     break;
3298                 case 24: op = rv_op_vmseq_vi; break;
3299                 case 25: op = rv_op_vmsne_vi; break;
3300                 case 28: op = rv_op_vmsleu_vi; break;
3301                 case 29: op = rv_op_vmsle_vi; break;
3302                 case 30: op = rv_op_vmsgtu_vi; break;
3303                 case 31: op = rv_op_vmsgt_vi; break;
3304                 case 32: op = rv_op_vsaddu_vi; break;
3305                 case 33: op = rv_op_vsadd_vi; break;
3306                 case 37: op = rv_op_vsll_vi; break;
3307                 case 39:
3308                     switch (((inst >> 15) & 0b11111)) {
3309                     case 0: op = rv_op_vmv1r_v; break;
3310                     case 1: op = rv_op_vmv2r_v; break;
3311                     case 3: op = rv_op_vmv4r_v; break;
3312                     case 7: op = rv_op_vmv8r_v; break;
3313                     }
3314                     break;
3315                 case 40: op = rv_op_vsrl_vi; break;
3316                 case 41: op = rv_op_vsra_vi; break;
3317                 case 42: op = rv_op_vssrl_vi; break;
3318                 case 43: op = rv_op_vssra_vi; break;
3319                 case 44: op = rv_op_vnsrl_wi; break;
3320                 case 45: op = rv_op_vnsra_wi; break;
3321                 case 46: op = rv_op_vnclipu_wi; break;
3322                 case 47: op = rv_op_vnclip_wi; break;
3323                 }
3324                 break;
3325             case 4:
3326                 switch (((inst >> 26) & 0b111111)) {
3327                 case 0: op = rv_op_vadd_vx; break;
3328                 case 2: op = rv_op_vsub_vx; break;
3329                 case 3: op = rv_op_vrsub_vx; break;
3330                 case 4: op = rv_op_vminu_vx; break;
3331                 case 5: op = rv_op_vmin_vx; break;
3332                 case 6: op = rv_op_vmaxu_vx; break;
3333                 case 7: op = rv_op_vmax_vx; break;
3334                 case 9: op = rv_op_vand_vx; break;
3335                 case 10: op = rv_op_vor_vx; break;
3336                 case 11: op = rv_op_vxor_vx; break;
3337                 case 12: op = rv_op_vrgather_vx; break;
3338                 case 14: op = rv_op_vslideup_vx; break;
3339                 case 15: op = rv_op_vslidedown_vx; break;
3340                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
3341                 case 17: op = rv_op_vmadc_vxm; break;
3342                 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
3343                 case 19: op = rv_op_vmsbc_vxm; break;
3344                 case 23:
3345                     if (((inst >> 20) & 0b111111) == 32)
3346                         op = rv_op_vmv_v_x;
3347                     else if (((inst >> 25) & 1) == 0)
3348                         op = rv_op_vmerge_vxm;
3349                     break;
3350                 case 24: op = rv_op_vmseq_vx; break;
3351                 case 25: op = rv_op_vmsne_vx; break;
3352                 case 26: op = rv_op_vmsltu_vx; break;
3353                 case 27: op = rv_op_vmslt_vx; break;
3354                 case 28: op = rv_op_vmsleu_vx; break;
3355                 case 29: op = rv_op_vmsle_vx; break;
3356                 case 30: op = rv_op_vmsgtu_vx; break;
3357                 case 31: op = rv_op_vmsgt_vx; break;
3358                 case 32: op = rv_op_vsaddu_vx; break;
3359                 case 33: op = rv_op_vsadd_vx; break;
3360                 case 34: op = rv_op_vssubu_vx; break;
3361                 case 35: op = rv_op_vssub_vx; break;
3362                 case 37: op = rv_op_vsll_vx; break;
3363                 case 39: op = rv_op_vsmul_vx; break;
3364                 case 40: op = rv_op_vsrl_vx; break;
3365                 case 41: op = rv_op_vsra_vx; break;
3366                 case 42: op = rv_op_vssrl_vx; break;
3367                 case 43: op = rv_op_vssra_vx; break;
3368                 case 44: op = rv_op_vnsrl_wx; break;
3369                 case 45: op = rv_op_vnsra_wx; break;
3370                 case 46: op = rv_op_vnclipu_wx; break;
3371                 case 47: op = rv_op_vnclip_wx; break;
3372                 }
3373                 break;
3374             case 5:
3375                 switch (((inst >> 26) & 0b111111)) {
3376                 case 0: op = rv_op_vfadd_vf; break;
3377                 case 2: op = rv_op_vfsub_vf; break;
3378                 case 4: op = rv_op_vfmin_vf; break;
3379                 case 6: op = rv_op_vfmax_vf; break;
3380                 case 8: op = rv_op_vfsgnj_vf; break;
3381                 case 9: op = rv_op_vfsgnjn_vf; break;
3382                 case 10: op = rv_op_vfsgnjx_vf; break;
3383                 case 14: op = rv_op_vfslide1up_vf; break;
3384                 case 15: op = rv_op_vfslide1down_vf; break;
3385                 case 16:
3386                     switch (((inst >> 20) & 0b11111)) {
3387                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
3388                     }
3389                     break;
3390                 case 23:
3391                     if (((inst >> 25) & 1) == 0)
3392                         op = rv_op_vfmerge_vfm;
3393                     else if (((inst >> 20) & 0b111111) == 32)
3394                         op = rv_op_vfmv_v_f;
3395                     break;
3396                 case 24: op = rv_op_vmfeq_vf; break;
3397                 case 25: op = rv_op_vmfle_vf; break;
3398                 case 27: op = rv_op_vmflt_vf; break;
3399                 case 28: op = rv_op_vmfne_vf; break;
3400                 case 29: op = rv_op_vmfgt_vf; break;
3401                 case 31: op = rv_op_vmfge_vf; break;
3402                 case 32: op = rv_op_vfdiv_vf; break;
3403                 case 33: op = rv_op_vfrdiv_vf; break;
3404                 case 36: op = rv_op_vfmul_vf; break;
3405                 case 39: op = rv_op_vfrsub_vf; break;
3406                 case 40: op = rv_op_vfmadd_vf; break;
3407                 case 41: op = rv_op_vfnmadd_vf; break;
3408                 case 42: op = rv_op_vfmsub_vf; break;
3409                 case 43: op = rv_op_vfnmsub_vf; break;
3410                 case 44: op = rv_op_vfmacc_vf; break;
3411                 case 45: op = rv_op_vfnmacc_vf; break;
3412                 case 46: op = rv_op_vfmsac_vf; break;
3413                 case 47: op = rv_op_vfnmsac_vf; break;
3414                 case 48: op = rv_op_vfwadd_vf; break;
3415                 case 50: op = rv_op_vfwsub_vf; break;
3416                 case 52: op = rv_op_vfwadd_wf; break;
3417                 case 54: op = rv_op_vfwsub_wf; break;
3418                 case 56: op = rv_op_vfwmul_vf; break;
3419                 case 60: op = rv_op_vfwmacc_vf; break;
3420                 case 61: op = rv_op_vfwnmacc_vf; break;
3421                 case 62: op = rv_op_vfwmsac_vf; break;
3422                 case 63: op = rv_op_vfwnmsac_vf; break;
3423                 }
3424                 break;
3425             case 6:
3426                 switch (((inst >> 26) & 0b111111)) {
3427                 case 8: op = rv_op_vaaddu_vx; break;
3428                 case 9: op = rv_op_vaadd_vx; break;
3429                 case 10: op = rv_op_vasubu_vx; break;
3430                 case 11: op = rv_op_vasub_vx; break;
3431                 case 14: op = rv_op_vslide1up_vx; break;
3432                 case 15: op = rv_op_vslide1down_vx; break;
3433                 case 16:
3434                     switch (((inst >> 20) & 0b11111)) {
3435                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
3436                     }
3437                     break;
3438                 case 32: op = rv_op_vdivu_vx; break;
3439                 case 33: op = rv_op_vdiv_vx; break;
3440                 case 34: op = rv_op_vremu_vx; break;
3441                 case 35: op = rv_op_vrem_vx; break;
3442                 case 36: op = rv_op_vmulhu_vx; break;
3443                 case 37: op = rv_op_vmul_vx; break;
3444                 case 38: op = rv_op_vmulhsu_vx; break;
3445                 case 39: op = rv_op_vmulh_vx; break;
3446                 case 41: op = rv_op_vmadd_vx; break;
3447                 case 43: op = rv_op_vnmsub_vx; break;
3448                 case 45: op = rv_op_vmacc_vx; break;
3449                 case 47: op = rv_op_vnmsac_vx; break;
3450                 case 48: op = rv_op_vwaddu_vx; break;
3451                 case 49: op = rv_op_vwadd_vx; break;
3452                 case 50: op = rv_op_vwsubu_vx; break;
3453                 case 51: op = rv_op_vwsub_vx; break;
3454                 case 52: op = rv_op_vwaddu_wx; break;
3455                 case 53: op = rv_op_vwadd_wx; break;
3456                 case 54: op = rv_op_vwsubu_wx; break;
3457                 case 55: op = rv_op_vwsub_wx; break;
3458                 case 56: op = rv_op_vwmulu_vx; break;
3459                 case 58: op = rv_op_vwmulsu_vx; break;
3460                 case 59: op = rv_op_vwmul_vx; break;
3461                 case 60: op = rv_op_vwmaccu_vx; break;
3462                 case 61: op = rv_op_vwmacc_vx; break;
3463                 case 62: op = rv_op_vwmaccus_vx; break;
3464                 case 63: op = rv_op_vwmaccsu_vx; break;
3465                 }
3466                 break;
3467             case 7:
3468                 if (((inst >> 31) & 1) == 0) {
3469                     op = rv_op_vsetvli;
3470                 } else if ((inst >> 30) & 1) {
3471                     op = rv_op_vsetivli;
3472                 } else if (((inst >> 25) & 0b11111) == 0) {
3473                     op = rv_op_vsetvl;
3474                 }
3475                 break;
3476             }
3477             break;
3478         case 22:
3479             switch (((inst >> 12) & 0b111)) {
3480             case 0: op = rv_op_addid; break;
3481             case 1:
3482                 switch (((inst >> 26) & 0b111111)) {
3483                 case 0: op = rv_op_sllid; break;
3484                 }
3485                 break;
3486             case 5:
3487                 switch (((inst >> 26) & 0b111111)) {
3488                 case 0: op = rv_op_srlid; break;
3489                 case 16: op = rv_op_sraid; break;
3490                 }
3491                 break;
3492             }
3493             break;
3494         case 24:
3495             switch (((inst >> 12) & 0b111)) {
3496             case 0: op = rv_op_beq; break;
3497             case 1: op = rv_op_bne; break;
3498             case 4: op = rv_op_blt; break;
3499             case 5: op = rv_op_bge; break;
3500             case 6: op = rv_op_bltu; break;
3501             case 7: op = rv_op_bgeu; break;
3502             }
3503             break;
3504         case 25:
3505             switch (((inst >> 12) & 0b111)) {
3506             case 0: op = rv_op_jalr; break;
3507             }
3508             break;
3509         case 27: op = rv_op_jal; break;
3510         case 28:
3511             switch (((inst >> 12) & 0b111)) {
3512             case 0:
3513                 switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
3514                 case 0:
3515                     switch (((inst >> 15) & 0b1111111111)) {
3516                     case 0: op = rv_op_ecall; break;
3517                     case 32: op = rv_op_ebreak; break;
3518                     case 64: op = rv_op_uret; break;
3519                     }
3520                     break;
3521                 case 256:
3522                     switch (((inst >> 20) & 0b11111)) {
3523                     case 2:
3524                         switch (((inst >> 15) & 0b11111)) {
3525                         case 0: op = rv_op_sret; break;
3526                         }
3527                         break;
3528                     case 4: op = rv_op_sfence_vm; break;
3529                     case 5:
3530                         switch (((inst >> 15) & 0b11111)) {
3531                         case 0: op = rv_op_wfi; break;
3532                         }
3533                         break;
3534                     }
3535                     break;
3536                 case 288: op = rv_op_sfence_vma; break;
3537                 case 512:
3538                     switch (((inst >> 15) & 0b1111111111)) {
3539                     case 64: op = rv_op_hret; break;
3540                     }
3541                     break;
3542                 case 768:
3543                     switch (((inst >> 15) & 0b1111111111)) {
3544                     case 64: op = rv_op_mret; break;
3545                     }
3546                     break;
3547                 case 1952:
3548                     switch (((inst >> 15) & 0b1111111111)) {
3549                     case 576: op = rv_op_dret; break;
3550                     }
3551                     break;
3552                 }
3553                 break;
3554             case 1: op = rv_op_csrrw; break;
3555             case 2: op = rv_op_csrrs; break;
3556             case 3: op = rv_op_csrrc; break;
3557             case 5: op = rv_op_csrrwi; break;
3558             case 6: op = rv_op_csrrsi; break;
3559             case 7: op = rv_op_csrrci; break;
3560             }
3561             break;
3562         case 30:
3563             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
3564             case 0: op = rv_op_addd; break;
3565             case 1: op = rv_op_slld; break;
3566             case 5: op = rv_op_srld; break;
3567             case 8: op = rv_op_muld; break;
3568             case 12: op = rv_op_divd; break;
3569             case 13: op = rv_op_divud; break;
3570             case 14: op = rv_op_remd; break;
3571             case 15: op = rv_op_remud; break;
3572             case 256: op = rv_op_subd; break;
3573             case 261: op = rv_op_srad; break;
3574             }
3575             break;
3576         }
3577         break;
3578     }
3579     dec->op = op;
3580 }
3581
3582 /* operand extractors */
3583
3584 static uint32_t operand_rd(rv_inst inst)
3585 {
3586     return (inst << 52) >> 59;
3587 }
3588
3589 static uint32_t operand_rs1(rv_inst inst)
3590 {
3591     return (inst << 44) >> 59;
3592 }
3593
3594 static uint32_t operand_rs2(rv_inst inst)
3595 {
3596     return (inst << 39) >> 59;
3597 }
3598
3599 static uint32_t operand_rs3(rv_inst inst)
3600 {
3601     return (inst << 32) >> 59;
3602 }
3603
3604 static uint32_t operand_aq(rv_inst inst)
3605 {
3606     return (inst << 37) >> 63;
3607 }
3608
3609 static uint32_t operand_rl(rv_inst inst)
3610 {
3611     return (inst << 38) >> 63;
3612 }
3613
3614 static uint32_t operand_pred(rv_inst inst)
3615 {
3616     return (inst << 36) >> 60;
3617 }
3618
3619 static uint32_t operand_succ(rv_inst inst)
3620 {
3621     return (inst << 40) >> 60;
3622 }
3623
3624 static uint32_t operand_rm(rv_inst inst)
3625 {
3626     return (inst << 49) >> 61;
3627 }
3628
3629 static uint32_t operand_shamt5(rv_inst inst)
3630 {
3631     return (inst << 39) >> 59;
3632 }
3633
3634 static uint32_t operand_shamt6(rv_inst inst)
3635 {
3636     return (inst << 38) >> 58;
3637 }
3638
3639 static uint32_t operand_shamt7(rv_inst inst)
3640 {
3641     return (inst << 37) >> 57;
3642 }
3643
3644 static uint32_t operand_crdq(rv_inst inst)
3645 {
3646     return (inst << 59) >> 61;
3647 }
3648
3649 static uint32_t operand_crs1q(rv_inst inst)
3650 {
3651     return (inst << 54) >> 61;
3652 }
3653
3654 static uint32_t operand_crs1rdq(rv_inst inst)
3655 {
3656     return (inst << 54) >> 61;
3657 }
3658
3659 static uint32_t operand_crs2q(rv_inst inst)
3660 {
3661     return (inst << 59) >> 61;
3662 }
3663
3664 static uint32_t operand_crd(rv_inst inst)
3665 {
3666     return (inst << 52) >> 59;
3667 }
3668
3669 static uint32_t operand_crs1(rv_inst inst)
3670 {
3671     return (inst << 52) >> 59;
3672 }
3673
3674 static uint32_t operand_crs1rd(rv_inst inst)
3675 {
3676     return (inst << 52) >> 59;
3677 }
3678
3679 static uint32_t operand_crs2(rv_inst inst)
3680 {
3681     return (inst << 57) >> 59;
3682 }
3683
3684 static uint32_t operand_cimmsh5(rv_inst inst)
3685 {
3686     return (inst << 57) >> 59;
3687 }
3688
3689 static uint32_t operand_csr12(rv_inst inst)
3690 {
3691     return (inst << 32) >> 52;
3692 }
3693
3694 static int32_t operand_imm12(rv_inst inst)
3695 {
3696     return ((int64_t)inst << 32) >> 52;
3697 }
3698
3699 static int32_t operand_imm20(rv_inst inst)
3700 {
3701     return (((int64_t)inst << 32) >> 44) << 12;
3702 }
3703
3704 static int32_t operand_jimm20(rv_inst inst)
3705 {
3706     return (((int64_t)inst << 32) >> 63) << 20 |
3707         ((inst << 33) >> 54) << 1 |
3708         ((inst << 43) >> 63) << 11 |
3709         ((inst << 44) >> 56) << 12;
3710 }
3711
3712 static int32_t operand_simm12(rv_inst inst)
3713 {
3714     return (((int64_t)inst << 32) >> 57) << 5 |
3715         (inst << 52) >> 59;
3716 }
3717
3718 static int32_t operand_sbimm12(rv_inst inst)
3719 {
3720     return (((int64_t)inst << 32) >> 63) << 12 |
3721         ((inst << 33) >> 58) << 5 |
3722         ((inst << 52) >> 60) << 1 |
3723         ((inst << 56) >> 63) << 11;
3724 }
3725
3726 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
3727 {
3728     int imm = ((inst << 51) >> 63) << 5 |
3729         (inst << 57) >> 59;
3730     if (isa == rv128) {
3731         imm = imm ? imm : 64;
3732     }
3733     return imm;
3734 }
3735
3736 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
3737 {
3738     int imm = ((inst << 51) >> 63) << 5 |
3739         (inst << 57) >> 59;
3740     if (isa == rv128) {
3741         imm = imm | (imm & 32) << 1;
3742         imm = imm ? imm : 64;
3743     }
3744     return imm;
3745 }
3746
3747 static int32_t operand_cimmi(rv_inst inst)
3748 {
3749     return (((int64_t)inst << 51) >> 63) << 5 |
3750         (inst << 57) >> 59;
3751 }
3752
3753 static int32_t operand_cimmui(rv_inst inst)
3754 {
3755     return (((int64_t)inst << 51) >> 63) << 17 |
3756         ((inst << 57) >> 59) << 12;
3757 }
3758
3759 static uint32_t operand_cimmlwsp(rv_inst inst)
3760 {
3761     return ((inst << 51) >> 63) << 5 |
3762         ((inst << 57) >> 61) << 2 |
3763         ((inst << 60) >> 62) << 6;
3764 }
3765
3766 static uint32_t operand_cimmldsp(rv_inst inst)
3767 {
3768     return ((inst << 51) >> 63) << 5 |
3769         ((inst << 57) >> 62) << 3 |
3770         ((inst << 59) >> 61) << 6;
3771 }
3772
3773 static uint32_t operand_cimmlqsp(rv_inst inst)
3774 {
3775     return ((inst << 51) >> 63) << 5 |
3776         ((inst << 57) >> 63) << 4 |
3777         ((inst << 58) >> 60) << 6;
3778 }
3779
3780 static int32_t operand_cimm16sp(rv_inst inst)
3781 {
3782     return (((int64_t)inst << 51) >> 63) << 9 |
3783         ((inst << 57) >> 63) << 4 |
3784         ((inst << 58) >> 63) << 6 |
3785         ((inst << 59) >> 62) << 7 |
3786         ((inst << 61) >> 63) << 5;
3787 }
3788
3789 static int32_t operand_cimmj(rv_inst inst)
3790 {
3791     return (((int64_t)inst << 51) >> 63) << 11 |
3792         ((inst << 52) >> 63) << 4 |
3793         ((inst << 53) >> 62) << 8 |
3794         ((inst << 55) >> 63) << 10 |
3795         ((inst << 56) >> 63) << 6 |
3796         ((inst << 57) >> 63) << 7 |
3797         ((inst << 58) >> 61) << 1 |
3798         ((inst << 61) >> 63) << 5;
3799 }
3800
3801 static int32_t operand_cimmb(rv_inst inst)
3802 {
3803     return (((int64_t)inst << 51) >> 63) << 8 |
3804         ((inst << 52) >> 62) << 3 |
3805         ((inst << 57) >> 62) << 6 |
3806         ((inst << 59) >> 62) << 1 |
3807         ((inst << 61) >> 63) << 5;
3808 }
3809
3810 static uint32_t operand_cimmswsp(rv_inst inst)
3811 {
3812     return ((inst << 51) >> 60) << 2 |
3813         ((inst << 55) >> 62) << 6;
3814 }
3815
3816 static uint32_t operand_cimmsdsp(rv_inst inst)
3817 {
3818     return ((inst << 51) >> 61) << 3 |
3819         ((inst << 54) >> 61) << 6;
3820 }
3821
3822 static uint32_t operand_cimmsqsp(rv_inst inst)
3823 {
3824     return ((inst << 51) >> 62) << 4 |
3825         ((inst << 53) >> 60) << 6;
3826 }
3827
3828 static uint32_t operand_cimm4spn(rv_inst inst)
3829 {
3830     return ((inst << 51) >> 62) << 4 |
3831         ((inst << 53) >> 60) << 6 |
3832         ((inst << 57) >> 63) << 2 |
3833         ((inst << 58) >> 63) << 3;
3834 }
3835
3836 static uint32_t operand_cimmw(rv_inst inst)
3837 {
3838     return ((inst << 51) >> 61) << 3 |
3839         ((inst << 57) >> 63) << 2 |
3840         ((inst << 58) >> 63) << 6;
3841 }
3842
3843 static uint32_t operand_cimmd(rv_inst inst)
3844 {
3845     return ((inst << 51) >> 61) << 3 |
3846         ((inst << 57) >> 62) << 6;
3847 }
3848
3849 static uint32_t operand_cimmq(rv_inst inst)
3850 {
3851     return ((inst << 51) >> 62) << 4 |
3852         ((inst << 53) >> 63) << 8 |
3853         ((inst << 57) >> 62) << 6;
3854 }
3855
3856 static uint32_t operand_vimm(rv_inst inst)
3857 {
3858     return (int64_t)(inst << 44) >> 59;
3859 }
3860
3861 static uint32_t operand_vzimm11(rv_inst inst)
3862 {
3863     return (inst << 33) >> 53;
3864 }
3865
3866 static uint32_t operand_vzimm10(rv_inst inst)
3867 {
3868     return (inst << 34) >> 54;
3869 }
3870
3871 static uint32_t operand_bs(rv_inst inst)
3872 {
3873     return (inst << 32) >> 62;
3874 }
3875
3876 static uint32_t operand_rnum(rv_inst inst)
3877 {
3878     return (inst << 40) >> 60;
3879 }
3880
3881 static uint32_t operand_vm(rv_inst inst)
3882 {
3883     return (inst << 38) >> 63;
3884 }
3885
3886 /* decode operands */
3887
3888 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
3889 {
3890     rv_inst inst = dec->inst;
3891     dec->codec = opcode_data[dec->op].codec;
3892     switch (dec->codec) {
3893     case rv_codec_none:
3894         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
3895         dec->imm = 0;
3896         break;
3897     case rv_codec_u:
3898         dec->rd = operand_rd(inst);
3899         dec->rs1 = dec->rs2 = rv_ireg_zero;
3900         dec->imm = operand_imm20(inst);
3901         break;
3902     case rv_codec_uj:
3903         dec->rd = operand_rd(inst);
3904         dec->rs1 = dec->rs2 = rv_ireg_zero;
3905         dec->imm = operand_jimm20(inst);
3906         break;
3907     case rv_codec_i:
3908         dec->rd = operand_rd(inst);
3909         dec->rs1 = operand_rs1(inst);
3910         dec->rs2 = rv_ireg_zero;
3911         dec->imm = operand_imm12(inst);
3912         break;
3913     case rv_codec_i_sh5:
3914         dec->rd = operand_rd(inst);
3915         dec->rs1 = operand_rs1(inst);
3916         dec->rs2 = rv_ireg_zero;
3917         dec->imm = operand_shamt5(inst);
3918         break;
3919     case rv_codec_i_sh6:
3920         dec->rd = operand_rd(inst);
3921         dec->rs1 = operand_rs1(inst);
3922         dec->rs2 = rv_ireg_zero;
3923         dec->imm = operand_shamt6(inst);
3924         break;
3925     case rv_codec_i_sh7:
3926         dec->rd = operand_rd(inst);
3927         dec->rs1 = operand_rs1(inst);
3928         dec->rs2 = rv_ireg_zero;
3929         dec->imm = operand_shamt7(inst);
3930         break;
3931     case rv_codec_i_csr:
3932         dec->rd = operand_rd(inst);
3933         dec->rs1 = operand_rs1(inst);
3934         dec->rs2 = rv_ireg_zero;
3935         dec->imm = operand_csr12(inst);
3936         break;
3937     case rv_codec_s:
3938         dec->rd = rv_ireg_zero;
3939         dec->rs1 = operand_rs1(inst);
3940         dec->rs2 = operand_rs2(inst);
3941         dec->imm = operand_simm12(inst);
3942         break;
3943     case rv_codec_sb:
3944         dec->rd = rv_ireg_zero;
3945         dec->rs1 = operand_rs1(inst);
3946         dec->rs2 = operand_rs2(inst);
3947         dec->imm = operand_sbimm12(inst);
3948         break;
3949     case rv_codec_r:
3950         dec->rd = operand_rd(inst);
3951         dec->rs1 = operand_rs1(inst);
3952         dec->rs2 = operand_rs2(inst);
3953         dec->imm = 0;
3954         break;
3955     case rv_codec_r_m:
3956         dec->rd = operand_rd(inst);
3957         dec->rs1 = operand_rs1(inst);
3958         dec->rs2 = operand_rs2(inst);
3959         dec->imm = 0;
3960         dec->rm = operand_rm(inst);
3961         break;
3962     case rv_codec_r4_m:
3963         dec->rd = operand_rd(inst);
3964         dec->rs1 = operand_rs1(inst);
3965         dec->rs2 = operand_rs2(inst);
3966         dec->rs3 = operand_rs3(inst);
3967         dec->imm = 0;
3968         dec->rm = operand_rm(inst);
3969         break;
3970     case rv_codec_r_a:
3971         dec->rd = operand_rd(inst);
3972         dec->rs1 = operand_rs1(inst);
3973         dec->rs2 = operand_rs2(inst);
3974         dec->imm = 0;
3975         dec->aq = operand_aq(inst);
3976         dec->rl = operand_rl(inst);
3977         break;
3978     case rv_codec_r_l:
3979         dec->rd = operand_rd(inst);
3980         dec->rs1 = operand_rs1(inst);
3981         dec->rs2 = rv_ireg_zero;
3982         dec->imm = 0;
3983         dec->aq = operand_aq(inst);
3984         dec->rl = operand_rl(inst);
3985         break;
3986     case rv_codec_r_f:
3987         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
3988         dec->pred = operand_pred(inst);
3989         dec->succ = operand_succ(inst);
3990         dec->imm = 0;
3991         break;
3992     case rv_codec_cb:
3993         dec->rd = rv_ireg_zero;
3994         dec->rs1 = operand_crs1q(inst) + 8;
3995         dec->rs2 = rv_ireg_zero;
3996         dec->imm = operand_cimmb(inst);
3997         break;
3998     case rv_codec_cb_imm:
3999         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4000         dec->rs2 = rv_ireg_zero;
4001         dec->imm = operand_cimmi(inst);
4002         break;
4003     case rv_codec_cb_sh5:
4004         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4005         dec->rs2 = rv_ireg_zero;
4006         dec->imm = operand_cimmsh5(inst);
4007         break;
4008     case rv_codec_cb_sh6:
4009         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4010         dec->rs2 = rv_ireg_zero;
4011         dec->imm = operand_cimmshr6(inst, isa);
4012         break;
4013     case rv_codec_ci:
4014         dec->rd = dec->rs1 = operand_crs1rd(inst);
4015         dec->rs2 = rv_ireg_zero;
4016         dec->imm = operand_cimmi(inst);
4017         break;
4018     case rv_codec_ci_sh5:
4019         dec->rd = dec->rs1 = operand_crs1rd(inst);
4020         dec->rs2 = rv_ireg_zero;
4021         dec->imm = operand_cimmsh5(inst);
4022         break;
4023     case rv_codec_ci_sh6:
4024         dec->rd = dec->rs1 = operand_crs1rd(inst);
4025         dec->rs2 = rv_ireg_zero;
4026         dec->imm = operand_cimmshl6(inst, isa);
4027         break;
4028     case rv_codec_ci_16sp:
4029         dec->rd = rv_ireg_sp;
4030         dec->rs1 = rv_ireg_sp;
4031         dec->rs2 = rv_ireg_zero;
4032         dec->imm = operand_cimm16sp(inst);
4033         break;
4034     case rv_codec_ci_lwsp:
4035         dec->rd = operand_crd(inst);
4036         dec->rs1 = rv_ireg_sp;
4037         dec->rs2 = rv_ireg_zero;
4038         dec->imm = operand_cimmlwsp(inst);
4039         break;
4040     case rv_codec_ci_ldsp:
4041         dec->rd = operand_crd(inst);
4042         dec->rs1 = rv_ireg_sp;
4043         dec->rs2 = rv_ireg_zero;
4044         dec->imm = operand_cimmldsp(inst);
4045         break;
4046     case rv_codec_ci_lqsp:
4047         dec->rd = operand_crd(inst);
4048         dec->rs1 = rv_ireg_sp;
4049         dec->rs2 = rv_ireg_zero;
4050         dec->imm = operand_cimmlqsp(inst);
4051         break;
4052     case rv_codec_ci_li:
4053         dec->rd = operand_crd(inst);
4054         dec->rs1 = rv_ireg_zero;
4055         dec->rs2 = rv_ireg_zero;
4056         dec->imm = operand_cimmi(inst);
4057         break;
4058     case rv_codec_ci_lui:
4059         dec->rd = operand_crd(inst);
4060         dec->rs1 = rv_ireg_zero;
4061         dec->rs2 = rv_ireg_zero;
4062         dec->imm = operand_cimmui(inst);
4063         break;
4064     case rv_codec_ci_none:
4065         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4066         dec->imm = 0;
4067         break;
4068     case rv_codec_ciw_4spn:
4069         dec->rd = operand_crdq(inst) + 8;
4070         dec->rs1 = rv_ireg_sp;
4071         dec->rs2 = rv_ireg_zero;
4072         dec->imm = operand_cimm4spn(inst);
4073         break;
4074     case rv_codec_cj:
4075         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4076         dec->imm = operand_cimmj(inst);
4077         break;
4078     case rv_codec_cj_jal:
4079         dec->rd = rv_ireg_ra;
4080         dec->rs1 = dec->rs2 = rv_ireg_zero;
4081         dec->imm = operand_cimmj(inst);
4082         break;
4083     case rv_codec_cl_lw:
4084         dec->rd = operand_crdq(inst) + 8;
4085         dec->rs1 = operand_crs1q(inst) + 8;
4086         dec->rs2 = rv_ireg_zero;
4087         dec->imm = operand_cimmw(inst);
4088         break;
4089     case rv_codec_cl_ld:
4090         dec->rd = operand_crdq(inst) + 8;
4091         dec->rs1 = operand_crs1q(inst) + 8;
4092         dec->rs2 = rv_ireg_zero;
4093         dec->imm = operand_cimmd(inst);
4094         break;
4095     case rv_codec_cl_lq:
4096         dec->rd = operand_crdq(inst) + 8;
4097         dec->rs1 = operand_crs1q(inst) + 8;
4098         dec->rs2 = rv_ireg_zero;
4099         dec->imm = operand_cimmq(inst);
4100         break;
4101     case rv_codec_cr:
4102         dec->rd = dec->rs1 = operand_crs1rd(inst);
4103         dec->rs2 = operand_crs2(inst);
4104         dec->imm = 0;
4105         break;
4106     case rv_codec_cr_mv:
4107         dec->rd = operand_crd(inst);
4108         dec->rs1 = operand_crs2(inst);
4109         dec->rs2 = rv_ireg_zero;
4110         dec->imm = 0;
4111         break;
4112     case rv_codec_cr_jalr:
4113         dec->rd = rv_ireg_ra;
4114         dec->rs1 = operand_crs1(inst);
4115         dec->rs2 = rv_ireg_zero;
4116         dec->imm = 0;
4117         break;
4118     case rv_codec_cr_jr:
4119         dec->rd = rv_ireg_zero;
4120         dec->rs1 = operand_crs1(inst);
4121         dec->rs2 = rv_ireg_zero;
4122         dec->imm = 0;
4123         break;
4124     case rv_codec_cs:
4125         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4126         dec->rs2 = operand_crs2q(inst) + 8;
4127         dec->imm = 0;
4128         break;
4129     case rv_codec_cs_sw:
4130         dec->rd = rv_ireg_zero;
4131         dec->rs1 = operand_crs1q(inst) + 8;
4132         dec->rs2 = operand_crs2q(inst) + 8;
4133         dec->imm = operand_cimmw(inst);
4134         break;
4135     case rv_codec_cs_sd:
4136         dec->rd = rv_ireg_zero;
4137         dec->rs1 = operand_crs1q(inst) + 8;
4138         dec->rs2 = operand_crs2q(inst) + 8;
4139         dec->imm = operand_cimmd(inst);
4140         break;
4141     case rv_codec_cs_sq:
4142         dec->rd = rv_ireg_zero;
4143         dec->rs1 = operand_crs1q(inst) + 8;
4144         dec->rs2 = operand_crs2q(inst) + 8;
4145         dec->imm = operand_cimmq(inst);
4146         break;
4147     case rv_codec_css_swsp:
4148         dec->rd = rv_ireg_zero;
4149         dec->rs1 = rv_ireg_sp;
4150         dec->rs2 = operand_crs2(inst);
4151         dec->imm = operand_cimmswsp(inst);
4152         break;
4153     case rv_codec_css_sdsp:
4154         dec->rd = rv_ireg_zero;
4155         dec->rs1 = rv_ireg_sp;
4156         dec->rs2 = operand_crs2(inst);
4157         dec->imm = operand_cimmsdsp(inst);
4158         break;
4159     case rv_codec_css_sqsp:
4160         dec->rd = rv_ireg_zero;
4161         dec->rs1 = rv_ireg_sp;
4162         dec->rs2 = operand_crs2(inst);
4163         dec->imm = operand_cimmsqsp(inst);
4164         break;
4165     case rv_codec_k_bs:
4166         dec->rs1 = operand_rs1(inst);
4167         dec->rs2 = operand_rs2(inst);
4168         dec->bs = operand_bs(inst);
4169         break;
4170     case rv_codec_k_rnum:
4171         dec->rd = operand_rd(inst);
4172         dec->rs1 = operand_rs1(inst);
4173         dec->rnum = operand_rnum(inst);
4174         break;
4175     case rv_codec_v_r:
4176         dec->rd = operand_rd(inst);
4177         dec->rs1 = operand_rs1(inst);
4178         dec->rs2 = operand_rs2(inst);
4179         dec->vm = operand_vm(inst);
4180         break;
4181     case rv_codec_v_ldst:
4182         dec->rd = operand_rd(inst);
4183         dec->rs1 = operand_rs1(inst);
4184         dec->vm = operand_vm(inst);
4185         break;
4186     case rv_codec_v_i:
4187         dec->rd = operand_rd(inst);
4188         dec->rs2 = operand_rs2(inst);
4189         dec->imm = operand_vimm(inst);
4190         dec->vm = operand_vm(inst);
4191         break;
4192     case rv_codec_vsetvli:
4193         dec->rd = operand_rd(inst);
4194         dec->rs1 = operand_rs1(inst);
4195         dec->vzimm = operand_vzimm11(inst);
4196         break;
4197     case rv_codec_vsetivli:
4198         dec->rd = operand_rd(inst);
4199         dec->imm = operand_vimm(inst);
4200         dec->vzimm = operand_vzimm10(inst);
4201         break;
4202     };
4203 }
4204
4205 /* check constraint */
4206
4207 static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
4208 {
4209     int32_t imm = dec->imm;
4210     uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
4211     while (*c != rvc_end) {
4212         switch (*c) {
4213         case rvc_rd_eq_ra:
4214             if (!(rd == 1)) {
4215                 return false;
4216             }
4217             break;
4218         case rvc_rd_eq_x0:
4219             if (!(rd == 0)) {
4220                 return false;
4221             }
4222             break;
4223         case rvc_rs1_eq_x0:
4224             if (!(rs1 == 0)) {
4225                 return false;
4226             }
4227             break;
4228         case rvc_rs2_eq_x0:
4229             if (!(rs2 == 0)) {
4230                 return false;
4231             }
4232             break;
4233         case rvc_rs2_eq_rs1:
4234             if (!(rs2 == rs1)) {
4235                 return false;
4236             }
4237             break;
4238         case rvc_rs1_eq_ra:
4239             if (!(rs1 == 1)) {
4240                 return false;
4241             }
4242             break;
4243         case rvc_imm_eq_zero:
4244             if (!(imm == 0)) {
4245                 return false;
4246             }
4247             break;
4248         case rvc_imm_eq_n1:
4249             if (!(imm == -1)) {
4250                 return false;
4251             }
4252             break;
4253         case rvc_imm_eq_p1:
4254             if (!(imm == 1)) {
4255                 return false;
4256             }
4257             break;
4258         case rvc_csr_eq_0x001:
4259             if (!(imm == 0x001)) {
4260                 return false;
4261             }
4262             break;
4263         case rvc_csr_eq_0x002:
4264             if (!(imm == 0x002)) {
4265                 return false;
4266             }
4267             break;
4268         case rvc_csr_eq_0x003:
4269             if (!(imm == 0x003)) {
4270                 return false;
4271             }
4272             break;
4273         case rvc_csr_eq_0xc00:
4274             if (!(imm == 0xc00)) {
4275                 return false;
4276             }
4277             break;
4278         case rvc_csr_eq_0xc01:
4279             if (!(imm == 0xc01)) {
4280                 return false;
4281             }
4282             break;
4283         case rvc_csr_eq_0xc02:
4284             if (!(imm == 0xc02)) {
4285                 return false;
4286             }
4287             break;
4288         case rvc_csr_eq_0xc80:
4289             if (!(imm == 0xc80)) {
4290                 return false;
4291             }
4292             break;
4293         case rvc_csr_eq_0xc81:
4294             if (!(imm == 0xc81)) {
4295                 return false;
4296             }
4297             break;
4298         case rvc_csr_eq_0xc82:
4299             if (!(imm == 0xc82)) {
4300                 return false;
4301             }
4302             break;
4303         default: break;
4304         }
4305         c++;
4306     }
4307     return true;
4308 }
4309
4310 /* instruction length */
4311
4312 static size_t inst_length(rv_inst inst)
4313 {
4314     /* NOTE: supports maximum instruction size of 64-bits */
4315
4316     /* instruction length coding
4317      *
4318      *      aa - 16 bit aa != 11
4319      *   bbb11 - 32 bit bbb != 111
4320      *  011111 - 48 bit
4321      * 0111111 - 64 bit
4322      */
4323
4324     return (inst &      0b11) != 0b11      ? 2
4325          : (inst &   0b11100) != 0b11100   ? 4
4326          : (inst &  0b111111) == 0b011111  ? 6
4327          : (inst & 0b1111111) == 0b0111111 ? 8
4328          : 0;
4329 }
4330
4331 /* format instruction */
4332
4333 static void append(char *s1, const char *s2, size_t n)
4334 {
4335     size_t l1 = strlen(s1);
4336     if (n - l1 - 1 > 0) {
4337         strncat(s1, s2, n - l1);
4338     }
4339 }
4340
4341 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
4342 {
4343     char tmp[64];
4344     const char *fmt;
4345
4346     fmt = opcode_data[dec->op].format;
4347     while (*fmt) {
4348         switch (*fmt) {
4349         case 'O':
4350             append(buf, opcode_data[dec->op].name, buflen);
4351             break;
4352         case '(':
4353             append(buf, "(", buflen);
4354             break;
4355         case ',':
4356             append(buf, ",", buflen);
4357             break;
4358         case ')':
4359             append(buf, ")", buflen);
4360             break;
4361         case 'b':
4362             snprintf(tmp, sizeof(tmp), "%d", dec->bs);
4363             append(buf, tmp, buflen);
4364             break;
4365         case 'n':
4366             snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
4367             append(buf, tmp, buflen);
4368             break;
4369         case '0':
4370             append(buf, rv_ireg_name_sym[dec->rd], buflen);
4371             break;
4372         case '1':
4373             append(buf, rv_ireg_name_sym[dec->rs1], buflen);
4374             break;
4375         case '2':
4376             append(buf, rv_ireg_name_sym[dec->rs2], buflen);
4377             break;
4378         case '3':
4379             append(buf, rv_freg_name_sym[dec->rd], buflen);
4380             break;
4381         case '4':
4382             append(buf, rv_freg_name_sym[dec->rs1], buflen);
4383             break;
4384         case '5':
4385             append(buf, rv_freg_name_sym[dec->rs2], buflen);
4386             break;
4387         case '6':
4388             append(buf, rv_freg_name_sym[dec->rs3], buflen);
4389             break;
4390         case '7':
4391             snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
4392             append(buf, tmp, buflen);
4393             break;
4394         case 'i':
4395             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4396             append(buf, tmp, buflen);
4397             break;
4398         case 'u':
4399             snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
4400             append(buf, tmp, buflen);
4401             break;
4402         case 'o':
4403             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4404             append(buf, tmp, buflen);
4405             while (strlen(buf) < tab * 2) {
4406                 append(buf, " ", buflen);
4407             }
4408             snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
4409                 dec->pc + dec->imm);
4410             append(buf, tmp, buflen);
4411             break;
4412         case 'c': {
4413             const char *name = csr_name(dec->imm & 0xfff);
4414             if (name) {
4415                 append(buf, name, buflen);
4416             } else {
4417                 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);
4418                 append(buf, tmp, buflen);
4419             }
4420             break;
4421         }
4422         case 'r':
4423             switch (dec->rm) {
4424             case rv_rm_rne:
4425                 append(buf, "rne", buflen);
4426                 break;
4427             case rv_rm_rtz:
4428                 append(buf, "rtz", buflen);
4429                 break;
4430             case rv_rm_rdn:
4431                 append(buf, "rdn", buflen);
4432                 break;
4433             case rv_rm_rup:
4434                 append(buf, "rup", buflen);
4435                 break;
4436             case rv_rm_rmm:
4437                 append(buf, "rmm", buflen);
4438                 break;
4439             case rv_rm_dyn:
4440                 append(buf, "dyn", buflen);
4441                 break;
4442             default:
4443                 append(buf, "inv", buflen);
4444                 break;
4445             }
4446             break;
4447         case 'p':
4448             if (dec->pred & rv_fence_i) {
4449                 append(buf, "i", buflen);
4450             }
4451             if (dec->pred & rv_fence_o) {
4452                 append(buf, "o", buflen);
4453             }
4454             if (dec->pred & rv_fence_r) {
4455                 append(buf, "r", buflen);
4456             }
4457             if (dec->pred & rv_fence_w) {
4458                 append(buf, "w", buflen);
4459             }
4460             break;
4461         case 's':
4462             if (dec->succ & rv_fence_i) {
4463                 append(buf, "i", buflen);
4464             }
4465             if (dec->succ & rv_fence_o) {
4466                 append(buf, "o", buflen);
4467             }
4468             if (dec->succ & rv_fence_r) {
4469                 append(buf, "r", buflen);
4470             }
4471             if (dec->succ & rv_fence_w) {
4472                 append(buf, "w", buflen);
4473             }
4474             break;
4475         case '\t':
4476             while (strlen(buf) < tab) {
4477                 append(buf, " ", buflen);
4478             }
4479             break;
4480         case 'A':
4481             if (dec->aq) {
4482                 append(buf, ".aq", buflen);
4483             }
4484             break;
4485         case 'R':
4486             if (dec->rl) {
4487                 append(buf, ".rl", buflen);
4488             }
4489             break;
4490         case 'l':
4491             append(buf, ",v0", buflen);
4492             break;
4493         case 'm':
4494             if (dec->vm == 0) {
4495                 append(buf, ",v0.t", buflen);
4496             }
4497             break;
4498         case 'D':
4499             append(buf, rv_vreg_name_sym[dec->rd], buflen);
4500             break;
4501         case 'E':
4502             append(buf, rv_vreg_name_sym[dec->rs1], buflen);
4503             break;
4504         case 'F':
4505             append(buf, rv_vreg_name_sym[dec->rs2], buflen);
4506             break;
4507         case 'G':
4508             append(buf, rv_vreg_name_sym[dec->rs3], buflen);
4509             break;
4510         case 'v': {
4511             char nbuf[32] = {0};
4512             const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
4513             sprintf(nbuf, "%d", sew);
4514             const int lmul = dec->vzimm & 0b11;
4515             const int flmul = (dec->vzimm >> 2) & 1;
4516             const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
4517             const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
4518             append(buf, "e", buflen);
4519             append(buf, nbuf, buflen);
4520             append(buf, ",m", buflen);
4521             if (flmul) {
4522                 switch (lmul) {
4523                 case 3:
4524                     sprintf(nbuf, "f2");
4525                     break;
4526                 case 2:
4527                     sprintf(nbuf, "f4");
4528                     break;
4529                 case 1:
4530                     sprintf(nbuf, "f8");
4531                 break;
4532                 }
4533                 append(buf, nbuf, buflen);
4534             } else {
4535                 sprintf(nbuf, "%d", 1 << lmul);
4536                 append(buf, nbuf, buflen);
4537             }
4538             append(buf, ",", buflen);
4539             append(buf, vta, buflen);
4540             append(buf, ",", buflen);
4541             append(buf, vma, buflen);
4542             break;
4543         }
4544         default:
4545             break;
4546         }
4547         fmt++;
4548     }
4549 }
4550
4551 /* lift instruction to pseudo-instruction */
4552
4553 static void decode_inst_lift_pseudo(rv_decode *dec)
4554 {
4555     const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
4556     if (!comp_data) {
4557         return;
4558     }
4559     while (comp_data->constraints) {
4560         if (check_constraints(dec, comp_data->constraints)) {
4561             dec->op = comp_data->op;
4562             dec->codec = opcode_data[dec->op].codec;
4563             return;
4564         }
4565         comp_data++;
4566     }
4567 }
4568
4569 /* decompress instruction */
4570
4571 static void decode_inst_decompress_rv32(rv_decode *dec)
4572 {
4573     int decomp_op = opcode_data[dec->op].decomp_rv32;
4574     if (decomp_op != rv_op_illegal) {
4575         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4576             && dec->imm == 0) {
4577             dec->op = rv_op_illegal;
4578         } else {
4579             dec->op = decomp_op;
4580             dec->codec = opcode_data[decomp_op].codec;
4581         }
4582     }
4583 }
4584
4585 static void decode_inst_decompress_rv64(rv_decode *dec)
4586 {
4587     int decomp_op = opcode_data[dec->op].decomp_rv64;
4588     if (decomp_op != rv_op_illegal) {
4589         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4590             && dec->imm == 0) {
4591             dec->op = rv_op_illegal;
4592         } else {
4593             dec->op = decomp_op;
4594             dec->codec = opcode_data[decomp_op].codec;
4595         }
4596     }
4597 }
4598
4599 static void decode_inst_decompress_rv128(rv_decode *dec)
4600 {
4601     int decomp_op = opcode_data[dec->op].decomp_rv128;
4602     if (decomp_op != rv_op_illegal) {
4603         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4604             && dec->imm == 0) {
4605             dec->op = rv_op_illegal;
4606         } else {
4607             dec->op = decomp_op;
4608             dec->codec = opcode_data[decomp_op].codec;
4609         }
4610     }
4611 }
4612
4613 static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
4614 {
4615     switch (isa) {
4616     case rv32:
4617         decode_inst_decompress_rv32(dec);
4618         break;
4619     case rv64:
4620         decode_inst_decompress_rv64(dec);
4621         break;
4622     case rv128:
4623         decode_inst_decompress_rv128(dec);
4624         break;
4625     }
4626 }
4627
4628 /* disassemble instruction */
4629
4630 static void
4631 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
4632 {
4633     rv_decode dec = { 0 };
4634     dec.pc = pc;
4635     dec.inst = inst;
4636     decode_inst_opcode(&dec, isa);
4637     decode_inst_operands(&dec, isa);
4638     decode_inst_decompress(&dec, isa);
4639     decode_inst_lift_pseudo(&dec);
4640     format_inst(buf, buflen, 24, &dec);
4641 }
4642
4643 #define INST_FMT_2 "%04" PRIx64 "              "
4644 #define INST_FMT_4 "%08" PRIx64 "          "
4645 #define INST_FMT_6 "%012" PRIx64 "      "
4646 #define INST_FMT_8 "%016" PRIx64 "  "
4647
4648 static int
4649 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
4650 {
4651     char buf[128] = { 0 };
4652     bfd_byte packet[2];
4653     rv_inst inst = 0;
4654     size_t len = 2;
4655     bfd_vma n;
4656     int status;
4657
4658     /* Instructions are made of 2-byte packets in little-endian order */
4659     for (n = 0; n < len; n += 2) {
4660         status = (*info->read_memory_func)(memaddr + n, packet, 2, info);
4661         if (status != 0) {
4662             /* Don't fail just because we fell off the end.  */
4663             if (n > 0) {
4664                 break;
4665             }
4666             (*info->memory_error_func)(status, memaddr, info);
4667             return status;
4668         }
4669         inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n);
4670         if (n == 0) {
4671             len = inst_length(inst);
4672         }
4673     }
4674
4675     switch (len) {
4676     case 2:
4677         (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
4678         break;
4679     case 4:
4680         (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
4681         break;
4682     case 6:
4683         (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
4684         break;
4685     default:
4686         (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
4687         break;
4688     }
4689
4690     disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
4691     (*info->fprintf_func)(info->stream, "%s", buf);
4692
4693     return len;
4694 }
4695
4696 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info)
4697 {
4698     return print_insn_riscv(memaddr, info, rv32);
4699 }
4700
4701 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info)
4702 {
4703     return print_insn_riscv(memaddr, info, rv64);
4704 }
4705
4706 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
4707 {
4708     return print_insn_riscv(memaddr, info, rv128);
4709 }