hw/intc/etraxfs_pic.c

   1 /*
   2  * QEMU ETRAX Interrupt Controller.
   3  *
   4  * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "hw/hw.h"
  27 //#include "pc.h"
  28 //#include "etraxfs.h"
  29
  30 #define D(x)
  31
  32 #define R_RW_MASK   0
  33 #define R_R_VECT    1
  34 #define R_R_MASKED_VECT 2
  35 #define R_R_NMI     3
  36 #define R_R_GURU    4
  37 #define R_MAX       5
  38
  39 #define TYPE_ETRAX_FS_PIC "etraxfs,pic"
  40 #define ETRAX_FS_PIC(obj) \
  41     OBJECT_CHECK(struct etrax_pic, (obj), TYPE_ETRAX_FS_PIC)
  42
  43 struct etrax_pic
  44 {
  45     SysBusDevice parent_obj;
  46
  47     MemoryRegion mmio;
  48     void *interrupt_vector;
  49     qemu_irq parent_irq;
  50     qemu_irq parent_nmi;
  51     uint32_t regs[R_MAX];
  52 };
  53
  54 static void pic_update(struct etrax_pic *fs)
  55 {
  56     uint32_t vector = 0;
  57     int i;
  58
  59     fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
  60
  61     /* The ETRAX interrupt controller signals interrupts to the core
  62        through an interrupt request wire and an irq vector bus. If
  63        multiple interrupts are simultaneously active it chooses vector
  64        0x30 and lets the sw choose the priorities.  */
  65     if (fs->regs[R_R_MASKED_VECT]) {
  66         uint32_t mv = fs->regs[R_R_MASKED_VECT];
  67         for (i = 0; i < 31; i++) {
  68             if (mv & 1) {
  69                 vector = 0x31 + i;
  70                 /* Check for multiple interrupts.  */
  71                 if (mv > 1)
  72                     vector = 0x30;
  73                 break;
  74             }
  75             mv >>= 1;
  76         }
  77     }
  78
  79     if (fs->interrupt_vector) {
  80         /* hack alert: ptr property */
  81         *(uint32_t*)(fs->interrupt_vector) = vector;
  82     }
  83     qemu_set_irq(fs->parent_irq, !!vector);
  84 }
  85
  86 static uint64_t
  87 pic_read(void *opaque, hwaddr addr, unsigned int size)
  88 {
  89     struct etrax_pic *fs = opaque;
  90     uint32_t rval;
  91
  92     rval = fs->regs[addr >> 2];
  93     D(printf("%s %x=%x\n", __func__, addr, rval));
  94     return rval;
  95 }
  96
  97 static void pic_write(void *opaque, hwaddr addr,
  98                       uint64_t value, unsigned int size)
  99 {
 100     struct etrax_pic *fs = opaque;
 101     D(printf("%s addr=%x val=%x\n", __func__, addr, value));
 102
 103     if (addr == R_RW_MASK) {
 104         fs->regs[R_RW_MASK] = value;
 105         pic_update(fs);
 106     }
 107 }
 108
 109 static const MemoryRegionOps pic_ops = {
 110     .read = pic_read,
 111     .write = pic_write,
 112     .endianness = DEVICE_NATIVE_ENDIAN,
 113     .valid = {
 114         .min_access_size = 4,
 115         .max_access_size = 4
 116     }
 117 };
 118
 119 static void nmi_handler(void *opaque, int irq, int level)
 120 {
 121     struct etrax_pic *fs = (void *)opaque;
 122     uint32_t mask;
 123
 124     mask = 1 << irq;
 125     if (level)
 126         fs->regs[R_R_NMI] |= mask;
 127     else
 128         fs->regs[R_R_NMI] &= ~mask;
 129
 130     qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);
 131 }
 132
 133 static void irq_handler(void *opaque, int irq, int level)
 134 {
 135     struct etrax_pic *fs = (void *)opaque;
 136
 137     if (irq >= 30)
 138         return nmi_handler(opaque, irq, level);
 139
 140     irq -= 1;
 141     fs->regs[R_R_VECT] &= ~(1 << irq);
 142     fs->regs[R_R_VECT] |= (!!level << irq);
 143     pic_update(fs);
 144 }
 145
 146 static int etraxfs_pic_init(SysBusDevice *sbd)
 147 {
 148     DeviceState *dev = DEVICE(sbd);
 149     struct etrax_pic *s = ETRAX_FS_PIC(dev);
 150
 151     qdev_init_gpio_in(dev, irq_handler, 32);
 152     sysbus_init_irq(sbd, &s->parent_irq);
 153     sysbus_init_irq(sbd, &s->parent_nmi);
 154
 155     memory_region_init_io(&s->mmio, OBJECT(s), &pic_ops, s,
 156                           "etraxfs-pic", R_MAX * 4);
 157     sysbus_init_mmio(sbd, &s->mmio);
 158     return 0;
 159 }
 160
 161 static Property etraxfs_pic_properties[] = {
 162     DEFINE_PROP_PTR("interrupt_vector", struct etrax_pic, interrupt_vector),
 163     DEFINE_PROP_END_OF_LIST(),
 164 };
 165
 166 static void etraxfs_pic_class_init(ObjectClass *klass, void *data)
 167 {
 168     DeviceClass *dc = DEVICE_CLASS(klass);
 169     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 170
 171     k->init = etraxfs_pic_init;
 172     dc->props = etraxfs_pic_properties;
 173 }
 174
 175 static const TypeInfo etraxfs_pic_info = {
 176     .name          = TYPE_ETRAX_FS_PIC,
 177     .parent        = TYPE_SYS_BUS_DEVICE,
 178     .instance_size = sizeof(struct etrax_pic),
 179     .class_init    = etraxfs_pic_class_init,
 180 };
 181
 182 static void etraxfs_pic_register_types(void)
 183 {
 184     type_register_static(&etraxfs_pic_info);
 185 }
 186
 187 type_init(etraxfs_pic_register_types)