2 * QEMU model for the AXIS devboard 88.
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/sysbus.h"
27 #include "hw/block/flash.h"
28 #include "hw/boards.h"
29 #include "hw/cris/etraxfs.h"
30 #include "hw/loader.h"
33 #include "sysemu/blockdev.h"
34 #include "exec/address-spaces.h"
49 static struct nand_state_t nand_state
;
50 static uint64_t nand_read(void *opaque
, hwaddr addr
, unsigned size
)
52 struct nand_state_t
*s
= opaque
;
56 r
= nand_getio(s
->nand
);
57 nand_getpins(s
->nand
, &rdy
);
60 DNAND(printf("%s addr=%x r=%x\n", __func__
, addr
, r
));
65 nand_write(void *opaque
, hwaddr addr
, uint64_t value
,
68 struct nand_state_t
*s
= opaque
;
71 DNAND(printf("%s addr=%x v=%x\n", __func__
, addr
, (unsigned)value
));
72 nand_setpins(s
->nand
, s
->cle
, s
->ale
, s
->ce
, 1, 0);
73 nand_setio(s
->nand
, value
);
74 nand_getpins(s
->nand
, &rdy
);
78 static const MemoryRegionOps nand_ops
= {
81 .endianness
= DEVICE_NATIVE_ENDIAN
,
86 unsigned int shiftreg
;
95 static void tempsensor_clkedge(struct tempsensor_t
*s
,
96 unsigned int clk
, unsigned int data_in
)
98 D(printf("%s clk=%d state=%d sr=%x\n", __func__
,
99 clk
, s
->state
, s
->shiftreg
));
106 /* Output reg is clocked at negedge. */
128 /* Indata is sampled at posedge. */
132 s
->shiftreg
|= data_in
& 1;
134 D(printf("%s cfgreg=%x\n", __func__
, s
->shiftreg
));
135 s
->regs
[0] = s
->shiftreg
;
139 if ((s
->regs
[0] & 0xff) == 0) {
140 /* 25 degrees celcius. */
141 s
->shiftreg
= 0x0b9f;
142 } else if ((s
->regs
[0] & 0xff) == 0xff) {
143 /* Sensor ID, 0x8100 LM70. */
144 s
->shiftreg
= 0x8100;
146 printf("Invalid tempsens state %x\n", s
->regs
[0]);
154 #define RW_PA_DOUT 0x00
155 #define R_PA_DIN 0x01
156 #define RW_PA_OE 0x02
157 #define RW_PD_DOUT 0x10
158 #define R_PD_DIN 0x11
159 #define RW_PD_OE 0x12
161 static struct gpio_state_t
164 struct nand_state_t
*nand
;
165 struct tempsensor_t tempsensor
;
166 uint32_t regs
[0x5c / 4];
169 static uint64_t gpio_read(void *opaque
, hwaddr addr
, unsigned size
)
171 struct gpio_state_t
*s
= opaque
;
178 r
= s
->regs
[RW_PA_DOUT
] & s
->regs
[RW_PA_OE
];
180 /* Encode pins from the nand. */
181 r
|= s
->nand
->rdy
<< 7;
184 r
= s
->regs
[RW_PD_DOUT
] & s
->regs
[RW_PD_OE
];
186 /* Encode temp sensor pins. */
187 r
|= (!!(s
->tempsensor
.shiftreg
& 0x10000)) << 4;
195 D(printf("%s %x=%x\n", __func__
, addr
, r
));
198 static void gpio_write(void *opaque
, hwaddr addr
, uint64_t value
,
201 struct gpio_state_t
*s
= opaque
;
202 D(printf("%s %x=%x\n", __func__
, addr
, (unsigned)value
));
208 /* Decode nand pins. */
209 s
->nand
->ale
= !!(value
& (1 << 6));
210 s
->nand
->cle
= !!(value
& (1 << 5));
211 s
->nand
->ce
= !!(value
& (1 << 4));
213 s
->regs
[addr
] = value
;
217 /* Temp sensor clk. */
218 if ((s
->regs
[addr
] ^ value
) & 2)
219 tempsensor_clkedge(&s
->tempsensor
, !!(value
& 2),
221 s
->regs
[addr
] = value
;
225 s
->regs
[addr
] = value
;
230 static const MemoryRegionOps gpio_ops
= {
233 .endianness
= DEVICE_NATIVE_ENDIAN
,
235 .min_access_size
= 4,
236 .max_access_size
= 4,
240 #define INTMEM_SIZE (128 * 1024)
242 static struct cris_load_info li
;
245 void axisdev88_init(QEMUMachineInitArgs
*args
)
247 ram_addr_t ram_size
= args
->ram_size
;
248 const char *cpu_model
= args
->cpu_model
;
249 const char *kernel_filename
= args
->kernel_filename
;
250 const char *kernel_cmdline
= args
->kernel_cmdline
;
256 qemu_irq irq
[30], nmi
[2], *cpu_irq
;
258 struct etraxfs_dma_client
*dma_eth
;
260 MemoryRegion
*address_space_mem
= get_system_memory();
261 MemoryRegion
*phys_ram
= g_new(MemoryRegion
, 1);
262 MemoryRegion
*phys_intmem
= g_new(MemoryRegion
, 1);
265 if (cpu_model
== NULL
) {
266 cpu_model
= "crisv32";
268 cpu
= cpu_cris_init(cpu_model
);
272 memory_region_init_ram(phys_ram
, NULL
, "axisdev88.ram", ram_size
);
273 vmstate_register_ram_global(phys_ram
);
274 memory_region_add_subregion(address_space_mem
, 0x40000000, phys_ram
);
276 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
278 memory_region_init_ram(phys_intmem
, NULL
, "axisdev88.chipram", INTMEM_SIZE
);
279 vmstate_register_ram_global(phys_intmem
);
280 memory_region_add_subregion(address_space_mem
, 0x38000000, phys_intmem
);
282 /* Attach a NAND flash to CS1. */
283 nand
= drive_get(IF_MTD
, 0, 0);
284 nand_state
.nand
= nand_init(nand
? nand
->bdrv
: NULL
,
285 NAND_MFR_STMICRO
, 0x39);
286 memory_region_init_io(&nand_state
.iomem
, NULL
, &nand_ops
, &nand_state
,
288 memory_region_add_subregion(address_space_mem
, 0x10000000,
291 gpio_state
.nand
= &nand_state
;
292 memory_region_init_io(&gpio_state
.iomem
, NULL
, &gpio_ops
, &gpio_state
,
294 memory_region_add_subregion(address_space_mem
, 0x3001a000,
298 cpu_irq
= cris_pic_init_cpu(env
);
299 dev
= qdev_create(NULL
, "etraxfs,pic");
300 /* FIXME: Is there a proper way to signal vectors to the CPU core? */
301 qdev_prop_set_ptr(dev
, "interrupt_vector", &env
->interrupt_vector
);
302 qdev_init_nofail(dev
);
303 s
= SYS_BUS_DEVICE(dev
);
304 sysbus_mmio_map(s
, 0, 0x3001c000);
305 sysbus_connect_irq(s
, 0, cpu_irq
[0]);
306 sysbus_connect_irq(s
, 1, cpu_irq
[1]);
307 for (i
= 0; i
< 30; i
++) {
308 irq
[i
] = qdev_get_gpio_in(dev
, i
);
310 nmi
[0] = qdev_get_gpio_in(dev
, 30);
311 nmi
[1] = qdev_get_gpio_in(dev
, 31);
313 etraxfs_dmac
= etraxfs_dmac_init(0x30000000, 10);
314 for (i
= 0; i
< 10; i
++) {
315 /* On ETRAX, odd numbered channels are inputs. */
316 etraxfs_dmac_connect(etraxfs_dmac
, i
, irq
+ 7 + i
, i
& 1);
319 /* Add the two ethernet blocks. */
320 dma_eth
= g_malloc0(sizeof dma_eth
[0] * 4); /* Allocate 4 channels. */
321 etraxfs_eth_init(&nd_table
[0], 0x30034000, 1, &dma_eth
[0], &dma_eth
[1]);
323 etraxfs_eth_init(&nd_table
[1], 0x30036000, 2, &dma_eth
[2], &dma_eth
[3]);
326 /* The DMA Connector block is missing, hardwire things for now. */
327 etraxfs_dmac_connect_client(etraxfs_dmac
, 0, &dma_eth
[0]);
328 etraxfs_dmac_connect_client(etraxfs_dmac
, 1, &dma_eth
[1]);
330 etraxfs_dmac_connect_client(etraxfs_dmac
, 6, &dma_eth
[2]);
331 etraxfs_dmac_connect_client(etraxfs_dmac
, 7, &dma_eth
[3]);
335 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq
[0x1b], nmi
[1], NULL
);
336 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq
[0x1b], nmi
[1], NULL
);
338 for (i
= 0; i
< 4; i
++) {
339 sysbus_create_simple("etraxfs,serial", 0x30026000 + i
* 0x2000,
343 if (!kernel_filename
) {
344 fprintf(stderr
, "Kernel image must be specified\n");
348 li
.image_filename
= kernel_filename
;
349 li
.cmdline
= kernel_cmdline
;
350 cris_load_image(cpu
, &li
);
353 static QEMUMachine axisdev88_machine
= {
354 .name
= "axis-dev88",
355 .desc
= "AXIS devboard 88",
356 .init
= axisdev88_init
,
360 static void axisdev88_machine_init(void)
362 qemu_register_machine(&axisdev88_machine
);
365 machine_init(axisdev88_machine_init
);