target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "helper.h"
  30 #include "qemu/host-utils.h"
  31
  32 static void do_unaligned_access(CPUXtensaState *env,
  33         target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
  34
  35 #define ALIGNED_ONLY
  36 #define MMUSUFFIX _mmu
  37
  38 #define SHIFT 0
  39 #include "exec/softmmu_template.h"
  40
  41 #define SHIFT 1
  42 #include "exec/softmmu_template.h"
  43
  44 #define SHIFT 2
  45 #include "exec/softmmu_template.h"
  46
  47 #define SHIFT 3
  48 #include "exec/softmmu_template.h"
  49
  50 static void do_unaligned_access(CPUXtensaState *env,
  51         target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
  52 {
  53     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  54             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  55         cpu_restore_state(env, retaddr);
  56         HELPER(exception_cause_vaddr)(env,
  57                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  58     }
  59 }
  60
  61 void tlb_fill(CPUXtensaState *env,
  62         target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  63 {
  64     uint32_t paddr;
  65     uint32_t page_size;
  66     unsigned access;
  67     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  68             &paddr, &page_size, &access);
  69
  70     qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  71             vaddr, is_write, mmu_idx, paddr, ret);
  72
  73     if (ret == 0) {
  74         tlb_set_page(env,
  75                 vaddr & TARGET_PAGE_MASK,
  76                 paddr & TARGET_PAGE_MASK,
  77                 access, mmu_idx, page_size);
  78     } else {
  79         cpu_restore_state(env, retaddr);
  80         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  81     }
  82 }
  83
  84 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  85 {
  86     uint32_t paddr;
  87     uint32_t page_size;
  88     unsigned access;
  89     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  90             &paddr, &page_size, &access);
  91     if (ret == 0) {
  92         tb_invalidate_phys_addr(paddr);
  93     }
  94 }
  95
  96 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
  97 {
  98     env->exception_index = excp;
  99     cpu_loop_exit(env);
 100 }
 101
 102 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 103 {
 104     uint32_t vector;
 105
 106     env->pc = pc;
 107     if (env->sregs[PS] & PS_EXCM) {
 108         if (env->config->ndepc) {
 109             env->sregs[DEPC] = pc;
 110         } else {
 111             env->sregs[EPC1] = pc;
 112         }
 113         vector = EXC_DOUBLE;
 114     } else {
 115         env->sregs[EPC1] = pc;
 116         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 117     }
 118
 119     env->sregs[EXCCAUSE] = cause;
 120     env->sregs[PS] |= PS_EXCM;
 121
 122     HELPER(exception)(env, vector);
 123 }
 124
 125 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 126         uint32_t pc, uint32_t cause, uint32_t vaddr)
 127 {
 128     env->sregs[EXCVADDR] = vaddr;
 129     HELPER(exception_cause)(env, pc, cause);
 130 }
 131
 132 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 133 {
 134     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 135         HELPER(debug_exception)(env, env->pc, cause);
 136     }
 137 }
 138
 139 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 140 {
 141     unsigned level = env->config->debug_level;
 142
 143     env->pc = pc;
 144     env->sregs[DEBUGCAUSE] = cause;
 145     env->sregs[EPC1 + level - 1] = pc;
 146     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 147     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 148         (level << PS_INTLEVEL_SHIFT);
 149     HELPER(exception)(env, EXC_DEBUG);
 150 }
 151
 152 uint32_t HELPER(nsa)(uint32_t v)
 153 {
 154     if (v & 0x80000000) {
 155         v = ~v;
 156     }
 157     return v ? clz32(v) - 1 : 31;
 158 }
 159
 160 uint32_t HELPER(nsau)(uint32_t v)
 161 {
 162     return v ? clz32(v) : 32;
 163 }
 164
 165 static void copy_window_from_phys(CPUXtensaState *env,
 166         uint32_t window, uint32_t phys, uint32_t n)
 167 {
 168     assert(phys < env->config->nareg);
 169     if (phys + n <= env->config->nareg) {
 170         memcpy(env->regs + window, env->phys_regs + phys,
 171                 n * sizeof(uint32_t));
 172     } else {
 173         uint32_t n1 = env->config->nareg - phys;
 174         memcpy(env->regs + window, env->phys_regs + phys,
 175                 n1 * sizeof(uint32_t));
 176         memcpy(env->regs + window + n1, env->phys_regs,
 177                 (n - n1) * sizeof(uint32_t));
 178     }
 179 }
 180
 181 static void copy_phys_from_window(CPUXtensaState *env,
 182         uint32_t phys, uint32_t window, uint32_t n)
 183 {
 184     assert(phys < env->config->nareg);
 185     if (phys + n <= env->config->nareg) {
 186         memcpy(env->phys_regs + phys, env->regs + window,
 187                 n * sizeof(uint32_t));
 188     } else {
 189         uint32_t n1 = env->config->nareg - phys;
 190         memcpy(env->phys_regs + phys, env->regs + window,
 191                 n1 * sizeof(uint32_t));
 192         memcpy(env->phys_regs, env->regs + window + n1,
 193                 (n - n1) * sizeof(uint32_t));
 194     }
 195 }
 196
 197
 198 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 199 {
 200     return a & (env->config->nareg / 4 - 1);
 201 }
 202
 203 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 204 {
 205     return 1 << windowbase_bound(a, env);
 206 }
 207
 208 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 209 {
 210     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 211 }
 212
 213 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 214 {
 215     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 216 }
 217
 218 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 219 {
 220     xtensa_sync_phys_from_window(env);
 221     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 222     xtensa_sync_window_from_phys(env);
 223 }
 224
 225 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 226 {
 227     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 228 }
 229
 230 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 231 {
 232     rotate_window_abs(env, v);
 233 }
 234
 235 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 236 {
 237     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 238     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 239         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 240                 pc, env->sregs[PS]);
 241         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 242     } else {
 243         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 244         rotate_window(env, callinc);
 245         env->sregs[WINDOW_START] |=
 246             windowstart_bit(env->sregs[WINDOW_BASE], env);
 247     }
 248 }
 249
 250 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 251 {
 252     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 253     uint32_t windowstart = env->sregs[WINDOW_START];
 254     uint32_t m, n;
 255
 256     if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
 257         return;
 258     }
 259
 260     for (n = 1; ; ++n) {
 261         if (n > w) {
 262             return;
 263         }
 264         if (windowstart & windowstart_bit(windowbase + n, env)) {
 265             break;
 266         }
 267     }
 268
 269     m = windowbase_bound(windowbase + n, env);
 270     rotate_window(env, n);
 271     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 272         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 273     env->sregs[EPC1] = env->pc = pc;
 274
 275     if (windowstart & windowstart_bit(m + 1, env)) {
 276         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 277     } else if (windowstart & windowstart_bit(m + 2, env)) {
 278         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 279     } else {
 280         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 281     }
 282 }
 283
 284 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 285 {
 286     int n = (env->regs[0] >> 30) & 0x3;
 287     int m = 0;
 288     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 289     uint32_t windowstart = env->sregs[WINDOW_START];
 290     uint32_t ret_pc = 0;
 291
 292     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 293         m = 1;
 294     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 295         m = 2;
 296     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 297         m = 3;
 298     }
 299
 300     if (n == 0 || (m != 0 && m != n) ||
 301             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 302         qemu_log("Illegal retw instruction(pc = %08x), "
 303                 "PS = %08x, m = %d, n = %d\n",
 304                 pc, env->sregs[PS], m, n);
 305         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 306     } else {
 307         int owb = windowbase;
 308
 309         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 310
 311         rotate_window(env, -n);
 312         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 313             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 314         } else {
 315             /* window underflow */
 316             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 317                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 318             env->sregs[EPC1] = env->pc = pc;
 319
 320             if (n == 1) {
 321                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 322             } else if (n == 2) {
 323                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 324             } else if (n == 3) {
 325                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 326             }
 327         }
 328     }
 329     return ret_pc;
 330 }
 331
 332 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 333 {
 334     rotate_window(env, imm4);
 335 }
 336
 337 void HELPER(restore_owb)(CPUXtensaState *env)
 338 {
 339     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 340 }
 341
 342 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 343 {
 344     if ((env->sregs[WINDOW_START] &
 345             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 346              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 347              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 348         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 349     }
 350 }
 351
 352 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 353 {
 354     if (env->sregs[LBEG] != v) {
 355         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 356         env->sregs[LBEG] = v;
 357     }
 358 }
 359
 360 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 361 {
 362     if (env->sregs[LEND] != v) {
 363         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 364         env->sregs[LEND] = v;
 365         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 366     }
 367 }
 368
 369 void HELPER(dump_state)(CPUXtensaState *env)
 370 {
 371     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 372
 373     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
 374 }
 375
 376 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 377 {
 378     CPUState *cpu;
 379
 380     env->pc = pc;
 381     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 382         (intlevel << PS_INTLEVEL_SHIFT);
 383     check_interrupts(env);
 384     if (env->pending_irq_level) {
 385         cpu_loop_exit(env);
 386         return;
 387     }
 388
 389     cpu = CPU(xtensa_env_get_cpu(env));
 390     env->halt_clock = qemu_get_clock_ns(vm_clock);
 391     cpu->halted = 1;
 392     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 393         xtensa_rearm_ccompare_timer(env);
 394     }
 395     HELPER(exception)(env, EXCP_HLT);
 396 }
 397
 398 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 399 {
 400     xtensa_timer_irq(env, id, active);
 401 }
 402
 403 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 404 {
 405     xtensa_advance_ccount(env, d);
 406 }
 407
 408 void HELPER(check_interrupts)(CPUXtensaState *env)
 409 {
 410     check_interrupts(env);
 411 }
 412
 413 /*!
 414  * Check vaddr accessibility/cache attributes and raise an exception if
 415  * specified by the ATOMCTL SR.
 416  *
 417  * Note: local memory exclusion is not implemented
 418  */
 419 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 420 {
 421     uint32_t paddr, page_size, access;
 422     uint32_t atomctl = env->sregs[ATOMCTL];
 423     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 424             xtensa_get_cring(env), &paddr, &page_size, &access);
 425
 426     /*
 427      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 428      * see opcode description in the ISA
 429      */
 430     if (rc == 0 &&
 431             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 432         rc = STORE_PROHIBITED_CAUSE;
 433     }
 434
 435     if (rc) {
 436         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 437     }
 438
 439     /*
 440      * When data cache is not configured use ATOMCTL bypass field.
 441      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 442      * under the Conditional Store Option.
 443      */
 444     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 445         access = PAGE_CACHE_BYPASS;
 446     }
 447
 448     switch (access & PAGE_CACHE_MASK) {
 449     case PAGE_CACHE_WB:
 450         atomctl >>= 2;
 451     case PAGE_CACHE_WT:
 452         atomctl >>= 2;
 453     case PAGE_CACHE_BYPASS:
 454         if ((atomctl & 0x3) == 0) {
 455             HELPER(exception_cause_vaddr)(env, pc,
 456                     LOAD_STORE_ERROR_CAUSE, vaddr);
 457         }
 458         break;
 459
 460     case PAGE_CACHE_ISOLATE:
 461         HELPER(exception_cause_vaddr)(env, pc,
 462                 LOAD_STORE_ERROR_CAUSE, vaddr);
 463         break;
 464
 465     default:
 466         break;
 467     }
 468 }
 469
 470 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 471 {
 472     v = (v & 0xffffff00) | 0x1;
 473     if (v != env->sregs[RASID]) {
 474         env->sregs[RASID] = v;
 475         tlb_flush(env, 1);
 476     }
 477 }
 478
 479 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 480 {
 481     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 482
 483     switch (way) {
 484     case 4:
 485         return (tlbcfg >> 16) & 0x3;
 486
 487     case 5:
 488         return (tlbcfg >> 20) & 0x1;
 489
 490     case 6:
 491         return (tlbcfg >> 24) & 0x1;
 492
 493     default:
 494         return 0;
 495     }
 496 }
 497
 498 /*!
 499  * Get bit mask for the virtual address bits translated by the TLB way
 500  */
 501 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 502 {
 503     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 504         bool varway56 = dtlb ?
 505             env->config->dtlb.varway56 :
 506             env->config->itlb.varway56;
 507
 508         switch (way) {
 509         case 4:
 510             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 511
 512         case 5:
 513             if (varway56) {
 514                 return 0xf8000000 << get_page_size(env, dtlb, way);
 515             } else {
 516                 return 0xf8000000;
 517             }
 518
 519         case 6:
 520             if (varway56) {
 521                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 522             } else {
 523                 return 0xf0000000;
 524             }
 525
 526         default:
 527             return 0xfffff000;
 528         }
 529     } else {
 530         return REGION_PAGE_MASK;
 531     }
 532 }
 533
 534 /*!
 535  * Get bit mask for the 'VPN without index' field.
 536  * See ISA, 4.6.5.6, data format for RxTLB0
 537  */
 538 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 539 {
 540     if (way < 4) {
 541         bool is32 = (dtlb ?
 542                 env->config->dtlb.nrefillentries :
 543                 env->config->itlb.nrefillentries) == 32;
 544         return is32 ? 0xffff8000 : 0xffffc000;
 545     } else if (way == 4) {
 546         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 547     } else if (way <= 6) {
 548         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 549         bool varway56 = dtlb ?
 550             env->config->dtlb.varway56 :
 551             env->config->itlb.varway56;
 552
 553         if (varway56) {
 554             return mask << (way == 5 ? 2 : 3);
 555         } else {
 556             return mask << 1;
 557         }
 558     } else {
 559         return 0xfffff000;
 560     }
 561 }
 562
 563 /*!
 564  * Split virtual address into VPN (with index) and entry index
 565  * for the given TLB way
 566  */
 567 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 568         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 569 {
 570     bool varway56 = dtlb ?
 571         env->config->dtlb.varway56 :
 572         env->config->itlb.varway56;
 573
 574     if (!dtlb) {
 575         wi &= 7;
 576     }
 577
 578     if (wi < 4) {
 579         bool is32 = (dtlb ?
 580                 env->config->dtlb.nrefillentries :
 581                 env->config->itlb.nrefillentries) == 32;
 582         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 583     } else {
 584         switch (wi) {
 585         case 4:
 586             {
 587                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 588                 *ei = (v >> eibase) & 0x3;
 589             }
 590             break;
 591
 592         case 5:
 593             if (varway56) {
 594                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 595                 *ei = (v >> eibase) & 0x3;
 596             } else {
 597                 *ei = (v >> 27) & 0x1;
 598             }
 599             break;
 600
 601         case 6:
 602             if (varway56) {
 603                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 604                 *ei = (v >> eibase) & 0x7;
 605             } else {
 606                 *ei = (v >> 28) & 0x1;
 607             }
 608             break;
 609
 610         default:
 611             *ei = 0;
 612             break;
 613         }
 614     }
 615     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 616 }
 617
 618 /*!
 619  * Split TLB address into TLB way, entry index and VPN (with index).
 620  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 621  */
 622 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 623         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 624 {
 625     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 626         *wi = v & (dtlb ? 0xf : 0x7);
 627         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 628     } else {
 629         *vpn = v & REGION_PAGE_MASK;
 630         *wi = 0;
 631         *ei = (v >> 29) & 0x7;
 632     }
 633 }
 634
 635 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 636         uint32_t v, bool dtlb, uint32_t *pwi)
 637 {
 638     uint32_t vpn;
 639     uint32_t wi;
 640     uint32_t ei;
 641
 642     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 643     if (pwi) {
 644         *pwi = wi;
 645     }
 646     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 647 }
 648
 649 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 650 {
 651     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 652         uint32_t wi;
 653         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 654         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 655     } else {
 656         return v & REGION_PAGE_MASK;
 657     }
 658 }
 659
 660 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 661 {
 662     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 663     return entry->paddr | entry->attr;
 664 }
 665
 666 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 667 {
 668     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 669         uint32_t wi;
 670         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 671         if (entry->variable && entry->asid) {
 672             tlb_flush_page(env, entry->vaddr);
 673             entry->asid = 0;
 674         }
 675     }
 676 }
 677
 678 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 679 {
 680     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 681         uint32_t wi;
 682         uint32_t ei;
 683         uint8_t ring;
 684         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 685
 686         switch (res) {
 687         case 0:
 688             if (ring >= xtensa_get_ring(env)) {
 689                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 690             }
 691             break;
 692
 693         case INST_TLB_MULTI_HIT_CAUSE:
 694         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 695             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 696             break;
 697         }
 698         return 0;
 699     } else {
 700         return (v & REGION_PAGE_MASK) | 0x1;
 701     }
 702 }
 703
 704 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 705         xtensa_tlb_entry *entry, bool dtlb,
 706         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 707 {
 708     entry->vaddr = vpn;
 709     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 710     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 711     entry->attr = pte & 0xf;
 712 }
 713
 714 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 715         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 716 {
 717     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 718
 719     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 720         if (entry->variable) {
 721             if (entry->asid) {
 722                 tlb_flush_page(env, entry->vaddr);
 723             }
 724             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 725             tlb_flush_page(env, entry->vaddr);
 726         } else {
 727             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 728                     __func__, dtlb, wi, ei);
 729         }
 730     } else {
 731         tlb_flush_page(env, entry->vaddr);
 732         if (xtensa_option_enabled(env->config,
 733                     XTENSA_OPTION_REGION_TRANSLATION)) {
 734             entry->paddr = pte & REGION_PAGE_MASK;
 735         }
 736         entry->attr = pte & 0xf;
 737     }
 738 }
 739
 740 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 741 {
 742     uint32_t vpn;
 743     uint32_t wi;
 744     uint32_t ei;
 745     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 746     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 747 }
 748
 749
 750 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 751 {
 752     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 753     unsigned i;
 754
 755     for (i = 0; i < env->config->nibreak; ++i) {
 756         if (change & (1 << i)) {
 757             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 758         }
 759     }
 760     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 761 }
 762
 763 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 764 {
 765     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 766         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 767         tb_invalidate_virtual_addr(env, v);
 768     }
 769     env->sregs[IBREAKA + i] = v;
 770 }
 771
 772 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 773         uint32_t dbreakc)
 774 {
 775     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 776     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 777
 778     if (env->cpu_watchpoint[i]) {
 779         cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 780     }
 781     if (dbreakc & DBREAKC_SB) {
 782         flags |= BP_MEM_WRITE;
 783     }
 784     if (dbreakc & DBREAKC_LB) {
 785         flags |= BP_MEM_READ;
 786     }
 787     /* contiguous mask after inversion is one less than some power of 2 */
 788     if ((~mask + 1) & ~mask) {
 789         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 790         /* cut mask after the first zero bit */
 791         mask = 0xffffffff << (32 - clo32(mask));
 792     }
 793     if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1,
 794             flags, &env->cpu_watchpoint[i])) {
 795         env->cpu_watchpoint[i] = NULL;
 796         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 797                 dbreaka & mask, ~mask + 1);
 798     }
 799 }
 800
 801 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 802 {
 803     uint32_t dbreakc = env->sregs[DBREAKC + i];
 804
 805     if ((dbreakc & DBREAKC_SB_LB) &&
 806             env->sregs[DBREAKA + i] != v) {
 807         set_dbreak(env, i, v, dbreakc);
 808     }
 809     env->sregs[DBREAKA + i] = v;
 810 }
 811
 812 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 813 {
 814     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 815         if (v & DBREAKC_SB_LB) {
 816             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 817         } else {
 818             if (env->cpu_watchpoint[i]) {
 819                 cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 820                 env->cpu_watchpoint[i] = NULL;
 821             }
 822         }
 823     }
 824     env->sregs[DBREAKC + i] = v;
 825 }
 826
 827 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 828 {
 829     static const int rounding_mode[] = {
 830         float_round_nearest_even,
 831         float_round_to_zero,
 832         float_round_up,
 833         float_round_down,
 834     };
 835
 836     env->uregs[FCR] = v & 0xfffff07f;
 837     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 838 }
 839
 840 float32 HELPER(abs_s)(float32 v)
 841 {
 842     return float32_abs(v);
 843 }
 844
 845 float32 HELPER(neg_s)(float32 v)
 846 {
 847     return float32_chs(v);
 848 }
 849
 850 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 851 {
 852     return float32_add(a, b, &env->fp_status);
 853 }
 854
 855 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 856 {
 857     return float32_sub(a, b, &env->fp_status);
 858 }
 859
 860 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 861 {
 862     return float32_mul(a, b, &env->fp_status);
 863 }
 864
 865 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 866 {
 867     return float32_muladd(b, c, a, 0,
 868             &env->fp_status);
 869 }
 870
 871 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 872 {
 873     return float32_muladd(b, c, a, float_muladd_negate_product,
 874             &env->fp_status);
 875 }
 876
 877 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 878 {
 879     float_status fp_status = {0};
 880
 881     set_float_rounding_mode(rounding_mode, &fp_status);
 882     return float32_to_int32(
 883             float32_scalbn(v, scale, &fp_status), &fp_status);
 884 }
 885
 886 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 887 {
 888     float_status fp_status = {0};
 889     float32 res;
 890
 891     set_float_rounding_mode(rounding_mode, &fp_status);
 892
 893     res = float32_scalbn(v, scale, &fp_status);
 894
 895     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 896         return float32_to_int32(res, &fp_status);
 897     } else {
 898         return float32_to_uint32(res, &fp_status);
 899     }
 900 }
 901
 902 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 903 {
 904     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 905             (int32_t)scale, &env->fp_status);
 906 }
 907
 908 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 909 {
 910     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 911             (int32_t)scale, &env->fp_status);
 912 }
 913
 914 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 915 {
 916     if (v) {
 917         env->sregs[BR] |= br;
 918     } else {
 919         env->sregs[BR] &= ~br;
 920     }
 921 }
 922
 923 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 924 {
 925     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 926 }
 927
 928 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 929 {
 930     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 931 }
 932
 933 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 934 {
 935     int v = float32_compare_quiet(a, b, &env->fp_status);
 936     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 937 }
 938
 939 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 940 {
 941     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 942 }
 943
 944 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 945 {
 946     int v = float32_compare_quiet(a, b, &env->fp_status);
 947     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 948 }
 949
 950 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 951 {
 952     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 953 }
 954
 955 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 956 {
 957     int v = float32_compare_quiet(a, b, &env->fp_status);
 958     set_br(env, v != float_relation_greater, br);
 959 }