target/ppc/helper_regs.c

   1 /*
   2  *  PowerPC emulation special registers manipulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/main-loop.h"
  22 #include "exec/exec-all.h"
  23 #include "sysemu/kvm.h"
  24 #include "helper_regs.h"
  25
  26 /* Swap temporary saved registers with GPRs */
  27 void hreg_swap_gpr_tgpr(CPUPPCState *env)
  28 {
  29     target_ulong tmp;
  30
  31     tmp = env->gpr[0];
  32     env->gpr[0] = env->tgpr[0];
  33     env->tgpr[0] = tmp;
  34     tmp = env->gpr[1];
  35     env->gpr[1] = env->tgpr[1];
  36     env->tgpr[1] = tmp;
  37     tmp = env->gpr[2];
  38     env->gpr[2] = env->tgpr[2];
  39     env->tgpr[2] = tmp;
  40     tmp = env->gpr[3];
  41     env->gpr[3] = env->tgpr[3];
  42     env->tgpr[3] = tmp;
  43 }
  44
  45 void hreg_compute_mem_idx(CPUPPCState *env)
  46 {
  47     /*
  48      * This is our encoding for server processors. The architecture
  49      * specifies that there is no such thing as userspace with
  50      * translation off, however it appears that MacOS does it and some
  51      * 32-bit CPUs support it. Weird...
  52      *
  53      *   0 = Guest User space virtual mode
  54      *   1 = Guest Kernel space virtual mode
  55      *   2 = Guest User space real mode
  56      *   3 = Guest Kernel space real mode
  57      *   4 = HV User space virtual mode
  58      *   5 = HV Kernel space virtual mode
  59      *   6 = HV User space real mode
  60      *   7 = HV Kernel space real mode
  61      *
  62      * For BookE, we need 8 MMU modes as follow:
  63      *
  64      *  0 = AS 0 HV User space
  65      *  1 = AS 0 HV Kernel space
  66      *  2 = AS 1 HV User space
  67      *  3 = AS 1 HV Kernel space
  68      *  4 = AS 0 Guest User space
  69      *  5 = AS 0 Guest Kernel space
  70      *  6 = AS 1 Guest User space
  71      *  7 = AS 1 Guest Kernel space
  72      */
  73     if (env->mmu_model & POWERPC_MMU_BOOKE) {
  74         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  75         env->immu_idx += msr_is ? 2 : 0;
  76         env->dmmu_idx += msr_ds ? 2 : 0;
  77         env->immu_idx += msr_gs ? 4 : 0;
  78         env->dmmu_idx += msr_gs ? 4 : 0;
  79     } else {
  80         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  81         env->immu_idx += msr_ir ? 0 : 2;
  82         env->dmmu_idx += msr_dr ? 0 : 2;
  83         env->immu_idx += msr_hv ? 4 : 0;
  84         env->dmmu_idx += msr_hv ? 4 : 0;
  85     }
  86 }
  87
  88 void hreg_compute_hflags(CPUPPCState *env)
  89 {
  90     target_ulong hflags_mask;
  91
  92     /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
  93     hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
  94         (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
  95         (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
  96     hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
  97     hreg_compute_mem_idx(env);
  98     env->hflags = env->msr & hflags_mask;
  99
 100     if (env->flags & POWERPC_FLAG_HID0_LE) {
 101         /*
 102          * Note that MSR_LE is not set in env->msr_mask for this cpu,
 103          * and so will never be set in msr or hflags at this point.
 104          */
 105         uint32_t le = extract32(env->spr[SPR_HID0], 3, 1);
 106         env->hflags |= le << MSR_LE;
 107         /* Retain for backward compatibility with migration. */
 108         env->hflags_nmsr = le << MSR_LE;
 109     }
 110 }
 111
 112 void cpu_interrupt_exittb(CPUState *cs)
 113 {
 114     if (!kvm_enabled()) {
 115         return;
 116     }
 117
 118     if (!qemu_mutex_iothread_locked()) {
 119         qemu_mutex_lock_iothread();
 120         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 121         qemu_mutex_unlock_iothread();
 122     } else {
 123         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 124     }
 125 }
 126
 127 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
 128 {
 129     int excp;
 130 #if !defined(CONFIG_USER_ONLY)
 131     CPUState *cs = env_cpu(env);
 132 #endif
 133
 134     excp = 0;
 135     value &= env->msr_mask;
 136 #if !defined(CONFIG_USER_ONLY)
 137     /* Neither mtmsr nor guest state can alter HV */
 138     if (!alter_hv || !(env->msr & MSR_HVB)) {
 139         value &= ~MSR_HVB;
 140         value |= env->msr & MSR_HVB;
 141     }
 142     if (((value >> MSR_IR) & 1) != msr_ir ||
 143         ((value >> MSR_DR) & 1) != msr_dr) {
 144         cpu_interrupt_exittb(cs);
 145     }
 146     if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
 147         ((value >> MSR_GS) & 1) != msr_gs) {
 148         cpu_interrupt_exittb(cs);
 149     }
 150     if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 151                  ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 152         /* Swap temporary saved registers with GPRs */
 153         hreg_swap_gpr_tgpr(env);
 154     }
 155     if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
 156         /* Change the exception prefix on PowerPC 601 */
 157         env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
 158     }
 159     /*
 160      * If PR=1 then EE, IR and DR must be 1
 161      *
 162      * Note: We only enforce this on 64-bit server processors.
 163      * It appears that:
 164      * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 165      *   exploits it.
 166      * - 64-bit embedded implementations do not need any operation to be
 167      *   performed when PR is set.
 168      */
 169     if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
 170         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 171     }
 172 #endif
 173     env->msr = value;
 174     hreg_compute_hflags(env);
 175 #if !defined(CONFIG_USER_ONLY)
 176     if (unlikely(msr_pow == 1)) {
 177         if (!env->pending_interrupts && (*env->check_pow)(env)) {
 178             cs->halted = 1;
 179             excp = EXCP_HALTED;
 180         }
 181     }
 182 #endif
 183
 184     return excp;
 185 }
 186
 187 #ifndef CONFIG_USER_ONLY
 188 void check_tlb_flush(CPUPPCState *env, bool global)
 189 {
 190     CPUState *cs = env_cpu(env);
 191
 192     /* Handle global flushes first */
 193     if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 194         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 195         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 196         tlb_flush_all_cpus_synced(cs);
 197         return;
 198     }
 199
 200     /* Then handle local ones */
 201     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 202         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 203         tlb_flush(cs);
 204     }
 205 }
 206 #endif