4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
17 #include "exec/address-spaces.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
21 #include "hw/i2c/aspeed_i2c.h"
24 #define ASPEED_SOC_UART_5_BASE 0x00184000
25 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
26 #define ASPEED_SOC_IOMEM_BASE 0x1E600000
27 #define ASPEED_SOC_FMC_BASE 0x1E620000
28 #define ASPEED_SOC_SPI_BASE 0x1E630000
29 #define ASPEED_SOC_SPI2_BASE 0x1E631000
30 #define ASPEED_SOC_VIC_BASE 0x1E6C0000
31 #define ASPEED_SOC_SDMC_BASE 0x1E6E0000
32 #define ASPEED_SOC_SCU_BASE 0x1E6E2000
33 #define ASPEED_SOC_SRAM_BASE 0x1E720000
34 #define ASPEED_SOC_TIMER_BASE 0x1E782000
35 #define ASPEED_SOC_WDT_BASE 0x1E785000
36 #define ASPEED_SOC_I2C_BASE 0x1E78A000
37 #define ASPEED_SOC_ETH1_BASE 0x1E660000
38 #define ASPEED_SOC_ETH2_BASE 0x1E680000
40 static const int uart_irqs
[] = { 9, 32, 33, 34, 10 };
41 static const int timer_irqs
[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
43 #define AST2400_SDRAM_BASE 0x40000000
44 #define AST2500_SDRAM_BASE 0x80000000
46 static const hwaddr aspeed_soc_ast2400_spi_bases
[] = { ASPEED_SOC_SPI_BASE
};
47 static const char *aspeed_soc_ast2400_typenames
[] = { "aspeed.smc.spi" };
49 static const hwaddr aspeed_soc_ast2500_spi_bases
[] = { ASPEED_SOC_SPI_BASE
,
50 ASPEED_SOC_SPI2_BASE
};
51 static const char *aspeed_soc_ast2500_typenames
[] = {
52 "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
54 static const AspeedSoCInfo aspeed_socs
[] = {
57 .cpu_type
= ARM_CPU_TYPE_NAME("arm926"),
58 .silicon_rev
= AST2400_A0_SILICON_REV
,
59 .sdram_base
= AST2400_SDRAM_BASE
,
62 .spi_bases
= aspeed_soc_ast2400_spi_bases
,
63 .fmc_typename
= "aspeed.smc.fmc",
64 .spi_typename
= aspeed_soc_ast2400_typenames
,
68 .cpu_type
= ARM_CPU_TYPE_NAME("arm926"),
69 .silicon_rev
= AST2400_A1_SILICON_REV
,
70 .sdram_base
= AST2400_SDRAM_BASE
,
73 .spi_bases
= aspeed_soc_ast2400_spi_bases
,
74 .fmc_typename
= "aspeed.smc.fmc",
75 .spi_typename
= aspeed_soc_ast2400_typenames
,
79 .cpu_type
= ARM_CPU_TYPE_NAME("arm926"),
80 .silicon_rev
= AST2400_A0_SILICON_REV
,
81 .sdram_base
= AST2400_SDRAM_BASE
,
84 .spi_bases
= aspeed_soc_ast2400_spi_bases
,
85 .fmc_typename
= "aspeed.smc.fmc",
86 .spi_typename
= aspeed_soc_ast2400_typenames
,
90 .cpu_type
= ARM_CPU_TYPE_NAME("arm1176"),
91 .silicon_rev
= AST2500_A1_SILICON_REV
,
92 .sdram_base
= AST2500_SDRAM_BASE
,
95 .spi_bases
= aspeed_soc_ast2500_spi_bases
,
96 .fmc_typename
= "aspeed.smc.ast2500-fmc",
97 .spi_typename
= aspeed_soc_ast2500_typenames
,
103 * IO handlers: simply catch any reads/writes to IO addresses that aren't
104 * handled by a device mapping.
107 static uint64_t aspeed_soc_io_read(void *p
, hwaddr offset
, unsigned size
)
109 qemu_log_mask(LOG_UNIMP
, "%s: 0x%" HWADDR_PRIx
" [%u]\n",
110 __func__
, offset
, size
);
114 static void aspeed_soc_io_write(void *opaque
, hwaddr offset
, uint64_t value
,
117 qemu_log_mask(LOG_UNIMP
, "%s: 0x%" HWADDR_PRIx
" <- 0x%" PRIx64
" [%u]\n",
118 __func__
, offset
, value
, size
);
121 static const MemoryRegionOps aspeed_soc_io_ops
= {
122 .read
= aspeed_soc_io_read
,
123 .write
= aspeed_soc_io_write
,
124 .endianness
= DEVICE_LITTLE_ENDIAN
,
127 static void aspeed_soc_init(Object
*obj
)
129 AspeedSoCState
*s
= ASPEED_SOC(obj
);
130 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
133 object_initialize(&s
->cpu
, sizeof(s
->cpu
), sc
->info
->cpu_type
);
134 object_property_add_child(obj
, "cpu", OBJECT(&s
->cpu
), NULL
);
136 object_initialize(&s
->vic
, sizeof(s
->vic
), TYPE_ASPEED_VIC
);
137 object_property_add_child(obj
, "vic", OBJECT(&s
->vic
), NULL
);
138 qdev_set_parent_bus(DEVICE(&s
->vic
), sysbus_get_default());
140 object_initialize(&s
->timerctrl
, sizeof(s
->timerctrl
), TYPE_ASPEED_TIMER
);
141 object_property_add_child(obj
, "timerctrl", OBJECT(&s
->timerctrl
), NULL
);
142 qdev_set_parent_bus(DEVICE(&s
->timerctrl
), sysbus_get_default());
144 object_initialize(&s
->i2c
, sizeof(s
->i2c
), TYPE_ASPEED_I2C
);
145 object_property_add_child(obj
, "i2c", OBJECT(&s
->i2c
), NULL
);
146 qdev_set_parent_bus(DEVICE(&s
->i2c
), sysbus_get_default());
148 object_initialize(&s
->scu
, sizeof(s
->scu
), TYPE_ASPEED_SCU
);
149 object_property_add_child(obj
, "scu", OBJECT(&s
->scu
), NULL
);
150 qdev_set_parent_bus(DEVICE(&s
->scu
), sysbus_get_default());
151 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
152 sc
->info
->silicon_rev
);
153 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
154 "hw-strap1", &error_abort
);
155 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
156 "hw-strap2", &error_abort
);
158 object_initialize(&s
->fmc
, sizeof(s
->fmc
), sc
->info
->fmc_typename
);
159 object_property_add_child(obj
, "fmc", OBJECT(&s
->fmc
), NULL
);
160 qdev_set_parent_bus(DEVICE(&s
->fmc
), sysbus_get_default());
161 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs",
164 for (i
= 0; i
< sc
->info
->spis_num
; i
++) {
165 object_initialize(&s
->spi
[i
], sizeof(s
->spi
[i
]),
166 sc
->info
->spi_typename
[i
]);
167 object_property_add_child(obj
, "spi[*]", OBJECT(&s
->spi
[i
]), NULL
);
168 qdev_set_parent_bus(DEVICE(&s
->spi
[i
]), sysbus_get_default());
171 object_initialize(&s
->sdmc
, sizeof(s
->sdmc
), TYPE_ASPEED_SDMC
);
172 object_property_add_child(obj
, "sdmc", OBJECT(&s
->sdmc
), NULL
);
173 qdev_set_parent_bus(DEVICE(&s
->sdmc
), sysbus_get_default());
174 qdev_prop_set_uint32(DEVICE(&s
->sdmc
), "silicon-rev",
175 sc
->info
->silicon_rev
);
176 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
177 "ram-size", &error_abort
);
179 for (i
= 0; i
< sc
->info
->wdts_num
; i
++) {
180 object_initialize(&s
->wdt
[i
], sizeof(s
->wdt
[i
]), TYPE_ASPEED_WDT
);
181 object_property_add_child(obj
, "wdt[*]", OBJECT(&s
->wdt
[i
]), NULL
);
182 qdev_set_parent_bus(DEVICE(&s
->wdt
[i
]), sysbus_get_default());
183 qdev_prop_set_uint32(DEVICE(&s
->wdt
[i
]), "silicon-rev",
184 sc
->info
->silicon_rev
);
187 object_initialize(&s
->ftgmac100
, sizeof(s
->ftgmac100
), TYPE_FTGMAC100
);
188 object_property_add_child(obj
, "ftgmac100", OBJECT(&s
->ftgmac100
), NULL
);
189 qdev_set_parent_bus(DEVICE(&s
->ftgmac100
), sysbus_get_default());
192 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
195 AspeedSoCState
*s
= ASPEED_SOC(dev
);
196 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
197 Error
*err
= NULL
, *local_err
= NULL
;
200 memory_region_init_io(&s
->iomem
, NULL
, &aspeed_soc_io_ops
, NULL
,
201 "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE
);
202 memory_region_add_subregion_overlap(get_system_memory(),
203 ASPEED_SOC_IOMEM_BASE
, &s
->iomem
, -1);
206 object_property_set_bool(OBJECT(&s
->cpu
), true, "realized", &err
);
208 error_propagate(errp
, err
);
213 memory_region_init_ram_nomigrate(&s
->sram
, OBJECT(dev
), "aspeed.sram",
214 sc
->info
->sram_size
, &err
);
216 error_propagate(errp
, err
);
219 vmstate_register_ram_global(&s
->sram
);
220 memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE
,
224 object_property_set_bool(OBJECT(&s
->vic
), true, "realized", &err
);
226 error_propagate(errp
, err
);
229 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, ASPEED_SOC_VIC_BASE
);
230 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
231 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
232 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
233 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
236 object_property_set_bool(OBJECT(&s
->timerctrl
), true, "realized", &err
);
238 error_propagate(errp
, err
);
241 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0, ASPEED_SOC_TIMER_BASE
);
242 for (i
= 0; i
< ARRAY_SIZE(timer_irqs
); i
++) {
243 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&s
->vic
), timer_irqs
[i
]);
244 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
248 object_property_set_bool(OBJECT(&s
->scu
), true, "realized", &err
);
250 error_propagate(errp
, err
);
253 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, ASPEED_SOC_SCU_BASE
);
255 /* UART - attach an 8250 to the IO space as our UART5 */
257 qemu_irq uart5
= qdev_get_gpio_in(DEVICE(&s
->vic
), uart_irqs
[4]);
258 serial_mm_init(&s
->iomem
, ASPEED_SOC_UART_5_BASE
, 2,
259 uart5
, 38400, serial_hds
[0], DEVICE_LITTLE_ENDIAN
);
263 object_property_set_bool(OBJECT(&s
->i2c
), true, "realized", &err
);
265 error_propagate(errp
, err
);
268 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, ASPEED_SOC_I2C_BASE
);
269 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
270 qdev_get_gpio_in(DEVICE(&s
->vic
), 12));
272 /* FMC, The number of CS is set at the board level */
273 object_property_set_bool(OBJECT(&s
->fmc
), true, "realized", &err
);
275 error_propagate(errp
, err
);
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, ASPEED_SOC_FMC_BASE
);
279 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
280 s
->fmc
.ctrl
->flash_window_base
);
281 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
282 qdev_get_gpio_in(DEVICE(&s
->vic
), 19));
285 for (i
= 0; i
< sc
->info
->spis_num
; i
++) {
286 object_property_set_int(OBJECT(&s
->spi
[i
]), 1, "num-cs", &err
);
287 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized",
289 error_propagate(&err
, local_err
);
291 error_propagate(errp
, err
);
294 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, sc
->info
->spi_bases
[i
]);
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
296 s
->spi
[i
].ctrl
->flash_window_base
);
299 /* SDMC - SDRAM Memory Controller */
300 object_property_set_bool(OBJECT(&s
->sdmc
), true, "realized", &err
);
302 error_propagate(errp
, err
);
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, ASPEED_SOC_SDMC_BASE
);
308 for (i
= 0; i
< sc
->info
->wdts_num
; i
++) {
309 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "realized", &err
);
311 error_propagate(errp
, err
);
314 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
315 ASPEED_SOC_WDT_BASE
+ i
* 0x20);
319 qdev_set_nic_properties(DEVICE(&s
->ftgmac100
), &nd_table
[0]);
320 object_property_set_bool(OBJECT(&s
->ftgmac100
), true, "aspeed", &err
);
321 object_property_set_bool(OBJECT(&s
->ftgmac100
), true, "realized",
323 error_propagate(&err
, local_err
);
325 error_propagate(errp
, err
);
328 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
), 0, ASPEED_SOC_ETH1_BASE
);
329 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
), 0,
330 qdev_get_gpio_in(DEVICE(&s
->vic
), 2));
333 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
335 DeviceClass
*dc
= DEVICE_CLASS(oc
);
336 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
338 sc
->info
= (AspeedSoCInfo
*) data
;
339 dc
->realize
= aspeed_soc_realize
;
340 /* Reason: Uses serial_hds and nd_table in realize() directly */
341 dc
->user_creatable
= false;
344 static const TypeInfo aspeed_soc_type_info
= {
345 .name
= TYPE_ASPEED_SOC
,
346 .parent
= TYPE_DEVICE
,
347 .instance_init
= aspeed_soc_init
,
348 .instance_size
= sizeof(AspeedSoCState
),
349 .class_size
= sizeof(AspeedSoCClass
),
353 static void aspeed_soc_register_types(void)
357 type_register_static(&aspeed_soc_type_info
);
358 for (i
= 0; i
< ARRAY_SIZE(aspeed_socs
); ++i
) {
360 .name
= aspeed_socs
[i
].name
,
361 .parent
= TYPE_ASPEED_SOC
,
362 .class_init
= aspeed_soc_class_init
,
363 .class_data
= (void *) &aspeed_socs
[i
],
369 type_init(aspeed_soc_register_types
)