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tcg: Avoid including 'trace-tcg.h' in target translate.c
[qemu/ar7.git] / target / xtensa / translate.c
blobd5da35f4fcd1f2ae18d2c7ad52f2a085e88fd059
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg/tcg-op.h"
37 #include "qemu/log.h"
38 #include "qemu/qemu-print.h"
39 #include "exec/cpu_ldst.h"
40 #include "semihosting/semihost.h"
41 #include "exec/translator.h"
42
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
45
46 #include "exec/log.h"
47
48
49 struct DisasContext {
50 DisasContextBase base;
51 const XtensaConfig *config;
52 uint32_t pc;
53 int cring;
54 int ring;
55 uint32_t lbeg_off;
56 uint32_t lend;
57
58 bool sar_5bit;
59 bool sar_m32_5bit;
60 bool sar_m32_allocated;
61 TCGv_i32 sar_m32;
62
63 unsigned window;
64 unsigned callinc;
65 bool cwoe;
66
67 bool debug;
68 bool icount;
69 TCGv_i32 next_icount;
70
71 unsigned cpenable;
72
73 uint32_t op_flags;
74 xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH];
75 xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH];
76 };
77
78 static TCGv_i32 cpu_pc;
79 static TCGv_i32 cpu_R[16];
80 static TCGv_i32 cpu_FR[16];
81 static TCGv_i64 cpu_FRD[16];
82 static TCGv_i32 cpu_MR[4];
83 static TCGv_i32 cpu_BR[16];
84 static TCGv_i32 cpu_BR4[4];
85 static TCGv_i32 cpu_BR8[2];
86 static TCGv_i32 cpu_SR[256];
87 static TCGv_i32 cpu_UR[256];
88 static TCGv_i32 cpu_windowbase_next;
89 static TCGv_i32 cpu_exclusive_addr;
90 static TCGv_i32 cpu_exclusive_val;
91
92 static GHashTable *xtensa_regfile_table;
93
94 #include "exec/gen-icount.h"
95
96 static char *sr_name[256];
97 static char *ur_name[256];
98
99 void xtensa_collect_sr_names(const XtensaConfig *config)
100 {
101 xtensa_isa isa = config->isa;
102 int n = xtensa_isa_num_sysregs(isa);
103 int i;
104
105 for (i = 0; i < n; ++i) {
106 int sr = xtensa_sysreg_number(isa, i);
107
108 if (sr >= 0 && sr < 256) {
109 const char *name = xtensa_sysreg_name(isa, i);
110 char **pname =
111 (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr;
112
113 if (*pname) {
114 if (strstr(*pname, name) == NULL) {
115 char *new_name =
116 malloc(strlen(*pname) + strlen(name) + 2);
117
118 strcpy(new_name, *pname);
119 strcat(new_name, "/");
120 strcat(new_name, name);
121 free(*pname);
122 *pname = new_name;
123 }
124 } else {
125 *pname = strdup(name);
126 }
127 }
128 }
129 }
130
131 void xtensa_translate_init(void)
132 {
133 static const char * const regnames[] = {
134 "ar0", "ar1", "ar2", "ar3",
135 "ar4", "ar5", "ar6", "ar7",
136 "ar8", "ar9", "ar10", "ar11",
137 "ar12", "ar13", "ar14", "ar15",
138 };
139 static const char * const fregnames[] = {
140 "f0", "f1", "f2", "f3",
141 "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11",
143 "f12", "f13", "f14", "f15",
144 };
145 static const char * const mregnames[] = {
146 "m0", "m1", "m2", "m3",
147 };
148 static const char * const bregnames[] = {
149 "b0", "b1", "b2", "b3",
150 "b4", "b5", "b6", "b7",
151 "b8", "b9", "b10", "b11",
152 "b12", "b13", "b14", "b15",
153 };
154 int i;
155
156 cpu_pc = tcg_global_mem_new_i32(cpu_env,
157 offsetof(CPUXtensaState, pc), "pc");
158
159 for (i = 0; i < 16; i++) {
160 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
161 offsetof(CPUXtensaState, regs[i]),
162 regnames[i]);
163 }
164
165 for (i = 0; i < 16; i++) {
166 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
167 offsetof(CPUXtensaState,
168 fregs[i].f32[FP_F32_LOW]),
169 fregnames[i]);
170 }
171
172 for (i = 0; i < 16; i++) {
173 cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env,
174 offsetof(CPUXtensaState,
175 fregs[i].f64),
176 fregnames[i]);
177 }
178
179 for (i = 0; i < 4; i++) {
180 cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
181 offsetof(CPUXtensaState,
182 sregs[MR + i]),
183 mregnames[i]);
184 }
185
186 for (i = 0; i < 16; i++) {
187 cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
188 offsetof(CPUXtensaState,
189 sregs[BR]),
190 bregnames[i]);
191 if (i % 4 == 0) {
192 cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
193 offsetof(CPUXtensaState,
194 sregs[BR]),
195 bregnames[i]);
196 }
197 if (i % 8 == 0) {
198 cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
199 offsetof(CPUXtensaState,
200 sregs[BR]),
201 bregnames[i]);
202 }
203 }
204
205 for (i = 0; i < 256; ++i) {
206 if (sr_name[i]) {
207 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
208 offsetof(CPUXtensaState,
209 sregs[i]),
210 sr_name[i]);
211 }
212 }
213
214 for (i = 0; i < 256; ++i) {
215 if (ur_name[i]) {
216 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
217 offsetof(CPUXtensaState,
218 uregs[i]),
219 ur_name[i]);
220 }
221 }
222
223 cpu_windowbase_next =
224 tcg_global_mem_new_i32(cpu_env,
225 offsetof(CPUXtensaState, windowbase_next),
226 "windowbase_next");
227 cpu_exclusive_addr =
228 tcg_global_mem_new_i32(cpu_env,
229 offsetof(CPUXtensaState, exclusive_addr),
230 "exclusive_addr");
231 cpu_exclusive_val =
232 tcg_global_mem_new_i32(cpu_env,
233 offsetof(CPUXtensaState, exclusive_val),
234 "exclusive_val");
235 }
236
237 void **xtensa_get_regfile_by_name(const char *name, int entries, int bits)
238 {
239 char *geometry_name;
240 void **res;
241
242 if (xtensa_regfile_table == NULL) {
243 xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal);
244 /*
245 * AR is special. Xtensa translator uses it as a current register
246 * window, but configuration overlays represent it as a complete
247 * physical register file.
248 */
249 g_hash_table_insert(xtensa_regfile_table,
250 (void *)"AR 16x32", (void *)cpu_R);
251 g_hash_table_insert(xtensa_regfile_table,
252 (void *)"AR 32x32", (void *)cpu_R);
253 g_hash_table_insert(xtensa_regfile_table,
254 (void *)"AR 64x32", (void *)cpu_R);
255
256 g_hash_table_insert(xtensa_regfile_table,
257 (void *)"MR 4x32", (void *)cpu_MR);
258
259 g_hash_table_insert(xtensa_regfile_table,
260 (void *)"FR 16x32", (void *)cpu_FR);
261 g_hash_table_insert(xtensa_regfile_table,
262 (void *)"FR 16x64", (void *)cpu_FRD);
263
264 g_hash_table_insert(xtensa_regfile_table,
265 (void *)"BR 16x1", (void *)cpu_BR);
266 g_hash_table_insert(xtensa_regfile_table,
267 (void *)"BR4 4x4", (void *)cpu_BR4);
268 g_hash_table_insert(xtensa_regfile_table,
269 (void *)"BR8 2x8", (void *)cpu_BR8);
270 }
271
272 geometry_name = g_strdup_printf("%s %dx%d", name, entries, bits);
273 res = (void **)g_hash_table_lookup(xtensa_regfile_table, geometry_name);
274 g_free(geometry_name);
275 return res;
276 }
277
278 static inline bool option_enabled(DisasContext *dc, int opt)
279 {
280 return xtensa_option_enabled(dc->config, opt);
281 }
282
283 static void init_sar_tracker(DisasContext *dc)
284 {
285 dc->sar_5bit = false;
286 dc->sar_m32_5bit = false;
287 dc->sar_m32_allocated = false;
288 }
289
290 static void reset_sar_tracker(DisasContext *dc)
291 {
292 if (dc->sar_m32_allocated) {
293 tcg_temp_free(dc->sar_m32);
294 }
295 }
296
297 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
298 {
299 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
300 if (dc->sar_m32_5bit) {
301 tcg_gen_discard_i32(dc->sar_m32);
302 }
303 dc->sar_5bit = true;
304 dc->sar_m32_5bit = false;
305 }
306
307 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
308 {
309 TCGv_i32 tmp = tcg_const_i32(32);
310 if (!dc->sar_m32_allocated) {
311 dc->sar_m32 = tcg_temp_local_new_i32();
312 dc->sar_m32_allocated = true;
313 }
314 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
315 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
316 dc->sar_5bit = false;
317 dc->sar_m32_5bit = true;
318 tcg_temp_free(tmp);
319 }
320
321 static void gen_exception(DisasContext *dc, int excp)
322 {
323 TCGv_i32 tmp = tcg_const_i32(excp);
324 gen_helper_exception(cpu_env, tmp);
325 tcg_temp_free(tmp);
326 }
327
328 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
329 {
330 TCGv_i32 tpc = tcg_const_i32(dc->pc);
331 TCGv_i32 tcause = tcg_const_i32(cause);
332 gen_helper_exception_cause(cpu_env, tpc, tcause);
333 tcg_temp_free(tpc);
334 tcg_temp_free(tcause);
335 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
336 cause == SYSCALL_CAUSE) {
337 dc->base.is_jmp = DISAS_NORETURN;
338 }
339 }
340
341 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
342 {
343 TCGv_i32 tpc = tcg_const_i32(dc->pc);
344 TCGv_i32 tcause = tcg_const_i32(cause);
345 gen_helper_debug_exception(cpu_env, tpc, tcause);
346 tcg_temp_free(tpc);
347 tcg_temp_free(tcause);
348 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
349 dc->base.is_jmp = DISAS_NORETURN;
350 }
351 }
352
353 static bool gen_check_privilege(DisasContext *dc)
354 {
355 #ifndef CONFIG_USER_ONLY
356 if (!dc->cring) {
357 return true;
358 }
359 #endif
360 gen_exception_cause(dc, PRIVILEGED_CAUSE);
361 dc->base.is_jmp = DISAS_NORETURN;
362 return false;
363 }
364
365 static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)
366 {
367 cp_mask &= ~dc->cpenable;
368
369 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
370 gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));
371 dc->base.is_jmp = DISAS_NORETURN;
372 return false;
373 }
374 return true;
375 }
376
377 static int gen_postprocess(DisasContext *dc, int slot);
378
379 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
380 {
381 tcg_gen_mov_i32(cpu_pc, dest);
382 if (dc->icount) {
383 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
384 }
385 if (dc->base.singlestep_enabled) {
386 gen_exception(dc, EXCP_DEBUG);
387 } else {
388 if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
389 slot = gen_postprocess(dc, slot);
390 }
391 if (slot >= 0) {
392 tcg_gen_goto_tb(slot);
393 tcg_gen_exit_tb(dc->base.tb, slot);
394 } else {
395 tcg_gen_exit_tb(NULL, 0);
396 }
397 }
398 dc->base.is_jmp = DISAS_NORETURN;
399 }
400
401 static void gen_jump(DisasContext *dc, TCGv dest)
402 {
403 gen_jump_slot(dc, dest, -1);
404 }
405
406 static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot)
407 {
408 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
409 return -1;
410 } else {
411 return slot;
412 }
413 }
414
415 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
416 {
417 TCGv_i32 tmp = tcg_const_i32(dest);
418 gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
419 tcg_temp_free(tmp);
420 }
421
422 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
423 int slot)
424 {
425 TCGv_i32 tcallinc = tcg_const_i32(callinc);
426
427 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
428 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
429 tcg_temp_free(tcallinc);
430 tcg_gen_movi_i32(cpu_R[callinc << 2],
431 (callinc << 30) | (dc->base.pc_next & 0x3fffffff));
432 gen_jump_slot(dc, dest, slot);
433 }
434
435 static bool gen_check_loop_end(DisasContext *dc, int slot)
436 {
437 if (dc->base.pc_next == dc->lend) {
438 TCGLabel *label = gen_new_label();
439
440 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
441 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
442 if (dc->lbeg_off) {
443 gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
444 } else {
445 gen_jump(dc, cpu_SR[LBEG]);
446 }
447 gen_set_label(label);
448 gen_jumpi(dc, dc->base.pc_next, -1);
449 return true;
450 }
451 return false;
452 }
453
454 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
455 {
456 if (!gen_check_loop_end(dc, slot)) {
457 gen_jumpi(dc, dc->base.pc_next, slot);
458 }
459 }
460
461 static void gen_brcond(DisasContext *dc, TCGCond cond,
462 TCGv_i32 t0, TCGv_i32 t1, uint32_t addr)
463 {
464 TCGLabel *label = gen_new_label();
465
466 tcg_gen_brcond_i32(cond, t0, t1, label);
467 gen_jumpi_check_loop_end(dc, 0);
468 gen_set_label(label);
469 gen_jumpi(dc, addr, 1);
470 }
471
472 static void gen_brcondi(DisasContext *dc, TCGCond cond,
473 TCGv_i32 t0, uint32_t t1, uint32_t addr)
474 {
475 TCGv_i32 tmp = tcg_const_i32(t1);
476 gen_brcond(dc, cond, t0, tmp, addr);
477 tcg_temp_free(tmp);
478 }
479
480 static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
481 const uint32_t par[])
482 {
483 return xtensa_option_enabled(dc->config, par[1]) ? 0 : XTENSA_OP_ILL;
484 }
485
486 static uint32_t test_exceptions_ccompare(DisasContext *dc,
487 const OpcodeArg arg[],
488 const uint32_t par[])
489 {
490 unsigned n = par[0] - CCOMPARE;
491
492 if (n >= dc->config->nccompare) {
493 return XTENSA_OP_ILL;
494 }
495 return test_exceptions_sr(dc, arg, par);
496 }
497
498 static uint32_t test_exceptions_dbreak(DisasContext *dc, const OpcodeArg arg[],
499 const uint32_t par[])
500 {
501 unsigned n = MAX_NDBREAK;
502
503 if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) {
504 n = par[0] - DBREAKA;
505 }
506 if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) {
507 n = par[0] - DBREAKC;
508 }
509 if (n >= dc->config->ndbreak) {
510 return XTENSA_OP_ILL;
511 }
512 return test_exceptions_sr(dc, arg, par);
513 }
514
515 static uint32_t test_exceptions_ibreak(DisasContext *dc, const OpcodeArg arg[],
516 const uint32_t par[])
517 {
518 unsigned n = par[0] - IBREAKA;
519
520 if (n >= dc->config->nibreak) {
521 return XTENSA_OP_ILL;
522 }
523 return test_exceptions_sr(dc, arg, par);
524 }
525
526 static uint32_t test_exceptions_hpi(DisasContext *dc, const OpcodeArg arg[],
527 const uint32_t par[])
528 {
529 unsigned n = MAX_NLEVEL + 1;
530
531 if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) {
532 n = par[0] - EXCSAVE1 + 1;
533 }
534 if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) {
535 n = par[0] - EPC1 + 1;
536 }
537 if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) {
538 n = par[0] - EPS2 + 2;
539 }
540 if (n > dc->config->nlevel) {
541 return XTENSA_OP_ILL;
542 }
543 return test_exceptions_sr(dc, arg, par);
544 }
545
546 static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop,
547 TCGv_i32 addr)
548 {
549 if ((mop & MO_SIZE) == MO_8) {
550 return mop;
551 }
552 if ((mop & MO_AMASK) == MO_UNALN &&
553 !option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT)) {
554 mop |= MO_ALIGN;
555 }
556 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
557 tcg_gen_andi_i32(addr, addr, ~0 << get_alignment_bits(mop));
558 }
559 return mop;
560 }
561
562 #ifndef CONFIG_USER_ONLY
563 static void gen_waiti(DisasContext *dc, uint32_t imm4)
564 {
565 TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
566 TCGv_i32 intlevel = tcg_const_i32(imm4);
567
568 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
569 gen_io_start();
570 }
571 gen_helper_waiti(cpu_env, pc, intlevel);
572 tcg_temp_free(pc);
573 tcg_temp_free(intlevel);
574 }
575 #endif
576
577 static bool gen_window_check(DisasContext *dc, uint32_t mask)
578 {
579 unsigned r = 31 - clz32(mask);
580
581 if (r / 4 > dc->window) {
582 TCGv_i32 pc = tcg_const_i32(dc->pc);
583 TCGv_i32 w = tcg_const_i32(r / 4);
584
585 gen_helper_window_check(cpu_env, pc, w);
586 dc->base.is_jmp = DISAS_NORETURN;
587 return false;
588 }
589 return true;
590 }
591
592 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
593 {
594 TCGv_i32 m = tcg_temp_new_i32();
595
596 if (hi) {
597 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
598 } else {
599 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
600 }
601 return m;
602 }
603
604 static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[])
605 {
606 TCGLabel *label = gen_new_label();
607
608 tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label);
609 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
610 gen_set_label(label);
611 }
612
613 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
614 {
615 return xtensa_isa_length_from_chars(dc->config->isa, &op0);
616 }
617
618 static int gen_postprocess(DisasContext *dc, int slot)
619 {
620 uint32_t op_flags = dc->op_flags;
621
622 #ifndef CONFIG_USER_ONLY
623 if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
624 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
625 gen_io_start();
626 }
627 gen_helper_check_interrupts(cpu_env);
628 }
629 #endif
630 if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
631 gen_helper_sync_windowbase(cpu_env);
632 }
633 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
634 slot = -1;
635 }
636 return slot;
637 }
638
639 struct opcode_arg_copy {
640 uint32_t resource;
641 void *temp;
642 OpcodeArg *arg;
643 };
644
645 struct opcode_arg_info {
646 uint32_t resource;
647 int index;
648 };
649
650 struct slot_prop {
651 XtensaOpcodeOps *ops;
652 OpcodeArg arg[MAX_OPCODE_ARGS];
653 struct opcode_arg_info in[MAX_OPCODE_ARGS];
654 struct opcode_arg_info out[MAX_OPCODE_ARGS];
655 unsigned n_in;
656 unsigned n_out;
657 uint32_t op_flags;
658 };
659
660 enum resource_type {
661 RES_REGFILE,
662 RES_STATE,
663 RES_MAX,
664 };
665
666 static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n)
667 {
668 assert(r < RES_MAX && g < 256 && n < 65536);
669 return (r << 24) | (g << 16) | n;
670 }
671
672 static enum resource_type get_resource_type(uint32_t resource)
673 {
674 return resource >> 24;
675 }
676
677 /*
678 * a depends on b if b must be executed before a,
679 * because a's side effects will destroy b's inputs.
680 */
681 static bool op_depends_on(const struct slot_prop *a,
682 const struct slot_prop *b)
683 {
684 unsigned i = 0;
685 unsigned j = 0;
686
687 if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
688 return true;
689 }
690 if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
691 (b->op_flags & XTENSA_OP_LOAD_STORE)) {
692 return true;
693 }
694 while (i < a->n_out && j < b->n_in) {
695 if (a->out[i].resource < b->in[j].resource) {
696 ++i;
697 } else if (a->out[i].resource > b->in[j].resource) {
698 ++j;
699 } else {
700 return true;
701 }
702 }
703 return false;
704 }
705
706 /*
707 * Try to break a dependency on b, append temporary register copy records
708 * to the end of copy and update n_copy in case of success.
709 * This is not always possible: e.g. control flow must always be the last,
710 * load/store must be first and state dependencies are not supported yet.
711 */
712 static bool break_dependency(struct slot_prop *a,
713 struct slot_prop *b,
714 struct opcode_arg_copy *copy,
715 unsigned *n_copy)
716 {
717 unsigned i = 0;
718 unsigned j = 0;
719 unsigned n = *n_copy;
720 bool rv = false;
721
722 if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
723 return false;
724 }
725 if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
726 (b->op_flags & XTENSA_OP_LOAD_STORE)) {
727 return false;
728 }
729 while (i < a->n_out && j < b->n_in) {
730 if (a->out[i].resource < b->in[j].resource) {
731 ++i;
732 } else if (a->out[i].resource > b->in[j].resource) {
733 ++j;
734 } else {
735 int index = b->in[j].index;
736
737 if (get_resource_type(a->out[i].resource) != RES_REGFILE ||
738 index < 0) {
739 return false;
740 }
741 copy[n].resource = b->in[j].resource;
742 copy[n].arg = b->arg + index;
743 ++n;
744 ++j;
745 rv = true;
746 }
747 }
748 *n_copy = n;
749 return rv;
750 }
751
752 /*
753 * Calculate evaluation order for slot opcodes.
754 * Build opcode order graph and output its nodes in topological sort order.
755 * An edge a -> b in the graph means that opcode a must be followed by
756 * opcode b.
757 */
758 static bool tsort(struct slot_prop *slot,
759 struct slot_prop *sorted[],
760 unsigned n,
761 struct opcode_arg_copy *copy,
762 unsigned *n_copy)
763 {
764 struct tsnode {
765 unsigned n_in_edge;
766 unsigned n_out_edge;
767 unsigned out_edge[MAX_INSN_SLOTS];
768 } node[MAX_INSN_SLOTS];
769
770 unsigned in[MAX_INSN_SLOTS];
771 unsigned i, j;
772 unsigned n_in = 0;
773 unsigned n_out = 0;
774 unsigned n_edge = 0;
775 unsigned in_idx = 0;
776 unsigned node_idx = 0;
777
778 for (i = 0; i < n; ++i) {
779 node[i].n_in_edge = 0;
780 node[i].n_out_edge = 0;
781 }
782
783 for (i = 0; i < n; ++i) {
784 unsigned n_out_edge = 0;
785
786 for (j = 0; j < n; ++j) {
787 if (i != j && op_depends_on(slot + j, slot + i)) {
788 node[i].out_edge[n_out_edge] = j;
789 ++node[j].n_in_edge;
790 ++n_out_edge;
791 ++n_edge;
792 }
793 }
794 node[i].n_out_edge = n_out_edge;
795 }
796
797 for (i = 0; i < n; ++i) {
798 if (!node[i].n_in_edge) {
799 in[n_in] = i;
800 ++n_in;
801 }
802 }
803
804 again:
805 for (; in_idx < n_in; ++in_idx) {
806 i = in[in_idx];
807 sorted[n_out] = slot + i;
808 ++n_out;
809 for (j = 0; j < node[i].n_out_edge; ++j) {
810 --n_edge;
811 if (--node[node[i].out_edge[j]].n_in_edge == 0) {
812 in[n_in] = node[i].out_edge[j];
813 ++n_in;
814 }
815 }
816 }
817 if (n_edge) {
818 for (; node_idx < n; ++node_idx) {
819 struct tsnode *cnode = node + node_idx;
820
821 if (cnode->n_in_edge) {
822 for (j = 0; j < cnode->n_out_edge; ++j) {
823 unsigned k = cnode->out_edge[j];
824
825 if (break_dependency(slot + k, slot + node_idx,
826 copy, n_copy) &&
827 --node[k].n_in_edge == 0) {
828 in[n_in] = k;
829 ++n_in;
830 --n_edge;
831 cnode->out_edge[j] =
832 cnode->out_edge[cnode->n_out_edge - 1];
833 --cnode->n_out_edge;
834 goto again;
835 }
836 }
837 }
838 }
839 }
840 return n_edge == 0;
841 }
842
843 static void opcode_add_resource(struct slot_prop *op,
844 uint32_t resource, char direction,
845 int index)
846 {
847 switch (direction) {
848 case 'm':
849 case 'i':
850 assert(op->n_in < ARRAY_SIZE(op->in));
851 op->in[op->n_in].resource = resource;
852 op->in[op->n_in].index = index;
853 ++op->n_in;
854 /* fall through */
855 case 'o':
856 if (direction == 'm' || direction == 'o') {
857 assert(op->n_out < ARRAY_SIZE(op->out));
858 op->out[op->n_out].resource = resource;
859 op->out[op->n_out].index = index;
860 ++op->n_out;
861 }
862 break;
863 default:
864 g_assert_not_reached();
865 }
866 }
867
868 static int resource_compare(const void *a, const void *b)
869 {
870 const struct opcode_arg_info *pa = a;
871 const struct opcode_arg_info *pb = b;
872
873 return pa->resource < pb->resource ?
874 -1 : (pa->resource > pb->resource ? 1 : 0);
875 }
876
877 static int arg_copy_compare(const void *a, const void *b)
878 {
879 const struct opcode_arg_copy *pa = a;
880 const struct opcode_arg_copy *pb = b;
881
882 return pa->resource < pb->resource ?
883 -1 : (pa->resource > pb->resource ? 1 : 0);
884 }
885
886 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
887 {
888 xtensa_isa isa = dc->config->isa;
889 unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
890 unsigned len = xtensa_op0_insn_len(dc, b[0]);
891 xtensa_format fmt;
892 int slot, slots;
893 unsigned i;
894 uint32_t op_flags = 0;
895 struct slot_prop slot_prop[MAX_INSN_SLOTS];
896 struct slot_prop *ordered[MAX_INSN_SLOTS];
897 struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS];
898 unsigned n_arg_copy = 0;
899 uint32_t debug_cause = 0;
900 uint32_t windowed_register = 0;
901 uint32_t coprocessor = 0;
902
903 if (len == XTENSA_UNDEFINED) {
904 qemu_log_mask(LOG_GUEST_ERROR,
905 "unknown instruction length (pc = %08x)\n",
906 dc->pc);
907 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
908 dc->base.pc_next = dc->pc + 1;
909 return;
910 }
911
912 dc->base.pc_next = dc->pc + len;
913 for (i = 1; i < len; ++i) {
914 b[i] = translator_ldub(env, dc->pc + i);
915 }
916 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
917 fmt = xtensa_format_decode(isa, dc->insnbuf);
918 if (fmt == XTENSA_UNDEFINED) {
919 qemu_log_mask(LOG_GUEST_ERROR,
920 "unrecognized instruction format (pc = %08x)\n",
921 dc->pc);
922 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
923 return;
924 }
925 slots = xtensa_format_num_slots(isa, fmt);
926 for (slot = 0; slot < slots; ++slot) {
927 xtensa_opcode opc;
928 int opnd, vopnd, opnds;
929 OpcodeArg *arg = slot_prop[slot].arg;
930 XtensaOpcodeOps *ops;
931
932 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
933 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
934 if (opc == XTENSA_UNDEFINED) {
935 qemu_log_mask(LOG_GUEST_ERROR,
936 "unrecognized opcode in slot %d (pc = %08x)\n",
937 slot, dc->pc);
938 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
939 return;
940 }
941 opnds = xtensa_opcode_num_operands(isa, opc);
942
943 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
944 void **register_file = NULL;
945 xtensa_regfile rf;
946
947 if (xtensa_operand_is_register(isa, opc, opnd)) {
948 rf = xtensa_operand_regfile(isa, opc, opnd);
949 register_file = dc->config->regfile[rf];
950
951 if (rf == dc->config->a_regfile) {
952 uint32_t v;
953
954 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
955 dc->slotbuf, &v);
956 xtensa_operand_decode(isa, opc, opnd, &v);
957 windowed_register |= 1u << v;
958 }
959 }
960 if (xtensa_operand_is_visible(isa, opc, opnd)) {
961 uint32_t v;
962
963 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
964 dc->slotbuf, &v);
965 xtensa_operand_decode(isa, opc, opnd, &v);
966 arg[vopnd].raw_imm = v;
967 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
968 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
969 }
970 arg[vopnd].imm = v;
971 if (register_file) {
972 arg[vopnd].in = register_file[v];
973 arg[vopnd].out = register_file[v];
974 arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf);
975 } else {
976 arg[vopnd].num_bits = 32;
977 }
978 ++vopnd;
979 }
980 }
981 ops = dc->config->opcode_ops[opc];
982 slot_prop[slot].ops = ops;
983
984 if (ops) {
985 op_flags |= ops->op_flags;
986 if (ops->test_exceptions) {
987 op_flags |= ops->test_exceptions(dc, arg, ops->par);
988 }
989 } else {
990 qemu_log_mask(LOG_UNIMP,
991 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
992 xtensa_opcode_name(isa, opc), slot, dc->pc);
993 op_flags |= XTENSA_OP_ILL;
994 }
995 if (op_flags & XTENSA_OP_ILL) {
996 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
997 return;
998 }
999 if (op_flags & XTENSA_OP_DEBUG_BREAK) {
1000 debug_cause |= ops->par[0];
1001 }
1002 if (ops->test_overflow) {
1003 windowed_register |= ops->test_overflow(dc, arg, ops->par);
1004 }
1005 coprocessor |= ops->coprocessor;
1006
1007 if (slots > 1) {
1008 slot_prop[slot].n_in = 0;
1009 slot_prop[slot].n_out = 0;
1010 slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE;
1011
1012 opnds = xtensa_opcode_num_operands(isa, opc);
1013
1014 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
1015 bool visible = xtensa_operand_is_visible(isa, opc, opnd);
1016
1017 if (xtensa_operand_is_register(isa, opc, opnd)) {
1018 xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
1019 uint32_t v = 0;
1020
1021 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
1022 dc->slotbuf, &v);
1023 xtensa_operand_decode(isa, opc, opnd, &v);
1024 opcode_add_resource(slot_prop + slot,
1025 encode_resource(RES_REGFILE, rf, v),
1026 xtensa_operand_inout(isa, opc, opnd),
1027 visible ? vopnd : -1);
1028 }
1029 if (visible) {
1030 ++vopnd;
1031 }
1032 }
1033
1034 opnds = xtensa_opcode_num_stateOperands(isa, opc);
1035
1036 for (opnd = 0; opnd < opnds; ++opnd) {
1037 xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd);
1038
1039 opcode_add_resource(slot_prop + slot,
1040 encode_resource(RES_STATE, 0, state),
1041 xtensa_stateOperand_inout(isa, opc, opnd),
1042 -1);
1043 }
1044 if (xtensa_opcode_is_branch(isa, opc) ||
1045 xtensa_opcode_is_jump(isa, opc) ||
1046 xtensa_opcode_is_loop(isa, opc) ||
1047 xtensa_opcode_is_call(isa, opc)) {
1048 slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW;
1049 }
1050
1051 qsort(slot_prop[slot].in, slot_prop[slot].n_in,
1052 sizeof(slot_prop[slot].in[0]), resource_compare);
1053 qsort(slot_prop[slot].out, slot_prop[slot].n_out,
1054 sizeof(slot_prop[slot].out[0]), resource_compare);
1055 }
1056 }
1057
1058 if (slots > 1) {
1059 if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) {
1060 qemu_log_mask(LOG_UNIMP,
1061 "Circular resource dependencies (pc = %08x)\n",
1062 dc->pc);
1063 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1064 return;
1065 }
1066 } else {
1067 ordered[0] = slot_prop + 0;
1068 }
1069
1070 if ((op_flags & XTENSA_OP_PRIVILEGED) &&
1071 !gen_check_privilege(dc)) {
1072 return;
1073 }
1074
1075 if (op_flags & XTENSA_OP_SYSCALL) {
1076 gen_exception_cause(dc, SYSCALL_CAUSE);
1077 return;
1078 }
1079
1080 if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) {
1081 gen_debug_exception(dc, debug_cause);
1082 return;
1083 }
1084
1085 if (windowed_register && !gen_window_check(dc, windowed_register)) {
1086 return;
1087 }
1088
1089 if (op_flags & XTENSA_OP_UNDERFLOW) {
1090 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1091
1092 gen_helper_test_underflow_retw(cpu_env, tmp);
1093 tcg_temp_free(tmp);
1094 }
1095
1096 if (op_flags & XTENSA_OP_ALLOCA) {
1097 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1098
1099 gen_helper_movsp(cpu_env, tmp);
1100 tcg_temp_free(tmp);
1101 }
1102
1103 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
1104 return;
1105 }
1106
1107 if (n_arg_copy) {
1108 uint32_t resource;
1109 void *temp;
1110 unsigned j;
1111
1112 qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare);
1113 for (i = j = 0; i < n_arg_copy; ++i) {
1114 if (i == 0 || arg_copy[i].resource != resource) {
1115 resource = arg_copy[i].resource;
1116 if (arg_copy[i].arg->num_bits <= 32) {
1117 temp = tcg_temp_local_new_i32();
1118 tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
1119 } else if (arg_copy[i].arg->num_bits <= 64) {
1120 temp = tcg_temp_local_new_i64();
1121 tcg_gen_mov_i64(temp, arg_copy[i].arg->in);
1122 } else {
1123 g_assert_not_reached();
1124 }
1125 arg_copy[i].temp = temp;
1126
1127 if (i != j) {
1128 arg_copy[j] = arg_copy[i];
1129 }
1130 ++j;
1131 }
1132 arg_copy[i].arg->in = temp;
1133 }
1134 n_arg_copy = j;
1135 }
1136
1137 if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1138 for (slot = 0; slot < slots; ++slot) {
1139 if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1140 gen_zero_check(dc, slot_prop[slot].arg);
1141 }
1142 }
1143 }
1144
1145 dc->op_flags = op_flags;
1146
1147 for (slot = 0; slot < slots; ++slot) {
1148 struct slot_prop *pslot = ordered[slot];
1149 XtensaOpcodeOps *ops = pslot->ops;
1150
1151 ops->translate(dc, pslot->arg, ops->par);
1152 }
1153
1154 for (i = 0; i < n_arg_copy; ++i) {
1155 if (arg_copy[i].arg->num_bits <= 32) {
1156 tcg_temp_free_i32(arg_copy[i].temp);
1157 } else if (arg_copy[i].arg->num_bits <= 64) {
1158 tcg_temp_free_i64(arg_copy[i].temp);
1159 } else {
1160 g_assert_not_reached();
1161 }
1162 }
1163
1164 if (dc->base.is_jmp == DISAS_NEXT) {
1165 gen_postprocess(dc, 0);
1166 dc->op_flags = 0;
1167 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
1168 /* Change in mmu index, memory mapping or tb->flags; exit tb */
1169 gen_jumpi_check_loop_end(dc, -1);
1170 } else if (op_flags & XTENSA_OP_EXIT_TB_0) {
1171 gen_jumpi_check_loop_end(dc, 0);
1172 } else {
1173 gen_check_loop_end(dc, 0);
1174 }
1175 }
1176 dc->pc = dc->base.pc_next;
1177 }
1178
1179 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
1180 {
1181 uint8_t b0 = cpu_ldub_code(env, dc->pc);
1182 return xtensa_op0_insn_len(dc, b0);
1183 }
1184
1185 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
1186 {
1187 unsigned i;
1188
1189 for (i = 0; i < dc->config->nibreak; ++i) {
1190 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
1191 env->sregs[IBREAKA + i] == dc->pc) {
1192 gen_debug_exception(dc, DEBUGCAUSE_IB);
1193 break;
1194 }
1195 }
1196 }
1197
1198 static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
1199 CPUState *cpu)
1200 {
1201 DisasContext *dc = container_of(dcbase, DisasContext, base);
1202 CPUXtensaState *env = cpu->env_ptr;
1203 uint32_t tb_flags = dc->base.tb->flags;
1204
1205 dc->config = env->config;
1206 dc->pc = dc->base.pc_first;
1207 dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
1208 dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
1209 dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >>
1210 XTENSA_CSBASE_LBEG_OFF_SHIFT;
1211 dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) +
1212 (dc->base.pc_first & TARGET_PAGE_MASK);
1213 dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
1214 dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
1215 dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
1216 XTENSA_TBFLAG_CPENABLE_SHIFT;
1217 dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
1218 XTENSA_TBFLAG_WINDOW_SHIFT);
1219 dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
1220 dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
1221 XTENSA_TBFLAG_CALLINC_SHIFT);
1222 init_sar_tracker(dc);
1223 }
1224
1225 static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
1226 {
1227 DisasContext *dc = container_of(dcbase, DisasContext, base);
1228
1229 if (dc->icount) {
1230 dc->next_icount = tcg_temp_local_new_i32();
1231 }
1232 }
1233
1234 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1235 {
1236 tcg_gen_insn_start(dcbase->pc_next);
1237 }
1238
1239 static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
1240 const CPUBreakpoint *bp)
1241 {
1242 DisasContext *dc = container_of(dcbase, DisasContext, base);
1243
1244 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
1245 gen_exception(dc, EXCP_DEBUG);
1246 dc->base.is_jmp = DISAS_NORETURN;
1247 /* The address covered by the breakpoint must be included in
1248 [tb->pc, tb->pc + tb->size) in order to for it to be
1249 properly cleared -- thus we increment the PC here so that
1250 the logic setting tb->size below does the right thing. */
1251 dc->base.pc_next += 2;
1252 return true;
1253 }
1254
1255 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1256 {
1257 DisasContext *dc = container_of(dcbase, DisasContext, base);
1258 CPUXtensaState *env = cpu->env_ptr;
1259 target_ulong page_start;
1260
1261 /* These two conditions only apply to the first insn in the TB,
1262 but this is the first TranslateOps hook that allows exiting. */
1263 if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
1264 && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) {
1265 gen_exception(dc, EXCP_YIELD);
1266 dc->base.pc_next = dc->pc + 1;
1267 dc->base.is_jmp = DISAS_NORETURN;
1268 return;
1269 }
1270
1271 if (dc->icount) {
1272 TCGLabel *label = gen_new_label();
1273
1274 tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
1275 tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
1276 tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
1277 if (dc->debug) {
1278 gen_debug_exception(dc, DEBUGCAUSE_IC);
1279 }
1280 gen_set_label(label);
1281 }
1282
1283 if (dc->debug) {
1284 gen_ibreak_check(env, dc);
1285 }
1286
1287 disas_xtensa_insn(env, dc);
1288
1289 if (dc->icount) {
1290 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
1291 }
1292
1293 /* End the TB if the next insn will cross into the next page. */
1294 page_start = dc->base.pc_first & TARGET_PAGE_MASK;
1295 if (dc->base.is_jmp == DISAS_NEXT &&
1296 (dc->pc - page_start >= TARGET_PAGE_SIZE ||
1297 dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) {
1298 dc->base.is_jmp = DISAS_TOO_MANY;
1299 }
1300 }
1301
1302 static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
1303 {
1304 DisasContext *dc = container_of(dcbase, DisasContext, base);
1305
1306 reset_sar_tracker(dc);
1307 if (dc->icount) {
1308 tcg_temp_free(dc->next_icount);
1309 }
1310
1311 switch (dc->base.is_jmp) {
1312 case DISAS_NORETURN:
1313 break;
1314 case DISAS_TOO_MANY:
1315 if (dc->base.singlestep_enabled) {
1316 tcg_gen_movi_i32(cpu_pc, dc->pc);
1317 gen_exception(dc, EXCP_DEBUG);
1318 } else {
1319 gen_jumpi(dc, dc->pc, 0);
1320 }
1321 break;
1322 default:
1323 g_assert_not_reached();
1324 }
1325 }
1326
1327 static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
1328 {
1329 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
1330 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
1331 }
1332
1333 static const TranslatorOps xtensa_translator_ops = {
1334 .init_disas_context = xtensa_tr_init_disas_context,
1335 .tb_start = xtensa_tr_tb_start,
1336 .insn_start = xtensa_tr_insn_start,
1337 .breakpoint_check = xtensa_tr_breakpoint_check,
1338 .translate_insn = xtensa_tr_translate_insn,
1339 .tb_stop = xtensa_tr_tb_stop,
1340 .disas_log = xtensa_tr_disas_log,
1341 };
1342
1343 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
1344 {
1345 DisasContext dc = {};
1346 translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
1347 }
1348
1349 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1350 {
1351 XtensaCPU *cpu = XTENSA_CPU(cs);
1352 CPUXtensaState *env = &cpu->env;
1353 xtensa_isa isa = env->config->isa;
1354 int i, j;
1355
1356 qemu_fprintf(f, "PC=%08x\n\n", env->pc);
1357
1358 for (i = j = 0; i < xtensa_isa_num_sysregs(isa); ++i) {
1359 const uint32_t *reg =
1360 xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs;
1361 int regno = xtensa_sysreg_number(isa, i);
1362
1363 if (regno >= 0) {
1364 qemu_fprintf(f, "%12s=%08x%c",
1365 xtensa_sysreg_name(isa, i),
1366 reg[regno],
1367 (j++ % 4) == 3 ? '\n' : ' ');
1368 }
1369 }
1370
1371 qemu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1372
1373 for (i = 0; i < 16; ++i) {
1374 qemu_fprintf(f, " A%02d=%08x%c",
1375 i, env->regs[i], (i % 4) == 3 ? '\n' : ' ');
1376 }
1377
1378 xtensa_sync_phys_from_window(env);
1379 qemu_fprintf(f, "\n");
1380
1381 for (i = 0; i < env->config->nareg; ++i) {
1382 qemu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]);
1383 if (i % 4 == 3) {
1384 bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0;
1385 bool cw = env->sregs[WINDOW_BASE] == i / 4;
1386
1387 qemu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' ');
1388 }
1389 }
1390
1391 if ((flags & CPU_DUMP_FPU) &&
1392 xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
1393 qemu_fprintf(f, "\n");
1394
1395 for (i = 0; i < 16; ++i) {
1396 qemu_fprintf(f, "F%02d=%08x (%-+15.8e)%c", i,
1397 float32_val(env->fregs[i].f32[FP_F32_LOW]),
1398 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
1399 (i % 2) == 1 ? '\n' : ' ');
1400 }
1401 }
1402
1403 if ((flags & CPU_DUMP_FPU) &&
1404 xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR) &&
1405 !xtensa_option_enabled(env->config, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
1406 qemu_fprintf(f, "\n");
1407
1408 for (i = 0; i < 16; ++i) {
1409 qemu_fprintf(f, "F%02d=%016"PRIx64" (%-+24.16le)%c", i,
1410 float64_val(env->fregs[i].f64),
1411 *(double *)(&env->fregs[i].f64),
1412 (i % 2) == 1 ? '\n' : ' ');
1413 }
1414 }
1415 }
1416
1417 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
1418 target_ulong *data)
1419 {
1420 env->pc = data[0];
1421 }
1422
1423 static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
1424 const uint32_t par[])
1425 {
1426 tcg_gen_abs_i32(arg[0].out, arg[1].in);
1427 }
1428
1429 static void translate_add(DisasContext *dc, const OpcodeArg arg[],
1430 const uint32_t par[])
1431 {
1432 tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in);
1433 }
1434
1435 static void translate_addi(DisasContext *dc, const OpcodeArg arg[],
1436 const uint32_t par[])
1437 {
1438 tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm);
1439 }
1440
1441 static void translate_addx(DisasContext *dc, const OpcodeArg arg[],
1442 const uint32_t par[])
1443 {
1444 TCGv_i32 tmp = tcg_temp_new_i32();
1445 tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
1446 tcg_gen_add_i32(arg[0].out, tmp, arg[2].in);
1447 tcg_temp_free(tmp);
1448 }
1449
1450 static void translate_all(DisasContext *dc, const OpcodeArg arg[],
1451 const uint32_t par[])
1452 {
1453 uint32_t shift = par[1];
1454 TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm);
1455 TCGv_i32 tmp = tcg_temp_new_i32();
1456
1457 tcg_gen_and_i32(tmp, arg[1].in, mask);
1458 if (par[0]) {
1459 tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm);
1460 } else {
1461 tcg_gen_add_i32(tmp, tmp, mask);
1462 }
1463 tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift);
1464 tcg_gen_deposit_i32(arg[0].out, arg[0].out,
1465 tmp, arg[0].imm, 1);
1466 tcg_temp_free(mask);
1467 tcg_temp_free(tmp);
1468 }
1469
1470 static void translate_and(DisasContext *dc, const OpcodeArg arg[],
1471 const uint32_t par[])
1472 {
1473 tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in);
1474 }
1475
1476 static void translate_ball(DisasContext *dc, const OpcodeArg arg[],
1477 const uint32_t par[])
1478 {
1479 TCGv_i32 tmp = tcg_temp_new_i32();
1480 tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
1481 gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm);
1482 tcg_temp_free(tmp);
1483 }
1484
1485 static void translate_bany(DisasContext *dc, const OpcodeArg arg[],
1486 const uint32_t par[])
1487 {
1488 TCGv_i32 tmp = tcg_temp_new_i32();
1489 tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
1490 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1491 tcg_temp_free(tmp);
1492 }
1493
1494 static void translate_b(DisasContext *dc, const OpcodeArg arg[],
1495 const uint32_t par[])
1496 {
1497 gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm);
1498 }
1499
1500 static void translate_bb(DisasContext *dc, const OpcodeArg arg[],
1501 const uint32_t par[])
1502 {
1503 #ifdef TARGET_WORDS_BIGENDIAN
1504 TCGv_i32 bit = tcg_const_i32(0x80000000u);
1505 #else
1506 TCGv_i32 bit = tcg_const_i32(0x00000001u);
1507 #endif
1508 TCGv_i32 tmp = tcg_temp_new_i32();
1509 tcg_gen_andi_i32(tmp, arg[1].in, 0x1f);
1510 #ifdef TARGET_WORDS_BIGENDIAN
1511 tcg_gen_shr_i32(bit, bit, tmp);
1512 #else
1513 tcg_gen_shl_i32(bit, bit, tmp);
1514 #endif
1515 tcg_gen_and_i32(tmp, arg[0].in, bit);
1516 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1517 tcg_temp_free(tmp);
1518 tcg_temp_free(bit);
1519 }
1520
1521 static void translate_bbi(DisasContext *dc, const OpcodeArg arg[],
1522 const uint32_t par[])
1523 {
1524 TCGv_i32 tmp = tcg_temp_new_i32();
1525 #ifdef TARGET_WORDS_BIGENDIAN
1526 tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
1527 #else
1528 tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
1529 #endif
1530 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1531 tcg_temp_free(tmp);
1532 }
1533
1534 static void translate_bi(DisasContext *dc, const OpcodeArg arg[],
1535 const uint32_t par[])
1536 {
1537 gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm);
1538 }
1539
1540 static void translate_bz(DisasContext *dc, const OpcodeArg arg[],
1541 const uint32_t par[])
1542 {
1543 gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm);
1544 }
1545
1546 enum {
1547 BOOLEAN_AND,
1548 BOOLEAN_ANDC,
1549 BOOLEAN_OR,
1550 BOOLEAN_ORC,
1551 BOOLEAN_XOR,
1552 };
1553
1554 static void translate_boolean(DisasContext *dc, const OpcodeArg arg[],
1555 const uint32_t par[])
1556 {
1557 static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = {
1558 [BOOLEAN_AND] = tcg_gen_and_i32,
1559 [BOOLEAN_ANDC] = tcg_gen_andc_i32,
1560 [BOOLEAN_OR] = tcg_gen_or_i32,
1561 [BOOLEAN_ORC] = tcg_gen_orc_i32,
1562 [BOOLEAN_XOR] = tcg_gen_xor_i32,
1563 };
1564
1565 TCGv_i32 tmp1 = tcg_temp_new_i32();
1566 TCGv_i32 tmp2 = tcg_temp_new_i32();
1567
1568 tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm);
1569 tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm);
1570 op[par[0]](tmp1, tmp1, tmp2);
1571 tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1);
1572 tcg_temp_free(tmp1);
1573 tcg_temp_free(tmp2);
1574 }
1575
1576 static void translate_bp(DisasContext *dc, const OpcodeArg arg[],
1577 const uint32_t par[])
1578 {
1579 TCGv_i32 tmp = tcg_temp_new_i32();
1580
1581 tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm);
1582 gen_brcondi(dc, par[0], tmp, 0, arg[1].imm);
1583 tcg_temp_free(tmp);
1584 }
1585
1586 static void translate_call0(DisasContext *dc, const OpcodeArg arg[],
1587 const uint32_t par[])
1588 {
1589 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1590 gen_jumpi(dc, arg[0].imm, 0);
1591 }
1592
1593 static void translate_callw(DisasContext *dc, const OpcodeArg arg[],
1594 const uint32_t par[])
1595 {
1596 TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
1597 gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0));
1598 tcg_temp_free(tmp);
1599 }
1600
1601 static void translate_callx0(DisasContext *dc, const OpcodeArg arg[],
1602 const uint32_t par[])
1603 {
1604 TCGv_i32 tmp = tcg_temp_new_i32();
1605 tcg_gen_mov_i32(tmp, arg[0].in);
1606 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1607 gen_jump(dc, tmp);
1608 tcg_temp_free(tmp);
1609 }
1610
1611 static void translate_callxw(DisasContext *dc, const OpcodeArg arg[],
1612 const uint32_t par[])
1613 {
1614 TCGv_i32 tmp = tcg_temp_new_i32();
1615
1616 tcg_gen_mov_i32(tmp, arg[0].in);
1617 gen_callw_slot(dc, par[0], tmp, -1);
1618 tcg_temp_free(tmp);
1619 }
1620
1621 static void translate_clamps(DisasContext *dc, const OpcodeArg arg[],
1622 const uint32_t par[])
1623 {
1624 TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm);
1625 TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1);
1626
1627 tcg_gen_smax_i32(tmp1, tmp1, arg[1].in);
1628 tcg_gen_smin_i32(arg[0].out, tmp1, tmp2);
1629 tcg_temp_free(tmp1);
1630 tcg_temp_free(tmp2);
1631 }
1632
1633 static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[],
1634 const uint32_t par[])
1635 {
1636 /* TODO: GPIO32 may be a part of coprocessor */
1637 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm));
1638 }
1639
1640 static void translate_clrex(DisasContext *dc, const OpcodeArg arg[],
1641 const uint32_t par[])
1642 {
1643 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
1644 }
1645
1646 static void translate_const16(DisasContext *dc, const OpcodeArg arg[],
1647 const uint32_t par[])
1648 {
1649 TCGv_i32 c = tcg_const_i32(arg[1].imm);
1650
1651 tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16);
1652 tcg_temp_free(c);
1653 }
1654
1655 static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
1656 const uint32_t par[])
1657 {
1658 TCGv_i32 addr = tcg_temp_new_i32();
1659 TCGv_i32 res = tcg_temp_new_i32();
1660
1661 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
1662 tcg_gen_qemu_ld8u(res, addr, dc->cring);
1663 tcg_temp_free(addr);
1664 tcg_temp_free(res);
1665 }
1666
1667 static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
1668 const uint32_t par[])
1669 {
1670 tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in,
1671 arg[2].imm, arg[3].imm);
1672 }
1673
1674 static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[],
1675 const uint32_t par[])
1676 {
1677 tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes);
1678 }
1679
1680 static uint32_t test_exceptions_entry(DisasContext *dc, const OpcodeArg arg[],
1681 const uint32_t par[])
1682 {
1683 if (arg[0].imm > 3 || !dc->cwoe) {
1684 qemu_log_mask(LOG_GUEST_ERROR,
1685 "Illegal entry instruction(pc = %08x)\n", dc->pc);
1686 return XTENSA_OP_ILL;
1687 } else {
1688 return 0;
1689 }
1690 }
1691
1692 static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[],
1693 const uint32_t par[])
1694 {
1695 return 1 << (dc->callinc * 4);
1696 }
1697
1698 static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
1699 const uint32_t par[])
1700 {
1701 TCGv_i32 pc = tcg_const_i32(dc->pc);
1702 TCGv_i32 s = tcg_const_i32(arg[0].imm);
1703 TCGv_i32 imm = tcg_const_i32(arg[1].imm);
1704 gen_helper_entry(cpu_env, pc, s, imm);
1705 tcg_temp_free(imm);
1706 tcg_temp_free(s);
1707 tcg_temp_free(pc);
1708 }
1709
1710 static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
1711 const uint32_t par[])
1712 {
1713 int maskimm = (1 << arg[3].imm) - 1;
1714
1715 TCGv_i32 tmp = tcg_temp_new_i32();
1716 tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm);
1717 tcg_gen_andi_i32(arg[0].out, tmp, maskimm);
1718 tcg_temp_free(tmp);
1719 }
1720
1721 static void translate_getex(DisasContext *dc, const OpcodeArg arg[],
1722 const uint32_t par[])
1723 {
1724 TCGv_i32 tmp = tcg_temp_new_i32();
1725
1726 tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1);
1727 tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1);
1728 tcg_gen_mov_i32(arg[0].out, tmp);
1729 tcg_temp_free(tmp);
1730 }
1731
1732 static void translate_icache(DisasContext *dc, const OpcodeArg arg[],
1733 const uint32_t par[])
1734 {
1735 #ifndef CONFIG_USER_ONLY
1736 TCGv_i32 addr = tcg_temp_new_i32();
1737
1738 tcg_gen_movi_i32(cpu_pc, dc->pc);
1739 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
1740 gen_helper_itlb_hit_test(cpu_env, addr);
1741 tcg_temp_free(addr);
1742 #endif
1743 }
1744
1745 static void translate_itlb(DisasContext *dc, const OpcodeArg arg[],
1746 const uint32_t par[])
1747 {
1748 #ifndef CONFIG_USER_ONLY
1749 TCGv_i32 dtlb = tcg_const_i32(par[0]);
1750
1751 gen_helper_itlb(cpu_env, arg[0].in, dtlb);
1752 tcg_temp_free(dtlb);
1753 #endif
1754 }
1755
1756 static void translate_j(DisasContext *dc, const OpcodeArg arg[],
1757 const uint32_t par[])
1758 {
1759 gen_jumpi(dc, arg[0].imm, 0);
1760 }
1761
1762 static void translate_jx(DisasContext *dc, const OpcodeArg arg[],
1763 const uint32_t par[])
1764 {
1765 gen_jump(dc, arg[0].in);
1766 }
1767
1768 static void translate_l32e(DisasContext *dc, const OpcodeArg arg[],
1769 const uint32_t par[])
1770 {
1771 TCGv_i32 addr = tcg_temp_new_i32();
1772 MemOp mop;
1773
1774 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
1775 mop = gen_load_store_alignment(dc, MO_TEUL, addr);
1776 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, mop);
1777 tcg_temp_free(addr);
1778 }
1779
1780 #ifdef CONFIG_USER_ONLY
1781 static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
1782 {
1783 }
1784 #else
1785 static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
1786 {
1787 if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
1788 TCGv_i32 tpc = tcg_const_i32(dc->pc);
1789 TCGv_i32 write = tcg_const_i32(is_write);
1790
1791 gen_helper_check_exclusive(cpu_env, tpc, addr, write);
1792 tcg_temp_free(tpc);
1793 tcg_temp_free(write);
1794 }
1795 }
1796 #endif
1797
1798 static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[],
1799 const uint32_t par[])
1800 {
1801 TCGv_i32 addr = tcg_temp_new_i32();
1802 MemOp mop;
1803
1804 tcg_gen_mov_i32(addr, arg[1].in);
1805 mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr);
1806 gen_check_exclusive(dc, addr, false);
1807 tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, mop);
1808 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
1809 tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out);
1810 tcg_temp_free(addr);
1811 }
1812
1813 static void translate_ldst(DisasContext *dc, const OpcodeArg arg[],
1814 const uint32_t par[])
1815 {
1816 TCGv_i32 addr = tcg_temp_new_i32();
1817 MemOp mop;
1818
1819 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
1820 mop = gen_load_store_alignment(dc, par[0], addr);
1821
1822 if (par[2]) {
1823 if (par[1]) {
1824 tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
1825 }
1826 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop);
1827 } else {
1828 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop);
1829 if (par[1]) {
1830 tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
1831 }
1832 }
1833 tcg_temp_free(addr);
1834 }
1835
1836 static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
1837 const uint32_t par[])
1838 {
1839 TCGv_i32 tmp;
1840
1841 if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
1842 tmp = tcg_const_i32(arg[1].raw_imm - 1);
1843 tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
1844 } else {
1845 tmp = tcg_const_i32(arg[1].imm);
1846 }
1847 tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
1848 tcg_temp_free(tmp);
1849 }
1850
1851 static void translate_loop(DisasContext *dc, const OpcodeArg arg[],
1852 const uint32_t par[])
1853 {
1854 uint32_t lend = arg[1].imm;
1855
1856 tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1);
1857 tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
1858 tcg_gen_movi_i32(cpu_SR[LEND], lend);
1859
1860 if (par[0] != TCG_COND_NEVER) {
1861 TCGLabel *label = gen_new_label();
1862 tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label);
1863 gen_jumpi(dc, lend, 1);
1864 gen_set_label(label);
1865 }
1866
1867 gen_jumpi(dc, dc->base.pc_next, 0);
1868 }
1869
1870 enum {
1871 MAC16_UMUL,
1872 MAC16_MUL,
1873 MAC16_MULA,
1874 MAC16_MULS,
1875 MAC16_NONE,
1876 };
1877
1878 enum {
1879 MAC16_LL,
1880 MAC16_HL,
1881 MAC16_LH,
1882 MAC16_HH,
1883
1884 MAC16_HX = 0x1,
1885 MAC16_XH = 0x2,
1886 };
1887
1888 static void translate_mac16(DisasContext *dc, const OpcodeArg arg[],
1889 const uint32_t par[])
1890 {
1891 int op = par[0];
1892 unsigned half = par[1];
1893 uint32_t ld_offset = par[2];
1894 unsigned off = ld_offset ? 2 : 0;
1895 TCGv_i32 vaddr = tcg_temp_new_i32();
1896 TCGv_i32 mem32 = tcg_temp_new_i32();
1897
1898 if (ld_offset) {
1899 MemOp mop;
1900
1901 tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset);
1902 mop = gen_load_store_alignment(dc, MO_TEUL, vaddr);
1903 tcg_gen_qemu_ld_tl(mem32, vaddr, dc->cring, mop);
1904 }
1905 if (op != MAC16_NONE) {
1906 TCGv_i32 m1 = gen_mac16_m(arg[off].in,
1907 half & MAC16_HX, op == MAC16_UMUL);
1908 TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in,
1909 half & MAC16_XH, op == MAC16_UMUL);
1910
1911 if (op == MAC16_MUL || op == MAC16_UMUL) {
1912 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
1913 if (op == MAC16_UMUL) {
1914 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
1915 } else {
1916 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
1917 }
1918 } else {
1919 TCGv_i32 lo = tcg_temp_new_i32();
1920 TCGv_i32 hi = tcg_temp_new_i32();
1921
1922 tcg_gen_mul_i32(lo, m1, m2);
1923 tcg_gen_sari_i32(hi, lo, 31);
1924 if (op == MAC16_MULA) {
1925 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1926 cpu_SR[ACCLO], cpu_SR[ACCHI],
1927 lo, hi);
1928 } else {
1929 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1930 cpu_SR[ACCLO], cpu_SR[ACCHI],
1931 lo, hi);
1932 }
1933 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
1934
1935 tcg_temp_free_i32(lo);
1936 tcg_temp_free_i32(hi);
1937 }
1938 tcg_temp_free(m1);
1939 tcg_temp_free(m2);
1940 }
1941 if (ld_offset) {
1942 tcg_gen_mov_i32(arg[1].out, vaddr);
1943 tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32);
1944 }
1945 tcg_temp_free(vaddr);
1946 tcg_temp_free(mem32);
1947 }
1948
1949 static void translate_memw(DisasContext *dc, const OpcodeArg arg[],
1950 const uint32_t par[])
1951 {
1952 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
1953 }
1954
1955 static void translate_smin(DisasContext *dc, const OpcodeArg arg[],
1956 const uint32_t par[])
1957 {
1958 tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in);
1959 }
1960
1961 static void translate_umin(DisasContext *dc, const OpcodeArg arg[],
1962 const uint32_t par[])
1963 {
1964 tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in);
1965 }
1966
1967 static void translate_smax(DisasContext *dc, const OpcodeArg arg[],
1968 const uint32_t par[])
1969 {
1970 tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in);
1971 }
1972
1973 static void translate_umax(DisasContext *dc, const OpcodeArg arg[],
1974 const uint32_t par[])
1975 {
1976 tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in);
1977 }
1978
1979 static void translate_mov(DisasContext *dc, const OpcodeArg arg[],
1980 const uint32_t par[])
1981 {
1982 tcg_gen_mov_i32(arg[0].out, arg[1].in);
1983 }
1984
1985 static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
1986 const uint32_t par[])
1987 {
1988 TCGv_i32 zero = tcg_const_i32(0);
1989
1990 tcg_gen_movcond_i32(par[0], arg[0].out,
1991 arg[2].in, zero, arg[1].in, arg[0].in);
1992 tcg_temp_free(zero);
1993 }
1994
1995 static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
1996 const uint32_t par[])
1997 {
1998 tcg_gen_movi_i32(arg[0].out, arg[1].imm);
1999 }
2000
2001 static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
2002 const uint32_t par[])
2003 {
2004 TCGv_i32 zero = tcg_const_i32(0);
2005 TCGv_i32 tmp = tcg_temp_new_i32();
2006
2007 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
2008 tcg_gen_movcond_i32(par[0],
2009 arg[0].out, tmp, zero,
2010 arg[1].in, arg[0].in);
2011 tcg_temp_free(tmp);
2012 tcg_temp_free(zero);
2013 }
2014
2015 static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
2016 const uint32_t par[])
2017 {
2018 tcg_gen_mov_i32(arg[0].out, arg[1].in);
2019 }
2020
2021 static void translate_mul16(DisasContext *dc, const OpcodeArg arg[],
2022 const uint32_t par[])
2023 {
2024 TCGv_i32 v1 = tcg_temp_new_i32();
2025 TCGv_i32 v2 = tcg_temp_new_i32();
2026
2027 if (par[0]) {
2028 tcg_gen_ext16s_i32(v1, arg[1].in);
2029 tcg_gen_ext16s_i32(v2, arg[2].in);
2030 } else {
2031 tcg_gen_ext16u_i32(v1, arg[1].in);
2032 tcg_gen_ext16u_i32(v2, arg[2].in);
2033 }
2034 tcg_gen_mul_i32(arg[0].out, v1, v2);
2035 tcg_temp_free(v2);
2036 tcg_temp_free(v1);
2037 }
2038
2039 static void translate_mull(DisasContext *dc, const OpcodeArg arg[],
2040 const uint32_t par[])
2041 {
2042 tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in);
2043 }
2044
2045 static void translate_mulh(DisasContext *dc, const OpcodeArg arg[],
2046 const uint32_t par[])
2047 {
2048 TCGv_i32 lo = tcg_temp_new();
2049
2050 if (par[0]) {
2051 tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
2052 } else {
2053 tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
2054 }
2055 tcg_temp_free(lo);
2056 }
2057
2058 static void translate_neg(DisasContext *dc, const OpcodeArg arg[],
2059 const uint32_t par[])
2060 {
2061 tcg_gen_neg_i32(arg[0].out, arg[1].in);
2062 }
2063
2064 static void translate_nop(DisasContext *dc, const OpcodeArg arg[],
2065 const uint32_t par[])
2066 {
2067 }
2068
2069 static void translate_nsa(DisasContext *dc, const OpcodeArg arg[],
2070 const uint32_t par[])
2071 {
2072 tcg_gen_clrsb_i32(arg[0].out, arg[1].in);
2073 }
2074
2075 static void translate_nsau(DisasContext *dc, const OpcodeArg arg[],
2076 const uint32_t par[])
2077 {
2078 tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32);
2079 }
2080
2081 static void translate_or(DisasContext *dc, const OpcodeArg arg[],
2082 const uint32_t par[])
2083 {
2084 tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in);
2085 }
2086
2087 static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],
2088 const uint32_t par[])
2089 {
2090 #ifndef CONFIG_USER_ONLY
2091 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2092
2093 tcg_gen_movi_i32(cpu_pc, dc->pc);
2094 gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
2095 tcg_temp_free(dtlb);
2096 #endif
2097 }
2098
2099 static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[],
2100 const uint32_t par[])
2101 {
2102 #ifndef CONFIG_USER_ONLY
2103 tcg_gen_movi_i32(cpu_pc, dc->pc);
2104 gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
2105 #endif
2106 }
2107
2108 static void translate_quos(DisasContext *dc, const OpcodeArg arg[],
2109 const uint32_t par[])
2110 {
2111 TCGLabel *label1 = gen_new_label();
2112 TCGLabel *label2 = gen_new_label();
2113
2114 tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000,
2115 label1);
2116 tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff,
2117 label1);
2118 tcg_gen_movi_i32(arg[0].out,
2119 par[0] ? 0x80000000 : 0);
2120 tcg_gen_br(label2);
2121 gen_set_label(label1);
2122 if (par[0]) {
2123 tcg_gen_div_i32(arg[0].out,
2124 arg[1].in, arg[2].in);
2125 } else {
2126 tcg_gen_rem_i32(arg[0].out,
2127 arg[1].in, arg[2].in);
2128 }
2129 gen_set_label(label2);
2130 }
2131
2132 static void translate_quou(DisasContext *dc, const OpcodeArg arg[],
2133 const uint32_t par[])
2134 {
2135 tcg_gen_divu_i32(arg[0].out,
2136 arg[1].in, arg[2].in);
2137 }
2138
2139 static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[],
2140 const uint32_t par[])
2141 {
2142 /* TODO: GPIO32 may be a part of coprocessor */
2143 tcg_gen_movi_i32(arg[0].out, 0);
2144 }
2145
2146 static void translate_remu(DisasContext *dc, const OpcodeArg arg[],
2147 const uint32_t par[])
2148 {
2149 tcg_gen_remu_i32(arg[0].out,
2150 arg[1].in, arg[2].in);
2151 }
2152
2153 static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
2154 const uint32_t par[])
2155 {
2156 gen_helper_rer(arg[0].out, cpu_env, arg[1].in);
2157 }
2158
2159 static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
2160 const uint32_t par[])
2161 {
2162 gen_jump(dc, cpu_R[0]);
2163 }
2164
2165 static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[],
2166 const uint32_t par[])
2167 {
2168 if (!dc->cwoe) {
2169 qemu_log_mask(LOG_GUEST_ERROR,
2170 "Illegal retw instruction(pc = %08x)\n", dc->pc);
2171 return XTENSA_OP_ILL;
2172 } else {
2173 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2174
2175 gen_helper_test_ill_retw(cpu_env, tmp);
2176 tcg_temp_free(tmp);
2177 return 0;
2178 }
2179 }
2180
2181 static void translate_retw(DisasContext *dc, const OpcodeArg arg[],
2182 const uint32_t par[])
2183 {
2184 TCGv_i32 tmp = tcg_const_i32(1);
2185 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2186 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2187 cpu_SR[WINDOW_START], tmp);
2188 tcg_gen_movi_i32(tmp, dc->pc);
2189 tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
2190 gen_helper_retw(cpu_env, cpu_R[0]);
2191 gen_jump(dc, tmp);
2192 tcg_temp_free(tmp);
2193 }
2194
2195 static void translate_rfde(DisasContext *dc, const OpcodeArg arg[],
2196 const uint32_t par[])
2197 {
2198 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
2199 }
2200
2201 static void translate_rfe(DisasContext *dc, const OpcodeArg arg[],
2202 const uint32_t par[])
2203 {
2204 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2205 gen_jump(dc, cpu_SR[EPC1]);
2206 }
2207
2208 static void translate_rfi(DisasContext *dc, const OpcodeArg arg[],
2209 const uint32_t par[])
2210 {
2211 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]);
2212 gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]);
2213 }
2214
2215 static void translate_rfw(DisasContext *dc, const OpcodeArg arg[],
2216 const uint32_t par[])
2217 {
2218 TCGv_i32 tmp = tcg_const_i32(1);
2219
2220 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2221 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2222
2223 if (par[0]) {
2224 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2225 cpu_SR[WINDOW_START], tmp);
2226 } else {
2227 tcg_gen_or_i32(cpu_SR[WINDOW_START],
2228 cpu_SR[WINDOW_START], tmp);
2229 }
2230
2231 tcg_temp_free(tmp);
2232 gen_helper_restore_owb(cpu_env);
2233 gen_jump(dc, cpu_SR[EPC1]);
2234 }
2235
2236 static void translate_rotw(DisasContext *dc, const OpcodeArg arg[],
2237 const uint32_t par[])
2238 {
2239 tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm);
2240 }
2241
2242 static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],
2243 const uint32_t par[])
2244 {
2245 tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]);
2246 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
2247 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm);
2248 }
2249
2250 static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
2251 const uint32_t par[])
2252 {
2253 if (sr_name[par[0]]) {
2254 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2255 } else {
2256 tcg_gen_movi_i32(arg[0].out, 0);
2257 }
2258 }
2259
2260 static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2261 const uint32_t par[])
2262 {
2263 #ifndef CONFIG_USER_ONLY
2264 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2265 gen_io_start();
2266 }
2267 gen_helper_update_ccount(cpu_env);
2268 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2269 #endif
2270 }
2271
2272 static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[],
2273 const uint32_t par[])
2274 {
2275 #ifndef CONFIG_USER_ONLY
2276 TCGv_i32 tmp = tcg_temp_new_i32();
2277
2278 tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10);
2279 tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]);
2280 tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc);
2281 tcg_temp_free(tmp);
2282 #endif
2283 }
2284
2285 static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],
2286 const uint32_t par[])
2287 {
2288 #ifndef CONFIG_USER_ONLY
2289 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
2290 TCGv_i32 a2) = {
2291 gen_helper_rtlb0,
2292 gen_helper_rtlb1,
2293 };
2294 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2295
2296 helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
2297 tcg_temp_free(dtlb);
2298 #endif
2299 }
2300
2301 static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[],
2302 const uint32_t par[])
2303 {
2304 #ifndef CONFIG_USER_ONLY
2305 gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
2306 #endif
2307 }
2308
2309 static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[],
2310 const uint32_t par[])
2311 {
2312 #ifndef CONFIG_USER_ONLY
2313 gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
2314 #endif
2315 }
2316
2317 static void translate_rur(DisasContext *dc, const OpcodeArg arg[],
2318 const uint32_t par[])
2319 {
2320 tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]);
2321 }
2322
2323 static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[],
2324 const uint32_t par[])
2325 {
2326 /* TODO: GPIO32 may be a part of coprocessor */
2327 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm);
2328 }
2329
2330 #ifdef CONFIG_USER_ONLY
2331 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2332 {
2333 }
2334 #else
2335 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2336 {
2337 TCGv_i32 tpc = tcg_const_i32(dc->pc);
2338
2339 gen_helper_check_atomctl(cpu_env, tpc, addr);
2340 tcg_temp_free(tpc);
2341 }
2342 #endif
2343
2344 static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[],
2345 const uint32_t par[])
2346 {
2347 TCGv_i32 tmp = tcg_temp_local_new_i32();
2348 TCGv_i32 addr = tcg_temp_local_new_i32();
2349 MemOp mop;
2350
2351 tcg_gen_mov_i32(tmp, arg[0].in);
2352 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
2353 mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr);
2354 gen_check_atomctl(dc, addr);
2355 tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1],
2356 tmp, dc->cring, mop);
2357 tcg_temp_free(addr);
2358 tcg_temp_free(tmp);
2359 }
2360
2361 static void translate_s32e(DisasContext *dc, const OpcodeArg arg[],
2362 const uint32_t par[])
2363 {
2364 TCGv_i32 addr = tcg_temp_new_i32();
2365 MemOp mop;
2366
2367 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
2368 mop = gen_load_store_alignment(dc, MO_TEUL, addr);
2369 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, mop);
2370 tcg_temp_free(addr);
2371 }
2372
2373 static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[],
2374 const uint32_t par[])
2375 {
2376 TCGv_i32 prev = tcg_temp_new_i32();
2377 TCGv_i32 addr = tcg_temp_local_new_i32();
2378 TCGv_i32 res = tcg_temp_local_new_i32();
2379 TCGLabel *label = gen_new_label();
2380 MemOp mop;
2381
2382 tcg_gen_movi_i32(res, 0);
2383 tcg_gen_mov_i32(addr, arg[1].in);
2384 mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr);
2385 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, label);
2386 gen_check_exclusive(dc, addr, true);
2387 tcg_gen_atomic_cmpxchg_i32(prev, cpu_exclusive_addr, cpu_exclusive_val,
2388 arg[0].in, dc->cring, mop);
2389 tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val);
2390 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val,
2391 prev, cpu_exclusive_val, prev, cpu_exclusive_val);
2392 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
2393 gen_set_label(label);
2394 tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1);
2395 tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1);
2396 tcg_temp_free(prev);
2397 tcg_temp_free(addr);
2398 tcg_temp_free(res);
2399 }
2400
2401 static void translate_salt(DisasContext *dc, const OpcodeArg arg[],
2402 const uint32_t par[])
2403 {
2404 tcg_gen_setcond_i32(par[0],
2405 arg[0].out,
2406 arg[1].in, arg[2].in);
2407 }
2408
2409 static void translate_sext(DisasContext *dc, const OpcodeArg arg[],
2410 const uint32_t par[])
2411 {
2412 int shift = 31 - arg[2].imm;
2413
2414 if (shift == 24) {
2415 tcg_gen_ext8s_i32(arg[0].out, arg[1].in);
2416 } else if (shift == 16) {
2417 tcg_gen_ext16s_i32(arg[0].out, arg[1].in);
2418 } else {
2419 TCGv_i32 tmp = tcg_temp_new_i32();
2420 tcg_gen_shli_i32(tmp, arg[1].in, shift);
2421 tcg_gen_sari_i32(arg[0].out, tmp, shift);
2422 tcg_temp_free(tmp);
2423 }
2424 }
2425
2426 static uint32_t test_exceptions_simcall(DisasContext *dc,
2427 const OpcodeArg arg[],
2428 const uint32_t par[])
2429 {
2430 #ifdef CONFIG_USER_ONLY
2431 bool ill = true;
2432 #else
2433 /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
2434 bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
2435 #endif
2436 if (ill || !semihosting_enabled()) {
2437 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
2438 }
2439 return ill ? XTENSA_OP_ILL : 0;
2440 }
2441
2442 static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
2443 const uint32_t par[])
2444 {
2445 #ifndef CONFIG_USER_ONLY
2446 if (semihosting_enabled()) {
2447 gen_helper_simcall(cpu_env);
2448 }
2449 #endif
2450 }
2451
2452 /*
2453 * Note: 64 bit ops are used here solely because SAR values
2454 * have range 0..63
2455 */
2456 #define gen_shift_reg(cmd, reg) do { \
2457 TCGv_i64 tmp = tcg_temp_new_i64(); \
2458 tcg_gen_extu_i32_i64(tmp, reg); \
2459 tcg_gen_##cmd##_i64(v, v, tmp); \
2460 tcg_gen_extrl_i64_i32(arg[0].out, v); \
2461 tcg_temp_free_i64(v); \
2462 tcg_temp_free_i64(tmp); \
2463 } while (0)
2464
2465 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2466
2467 static void translate_sll(DisasContext *dc, const OpcodeArg arg[],
2468 const uint32_t par[])
2469 {
2470 if (dc->sar_m32_5bit) {
2471 tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32);
2472 } else {
2473 TCGv_i64 v = tcg_temp_new_i64();
2474 TCGv_i32 s = tcg_const_i32(32);
2475 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
2476 tcg_gen_andi_i32(s, s, 0x3f);
2477 tcg_gen_extu_i32_i64(v, arg[1].in);
2478 gen_shift_reg(shl, s);
2479 tcg_temp_free(s);
2480 }
2481 }
2482
2483 static void translate_slli(DisasContext *dc, const OpcodeArg arg[],
2484 const uint32_t par[])
2485 {
2486 if (arg[2].imm == 32) {
2487 qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
2488 arg[0].imm, arg[1].imm);
2489 }
2490 tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f);
2491 }
2492
2493 static void translate_sra(DisasContext *dc, const OpcodeArg arg[],
2494 const uint32_t par[])
2495 {
2496 if (dc->sar_m32_5bit) {
2497 tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
2498 } else {
2499 TCGv_i64 v = tcg_temp_new_i64();
2500 tcg_gen_ext_i32_i64(v, arg[1].in);
2501 gen_shift(sar);
2502 }
2503 }
2504
2505 static void translate_srai(DisasContext *dc, const OpcodeArg arg[],
2506 const uint32_t par[])
2507 {
2508 tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm);
2509 }
2510
2511 static void translate_src(DisasContext *dc, const OpcodeArg arg[],
2512 const uint32_t par[])
2513 {
2514 TCGv_i64 v = tcg_temp_new_i64();
2515 tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in);
2516 gen_shift(shr);
2517 }
2518
2519 static void translate_srl(DisasContext *dc, const OpcodeArg arg[],
2520 const uint32_t par[])
2521 {
2522 if (dc->sar_m32_5bit) {
2523 tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
2524 } else {
2525 TCGv_i64 v = tcg_temp_new_i64();
2526 tcg_gen_extu_i32_i64(v, arg[1].in);
2527 gen_shift(shr);
2528 }
2529 }
2530
2531 #undef gen_shift
2532 #undef gen_shift_reg
2533
2534 static void translate_srli(DisasContext *dc, const OpcodeArg arg[],
2535 const uint32_t par[])
2536 {
2537 tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm);
2538 }
2539
2540 static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[],
2541 const uint32_t par[])
2542 {
2543 TCGv_i32 tmp = tcg_temp_new_i32();
2544 tcg_gen_shli_i32(tmp, arg[0].in, 3);
2545 gen_left_shift_sar(dc, tmp);
2546 tcg_temp_free(tmp);
2547 }
2548
2549 static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[],
2550 const uint32_t par[])
2551 {
2552 TCGv_i32 tmp = tcg_temp_new_i32();
2553 tcg_gen_shli_i32(tmp, arg[0].in, 3);
2554 gen_right_shift_sar(dc, tmp);
2555 tcg_temp_free(tmp);
2556 }
2557
2558 static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
2559 const uint32_t par[])
2560 {
2561 TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
2562 gen_right_shift_sar(dc, tmp);
2563 tcg_temp_free(tmp);
2564 }
2565
2566 static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
2567 const uint32_t par[])
2568 {
2569 gen_left_shift_sar(dc, arg[0].in);
2570 }
2571
2572 static void translate_ssr(DisasContext *dc, const OpcodeArg arg[],
2573 const uint32_t par[])
2574 {
2575 gen_right_shift_sar(dc, arg[0].in);
2576 }
2577
2578 static void translate_sub(DisasContext *dc, const OpcodeArg arg[],
2579 const uint32_t par[])
2580 {
2581 tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in);
2582 }
2583
2584 static void translate_subx(DisasContext *dc, const OpcodeArg arg[],
2585 const uint32_t par[])
2586 {
2587 TCGv_i32 tmp = tcg_temp_new_i32();
2588 tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
2589 tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in);
2590 tcg_temp_free(tmp);
2591 }
2592
2593 static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
2594 const uint32_t par[])
2595 {
2596 #ifndef CONFIG_USER_ONLY
2597 gen_waiti(dc, arg[0].imm);
2598 #endif
2599 }
2600
2601 static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
2602 const uint32_t par[])
2603 {
2604 #ifndef CONFIG_USER_ONLY
2605 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2606
2607 gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
2608 tcg_temp_free(dtlb);
2609 #endif
2610 }
2611
2612 static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[],
2613 const uint32_t par[])
2614 {
2615 #ifndef CONFIG_USER_ONLY
2616 gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
2617 #endif
2618 }
2619
2620 static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
2621 const uint32_t par[])
2622 {
2623 gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
2624 }
2625
2626 static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
2627 const uint32_t par[])
2628 {
2629 /* TODO: GPIO32 may be a part of coprocessor */
2630 tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in);
2631 }
2632
2633 static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
2634 const uint32_t par[])
2635 {
2636 if (sr_name[par[0]]) {
2637 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2638 }
2639 }
2640
2641 static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
2642 const uint32_t par[])
2643 {
2644 if (sr_name[par[0]]) {
2645 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2646 }
2647 }
2648
2649 static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
2650 const uint32_t par[])
2651 {
2652 tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in);
2653 }
2654
2655 static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
2656 const uint32_t par[])
2657 {
2658 #ifndef CONFIG_USER_ONLY
2659 uint32_t id = par[0] - CCOMPARE;
2660 TCGv_i32 tmp = tcg_const_i32(id);
2661
2662 assert(id < dc->config->nccompare);
2663 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2664 gen_io_start();
2665 }
2666 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2667 gen_helper_update_ccompare(cpu_env, tmp);
2668 tcg_temp_free(tmp);
2669 #endif
2670 }
2671
2672 static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2673 const uint32_t par[])
2674 {
2675 #ifndef CONFIG_USER_ONLY
2676 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2677 gen_io_start();
2678 }
2679 gen_helper_wsr_ccount(cpu_env, arg[0].in);
2680 #endif
2681 }
2682
2683 static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
2684 const uint32_t par[])
2685 {
2686 #ifndef CONFIG_USER_ONLY
2687 unsigned id = par[0] - DBREAKA;
2688 TCGv_i32 tmp = tcg_const_i32(id);
2689
2690 assert(id < dc->config->ndbreak);
2691 gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
2692 tcg_temp_free(tmp);
2693 #endif
2694 }
2695
2696 static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
2697 const uint32_t par[])
2698 {
2699 #ifndef CONFIG_USER_ONLY
2700 unsigned id = par[0] - DBREAKC;
2701 TCGv_i32 tmp = tcg_const_i32(id);
2702
2703 assert(id < dc->config->ndbreak);
2704 gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
2705 tcg_temp_free(tmp);
2706 #endif
2707 }
2708
2709 static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
2710 const uint32_t par[])
2711 {
2712 #ifndef CONFIG_USER_ONLY
2713 unsigned id = par[0] - IBREAKA;
2714 TCGv_i32 tmp = tcg_const_i32(id);
2715
2716 assert(id < dc->config->nibreak);
2717 gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
2718 tcg_temp_free(tmp);
2719 #endif
2720 }
2721
2722 static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[],
2723 const uint32_t par[])
2724 {
2725 #ifndef CONFIG_USER_ONLY
2726 gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);
2727 #endif
2728 }
2729
2730 static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[],
2731 const uint32_t par[])
2732 {
2733 #ifndef CONFIG_USER_ONLY
2734 if (dc->icount) {
2735 tcg_gen_mov_i32(dc->next_icount, arg[0].in);
2736 } else {
2737 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2738 }
2739 #endif
2740 }
2741
2742 static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[],
2743 const uint32_t par[])
2744 {
2745 #ifndef CONFIG_USER_ONLY
2746 gen_helper_intclear(cpu_env, arg[0].in);
2747 #endif
2748 }
2749
2750 static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[],
2751 const uint32_t par[])
2752 {
2753 #ifndef CONFIG_USER_ONLY
2754 gen_helper_intset(cpu_env, arg[0].in);
2755 #endif
2756 }
2757
2758 static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[],
2759 const uint32_t par[])
2760 {
2761 #ifndef CONFIG_USER_ONLY
2762 gen_helper_wsr_memctl(cpu_env, arg[0].in);
2763 #endif
2764 }
2765
2766 static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[],
2767 const uint32_t par[])
2768 {
2769 #ifndef CONFIG_USER_ONLY
2770 gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
2771 #endif
2772 }
2773
2774 static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[],
2775 const uint32_t par[])
2776 {
2777 #ifndef CONFIG_USER_ONLY
2778 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
2779 PS_UM | PS_EXCM | PS_INTLEVEL;
2780
2781 if (option_enabled(dc, XTENSA_OPTION_MMU) ||
2782 option_enabled(dc, XTENSA_OPTION_MPU)) {
2783 mask |= PS_RING;
2784 }
2785 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask);
2786 #endif
2787 }
2788
2789 static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[],
2790 const uint32_t par[])
2791 {
2792 #ifndef CONFIG_USER_ONLY
2793 gen_helper_wsr_rasid(cpu_env, arg[0].in);
2794 #endif
2795 }
2796
2797 static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[],
2798 const uint32_t par[])
2799 {
2800 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f);
2801 if (dc->sar_m32_5bit) {
2802 tcg_gen_discard_i32(dc->sar_m32);
2803 }
2804 dc->sar_5bit = false;
2805 dc->sar_m32_5bit = false;
2806 }
2807
2808 static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[],
2809 const uint32_t par[])
2810 {
2811 #ifndef CONFIG_USER_ONLY
2812 tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in);
2813 #endif
2814 }
2815
2816 static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[],
2817 const uint32_t par[])
2818 {
2819 #ifndef CONFIG_USER_ONLY
2820 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in,
2821 (1 << dc->config->nareg / 4) - 1);
2822 #endif
2823 }
2824
2825 static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
2826 const uint32_t par[])
2827 {
2828 tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
2829 }
2830
2831 static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
2832 const uint32_t par[])
2833 {
2834 tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in);
2835 }
2836
2837 static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
2838 const uint32_t par[])
2839 {
2840 if (sr_name[par[0]]) {
2841 TCGv_i32 tmp = tcg_temp_new_i32();
2842
2843 tcg_gen_mov_i32(tmp, arg[0].in);
2844 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2845 tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2846 tcg_temp_free(tmp);
2847 } else {
2848 tcg_gen_movi_i32(arg[0].out, 0);
2849 }
2850 }
2851
2852 static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
2853 const uint32_t par[])
2854 {
2855 if (sr_name[par[0]]) {
2856 TCGv_i32 tmp = tcg_temp_new_i32();
2857
2858 tcg_gen_mov_i32(tmp, arg[0].in);
2859 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2860 tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2861 tcg_temp_free(tmp);
2862 } else {
2863 tcg_gen_movi_i32(arg[0].out, 0);
2864 }
2865 }
2866
2867 static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2868 const uint32_t par[])
2869 {
2870 #ifndef CONFIG_USER_ONLY
2871 TCGv_i32 tmp = tcg_temp_new_i32();
2872
2873 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2874 gen_io_start();
2875 }
2876
2877 gen_helper_update_ccount(cpu_env);
2878 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
2879 gen_helper_wsr_ccount(cpu_env, arg[0].in);
2880 tcg_gen_mov_i32(arg[0].out, tmp);
2881 tcg_temp_free(tmp);
2882
2883 #endif
2884 }
2885
2886 #define gen_translate_xsr(name) \
2887 static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
2888 const uint32_t par[]) \
2889 { \
2890 TCGv_i32 tmp = tcg_temp_new_i32(); \
2891 \
2892 if (sr_name[par[0]]) { \
2893 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2894 } else { \
2895 tcg_gen_movi_i32(tmp, 0); \
2896 } \
2897 translate_wsr_##name(dc, arg, par); \
2898 tcg_gen_mov_i32(arg[0].out, tmp); \
2899 tcg_temp_free(tmp); \
2900 }
2901
2902 gen_translate_xsr(acchi)
2903 gen_translate_xsr(ccompare)
2904 gen_translate_xsr(dbreaka)
2905 gen_translate_xsr(dbreakc)
2906 gen_translate_xsr(ibreaka)
2907 gen_translate_xsr(ibreakenable)
2908 gen_translate_xsr(icount)
2909 gen_translate_xsr(memctl)
2910 gen_translate_xsr(mpuenb)
2911 gen_translate_xsr(ps)
2912 gen_translate_xsr(rasid)
2913 gen_translate_xsr(sar)
2914 gen_translate_xsr(windowbase)
2915 gen_translate_xsr(windowstart)
2916
2917 #undef gen_translate_xsr
2918
2919 static const XtensaOpcodeOps core_ops[] = {
2920 {
2921 .name = "abs",
2922 .translate = translate_abs,
2923 }, {
2924 .name = (const char * const[]) {
2925 "add", "add.n", NULL,
2926 },
2927 .translate = translate_add,
2928 .op_flags = XTENSA_OP_NAME_ARRAY,
2929 }, {
2930 .name = (const char * const[]) {
2931 "addi", "addi.n", NULL,
2932 },
2933 .translate = translate_addi,
2934 .op_flags = XTENSA_OP_NAME_ARRAY,
2935 }, {
2936 .name = "addmi",
2937 .translate = translate_addi,
2938 }, {
2939 .name = "addx2",
2940 .translate = translate_addx,
2941 .par = (const uint32_t[]){1},
2942 }, {
2943 .name = "addx4",
2944 .translate = translate_addx,
2945 .par = (const uint32_t[]){2},
2946 }, {
2947 .name = "addx8",
2948 .translate = translate_addx,
2949 .par = (const uint32_t[]){3},
2950 }, {
2951 .name = "all4",
2952 .translate = translate_all,
2953 .par = (const uint32_t[]){true, 4},
2954 }, {
2955 .name = "all8",
2956 .translate = translate_all,
2957 .par = (const uint32_t[]){true, 8},
2958 }, {
2959 .name = "and",
2960 .translate = translate_and,
2961 }, {
2962 .name = "andb",
2963 .translate = translate_boolean,
2964 .par = (const uint32_t[]){BOOLEAN_AND},
2965 }, {
2966 .name = "andbc",
2967 .translate = translate_boolean,
2968 .par = (const uint32_t[]){BOOLEAN_ANDC},
2969 }, {
2970 .name = "any4",
2971 .translate = translate_all,
2972 .par = (const uint32_t[]){false, 4},
2973 }, {
2974 .name = "any8",
2975 .translate = translate_all,
2976 .par = (const uint32_t[]){false, 8},
2977 }, {
2978 .name = (const char * const[]) {
2979 "ball", "ball.w15", "ball.w18", NULL,
2980 },
2981 .translate = translate_ball,
2982 .par = (const uint32_t[]){TCG_COND_EQ},
2983 .op_flags = XTENSA_OP_NAME_ARRAY,
2984 }, {
2985 .name = (const char * const[]) {
2986 "bany", "bany.w15", "bany.w18", NULL,
2987 },
2988 .translate = translate_bany,
2989 .par = (const uint32_t[]){TCG_COND_NE},
2990 .op_flags = XTENSA_OP_NAME_ARRAY,
2991 }, {
2992 .name = (const char * const[]) {
2993 "bbc", "bbc.w15", "bbc.w18", NULL,
2994 },
2995 .translate = translate_bb,
2996 .par = (const uint32_t[]){TCG_COND_EQ},
2997 .op_flags = XTENSA_OP_NAME_ARRAY,
2998 }, {
2999 .name = (const char * const[]) {
3000 "bbci", "bbci.w15", "bbci.w18", NULL,
3001 },
3002 .translate = translate_bbi,
3003 .par = (const uint32_t[]){TCG_COND_EQ},
3004 .op_flags = XTENSA_OP_NAME_ARRAY,
3005 }, {
3006 .name = (const char * const[]) {
3007 "bbs", "bbs.w15", "bbs.w18", NULL,
3008 },
3009 .translate = translate_bb,
3010 .par = (const uint32_t[]){TCG_COND_NE},
3011 .op_flags = XTENSA_OP_NAME_ARRAY,
3012 }, {
3013 .name = (const char * const[]) {
3014 "bbsi", "bbsi.w15", "bbsi.w18", NULL,
3015 },
3016 .translate = translate_bbi,
3017 .par = (const uint32_t[]){TCG_COND_NE},
3018 .op_flags = XTENSA_OP_NAME_ARRAY,
3019 }, {
3020 .name = (const char * const[]) {
3021 "beq", "beq.w15", "beq.w18", NULL,
3022 },
3023 .translate = translate_b,
3024 .par = (const uint32_t[]){TCG_COND_EQ},
3025 .op_flags = XTENSA_OP_NAME_ARRAY,
3026 }, {
3027 .name = (const char * const[]) {
3028 "beqi", "beqi.w15", "beqi.w18", NULL,
3029 },
3030 .translate = translate_bi,
3031 .par = (const uint32_t[]){TCG_COND_EQ},
3032 .op_flags = XTENSA_OP_NAME_ARRAY,
3033 }, {
3034 .name = (const char * const[]) {
3035 "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL,
3036 },
3037 .translate = translate_bz,
3038 .par = (const uint32_t[]){TCG_COND_EQ},
3039 .op_flags = XTENSA_OP_NAME_ARRAY,
3040 }, {
3041 .name = "bf",
3042 .translate = translate_bp,
3043 .par = (const uint32_t[]){TCG_COND_EQ},
3044 }, {
3045 .name = (const char * const[]) {
3046 "bge", "bge.w15", "bge.w18", NULL,
3047 },
3048 .translate = translate_b,
3049 .par = (const uint32_t[]){TCG_COND_GE},
3050 .op_flags = XTENSA_OP_NAME_ARRAY,
3051 }, {
3052 .name = (const char * const[]) {
3053 "bgei", "bgei.w15", "bgei.w18", NULL,
3054 },
3055 .translate = translate_bi,
3056 .par = (const uint32_t[]){TCG_COND_GE},
3057 .op_flags = XTENSA_OP_NAME_ARRAY,
3058 }, {
3059 .name = (const char * const[]) {
3060 "bgeu", "bgeu.w15", "bgeu.w18", NULL,
3061 },
3062 .translate = translate_b,
3063 .par = (const uint32_t[]){TCG_COND_GEU},
3064 .op_flags = XTENSA_OP_NAME_ARRAY,
3065 }, {
3066 .name = (const char * const[]) {
3067 "bgeui", "bgeui.w15", "bgeui.w18", NULL,
3068 },
3069 .translate = translate_bi,
3070 .par = (const uint32_t[]){TCG_COND_GEU},
3071 .op_flags = XTENSA_OP_NAME_ARRAY,
3072 }, {
3073 .name = (const char * const[]) {
3074 "bgez", "bgez.w15", "bgez.w18", NULL,
3075 },
3076 .translate = translate_bz,
3077 .par = (const uint32_t[]){TCG_COND_GE},
3078 .op_flags = XTENSA_OP_NAME_ARRAY,
3079 }, {
3080 .name = (const char * const[]) {
3081 "blt", "blt.w15", "blt.w18", NULL,
3082 },
3083 .translate = translate_b,
3084 .par = (const uint32_t[]){TCG_COND_LT},
3085 .op_flags = XTENSA_OP_NAME_ARRAY,
3086 }, {
3087 .name = (const char * const[]) {
3088 "blti", "blti.w15", "blti.w18", NULL,
3089 },
3090 .translate = translate_bi,
3091 .par = (const uint32_t[]){TCG_COND_LT},
3092 .op_flags = XTENSA_OP_NAME_ARRAY,
3093 }, {
3094 .name = (const char * const[]) {
3095 "bltu", "bltu.w15", "bltu.w18", NULL,
3096 },
3097 .translate = translate_b,
3098 .par = (const uint32_t[]){TCG_COND_LTU},
3099 .op_flags = XTENSA_OP_NAME_ARRAY,
3100 }, {
3101 .name = (const char * const[]) {
3102 "bltui", "bltui.w15", "bltui.w18", NULL,
3103 },
3104 .translate = translate_bi,
3105 .par = (const uint32_t[]){TCG_COND_LTU},
3106 .op_flags = XTENSA_OP_NAME_ARRAY,
3107 }, {
3108 .name = (const char * const[]) {
3109 "bltz", "bltz.w15", "bltz.w18", NULL,
3110 },
3111 .translate = translate_bz,
3112 .par = (const uint32_t[]){TCG_COND_LT},
3113 .op_flags = XTENSA_OP_NAME_ARRAY,
3114 }, {
3115 .name = (const char * const[]) {
3116 "bnall", "bnall.w15", "bnall.w18", NULL,
3117 },
3118 .translate = translate_ball,
3119 .par = (const uint32_t[]){TCG_COND_NE},
3120 .op_flags = XTENSA_OP_NAME_ARRAY,
3121 }, {
3122 .name = (const char * const[]) {
3123 "bne", "bne.w15", "bne.w18", NULL,
3124 },
3125 .translate = translate_b,
3126 .par = (const uint32_t[]){TCG_COND_NE},
3127 .op_flags = XTENSA_OP_NAME_ARRAY,
3128 }, {
3129 .name = (const char * const[]) {
3130 "bnei", "bnei.w15", "bnei.w18", NULL,
3131 },
3132 .translate = translate_bi,
3133 .par = (const uint32_t[]){TCG_COND_NE},
3134 .op_flags = XTENSA_OP_NAME_ARRAY,
3135 }, {
3136 .name = (const char * const[]) {
3137 "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL,
3138 },
3139 .translate = translate_bz,
3140 .par = (const uint32_t[]){TCG_COND_NE},
3141 .op_flags = XTENSA_OP_NAME_ARRAY,
3142 }, {
3143 .name = (const char * const[]) {
3144 "bnone", "bnone.w15", "bnone.w18", NULL,
3145 },
3146 .translate = translate_bany,
3147 .par = (const uint32_t[]){TCG_COND_EQ},
3148 .op_flags = XTENSA_OP_NAME_ARRAY,
3149 }, {
3150 .name = "break",
3151 .translate = translate_nop,
3152 .par = (const uint32_t[]){DEBUGCAUSE_BI},
3153 .op_flags = XTENSA_OP_DEBUG_BREAK,
3154 }, {
3155 .name = "break.n",
3156 .translate = translate_nop,
3157 .par = (const uint32_t[]){DEBUGCAUSE_BN},
3158 .op_flags = XTENSA_OP_DEBUG_BREAK,
3159 }, {
3160 .name = "bt",
3161 .translate = translate_bp,
3162 .par = (const uint32_t[]){TCG_COND_NE},
3163 }, {
3164 .name = "call0",
3165 .translate = translate_call0,
3166 }, {
3167 .name = "call12",
3168 .translate = translate_callw,
3169 .par = (const uint32_t[]){3},
3170 }, {
3171 .name = "call4",
3172 .translate = translate_callw,
3173 .par = (const uint32_t[]){1},
3174 }, {
3175 .name = "call8",
3176 .translate = translate_callw,
3177 .par = (const uint32_t[]){2},
3178 }, {
3179 .name = "callx0",
3180 .translate = translate_callx0,
3181 }, {
3182 .name = "callx12",
3183 .translate = translate_callxw,
3184 .par = (const uint32_t[]){3},
3185 }, {
3186 .name = "callx4",
3187 .translate = translate_callxw,
3188 .par = (const uint32_t[]){1},
3189 }, {
3190 .name = "callx8",
3191 .translate = translate_callxw,
3192 .par = (const uint32_t[]){2},
3193 }, {
3194 .name = "clamps",
3195 .translate = translate_clamps,
3196 }, {
3197 .name = "clrb_expstate",
3198 .translate = translate_clrb_expstate,
3199 }, {
3200 .name = "clrex",
3201 .translate = translate_clrex,
3202 }, {
3203 .name = "const16",
3204 .translate = translate_const16,
3205 }, {
3206 .name = "depbits",
3207 .translate = translate_depbits,
3208 }, {
3209 .name = "dhi",
3210 .translate = translate_dcache,
3211 .op_flags = XTENSA_OP_PRIVILEGED,
3212 }, {
3213 .name = "dhi.b",
3214 .translate = translate_nop,
3215 }, {
3216 .name = "dhu",
3217 .translate = translate_dcache,
3218 .op_flags = XTENSA_OP_PRIVILEGED,
3219 }, {
3220 .name = "dhwb",
3221 .translate = translate_dcache,
3222 }, {
3223 .name = "dhwb.b",
3224 .translate = translate_nop,
3225 }, {
3226 .name = "dhwbi",
3227 .translate = translate_dcache,
3228 }, {
3229 .name = "dhwbi.b",
3230 .translate = translate_nop,
3231 }, {
3232 .name = "dii",
3233 .translate = translate_nop,
3234 .op_flags = XTENSA_OP_PRIVILEGED,
3235 }, {
3236 .name = "diu",
3237 .translate = translate_nop,
3238 .op_flags = XTENSA_OP_PRIVILEGED,
3239 }, {
3240 .name = "diwb",
3241 .translate = translate_nop,
3242 .op_flags = XTENSA_OP_PRIVILEGED,
3243 }, {
3244 .name = "diwbi",
3245 .translate = translate_nop,
3246 .op_flags = XTENSA_OP_PRIVILEGED,
3247 }, {
3248 .name = "diwbui.p",
3249 .translate = translate_diwbuip,
3250 .op_flags = XTENSA_OP_PRIVILEGED,
3251 }, {
3252 .name = "dpfl",
3253 .translate = translate_dcache,
3254 .op_flags = XTENSA_OP_PRIVILEGED,
3255 }, {
3256 .name = "dpfm.b",
3257 .translate = translate_nop,
3258 }, {
3259 .name = "dpfm.bf",
3260 .translate = translate_nop,
3261 }, {
3262 .name = "dpfr",
3263 .translate = translate_nop,
3264 }, {
3265 .name = "dpfr.b",
3266 .translate = translate_nop,
3267 }, {
3268 .name = "dpfr.bf",
3269 .translate = translate_nop,
3270 }, {
3271 .name = "dpfro",
3272 .translate = translate_nop,
3273 }, {
3274 .name = "dpfw",
3275 .translate = translate_nop,
3276 }, {
3277 .name = "dpfw.b",
3278 .translate = translate_nop,
3279 }, {
3280 .name = "dpfw.bf",
3281 .translate = translate_nop,
3282 }, {
3283 .name = "dpfwo",
3284 .translate = translate_nop,
3285 }, {
3286 .name = "dsync",
3287 .translate = translate_nop,
3288 }, {
3289 .name = "entry",
3290 .translate = translate_entry,
3291 .test_exceptions = test_exceptions_entry,
3292 .test_overflow = test_overflow_entry,
3293 .op_flags = XTENSA_OP_EXIT_TB_M1 |
3294 XTENSA_OP_SYNC_REGISTER_WINDOW,
3295 }, {
3296 .name = "esync",
3297 .translate = translate_nop,
3298 }, {
3299 .name = "excw",
3300 .translate = translate_nop,
3301 }, {
3302 .name = "extui",
3303 .translate = translate_extui,
3304 }, {
3305 .name = "extw",
3306 .translate = translate_memw,
3307 }, {
3308 .name = "getex",
3309 .translate = translate_getex,
3310 }, {
3311 .name = "hwwdtlba",
3312 .op_flags = XTENSA_OP_ILL,
3313 }, {
3314 .name = "hwwitlba",
3315 .op_flags = XTENSA_OP_ILL,
3316 }, {
3317 .name = "idtlb",
3318 .translate = translate_itlb,
3319 .par = (const uint32_t[]){true},
3320 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3321 }, {
3322 .name = "ihi",
3323 .translate = translate_icache,
3324 }, {
3325 .name = "ihu",
3326 .translate = translate_icache,
3327 .op_flags = XTENSA_OP_PRIVILEGED,
3328 }, {
3329 .name = "iii",
3330 .translate = translate_nop,
3331 .op_flags = XTENSA_OP_PRIVILEGED,
3332 }, {
3333 .name = "iitlb",
3334 .translate = translate_itlb,
3335 .par = (const uint32_t[]){false},
3336 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3337 }, {
3338 .name = "iiu",
3339 .translate = translate_nop,
3340 .op_flags = XTENSA_OP_PRIVILEGED,
3341 }, {
3342 .name = (const char * const[]) {
3343 "ill", "ill.n", NULL,
3344 },
3345 .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY,
3346 }, {
3347 .name = "ipf",
3348 .translate = translate_nop,
3349 }, {
3350 .name = "ipfl",
3351 .translate = translate_icache,
3352 .op_flags = XTENSA_OP_PRIVILEGED,
3353 }, {
3354 .name = "isync",
3355 .translate = translate_nop,
3356 }, {
3357 .name = "j",
3358 .translate = translate_j,
3359 }, {
3360 .name = "jx",
3361 .translate = translate_jx,
3362 }, {
3363 .name = "l16si",
3364 .translate = translate_ldst,
3365 .par = (const uint32_t[]){MO_TESW, false, false},
3366 .op_flags = XTENSA_OP_LOAD,
3367 }, {
3368 .name = "l16ui",
3369 .translate = translate_ldst,
3370 .par = (const uint32_t[]){MO_TEUW, false, false},
3371 .op_flags = XTENSA_OP_LOAD,
3372 }, {
3373 .name = "l32ai",
3374 .translate = translate_ldst,
3375 .par = (const uint32_t[]){MO_TEUL | MO_ALIGN, true, false},
3376 .op_flags = XTENSA_OP_LOAD,
3377 }, {
3378 .name = "l32e",
3379 .translate = translate_l32e,
3380 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD,
3381 }, {
3382 .name = "l32ex",
3383 .translate = translate_l32ex,
3384 .op_flags = XTENSA_OP_LOAD,
3385 }, {
3386 .name = (const char * const[]) {
3387 "l32i", "l32i.n", NULL,
3388 },
3389 .translate = translate_ldst,
3390 .par = (const uint32_t[]){MO_TEUL, false, false},
3391 .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD,
3392 }, {
3393 .name = "l32r",
3394 .translate = translate_l32r,
3395 .op_flags = XTENSA_OP_LOAD,
3396 }, {
3397 .name = "l8ui",
3398 .translate = translate_ldst,
3399 .par = (const uint32_t[]){MO_UB, false, false},
3400 .op_flags = XTENSA_OP_LOAD,
3401 }, {
3402 .name = "lddec",
3403 .translate = translate_mac16,
3404 .par = (const uint32_t[]){MAC16_NONE, 0, -4},
3405 .op_flags = XTENSA_OP_LOAD,
3406 }, {
3407 .name = "ldinc",
3408 .translate = translate_mac16,
3409 .par = (const uint32_t[]){MAC16_NONE, 0, 4},
3410 .op_flags = XTENSA_OP_LOAD,
3411 }, {
3412 .name = "ldpte",
3413 .op_flags = XTENSA_OP_ILL,
3414 }, {
3415 .name = (const char * const[]) {
3416 "loop", "loop.w15", NULL,
3417 },
3418 .translate = translate_loop,
3419 .par = (const uint32_t[]){TCG_COND_NEVER},
3420 .op_flags = XTENSA_OP_NAME_ARRAY,
3421 }, {
3422 .name = (const char * const[]) {
3423 "loopgtz", "loopgtz.w15", NULL,
3424 },
3425 .translate = translate_loop,
3426 .par = (const uint32_t[]){TCG_COND_GT},
3427 .op_flags = XTENSA_OP_NAME_ARRAY,
3428 }, {
3429 .name = (const char * const[]) {
3430 "loopnez", "loopnez.w15", NULL,
3431 },
3432 .translate = translate_loop,
3433 .par = (const uint32_t[]){TCG_COND_NE},
3434 .op_flags = XTENSA_OP_NAME_ARRAY,
3435 }, {
3436 .name = "max",
3437 .translate = translate_smax,
3438 }, {
3439 .name = "maxu",
3440 .translate = translate_umax,
3441 }, {
3442 .name = "memw",
3443 .translate = translate_memw,
3444 }, {
3445 .name = "min",
3446 .translate = translate_smin,
3447 }, {
3448 .name = "minu",
3449 .translate = translate_umin,
3450 }, {
3451 .name = (const char * const[]) {
3452 "mov", "mov.n", NULL,
3453 },
3454 .translate = translate_mov,
3455 .op_flags = XTENSA_OP_NAME_ARRAY,
3456 }, {
3457 .name = "moveqz",
3458 .translate = translate_movcond,
3459 .par = (const uint32_t[]){TCG_COND_EQ},
3460 }, {
3461 .name = "movf",
3462 .translate = translate_movp,
3463 .par = (const uint32_t[]){TCG_COND_EQ},
3464 }, {
3465 .name = "movgez",
3466 .translate = translate_movcond,
3467 .par = (const uint32_t[]){TCG_COND_GE},
3468 }, {
3469 .name = "movi",
3470 .translate = translate_movi,
3471 }, {
3472 .name = "movi.n",
3473 .translate = translate_movi,
3474 }, {
3475 .name = "movltz",
3476 .translate = translate_movcond,
3477 .par = (const uint32_t[]){TCG_COND_LT},
3478 }, {
3479 .name = "movnez",
3480 .translate = translate_movcond,
3481 .par = (const uint32_t[]){TCG_COND_NE},
3482 }, {
3483 .name = "movsp",
3484 .translate = translate_movsp,
3485 .op_flags = XTENSA_OP_ALLOCA,
3486 }, {
3487 .name = "movt",
3488 .translate = translate_movp,
3489 .par = (const uint32_t[]){TCG_COND_NE},
3490 }, {
3491 .name = "mul.aa.hh",
3492 .translate = translate_mac16,
3493 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3494 }, {
3495 .name = "mul.aa.hl",
3496 .translate = translate_mac16,
3497 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3498 }, {
3499 .name = "mul.aa.lh",
3500 .translate = translate_mac16,
3501 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3502 }, {
3503 .name = "mul.aa.ll",
3504 .translate = translate_mac16,
3505 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3506 }, {
3507 .name = "mul.ad.hh",
3508 .translate = translate_mac16,
3509 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3510 }, {
3511 .name = "mul.ad.hl",
3512 .translate = translate_mac16,
3513 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3514 }, {
3515 .name = "mul.ad.lh",
3516 .translate = translate_mac16,
3517 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3518 }, {
3519 .name = "mul.ad.ll",
3520 .translate = translate_mac16,
3521 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3522 }, {
3523 .name = "mul.da.hh",
3524 .translate = translate_mac16,
3525 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3526 }, {
3527 .name = "mul.da.hl",
3528 .translate = translate_mac16,
3529 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3530 }, {
3531 .name = "mul.da.lh",
3532 .translate = translate_mac16,
3533 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3534 }, {
3535 .name = "mul.da.ll",
3536 .translate = translate_mac16,
3537 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3538 }, {
3539 .name = "mul.dd.hh",
3540 .translate = translate_mac16,
3541 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3542 }, {
3543 .name = "mul.dd.hl",
3544 .translate = translate_mac16,
3545 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3546 }, {
3547 .name = "mul.dd.lh",
3548 .translate = translate_mac16,
3549 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3550 }, {
3551 .name = "mul.dd.ll",
3552 .translate = translate_mac16,
3553 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3554 }, {
3555 .name = "mul16s",
3556 .translate = translate_mul16,
3557 .par = (const uint32_t[]){true},
3558 }, {
3559 .name = "mul16u",
3560 .translate = translate_mul16,
3561 .par = (const uint32_t[]){false},
3562 }, {
3563 .name = "mula.aa.hh",
3564 .translate = translate_mac16,
3565 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3566 }, {
3567 .name = "mula.aa.hl",
3568 .translate = translate_mac16,
3569 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3570 }, {
3571 .name = "mula.aa.lh",
3572 .translate = translate_mac16,
3573 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3574 }, {
3575 .name = "mula.aa.ll",
3576 .translate = translate_mac16,
3577 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3578 }, {
3579 .name = "mula.ad.hh",
3580 .translate = translate_mac16,
3581 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3582 }, {
3583 .name = "mula.ad.hl",
3584 .translate = translate_mac16,
3585 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3586 }, {
3587 .name = "mula.ad.lh",
3588 .translate = translate_mac16,
3589 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3590 }, {
3591 .name = "mula.ad.ll",
3592 .translate = translate_mac16,
3593 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3594 }, {
3595 .name = "mula.da.hh",
3596 .translate = translate_mac16,
3597 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3598 }, {
3599 .name = "mula.da.hh.lddec",
3600 .translate = translate_mac16,
3601 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},
3602 }, {
3603 .name = "mula.da.hh.ldinc",
3604 .translate = translate_mac16,
3605 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},
3606 }, {
3607 .name = "mula.da.hl",
3608 .translate = translate_mac16,
3609 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3610 }, {
3611 .name = "mula.da.hl.lddec",
3612 .translate = translate_mac16,
3613 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},
3614 }, {
3615 .name = "mula.da.hl.ldinc",
3616 .translate = translate_mac16,
3617 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},
3618 }, {
3619 .name = "mula.da.lh",
3620 .translate = translate_mac16,
3621 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3622 }, {
3623 .name = "mula.da.lh.lddec",
3624 .translate = translate_mac16,
3625 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},
3626 }, {
3627 .name = "mula.da.lh.ldinc",
3628 .translate = translate_mac16,
3629 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},
3630 }, {
3631 .name = "mula.da.ll",
3632 .translate = translate_mac16,
3633 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3634 }, {
3635 .name = "mula.da.ll.lddec",
3636 .translate = translate_mac16,
3637 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},
3638 }, {
3639 .name = "mula.da.ll.ldinc",
3640 .translate = translate_mac16,
3641 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},
3642 }, {
3643 .name = "mula.dd.hh",
3644 .translate = translate_mac16,
3645 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3646 }, {
3647 .name = "mula.dd.hh.lddec",
3648 .translate = translate_mac16,
3649 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},
3650 }, {
3651 .name = "mula.dd.hh.ldinc",
3652 .translate = translate_mac16,
3653 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},
3654 }, {
3655 .name = "mula.dd.hl",
3656 .translate = translate_mac16,
3657 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3658 }, {
3659 .name = "mula.dd.hl.lddec",
3660 .translate = translate_mac16,
3661 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},
3662 }, {
3663 .name = "mula.dd.hl.ldinc",
3664 .translate = translate_mac16,
3665 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},
3666 }, {
3667 .name = "mula.dd.lh",
3668 .translate = translate_mac16,
3669 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3670 }, {
3671 .name = "mula.dd.lh.lddec",
3672 .translate = translate_mac16,
3673 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},
3674 }, {
3675 .name = "mula.dd.lh.ldinc",
3676 .translate = translate_mac16,
3677 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},
3678 }, {
3679 .name = "mula.dd.ll",
3680 .translate = translate_mac16,
3681 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3682 }, {
3683 .name = "mula.dd.ll.lddec",
3684 .translate = translate_mac16,
3685 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},
3686 }, {
3687 .name = "mula.dd.ll.ldinc",
3688 .translate = translate_mac16,
3689 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},
3690 }, {
3691 .name = "mull",
3692 .translate = translate_mull,
3693 }, {
3694 .name = "muls.aa.hh",
3695 .translate = translate_mac16,
3696 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3697 }, {
3698 .name = "muls.aa.hl",
3699 .translate = translate_mac16,
3700 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3701 }, {
3702 .name = "muls.aa.lh",
3703 .translate = translate_mac16,
3704 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3705 }, {
3706 .name = "muls.aa.ll",
3707 .translate = translate_mac16,
3708 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3709 }, {
3710 .name = "muls.ad.hh",
3711 .translate = translate_mac16,
3712 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3713 }, {
3714 .name = "muls.ad.hl",
3715 .translate = translate_mac16,
3716 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3717 }, {
3718 .name = "muls.ad.lh",
3719 .translate = translate_mac16,
3720 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3721 }, {
3722 .name = "muls.ad.ll",
3723 .translate = translate_mac16,
3724 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3725 }, {
3726 .name = "muls.da.hh",
3727 .translate = translate_mac16,
3728 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3729 }, {
3730 .name = "muls.da.hl",
3731 .translate = translate_mac16,
3732 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3733 }, {
3734 .name = "muls.da.lh",
3735 .translate = translate_mac16,
3736 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3737 }, {
3738 .name = "muls.da.ll",
3739 .translate = translate_mac16,
3740 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3741 }, {
3742 .name = "muls.dd.hh",
3743 .translate = translate_mac16,
3744 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3745 }, {
3746 .name = "muls.dd.hl",
3747 .translate = translate_mac16,
3748 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3749 }, {
3750 .name = "muls.dd.lh",
3751 .translate = translate_mac16,
3752 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3753 }, {
3754 .name = "muls.dd.ll",
3755 .translate = translate_mac16,
3756 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3757 }, {
3758 .name = "mulsh",
3759 .translate = translate_mulh,
3760 .par = (const uint32_t[]){true},
3761 }, {
3762 .name = "muluh",
3763 .translate = translate_mulh,
3764 .par = (const uint32_t[]){false},
3765 }, {
3766 .name = "neg",
3767 .translate = translate_neg,
3768 }, {
3769 .name = (const char * const[]) {
3770 "nop", "nop.n", NULL,
3771 },
3772 .translate = translate_nop,
3773 .op_flags = XTENSA_OP_NAME_ARRAY,
3774 }, {
3775 .name = "nsa",
3776 .translate = translate_nsa,
3777 }, {
3778 .name = "nsau",
3779 .translate = translate_nsau,
3780 }, {
3781 .name = "or",
3782 .translate = translate_or,
3783 }, {
3784 .name = "orb",
3785 .translate = translate_boolean,
3786 .par = (const uint32_t[]){BOOLEAN_OR},
3787 }, {
3788 .name = "orbc",
3789 .translate = translate_boolean,
3790 .par = (const uint32_t[]){BOOLEAN_ORC},
3791 }, {
3792 .name = "pdtlb",
3793 .translate = translate_ptlb,
3794 .par = (const uint32_t[]){true},
3795 .op_flags = XTENSA_OP_PRIVILEGED,
3796 }, {
3797 .name = "pfend.a",
3798 .translate = translate_nop,
3799 }, {
3800 .name = "pfend.o",
3801 .translate = translate_nop,
3802 }, {
3803 .name = "pfnxt.f",
3804 .translate = translate_nop,
3805 }, {
3806 .name = "pfwait.a",
3807 .translate = translate_nop,
3808 }, {
3809 .name = "pfwait.r",
3810 .translate = translate_nop,
3811 }, {
3812 .name = "pitlb",
3813 .translate = translate_ptlb,
3814 .par = (const uint32_t[]){false},
3815 .op_flags = XTENSA_OP_PRIVILEGED,
3816 }, {
3817 .name = "pptlb",
3818 .translate = translate_pptlb,
3819 .op_flags = XTENSA_OP_PRIVILEGED,
3820 }, {
3821 .name = "quos",
3822 .translate = translate_quos,
3823 .par = (const uint32_t[]){true},
3824 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3825 }, {
3826 .name = "quou",
3827 .translate = translate_quou,
3828 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3829 }, {
3830 .name = "rdtlb0",
3831 .translate = translate_rtlb,
3832 .par = (const uint32_t[]){true, 0},
3833 .op_flags = XTENSA_OP_PRIVILEGED,
3834 }, {
3835 .name = "rdtlb1",
3836 .translate = translate_rtlb,
3837 .par = (const uint32_t[]){true, 1},
3838 .op_flags = XTENSA_OP_PRIVILEGED,
3839 }, {
3840 .name = "read_impwire",
3841 .translate = translate_read_impwire,
3842 }, {
3843 .name = "rems",
3844 .translate = translate_quos,
3845 .par = (const uint32_t[]){false},
3846 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3847 }, {
3848 .name = "remu",
3849 .translate = translate_remu,
3850 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3851 }, {
3852 .name = "rer",
3853 .translate = translate_rer,
3854 .op_flags = XTENSA_OP_PRIVILEGED,
3855 }, {
3856 .name = (const char * const[]) {
3857 "ret", "ret.n", NULL,
3858 },
3859 .translate = translate_ret,
3860 .op_flags = XTENSA_OP_NAME_ARRAY,
3861 }, {
3862 .name = (const char * const[]) {
3863 "retw", "retw.n", NULL,
3864 },
3865 .translate = translate_retw,
3866 .test_exceptions = test_exceptions_retw,
3867 .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY,
3868 }, {
3869 .name = "rfdd",
3870 .op_flags = XTENSA_OP_ILL,
3871 }, {
3872 .name = "rfde",
3873 .translate = translate_rfde,
3874 .op_flags = XTENSA_OP_PRIVILEGED,
3875 }, {
3876 .name = "rfdo",
3877 .op_flags = XTENSA_OP_ILL,
3878 }, {
3879 .name = "rfe",
3880 .translate = translate_rfe,
3881 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3882 }, {
3883 .name = "rfi",
3884 .translate = translate_rfi,
3885 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3886 }, {
3887 .name = "rfwo",
3888 .translate = translate_rfw,
3889 .par = (const uint32_t[]){true},
3890 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3891 }, {
3892 .name = "rfwu",
3893 .translate = translate_rfw,
3894 .par = (const uint32_t[]){false},
3895 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3896 }, {
3897 .name = "ritlb0",
3898 .translate = translate_rtlb,
3899 .par = (const uint32_t[]){false, 0},
3900 .op_flags = XTENSA_OP_PRIVILEGED,
3901 }, {
3902 .name = "ritlb1",
3903 .translate = translate_rtlb,
3904 .par = (const uint32_t[]){false, 1},
3905 .op_flags = XTENSA_OP_PRIVILEGED,
3906 }, {
3907 .name = "rptlb0",
3908 .translate = translate_rptlb0,
3909 .op_flags = XTENSA_OP_PRIVILEGED,
3910 }, {
3911 .name = "rptlb1",
3912 .translate = translate_rptlb1,
3913 .op_flags = XTENSA_OP_PRIVILEGED,
3914 }, {
3915 .name = "rotw",
3916 .translate = translate_rotw,
3917 .op_flags = XTENSA_OP_PRIVILEGED |
3918 XTENSA_OP_EXIT_TB_M1 |
3919 XTENSA_OP_SYNC_REGISTER_WINDOW,
3920 }, {
3921 .name = "rsil",
3922 .translate = translate_rsil,
3923 .op_flags =
3924 XTENSA_OP_PRIVILEGED |
3925 XTENSA_OP_EXIT_TB_0 |
3926 XTENSA_OP_CHECK_INTERRUPTS,
3927 }, {
3928 .name = "rsr.176",
3929 .translate = translate_rsr,
3930 .par = (const uint32_t[]){176},
3931 .op_flags = XTENSA_OP_PRIVILEGED,
3932 }, {
3933 .name = "rsr.208",
3934 .translate = translate_rsr,
3935 .par = (const uint32_t[]){208},
3936 .op_flags = XTENSA_OP_PRIVILEGED,
3937 }, {
3938 .name = "rsr.acchi",
3939 .translate = translate_rsr,
3940 .test_exceptions = test_exceptions_sr,
3941 .par = (const uint32_t[]){
3942 ACCHI,
3943 XTENSA_OPTION_MAC16,
3944 },
3945 }, {
3946 .name = "rsr.acclo",
3947 .translate = translate_rsr,
3948 .test_exceptions = test_exceptions_sr,
3949 .par = (const uint32_t[]){
3950 ACCLO,
3951 XTENSA_OPTION_MAC16,
3952 },
3953 }, {
3954 .name = "rsr.atomctl",
3955 .translate = translate_rsr,
3956 .test_exceptions = test_exceptions_sr,
3957 .par = (const uint32_t[]){
3958 ATOMCTL,
3959 XTENSA_OPTION_ATOMCTL,
3960 },
3961 .op_flags = XTENSA_OP_PRIVILEGED,
3962 }, {
3963 .name = "rsr.br",
3964 .translate = translate_rsr,
3965 .test_exceptions = test_exceptions_sr,
3966 .par = (const uint32_t[]){
3967 BR,
3968 XTENSA_OPTION_BOOLEAN,
3969 },
3970 }, {
3971 .name = "rsr.cacheadrdis",
3972 .translate = translate_rsr,
3973 .test_exceptions = test_exceptions_sr,
3974 .par = (const uint32_t[]){
3975 CACHEADRDIS,
3976 XTENSA_OPTION_MPU,
3977 },
3978 .op_flags = XTENSA_OP_PRIVILEGED,
3979 }, {
3980 .name = "rsr.cacheattr",
3981 .translate = translate_rsr,
3982 .test_exceptions = test_exceptions_sr,
3983 .par = (const uint32_t[]){
3984 CACHEATTR,
3985 XTENSA_OPTION_CACHEATTR,
3986 },
3987 .op_flags = XTENSA_OP_PRIVILEGED,
3988 }, {
3989 .name = "rsr.ccompare0",
3990 .translate = translate_rsr,
3991 .test_exceptions = test_exceptions_ccompare,
3992 .par = (const uint32_t[]){
3993 CCOMPARE,
3994 XTENSA_OPTION_TIMER_INTERRUPT,
3995 },
3996 .op_flags = XTENSA_OP_PRIVILEGED,
3997 }, {
3998 .name = "rsr.ccompare1",
3999 .translate = translate_rsr,
4000 .test_exceptions = test_exceptions_ccompare,
4001 .par = (const uint32_t[]){
4002 CCOMPARE + 1,
4003 XTENSA_OPTION_TIMER_INTERRUPT,
4004 },
4005 .op_flags = XTENSA_OP_PRIVILEGED,
4006 }, {
4007 .name = "rsr.ccompare2",
4008 .translate = translate_rsr,
4009 .test_exceptions = test_exceptions_ccompare,
4010 .par = (const uint32_t[]){
4011 CCOMPARE + 2,
4012 XTENSA_OPTION_TIMER_INTERRUPT,
4013 },
4014 .op_flags = XTENSA_OP_PRIVILEGED,
4015 }, {
4016 .name = "rsr.ccount",
4017 .translate = translate_rsr_ccount,
4018 .test_exceptions = test_exceptions_sr,
4019 .par = (const uint32_t[]){
4020 CCOUNT,
4021 XTENSA_OPTION_TIMER_INTERRUPT,
4022 },
4023 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4024 }, {
4025 .name = "rsr.configid0",
4026 .translate = translate_rsr,
4027 .par = (const uint32_t[]){CONFIGID0},
4028 .op_flags = XTENSA_OP_PRIVILEGED,
4029 }, {
4030 .name = "rsr.configid1",
4031 .translate = translate_rsr,
4032 .par = (const uint32_t[]){CONFIGID1},
4033 .op_flags = XTENSA_OP_PRIVILEGED,
4034 }, {
4035 .name = "rsr.cpenable",
4036 .translate = translate_rsr,
4037 .test_exceptions = test_exceptions_sr,
4038 .par = (const uint32_t[]){
4039 CPENABLE,
4040 XTENSA_OPTION_COPROCESSOR,
4041 },
4042 .op_flags = XTENSA_OP_PRIVILEGED,
4043 }, {
4044 .name = "rsr.dbreaka0",
4045 .translate = translate_rsr,
4046 .test_exceptions = test_exceptions_dbreak,
4047 .par = (const uint32_t[]){
4048 DBREAKA,
4049 XTENSA_OPTION_DEBUG,
4050 },
4051 .op_flags = XTENSA_OP_PRIVILEGED,
4052 }, {
4053 .name = "rsr.dbreaka1",
4054 .translate = translate_rsr,
4055 .test_exceptions = test_exceptions_dbreak,
4056 .par = (const uint32_t[]){
4057 DBREAKA + 1,
4058 XTENSA_OPTION_DEBUG,
4059 },
4060 .op_flags = XTENSA_OP_PRIVILEGED,
4061 }, {
4062 .name = "rsr.dbreakc0",
4063 .translate = translate_rsr,
4064 .test_exceptions = test_exceptions_dbreak,
4065 .par = (const uint32_t[]){
4066 DBREAKC,
4067 XTENSA_OPTION_DEBUG,
4068 },
4069 .op_flags = XTENSA_OP_PRIVILEGED,
4070 }, {
4071 .name = "rsr.dbreakc1",
4072 .translate = translate_rsr,
4073 .test_exceptions = test_exceptions_dbreak,
4074 .par = (const uint32_t[]){
4075 DBREAKC + 1,
4076 XTENSA_OPTION_DEBUG,
4077 },
4078 .op_flags = XTENSA_OP_PRIVILEGED,
4079 }, {
4080 .name = "rsr.ddr",
4081 .translate = translate_rsr,
4082 .test_exceptions = test_exceptions_sr,
4083 .par = (const uint32_t[]){
4084 DDR,
4085 XTENSA_OPTION_DEBUG,
4086 },
4087 .op_flags = XTENSA_OP_PRIVILEGED,
4088 }, {
4089 .name = "rsr.debugcause",
4090 .translate = translate_rsr,
4091 .test_exceptions = test_exceptions_sr,
4092 .par = (const uint32_t[]){
4093 DEBUGCAUSE,
4094 XTENSA_OPTION_DEBUG,
4095 },
4096 .op_flags = XTENSA_OP_PRIVILEGED,
4097 }, {
4098 .name = "rsr.depc",
4099 .translate = translate_rsr,
4100 .test_exceptions = test_exceptions_sr,
4101 .par = (const uint32_t[]){
4102 DEPC,
4103 XTENSA_OPTION_EXCEPTION,
4104 },
4105 .op_flags = XTENSA_OP_PRIVILEGED,
4106 }, {
4107 .name = "rsr.dtlbcfg",
4108 .translate = translate_rsr,
4109 .test_exceptions = test_exceptions_sr,
4110 .par = (const uint32_t[]){
4111 DTLBCFG,
4112 XTENSA_OPTION_MMU,
4113 },
4114 .op_flags = XTENSA_OP_PRIVILEGED,
4115 }, {
4116 .name = "rsr.epc1",
4117 .translate = translate_rsr,
4118 .test_exceptions = test_exceptions_sr,
4119 .par = (const uint32_t[]){
4120 EPC1,
4121 XTENSA_OPTION_EXCEPTION,
4122 },
4123 .op_flags = XTENSA_OP_PRIVILEGED,
4124 }, {
4125 .name = "rsr.epc2",
4126 .translate = translate_rsr,
4127 .test_exceptions = test_exceptions_hpi,
4128 .par = (const uint32_t[]){
4129 EPC1 + 1,
4130 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4131 },
4132 .op_flags = XTENSA_OP_PRIVILEGED,
4133 }, {
4134 .name = "rsr.epc3",
4135 .translate = translate_rsr,
4136 .test_exceptions = test_exceptions_hpi,
4137 .par = (const uint32_t[]){
4138 EPC1 + 2,
4139 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4140 },
4141 .op_flags = XTENSA_OP_PRIVILEGED,
4142 }, {
4143 .name = "rsr.epc4",
4144 .translate = translate_rsr,
4145 .test_exceptions = test_exceptions_hpi,
4146 .par = (const uint32_t[]){
4147 EPC1 + 3,
4148 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4149 },
4150 .op_flags = XTENSA_OP_PRIVILEGED,
4151 }, {
4152 .name = "rsr.epc5",
4153 .translate = translate_rsr,
4154 .test_exceptions = test_exceptions_hpi,
4155 .par = (const uint32_t[]){
4156 EPC1 + 4,
4157 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4158 },
4159 .op_flags = XTENSA_OP_PRIVILEGED,
4160 }, {
4161 .name = "rsr.epc6",
4162 .translate = translate_rsr,
4163 .test_exceptions = test_exceptions_hpi,
4164 .par = (const uint32_t[]){
4165 EPC1 + 5,
4166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4167 },
4168 .op_flags = XTENSA_OP_PRIVILEGED,
4169 }, {
4170 .name = "rsr.epc7",
4171 .translate = translate_rsr,
4172 .test_exceptions = test_exceptions_hpi,
4173 .par = (const uint32_t[]){
4174 EPC1 + 6,
4175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4176 },
4177 .op_flags = XTENSA_OP_PRIVILEGED,
4178 }, {
4179 .name = "rsr.eps2",
4180 .translate = translate_rsr,
4181 .test_exceptions = test_exceptions_hpi,
4182 .par = (const uint32_t[]){
4183 EPS2,
4184 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4185 },
4186 .op_flags = XTENSA_OP_PRIVILEGED,
4187 }, {
4188 .name = "rsr.eps3",
4189 .translate = translate_rsr,
4190 .test_exceptions = test_exceptions_hpi,
4191 .par = (const uint32_t[]){
4192 EPS2 + 1,
4193 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4194 },
4195 .op_flags = XTENSA_OP_PRIVILEGED,
4196 }, {
4197 .name = "rsr.eps4",
4198 .translate = translate_rsr,
4199 .test_exceptions = test_exceptions_hpi,
4200 .par = (const uint32_t[]){
4201 EPS2 + 2,
4202 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4203 },
4204 .op_flags = XTENSA_OP_PRIVILEGED,
4205 }, {
4206 .name = "rsr.eps5",
4207 .translate = translate_rsr,
4208 .test_exceptions = test_exceptions_hpi,
4209 .par = (const uint32_t[]){
4210 EPS2 + 3,
4211 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4212 },
4213 .op_flags = XTENSA_OP_PRIVILEGED,
4214 }, {
4215 .name = "rsr.eps6",
4216 .translate = translate_rsr,
4217 .test_exceptions = test_exceptions_hpi,
4218 .par = (const uint32_t[]){
4219 EPS2 + 4,
4220 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4221 },
4222 .op_flags = XTENSA_OP_PRIVILEGED,
4223 }, {
4224 .name = "rsr.eps7",
4225 .translate = translate_rsr,
4226 .test_exceptions = test_exceptions_hpi,
4227 .par = (const uint32_t[]){
4228 EPS2 + 5,
4229 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4230 },
4231 .op_flags = XTENSA_OP_PRIVILEGED,
4232 }, {
4233 .name = "rsr.eraccess",
4234 .translate = translate_rsr,
4235 .par = (const uint32_t[]){ERACCESS},
4236 .op_flags = XTENSA_OP_PRIVILEGED,
4237 }, {
4238 .name = "rsr.exccause",
4239 .translate = translate_rsr,
4240 .test_exceptions = test_exceptions_sr,
4241 .par = (const uint32_t[]){
4242 EXCCAUSE,
4243 XTENSA_OPTION_EXCEPTION,
4244 },
4245 .op_flags = XTENSA_OP_PRIVILEGED,
4246 }, {
4247 .name = "rsr.excsave1",
4248 .translate = translate_rsr,
4249 .test_exceptions = test_exceptions_sr,
4250 .par = (const uint32_t[]){
4251 EXCSAVE1,
4252 XTENSA_OPTION_EXCEPTION,
4253 },
4254 .op_flags = XTENSA_OP_PRIVILEGED,
4255 }, {
4256 .name = "rsr.excsave2",
4257 .translate = translate_rsr,
4258 .test_exceptions = test_exceptions_hpi,
4259 .par = (const uint32_t[]){
4260 EXCSAVE1 + 1,
4261 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4262 },
4263 .op_flags = XTENSA_OP_PRIVILEGED,
4264 }, {
4265 .name = "rsr.excsave3",
4266 .translate = translate_rsr,
4267 .test_exceptions = test_exceptions_hpi,
4268 .par = (const uint32_t[]){
4269 EXCSAVE1 + 2,
4270 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4271 },
4272 .op_flags = XTENSA_OP_PRIVILEGED,
4273 }, {
4274 .name = "rsr.excsave4",
4275 .translate = translate_rsr,
4276 .test_exceptions = test_exceptions_hpi,
4277 .par = (const uint32_t[]){
4278 EXCSAVE1 + 3,
4279 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4280 },
4281 .op_flags = XTENSA_OP_PRIVILEGED,
4282 }, {
4283 .name = "rsr.excsave5",
4284 .translate = translate_rsr,
4285 .test_exceptions = test_exceptions_hpi,
4286 .par = (const uint32_t[]){
4287 EXCSAVE1 + 4,
4288 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4289 },
4290 .op_flags = XTENSA_OP_PRIVILEGED,
4291 }, {
4292 .name = "rsr.excsave6",
4293 .translate = translate_rsr,
4294 .test_exceptions = test_exceptions_hpi,
4295 .par = (const uint32_t[]){
4296 EXCSAVE1 + 5,
4297 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4298 },
4299 .op_flags = XTENSA_OP_PRIVILEGED,
4300 }, {
4301 .name = "rsr.excsave7",
4302 .translate = translate_rsr,
4303 .test_exceptions = test_exceptions_hpi,
4304 .par = (const uint32_t[]){
4305 EXCSAVE1 + 6,
4306 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4307 },
4308 .op_flags = XTENSA_OP_PRIVILEGED,
4309 }, {
4310 .name = "rsr.excvaddr",
4311 .translate = translate_rsr,
4312 .test_exceptions = test_exceptions_sr,
4313 .par = (const uint32_t[]){
4314 EXCVADDR,
4315 XTENSA_OPTION_EXCEPTION,
4316 },
4317 .op_flags = XTENSA_OP_PRIVILEGED,
4318 }, {
4319 .name = "rsr.ibreaka0",
4320 .translate = translate_rsr,
4321 .test_exceptions = test_exceptions_ibreak,
4322 .par = (const uint32_t[]){
4323 IBREAKA,
4324 XTENSA_OPTION_DEBUG,
4325 },
4326 .op_flags = XTENSA_OP_PRIVILEGED,
4327 }, {
4328 .name = "rsr.ibreaka1",
4329 .translate = translate_rsr,
4330 .test_exceptions = test_exceptions_ibreak,
4331 .par = (const uint32_t[]){
4332 IBREAKA + 1,
4333 XTENSA_OPTION_DEBUG,
4334 },
4335 .op_flags = XTENSA_OP_PRIVILEGED,
4336 }, {
4337 .name = "rsr.ibreakenable",
4338 .translate = translate_rsr,
4339 .test_exceptions = test_exceptions_sr,
4340 .par = (const uint32_t[]){
4341 IBREAKENABLE,
4342 XTENSA_OPTION_DEBUG,
4343 },
4344 .op_flags = XTENSA_OP_PRIVILEGED,
4345 }, {
4346 .name = "rsr.icount",
4347 .translate = translate_rsr,
4348 .test_exceptions = test_exceptions_sr,
4349 .par = (const uint32_t[]){
4350 ICOUNT,
4351 XTENSA_OPTION_DEBUG,
4352 },
4353 .op_flags = XTENSA_OP_PRIVILEGED,
4354 }, {
4355 .name = "rsr.icountlevel",
4356 .translate = translate_rsr,
4357 .test_exceptions = test_exceptions_sr,
4358 .par = (const uint32_t[]){
4359 ICOUNTLEVEL,
4360 XTENSA_OPTION_DEBUG,
4361 },
4362 .op_flags = XTENSA_OP_PRIVILEGED,
4363 }, {
4364 .name = "rsr.intclear",
4365 .translate = translate_rsr,
4366 .test_exceptions = test_exceptions_sr,
4367 .par = (const uint32_t[]){
4368 INTCLEAR,
4369 XTENSA_OPTION_INTERRUPT,
4370 },
4371 .op_flags = XTENSA_OP_PRIVILEGED,
4372 }, {
4373 .name = "rsr.intenable",
4374 .translate = translate_rsr,
4375 .test_exceptions = test_exceptions_sr,
4376 .par = (const uint32_t[]){
4377 INTENABLE,
4378 XTENSA_OPTION_INTERRUPT,
4379 },
4380 .op_flags = XTENSA_OP_PRIVILEGED,
4381 }, {
4382 .name = "rsr.interrupt",
4383 .translate = translate_rsr_ccount,
4384 .test_exceptions = test_exceptions_sr,
4385 .par = (const uint32_t[]){
4386 INTSET,
4387 XTENSA_OPTION_INTERRUPT,
4388 },
4389 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4390 }, {
4391 .name = "rsr.intset",
4392 .translate = translate_rsr_ccount,
4393 .test_exceptions = test_exceptions_sr,
4394 .par = (const uint32_t[]){
4395 INTSET,
4396 XTENSA_OPTION_INTERRUPT,
4397 },
4398 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4399 }, {
4400 .name = "rsr.itlbcfg",
4401 .translate = translate_rsr,
4402 .test_exceptions = test_exceptions_sr,
4403 .par = (const uint32_t[]){
4404 ITLBCFG,
4405 XTENSA_OPTION_MMU,
4406 },
4407 .op_flags = XTENSA_OP_PRIVILEGED,
4408 }, {
4409 .name = "rsr.lbeg",
4410 .translate = translate_rsr,
4411 .test_exceptions = test_exceptions_sr,
4412 .par = (const uint32_t[]){
4413 LBEG,
4414 XTENSA_OPTION_LOOP,
4415 },
4416 }, {
4417 .name = "rsr.lcount",
4418 .translate = translate_rsr,
4419 .test_exceptions = test_exceptions_sr,
4420 .par = (const uint32_t[]){
4421 LCOUNT,
4422 XTENSA_OPTION_LOOP,
4423 },
4424 }, {
4425 .name = "rsr.lend",
4426 .translate = translate_rsr,
4427 .test_exceptions = test_exceptions_sr,
4428 .par = (const uint32_t[]){
4429 LEND,
4430 XTENSA_OPTION_LOOP,
4431 },
4432 }, {
4433 .name = "rsr.litbase",
4434 .translate = translate_rsr,
4435 .test_exceptions = test_exceptions_sr,
4436 .par = (const uint32_t[]){
4437 LITBASE,
4438 XTENSA_OPTION_EXTENDED_L32R,
4439 },
4440 }, {
4441 .name = "rsr.m0",
4442 .translate = translate_rsr,
4443 .test_exceptions = test_exceptions_sr,
4444 .par = (const uint32_t[]){
4445 MR,
4446 XTENSA_OPTION_MAC16,
4447 },
4448 }, {
4449 .name = "rsr.m1",
4450 .translate = translate_rsr,
4451 .test_exceptions = test_exceptions_sr,
4452 .par = (const uint32_t[]){
4453 MR + 1,
4454 XTENSA_OPTION_MAC16,
4455 },
4456 }, {
4457 .name = "rsr.m2",
4458 .translate = translate_rsr,
4459 .test_exceptions = test_exceptions_sr,
4460 .par = (const uint32_t[]){
4461 MR + 2,
4462 XTENSA_OPTION_MAC16,
4463 },
4464 }, {
4465 .name = "rsr.m3",
4466 .translate = translate_rsr,
4467 .test_exceptions = test_exceptions_sr,
4468 .par = (const uint32_t[]){
4469 MR + 3,
4470 XTENSA_OPTION_MAC16,
4471 },
4472 }, {
4473 .name = "rsr.memctl",
4474 .translate = translate_rsr,
4475 .par = (const uint32_t[]){MEMCTL},
4476 .op_flags = XTENSA_OP_PRIVILEGED,
4477 }, {
4478 .name = "rsr.mecr",
4479 .translate = translate_rsr,
4480 .test_exceptions = test_exceptions_sr,
4481 .par = (const uint32_t[]){
4482 MECR,
4483 XTENSA_OPTION_MEMORY_ECC_PARITY,
4484 },
4485 .op_flags = XTENSA_OP_PRIVILEGED,
4486 }, {
4487 .name = "rsr.mepc",
4488 .translate = translate_rsr,
4489 .test_exceptions = test_exceptions_sr,
4490 .par = (const uint32_t[]){
4491 MEPC,
4492 XTENSA_OPTION_MEMORY_ECC_PARITY,
4493 },
4494 .op_flags = XTENSA_OP_PRIVILEGED,
4495 }, {
4496 .name = "rsr.meps",
4497 .translate = translate_rsr,
4498 .test_exceptions = test_exceptions_sr,
4499 .par = (const uint32_t[]){
4500 MEPS,
4501 XTENSA_OPTION_MEMORY_ECC_PARITY,
4502 },
4503 .op_flags = XTENSA_OP_PRIVILEGED,
4504 }, {
4505 .name = "rsr.mesave",
4506 .translate = translate_rsr,
4507 .test_exceptions = test_exceptions_sr,
4508 .par = (const uint32_t[]){
4509 MESAVE,
4510 XTENSA_OPTION_MEMORY_ECC_PARITY,
4511 },
4512 .op_flags = XTENSA_OP_PRIVILEGED,
4513 }, {
4514 .name = "rsr.mesr",
4515 .translate = translate_rsr,
4516 .test_exceptions = test_exceptions_sr,
4517 .par = (const uint32_t[]){
4518 MESR,
4519 XTENSA_OPTION_MEMORY_ECC_PARITY,
4520 },
4521 .op_flags = XTENSA_OP_PRIVILEGED,
4522 }, {
4523 .name = "rsr.mevaddr",
4524 .translate = translate_rsr,
4525 .test_exceptions = test_exceptions_sr,
4526 .par = (const uint32_t[]){
4527 MESR,
4528 XTENSA_OPTION_MEMORY_ECC_PARITY,
4529 },
4530 .op_flags = XTENSA_OP_PRIVILEGED,
4531 }, {
4532 .name = "rsr.misc0",
4533 .translate = translate_rsr,
4534 .test_exceptions = test_exceptions_sr,
4535 .par = (const uint32_t[]){
4536 MISC,
4537 XTENSA_OPTION_MISC_SR,
4538 },
4539 .op_flags = XTENSA_OP_PRIVILEGED,
4540 }, {
4541 .name = "rsr.misc1",
4542 .translate = translate_rsr,
4543 .test_exceptions = test_exceptions_sr,
4544 .par = (const uint32_t[]){
4545 MISC + 1,
4546 XTENSA_OPTION_MISC_SR,
4547 },
4548 .op_flags = XTENSA_OP_PRIVILEGED,
4549 }, {
4550 .name = "rsr.misc2",
4551 .translate = translate_rsr,
4552 .test_exceptions = test_exceptions_sr,
4553 .par = (const uint32_t[]){
4554 MISC + 2,
4555 XTENSA_OPTION_MISC_SR,
4556 },
4557 .op_flags = XTENSA_OP_PRIVILEGED,
4558 }, {
4559 .name = "rsr.misc3",
4560 .translate = translate_rsr,
4561 .test_exceptions = test_exceptions_sr,
4562 .par = (const uint32_t[]){
4563 MISC + 3,
4564 XTENSA_OPTION_MISC_SR,
4565 },
4566 .op_flags = XTENSA_OP_PRIVILEGED,
4567 }, {
4568 .name = "rsr.mpucfg",
4569 .translate = translate_rsr,
4570 .test_exceptions = test_exceptions_sr,
4571 .par = (const uint32_t[]){
4572 MPUCFG,
4573 XTENSA_OPTION_MPU,
4574 },
4575 .op_flags = XTENSA_OP_PRIVILEGED,
4576 }, {
4577 .name = "rsr.mpuenb",
4578 .translate = translate_rsr,
4579 .test_exceptions = test_exceptions_sr,
4580 .par = (const uint32_t[]){
4581 MPUENB,
4582 XTENSA_OPTION_MPU,
4583 },
4584 .op_flags = XTENSA_OP_PRIVILEGED,
4585 }, {
4586 .name = "rsr.prefctl",
4587 .translate = translate_rsr,
4588 .par = (const uint32_t[]){PREFCTL},
4589 }, {
4590 .name = "rsr.prid",
4591 .translate = translate_rsr,
4592 .test_exceptions = test_exceptions_sr,
4593 .par = (const uint32_t[]){
4594 PRID,
4595 XTENSA_OPTION_PROCESSOR_ID,
4596 },
4597 .op_flags = XTENSA_OP_PRIVILEGED,
4598 }, {
4599 .name = "rsr.ps",
4600 .translate = translate_rsr,
4601 .test_exceptions = test_exceptions_sr,
4602 .par = (const uint32_t[]){
4603 PS,
4604 XTENSA_OPTION_EXCEPTION,
4605 },
4606 .op_flags = XTENSA_OP_PRIVILEGED,
4607 }, {
4608 .name = "rsr.ptevaddr",
4609 .translate = translate_rsr_ptevaddr,
4610 .test_exceptions = test_exceptions_sr,
4611 .par = (const uint32_t[]){
4612 PTEVADDR,
4613 XTENSA_OPTION_MMU,
4614 },
4615 .op_flags = XTENSA_OP_PRIVILEGED,
4616 }, {
4617 .name = "rsr.rasid",
4618 .translate = translate_rsr,
4619 .test_exceptions = test_exceptions_sr,
4620 .par = (const uint32_t[]){
4621 RASID,
4622 XTENSA_OPTION_MMU,
4623 },
4624 .op_flags = XTENSA_OP_PRIVILEGED,
4625 }, {
4626 .name = "rsr.sar",
4627 .translate = translate_rsr,
4628 .par = (const uint32_t[]){SAR},
4629 }, {
4630 .name = "rsr.scompare1",
4631 .translate = translate_rsr,
4632 .test_exceptions = test_exceptions_sr,
4633 .par = (const uint32_t[]){
4634 SCOMPARE1,
4635 XTENSA_OPTION_CONDITIONAL_STORE,
4636 },
4637 }, {
4638 .name = "rsr.vecbase",
4639 .translate = translate_rsr,
4640 .test_exceptions = test_exceptions_sr,
4641 .par = (const uint32_t[]){
4642 VECBASE,
4643 XTENSA_OPTION_RELOCATABLE_VECTOR,
4644 },
4645 .op_flags = XTENSA_OP_PRIVILEGED,
4646 }, {
4647 .name = "rsr.windowbase",
4648 .translate = translate_rsr,
4649 .test_exceptions = test_exceptions_sr,
4650 .par = (const uint32_t[]){
4651 WINDOW_BASE,
4652 XTENSA_OPTION_WINDOWED_REGISTER,
4653 },
4654 .op_flags = XTENSA_OP_PRIVILEGED,
4655 }, {
4656 .name = "rsr.windowstart",
4657 .translate = translate_rsr,
4658 .test_exceptions = test_exceptions_sr,
4659 .par = (const uint32_t[]){
4660 WINDOW_START,
4661 XTENSA_OPTION_WINDOWED_REGISTER,
4662 },
4663 .op_flags = XTENSA_OP_PRIVILEGED,
4664 }, {
4665 .name = "rsync",
4666 .translate = translate_nop,
4667 }, {
4668 .name = "rur.expstate",
4669 .translate = translate_rur,
4670 .par = (const uint32_t[]){EXPSTATE},
4671 }, {
4672 .name = "rur.threadptr",
4673 .translate = translate_rur,
4674 .par = (const uint32_t[]){THREADPTR},
4675 }, {
4676 .name = "s16i",
4677 .translate = translate_ldst,
4678 .par = (const uint32_t[]){MO_TEUW, false, true},
4679 .op_flags = XTENSA_OP_STORE,
4680 }, {
4681 .name = "s32c1i",
4682 .translate = translate_s32c1i,
4683 .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE,
4684 }, {
4685 .name = "s32e",
4686 .translate = translate_s32e,
4687 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE,
4688 }, {
4689 .name = "s32ex",
4690 .translate = translate_s32ex,
4691 .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE,
4692 }, {
4693 .name = (const char * const[]) {
4694 "s32i", "s32i.n", "s32nb", NULL,
4695 },
4696 .translate = translate_ldst,
4697 .par = (const uint32_t[]){MO_TEUL, false, true},
4698 .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE,
4699 }, {
4700 .name = "s32ri",
4701 .translate = translate_ldst,
4702 .par = (const uint32_t[]){MO_TEUL | MO_ALIGN, true, true},
4703 .op_flags = XTENSA_OP_STORE,
4704 }, {
4705 .name = "s8i",
4706 .translate = translate_ldst,
4707 .par = (const uint32_t[]){MO_UB, false, true},
4708 .op_flags = XTENSA_OP_STORE,
4709 }, {
4710 .name = "salt",
4711 .translate = translate_salt,
4712 .par = (const uint32_t[]){TCG_COND_LT},
4713 }, {
4714 .name = "saltu",
4715 .translate = translate_salt,
4716 .par = (const uint32_t[]){TCG_COND_LTU},
4717 }, {
4718 .name = "setb_expstate",
4719 .translate = translate_setb_expstate,
4720 }, {
4721 .name = "sext",
4722 .translate = translate_sext,
4723 }, {
4724 .name = "simcall",
4725 .translate = translate_simcall,
4726 .test_exceptions = test_exceptions_simcall,
4727 .op_flags = XTENSA_OP_PRIVILEGED,
4728 }, {
4729 .name = "sll",
4730 .translate = translate_sll,
4731 }, {
4732 .name = "slli",
4733 .translate = translate_slli,
4734 }, {
4735 .name = "sra",
4736 .translate = translate_sra,
4737 }, {
4738 .name = "srai",
4739 .translate = translate_srai,
4740 }, {
4741 .name = "src",
4742 .translate = translate_src,
4743 }, {
4744 .name = "srl",
4745 .translate = translate_srl,
4746 }, {
4747 .name = "srli",
4748 .translate = translate_srli,
4749 }, {
4750 .name = "ssa8b",
4751 .translate = translate_ssa8b,
4752 }, {
4753 .name = "ssa8l",
4754 .translate = translate_ssa8l,
4755 }, {
4756 .name = "ssai",
4757 .translate = translate_ssai,
4758 }, {
4759 .name = "ssl",
4760 .translate = translate_ssl,
4761 }, {
4762 .name = "ssr",
4763 .translate = translate_ssr,
4764 }, {
4765 .name = "sub",
4766 .translate = translate_sub,
4767 }, {
4768 .name = "subx2",
4769 .translate = translate_subx,
4770 .par = (const uint32_t[]){1},
4771 }, {
4772 .name = "subx4",
4773 .translate = translate_subx,
4774 .par = (const uint32_t[]){2},
4775 }, {
4776 .name = "subx8",
4777 .translate = translate_subx,
4778 .par = (const uint32_t[]){3},
4779 }, {
4780 .name = "syscall",
4781 .op_flags = XTENSA_OP_SYSCALL,
4782 }, {
4783 .name = "umul.aa.hh",
4784 .translate = translate_mac16,
4785 .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0},
4786 }, {
4787 .name = "umul.aa.hl",
4788 .translate = translate_mac16,
4789 .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0},
4790 }, {
4791 .name = "umul.aa.lh",
4792 .translate = translate_mac16,
4793 .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0},
4794 }, {
4795 .name = "umul.aa.ll",
4796 .translate = translate_mac16,
4797 .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0},
4798 }, {
4799 .name = "waiti",
4800 .translate = translate_waiti,
4801 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4802 }, {
4803 .name = "wdtlb",
4804 .translate = translate_wtlb,
4805 .par = (const uint32_t[]){true},
4806 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4807 }, {
4808 .name = "wer",
4809 .translate = translate_wer,
4810 .op_flags = XTENSA_OP_PRIVILEGED,
4811 }, {
4812 .name = "witlb",
4813 .translate = translate_wtlb,
4814 .par = (const uint32_t[]){false},
4815 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4816 }, {
4817 .name = "wptlb",
4818 .translate = translate_wptlb,
4819 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4820 }, {
4821 .name = "wrmsk_expstate",
4822 .translate = translate_wrmsk_expstate,
4823 }, {
4824 .name = "wsr.176",
4825 .op_flags = XTENSA_OP_ILL,
4826 }, {
4827 .name = "wsr.208",
4828 .op_flags = XTENSA_OP_ILL,
4829 }, {
4830 .name = "wsr.acchi",
4831 .translate = translate_wsr_acchi,
4832 .test_exceptions = test_exceptions_sr,
4833 .par = (const uint32_t[]){
4834 ACCHI,
4835 XTENSA_OPTION_MAC16,
4836 },
4837 }, {
4838 .name = "wsr.acclo",
4839 .translate = translate_wsr,
4840 .test_exceptions = test_exceptions_sr,
4841 .par = (const uint32_t[]){
4842 ACCLO,
4843 XTENSA_OPTION_MAC16,
4844 },
4845 }, {
4846 .name = "wsr.atomctl",
4847 .translate = translate_wsr_mask,
4848 .test_exceptions = test_exceptions_sr,
4849 .par = (const uint32_t[]){
4850 ATOMCTL,
4851 XTENSA_OPTION_ATOMCTL,
4852 0x3f,
4853 },
4854 .op_flags = XTENSA_OP_PRIVILEGED,
4855 }, {
4856 .name = "wsr.br",
4857 .translate = translate_wsr_mask,
4858 .test_exceptions = test_exceptions_sr,
4859 .par = (const uint32_t[]){
4860 BR,
4861 XTENSA_OPTION_BOOLEAN,
4862 0xffff,
4863 },
4864 }, {
4865 .name = "wsr.cacheadrdis",
4866 .translate = translate_wsr_mask,
4867 .test_exceptions = test_exceptions_sr,
4868 .par = (const uint32_t[]){
4869 CACHEADRDIS,
4870 XTENSA_OPTION_MPU,
4871 0xff,
4872 },
4873 .op_flags = XTENSA_OP_PRIVILEGED,
4874 }, {
4875 .name = "wsr.cacheattr",
4876 .translate = translate_wsr,
4877 .test_exceptions = test_exceptions_sr,
4878 .par = (const uint32_t[]){
4879 CACHEATTR,
4880 XTENSA_OPTION_CACHEATTR,
4881 },
4882 .op_flags = XTENSA_OP_PRIVILEGED,
4883 }, {
4884 .name = "wsr.ccompare0",
4885 .translate = translate_wsr_ccompare,
4886 .test_exceptions = test_exceptions_ccompare,
4887 .par = (const uint32_t[]){
4888 CCOMPARE,
4889 XTENSA_OPTION_TIMER_INTERRUPT,
4890 },
4891 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4892 }, {
4893 .name = "wsr.ccompare1",
4894 .translate = translate_wsr_ccompare,
4895 .test_exceptions = test_exceptions_ccompare,
4896 .par = (const uint32_t[]){
4897 CCOMPARE + 1,
4898 XTENSA_OPTION_TIMER_INTERRUPT,
4899 },
4900 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4901 }, {
4902 .name = "wsr.ccompare2",
4903 .translate = translate_wsr_ccompare,
4904 .test_exceptions = test_exceptions_ccompare,
4905 .par = (const uint32_t[]){
4906 CCOMPARE + 2,
4907 XTENSA_OPTION_TIMER_INTERRUPT,
4908 },
4909 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4910 }, {
4911 .name = "wsr.ccount",
4912 .translate = translate_wsr_ccount,
4913 .test_exceptions = test_exceptions_sr,
4914 .par = (const uint32_t[]){
4915 CCOUNT,
4916 XTENSA_OPTION_TIMER_INTERRUPT,
4917 },
4918 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4919 }, {
4920 .name = "wsr.configid0",
4921 .op_flags = XTENSA_OP_ILL,
4922 }, {
4923 .name = "wsr.configid1",
4924 .op_flags = XTENSA_OP_ILL,
4925 }, {
4926 .name = "wsr.cpenable",
4927 .translate = translate_wsr_mask,
4928 .test_exceptions = test_exceptions_sr,
4929 .par = (const uint32_t[]){
4930 CPENABLE,
4931 XTENSA_OPTION_COPROCESSOR,
4932 0xff,
4933 },
4934 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4935 }, {
4936 .name = "wsr.dbreaka0",
4937 .translate = translate_wsr_dbreaka,
4938 .test_exceptions = test_exceptions_dbreak,
4939 .par = (const uint32_t[]){
4940 DBREAKA,
4941 XTENSA_OPTION_DEBUG,
4942 },
4943 .op_flags = XTENSA_OP_PRIVILEGED,
4944 }, {
4945 .name = "wsr.dbreaka1",
4946 .translate = translate_wsr_dbreaka,
4947 .test_exceptions = test_exceptions_dbreak,
4948 .par = (const uint32_t[]){
4949 DBREAKA + 1,
4950 XTENSA_OPTION_DEBUG,
4951 },
4952 .op_flags = XTENSA_OP_PRIVILEGED,
4953 }, {
4954 .name = "wsr.dbreakc0",
4955 .translate = translate_wsr_dbreakc,
4956 .test_exceptions = test_exceptions_dbreak,
4957 .par = (const uint32_t[]){
4958 DBREAKC,
4959 XTENSA_OPTION_DEBUG,
4960 },
4961 .op_flags = XTENSA_OP_PRIVILEGED,
4962 }, {
4963 .name = "wsr.dbreakc1",
4964 .translate = translate_wsr_dbreakc,
4965 .test_exceptions = test_exceptions_dbreak,
4966 .par = (const uint32_t[]){
4967 DBREAKC + 1,
4968 XTENSA_OPTION_DEBUG,
4969 },
4970 .op_flags = XTENSA_OP_PRIVILEGED,
4971 }, {
4972 .name = "wsr.ddr",
4973 .translate = translate_wsr,
4974 .test_exceptions = test_exceptions_sr,
4975 .par = (const uint32_t[]){
4976 DDR,
4977 XTENSA_OPTION_DEBUG,
4978 },
4979 .op_flags = XTENSA_OP_PRIVILEGED,
4980 }, {
4981 .name = "wsr.debugcause",
4982 .op_flags = XTENSA_OP_ILL,
4983 }, {
4984 .name = "wsr.depc",
4985 .translate = translate_wsr,
4986 .test_exceptions = test_exceptions_sr,
4987 .par = (const uint32_t[]){
4988 DEPC,
4989 XTENSA_OPTION_EXCEPTION,
4990 },
4991 .op_flags = XTENSA_OP_PRIVILEGED,
4992 }, {
4993 .name = "wsr.dtlbcfg",
4994 .translate = translate_wsr_mask,
4995 .test_exceptions = test_exceptions_sr,
4996 .par = (const uint32_t[]){
4997 DTLBCFG,
4998 XTENSA_OPTION_MMU,
4999 0x01130000,
5000 },
5001 .op_flags = XTENSA_OP_PRIVILEGED,
5002 }, {
5003 .name = "wsr.epc1",
5004 .translate = translate_wsr,
5005 .test_exceptions = test_exceptions_sr,
5006 .par = (const uint32_t[]){
5007 EPC1,
5008 XTENSA_OPTION_EXCEPTION,
5009 },
5010 .op_flags = XTENSA_OP_PRIVILEGED,
5011 }, {
5012 .name = "wsr.epc2",
5013 .translate = translate_wsr,
5014 .test_exceptions = test_exceptions_hpi,
5015 .par = (const uint32_t[]){
5016 EPC1 + 1,
5017 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5018 },
5019 .op_flags = XTENSA_OP_PRIVILEGED,
5020 }, {
5021 .name = "wsr.epc3",
5022 .translate = translate_wsr,
5023 .test_exceptions = test_exceptions_hpi,
5024 .par = (const uint32_t[]){
5025 EPC1 + 2,
5026 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5027 },
5028 .op_flags = XTENSA_OP_PRIVILEGED,
5029 }, {
5030 .name = "wsr.epc4",
5031 .translate = translate_wsr,
5032 .test_exceptions = test_exceptions_hpi,
5033 .par = (const uint32_t[]){
5034 EPC1 + 3,
5035 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5036 },
5037 .op_flags = XTENSA_OP_PRIVILEGED,
5038 }, {
5039 .name = "wsr.epc5",
5040 .translate = translate_wsr,
5041 .test_exceptions = test_exceptions_hpi,
5042 .par = (const uint32_t[]){
5043 EPC1 + 4,
5044 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5045 },
5046 .op_flags = XTENSA_OP_PRIVILEGED,
5047 }, {
5048 .name = "wsr.epc6",
5049 .translate = translate_wsr,
5050 .test_exceptions = test_exceptions_hpi,
5051 .par = (const uint32_t[]){
5052 EPC1 + 5,
5053 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5054 },
5055 .op_flags = XTENSA_OP_PRIVILEGED,
5056 }, {
5057 .name = "wsr.epc7",
5058 .translate = translate_wsr,
5059 .test_exceptions = test_exceptions_hpi,
5060 .par = (const uint32_t[]){
5061 EPC1 + 6,
5062 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5063 },
5064 .op_flags = XTENSA_OP_PRIVILEGED,
5065 }, {
5066 .name = "wsr.eps2",
5067 .translate = translate_wsr,
5068 .test_exceptions = test_exceptions_hpi,
5069 .par = (const uint32_t[]){
5070 EPS2,
5071 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5072 },
5073 .op_flags = XTENSA_OP_PRIVILEGED,
5074 }, {
5075 .name = "wsr.eps3",
5076 .translate = translate_wsr,
5077 .test_exceptions = test_exceptions_hpi,
5078 .par = (const uint32_t[]){
5079 EPS2 + 1,
5080 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5081 },
5082 .op_flags = XTENSA_OP_PRIVILEGED,
5083 }, {
5084 .name = "wsr.eps4",
5085 .translate = translate_wsr,
5086 .test_exceptions = test_exceptions_hpi,
5087 .par = (const uint32_t[]){
5088 EPS2 + 2,
5089 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5090 },
5091 .op_flags = XTENSA_OP_PRIVILEGED,
5092 }, {
5093 .name = "wsr.eps5",
5094 .translate = translate_wsr,
5095 .test_exceptions = test_exceptions_hpi,
5096 .par = (const uint32_t[]){
5097 EPS2 + 3,
5098 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5099 },
5100 .op_flags = XTENSA_OP_PRIVILEGED,
5101 }, {
5102 .name = "wsr.eps6",
5103 .translate = translate_wsr,
5104 .test_exceptions = test_exceptions_hpi,
5105 .par = (const uint32_t[]){
5106 EPS2 + 4,
5107 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5108 },
5109 .op_flags = XTENSA_OP_PRIVILEGED,
5110 }, {
5111 .name = "wsr.eps7",
5112 .translate = translate_wsr,
5113 .test_exceptions = test_exceptions_hpi,
5114 .par = (const uint32_t[]){
5115 EPS2 + 5,
5116 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5117 },
5118 .op_flags = XTENSA_OP_PRIVILEGED,
5119 }, {
5120 .name = "wsr.eraccess",
5121 .translate = translate_wsr_mask,
5122 .par = (const uint32_t[]){
5123 ERACCESS,
5124 0,
5125 0xffff,
5126 },
5127 .op_flags = XTENSA_OP_PRIVILEGED,
5128 }, {
5129 .name = "wsr.exccause",
5130 .translate = translate_wsr,
5131 .test_exceptions = test_exceptions_sr,
5132 .par = (const uint32_t[]){
5133 EXCCAUSE,
5134 XTENSA_OPTION_EXCEPTION,
5135 },
5136 .op_flags = XTENSA_OP_PRIVILEGED,
5137 }, {
5138 .name = "wsr.excsave1",
5139 .translate = translate_wsr,
5140 .test_exceptions = test_exceptions_sr,
5141 .par = (const uint32_t[]){
5142 EXCSAVE1,
5143 XTENSA_OPTION_EXCEPTION,
5144 },
5145 .op_flags = XTENSA_OP_PRIVILEGED,
5146 }, {
5147 .name = "wsr.excsave2",
5148 .translate = translate_wsr,
5149 .test_exceptions = test_exceptions_hpi,
5150 .par = (const uint32_t[]){
5151 EXCSAVE1 + 1,
5152 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5153 },
5154 .op_flags = XTENSA_OP_PRIVILEGED,
5155 }, {
5156 .name = "wsr.excsave3",
5157 .translate = translate_wsr,
5158 .test_exceptions = test_exceptions_hpi,
5159 .par = (const uint32_t[]){
5160 EXCSAVE1 + 2,
5161 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5162 },
5163 .op_flags = XTENSA_OP_PRIVILEGED,
5164 }, {
5165 .name = "wsr.excsave4",
5166 .translate = translate_wsr,
5167 .test_exceptions = test_exceptions_hpi,
5168 .par = (const uint32_t[]){
5169 EXCSAVE1 + 3,
5170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5171 },
5172 .op_flags = XTENSA_OP_PRIVILEGED,
5173 }, {
5174 .name = "wsr.excsave5",
5175 .translate = translate_wsr,
5176 .test_exceptions = test_exceptions_hpi,
5177 .par = (const uint32_t[]){
5178 EXCSAVE1 + 4,
5179 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5180 },
5181 .op_flags = XTENSA_OP_PRIVILEGED,
5182 }, {
5183 .name = "wsr.excsave6",
5184 .translate = translate_wsr,
5185 .test_exceptions = test_exceptions_hpi,
5186 .par = (const uint32_t[]){
5187 EXCSAVE1 + 5,
5188 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5189 },
5190 .op_flags = XTENSA_OP_PRIVILEGED,
5191 }, {
5192 .name = "wsr.excsave7",
5193 .translate = translate_wsr,
5194 .test_exceptions = test_exceptions_hpi,
5195 .par = (const uint32_t[]){
5196 EXCSAVE1 + 6,
5197 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5198 },
5199 .op_flags = XTENSA_OP_PRIVILEGED,
5200 }, {
5201 .name = "wsr.excvaddr",
5202 .translate = translate_wsr,
5203 .test_exceptions = test_exceptions_sr,
5204 .par = (const uint32_t[]){
5205 EXCVADDR,
5206 XTENSA_OPTION_EXCEPTION,
5207 },
5208 .op_flags = XTENSA_OP_PRIVILEGED,
5209 }, {
5210 .name = "wsr.ibreaka0",
5211 .translate = translate_wsr_ibreaka,
5212 .test_exceptions = test_exceptions_ibreak,
5213 .par = (const uint32_t[]){
5214 IBREAKA,
5215 XTENSA_OPTION_DEBUG,
5216 },
5217 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5218 }, {
5219 .name = "wsr.ibreaka1",
5220 .translate = translate_wsr_ibreaka,
5221 .test_exceptions = test_exceptions_ibreak,
5222 .par = (const uint32_t[]){
5223 IBREAKA + 1,
5224 XTENSA_OPTION_DEBUG,
5225 },
5226 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5227 }, {
5228 .name = "wsr.ibreakenable",
5229 .translate = translate_wsr_ibreakenable,
5230 .test_exceptions = test_exceptions_sr,
5231 .par = (const uint32_t[]){
5232 IBREAKENABLE,
5233 XTENSA_OPTION_DEBUG,
5234 },
5235 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5236 }, {
5237 .name = "wsr.icount",
5238 .translate = translate_wsr_icount,
5239 .test_exceptions = test_exceptions_sr,
5240 .par = (const uint32_t[]){
5241 ICOUNT,
5242 XTENSA_OPTION_DEBUG,
5243 },
5244 .op_flags = XTENSA_OP_PRIVILEGED,
5245 }, {
5246 .name = "wsr.icountlevel",
5247 .translate = translate_wsr_mask,
5248 .test_exceptions = test_exceptions_sr,
5249 .par = (const uint32_t[]){
5250 ICOUNTLEVEL,
5251 XTENSA_OPTION_DEBUG,
5252 0xf,
5253 },
5254 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5255 }, {
5256 .name = "wsr.intclear",
5257 .translate = translate_wsr_intclear,
5258 .test_exceptions = test_exceptions_sr,
5259 .par = (const uint32_t[]){
5260 INTCLEAR,
5261 XTENSA_OPTION_INTERRUPT,
5262 },
5263 .op_flags =
5264 XTENSA_OP_PRIVILEGED |
5265 XTENSA_OP_EXIT_TB_0 |
5266 XTENSA_OP_CHECK_INTERRUPTS,
5267 }, {
5268 .name = "wsr.intenable",
5269 .translate = translate_wsr,
5270 .test_exceptions = test_exceptions_sr,
5271 .par = (const uint32_t[]){
5272 INTENABLE,
5273 XTENSA_OPTION_INTERRUPT,
5274 },
5275 .op_flags =
5276 XTENSA_OP_PRIVILEGED |
5277 XTENSA_OP_EXIT_TB_0 |
5278 XTENSA_OP_CHECK_INTERRUPTS,
5279 }, {
5280 .name = "wsr.interrupt",
5281 .translate = translate_wsr,
5282 .test_exceptions = test_exceptions_sr,
5283 .par = (const uint32_t[]){
5284 INTSET,
5285 XTENSA_OPTION_INTERRUPT,
5286 },
5287 .op_flags =
5288 XTENSA_OP_PRIVILEGED |
5289 XTENSA_OP_EXIT_TB_0 |
5290 XTENSA_OP_CHECK_INTERRUPTS,
5291 }, {
5292 .name = "wsr.intset",
5293 .translate = translate_wsr_intset,
5294 .test_exceptions = test_exceptions_sr,
5295 .par = (const uint32_t[]){
5296 INTSET,
5297 XTENSA_OPTION_INTERRUPT,
5298 },
5299 .op_flags =
5300 XTENSA_OP_PRIVILEGED |
5301 XTENSA_OP_EXIT_TB_0 |
5302 XTENSA_OP_CHECK_INTERRUPTS,
5303 }, {
5304 .name = "wsr.itlbcfg",
5305 .translate = translate_wsr_mask,
5306 .test_exceptions = test_exceptions_sr,
5307 .par = (const uint32_t[]){
5308 ITLBCFG,
5309 XTENSA_OPTION_MMU,
5310 0x01130000,
5311 },
5312 .op_flags = XTENSA_OP_PRIVILEGED,
5313 }, {
5314 .name = "wsr.lbeg",
5315 .translate = translate_wsr,
5316 .test_exceptions = test_exceptions_sr,
5317 .par = (const uint32_t[]){
5318 LBEG,
5319 XTENSA_OPTION_LOOP,
5320 },
5321 .op_flags = XTENSA_OP_EXIT_TB_M1,
5322 }, {
5323 .name = "wsr.lcount",
5324 .translate = translate_wsr,
5325 .test_exceptions = test_exceptions_sr,
5326 .par = (const uint32_t[]){
5327 LCOUNT,
5328 XTENSA_OPTION_LOOP,
5329 },
5330 }, {
5331 .name = "wsr.lend",
5332 .translate = translate_wsr,
5333 .test_exceptions = test_exceptions_sr,
5334 .par = (const uint32_t[]){
5335 LEND,
5336 XTENSA_OPTION_LOOP,
5337 },
5338 .op_flags = XTENSA_OP_EXIT_TB_M1,
5339 }, {
5340 .name = "wsr.litbase",
5341 .translate = translate_wsr_mask,
5342 .test_exceptions = test_exceptions_sr,
5343 .par = (const uint32_t[]){
5344 LITBASE,
5345 XTENSA_OPTION_EXTENDED_L32R,
5346 0xfffff001,
5347 },
5348 .op_flags = XTENSA_OP_EXIT_TB_M1,
5349 }, {
5350 .name = "wsr.m0",
5351 .translate = translate_wsr,
5352 .test_exceptions = test_exceptions_sr,
5353 .par = (const uint32_t[]){
5354 MR,
5355 XTENSA_OPTION_MAC16,
5356 },
5357 }, {
5358 .name = "wsr.m1",
5359 .translate = translate_wsr,
5360 .test_exceptions = test_exceptions_sr,
5361 .par = (const uint32_t[]){
5362 MR + 1,
5363 XTENSA_OPTION_MAC16,
5364 },
5365 }, {
5366 .name = "wsr.m2",
5367 .translate = translate_wsr,
5368 .test_exceptions = test_exceptions_sr,
5369 .par = (const uint32_t[]){
5370 MR + 2,
5371 XTENSA_OPTION_MAC16,
5372 },
5373 }, {
5374 .name = "wsr.m3",
5375 .translate = translate_wsr,
5376 .test_exceptions = test_exceptions_sr,
5377 .par = (const uint32_t[]){
5378 MR + 3,
5379 XTENSA_OPTION_MAC16,
5380 },
5381 }, {
5382 .name = "wsr.memctl",
5383 .translate = translate_wsr_memctl,
5384 .par = (const uint32_t[]){MEMCTL},
5385 .op_flags = XTENSA_OP_PRIVILEGED,
5386 }, {
5387 .name = "wsr.mecr",
5388 .translate = translate_wsr,
5389 .test_exceptions = test_exceptions_sr,
5390 .par = (const uint32_t[]){
5391 MECR,
5392 XTENSA_OPTION_MEMORY_ECC_PARITY,
5393 },
5394 .op_flags = XTENSA_OP_PRIVILEGED,
5395 }, {
5396 .name = "wsr.mepc",
5397 .translate = translate_wsr,
5398 .test_exceptions = test_exceptions_sr,
5399 .par = (const uint32_t[]){
5400 MEPC,
5401 XTENSA_OPTION_MEMORY_ECC_PARITY,
5402 },
5403 .op_flags = XTENSA_OP_PRIVILEGED,
5404 }, {
5405 .name = "wsr.meps",
5406 .translate = translate_wsr,
5407 .test_exceptions = test_exceptions_sr,
5408 .par = (const uint32_t[]){
5409 MEPS,
5410 XTENSA_OPTION_MEMORY_ECC_PARITY,
5411 },
5412 .op_flags = XTENSA_OP_PRIVILEGED,
5413 }, {
5414 .name = "wsr.mesave",
5415 .translate = translate_wsr,
5416 .test_exceptions = test_exceptions_sr,
5417 .par = (const uint32_t[]){
5418 MESAVE,
5419 XTENSA_OPTION_MEMORY_ECC_PARITY,
5420 },
5421 .op_flags = XTENSA_OP_PRIVILEGED,
5422 }, {
5423 .name = "wsr.mesr",
5424 .translate = translate_wsr,
5425 .test_exceptions = test_exceptions_sr,
5426 .par = (const uint32_t[]){
5427 MESR,
5428 XTENSA_OPTION_MEMORY_ECC_PARITY,
5429 },
5430 .op_flags = XTENSA_OP_PRIVILEGED,
5431 }, {
5432 .name = "wsr.mevaddr",
5433 .translate = translate_wsr,
5434 .test_exceptions = test_exceptions_sr,
5435 .par = (const uint32_t[]){
5436 MESR,
5437 XTENSA_OPTION_MEMORY_ECC_PARITY,
5438 },
5439 .op_flags = XTENSA_OP_PRIVILEGED,
5440 }, {
5441 .name = "wsr.misc0",
5442 .translate = translate_wsr,
5443 .test_exceptions = test_exceptions_sr,
5444 .par = (const uint32_t[]){
5445 MISC,
5446 XTENSA_OPTION_MISC_SR,
5447 },
5448 .op_flags = XTENSA_OP_PRIVILEGED,
5449 }, {
5450 .name = "wsr.misc1",
5451 .translate = translate_wsr,
5452 .test_exceptions = test_exceptions_sr,
5453 .par = (const uint32_t[]){
5454 MISC + 1,
5455 XTENSA_OPTION_MISC_SR,
5456 },
5457 .op_flags = XTENSA_OP_PRIVILEGED,
5458 }, {
5459 .name = "wsr.misc2",
5460 .translate = translate_wsr,
5461 .test_exceptions = test_exceptions_sr,
5462 .par = (const uint32_t[]){
5463 MISC + 2,
5464 XTENSA_OPTION_MISC_SR,
5465 },
5466 .op_flags = XTENSA_OP_PRIVILEGED,
5467 }, {
5468 .name = "wsr.misc3",
5469 .translate = translate_wsr,
5470 .test_exceptions = test_exceptions_sr,
5471 .par = (const uint32_t[]){
5472 MISC + 3,
5473 XTENSA_OPTION_MISC_SR,
5474 },
5475 .op_flags = XTENSA_OP_PRIVILEGED,
5476 }, {
5477 .name = "wsr.mmid",
5478 .translate = translate_wsr,
5479 .test_exceptions = test_exceptions_sr,
5480 .par = (const uint32_t[]){
5481 MMID,
5482 XTENSA_OPTION_TRACE_PORT,
5483 },
5484 .op_flags = XTENSA_OP_PRIVILEGED,
5485 }, {
5486 .name = "wsr.mpuenb",
5487 .translate = translate_wsr_mpuenb,
5488 .test_exceptions = test_exceptions_sr,
5489 .par = (const uint32_t[]){
5490 MPUENB,
5491 XTENSA_OPTION_MPU,
5492 },
5493 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5494 }, {
5495 .name = "wsr.prefctl",
5496 .translate = translate_wsr,
5497 .par = (const uint32_t[]){PREFCTL},
5498 }, {
5499 .name = "wsr.prid",
5500 .op_flags = XTENSA_OP_ILL,
5501 }, {
5502 .name = "wsr.ps",
5503 .translate = translate_wsr_ps,
5504 .test_exceptions = test_exceptions_sr,
5505 .par = (const uint32_t[]){
5506 PS,
5507 XTENSA_OPTION_EXCEPTION,
5508 },
5509 .op_flags =
5510 XTENSA_OP_PRIVILEGED |
5511 XTENSA_OP_EXIT_TB_M1 |
5512 XTENSA_OP_CHECK_INTERRUPTS,
5513 }, {
5514 .name = "wsr.ptevaddr",
5515 .translate = translate_wsr_mask,
5516 .test_exceptions = test_exceptions_sr,
5517 .par = (const uint32_t[]){
5518 PTEVADDR,
5519 XTENSA_OPTION_MMU,
5520 0xffc00000,
5521 },
5522 .op_flags = XTENSA_OP_PRIVILEGED,
5523 }, {
5524 .name = "wsr.rasid",
5525 .translate = translate_wsr_rasid,
5526 .test_exceptions = test_exceptions_sr,
5527 .par = (const uint32_t[]){
5528 RASID,
5529 XTENSA_OPTION_MMU,
5530 },
5531 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5532 }, {
5533 .name = "wsr.sar",
5534 .translate = translate_wsr_sar,
5535 .par = (const uint32_t[]){SAR},
5536 }, {
5537 .name = "wsr.scompare1",
5538 .translate = translate_wsr,
5539 .test_exceptions = test_exceptions_sr,
5540 .par = (const uint32_t[]){
5541 SCOMPARE1,
5542 XTENSA_OPTION_CONDITIONAL_STORE,
5543 },
5544 }, {
5545 .name = "wsr.vecbase",
5546 .translate = translate_wsr,
5547 .test_exceptions = test_exceptions_sr,
5548 .par = (const uint32_t[]){
5549 VECBASE,
5550 XTENSA_OPTION_RELOCATABLE_VECTOR,
5551 },
5552 .op_flags = XTENSA_OP_PRIVILEGED,
5553 }, {
5554 .name = "wsr.windowbase",
5555 .translate = translate_wsr_windowbase,
5556 .test_exceptions = test_exceptions_sr,
5557 .par = (const uint32_t[]){
5558 WINDOW_BASE,
5559 XTENSA_OPTION_WINDOWED_REGISTER,
5560 },
5561 .op_flags = XTENSA_OP_PRIVILEGED |
5562 XTENSA_OP_EXIT_TB_M1 |
5563 XTENSA_OP_SYNC_REGISTER_WINDOW,
5564 }, {
5565 .name = "wsr.windowstart",
5566 .translate = translate_wsr_windowstart,
5567 .test_exceptions = test_exceptions_sr,
5568 .par = (const uint32_t[]){
5569 WINDOW_START,
5570 XTENSA_OPTION_WINDOWED_REGISTER,
5571 },
5572 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5573 }, {
5574 .name = "wur.expstate",
5575 .translate = translate_wur,
5576 .par = (const uint32_t[]){EXPSTATE},
5577 }, {
5578 .name = "wur.threadptr",
5579 .translate = translate_wur,
5580 .par = (const uint32_t[]){THREADPTR},
5581 }, {
5582 .name = "xor",
5583 .translate = translate_xor,
5584 }, {
5585 .name = "xorb",
5586 .translate = translate_boolean,
5587 .par = (const uint32_t[]){BOOLEAN_XOR},
5588 }, {
5589 .name = "xsr.176",
5590 .op_flags = XTENSA_OP_ILL,
5591 }, {
5592 .name = "xsr.208",
5593 .op_flags = XTENSA_OP_ILL,
5594 }, {
5595 .name = "xsr.acchi",
5596 .translate = translate_xsr_acchi,
5597 .test_exceptions = test_exceptions_sr,
5598 .par = (const uint32_t[]){
5599 ACCHI,
5600 XTENSA_OPTION_MAC16,
5601 },
5602 }, {
5603 .name = "xsr.acclo",
5604 .translate = translate_xsr,
5605 .test_exceptions = test_exceptions_sr,
5606 .par = (const uint32_t[]){
5607 ACCLO,
5608 XTENSA_OPTION_MAC16,
5609 },
5610 }, {
5611 .name = "xsr.atomctl",
5612 .translate = translate_xsr_mask,
5613 .test_exceptions = test_exceptions_sr,
5614 .par = (const uint32_t[]){
5615 ATOMCTL,
5616 XTENSA_OPTION_ATOMCTL,
5617 0x3f,
5618 },
5619 .op_flags = XTENSA_OP_PRIVILEGED,
5620 }, {
5621 .name = "xsr.br",
5622 .translate = translate_xsr_mask,
5623 .test_exceptions = test_exceptions_sr,
5624 .par = (const uint32_t[]){
5625 BR,
5626 XTENSA_OPTION_BOOLEAN,
5627 0xffff,
5628 },
5629 }, {
5630 .name = "xsr.cacheadrdis",
5631 .translate = translate_xsr_mask,
5632 .test_exceptions = test_exceptions_sr,
5633 .par = (const uint32_t[]){
5634 CACHEADRDIS,
5635 XTENSA_OPTION_MPU,
5636 0xff,
5637 },
5638 .op_flags = XTENSA_OP_PRIVILEGED,
5639 }, {
5640 .name = "xsr.cacheattr",
5641 .translate = translate_xsr,
5642 .test_exceptions = test_exceptions_sr,
5643 .par = (const uint32_t[]){
5644 CACHEATTR,
5645 XTENSA_OPTION_CACHEATTR,
5646 },
5647 .op_flags = XTENSA_OP_PRIVILEGED,
5648 }, {
5649 .name = "xsr.ccompare0",
5650 .translate = translate_xsr_ccompare,
5651 .test_exceptions = test_exceptions_ccompare,
5652 .par = (const uint32_t[]){
5653 CCOMPARE,
5654 XTENSA_OPTION_TIMER_INTERRUPT,
5655 },
5656 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5657 }, {
5658 .name = "xsr.ccompare1",
5659 .translate = translate_xsr_ccompare,
5660 .test_exceptions = test_exceptions_ccompare,
5661 .par = (const uint32_t[]){
5662 CCOMPARE + 1,
5663 XTENSA_OPTION_TIMER_INTERRUPT,
5664 },
5665 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5666 }, {
5667 .name = "xsr.ccompare2",
5668 .translate = translate_xsr_ccompare,
5669 .test_exceptions = test_exceptions_ccompare,
5670 .par = (const uint32_t[]){
5671 CCOMPARE + 2,
5672 XTENSA_OPTION_TIMER_INTERRUPT,
5673 },
5674 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5675 }, {
5676 .name = "xsr.ccount",
5677 .translate = translate_xsr_ccount,
5678 .test_exceptions = test_exceptions_sr,
5679 .par = (const uint32_t[]){
5680 CCOUNT,
5681 XTENSA_OPTION_TIMER_INTERRUPT,
5682 },
5683 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5684 }, {
5685 .name = "xsr.configid0",
5686 .op_flags = XTENSA_OP_ILL,
5687 }, {
5688 .name = "xsr.configid1",
5689 .op_flags = XTENSA_OP_ILL,
5690 }, {
5691 .name = "xsr.cpenable",
5692 .translate = translate_xsr_mask,
5693 .test_exceptions = test_exceptions_sr,
5694 .par = (const uint32_t[]){
5695 CPENABLE,
5696 XTENSA_OPTION_COPROCESSOR,
5697 0xff,
5698 },
5699 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5700 }, {
5701 .name = "xsr.dbreaka0",
5702 .translate = translate_xsr_dbreaka,
5703 .test_exceptions = test_exceptions_dbreak,
5704 .par = (const uint32_t[]){
5705 DBREAKA,
5706 XTENSA_OPTION_DEBUG,
5707 },
5708 .op_flags = XTENSA_OP_PRIVILEGED,
5709 }, {
5710 .name = "xsr.dbreaka1",
5711 .translate = translate_xsr_dbreaka,
5712 .test_exceptions = test_exceptions_dbreak,
5713 .par = (const uint32_t[]){
5714 DBREAKA + 1,
5715 XTENSA_OPTION_DEBUG,
5716 },
5717 .op_flags = XTENSA_OP_PRIVILEGED,
5718 }, {
5719 .name = "xsr.dbreakc0",
5720 .translate = translate_xsr_dbreakc,
5721 .test_exceptions = test_exceptions_dbreak,
5722 .par = (const uint32_t[]){
5723 DBREAKC,
5724 XTENSA_OPTION_DEBUG,
5725 },
5726 .op_flags = XTENSA_OP_PRIVILEGED,
5727 }, {
5728 .name = "xsr.dbreakc1",
5729 .translate = translate_xsr_dbreakc,
5730 .test_exceptions = test_exceptions_dbreak,
5731 .par = (const uint32_t[]){
5732 DBREAKC + 1,
5733 XTENSA_OPTION_DEBUG,
5734 },
5735 .op_flags = XTENSA_OP_PRIVILEGED,
5736 }, {
5737 .name = "xsr.ddr",
5738 .translate = translate_xsr,
5739 .test_exceptions = test_exceptions_sr,
5740 .par = (const uint32_t[]){
5741 DDR,
5742 XTENSA_OPTION_DEBUG,
5743 },
5744 .op_flags = XTENSA_OP_PRIVILEGED,
5745 }, {
5746 .name = "xsr.debugcause",
5747 .op_flags = XTENSA_OP_ILL,
5748 }, {
5749 .name = "xsr.depc",
5750 .translate = translate_xsr,
5751 .test_exceptions = test_exceptions_sr,
5752 .par = (const uint32_t[]){
5753 DEPC,
5754 XTENSA_OPTION_EXCEPTION,
5755 },
5756 .op_flags = XTENSA_OP_PRIVILEGED,
5757 }, {
5758 .name = "xsr.dtlbcfg",
5759 .translate = translate_xsr_mask,
5760 .test_exceptions = test_exceptions_sr,
5761 .par = (const uint32_t[]){
5762 DTLBCFG,
5763 XTENSA_OPTION_MMU,
5764 0x01130000,
5765 },
5766 .op_flags = XTENSA_OP_PRIVILEGED,
5767 }, {
5768 .name = "xsr.epc1",
5769 .translate = translate_xsr,
5770 .test_exceptions = test_exceptions_sr,
5771 .par = (const uint32_t[]){
5772 EPC1,
5773 XTENSA_OPTION_EXCEPTION,
5774 },
5775 .op_flags = XTENSA_OP_PRIVILEGED,
5776 }, {
5777 .name = "xsr.epc2",
5778 .translate = translate_xsr,
5779 .test_exceptions = test_exceptions_hpi,
5780 .par = (const uint32_t[]){
5781 EPC1 + 1,
5782 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5783 },
5784 .op_flags = XTENSA_OP_PRIVILEGED,
5785 }, {
5786 .name = "xsr.epc3",
5787 .translate = translate_xsr,
5788 .test_exceptions = test_exceptions_hpi,
5789 .par = (const uint32_t[]){
5790 EPC1 + 2,
5791 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5792 },
5793 .op_flags = XTENSA_OP_PRIVILEGED,
5794 }, {
5795 .name = "xsr.epc4",
5796 .translate = translate_xsr,
5797 .test_exceptions = test_exceptions_hpi,
5798 .par = (const uint32_t[]){
5799 EPC1 + 3,
5800 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5801 },
5802 .op_flags = XTENSA_OP_PRIVILEGED,
5803 }, {
5804 .name = "xsr.epc5",
5805 .translate = translate_xsr,
5806 .test_exceptions = test_exceptions_hpi,
5807 .par = (const uint32_t[]){
5808 EPC1 + 4,
5809 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5810 },
5811 .op_flags = XTENSA_OP_PRIVILEGED,
5812 }, {
5813 .name = "xsr.epc6",
5814 .translate = translate_xsr,
5815 .test_exceptions = test_exceptions_hpi,
5816 .par = (const uint32_t[]){
5817 EPC1 + 5,
5818 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5819 },
5820 .op_flags = XTENSA_OP_PRIVILEGED,
5821 }, {
5822 .name = "xsr.epc7",
5823 .translate = translate_xsr,
5824 .test_exceptions = test_exceptions_hpi,
5825 .par = (const uint32_t[]){
5826 EPC1 + 6,
5827 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5828 },
5829 .op_flags = XTENSA_OP_PRIVILEGED,
5830 }, {
5831 .name = "xsr.eps2",
5832 .translate = translate_xsr,
5833 .test_exceptions = test_exceptions_hpi,
5834 .par = (const uint32_t[]){
5835 EPS2,
5836 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5837 },
5838 .op_flags = XTENSA_OP_PRIVILEGED,
5839 }, {
5840 .name = "xsr.eps3",
5841 .translate = translate_xsr,
5842 .test_exceptions = test_exceptions_hpi,
5843 .par = (const uint32_t[]){
5844 EPS2 + 1,
5845 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5846 },
5847 .op_flags = XTENSA_OP_PRIVILEGED,
5848 }, {
5849 .name = "xsr.eps4",
5850 .translate = translate_xsr,
5851 .test_exceptions = test_exceptions_hpi,
5852 .par = (const uint32_t[]){
5853 EPS2 + 2,
5854 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5855 },
5856 .op_flags = XTENSA_OP_PRIVILEGED,
5857 }, {
5858 .name = "xsr.eps5",
5859 .translate = translate_xsr,
5860 .test_exceptions = test_exceptions_hpi,
5861 .par = (const uint32_t[]){
5862 EPS2 + 3,
5863 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5864 },
5865 .op_flags = XTENSA_OP_PRIVILEGED,
5866 }, {
5867 .name = "xsr.eps6",
5868 .translate = translate_xsr,
5869 .test_exceptions = test_exceptions_hpi,
5870 .par = (const uint32_t[]){
5871 EPS2 + 4,
5872 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5873 },
5874 .op_flags = XTENSA_OP_PRIVILEGED,
5875 }, {
5876 .name = "xsr.eps7",
5877 .translate = translate_xsr,
5878 .test_exceptions = test_exceptions_hpi,
5879 .par = (const uint32_t[]){
5880 EPS2 + 5,
5881 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5882 },
5883 .op_flags = XTENSA_OP_PRIVILEGED,
5884 }, {
5885 .name = "xsr.eraccess",
5886 .translate = translate_xsr_mask,
5887 .par = (const uint32_t[]){
5888 ERACCESS,
5889 0,
5890 0xffff,
5891 },
5892 .op_flags = XTENSA_OP_PRIVILEGED,
5893 }, {
5894 .name = "xsr.exccause",
5895 .translate = translate_xsr,
5896 .test_exceptions = test_exceptions_sr,
5897 .par = (const uint32_t[]){
5898 EXCCAUSE,
5899 XTENSA_OPTION_EXCEPTION,
5900 },
5901 .op_flags = XTENSA_OP_PRIVILEGED,
5902 }, {
5903 .name = "xsr.excsave1",
5904 .translate = translate_xsr,
5905 .test_exceptions = test_exceptions_sr,
5906 .par = (const uint32_t[]){
5907 EXCSAVE1,
5908 XTENSA_OPTION_EXCEPTION,
5909 },
5910 .op_flags = XTENSA_OP_PRIVILEGED,
5911 }, {
5912 .name = "xsr.excsave2",
5913 .translate = translate_xsr,
5914 .test_exceptions = test_exceptions_hpi,
5915 .par = (const uint32_t[]){
5916 EXCSAVE1 + 1,
5917 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5918 },
5919 .op_flags = XTENSA_OP_PRIVILEGED,
5920 }, {
5921 .name = "xsr.excsave3",
5922 .translate = translate_xsr,
5923 .test_exceptions = test_exceptions_hpi,
5924 .par = (const uint32_t[]){
5925 EXCSAVE1 + 2,
5926 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5927 },
5928 .op_flags = XTENSA_OP_PRIVILEGED,
5929 }, {
5930 .name = "xsr.excsave4",
5931 .translate = translate_xsr,
5932 .test_exceptions = test_exceptions_hpi,
5933 .par = (const uint32_t[]){
5934 EXCSAVE1 + 3,
5935 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5936 },
5937 .op_flags = XTENSA_OP_PRIVILEGED,
5938 }, {
5939 .name = "xsr.excsave5",
5940 .translate = translate_xsr,
5941 .test_exceptions = test_exceptions_hpi,
5942 .par = (const uint32_t[]){
5943 EXCSAVE1 + 4,
5944 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5945 },
5946 .op_flags = XTENSA_OP_PRIVILEGED,
5947 }, {
5948 .name = "xsr.excsave6",
5949 .translate = translate_xsr,
5950 .test_exceptions = test_exceptions_hpi,
5951 .par = (const uint32_t[]){
5952 EXCSAVE1 + 5,
5953 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5954 },
5955 .op_flags = XTENSA_OP_PRIVILEGED,
5956 }, {
5957 .name = "xsr.excsave7",
5958 .translate = translate_xsr,
5959 .test_exceptions = test_exceptions_hpi,
5960 .par = (const uint32_t[]){
5961 EXCSAVE1 + 6,
5962 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5963 },
5964 .op_flags = XTENSA_OP_PRIVILEGED,
5965 }, {
5966 .name = "xsr.excvaddr",
5967 .translate = translate_xsr,
5968 .test_exceptions = test_exceptions_sr,
5969 .par = (const uint32_t[]){
5970 EXCVADDR,
5971 XTENSA_OPTION_EXCEPTION,
5972 },
5973 .op_flags = XTENSA_OP_PRIVILEGED,
5974 }, {
5975 .name = "xsr.ibreaka0",
5976 .translate = translate_xsr_ibreaka,
5977 .test_exceptions = test_exceptions_ibreak,
5978 .par = (const uint32_t[]){
5979 IBREAKA,
5980 XTENSA_OPTION_DEBUG,
5981 },
5982 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5983 }, {
5984 .name = "xsr.ibreaka1",
5985 .translate = translate_xsr_ibreaka,
5986 .test_exceptions = test_exceptions_ibreak,
5987 .par = (const uint32_t[]){
5988 IBREAKA + 1,
5989 XTENSA_OPTION_DEBUG,
5990 },
5991 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5992 }, {
5993 .name = "xsr.ibreakenable",
5994 .translate = translate_xsr_ibreakenable,
5995 .test_exceptions = test_exceptions_sr,
5996 .par = (const uint32_t[]){
5997 IBREAKENABLE,
5998 XTENSA_OPTION_DEBUG,
5999 },
6000 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
6001 }, {
6002 .name = "xsr.icount",
6003 .translate = translate_xsr_icount,
6004 .test_exceptions = test_exceptions_sr,
6005 .par = (const uint32_t[]){
6006 ICOUNT,
6007 XTENSA_OPTION_DEBUG,
6008 },
6009 .op_flags = XTENSA_OP_PRIVILEGED,
6010 }, {
6011 .name = "xsr.icountlevel",
6012 .translate = translate_xsr_mask,
6013 .test_exceptions = test_exceptions_sr,
6014 .par = (const uint32_t[]){
6015 ICOUNTLEVEL,
6016 XTENSA_OPTION_DEBUG,
6017 0xf,
6018 },
6019 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6020 }, {
6021 .name = "xsr.intclear",
6022 .op_flags = XTENSA_OP_ILL,
6023 }, {
6024 .name = "xsr.intenable",
6025 .translate = translate_xsr,
6026 .test_exceptions = test_exceptions_sr,
6027 .par = (const uint32_t[]){
6028 INTENABLE,
6029 XTENSA_OPTION_INTERRUPT,
6030 },
6031 .op_flags =
6032 XTENSA_OP_PRIVILEGED |
6033 XTENSA_OP_EXIT_TB_0 |
6034 XTENSA_OP_CHECK_INTERRUPTS,
6035 }, {
6036 .name = "xsr.interrupt",
6037 .op_flags = XTENSA_OP_ILL,
6038 }, {
6039 .name = "xsr.intset",
6040 .op_flags = XTENSA_OP_ILL,
6041 }, {
6042 .name = "xsr.itlbcfg",
6043 .translate = translate_xsr_mask,
6044 .test_exceptions = test_exceptions_sr,
6045 .par = (const uint32_t[]){
6046 ITLBCFG,
6047 XTENSA_OPTION_MMU,
6048 0x01130000,
6049 },
6050 .op_flags = XTENSA_OP_PRIVILEGED,
6051 }, {
6052 .name = "xsr.lbeg",
6053 .translate = translate_xsr,
6054 .test_exceptions = test_exceptions_sr,
6055 .par = (const uint32_t[]){
6056 LBEG,
6057 XTENSA_OPTION_LOOP,
6058 },
6059 .op_flags = XTENSA_OP_EXIT_TB_M1,
6060 }, {
6061 .name = "xsr.lcount",
6062 .translate = translate_xsr,
6063 .test_exceptions = test_exceptions_sr,
6064 .par = (const uint32_t[]){
6065 LCOUNT,
6066 XTENSA_OPTION_LOOP,
6067 },
6068 }, {
6069 .name = "xsr.lend",
6070 .translate = translate_xsr,
6071 .test_exceptions = test_exceptions_sr,
6072 .par = (const uint32_t[]){
6073 LEND,
6074 XTENSA_OPTION_LOOP,
6075 },
6076 .op_flags = XTENSA_OP_EXIT_TB_M1,
6077 }, {
6078 .name = "xsr.litbase",
6079 .translate = translate_xsr_mask,
6080 .test_exceptions = test_exceptions_sr,
6081 .par = (const uint32_t[]){
6082 LITBASE,
6083 XTENSA_OPTION_EXTENDED_L32R,
6084 0xfffff001,
6085 },
6086 .op_flags = XTENSA_OP_EXIT_TB_M1,
6087 }, {
6088 .name = "xsr.m0",
6089 .translate = translate_xsr,
6090 .test_exceptions = test_exceptions_sr,
6091 .par = (const uint32_t[]){
6092 MR,
6093 XTENSA_OPTION_MAC16,
6094 },
6095 }, {
6096 .name = "xsr.m1",
6097 .translate = translate_xsr,
6098 .test_exceptions = test_exceptions_sr,
6099 .par = (const uint32_t[]){
6100 MR + 1,
6101 XTENSA_OPTION_MAC16,
6102 },
6103 }, {
6104 .name = "xsr.m2",
6105 .translate = translate_xsr,
6106 .test_exceptions = test_exceptions_sr,
6107 .par = (const uint32_t[]){
6108 MR + 2,
6109 XTENSA_OPTION_MAC16,
6110 },
6111 }, {
6112 .name = "xsr.m3",
6113 .translate = translate_xsr,
6114 .test_exceptions = test_exceptions_sr,
6115 .par = (const uint32_t[]){
6116 MR + 3,
6117 XTENSA_OPTION_MAC16,
6118 },
6119 }, {
6120 .name = "xsr.memctl",
6121 .translate = translate_xsr_memctl,
6122 .par = (const uint32_t[]){MEMCTL},
6123 .op_flags = XTENSA_OP_PRIVILEGED,
6124 }, {
6125 .name = "xsr.mecr",
6126 .translate = translate_xsr,
6127 .test_exceptions = test_exceptions_sr,
6128 .par = (const uint32_t[]){
6129 MECR,
6130 XTENSA_OPTION_MEMORY_ECC_PARITY,
6131 },
6132 .op_flags = XTENSA_OP_PRIVILEGED,
6133 }, {
6134 .name = "xsr.mepc",
6135 .translate = translate_xsr,
6136 .test_exceptions = test_exceptions_sr,
6137 .par = (const uint32_t[]){
6138 MEPC,
6139 XTENSA_OPTION_MEMORY_ECC_PARITY,
6140 },
6141 .op_flags = XTENSA_OP_PRIVILEGED,
6142 }, {
6143 .name = "xsr.meps",
6144 .translate = translate_xsr,
6145 .test_exceptions = test_exceptions_sr,
6146 .par = (const uint32_t[]){
6147 MEPS,
6148 XTENSA_OPTION_MEMORY_ECC_PARITY,
6149 },
6150 .op_flags = XTENSA_OP_PRIVILEGED,
6151 }, {
6152 .name = "xsr.mesave",
6153 .translate = translate_xsr,
6154 .test_exceptions = test_exceptions_sr,
6155 .par = (const uint32_t[]){
6156 MESAVE,
6157 XTENSA_OPTION_MEMORY_ECC_PARITY,
6158 },
6159 .op_flags = XTENSA_OP_PRIVILEGED,
6160 }, {
6161 .name = "xsr.mesr",
6162 .translate = translate_xsr,
6163 .test_exceptions = test_exceptions_sr,
6164 .par = (const uint32_t[]){
6165 MESR,
6166 XTENSA_OPTION_MEMORY_ECC_PARITY,
6167 },
6168 .op_flags = XTENSA_OP_PRIVILEGED,
6169 }, {
6170 .name = "xsr.mevaddr",
6171 .translate = translate_xsr,
6172 .test_exceptions = test_exceptions_sr,
6173 .par = (const uint32_t[]){
6174 MESR,
6175 XTENSA_OPTION_MEMORY_ECC_PARITY,
6176 },
6177 .op_flags = XTENSA_OP_PRIVILEGED,
6178 }, {
6179 .name = "xsr.misc0",
6180 .translate = translate_xsr,
6181 .test_exceptions = test_exceptions_sr,
6182 .par = (const uint32_t[]){
6183 MISC,
6184 XTENSA_OPTION_MISC_SR,
6185 },
6186 .op_flags = XTENSA_OP_PRIVILEGED,
6187 }, {
6188 .name = "xsr.misc1",
6189 .translate = translate_xsr,
6190 .test_exceptions = test_exceptions_sr,
6191 .par = (const uint32_t[]){
6192 MISC + 1,
6193 XTENSA_OPTION_MISC_SR,
6194 },
6195 .op_flags = XTENSA_OP_PRIVILEGED,
6196 }, {
6197 .name = "xsr.misc2",
6198 .translate = translate_xsr,
6199 .test_exceptions = test_exceptions_sr,
6200 .par = (const uint32_t[]){
6201 MISC + 2,
6202 XTENSA_OPTION_MISC_SR,
6203 },
6204 .op_flags = XTENSA_OP_PRIVILEGED,
6205 }, {
6206 .name = "xsr.misc3",
6207 .translate = translate_xsr,
6208 .test_exceptions = test_exceptions_sr,
6209 .par = (const uint32_t[]){
6210 MISC + 3,
6211 XTENSA_OPTION_MISC_SR,
6212 },
6213 .op_flags = XTENSA_OP_PRIVILEGED,
6214 }, {
6215 .name = "xsr.mpuenb",
6216 .translate = translate_xsr_mpuenb,
6217 .test_exceptions = test_exceptions_sr,
6218 .par = (const uint32_t[]){
6219 MPUENB,
6220 XTENSA_OPTION_MPU,
6221 },
6222 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6223 }, {
6224 .name = "xsr.prefctl",
6225 .translate = translate_xsr,
6226 .par = (const uint32_t[]){PREFCTL},
6227 }, {
6228 .name = "xsr.prid",
6229 .op_flags = XTENSA_OP_ILL,
6230 }, {
6231 .name = "xsr.ps",
6232 .translate = translate_xsr_ps,
6233 .test_exceptions = test_exceptions_sr,
6234 .par = (const uint32_t[]){
6235 PS,
6236 XTENSA_OPTION_EXCEPTION,
6237 },
6238 .op_flags =
6239 XTENSA_OP_PRIVILEGED |
6240 XTENSA_OP_EXIT_TB_M1 |
6241 XTENSA_OP_CHECK_INTERRUPTS,
6242 }, {
6243 .name = "xsr.ptevaddr",
6244 .translate = translate_xsr_mask,
6245 .test_exceptions = test_exceptions_sr,
6246 .par = (const uint32_t[]){
6247 PTEVADDR,
6248 XTENSA_OPTION_MMU,
6249 0xffc00000,
6250 },
6251 .op_flags = XTENSA_OP_PRIVILEGED,
6252 }, {
6253 .name = "xsr.rasid",
6254 .translate = translate_xsr_rasid,
6255 .test_exceptions = test_exceptions_sr,
6256 .par = (const uint32_t[]){
6257 RASID,
6258 XTENSA_OPTION_MMU,
6259 },
6260 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6261 }, {
6262 .name = "xsr.sar",
6263 .translate = translate_xsr_sar,
6264 .par = (const uint32_t[]){SAR},
6265 }, {
6266 .name = "xsr.scompare1",
6267 .translate = translate_xsr,
6268 .test_exceptions = test_exceptions_sr,
6269 .par = (const uint32_t[]){
6270 SCOMPARE1,
6271 XTENSA_OPTION_CONDITIONAL_STORE,
6272 },
6273 }, {
6274 .name = "xsr.vecbase",
6275 .translate = translate_xsr,
6276 .test_exceptions = test_exceptions_sr,
6277 .par = (const uint32_t[]){
6278 VECBASE,
6279 XTENSA_OPTION_RELOCATABLE_VECTOR,
6280 },
6281 .op_flags = XTENSA_OP_PRIVILEGED,
6282 }, {
6283 .name = "xsr.windowbase",
6284 .translate = translate_xsr_windowbase,
6285 .test_exceptions = test_exceptions_sr,
6286 .par = (const uint32_t[]){
6287 WINDOW_BASE,
6288 XTENSA_OPTION_WINDOWED_REGISTER,
6289 },
6290 .op_flags = XTENSA_OP_PRIVILEGED |
6291 XTENSA_OP_EXIT_TB_M1 |
6292 XTENSA_OP_SYNC_REGISTER_WINDOW,
6293 }, {
6294 .name = "xsr.windowstart",
6295 .translate = translate_xsr_windowstart,
6296 .test_exceptions = test_exceptions_sr,
6297 .par = (const uint32_t[]){
6298 WINDOW_START,
6299 XTENSA_OPTION_WINDOWED_REGISTER,
6300 },
6301 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6302 },
6303 };
6304
6305 const XtensaOpcodeTranslators xtensa_core_opcodes = {
6306 .num_opcodes = ARRAY_SIZE(core_ops),
6307 .opcode = core_ops,
6308 };
6309
6310
6311 static inline void get_f32_o1_i3(const OpcodeArg *arg, OpcodeArg *arg32,
6312 int o0, int i0, int i1, int i2)
6313 {
6314 if ((i0 >= 0 && arg[i0].num_bits == 64) ||
6315 (o0 >= 0 && arg[o0].num_bits == 64)) {
6316 if (o0 >= 0) {
6317 arg32[o0].out = tcg_temp_new_i32();
6318 }
6319 if (i0 >= 0) {
6320 arg32[i0].in = tcg_temp_new_i32();
6321 tcg_gen_extrl_i64_i32(arg32[i0].in, arg[i0].in);
6322 }
6323 if (i1 >= 0) {
6324 arg32[i1].in = tcg_temp_new_i32();
6325 tcg_gen_extrl_i64_i32(arg32[i1].in, arg[i1].in);
6326 }
6327 if (i2 >= 0) {
6328 arg32[i2].in = tcg_temp_new_i32();
6329 tcg_gen_extrl_i64_i32(arg32[i2].in, arg[i2].in);
6330 }
6331 } else {
6332 if (o0 >= 0) {
6333 arg32[o0].out = arg[o0].out;
6334 }
6335 if (i0 >= 0) {
6336 arg32[i0].in = arg[i0].in;
6337 }
6338 if (i1 >= 0) {
6339 arg32[i1].in = arg[i1].in;
6340 }
6341 if (i2 >= 0) {
6342 arg32[i2].in = arg[i2].in;
6343 }
6344 }
6345 }
6346
6347 static inline void put_f32_o1_i3(const OpcodeArg *arg, const OpcodeArg *arg32,
6348 int o0, int i0, int i1, int i2)
6349 {
6350 if ((i0 >= 0 && arg[i0].num_bits == 64) ||
6351 (o0 >= 0 && arg[o0].num_bits == 64)) {
6352 if (o0 >= 0) {
6353 tcg_gen_extu_i32_i64(arg[o0].out, arg32[o0].out);
6354 tcg_temp_free_i32(arg32[o0].out);
6355 }
6356 if (i0 >= 0) {
6357 tcg_temp_free_i32(arg32[i0].in);
6358 }
6359 if (i1 >= 0) {
6360 tcg_temp_free_i32(arg32[i1].in);
6361 }
6362 if (i2 >= 0) {
6363 tcg_temp_free_i32(arg32[i2].in);
6364 }
6365 }
6366 }
6367
6368 static inline void get_f32_o1_i2(const OpcodeArg *arg, OpcodeArg *arg32,
6369 int o0, int i0, int i1)
6370 {
6371 get_f32_o1_i3(arg, arg32, o0, i0, i1, -1);
6372 }
6373
6374 static inline void put_f32_o1_i2(const OpcodeArg *arg, const OpcodeArg *arg32,
6375 int o0, int i0, int i1)
6376 {
6377 put_f32_o1_i3(arg, arg32, o0, i0, i1, -1);
6378 }
6379
6380 static inline void get_f32_o1_i1(const OpcodeArg *arg, OpcodeArg *arg32,
6381 int o0, int i0)
6382 {
6383 get_f32_o1_i2(arg, arg32, o0, i0, -1);
6384 }
6385
6386 static inline void put_f32_o1_i1(const OpcodeArg *arg, const OpcodeArg *arg32,
6387 int o0, int i0)
6388 {
6389 put_f32_o1_i2(arg, arg32, o0, i0, -1);
6390 }
6391
6392 static inline void get_f32_o1(const OpcodeArg *arg, OpcodeArg *arg32,
6393 int o0)
6394 {
6395 get_f32_o1_i1(arg, arg32, o0, -1);
6396 }
6397
6398 static inline void put_f32_o1(const OpcodeArg *arg, const OpcodeArg *arg32,
6399 int o0)
6400 {
6401 put_f32_o1_i1(arg, arg32, o0, -1);
6402 }
6403
6404 static inline void get_f32_i2(const OpcodeArg *arg, OpcodeArg *arg32,
6405 int i0, int i1)
6406 {
6407 get_f32_o1_i2(arg, arg32, -1, i0, i1);
6408 }
6409
6410 static inline void put_f32_i2(const OpcodeArg *arg, const OpcodeArg *arg32,
6411 int i0, int i1)
6412 {
6413 put_f32_o1_i2(arg, arg32, -1, i0, i1);
6414 }
6415
6416 static inline void get_f32_i1(const OpcodeArg *arg, OpcodeArg *arg32,
6417 int i0)
6418 {
6419 get_f32_i2(arg, arg32, i0, -1);
6420 }
6421
6422 static inline void put_f32_i1(const OpcodeArg *arg, const OpcodeArg *arg32,
6423 int i0)
6424 {
6425 put_f32_i2(arg, arg32, i0, -1);
6426 }
6427
6428
6429 static void translate_abs_d(DisasContext *dc, const OpcodeArg arg[],
6430 const uint32_t par[])
6431 {
6432 gen_helper_abs_d(arg[0].out, arg[1].in);
6433 }
6434
6435 static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[],
6436 const uint32_t par[])
6437 {
6438 OpcodeArg arg32[2];
6439
6440 get_f32_o1_i1(arg, arg32, 0, 1);
6441 gen_helper_abs_s(arg32[0].out, arg32[1].in);
6442 put_f32_o1_i1(arg, arg32, 0, 1);
6443 }
6444
6445 static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
6446 const uint32_t par[])
6447 {
6448 gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
6449 arg[1].in, arg[2].in);
6450 }
6451
6452 enum {
6453 COMPARE_UN,
6454 COMPARE_OEQ,
6455 COMPARE_UEQ,
6456 COMPARE_OLT,
6457 COMPARE_ULT,
6458 COMPARE_OLE,
6459 COMPARE_ULE,
6460 };
6461
6462 static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
6463 const uint32_t par[])
6464 {
6465 static void (* const helper[])(TCGv_i32 res, TCGv_env env,
6466 TCGv_i64 s, TCGv_i64 t) = {
6467 [COMPARE_UN] = gen_helper_un_d,
6468 [COMPARE_OEQ] = gen_helper_oeq_d,
6469 [COMPARE_UEQ] = gen_helper_ueq_d,
6470 [COMPARE_OLT] = gen_helper_olt_d,
6471 [COMPARE_ULT] = gen_helper_ult_d,
6472 [COMPARE_OLE] = gen_helper_ole_d,
6473 [COMPARE_ULE] = gen_helper_ule_d,
6474 };
6475 TCGv_i32 zero = tcg_const_i32(0);
6476 TCGv_i32 res = tcg_temp_new_i32();
6477 TCGv_i32 set_br = tcg_temp_new_i32();
6478 TCGv_i32 clr_br = tcg_temp_new_i32();
6479
6480 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
6481 tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
6482
6483 helper[par[0]](res, cpu_env, arg[1].in, arg[2].in);
6484 tcg_gen_movcond_i32(TCG_COND_NE,
6485 arg[0].out, res, zero,
6486 set_br, clr_br);
6487 tcg_temp_free(zero);
6488 tcg_temp_free(res);
6489 tcg_temp_free(set_br);
6490 tcg_temp_free(clr_br);
6491 }
6492
6493 static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
6494 const uint32_t par[])
6495 {
6496 static void (* const helper[])(TCGv_i32 res, TCGv_env env,
6497 TCGv_i32 s, TCGv_i32 t) = {
6498 [COMPARE_UN] = gen_helper_un_s,
6499 [COMPARE_OEQ] = gen_helper_oeq_s,
6500 [COMPARE_UEQ] = gen_helper_ueq_s,
6501 [COMPARE_OLT] = gen_helper_olt_s,
6502 [COMPARE_ULT] = gen_helper_ult_s,
6503 [COMPARE_OLE] = gen_helper_ole_s,
6504 [COMPARE_ULE] = gen_helper_ule_s,
6505 };
6506 OpcodeArg arg32[3];
6507 TCGv_i32 zero = tcg_const_i32(0);
6508 TCGv_i32 res = tcg_temp_new_i32();
6509 TCGv_i32 set_br = tcg_temp_new_i32();
6510 TCGv_i32 clr_br = tcg_temp_new_i32();
6511
6512 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
6513 tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
6514
6515 get_f32_i2(arg, arg32, 1, 2);
6516 helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in);
6517 tcg_gen_movcond_i32(TCG_COND_NE,
6518 arg[0].out, res, zero,
6519 set_br, clr_br);
6520 put_f32_i2(arg, arg32, 1, 2);
6521 tcg_temp_free(zero);
6522 tcg_temp_free(res);
6523 tcg_temp_free(set_br);
6524 tcg_temp_free(clr_br);
6525 }
6526
6527 static void translate_const_d(DisasContext *dc, const OpcodeArg arg[],
6528 const uint32_t par[])
6529 {
6530 static const uint64_t v[] = {
6531 UINT64_C(0x0000000000000000),
6532 UINT64_C(0x3ff0000000000000),
6533 UINT64_C(0x4000000000000000),
6534 UINT64_C(0x3fe0000000000000),
6535 };
6536
6537 tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]);
6538 if (arg[1].imm >= ARRAY_SIZE(v)) {
6539 qemu_log_mask(LOG_GUEST_ERROR,
6540 "const.d f%d, #%d, immediate value is reserved\n",
6541 arg[0].imm, arg[1].imm);
6542 }
6543 }
6544
6545 static void translate_const_s(DisasContext *dc, const OpcodeArg arg[],
6546 const uint32_t par[])
6547 {
6548 static const uint32_t v[] = {
6549 0x00000000,
6550 0x3f800000,
6551 0x40000000,
6552 0x3f000000,
6553 };
6554
6555 if (arg[0].num_bits == 32) {
6556 tcg_gen_movi_i32(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]);
6557 } else {
6558 tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]);
6559 }
6560 if (arg[1].imm >= ARRAY_SIZE(v)) {
6561 qemu_log_mask(LOG_GUEST_ERROR,
6562 "const.s f%d, #%d, immediate value is reserved\n",
6563 arg[0].imm, arg[1].imm);
6564 }
6565 }
6566
6567 static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
6568 const uint32_t par[])
6569 {
6570 TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
6571
6572 if (par[0]) {
6573 gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
6574 } else {
6575 gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
6576 }
6577 tcg_temp_free(scale);
6578 }
6579
6580 static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
6581 const uint32_t par[])
6582 {
6583 TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
6584 OpcodeArg arg32[1];
6585
6586 get_f32_o1(arg, arg32, 0);
6587 if (par[0]) {
6588 gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale);
6589 } else {
6590 gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
6591 }
6592 put_f32_o1(arg, arg32, 0);
6593 tcg_temp_free(scale);
6594 }
6595
6596 static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
6597 const uint32_t par[])
6598 {
6599 TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
6600 TCGv_i32 scale = tcg_const_i32(arg[2].imm);
6601
6602 if (par[1]) {
6603 gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
6604 rounding_mode, scale);
6605 } else {
6606 gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
6607 rounding_mode, scale);
6608 }
6609 tcg_temp_free(rounding_mode);
6610 tcg_temp_free(scale);
6611 }
6612
6613 static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
6614 const uint32_t par[])
6615 {
6616 TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
6617 TCGv_i32 scale = tcg_const_i32(arg[2].imm);
6618 OpcodeArg arg32[2];
6619
6620 get_f32_i1(arg, arg32, 1);
6621 if (par[1]) {
6622 gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in,
6623 rounding_mode, scale);
6624 } else {
6625 gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in,
6626 rounding_mode, scale);
6627 }
6628 put_f32_i1(arg, arg32, 1);
6629 tcg_temp_free(rounding_mode);
6630 tcg_temp_free(scale);
6631 }
6632
6633 static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
6634 const uint32_t par[])
6635 {
6636 TCGv_i32 addr = tcg_temp_new_i32();
6637 MemOp mop;
6638
6639 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
6640 mop = gen_load_store_alignment(dc, MO_TEUL, addr);
6641 if (par[0]) {
6642 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop);
6643 } else {
6644 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop);
6645 }
6646 if (par[1]) {
6647 tcg_gen_mov_i32(arg[1].out, addr);
6648 }
6649 tcg_temp_free(addr);
6650 }
6651
6652 static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],
6653 const uint32_t par[])
6654 {
6655 TCGv_i32 addr = tcg_temp_new_i32();
6656 MemOp mop;
6657
6658 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
6659 mop = gen_load_store_alignment(dc, MO_TEUL, addr);
6660 if (par[0]) {
6661 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop);
6662 } else {
6663 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop);
6664 }
6665 if (par[1]) {
6666 tcg_gen_mov_i32(arg[1].out, addr);
6667 }
6668 tcg_temp_free(addr);
6669 }
6670
6671 static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
6672 const uint32_t par[])
6673 {
6674 gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
6675 arg[0].in, arg[1].in, arg[2].in);
6676 }
6677
6678 static void translate_mov_d(DisasContext *dc, const OpcodeArg arg[],
6679 const uint32_t par[])
6680 {
6681 tcg_gen_mov_i64(arg[0].out, arg[1].in);
6682 }
6683
6684 static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],
6685 const uint32_t par[])
6686 {
6687 if (arg[0].num_bits == 32) {
6688 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6689 } else {
6690 tcg_gen_mov_i64(arg[0].out, arg[1].in);
6691 }
6692 }
6693
6694 static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
6695 const uint32_t par[])
6696 {
6697 TCGv_i64 zero = tcg_const_i64(0);
6698 TCGv_i64 arg2 = tcg_temp_new_i64();
6699
6700 tcg_gen_ext_i32_i64(arg2, arg[2].in);
6701 tcg_gen_movcond_i64(par[0], arg[0].out,
6702 arg2, zero,
6703 arg[1].in, arg[0].in);
6704 tcg_temp_free_i64(zero);
6705 tcg_temp_free_i64(arg2);
6706 }
6707
6708 static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
6709 const uint32_t par[])
6710 {
6711 if (arg[0].num_bits == 32) {
6712 TCGv_i32 zero = tcg_const_i32(0);
6713
6714 tcg_gen_movcond_i32(par[0], arg[0].out,
6715 arg[2].in, zero,
6716 arg[1].in, arg[0].in);
6717 tcg_temp_free(zero);
6718 } else {
6719 translate_movcond_d(dc, arg, par);
6720 }
6721 }
6722
6723 static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
6724 const uint32_t par[])
6725 {
6726 TCGv_i64 zero = tcg_const_i64(0);
6727 TCGv_i32 tmp1 = tcg_temp_new_i32();
6728 TCGv_i64 tmp2 = tcg_temp_new_i64();
6729
6730 tcg_gen_andi_i32(tmp1, arg[2].in, 1 << arg[2].imm);
6731 tcg_gen_extu_i32_i64(tmp2, tmp1);
6732 tcg_gen_movcond_i64(par[0],
6733 arg[0].out, tmp2, zero,
6734 arg[1].in, arg[0].in);
6735 tcg_temp_free_i64(zero);
6736 tcg_temp_free_i32(tmp1);
6737 tcg_temp_free_i64(tmp2);
6738 }
6739
6740 static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
6741 const uint32_t par[])
6742 {
6743 if (arg[0].num_bits == 32) {
6744 TCGv_i32 zero = tcg_const_i32(0);
6745 TCGv_i32 tmp = tcg_temp_new_i32();
6746
6747 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
6748 tcg_gen_movcond_i32(par[0],
6749 arg[0].out, tmp, zero,
6750 arg[1].in, arg[0].in);
6751 tcg_temp_free(tmp);
6752 tcg_temp_free(zero);
6753 } else {
6754 translate_movp_d(dc, arg, par);
6755 }
6756 }
6757
6758 static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
6759 const uint32_t par[])
6760 {
6761 gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
6762 arg[1].in, arg[2].in);
6763 }
6764
6765 static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
6766 const uint32_t par[])
6767 {
6768 gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
6769 arg[0].in, arg[1].in, arg[2].in);
6770 }
6771
6772 static void translate_neg_d(DisasContext *dc, const OpcodeArg arg[],
6773 const uint32_t par[])
6774 {
6775 gen_helper_neg_d(arg[0].out, arg[1].in);
6776 }
6777
6778 static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[],
6779 const uint32_t par[])
6780 {
6781 OpcodeArg arg32[2];
6782
6783 get_f32_o1_i1(arg, arg32, 0, 1);
6784 gen_helper_neg_s(arg32[0].out, arg32[1].in);
6785 put_f32_o1_i1(arg, arg32, 0, 1);
6786 }
6787
6788 static void translate_rfr_d(DisasContext *dc, const OpcodeArg arg[],
6789 const uint32_t par[])
6790 {
6791 tcg_gen_extrh_i64_i32(arg[0].out, arg[1].in);
6792 }
6793
6794 static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[],
6795 const uint32_t par[])
6796 {
6797 if (arg[1].num_bits == 32) {
6798 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6799 } else {
6800 tcg_gen_extrl_i64_i32(arg[0].out, arg[1].in);
6801 }
6802 }
6803
6804 static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
6805 const uint32_t par[])
6806 {
6807 gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
6808 arg[1].in, arg[2].in);
6809 }
6810
6811 static void translate_wfr_d(DisasContext *dc, const OpcodeArg arg[],
6812 const uint32_t par[])
6813 {
6814 tcg_gen_concat_i32_i64(arg[0].out, arg[2].in, arg[1].in);
6815 }
6816
6817 static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
6818 const uint32_t par[])
6819 {
6820 if (arg[0].num_bits == 32) {
6821 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6822 } else {
6823 tcg_gen_ext_i32_i64(arg[0].out, arg[1].in);
6824 }
6825 }
6826
6827 static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
6828 const uint32_t par[])
6829 {
6830 gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
6831 }
6832
6833 static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
6834 const uint32_t par[])
6835 {
6836 tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
6837 }
6838
6839 static const XtensaOpcodeOps fpu2000_ops[] = {
6840 {
6841 .name = "abs.s",
6842 .translate = translate_abs_s,
6843 .coprocessor = 0x1,
6844 }, {
6845 .name = "add.s",
6846 .translate = translate_fpu2k_add_s,
6847 .coprocessor = 0x1,
6848 }, {
6849 .name = "ceil.s",
6850 .translate = translate_ftoi_s,
6851 .par = (const uint32_t[]){float_round_up, false},
6852 .coprocessor = 0x1,
6853 }, {
6854 .name = "float.s",
6855 .translate = translate_float_s,
6856 .par = (const uint32_t[]){false},
6857 .coprocessor = 0x1,
6858 }, {
6859 .name = "floor.s",
6860 .translate = translate_ftoi_s,
6861 .par = (const uint32_t[]){float_round_down, false},
6862 .coprocessor = 0x1,
6863 }, {
6864 .name = "lsi",
6865 .translate = translate_ldsti,
6866 .par = (const uint32_t[]){false, false},
6867 .op_flags = XTENSA_OP_LOAD,
6868 .coprocessor = 0x1,
6869 }, {
6870 .name = "lsiu",
6871 .translate = translate_ldsti,
6872 .par = (const uint32_t[]){false, true},
6873 .op_flags = XTENSA_OP_LOAD,
6874 .coprocessor = 0x1,
6875 }, {
6876 .name = "lsx",
6877 .translate = translate_ldstx,
6878 .par = (const uint32_t[]){false, false},
6879 .op_flags = XTENSA_OP_LOAD,
6880 .coprocessor = 0x1,
6881 }, {
6882 .name = "lsxu",
6883 .translate = translate_ldstx,
6884 .par = (const uint32_t[]){false, true},
6885 .op_flags = XTENSA_OP_LOAD,
6886 .coprocessor = 0x1,
6887 }, {
6888 .name = "madd.s",
6889 .translate = translate_fpu2k_madd_s,
6890 .coprocessor = 0x1,
6891 }, {
6892 .name = "mov.s",
6893 .translate = translate_mov_s,
6894 .coprocessor = 0x1,
6895 }, {
6896 .name = "moveqz.s",
6897 .translate = translate_movcond_s,
6898 .par = (const uint32_t[]){TCG_COND_EQ},
6899 .coprocessor = 0x1,
6900 }, {
6901 .name = "movf.s",
6902 .translate = translate_movp_s,
6903 .par = (const uint32_t[]){TCG_COND_EQ},
6904 .coprocessor = 0x1,
6905 }, {
6906 .name = "movgez.s",
6907 .translate = translate_movcond_s,
6908 .par = (const uint32_t[]){TCG_COND_GE},
6909 .coprocessor = 0x1,
6910 }, {
6911 .name = "movltz.s",
6912 .translate = translate_movcond_s,
6913 .par = (const uint32_t[]){TCG_COND_LT},
6914 .coprocessor = 0x1,
6915 }, {
6916 .name = "movnez.s",
6917 .translate = translate_movcond_s,
6918 .par = (const uint32_t[]){TCG_COND_NE},
6919 .coprocessor = 0x1,
6920 }, {
6921 .name = "movt.s",
6922 .translate = translate_movp_s,
6923 .par = (const uint32_t[]){TCG_COND_NE},
6924 .coprocessor = 0x1,
6925 }, {
6926 .name = "msub.s",
6927 .translate = translate_fpu2k_msub_s,
6928 .coprocessor = 0x1,
6929 }, {
6930 .name = "mul.s",
6931 .translate = translate_fpu2k_mul_s,
6932 .coprocessor = 0x1,
6933 }, {
6934 .name = "neg.s",
6935 .translate = translate_neg_s,
6936 .coprocessor = 0x1,
6937 }, {
6938 .name = "oeq.s",
6939 .translate = translate_compare_s,
6940 .par = (const uint32_t[]){COMPARE_OEQ},
6941 .coprocessor = 0x1,
6942 }, {
6943 .name = "ole.s",
6944 .translate = translate_compare_s,
6945 .par = (const uint32_t[]){COMPARE_OLE},
6946 .coprocessor = 0x1,
6947 }, {
6948 .name = "olt.s",
6949 .translate = translate_compare_s,
6950 .par = (const uint32_t[]){COMPARE_OLT},
6951 .coprocessor = 0x1,
6952 }, {
6953 .name = "rfr",
6954 .translate = translate_rfr_s,
6955 .coprocessor = 0x1,
6956 }, {
6957 .name = "round.s",
6958 .translate = translate_ftoi_s,
6959 .par = (const uint32_t[]){float_round_nearest_even, false},
6960 .coprocessor = 0x1,
6961 }, {
6962 .name = "rur.fcr",
6963 .translate = translate_rur,
6964 .par = (const uint32_t[]){FCR},
6965 .coprocessor = 0x1,
6966 }, {
6967 .name = "rur.fsr",
6968 .translate = translate_rur,
6969 .par = (const uint32_t[]){FSR},
6970 .coprocessor = 0x1,
6971 }, {
6972 .name = "ssi",
6973 .translate = translate_ldsti,
6974 .par = (const uint32_t[]){true, false},
6975 .op_flags = XTENSA_OP_STORE,
6976 .coprocessor = 0x1,
6977 }, {
6978 .name = "ssiu",
6979 .translate = translate_ldsti,
6980 .par = (const uint32_t[]){true, true},
6981 .op_flags = XTENSA_OP_STORE,
6982 .coprocessor = 0x1,
6983 }, {
6984 .name = "ssx",
6985 .translate = translate_ldstx,
6986 .par = (const uint32_t[]){true, false},
6987 .op_flags = XTENSA_OP_STORE,
6988 .coprocessor = 0x1,
6989 }, {
6990 .name = "ssxu",
6991 .translate = translate_ldstx,
6992 .par = (const uint32_t[]){true, true},
6993 .op_flags = XTENSA_OP_STORE,
6994 .coprocessor = 0x1,
6995 }, {
6996 .name = "sub.s",
6997 .translate = translate_fpu2k_sub_s,
6998 .coprocessor = 0x1,
6999 }, {
7000 .name = "trunc.s",
7001 .translate = translate_ftoi_s,
7002 .par = (const uint32_t[]){float_round_to_zero, false},
7003 .coprocessor = 0x1,
7004 }, {
7005 .name = "ueq.s",
7006 .translate = translate_compare_s,
7007 .par = (const uint32_t[]){COMPARE_UEQ},
7008 .coprocessor = 0x1,
7009 }, {
7010 .name = "ufloat.s",
7011 .translate = translate_float_s,
7012 .par = (const uint32_t[]){true},
7013 .coprocessor = 0x1,
7014 }, {
7015 .name = "ule.s",
7016 .translate = translate_compare_s,
7017 .par = (const uint32_t[]){COMPARE_ULE},
7018 .coprocessor = 0x1,
7019 }, {
7020 .name = "ult.s",
7021 .translate = translate_compare_s,
7022 .par = (const uint32_t[]){COMPARE_ULT},
7023 .coprocessor = 0x1,
7024 }, {
7025 .name = "un.s",
7026 .translate = translate_compare_s,
7027 .par = (const uint32_t[]){COMPARE_UN},
7028 .coprocessor = 0x1,
7029 }, {
7030 .name = "utrunc.s",
7031 .translate = translate_ftoi_s,
7032 .par = (const uint32_t[]){float_round_to_zero, true},
7033 .coprocessor = 0x1,
7034 }, {
7035 .name = "wfr",
7036 .translate = translate_wfr_s,
7037 .coprocessor = 0x1,
7038 }, {
7039 .name = "wur.fcr",
7040 .translate = translate_wur_fpu2k_fcr,
7041 .par = (const uint32_t[]){FCR},
7042 .coprocessor = 0x1,
7043 }, {
7044 .name = "wur.fsr",
7045 .translate = translate_wur_fpu2k_fsr,
7046 .par = (const uint32_t[]){FSR},
7047 .coprocessor = 0x1,
7048 },
7049 };
7050
7051 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = {
7052 .num_opcodes = ARRAY_SIZE(fpu2000_ops),
7053 .opcode = fpu2000_ops,
7054 };
7055
7056 static void translate_add_d(DisasContext *dc, const OpcodeArg arg[],
7057 const uint32_t par[])
7058 {
7059 gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
7060 }
7061
7062 static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
7063 const uint32_t par[])
7064 {
7065 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7066 gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
7067 arg[1].in, arg[2].in);
7068 } else {
7069 OpcodeArg arg32[3];
7070
7071 get_f32_o1_i2(arg, arg32, 0, 1, 2);
7072 gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
7073 put_f32_o1_i2(arg, arg32, 0, 1, 2);
7074 }
7075 }
7076
7077 static void translate_cvtd_s(DisasContext *dc, const OpcodeArg arg[],
7078 const uint32_t par[])
7079 {
7080 TCGv_i32 v = tcg_temp_new_i32();
7081
7082 tcg_gen_extrl_i64_i32(v, arg[1].in);
7083 gen_helper_cvtd_s(arg[0].out, cpu_env, v);
7084 tcg_temp_free_i32(v);
7085 }
7086
7087 static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
7088 const uint32_t par[])
7089 {
7090 TCGv_i32 v = tcg_temp_new_i32();
7091
7092 gen_helper_cvts_d(v, cpu_env, arg[1].in);
7093 tcg_gen_extu_i32_i64(arg[0].out, v);
7094 tcg_temp_free_i32(v);
7095 }
7096
7097 static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[],
7098 const uint32_t par[])
7099 {
7100 TCGv_i32 addr;
7101 MemOp mop;
7102
7103 if (par[1]) {
7104 addr = tcg_temp_new_i32();
7105 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
7106 } else {
7107 addr = arg[1].in;
7108 }
7109 mop = gen_load_store_alignment(dc, MO_TEQ, addr);
7110 if (par[0]) {
7111 tcg_gen_qemu_st_i64(arg[0].in, addr, dc->cring, mop);
7112 } else {
7113 tcg_gen_qemu_ld_i64(arg[0].out, addr, dc->cring, mop);
7114 }
7115 if (par[2]) {
7116 if (par[1]) {
7117 tcg_gen_mov_i32(arg[1].out, addr);
7118 } else {
7119 tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm);
7120 }
7121 }
7122 if (par[1]) {
7123 tcg_temp_free(addr);
7124 }
7125 }
7126
7127 static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[],
7128 const uint32_t par[])
7129 {
7130 TCGv_i32 addr;
7131 OpcodeArg arg32[1];
7132 MemOp mop;
7133
7134 if (par[1]) {
7135 addr = tcg_temp_new_i32();
7136 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
7137 } else {
7138 addr = arg[1].in;
7139 }
7140 mop = gen_load_store_alignment(dc, MO_TEUL, addr);
7141 if (par[0]) {
7142 get_f32_i1(arg, arg32, 0);
7143 tcg_gen_qemu_st_tl(arg32[0].in, addr, dc->cring, mop);
7144 put_f32_i1(arg, arg32, 0);
7145 } else {
7146 get_f32_o1(arg, arg32, 0);
7147 tcg_gen_qemu_ld_tl(arg32[0].out, addr, dc->cring, mop);
7148 put_f32_o1(arg, arg32, 0);
7149 }
7150 if (par[2]) {
7151 if (par[1]) {
7152 tcg_gen_mov_i32(arg[1].out, addr);
7153 } else {
7154 tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm);
7155 }
7156 }
7157 if (par[1]) {
7158 tcg_temp_free(addr);
7159 }
7160 }
7161
7162 static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[],
7163 const uint32_t par[])
7164 {
7165 TCGv_i32 addr;
7166 MemOp mop;
7167
7168 if (par[1]) {
7169 addr = tcg_temp_new_i32();
7170 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
7171 } else {
7172 addr = arg[1].in;
7173 }
7174 mop = gen_load_store_alignment(dc, MO_TEQ, addr);
7175 if (par[0]) {
7176 tcg_gen_qemu_st_i64(arg[0].in, addr, dc->cring, mop);
7177 } else {
7178 tcg_gen_qemu_ld_i64(arg[0].out, addr, dc->cring, mop);
7179 }
7180 if (par[2]) {
7181 if (par[1]) {
7182 tcg_gen_mov_i32(arg[1].out, addr);
7183 } else {
7184 tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in);
7185 }
7186 }
7187 if (par[1]) {
7188 tcg_temp_free(addr);
7189 }
7190 }
7191
7192 static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[],
7193 const uint32_t par[])
7194 {
7195 TCGv_i32 addr;
7196 OpcodeArg arg32[1];
7197 MemOp mop;
7198
7199 if (par[1]) {
7200 addr = tcg_temp_new_i32();
7201 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
7202 } else {
7203 addr = arg[1].in;
7204 }
7205 mop = gen_load_store_alignment(dc, MO_TEUL, addr);
7206 if (par[0]) {
7207 get_f32_i1(arg, arg32, 0);
7208 tcg_gen_qemu_st_tl(arg32[0].in, addr, dc->cring, mop);
7209 put_f32_i1(arg, arg32, 0);
7210 } else {
7211 get_f32_o1(arg, arg32, 0);
7212 tcg_gen_qemu_ld_tl(arg32[0].out, addr, dc->cring, mop);
7213 put_f32_o1(arg, arg32, 0);
7214 }
7215 if (par[2]) {
7216 if (par[1]) {
7217 tcg_gen_mov_i32(arg[1].out, addr);
7218 } else {
7219 tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in);
7220 }
7221 }
7222 if (par[1]) {
7223 tcg_temp_free(addr);
7224 }
7225 }
7226
7227 static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[],
7228 const uint32_t par[])
7229 {
7230 gen_helper_madd_d(arg[0].out, cpu_env,
7231 arg[0].in, arg[1].in, arg[2].in);
7232 }
7233
7234 static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],
7235 const uint32_t par[])
7236 {
7237 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7238 gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
7239 arg[0].in, arg[1].in, arg[2].in);
7240 } else {
7241 OpcodeArg arg32[3];
7242
7243 get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7244 gen_helper_madd_s(arg32[0].out, cpu_env,
7245 arg32[0].in, arg32[1].in, arg32[2].in);
7246 put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7247 }
7248 }
7249
7250 static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[],
7251 const uint32_t par[])
7252 {
7253 gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
7254 }
7255
7256 static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
7257 const uint32_t par[])
7258 {
7259 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7260 gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
7261 arg[1].in, arg[2].in);
7262 } else {
7263 OpcodeArg arg32[3];
7264
7265 get_f32_o1_i2(arg, arg32, 0, 1, 2);
7266 gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
7267 put_f32_o1_i2(arg, arg32, 0, 1, 2);
7268 }
7269 }
7270
7271 static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[],
7272 const uint32_t par[])
7273 {
7274 gen_helper_msub_d(arg[0].out, cpu_env,
7275 arg[0].in, arg[1].in, arg[2].in);
7276 }
7277
7278 static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],
7279 const uint32_t par[])
7280 {
7281 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7282 gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
7283 arg[0].in, arg[1].in, arg[2].in);
7284 } else {
7285 OpcodeArg arg32[3];
7286
7287 get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7288 gen_helper_msub_s(arg32[0].out, cpu_env,
7289 arg32[0].in, arg32[1].in, arg32[2].in);
7290 put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7291 }
7292 }
7293
7294 static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[],
7295 const uint32_t par[])
7296 {
7297 gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
7298 }
7299
7300 static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
7301 const uint32_t par[])
7302 {
7303 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7304 gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
7305 arg[1].in, arg[2].in);
7306 } else {
7307 OpcodeArg arg32[3];
7308
7309 get_f32_o1_i2(arg, arg32, 0, 1, 2);
7310 gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
7311 put_f32_o1_i2(arg, arg32, 0, 1, 2);
7312 }
7313 }
7314
7315 static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
7316 const uint32_t par[])
7317 {
7318 gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in);
7319 }
7320
7321 static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
7322 const uint32_t par[])
7323 {
7324 OpcodeArg arg32[2];
7325
7326 get_f32_o1_i2(arg, arg32, 0, 0, 1);
7327 gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in);
7328 put_f32_o1_i2(arg, arg32, 0, 0, 1);
7329 }
7330
7331 static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
7332 const uint32_t par[])
7333 {
7334 gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in);
7335 }
7336
7337 static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
7338 const uint32_t par[])
7339 {
7340 OpcodeArg arg32[2];
7341
7342 get_f32_o1_i1(arg, arg32, 0, 1);
7343 gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in);
7344 put_f32_o1_i1(arg, arg32, 0, 1);
7345 }
7346
7347 static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
7348 const uint32_t par[])
7349 {
7350 gen_helper_wur_fpu_fcr(cpu_env, arg[0].in);
7351 }
7352
7353 static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
7354 const uint32_t par[])
7355 {
7356 gen_helper_rur_fpu_fsr(arg[0].out, cpu_env);
7357 }
7358
7359 static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
7360 const uint32_t par[])
7361 {
7362 gen_helper_wur_fpu_fsr(cpu_env, arg[0].in);
7363 }
7364
7365 static const XtensaOpcodeOps fpu_ops[] = {
7366 {
7367 .name = "abs.d",
7368 .translate = translate_abs_d,
7369 .coprocessor = 0x1,
7370 }, {
7371 .name = "abs.s",
7372 .translate = translate_abs_s,
7373 .coprocessor = 0x1,
7374 }, {
7375 .name = "add.d",
7376 .translate = translate_add_d,
7377 .coprocessor = 0x1,
7378 }, {
7379 .name = "add.s",
7380 .translate = translate_add_s,
7381 .coprocessor = 0x1,
7382 }, {
7383 .name = "addexp.d",
7384 .translate = translate_nop,
7385 .coprocessor = 0x1,
7386 }, {
7387 .name = "addexp.s",
7388 .translate = translate_nop,
7389 .coprocessor = 0x1,
7390 }, {
7391 .name = "addexpm.d",
7392 .translate = translate_mov_s,
7393 .coprocessor = 0x1,
7394 }, {
7395 .name = "addexpm.s",
7396 .translate = translate_mov_s,
7397 .coprocessor = 0x1,
7398 }, {
7399 .name = "ceil.d",
7400 .translate = translate_ftoi_d,
7401 .par = (const uint32_t[]){float_round_up, false},
7402 .coprocessor = 0x1,
7403 }, {
7404 .name = "ceil.s",
7405 .translate = translate_ftoi_s,
7406 .par = (const uint32_t[]){float_round_up, false},
7407 .coprocessor = 0x1,
7408 }, {
7409 .name = "const.d",
7410 .translate = translate_const_d,
7411 .coprocessor = 0x1,
7412 }, {
7413 .name = "const.s",
7414 .translate = translate_const_s,
7415 .coprocessor = 0x1,
7416 }, {
7417 .name = "cvtd.s",
7418 .translate = translate_cvtd_s,
7419 .coprocessor = 0x1,
7420 }, {
7421 .name = "cvts.d",
7422 .translate = translate_cvts_d,
7423 .coprocessor = 0x1,
7424 }, {
7425 .name = "div0.d",
7426 .translate = translate_nop,
7427 .coprocessor = 0x1,
7428 }, {
7429 .name = "div0.s",
7430 .translate = translate_nop,
7431 .coprocessor = 0x1,
7432 }, {
7433 .name = "divn.d",
7434 .translate = translate_nop,
7435 .coprocessor = 0x1,
7436 }, {
7437 .name = "divn.s",
7438 .translate = translate_nop,
7439 .coprocessor = 0x1,
7440 }, {
7441 .name = "float.d",
7442 .translate = translate_float_d,
7443 .par = (const uint32_t[]){false},
7444 .coprocessor = 0x1,
7445 }, {
7446 .name = "float.s",
7447 .translate = translate_float_s,
7448 .par = (const uint32_t[]){false},
7449 .coprocessor = 0x1,
7450 }, {
7451 .name = "floor.d",
7452 .translate = translate_ftoi_d,
7453 .par = (const uint32_t[]){float_round_down, false},
7454 .coprocessor = 0x1,
7455 }, {
7456 .name = "floor.s",
7457 .translate = translate_ftoi_s,
7458 .par = (const uint32_t[]){float_round_down, false},
7459 .coprocessor = 0x1,
7460 }, {
7461 .name = "ldi",
7462 .translate = translate_ldsti_d,
7463 .par = (const uint32_t[]){false, true, false},
7464 .op_flags = XTENSA_OP_LOAD,
7465 .coprocessor = 0x1,
7466 }, {
7467 .name = "ldip",
7468 .translate = translate_ldsti_d,
7469 .par = (const uint32_t[]){false, false, true},
7470 .op_flags = XTENSA_OP_LOAD,
7471 .coprocessor = 0x1,
7472 }, {
7473 .name = "ldiu",
7474 .translate = translate_ldsti_d,
7475 .par = (const uint32_t[]){false, true, true},
7476 .op_flags = XTENSA_OP_LOAD,
7477 .coprocessor = 0x1,
7478 }, {
7479 .name = "ldx",
7480 .translate = translate_ldstx_d,
7481 .par = (const uint32_t[]){false, true, false},
7482 .op_flags = XTENSA_OP_LOAD,
7483 .coprocessor = 0x1,
7484 }, {
7485 .name = "ldxp",
7486 .translate = translate_ldstx_d,
7487 .par = (const uint32_t[]){false, false, true},
7488 .op_flags = XTENSA_OP_LOAD,
7489 .coprocessor = 0x1,
7490 }, {
7491 .name = "ldxu",
7492 .translate = translate_ldstx_d,
7493 .par = (const uint32_t[]){false, true, true},
7494 .op_flags = XTENSA_OP_LOAD,
7495 .coprocessor = 0x1,
7496 }, {
7497 .name = "lsi",
7498 .translate = translate_ldsti_s,
7499 .par = (const uint32_t[]){false, true, false},
7500 .op_flags = XTENSA_OP_LOAD,
7501 .coprocessor = 0x1,
7502 }, {
7503 .name = "lsip",
7504 .translate = translate_ldsti_s,
7505 .par = (const uint32_t[]){false, false, true},
7506 .op_flags = XTENSA_OP_LOAD,
7507 .coprocessor = 0x1,
7508 }, {
7509 .name = "lsiu",
7510 .translate = translate_ldsti_s,
7511 .par = (const uint32_t[]){false, true, true},
7512 .op_flags = XTENSA_OP_LOAD,
7513 .coprocessor = 0x1,
7514 }, {
7515 .name = "lsx",
7516 .translate = translate_ldstx_s,
7517 .par = (const uint32_t[]){false, true, false},
7518 .op_flags = XTENSA_OP_LOAD,
7519 .coprocessor = 0x1,
7520 }, {
7521 .name = "lsxp",
7522 .translate = translate_ldstx_s,
7523 .par = (const uint32_t[]){false, false, true},
7524 .op_flags = XTENSA_OP_LOAD,
7525 .coprocessor = 0x1,
7526 }, {
7527 .name = "lsxu",
7528 .translate = translate_ldstx_s,
7529 .par = (const uint32_t[]){false, true, true},
7530 .op_flags = XTENSA_OP_LOAD,
7531 .coprocessor = 0x1,
7532 }, {
7533 .name = "madd.d",
7534 .translate = translate_madd_d,
7535 .coprocessor = 0x1,
7536 }, {
7537 .name = "madd.s",
7538 .translate = translate_madd_s,
7539 .coprocessor = 0x1,
7540 }, {
7541 .name = "maddn.d",
7542 .translate = translate_nop,
7543 .coprocessor = 0x1,
7544 }, {
7545 .name = "maddn.s",
7546 .translate = translate_nop,
7547 .coprocessor = 0x1,
7548 }, {
7549 .name = "mkdadj.d",
7550 .translate = translate_mkdadj_d,
7551 .coprocessor = 0x1,
7552 }, {
7553 .name = "mkdadj.s",
7554 .translate = translate_mkdadj_s,
7555 .coprocessor = 0x1,
7556 }, {
7557 .name = "mksadj.d",
7558 .translate = translate_mksadj_d,
7559 .coprocessor = 0x1,
7560 }, {
7561 .name = "mksadj.s",
7562 .translate = translate_mksadj_s,
7563 .coprocessor = 0x1,
7564 }, {
7565 .name = "mov.d",
7566 .translate = translate_mov_d,
7567 .coprocessor = 0x1,
7568 }, {
7569 .name = "mov.s",
7570 .translate = translate_mov_s,
7571 .coprocessor = 0x1,
7572 }, {
7573 .name = "moveqz.d",
7574 .translate = translate_movcond_d,
7575 .par = (const uint32_t[]){TCG_COND_EQ},
7576 .coprocessor = 0x1,
7577 }, {
7578 .name = "moveqz.s",
7579 .translate = translate_movcond_s,
7580 .par = (const uint32_t[]){TCG_COND_EQ},
7581 .coprocessor = 0x1,
7582 }, {
7583 .name = "movf.d",
7584 .translate = translate_movp_d,
7585 .par = (const uint32_t[]){TCG_COND_EQ},
7586 .coprocessor = 0x1,
7587 }, {
7588 .name = "movf.s",
7589 .translate = translate_movp_s,
7590 .par = (const uint32_t[]){TCG_COND_EQ},
7591 .coprocessor = 0x1,
7592 }, {
7593 .name = "movgez.d",
7594 .translate = translate_movcond_d,
7595 .par = (const uint32_t[]){TCG_COND_GE},
7596 .coprocessor = 0x1,
7597 }, {
7598 .name = "movgez.s",
7599 .translate = translate_movcond_s,
7600 .par = (const uint32_t[]){TCG_COND_GE},
7601 .coprocessor = 0x1,
7602 }, {
7603 .name = "movltz.d",
7604 .translate = translate_movcond_d,
7605 .par = (const uint32_t[]){TCG_COND_LT},
7606 .coprocessor = 0x1,
7607 }, {
7608 .name = "movltz.s",
7609 .translate = translate_movcond_s,
7610 .par = (const uint32_t[]){TCG_COND_LT},
7611 .coprocessor = 0x1,
7612 }, {
7613 .name = "movnez.d",
7614 .translate = translate_movcond_d,
7615 .par = (const uint32_t[]){TCG_COND_NE},
7616 .coprocessor = 0x1,
7617 }, {
7618 .name = "movnez.s",
7619 .translate = translate_movcond_s,
7620 .par = (const uint32_t[]){TCG_COND_NE},
7621 .coprocessor = 0x1,
7622 }, {
7623 .name = "movt.d",
7624 .translate = translate_movp_d,
7625 .par = (const uint32_t[]){TCG_COND_NE},
7626 .coprocessor = 0x1,
7627 }, {
7628 .name = "movt.s",
7629 .translate = translate_movp_s,
7630 .par = (const uint32_t[]){TCG_COND_NE},
7631 .coprocessor = 0x1,
7632 }, {
7633 .name = "msub.d",
7634 .translate = translate_msub_d,
7635 .coprocessor = 0x1,
7636 }, {
7637 .name = "msub.s",
7638 .translate = translate_msub_s,
7639 .coprocessor = 0x1,
7640 }, {
7641 .name = "mul.d",
7642 .translate = translate_mul_d,
7643 .coprocessor = 0x1,
7644 }, {
7645 .name = "mul.s",
7646 .translate = translate_mul_s,
7647 .coprocessor = 0x1,
7648 }, {
7649 .name = "neg.d",
7650 .translate = translate_neg_d,
7651 .coprocessor = 0x1,
7652 }, {
7653 .name = "neg.s",
7654 .translate = translate_neg_s,
7655 .coprocessor = 0x1,
7656 }, {
7657 .name = "nexp01.d",
7658 .translate = translate_nop,
7659 .coprocessor = 0x1,
7660 }, {
7661 .name = "nexp01.s",
7662 .translate = translate_nop,
7663 .coprocessor = 0x1,
7664 }, {
7665 .name = "oeq.d",
7666 .translate = translate_compare_d,
7667 .par = (const uint32_t[]){COMPARE_OEQ},
7668 .coprocessor = 0x1,
7669 }, {
7670 .name = "oeq.s",
7671 .translate = translate_compare_s,
7672 .par = (const uint32_t[]){COMPARE_OEQ},
7673 .coprocessor = 0x1,
7674 }, {
7675 .name = "ole.d",
7676 .translate = translate_compare_d,
7677 .par = (const uint32_t[]){COMPARE_OLE},
7678 .coprocessor = 0x1,
7679 }, {
7680 .name = "ole.s",
7681 .translate = translate_compare_s,
7682 .par = (const uint32_t[]){COMPARE_OLE},
7683 .coprocessor = 0x1,
7684 }, {
7685 .name = "olt.d",
7686 .translate = translate_compare_d,
7687 .par = (const uint32_t[]){COMPARE_OLT},
7688 .coprocessor = 0x1,
7689 }, {
7690 .name = "olt.s",
7691 .translate = translate_compare_s,
7692 .par = (const uint32_t[]){COMPARE_OLT},
7693 .coprocessor = 0x1,
7694 }, {
7695 .name = "rfr",
7696 .translate = translate_rfr_s,
7697 .coprocessor = 0x1,
7698 }, {
7699 .name = "rfrd",
7700 .translate = translate_rfr_d,
7701 .coprocessor = 0x1,
7702 }, {
7703 .name = "round.d",
7704 .translate = translate_ftoi_d,
7705 .par = (const uint32_t[]){float_round_nearest_even, false},
7706 .coprocessor = 0x1,
7707 }, {
7708 .name = "round.s",
7709 .translate = translate_ftoi_s,
7710 .par = (const uint32_t[]){float_round_nearest_even, false},
7711 .coprocessor = 0x1,
7712 }, {
7713 .name = "rur.fcr",
7714 .translate = translate_rur,
7715 .par = (const uint32_t[]){FCR},
7716 .coprocessor = 0x1,
7717 }, {
7718 .name = "rur.fsr",
7719 .translate = translate_rur_fpu_fsr,
7720 .coprocessor = 0x1,
7721 }, {
7722 .name = "sdi",
7723 .translate = translate_ldsti_d,
7724 .par = (const uint32_t[]){true, true, false},
7725 .op_flags = XTENSA_OP_STORE,
7726 .coprocessor = 0x1,
7727 }, {
7728 .name = "sdip",
7729 .translate = translate_ldsti_d,
7730 .par = (const uint32_t[]){true, false, true},
7731 .op_flags = XTENSA_OP_STORE,
7732 .coprocessor = 0x1,
7733 }, {
7734 .name = "sdiu",
7735 .translate = translate_ldsti_d,
7736 .par = (const uint32_t[]){true, true, true},
7737 .op_flags = XTENSA_OP_STORE,
7738 .coprocessor = 0x1,
7739 }, {
7740 .name = "sdx",
7741 .translate = translate_ldstx_d,
7742 .par = (const uint32_t[]){true, true, false},
7743 .op_flags = XTENSA_OP_STORE,
7744 .coprocessor = 0x1,
7745 }, {
7746 .name = "sdxp",
7747 .translate = translate_ldstx_d,
7748 .par = (const uint32_t[]){true, false, true},
7749 .op_flags = XTENSA_OP_STORE,
7750 .coprocessor = 0x1,
7751 }, {
7752 .name = "sdxu",
7753 .translate = translate_ldstx_d,
7754 .par = (const uint32_t[]){true, true, true},
7755 .op_flags = XTENSA_OP_STORE,
7756 .coprocessor = 0x1,
7757 }, {
7758 .name = "sqrt0.d",
7759 .translate = translate_nop,
7760 .coprocessor = 0x1,
7761 }, {
7762 .name = "sqrt0.s",
7763 .translate = translate_nop,
7764 .coprocessor = 0x1,
7765 }, {
7766 .name = "ssi",
7767 .translate = translate_ldsti_s,
7768 .par = (const uint32_t[]){true, true, false},
7769 .op_flags = XTENSA_OP_STORE,
7770 .coprocessor = 0x1,
7771 }, {
7772 .name = "ssip",
7773 .translate = translate_ldsti_s,
7774 .par = (const uint32_t[]){true, false, true},
7775 .op_flags = XTENSA_OP_STORE,
7776 .coprocessor = 0x1,
7777 }, {
7778 .name = "ssiu",
7779 .translate = translate_ldsti_s,
7780 .par = (const uint32_t[]){true, true, true},
7781 .op_flags = XTENSA_OP_STORE,
7782 .coprocessor = 0x1,
7783 }, {
7784 .name = "ssx",
7785 .translate = translate_ldstx_s,
7786 .par = (const uint32_t[]){true, true, false},
7787 .op_flags = XTENSA_OP_STORE,
7788 .coprocessor = 0x1,
7789 }, {
7790 .name = "ssxp",
7791 .translate = translate_ldstx_s,
7792 .par = (const uint32_t[]){true, false, true},
7793 .op_flags = XTENSA_OP_STORE,
7794 .coprocessor = 0x1,
7795 }, {
7796 .name = "ssxu",
7797 .translate = translate_ldstx_s,
7798 .par = (const uint32_t[]){true, true, true},
7799 .op_flags = XTENSA_OP_STORE,
7800 .coprocessor = 0x1,
7801 }, {
7802 .name = "sub.d",
7803 .translate = translate_sub_d,
7804 .coprocessor = 0x1,
7805 }, {
7806 .name = "sub.s",
7807 .translate = translate_sub_s,
7808 .coprocessor = 0x1,
7809 }, {
7810 .name = "trunc.d",
7811 .translate = translate_ftoi_d,
7812 .par = (const uint32_t[]){float_round_to_zero, false},
7813 .coprocessor = 0x1,
7814 }, {
7815 .name = "trunc.s",
7816 .translate = translate_ftoi_s,
7817 .par = (const uint32_t[]){float_round_to_zero, false},
7818 .coprocessor = 0x1,
7819 }, {
7820 .name = "ueq.d",
7821 .translate = translate_compare_d,
7822 .par = (const uint32_t[]){COMPARE_UEQ},
7823 .coprocessor = 0x1,
7824 }, {
7825 .name = "ueq.s",
7826 .translate = translate_compare_s,
7827 .par = (const uint32_t[]){COMPARE_UEQ},
7828 .coprocessor = 0x1,
7829 }, {
7830 .name = "ufloat.d",
7831 .translate = translate_float_d,
7832 .par = (const uint32_t[]){true},
7833 .coprocessor = 0x1,
7834 }, {
7835 .name = "ufloat.s",
7836 .translate = translate_float_s,
7837 .par = (const uint32_t[]){true},
7838 .coprocessor = 0x1,
7839 }, {
7840 .name = "ule.d",
7841 .translate = translate_compare_d,
7842 .par = (const uint32_t[]){COMPARE_ULE},
7843 .coprocessor = 0x1,
7844 }, {
7845 .name = "ule.s",
7846 .translate = translate_compare_s,
7847 .par = (const uint32_t[]){COMPARE_ULE},
7848 .coprocessor = 0x1,
7849 }, {
7850 .name = "ult.d",
7851 .translate = translate_compare_d,
7852 .par = (const uint32_t[]){COMPARE_ULT},
7853 .coprocessor = 0x1,
7854 }, {
7855 .name = "ult.s",
7856 .translate = translate_compare_s,
7857 .par = (const uint32_t[]){COMPARE_ULT},
7858 .coprocessor = 0x1,
7859 }, {
7860 .name = "un.d",
7861 .translate = translate_compare_d,
7862 .par = (const uint32_t[]){COMPARE_UN},
7863 .coprocessor = 0x1,
7864 }, {
7865 .name = "un.s",
7866 .translate = translate_compare_s,
7867 .par = (const uint32_t[]){COMPARE_UN},
7868 .coprocessor = 0x1,
7869 }, {
7870 .name = "utrunc.d",
7871 .translate = translate_ftoi_d,
7872 .par = (const uint32_t[]){float_round_to_zero, true},
7873 .coprocessor = 0x1,
7874 }, {
7875 .name = "utrunc.s",
7876 .translate = translate_ftoi_s,
7877 .par = (const uint32_t[]){float_round_to_zero, true},
7878 .coprocessor = 0x1,
7879 }, {
7880 .name = "wfr",
7881 .translate = translate_wfr_s,
7882 .coprocessor = 0x1,
7883 }, {
7884 .name = "wfrd",
7885 .translate = translate_wfr_d,
7886 .coprocessor = 0x1,
7887 }, {
7888 .name = "wur.fcr",
7889 .translate = translate_wur_fpu_fcr,
7890 .par = (const uint32_t[]){FCR},
7891 .coprocessor = 0x1,
7892 }, {
7893 .name = "wur.fsr",
7894 .translate = translate_wur_fpu_fsr,
7895 .coprocessor = 0x1,
7896 },
7897 };
7898
7899 const XtensaOpcodeTranslators xtensa_fpu_opcodes = {
7900 .num_opcodes = ARRAY_SIZE(fpu_ops),
7901 .opcode = fpu_ops,
7902 };
AR7 emulation for QEMU