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tcg: Avoid including 'trace-tcg.h' in target translate.c
[qemu/ar7.git] / target / m68k / translate.c
blob348fc6e844e93c1c19a3c7b39c27dd23312486d0
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "qemu/log.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "exec/log.h"
35 #include "fpu/softfloat.h"
36
37
38 //#define DEBUG_DISPATCH 1
39
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
42 #include "qregs.def"
43 #undef DEFO32
44 #undef DEFO64
45
46 static TCGv_i32 cpu_halted;
47 static TCGv_i32 cpu_exception_index;
48
49 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs[8];
51 static TCGv cpu_aregs[8];
52 static TCGv_i64 cpu_macc[4];
53
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
59
60 static TCGv NULL_QREG;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy;
64
65 #include "exec/gen-icount.h"
66
67 void m68k_tcg_init(void)
68 {
69 char *p;
70 int i;
71
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
78 #include "qregs.def"
79 #undef DEFO32
80 #undef DEFO64
81
82 cpu_halted = tcg_global_mem_new_i32(cpu_env,
83 -offsetof(M68kCPU, env) +
84 offsetof(CPUState, halted), "HALTED");
85 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
86 -offsetof(M68kCPU, env) +
87 offsetof(CPUState, exception_index),
88 "EXCEPTION");
89
90 p = cpu_reg_names;
91 for (i = 0; i < 8; i++) {
92 sprintf(p, "D%d", i);
93 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
94 offsetof(CPUM68KState, dregs[i]), p);
95 p += 3;
96 sprintf(p, "A%d", i);
97 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
98 offsetof(CPUM68KState, aregs[i]), p);
99 p += 3;
100 }
101 for (i = 0; i < 4; i++) {
102 sprintf(p, "ACC%d", i);
103 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
104 offsetof(CPUM68KState, macc[i]), p);
105 p += 5;
106 }
107
108 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
109 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
110 }
111
112 /* internal defines */
113 typedef struct DisasContext {
114 DisasContextBase base;
115 CPUM68KState *env;
116 target_ulong pc;
117 CCOp cc_op; /* Current CC operation */
118 int cc_op_synced;
119 TCGv_i64 mactmp;
120 int done_mac;
121 int writeback_mask;
122 TCGv writeback[8];
123 #define MAX_TO_RELEASE 8
124 int release_count;
125 TCGv release[MAX_TO_RELEASE];
126 bool ss_active;
127 } DisasContext;
128
129 static void init_release_array(DisasContext *s)
130 {
131 #ifdef CONFIG_DEBUG_TCG
132 memset(s->release, 0, sizeof(s->release));
133 #endif
134 s->release_count = 0;
135 }
136
137 static void do_release(DisasContext *s)
138 {
139 int i;
140 for (i = 0; i < s->release_count; i++) {
141 tcg_temp_free(s->release[i]);
142 }
143 init_release_array(s);
144 }
145
146 static TCGv mark_to_release(DisasContext *s, TCGv tmp)
147 {
148 g_assert(s->release_count < MAX_TO_RELEASE);
149 return s->release[s->release_count++] = tmp;
150 }
151
152 static TCGv get_areg(DisasContext *s, unsigned regno)
153 {
154 if (s->writeback_mask & (1 << regno)) {
155 return s->writeback[regno];
156 } else {
157 return cpu_aregs[regno];
158 }
159 }
160
161 static void delay_set_areg(DisasContext *s, unsigned regno,
162 TCGv val, bool give_temp)
163 {
164 if (s->writeback_mask & (1 << regno)) {
165 if (give_temp) {
166 tcg_temp_free(s->writeback[regno]);
167 s->writeback[regno] = val;
168 } else {
169 tcg_gen_mov_i32(s->writeback[regno], val);
170 }
171 } else {
172 s->writeback_mask |= 1 << regno;
173 if (give_temp) {
174 s->writeback[regno] = val;
175 } else {
176 TCGv tmp = tcg_temp_new();
177 s->writeback[regno] = tmp;
178 tcg_gen_mov_i32(tmp, val);
179 }
180 }
181 }
182
183 static void do_writebacks(DisasContext *s)
184 {
185 unsigned mask = s->writeback_mask;
186 if (mask) {
187 s->writeback_mask = 0;
188 do {
189 unsigned regno = ctz32(mask);
190 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
191 tcg_temp_free(s->writeback[regno]);
192 mask &= mask - 1;
193 } while (mask);
194 }
195 }
196
197 static bool is_singlestepping(DisasContext *s)
198 {
199 /*
200 * Return true if we are singlestepping either because of
201 * architectural singlestep or QEMU gdbstub singlestep. This does
202 * not include the command line '-singlestep' mode which is rather
203 * misnamed as it only means "one instruction per TB" and doesn't
204 * affect the code we generate.
205 */
206 return s->base.singlestep_enabled || s->ss_active;
207 }
208
209 /* is_jmp field values */
210 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
211 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
212
213 #if defined(CONFIG_USER_ONLY)
214 #define IS_USER(s) 1
215 #else
216 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
217 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
218 MMU_KERNEL_IDX : MMU_USER_IDX)
219 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
220 MMU_KERNEL_IDX : MMU_USER_IDX)
221 #endif
222
223 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
224
225 #ifdef DEBUG_DISPATCH
226 #define DISAS_INSN(name) \
227 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
228 uint16_t insn); \
229 static void disas_##name(CPUM68KState *env, DisasContext *s, \
230 uint16_t insn) \
231 { \
232 qemu_log("Dispatch " #name "\n"); \
233 real_disas_##name(env, s, insn); \
234 } \
235 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
236 uint16_t insn)
237 #else
238 #define DISAS_INSN(name) \
239 static void disas_##name(CPUM68KState *env, DisasContext *s, \
240 uint16_t insn)
241 #endif
242
243 static const uint8_t cc_op_live[CC_OP_NB] = {
244 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
245 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
246 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
247 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
248 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
249 [CC_OP_LOGIC] = CCF_X | CCF_N
250 };
251
252 static void set_cc_op(DisasContext *s, CCOp op)
253 {
254 CCOp old_op = s->cc_op;
255 int dead;
256
257 if (old_op == op) {
258 return;
259 }
260 s->cc_op = op;
261 s->cc_op_synced = 0;
262
263 /*
264 * Discard CC computation that will no longer be used.
265 * Note that X and N are never dead.
266 */
267 dead = cc_op_live[old_op] & ~cc_op_live[op];
268 if (dead & CCF_C) {
269 tcg_gen_discard_i32(QREG_CC_C);
270 }
271 if (dead & CCF_Z) {
272 tcg_gen_discard_i32(QREG_CC_Z);
273 }
274 if (dead & CCF_V) {
275 tcg_gen_discard_i32(QREG_CC_V);
276 }
277 }
278
279 /* Update the CPU env CC_OP state. */
280 static void update_cc_op(DisasContext *s)
281 {
282 if (!s->cc_op_synced) {
283 s->cc_op_synced = 1;
284 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
285 }
286 }
287
288 /* Generate a jump to an immediate address. */
289 static void gen_jmp_im(DisasContext *s, uint32_t dest)
290 {
291 update_cc_op(s);
292 tcg_gen_movi_i32(QREG_PC, dest);
293 s->base.is_jmp = DISAS_JUMP;
294 }
295
296 /* Generate a jump to the address in qreg DEST. */
297 static void gen_jmp(DisasContext *s, TCGv dest)
298 {
299 update_cc_op(s);
300 tcg_gen_mov_i32(QREG_PC, dest);
301 s->base.is_jmp = DISAS_JUMP;
302 }
303
304 static void gen_raise_exception(int nr)
305 {
306 TCGv_i32 tmp;
307
308 tmp = tcg_const_i32(nr);
309 gen_helper_raise_exception(cpu_env, tmp);
310 tcg_temp_free_i32(tmp);
311 }
312
313 static void gen_exception(DisasContext *s, uint32_t dest, int nr)
314 {
315 update_cc_op(s);
316 tcg_gen_movi_i32(QREG_PC, dest);
317
318 gen_raise_exception(nr);
319
320 s->base.is_jmp = DISAS_NORETURN;
321 }
322
323 static void gen_singlestep_exception(DisasContext *s)
324 {
325 /*
326 * Generate the right kind of exception for singlestep, which is
327 * either the architectural singlestep or EXCP_DEBUG for QEMU's
328 * gdb singlestepping.
329 */
330 if (s->ss_active) {
331 gen_raise_exception(EXCP_TRACE);
332 } else {
333 gen_raise_exception(EXCP_DEBUG);
334 }
335 }
336
337 static inline void gen_addr_fault(DisasContext *s)
338 {
339 gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
340 }
341
342 /*
343 * Generate a load from the specified address. Narrow values are
344 * sign extended to full register width.
345 */
346 static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
347 int sign, int index)
348 {
349 TCGv tmp;
350 tmp = tcg_temp_new_i32();
351 switch(opsize) {
352 case OS_BYTE:
353 if (sign)
354 tcg_gen_qemu_ld8s(tmp, addr, index);
355 else
356 tcg_gen_qemu_ld8u(tmp, addr, index);
357 break;
358 case OS_WORD:
359 if (sign)
360 tcg_gen_qemu_ld16s(tmp, addr, index);
361 else
362 tcg_gen_qemu_ld16u(tmp, addr, index);
363 break;
364 case OS_LONG:
365 tcg_gen_qemu_ld32u(tmp, addr, index);
366 break;
367 default:
368 g_assert_not_reached();
369 }
370 return tmp;
371 }
372
373 /* Generate a store. */
374 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
375 int index)
376 {
377 switch(opsize) {
378 case OS_BYTE:
379 tcg_gen_qemu_st8(val, addr, index);
380 break;
381 case OS_WORD:
382 tcg_gen_qemu_st16(val, addr, index);
383 break;
384 case OS_LONG:
385 tcg_gen_qemu_st32(val, addr, index);
386 break;
387 default:
388 g_assert_not_reached();
389 }
390 }
391
392 typedef enum {
393 EA_STORE,
394 EA_LOADU,
395 EA_LOADS
396 } ea_what;
397
398 /*
399 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
400 * otherwise generate a store.
401 */
402 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
403 ea_what what, int index)
404 {
405 if (what == EA_STORE) {
406 gen_store(s, opsize, addr, val, index);
407 return store_dummy;
408 } else {
409 return mark_to_release(s, gen_load(s, opsize, addr,
410 what == EA_LOADS, index));
411 }
412 }
413
414 /* Read a 16-bit immediate constant */
415 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
416 {
417 uint16_t im;
418 im = translator_lduw(env, s->pc);
419 s->pc += 2;
420 return im;
421 }
422
423 /* Read an 8-bit immediate constant */
424 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
425 {
426 return read_im16(env, s);
427 }
428
429 /* Read a 32-bit immediate constant. */
430 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
431 {
432 uint32_t im;
433 im = read_im16(env, s) << 16;
434 im |= 0xffff & read_im16(env, s);
435 return im;
436 }
437
438 /* Read a 64-bit immediate constant. */
439 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
440 {
441 uint64_t im;
442 im = (uint64_t)read_im32(env, s) << 32;
443 im |= (uint64_t)read_im32(env, s);
444 return im;
445 }
446
447 /* Calculate and address index. */
448 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
449 {
450 TCGv add;
451 int scale;
452
453 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
454 if ((ext & 0x800) == 0) {
455 tcg_gen_ext16s_i32(tmp, add);
456 add = tmp;
457 }
458 scale = (ext >> 9) & 3;
459 if (scale != 0) {
460 tcg_gen_shli_i32(tmp, add, scale);
461 add = tmp;
462 }
463 return add;
464 }
465
466 /*
467 * Handle a base + index + displacement effective address.
468 * A NULL_QREG base means pc-relative.
469 */
470 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
471 {
472 uint32_t offset;
473 uint16_t ext;
474 TCGv add;
475 TCGv tmp;
476 uint32_t bd, od;
477
478 offset = s->pc;
479 ext = read_im16(env, s);
480
481 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
482 return NULL_QREG;
483
484 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
485 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
486 ext &= ~(3 << 9);
487 }
488
489 if (ext & 0x100) {
490 /* full extension word format */
491 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
492 return NULL_QREG;
493
494 if ((ext & 0x30) > 0x10) {
495 /* base displacement */
496 if ((ext & 0x30) == 0x20) {
497 bd = (int16_t)read_im16(env, s);
498 } else {
499 bd = read_im32(env, s);
500 }
501 } else {
502 bd = 0;
503 }
504 tmp = mark_to_release(s, tcg_temp_new());
505 if ((ext & 0x44) == 0) {
506 /* pre-index */
507 add = gen_addr_index(s, ext, tmp);
508 } else {
509 add = NULL_QREG;
510 }
511 if ((ext & 0x80) == 0) {
512 /* base not suppressed */
513 if (IS_NULL_QREG(base)) {
514 base = mark_to_release(s, tcg_const_i32(offset + bd));
515 bd = 0;
516 }
517 if (!IS_NULL_QREG(add)) {
518 tcg_gen_add_i32(tmp, add, base);
519 add = tmp;
520 } else {
521 add = base;
522 }
523 }
524 if (!IS_NULL_QREG(add)) {
525 if (bd != 0) {
526 tcg_gen_addi_i32(tmp, add, bd);
527 add = tmp;
528 }
529 } else {
530 add = mark_to_release(s, tcg_const_i32(bd));
531 }
532 if ((ext & 3) != 0) {
533 /* memory indirect */
534 base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
535 if ((ext & 0x44) == 4) {
536 add = gen_addr_index(s, ext, tmp);
537 tcg_gen_add_i32(tmp, add, base);
538 add = tmp;
539 } else {
540 add = base;
541 }
542 if ((ext & 3) > 1) {
543 /* outer displacement */
544 if ((ext & 3) == 2) {
545 od = (int16_t)read_im16(env, s);
546 } else {
547 od = read_im32(env, s);
548 }
549 } else {
550 od = 0;
551 }
552 if (od != 0) {
553 tcg_gen_addi_i32(tmp, add, od);
554 add = tmp;
555 }
556 }
557 } else {
558 /* brief extension word format */
559 tmp = mark_to_release(s, tcg_temp_new());
560 add = gen_addr_index(s, ext, tmp);
561 if (!IS_NULL_QREG(base)) {
562 tcg_gen_add_i32(tmp, add, base);
563 if ((int8_t)ext)
564 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
565 } else {
566 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
567 }
568 add = tmp;
569 }
570 return add;
571 }
572
573 /* Sign or zero extend a value. */
574
575 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
576 {
577 switch (opsize) {
578 case OS_BYTE:
579 if (sign) {
580 tcg_gen_ext8s_i32(res, val);
581 } else {
582 tcg_gen_ext8u_i32(res, val);
583 }
584 break;
585 case OS_WORD:
586 if (sign) {
587 tcg_gen_ext16s_i32(res, val);
588 } else {
589 tcg_gen_ext16u_i32(res, val);
590 }
591 break;
592 case OS_LONG:
593 tcg_gen_mov_i32(res, val);
594 break;
595 default:
596 g_assert_not_reached();
597 }
598 }
599
600 /* Evaluate all the CC flags. */
601
602 static void gen_flush_flags(DisasContext *s)
603 {
604 TCGv t0, t1;
605
606 switch (s->cc_op) {
607 case CC_OP_FLAGS:
608 return;
609
610 case CC_OP_ADDB:
611 case CC_OP_ADDW:
612 case CC_OP_ADDL:
613 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
614 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
615 /* Compute signed overflow for addition. */
616 t0 = tcg_temp_new();
617 t1 = tcg_temp_new();
618 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
619 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
620 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
621 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
622 tcg_temp_free(t0);
623 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
624 tcg_temp_free(t1);
625 break;
626
627 case CC_OP_SUBB:
628 case CC_OP_SUBW:
629 case CC_OP_SUBL:
630 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
631 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
632 /* Compute signed overflow for subtraction. */
633 t0 = tcg_temp_new();
634 t1 = tcg_temp_new();
635 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
636 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
637 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
638 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
639 tcg_temp_free(t0);
640 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
641 tcg_temp_free(t1);
642 break;
643
644 case CC_OP_CMPB:
645 case CC_OP_CMPW:
646 case CC_OP_CMPL:
647 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
648 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
649 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
650 /* Compute signed overflow for subtraction. */
651 t0 = tcg_temp_new();
652 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
653 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
654 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
655 tcg_temp_free(t0);
656 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
657 break;
658
659 case CC_OP_LOGIC:
660 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
661 tcg_gen_movi_i32(QREG_CC_C, 0);
662 tcg_gen_movi_i32(QREG_CC_V, 0);
663 break;
664
665 case CC_OP_DYNAMIC:
666 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
667 s->cc_op_synced = 1;
668 break;
669
670 default:
671 t0 = tcg_const_i32(s->cc_op);
672 gen_helper_flush_flags(cpu_env, t0);
673 tcg_temp_free(t0);
674 s->cc_op_synced = 1;
675 break;
676 }
677
678 /* Note that flush_flags also assigned to env->cc_op. */
679 s->cc_op = CC_OP_FLAGS;
680 }
681
682 static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
683 {
684 TCGv tmp;
685
686 if (opsize == OS_LONG) {
687 tmp = val;
688 } else {
689 tmp = mark_to_release(s, tcg_temp_new());
690 gen_ext(tmp, val, opsize, sign);
691 }
692
693 return tmp;
694 }
695
696 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
697 {
698 gen_ext(QREG_CC_N, val, opsize, 1);
699 set_cc_op(s, CC_OP_LOGIC);
700 }
701
702 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
703 {
704 tcg_gen_mov_i32(QREG_CC_N, dest);
705 tcg_gen_mov_i32(QREG_CC_V, src);
706 set_cc_op(s, CC_OP_CMPB + opsize);
707 }
708
709 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
710 {
711 gen_ext(QREG_CC_N, dest, opsize, 1);
712 tcg_gen_mov_i32(QREG_CC_V, src);
713 }
714
715 static inline int opsize_bytes(int opsize)
716 {
717 switch (opsize) {
718 case OS_BYTE: return 1;
719 case OS_WORD: return 2;
720 case OS_LONG: return 4;
721 case OS_SINGLE: return 4;
722 case OS_DOUBLE: return 8;
723 case OS_EXTENDED: return 12;
724 case OS_PACKED: return 12;
725 default:
726 g_assert_not_reached();
727 }
728 }
729
730 static inline int insn_opsize(int insn)
731 {
732 switch ((insn >> 6) & 3) {
733 case 0: return OS_BYTE;
734 case 1: return OS_WORD;
735 case 2: return OS_LONG;
736 default:
737 g_assert_not_reached();
738 }
739 }
740
741 static inline int ext_opsize(int ext, int pos)
742 {
743 switch ((ext >> pos) & 7) {
744 case 0: return OS_LONG;
745 case 1: return OS_SINGLE;
746 case 2: return OS_EXTENDED;
747 case 3: return OS_PACKED;
748 case 4: return OS_WORD;
749 case 5: return OS_DOUBLE;
750 case 6: return OS_BYTE;
751 default:
752 g_assert_not_reached();
753 }
754 }
755
756 /*
757 * Assign value to a register. If the width is less than the register width
758 * only the low part of the register is set.
759 */
760 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
761 {
762 TCGv tmp;
763 switch (opsize) {
764 case OS_BYTE:
765 tcg_gen_andi_i32(reg, reg, 0xffffff00);
766 tmp = tcg_temp_new();
767 tcg_gen_ext8u_i32(tmp, val);
768 tcg_gen_or_i32(reg, reg, tmp);
769 tcg_temp_free(tmp);
770 break;
771 case OS_WORD:
772 tcg_gen_andi_i32(reg, reg, 0xffff0000);
773 tmp = tcg_temp_new();
774 tcg_gen_ext16u_i32(tmp, val);
775 tcg_gen_or_i32(reg, reg, tmp);
776 tcg_temp_free(tmp);
777 break;
778 case OS_LONG:
779 case OS_SINGLE:
780 tcg_gen_mov_i32(reg, val);
781 break;
782 default:
783 g_assert_not_reached();
784 }
785 }
786
787 /*
788 * Generate code for an "effective address". Does not adjust the base
789 * register for autoincrement addressing modes.
790 */
791 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
792 int mode, int reg0, int opsize)
793 {
794 TCGv reg;
795 TCGv tmp;
796 uint16_t ext;
797 uint32_t offset;
798
799 switch (mode) {
800 case 0: /* Data register direct. */
801 case 1: /* Address register direct. */
802 return NULL_QREG;
803 case 3: /* Indirect postincrement. */
804 if (opsize == OS_UNSIZED) {
805 return NULL_QREG;
806 }
807 /* fallthru */
808 case 2: /* Indirect register */
809 return get_areg(s, reg0);
810 case 4: /* Indirect predecrememnt. */
811 if (opsize == OS_UNSIZED) {
812 return NULL_QREG;
813 }
814 reg = get_areg(s, reg0);
815 tmp = mark_to_release(s, tcg_temp_new());
816 if (reg0 == 7 && opsize == OS_BYTE &&
817 m68k_feature(s->env, M68K_FEATURE_M68000)) {
818 tcg_gen_subi_i32(tmp, reg, 2);
819 } else {
820 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
821 }
822 return tmp;
823 case 5: /* Indirect displacement. */
824 reg = get_areg(s, reg0);
825 tmp = mark_to_release(s, tcg_temp_new());
826 ext = read_im16(env, s);
827 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
828 return tmp;
829 case 6: /* Indirect index + displacement. */
830 reg = get_areg(s, reg0);
831 return gen_lea_indexed(env, s, reg);
832 case 7: /* Other */
833 switch (reg0) {
834 case 0: /* Absolute short. */
835 offset = (int16_t)read_im16(env, s);
836 return mark_to_release(s, tcg_const_i32(offset));
837 case 1: /* Absolute long. */
838 offset = read_im32(env, s);
839 return mark_to_release(s, tcg_const_i32(offset));
840 case 2: /* pc displacement */
841 offset = s->pc;
842 offset += (int16_t)read_im16(env, s);
843 return mark_to_release(s, tcg_const_i32(offset));
844 case 3: /* pc index+displacement. */
845 return gen_lea_indexed(env, s, NULL_QREG);
846 case 4: /* Immediate. */
847 default:
848 return NULL_QREG;
849 }
850 }
851 /* Should never happen. */
852 return NULL_QREG;
853 }
854
855 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
856 int opsize)
857 {
858 int mode = extract32(insn, 3, 3);
859 int reg0 = REG(insn, 0);
860 return gen_lea_mode(env, s, mode, reg0, opsize);
861 }
862
863 /*
864 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
865 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
866 * ADDRP is non-null for readwrite operands.
867 */
868 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
869 int opsize, TCGv val, TCGv *addrp, ea_what what,
870 int index)
871 {
872 TCGv reg, tmp, result;
873 int32_t offset;
874
875 switch (mode) {
876 case 0: /* Data register direct. */
877 reg = cpu_dregs[reg0];
878 if (what == EA_STORE) {
879 gen_partset_reg(opsize, reg, val);
880 return store_dummy;
881 } else {
882 return gen_extend(s, reg, opsize, what == EA_LOADS);
883 }
884 case 1: /* Address register direct. */
885 reg = get_areg(s, reg0);
886 if (what == EA_STORE) {
887 tcg_gen_mov_i32(reg, val);
888 return store_dummy;
889 } else {
890 return gen_extend(s, reg, opsize, what == EA_LOADS);
891 }
892 case 2: /* Indirect register */
893 reg = get_areg(s, reg0);
894 return gen_ldst(s, opsize, reg, val, what, index);
895 case 3: /* Indirect postincrement. */
896 reg = get_areg(s, reg0);
897 result = gen_ldst(s, opsize, reg, val, what, index);
898 if (what == EA_STORE || !addrp) {
899 TCGv tmp = tcg_temp_new();
900 if (reg0 == 7 && opsize == OS_BYTE &&
901 m68k_feature(s->env, M68K_FEATURE_M68000)) {
902 tcg_gen_addi_i32(tmp, reg, 2);
903 } else {
904 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
905 }
906 delay_set_areg(s, reg0, tmp, true);
907 }
908 return result;
909 case 4: /* Indirect predecrememnt. */
910 if (addrp && what == EA_STORE) {
911 tmp = *addrp;
912 } else {
913 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
914 if (IS_NULL_QREG(tmp)) {
915 return tmp;
916 }
917 if (addrp) {
918 *addrp = tmp;
919 }
920 }
921 result = gen_ldst(s, opsize, tmp, val, what, index);
922 if (what == EA_STORE || !addrp) {
923 delay_set_areg(s, reg0, tmp, false);
924 }
925 return result;
926 case 5: /* Indirect displacement. */
927 case 6: /* Indirect index + displacement. */
928 do_indirect:
929 if (addrp && what == EA_STORE) {
930 tmp = *addrp;
931 } else {
932 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
933 if (IS_NULL_QREG(tmp)) {
934 return tmp;
935 }
936 if (addrp) {
937 *addrp = tmp;
938 }
939 }
940 return gen_ldst(s, opsize, tmp, val, what, index);
941 case 7: /* Other */
942 switch (reg0) {
943 case 0: /* Absolute short. */
944 case 1: /* Absolute long. */
945 case 2: /* pc displacement */
946 case 3: /* pc index+displacement. */
947 goto do_indirect;
948 case 4: /* Immediate. */
949 /* Sign extend values for consistency. */
950 switch (opsize) {
951 case OS_BYTE:
952 if (what == EA_LOADS) {
953 offset = (int8_t)read_im8(env, s);
954 } else {
955 offset = read_im8(env, s);
956 }
957 break;
958 case OS_WORD:
959 if (what == EA_LOADS) {
960 offset = (int16_t)read_im16(env, s);
961 } else {
962 offset = read_im16(env, s);
963 }
964 break;
965 case OS_LONG:
966 offset = read_im32(env, s);
967 break;
968 default:
969 g_assert_not_reached();
970 }
971 return mark_to_release(s, tcg_const_i32(offset));
972 default:
973 return NULL_QREG;
974 }
975 }
976 /* Should never happen. */
977 return NULL_QREG;
978 }
979
980 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
981 int opsize, TCGv val, TCGv *addrp, ea_what what, int index)
982 {
983 int mode = extract32(insn, 3, 3);
984 int reg0 = REG(insn, 0);
985 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index);
986 }
987
988 static TCGv_ptr gen_fp_ptr(int freg)
989 {
990 TCGv_ptr fp = tcg_temp_new_ptr();
991 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
992 return fp;
993 }
994
995 static TCGv_ptr gen_fp_result_ptr(void)
996 {
997 TCGv_ptr fp = tcg_temp_new_ptr();
998 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
999 return fp;
1000 }
1001
1002 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
1003 {
1004 TCGv t32;
1005 TCGv_i64 t64;
1006
1007 t32 = tcg_temp_new();
1008 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
1009 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
1010 tcg_temp_free(t32);
1011
1012 t64 = tcg_temp_new_i64();
1013 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
1014 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
1015 tcg_temp_free_i64(t64);
1016 }
1017
1018 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1019 int index)
1020 {
1021 TCGv tmp;
1022 TCGv_i64 t64;
1023
1024 t64 = tcg_temp_new_i64();
1025 tmp = tcg_temp_new();
1026 switch (opsize) {
1027 case OS_BYTE:
1028 tcg_gen_qemu_ld8s(tmp, addr, index);
1029 gen_helper_exts32(cpu_env, fp, tmp);
1030 break;
1031 case OS_WORD:
1032 tcg_gen_qemu_ld16s(tmp, addr, index);
1033 gen_helper_exts32(cpu_env, fp, tmp);
1034 break;
1035 case OS_LONG:
1036 tcg_gen_qemu_ld32u(tmp, addr, index);
1037 gen_helper_exts32(cpu_env, fp, tmp);
1038 break;
1039 case OS_SINGLE:
1040 tcg_gen_qemu_ld32u(tmp, addr, index);
1041 gen_helper_extf32(cpu_env, fp, tmp);
1042 break;
1043 case OS_DOUBLE:
1044 tcg_gen_qemu_ld64(t64, addr, index);
1045 gen_helper_extf64(cpu_env, fp, t64);
1046 break;
1047 case OS_EXTENDED:
1048 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1049 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1050 break;
1051 }
1052 tcg_gen_qemu_ld32u(tmp, addr, index);
1053 tcg_gen_shri_i32(tmp, tmp, 16);
1054 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1055 tcg_gen_addi_i32(tmp, addr, 4);
1056 tcg_gen_qemu_ld64(t64, tmp, index);
1057 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1058 break;
1059 case OS_PACKED:
1060 /*
1061 * unimplemented data type on 68040/ColdFire
1062 * FIXME if needed for another FPU
1063 */
1064 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1065 break;
1066 default:
1067 g_assert_not_reached();
1068 }
1069 tcg_temp_free(tmp);
1070 tcg_temp_free_i64(t64);
1071 }
1072
1073 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1074 int index)
1075 {
1076 TCGv tmp;
1077 TCGv_i64 t64;
1078
1079 t64 = tcg_temp_new_i64();
1080 tmp = tcg_temp_new();
1081 switch (opsize) {
1082 case OS_BYTE:
1083 gen_helper_reds32(tmp, cpu_env, fp);
1084 tcg_gen_qemu_st8(tmp, addr, index);
1085 break;
1086 case OS_WORD:
1087 gen_helper_reds32(tmp, cpu_env, fp);
1088 tcg_gen_qemu_st16(tmp, addr, index);
1089 break;
1090 case OS_LONG:
1091 gen_helper_reds32(tmp, cpu_env, fp);
1092 tcg_gen_qemu_st32(tmp, addr, index);
1093 break;
1094 case OS_SINGLE:
1095 gen_helper_redf32(tmp, cpu_env, fp);
1096 tcg_gen_qemu_st32(tmp, addr, index);
1097 break;
1098 case OS_DOUBLE:
1099 gen_helper_redf64(t64, cpu_env, fp);
1100 tcg_gen_qemu_st64(t64, addr, index);
1101 break;
1102 case OS_EXTENDED:
1103 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1104 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1105 break;
1106 }
1107 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1108 tcg_gen_shli_i32(tmp, tmp, 16);
1109 tcg_gen_qemu_st32(tmp, addr, index);
1110 tcg_gen_addi_i32(tmp, addr, 4);
1111 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1112 tcg_gen_qemu_st64(t64, tmp, index);
1113 break;
1114 case OS_PACKED:
1115 /*
1116 * unimplemented data type on 68040/ColdFire
1117 * FIXME if needed for another FPU
1118 */
1119 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1120 break;
1121 default:
1122 g_assert_not_reached();
1123 }
1124 tcg_temp_free(tmp);
1125 tcg_temp_free_i64(t64);
1126 }
1127
1128 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1129 TCGv_ptr fp, ea_what what, int index)
1130 {
1131 if (what == EA_STORE) {
1132 gen_store_fp(s, opsize, addr, fp, index);
1133 } else {
1134 gen_load_fp(s, opsize, addr, fp, index);
1135 }
1136 }
1137
1138 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1139 int reg0, int opsize, TCGv_ptr fp, ea_what what,
1140 int index)
1141 {
1142 TCGv reg, addr, tmp;
1143 TCGv_i64 t64;
1144
1145 switch (mode) {
1146 case 0: /* Data register direct. */
1147 reg = cpu_dregs[reg0];
1148 if (what == EA_STORE) {
1149 switch (opsize) {
1150 case OS_BYTE:
1151 case OS_WORD:
1152 case OS_LONG:
1153 gen_helper_reds32(reg, cpu_env, fp);
1154 break;
1155 case OS_SINGLE:
1156 gen_helper_redf32(reg, cpu_env, fp);
1157 break;
1158 default:
1159 g_assert_not_reached();
1160 }
1161 } else {
1162 tmp = tcg_temp_new();
1163 switch (opsize) {
1164 case OS_BYTE:
1165 tcg_gen_ext8s_i32(tmp, reg);
1166 gen_helper_exts32(cpu_env, fp, tmp);
1167 break;
1168 case OS_WORD:
1169 tcg_gen_ext16s_i32(tmp, reg);
1170 gen_helper_exts32(cpu_env, fp, tmp);
1171 break;
1172 case OS_LONG:
1173 gen_helper_exts32(cpu_env, fp, reg);
1174 break;
1175 case OS_SINGLE:
1176 gen_helper_extf32(cpu_env, fp, reg);
1177 break;
1178 default:
1179 g_assert_not_reached();
1180 }
1181 tcg_temp_free(tmp);
1182 }
1183 return 0;
1184 case 1: /* Address register direct. */
1185 return -1;
1186 case 2: /* Indirect register */
1187 addr = get_areg(s, reg0);
1188 gen_ldst_fp(s, opsize, addr, fp, what, index);
1189 return 0;
1190 case 3: /* Indirect postincrement. */
1191 addr = cpu_aregs[reg0];
1192 gen_ldst_fp(s, opsize, addr, fp, what, index);
1193 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1194 return 0;
1195 case 4: /* Indirect predecrememnt. */
1196 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1197 if (IS_NULL_QREG(addr)) {
1198 return -1;
1199 }
1200 gen_ldst_fp(s, opsize, addr, fp, what, index);
1201 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1202 return 0;
1203 case 5: /* Indirect displacement. */
1204 case 6: /* Indirect index + displacement. */
1205 do_indirect:
1206 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1207 if (IS_NULL_QREG(addr)) {
1208 return -1;
1209 }
1210 gen_ldst_fp(s, opsize, addr, fp, what, index);
1211 return 0;
1212 case 7: /* Other */
1213 switch (reg0) {
1214 case 0: /* Absolute short. */
1215 case 1: /* Absolute long. */
1216 case 2: /* pc displacement */
1217 case 3: /* pc index+displacement. */
1218 goto do_indirect;
1219 case 4: /* Immediate. */
1220 if (what == EA_STORE) {
1221 return -1;
1222 }
1223 switch (opsize) {
1224 case OS_BYTE:
1225 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1226 gen_helper_exts32(cpu_env, fp, tmp);
1227 tcg_temp_free(tmp);
1228 break;
1229 case OS_WORD:
1230 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1231 gen_helper_exts32(cpu_env, fp, tmp);
1232 tcg_temp_free(tmp);
1233 break;
1234 case OS_LONG:
1235 tmp = tcg_const_i32(read_im32(env, s));
1236 gen_helper_exts32(cpu_env, fp, tmp);
1237 tcg_temp_free(tmp);
1238 break;
1239 case OS_SINGLE:
1240 tmp = tcg_const_i32(read_im32(env, s));
1241 gen_helper_extf32(cpu_env, fp, tmp);
1242 tcg_temp_free(tmp);
1243 break;
1244 case OS_DOUBLE:
1245 t64 = tcg_const_i64(read_im64(env, s));
1246 gen_helper_extf64(cpu_env, fp, t64);
1247 tcg_temp_free_i64(t64);
1248 break;
1249 case OS_EXTENDED:
1250 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1251 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1252 break;
1253 }
1254 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1255 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1256 tcg_temp_free(tmp);
1257 t64 = tcg_const_i64(read_im64(env, s));
1258 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1259 tcg_temp_free_i64(t64);
1260 break;
1261 case OS_PACKED:
1262 /*
1263 * unimplemented data type on 68040/ColdFire
1264 * FIXME if needed for another FPU
1265 */
1266 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1267 break;
1268 default:
1269 g_assert_not_reached();
1270 }
1271 return 0;
1272 default:
1273 return -1;
1274 }
1275 }
1276 return -1;
1277 }
1278
1279 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1280 int opsize, TCGv_ptr fp, ea_what what, int index)
1281 {
1282 int mode = extract32(insn, 3, 3);
1283 int reg0 = REG(insn, 0);
1284 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index);
1285 }
1286
1287 typedef struct {
1288 TCGCond tcond;
1289 bool g1;
1290 bool g2;
1291 TCGv v1;
1292 TCGv v2;
1293 } DisasCompare;
1294
1295 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1296 {
1297 TCGv tmp, tmp2;
1298 TCGCond tcond;
1299 CCOp op = s->cc_op;
1300
1301 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1302 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1303 c->g1 = c->g2 = 1;
1304 c->v1 = QREG_CC_N;
1305 c->v2 = QREG_CC_V;
1306 switch (cond) {
1307 case 2: /* HI */
1308 case 3: /* LS */
1309 tcond = TCG_COND_LEU;
1310 goto done;
1311 case 4: /* CC */
1312 case 5: /* CS */
1313 tcond = TCG_COND_LTU;
1314 goto done;
1315 case 6: /* NE */
1316 case 7: /* EQ */
1317 tcond = TCG_COND_EQ;
1318 goto done;
1319 case 10: /* PL */
1320 case 11: /* MI */
1321 c->g1 = c->g2 = 0;
1322 c->v2 = tcg_const_i32(0);
1323 c->v1 = tmp = tcg_temp_new();
1324 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1325 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1326 /* fallthru */
1327 case 12: /* GE */
1328 case 13: /* LT */
1329 tcond = TCG_COND_LT;
1330 goto done;
1331 case 14: /* GT */
1332 case 15: /* LE */
1333 tcond = TCG_COND_LE;
1334 goto done;
1335 }
1336 }
1337
1338 c->g1 = 1;
1339 c->g2 = 0;
1340 c->v2 = tcg_const_i32(0);
1341
1342 switch (cond) {
1343 case 0: /* T */
1344 case 1: /* F */
1345 c->v1 = c->v2;
1346 tcond = TCG_COND_NEVER;
1347 goto done;
1348 case 14: /* GT (!(Z || (N ^ V))) */
1349 case 15: /* LE (Z || (N ^ V)) */
1350 /*
1351 * Logic operations clear V, which simplifies LE to (Z || N),
1352 * and since Z and N are co-located, this becomes a normal
1353 * comparison vs N.
1354 */
1355 if (op == CC_OP_LOGIC) {
1356 c->v1 = QREG_CC_N;
1357 tcond = TCG_COND_LE;
1358 goto done;
1359 }
1360 break;
1361 case 12: /* GE (!(N ^ V)) */
1362 case 13: /* LT (N ^ V) */
1363 /* Logic operations clear V, which simplifies this to N. */
1364 if (op != CC_OP_LOGIC) {
1365 break;
1366 }
1367 /* fallthru */
1368 case 10: /* PL (!N) */
1369 case 11: /* MI (N) */
1370 /* Several cases represent N normally. */
1371 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1372 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1373 op == CC_OP_LOGIC) {
1374 c->v1 = QREG_CC_N;
1375 tcond = TCG_COND_LT;
1376 goto done;
1377 }
1378 break;
1379 case 6: /* NE (!Z) */
1380 case 7: /* EQ (Z) */
1381 /* Some cases fold Z into N. */
1382 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1383 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1384 op == CC_OP_LOGIC) {
1385 tcond = TCG_COND_EQ;
1386 c->v1 = QREG_CC_N;
1387 goto done;
1388 }
1389 break;
1390 case 4: /* CC (!C) */
1391 case 5: /* CS (C) */
1392 /* Some cases fold C into X. */
1393 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1394 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
1395 tcond = TCG_COND_NE;
1396 c->v1 = QREG_CC_X;
1397 goto done;
1398 }
1399 /* fallthru */
1400 case 8: /* VC (!V) */
1401 case 9: /* VS (V) */
1402 /* Logic operations clear V and C. */
1403 if (op == CC_OP_LOGIC) {
1404 tcond = TCG_COND_NEVER;
1405 c->v1 = c->v2;
1406 goto done;
1407 }
1408 break;
1409 }
1410
1411 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1412 gen_flush_flags(s);
1413
1414 switch (cond) {
1415 case 0: /* T */
1416 case 1: /* F */
1417 default:
1418 /* Invalid, or handled above. */
1419 abort();
1420 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1421 case 3: /* LS (C || Z) */
1422 c->v1 = tmp = tcg_temp_new();
1423 c->g1 = 0;
1424 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1425 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1426 tcond = TCG_COND_NE;
1427 break;
1428 case 4: /* CC (!C) */
1429 case 5: /* CS (C) */
1430 c->v1 = QREG_CC_C;
1431 tcond = TCG_COND_NE;
1432 break;
1433 case 6: /* NE (!Z) */
1434 case 7: /* EQ (Z) */
1435 c->v1 = QREG_CC_Z;
1436 tcond = TCG_COND_EQ;
1437 break;
1438 case 8: /* VC (!V) */
1439 case 9: /* VS (V) */
1440 c->v1 = QREG_CC_V;
1441 tcond = TCG_COND_LT;
1442 break;
1443 case 10: /* PL (!N) */
1444 case 11: /* MI (N) */
1445 c->v1 = QREG_CC_N;
1446 tcond = TCG_COND_LT;
1447 break;
1448 case 12: /* GE (!(N ^ V)) */
1449 case 13: /* LT (N ^ V) */
1450 c->v1 = tmp = tcg_temp_new();
1451 c->g1 = 0;
1452 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1453 tcond = TCG_COND_LT;
1454 break;
1455 case 14: /* GT (!(Z || (N ^ V))) */
1456 case 15: /* LE (Z || (N ^ V)) */
1457 c->v1 = tmp = tcg_temp_new();
1458 c->g1 = 0;
1459 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1460 tcg_gen_neg_i32(tmp, tmp);
1461 tmp2 = tcg_temp_new();
1462 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1463 tcg_gen_or_i32(tmp, tmp, tmp2);
1464 tcg_temp_free(tmp2);
1465 tcond = TCG_COND_LT;
1466 break;
1467 }
1468
1469 done:
1470 if ((cond & 1) == 0) {
1471 tcond = tcg_invert_cond(tcond);
1472 }
1473 c->tcond = tcond;
1474 }
1475
1476 static void free_cond(DisasCompare *c)
1477 {
1478 if (!c->g1) {
1479 tcg_temp_free(c->v1);
1480 }
1481 if (!c->g2) {
1482 tcg_temp_free(c->v2);
1483 }
1484 }
1485
1486 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1487 {
1488 DisasCompare c;
1489
1490 gen_cc_cond(&c, s, cond);
1491 update_cc_op(s);
1492 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1493 free_cond(&c);
1494 }
1495
1496 /* Force a TB lookup after an instruction that changes the CPU state. */
1497 static void gen_exit_tb(DisasContext *s)
1498 {
1499 update_cc_op(s);
1500 tcg_gen_movi_i32(QREG_PC, s->pc);
1501 s->base.is_jmp = DISAS_EXIT;
1502 }
1503
1504 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1505 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1506 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1507 if (IS_NULL_QREG(result)) { \
1508 gen_addr_fault(s); \
1509 return; \
1510 } \
1511 } while (0)
1512
1513 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1514 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1515 EA_STORE, IS_USER(s)); \
1516 if (IS_NULL_QREG(ea_result)) { \
1517 gen_addr_fault(s); \
1518 return; \
1519 } \
1520 } while (0)
1521
1522 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1523 {
1524 #ifndef CONFIG_USER_ONLY
1525 return (s->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
1526 || (s->base.pc_next & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1527 #else
1528 return true;
1529 #endif
1530 }
1531
1532 /* Generate a jump to an immediate address. */
1533 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1534 {
1535 if (unlikely(is_singlestepping(s))) {
1536 update_cc_op(s);
1537 tcg_gen_movi_i32(QREG_PC, dest);
1538 gen_singlestep_exception(s);
1539 } else if (use_goto_tb(s, dest)) {
1540 tcg_gen_goto_tb(n);
1541 tcg_gen_movi_i32(QREG_PC, dest);
1542 tcg_gen_exit_tb(s->base.tb, n);
1543 } else {
1544 gen_jmp_im(s, dest);
1545 tcg_gen_exit_tb(NULL, 0);
1546 }
1547 s->base.is_jmp = DISAS_NORETURN;
1548 }
1549
1550 DISAS_INSN(scc)
1551 {
1552 DisasCompare c;
1553 int cond;
1554 TCGv tmp;
1555
1556 cond = (insn >> 8) & 0xf;
1557 gen_cc_cond(&c, s, cond);
1558
1559 tmp = tcg_temp_new();
1560 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1561 free_cond(&c);
1562
1563 tcg_gen_neg_i32(tmp, tmp);
1564 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1565 tcg_temp_free(tmp);
1566 }
1567
1568 DISAS_INSN(dbcc)
1569 {
1570 TCGLabel *l1;
1571 TCGv reg;
1572 TCGv tmp;
1573 int16_t offset;
1574 uint32_t base;
1575
1576 reg = DREG(insn, 0);
1577 base = s->pc;
1578 offset = (int16_t)read_im16(env, s);
1579 l1 = gen_new_label();
1580 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1581
1582 tmp = tcg_temp_new();
1583 tcg_gen_ext16s_i32(tmp, reg);
1584 tcg_gen_addi_i32(tmp, tmp, -1);
1585 gen_partset_reg(OS_WORD, reg, tmp);
1586 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1587 gen_jmp_tb(s, 1, base + offset);
1588 gen_set_label(l1);
1589 gen_jmp_tb(s, 0, s->pc);
1590 }
1591
1592 DISAS_INSN(undef_mac)
1593 {
1594 gen_exception(s, s->base.pc_next, EXCP_LINEA);
1595 }
1596
1597 DISAS_INSN(undef_fpu)
1598 {
1599 gen_exception(s, s->base.pc_next, EXCP_LINEF);
1600 }
1601
1602 DISAS_INSN(undef)
1603 {
1604 /*
1605 * ??? This is both instructions that are as yet unimplemented
1606 * for the 680x0 series, as well as those that are implemented
1607 * but actually illegal for CPU32 or pre-68020.
1608 */
1609 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
1610 insn, s->base.pc_next);
1611 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1612 }
1613
1614 DISAS_INSN(mulw)
1615 {
1616 TCGv reg;
1617 TCGv tmp;
1618 TCGv src;
1619 int sign;
1620
1621 sign = (insn & 0x100) != 0;
1622 reg = DREG(insn, 9);
1623 tmp = tcg_temp_new();
1624 if (sign)
1625 tcg_gen_ext16s_i32(tmp, reg);
1626 else
1627 tcg_gen_ext16u_i32(tmp, reg);
1628 SRC_EA(env, src, OS_WORD, sign, NULL);
1629 tcg_gen_mul_i32(tmp, tmp, src);
1630 tcg_gen_mov_i32(reg, tmp);
1631 gen_logic_cc(s, tmp, OS_LONG);
1632 tcg_temp_free(tmp);
1633 }
1634
1635 DISAS_INSN(divw)
1636 {
1637 int sign;
1638 TCGv src;
1639 TCGv destr;
1640
1641 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1642
1643 sign = (insn & 0x100) != 0;
1644
1645 /* dest.l / src.w */
1646
1647 SRC_EA(env, src, OS_WORD, sign, NULL);
1648 destr = tcg_const_i32(REG(insn, 9));
1649 if (sign) {
1650 gen_helper_divsw(cpu_env, destr, src);
1651 } else {
1652 gen_helper_divuw(cpu_env, destr, src);
1653 }
1654 tcg_temp_free(destr);
1655
1656 set_cc_op(s, CC_OP_FLAGS);
1657 }
1658
1659 DISAS_INSN(divl)
1660 {
1661 TCGv num, reg, den;
1662 int sign;
1663 uint16_t ext;
1664
1665 ext = read_im16(env, s);
1666
1667 sign = (ext & 0x0800) != 0;
1668
1669 if (ext & 0x400) {
1670 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1671 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1672 return;
1673 }
1674
1675 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1676
1677 SRC_EA(env, den, OS_LONG, 0, NULL);
1678 num = tcg_const_i32(REG(ext, 12));
1679 reg = tcg_const_i32(REG(ext, 0));
1680 if (sign) {
1681 gen_helper_divsll(cpu_env, num, reg, den);
1682 } else {
1683 gen_helper_divull(cpu_env, num, reg, den);
1684 }
1685 tcg_temp_free(reg);
1686 tcg_temp_free(num);
1687 set_cc_op(s, CC_OP_FLAGS);
1688 return;
1689 }
1690
1691 /* divX.l <EA>, Dq 32/32 -> 32q */
1692 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1693
1694 SRC_EA(env, den, OS_LONG, 0, NULL);
1695 num = tcg_const_i32(REG(ext, 12));
1696 reg = tcg_const_i32(REG(ext, 0));
1697 if (sign) {
1698 gen_helper_divsl(cpu_env, num, reg, den);
1699 } else {
1700 gen_helper_divul(cpu_env, num, reg, den);
1701 }
1702 tcg_temp_free(reg);
1703 tcg_temp_free(num);
1704
1705 set_cc_op(s, CC_OP_FLAGS);
1706 }
1707
1708 static void bcd_add(TCGv dest, TCGv src)
1709 {
1710 TCGv t0, t1;
1711
1712 /*
1713 * dest10 = dest10 + src10 + X
1714 *
1715 * t1 = src
1716 * t2 = t1 + 0x066
1717 * t3 = t2 + dest + X
1718 * t4 = t2 ^ dest
1719 * t5 = t3 ^ t4
1720 * t6 = ~t5 & 0x110
1721 * t7 = (t6 >> 2) | (t6 >> 3)
1722 * return t3 - t7
1723 */
1724
1725 /*
1726 * t1 = (src + 0x066) + dest + X
1727 * = result with some possible exceeding 0x6
1728 */
1729
1730 t0 = tcg_const_i32(0x066);
1731 tcg_gen_add_i32(t0, t0, src);
1732
1733 t1 = tcg_temp_new();
1734 tcg_gen_add_i32(t1, t0, dest);
1735 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1736
1737 /* we will remove exceeding 0x6 where there is no carry */
1738
1739 /*
1740 * t0 = (src + 0x0066) ^ dest
1741 * = t1 without carries
1742 */
1743
1744 tcg_gen_xor_i32(t0, t0, dest);
1745
1746 /*
1747 * extract the carries
1748 * t0 = t0 ^ t1
1749 * = only the carries
1750 */
1751
1752 tcg_gen_xor_i32(t0, t0, t1);
1753
1754 /*
1755 * generate 0x1 where there is no carry
1756 * and for each 0x10, generate a 0x6
1757 */
1758
1759 tcg_gen_shri_i32(t0, t0, 3);
1760 tcg_gen_not_i32(t0, t0);
1761 tcg_gen_andi_i32(t0, t0, 0x22);
1762 tcg_gen_add_i32(dest, t0, t0);
1763 tcg_gen_add_i32(dest, dest, t0);
1764 tcg_temp_free(t0);
1765
1766 /*
1767 * remove the exceeding 0x6
1768 * for digits that have not generated a carry
1769 */
1770
1771 tcg_gen_sub_i32(dest, t1, dest);
1772 tcg_temp_free(t1);
1773 }
1774
1775 static void bcd_sub(TCGv dest, TCGv src)
1776 {
1777 TCGv t0, t1, t2;
1778
1779 /*
1780 * dest10 = dest10 - src10 - X
1781 * = bcd_add(dest + 1 - X, 0x199 - src)
1782 */
1783
1784 /* t0 = 0x066 + (0x199 - src) */
1785
1786 t0 = tcg_temp_new();
1787 tcg_gen_subfi_i32(t0, 0x1ff, src);
1788
1789 /* t1 = t0 + dest + 1 - X*/
1790
1791 t1 = tcg_temp_new();
1792 tcg_gen_add_i32(t1, t0, dest);
1793 tcg_gen_addi_i32(t1, t1, 1);
1794 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1795
1796 /* t2 = t0 ^ dest */
1797
1798 t2 = tcg_temp_new();
1799 tcg_gen_xor_i32(t2, t0, dest);
1800
1801 /* t0 = t1 ^ t2 */
1802
1803 tcg_gen_xor_i32(t0, t1, t2);
1804
1805 /*
1806 * t2 = ~t0 & 0x110
1807 * t0 = (t2 >> 2) | (t2 >> 3)
1808 *
1809 * to fit on 8bit operands, changed in:
1810 *
1811 * t2 = ~(t0 >> 3) & 0x22
1812 * t0 = t2 + t2
1813 * t0 = t0 + t2
1814 */
1815
1816 tcg_gen_shri_i32(t2, t0, 3);
1817 tcg_gen_not_i32(t2, t2);
1818 tcg_gen_andi_i32(t2, t2, 0x22);
1819 tcg_gen_add_i32(t0, t2, t2);
1820 tcg_gen_add_i32(t0, t0, t2);
1821 tcg_temp_free(t2);
1822
1823 /* return t1 - t0 */
1824
1825 tcg_gen_sub_i32(dest, t1, t0);
1826 tcg_temp_free(t0);
1827 tcg_temp_free(t1);
1828 }
1829
1830 static void bcd_flags(TCGv val)
1831 {
1832 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1833 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1834
1835 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1836
1837 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1838 }
1839
1840 DISAS_INSN(abcd_reg)
1841 {
1842 TCGv src;
1843 TCGv dest;
1844
1845 gen_flush_flags(s); /* !Z is sticky */
1846
1847 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1848 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1849 bcd_add(dest, src);
1850 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1851
1852 bcd_flags(dest);
1853 }
1854
1855 DISAS_INSN(abcd_mem)
1856 {
1857 TCGv src, dest, addr;
1858
1859 gen_flush_flags(s); /* !Z is sticky */
1860
1861 /* Indirect pre-decrement load (mode 4) */
1862
1863 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1864 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1865 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1866 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1867
1868 bcd_add(dest, src);
1869
1870 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1871 EA_STORE, IS_USER(s));
1872
1873 bcd_flags(dest);
1874 }
1875
1876 DISAS_INSN(sbcd_reg)
1877 {
1878 TCGv src, dest;
1879
1880 gen_flush_flags(s); /* !Z is sticky */
1881
1882 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1883 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1884
1885 bcd_sub(dest, src);
1886
1887 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1888
1889 bcd_flags(dest);
1890 }
1891
1892 DISAS_INSN(sbcd_mem)
1893 {
1894 TCGv src, dest, addr;
1895
1896 gen_flush_flags(s); /* !Z is sticky */
1897
1898 /* Indirect pre-decrement load (mode 4) */
1899
1900 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1901 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1902 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1903 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1904
1905 bcd_sub(dest, src);
1906
1907 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1908 EA_STORE, IS_USER(s));
1909
1910 bcd_flags(dest);
1911 }
1912
1913 DISAS_INSN(nbcd)
1914 {
1915 TCGv src, dest;
1916 TCGv addr;
1917
1918 gen_flush_flags(s); /* !Z is sticky */
1919
1920 SRC_EA(env, src, OS_BYTE, 0, &addr);
1921
1922 dest = tcg_const_i32(0);
1923 bcd_sub(dest, src);
1924
1925 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1926
1927 bcd_flags(dest);
1928
1929 tcg_temp_free(dest);
1930 }
1931
1932 DISAS_INSN(addsub)
1933 {
1934 TCGv reg;
1935 TCGv dest;
1936 TCGv src;
1937 TCGv tmp;
1938 TCGv addr;
1939 int add;
1940 int opsize;
1941
1942 add = (insn & 0x4000) != 0;
1943 opsize = insn_opsize(insn);
1944 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
1945 dest = tcg_temp_new();
1946 if (insn & 0x100) {
1947 SRC_EA(env, tmp, opsize, 1, &addr);
1948 src = reg;
1949 } else {
1950 tmp = reg;
1951 SRC_EA(env, src, opsize, 1, NULL);
1952 }
1953 if (add) {
1954 tcg_gen_add_i32(dest, tmp, src);
1955 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1956 set_cc_op(s, CC_OP_ADDB + opsize);
1957 } else {
1958 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1959 tcg_gen_sub_i32(dest, tmp, src);
1960 set_cc_op(s, CC_OP_SUBB + opsize);
1961 }
1962 gen_update_cc_add(dest, src, opsize);
1963 if (insn & 0x100) {
1964 DEST_EA(env, insn, opsize, dest, &addr);
1965 } else {
1966 gen_partset_reg(opsize, DREG(insn, 9), dest);
1967 }
1968 tcg_temp_free(dest);
1969 }
1970
1971 /* Reverse the order of the bits in REG. */
1972 DISAS_INSN(bitrev)
1973 {
1974 TCGv reg;
1975 reg = DREG(insn, 0);
1976 gen_helper_bitrev(reg, reg);
1977 }
1978
1979 DISAS_INSN(bitop_reg)
1980 {
1981 int opsize;
1982 int op;
1983 TCGv src1;
1984 TCGv src2;
1985 TCGv tmp;
1986 TCGv addr;
1987 TCGv dest;
1988
1989 if ((insn & 0x38) != 0)
1990 opsize = OS_BYTE;
1991 else
1992 opsize = OS_LONG;
1993 op = (insn >> 6) & 3;
1994 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1995
1996 gen_flush_flags(s);
1997 src2 = tcg_temp_new();
1998 if (opsize == OS_BYTE)
1999 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
2000 else
2001 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
2002
2003 tmp = tcg_const_i32(1);
2004 tcg_gen_shl_i32(tmp, tmp, src2);
2005 tcg_temp_free(src2);
2006
2007 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
2008
2009 dest = tcg_temp_new();
2010 switch (op) {
2011 case 1: /* bchg */
2012 tcg_gen_xor_i32(dest, src1, tmp);
2013 break;
2014 case 2: /* bclr */
2015 tcg_gen_andc_i32(dest, src1, tmp);
2016 break;
2017 case 3: /* bset */
2018 tcg_gen_or_i32(dest, src1, tmp);
2019 break;
2020 default: /* btst */
2021 break;
2022 }
2023 tcg_temp_free(tmp);
2024 if (op) {
2025 DEST_EA(env, insn, opsize, dest, &addr);
2026 }
2027 tcg_temp_free(dest);
2028 }
2029
2030 DISAS_INSN(sats)
2031 {
2032 TCGv reg;
2033 reg = DREG(insn, 0);
2034 gen_flush_flags(s);
2035 gen_helper_sats(reg, reg, QREG_CC_V);
2036 gen_logic_cc(s, reg, OS_LONG);
2037 }
2038
2039 static void gen_push(DisasContext *s, TCGv val)
2040 {
2041 TCGv tmp;
2042
2043 tmp = tcg_temp_new();
2044 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2045 gen_store(s, OS_LONG, tmp, val, IS_USER(s));
2046 tcg_gen_mov_i32(QREG_SP, tmp);
2047 tcg_temp_free(tmp);
2048 }
2049
2050 static TCGv mreg(int reg)
2051 {
2052 if (reg < 8) {
2053 /* Dx */
2054 return cpu_dregs[reg];
2055 }
2056 /* Ax */
2057 return cpu_aregs[reg & 7];
2058 }
2059
2060 DISAS_INSN(movem)
2061 {
2062 TCGv addr, incr, tmp, r[16];
2063 int is_load = (insn & 0x0400) != 0;
2064 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
2065 uint16_t mask = read_im16(env, s);
2066 int mode = extract32(insn, 3, 3);
2067 int reg0 = REG(insn, 0);
2068 int i;
2069
2070 tmp = cpu_aregs[reg0];
2071
2072 switch (mode) {
2073 case 0: /* data register direct */
2074 case 1: /* addr register direct */
2075 do_addr_fault:
2076 gen_addr_fault(s);
2077 return;
2078
2079 case 2: /* indirect */
2080 break;
2081
2082 case 3: /* indirect post-increment */
2083 if (!is_load) {
2084 /* post-increment is not allowed */
2085 goto do_addr_fault;
2086 }
2087 break;
2088
2089 case 4: /* indirect pre-decrement */
2090 if (is_load) {
2091 /* pre-decrement is not allowed */
2092 goto do_addr_fault;
2093 }
2094 /*
2095 * We want a bare copy of the address reg, without any pre-decrement
2096 * adjustment, as gen_lea would provide.
2097 */
2098 break;
2099
2100 default:
2101 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2102 if (IS_NULL_QREG(tmp)) {
2103 goto do_addr_fault;
2104 }
2105 break;
2106 }
2107
2108 addr = tcg_temp_new();
2109 tcg_gen_mov_i32(addr, tmp);
2110 incr = tcg_const_i32(opsize_bytes(opsize));
2111
2112 if (is_load) {
2113 /* memory to register */
2114 for (i = 0; i < 16; i++) {
2115 if (mask & (1 << i)) {
2116 r[i] = gen_load(s, opsize, addr, 1, IS_USER(s));
2117 tcg_gen_add_i32(addr, addr, incr);
2118 }
2119 }
2120 for (i = 0; i < 16; i++) {
2121 if (mask & (1 << i)) {
2122 tcg_gen_mov_i32(mreg(i), r[i]);
2123 tcg_temp_free(r[i]);
2124 }
2125 }
2126 if (mode == 3) {
2127 /* post-increment: movem (An)+,X */
2128 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2129 }
2130 } else {
2131 /* register to memory */
2132 if (mode == 4) {
2133 /* pre-decrement: movem X,-(An) */
2134 for (i = 15; i >= 0; i--) {
2135 if ((mask << i) & 0x8000) {
2136 tcg_gen_sub_i32(addr, addr, incr);
2137 if (reg0 + 8 == i &&
2138 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2139 /*
2140 * M68020+: if the addressing register is the
2141 * register moved to memory, the value written
2142 * is the initial value decremented by the size of
2143 * the operation, regardless of how many actual
2144 * stores have been performed until this point.
2145 * M68000/M68010: the value is the initial value.
2146 */
2147 tmp = tcg_temp_new();
2148 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2149 gen_store(s, opsize, addr, tmp, IS_USER(s));
2150 tcg_temp_free(tmp);
2151 } else {
2152 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2153 }
2154 }
2155 }
2156 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2157 } else {
2158 for (i = 0; i < 16; i++) {
2159 if (mask & (1 << i)) {
2160 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2161 tcg_gen_add_i32(addr, addr, incr);
2162 }
2163 }
2164 }
2165 }
2166
2167 tcg_temp_free(incr);
2168 tcg_temp_free(addr);
2169 }
2170
2171 DISAS_INSN(movep)
2172 {
2173 uint8_t i;
2174 int16_t displ;
2175 TCGv reg;
2176 TCGv addr;
2177 TCGv abuf;
2178 TCGv dbuf;
2179
2180 displ = read_im16(env, s);
2181
2182 addr = AREG(insn, 0);
2183 reg = DREG(insn, 9);
2184
2185 abuf = tcg_temp_new();
2186 tcg_gen_addi_i32(abuf, addr, displ);
2187 dbuf = tcg_temp_new();
2188
2189 if (insn & 0x40) {
2190 i = 4;
2191 } else {
2192 i = 2;
2193 }
2194
2195 if (insn & 0x80) {
2196 for ( ; i > 0 ; i--) {
2197 tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
2198 tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
2199 if (i > 1) {
2200 tcg_gen_addi_i32(abuf, abuf, 2);
2201 }
2202 }
2203 } else {
2204 for ( ; i > 0 ; i--) {
2205 tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
2206 tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
2207 if (i > 1) {
2208 tcg_gen_addi_i32(abuf, abuf, 2);
2209 }
2210 }
2211 }
2212 tcg_temp_free(abuf);
2213 tcg_temp_free(dbuf);
2214 }
2215
2216 DISAS_INSN(bitop_im)
2217 {
2218 int opsize;
2219 int op;
2220 TCGv src1;
2221 uint32_t mask;
2222 int bitnum;
2223 TCGv tmp;
2224 TCGv addr;
2225
2226 if ((insn & 0x38) != 0)
2227 opsize = OS_BYTE;
2228 else
2229 opsize = OS_LONG;
2230 op = (insn >> 6) & 3;
2231
2232 bitnum = read_im16(env, s);
2233 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2234 if (bitnum & 0xfe00) {
2235 disas_undef(env, s, insn);
2236 return;
2237 }
2238 } else {
2239 if (bitnum & 0xff00) {
2240 disas_undef(env, s, insn);
2241 return;
2242 }
2243 }
2244
2245 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2246
2247 gen_flush_flags(s);
2248 if (opsize == OS_BYTE)
2249 bitnum &= 7;
2250 else
2251 bitnum &= 31;
2252 mask = 1 << bitnum;
2253
2254 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2255
2256 if (op) {
2257 tmp = tcg_temp_new();
2258 switch (op) {
2259 case 1: /* bchg */
2260 tcg_gen_xori_i32(tmp, src1, mask);
2261 break;
2262 case 2: /* bclr */
2263 tcg_gen_andi_i32(tmp, src1, ~mask);
2264 break;
2265 case 3: /* bset */
2266 tcg_gen_ori_i32(tmp, src1, mask);
2267 break;
2268 default: /* btst */
2269 break;
2270 }
2271 DEST_EA(env, insn, opsize, tmp, &addr);
2272 tcg_temp_free(tmp);
2273 }
2274 }
2275
2276 static TCGv gen_get_ccr(DisasContext *s)
2277 {
2278 TCGv dest;
2279
2280 update_cc_op(s);
2281 dest = tcg_temp_new();
2282 gen_helper_get_ccr(dest, cpu_env);
2283 return dest;
2284 }
2285
2286 static TCGv gen_get_sr(DisasContext *s)
2287 {
2288 TCGv ccr;
2289 TCGv sr;
2290
2291 ccr = gen_get_ccr(s);
2292 sr = tcg_temp_new();
2293 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2294 tcg_gen_or_i32(sr, sr, ccr);
2295 tcg_temp_free(ccr);
2296 return sr;
2297 }
2298
2299 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2300 {
2301 if (ccr_only) {
2302 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2303 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2304 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2305 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2306 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2307 } else {
2308 TCGv sr = tcg_const_i32(val);
2309 gen_helper_set_sr(cpu_env, sr);
2310 tcg_temp_free(sr);
2311 }
2312 set_cc_op(s, CC_OP_FLAGS);
2313 }
2314
2315 static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
2316 {
2317 if (ccr_only) {
2318 gen_helper_set_ccr(cpu_env, val);
2319 } else {
2320 gen_helper_set_sr(cpu_env, val);
2321 }
2322 set_cc_op(s, CC_OP_FLAGS);
2323 }
2324
2325 static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2326 bool ccr_only)
2327 {
2328 if ((insn & 0x3f) == 0x3c) {
2329 uint16_t val;
2330 val = read_im16(env, s);
2331 gen_set_sr_im(s, val, ccr_only);
2332 } else {
2333 TCGv src;
2334 SRC_EA(env, src, OS_WORD, 0, NULL);
2335 gen_set_sr(s, src, ccr_only);
2336 }
2337 }
2338
2339 DISAS_INSN(arith_im)
2340 {
2341 int op;
2342 TCGv im;
2343 TCGv src1;
2344 TCGv dest;
2345 TCGv addr;
2346 int opsize;
2347 bool with_SR = ((insn & 0x3f) == 0x3c);
2348
2349 op = (insn >> 9) & 7;
2350 opsize = insn_opsize(insn);
2351 switch (opsize) {
2352 case OS_BYTE:
2353 im = tcg_const_i32((int8_t)read_im8(env, s));
2354 break;
2355 case OS_WORD:
2356 im = tcg_const_i32((int16_t)read_im16(env, s));
2357 break;
2358 case OS_LONG:
2359 im = tcg_const_i32(read_im32(env, s));
2360 break;
2361 default:
2362 g_assert_not_reached();
2363 }
2364
2365 if (with_SR) {
2366 /* SR/CCR can only be used with andi/eori/ori */
2367 if (op == 2 || op == 3 || op == 6) {
2368 disas_undef(env, s, insn);
2369 return;
2370 }
2371 switch (opsize) {
2372 case OS_BYTE:
2373 src1 = gen_get_ccr(s);
2374 break;
2375 case OS_WORD:
2376 if (IS_USER(s)) {
2377 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2378 return;
2379 }
2380 src1 = gen_get_sr(s);
2381 break;
2382 default:
2383 /* OS_LONG; others already g_assert_not_reached. */
2384 disas_undef(env, s, insn);
2385 return;
2386 }
2387 } else {
2388 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2389 }
2390 dest = tcg_temp_new();
2391 switch (op) {
2392 case 0: /* ori */
2393 tcg_gen_or_i32(dest, src1, im);
2394 if (with_SR) {
2395 gen_set_sr(s, dest, opsize == OS_BYTE);
2396 } else {
2397 DEST_EA(env, insn, opsize, dest, &addr);
2398 gen_logic_cc(s, dest, opsize);
2399 }
2400 break;
2401 case 1: /* andi */
2402 tcg_gen_and_i32(dest, src1, im);
2403 if (with_SR) {
2404 gen_set_sr(s, dest, opsize == OS_BYTE);
2405 } else {
2406 DEST_EA(env, insn, opsize, dest, &addr);
2407 gen_logic_cc(s, dest, opsize);
2408 }
2409 break;
2410 case 2: /* subi */
2411 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2412 tcg_gen_sub_i32(dest, src1, im);
2413 gen_update_cc_add(dest, im, opsize);
2414 set_cc_op(s, CC_OP_SUBB + opsize);
2415 DEST_EA(env, insn, opsize, dest, &addr);
2416 break;
2417 case 3: /* addi */
2418 tcg_gen_add_i32(dest, src1, im);
2419 gen_update_cc_add(dest, im, opsize);
2420 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2421 set_cc_op(s, CC_OP_ADDB + opsize);
2422 DEST_EA(env, insn, opsize, dest, &addr);
2423 break;
2424 case 5: /* eori */
2425 tcg_gen_xor_i32(dest, src1, im);
2426 if (with_SR) {
2427 gen_set_sr(s, dest, opsize == OS_BYTE);
2428 } else {
2429 DEST_EA(env, insn, opsize, dest, &addr);
2430 gen_logic_cc(s, dest, opsize);
2431 }
2432 break;
2433 case 6: /* cmpi */
2434 gen_update_cc_cmp(s, src1, im, opsize);
2435 break;
2436 default:
2437 abort();
2438 }
2439 tcg_temp_free(im);
2440 tcg_temp_free(dest);
2441 }
2442
2443 DISAS_INSN(cas)
2444 {
2445 int opsize;
2446 TCGv addr;
2447 uint16_t ext;
2448 TCGv load;
2449 TCGv cmp;
2450 MemOp opc;
2451
2452 switch ((insn >> 9) & 3) {
2453 case 1:
2454 opsize = OS_BYTE;
2455 opc = MO_SB;
2456 break;
2457 case 2:
2458 opsize = OS_WORD;
2459 opc = MO_TESW;
2460 break;
2461 case 3:
2462 opsize = OS_LONG;
2463 opc = MO_TESL;
2464 break;
2465 default:
2466 g_assert_not_reached();
2467 }
2468
2469 ext = read_im16(env, s);
2470
2471 /* cas Dc,Du,<EA> */
2472
2473 addr = gen_lea(env, s, insn, opsize);
2474 if (IS_NULL_QREG(addr)) {
2475 gen_addr_fault(s);
2476 return;
2477 }
2478
2479 cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
2480
2481 /*
2482 * if <EA> == Dc then
2483 * <EA> = Du
2484 * Dc = <EA> (because <EA> == Dc)
2485 * else
2486 * Dc = <EA>
2487 */
2488
2489 load = tcg_temp_new();
2490 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2491 IS_USER(s), opc);
2492 /* update flags before setting cmp to load */
2493 gen_update_cc_cmp(s, load, cmp, opsize);
2494 gen_partset_reg(opsize, DREG(ext, 0), load);
2495
2496 tcg_temp_free(load);
2497
2498 switch (extract32(insn, 3, 3)) {
2499 case 3: /* Indirect postincrement. */
2500 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2501 break;
2502 case 4: /* Indirect predecrememnt. */
2503 tcg_gen_mov_i32(AREG(insn, 0), addr);
2504 break;
2505 }
2506 }
2507
2508 DISAS_INSN(cas2w)
2509 {
2510 uint16_t ext1, ext2;
2511 TCGv addr1, addr2;
2512 TCGv regs;
2513
2514 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2515
2516 ext1 = read_im16(env, s);
2517
2518 if (ext1 & 0x8000) {
2519 /* Address Register */
2520 addr1 = AREG(ext1, 12);
2521 } else {
2522 /* Data Register */
2523 addr1 = DREG(ext1, 12);
2524 }
2525
2526 ext2 = read_im16(env, s);
2527 if (ext2 & 0x8000) {
2528 /* Address Register */
2529 addr2 = AREG(ext2, 12);
2530 } else {
2531 /* Data Register */
2532 addr2 = DREG(ext2, 12);
2533 }
2534
2535 /*
2536 * if (R1) == Dc1 && (R2) == Dc2 then
2537 * (R1) = Du1
2538 * (R2) = Du2
2539 * else
2540 * Dc1 = (R1)
2541 * Dc2 = (R2)
2542 */
2543
2544 regs = tcg_const_i32(REG(ext2, 6) |
2545 (REG(ext1, 6) << 3) |
2546 (REG(ext2, 0) << 6) |
2547 (REG(ext1, 0) << 9));
2548 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2549 gen_helper_exit_atomic(cpu_env);
2550 } else {
2551 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2552 }
2553 tcg_temp_free(regs);
2554
2555 /* Note that cas2w also assigned to env->cc_op. */
2556 s->cc_op = CC_OP_CMPW;
2557 s->cc_op_synced = 1;
2558 }
2559
2560 DISAS_INSN(cas2l)
2561 {
2562 uint16_t ext1, ext2;
2563 TCGv addr1, addr2, regs;
2564
2565 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2566
2567 ext1 = read_im16(env, s);
2568
2569 if (ext1 & 0x8000) {
2570 /* Address Register */
2571 addr1 = AREG(ext1, 12);
2572 } else {
2573 /* Data Register */
2574 addr1 = DREG(ext1, 12);
2575 }
2576
2577 ext2 = read_im16(env, s);
2578 if (ext2 & 0x8000) {
2579 /* Address Register */
2580 addr2 = AREG(ext2, 12);
2581 } else {
2582 /* Data Register */
2583 addr2 = DREG(ext2, 12);
2584 }
2585
2586 /*
2587 * if (R1) == Dc1 && (R2) == Dc2 then
2588 * (R1) = Du1
2589 * (R2) = Du2
2590 * else
2591 * Dc1 = (R1)
2592 * Dc2 = (R2)
2593 */
2594
2595 regs = tcg_const_i32(REG(ext2, 6) |
2596 (REG(ext1, 6) << 3) |
2597 (REG(ext2, 0) << 6) |
2598 (REG(ext1, 0) << 9));
2599 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2600 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2601 } else {
2602 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2603 }
2604 tcg_temp_free(regs);
2605
2606 /* Note that cas2l also assigned to env->cc_op. */
2607 s->cc_op = CC_OP_CMPL;
2608 s->cc_op_synced = 1;
2609 }
2610
2611 DISAS_INSN(byterev)
2612 {
2613 TCGv reg;
2614
2615 reg = DREG(insn, 0);
2616 tcg_gen_bswap32_i32(reg, reg);
2617 }
2618
2619 DISAS_INSN(move)
2620 {
2621 TCGv src;
2622 TCGv dest;
2623 int op;
2624 int opsize;
2625
2626 switch (insn >> 12) {
2627 case 1: /* move.b */
2628 opsize = OS_BYTE;
2629 break;
2630 case 2: /* move.l */
2631 opsize = OS_LONG;
2632 break;
2633 case 3: /* move.w */
2634 opsize = OS_WORD;
2635 break;
2636 default:
2637 abort();
2638 }
2639 SRC_EA(env, src, opsize, 1, NULL);
2640 op = (insn >> 6) & 7;
2641 if (op == 1) {
2642 /* movea */
2643 /* The value will already have been sign extended. */
2644 dest = AREG(insn, 9);
2645 tcg_gen_mov_i32(dest, src);
2646 } else {
2647 /* normal move */
2648 uint16_t dest_ea;
2649 dest_ea = ((insn >> 9) & 7) | (op << 3);
2650 DEST_EA(env, dest_ea, opsize, src, NULL);
2651 /* This will be correct because loads sign extend. */
2652 gen_logic_cc(s, src, opsize);
2653 }
2654 }
2655
2656 DISAS_INSN(negx)
2657 {
2658 TCGv z;
2659 TCGv src;
2660 TCGv addr;
2661 int opsize;
2662
2663 opsize = insn_opsize(insn);
2664 SRC_EA(env, src, opsize, 1, &addr);
2665
2666 gen_flush_flags(s); /* compute old Z */
2667
2668 /*
2669 * Perform subtract with borrow.
2670 * (X, N) = -(src + X);
2671 */
2672
2673 z = tcg_const_i32(0);
2674 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2675 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2676 tcg_temp_free(z);
2677 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2678
2679 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2680
2681 /*
2682 * Compute signed-overflow for negation. The normal formula for
2683 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2684 * this simplifies to res & src.
2685 */
2686
2687 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2688
2689 /* Copy the rest of the results into place. */
2690 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2691 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2692
2693 set_cc_op(s, CC_OP_FLAGS);
2694
2695 /* result is in QREG_CC_N */
2696
2697 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2698 }
2699
2700 DISAS_INSN(lea)
2701 {
2702 TCGv reg;
2703 TCGv tmp;
2704
2705 reg = AREG(insn, 9);
2706 tmp = gen_lea(env, s, insn, OS_LONG);
2707 if (IS_NULL_QREG(tmp)) {
2708 gen_addr_fault(s);
2709 return;
2710 }
2711 tcg_gen_mov_i32(reg, tmp);
2712 }
2713
2714 DISAS_INSN(clr)
2715 {
2716 int opsize;
2717 TCGv zero;
2718
2719 zero = tcg_const_i32(0);
2720
2721 opsize = insn_opsize(insn);
2722 DEST_EA(env, insn, opsize, zero, NULL);
2723 gen_logic_cc(s, zero, opsize);
2724 tcg_temp_free(zero);
2725 }
2726
2727 DISAS_INSN(move_from_ccr)
2728 {
2729 TCGv ccr;
2730
2731 ccr = gen_get_ccr(s);
2732 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2733 }
2734
2735 DISAS_INSN(neg)
2736 {
2737 TCGv src1;
2738 TCGv dest;
2739 TCGv addr;
2740 int opsize;
2741
2742 opsize = insn_opsize(insn);
2743 SRC_EA(env, src1, opsize, 1, &addr);
2744 dest = tcg_temp_new();
2745 tcg_gen_neg_i32(dest, src1);
2746 set_cc_op(s, CC_OP_SUBB + opsize);
2747 gen_update_cc_add(dest, src1, opsize);
2748 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2749 DEST_EA(env, insn, opsize, dest, &addr);
2750 tcg_temp_free(dest);
2751 }
2752
2753 DISAS_INSN(move_to_ccr)
2754 {
2755 gen_move_to_sr(env, s, insn, true);
2756 }
2757
2758 DISAS_INSN(not)
2759 {
2760 TCGv src1;
2761 TCGv dest;
2762 TCGv addr;
2763 int opsize;
2764
2765 opsize = insn_opsize(insn);
2766 SRC_EA(env, src1, opsize, 1, &addr);
2767 dest = tcg_temp_new();
2768 tcg_gen_not_i32(dest, src1);
2769 DEST_EA(env, insn, opsize, dest, &addr);
2770 gen_logic_cc(s, dest, opsize);
2771 }
2772
2773 DISAS_INSN(swap)
2774 {
2775 TCGv src1;
2776 TCGv src2;
2777 TCGv reg;
2778
2779 src1 = tcg_temp_new();
2780 src2 = tcg_temp_new();
2781 reg = DREG(insn, 0);
2782 tcg_gen_shli_i32(src1, reg, 16);
2783 tcg_gen_shri_i32(src2, reg, 16);
2784 tcg_gen_or_i32(reg, src1, src2);
2785 tcg_temp_free(src2);
2786 tcg_temp_free(src1);
2787 gen_logic_cc(s, reg, OS_LONG);
2788 }
2789
2790 DISAS_INSN(bkpt)
2791 {
2792 gen_exception(s, s->base.pc_next, EXCP_DEBUG);
2793 }
2794
2795 DISAS_INSN(pea)
2796 {
2797 TCGv tmp;
2798
2799 tmp = gen_lea(env, s, insn, OS_LONG);
2800 if (IS_NULL_QREG(tmp)) {
2801 gen_addr_fault(s);
2802 return;
2803 }
2804 gen_push(s, tmp);
2805 }
2806
2807 DISAS_INSN(ext)
2808 {
2809 int op;
2810 TCGv reg;
2811 TCGv tmp;
2812
2813 reg = DREG(insn, 0);
2814 op = (insn >> 6) & 7;
2815 tmp = tcg_temp_new();
2816 if (op == 3)
2817 tcg_gen_ext16s_i32(tmp, reg);
2818 else
2819 tcg_gen_ext8s_i32(tmp, reg);
2820 if (op == 2)
2821 gen_partset_reg(OS_WORD, reg, tmp);
2822 else
2823 tcg_gen_mov_i32(reg, tmp);
2824 gen_logic_cc(s, tmp, OS_LONG);
2825 tcg_temp_free(tmp);
2826 }
2827
2828 DISAS_INSN(tst)
2829 {
2830 int opsize;
2831 TCGv tmp;
2832
2833 opsize = insn_opsize(insn);
2834 SRC_EA(env, tmp, opsize, 1, NULL);
2835 gen_logic_cc(s, tmp, opsize);
2836 }
2837
2838 DISAS_INSN(pulse)
2839 {
2840 /* Implemented as a NOP. */
2841 }
2842
2843 DISAS_INSN(illegal)
2844 {
2845 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2846 }
2847
2848 /* ??? This should be atomic. */
2849 DISAS_INSN(tas)
2850 {
2851 TCGv dest;
2852 TCGv src1;
2853 TCGv addr;
2854
2855 dest = tcg_temp_new();
2856 SRC_EA(env, src1, OS_BYTE, 1, &addr);
2857 gen_logic_cc(s, src1, OS_BYTE);
2858 tcg_gen_ori_i32(dest, src1, 0x80);
2859 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2860 tcg_temp_free(dest);
2861 }
2862
2863 DISAS_INSN(mull)
2864 {
2865 uint16_t ext;
2866 TCGv src1;
2867 int sign;
2868
2869 ext = read_im16(env, s);
2870
2871 sign = ext & 0x800;
2872
2873 if (ext & 0x400) {
2874 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2875 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2876 return;
2877 }
2878
2879 SRC_EA(env, src1, OS_LONG, 0, NULL);
2880
2881 if (sign) {
2882 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2883 } else {
2884 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2885 }
2886 /* if Dl == Dh, 68040 returns low word */
2887 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2888 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2889 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2890
2891 tcg_gen_movi_i32(QREG_CC_V, 0);
2892 tcg_gen_movi_i32(QREG_CC_C, 0);
2893
2894 set_cc_op(s, CC_OP_FLAGS);
2895 return;
2896 }
2897 SRC_EA(env, src1, OS_LONG, 0, NULL);
2898 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2899 tcg_gen_movi_i32(QREG_CC_C, 0);
2900 if (sign) {
2901 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2902 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2903 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2904 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2905 } else {
2906 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2907 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2908 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2909 }
2910 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2911 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2912
2913 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2914
2915 set_cc_op(s, CC_OP_FLAGS);
2916 } else {
2917 /*
2918 * The upper 32 bits of the product are discarded, so
2919 * muls.l and mulu.l are functionally equivalent.
2920 */
2921 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2922 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2923 }
2924 }
2925
2926 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2927 {
2928 TCGv reg;
2929 TCGv tmp;
2930
2931 reg = AREG(insn, 0);
2932 tmp = tcg_temp_new();
2933 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2934 gen_store(s, OS_LONG, tmp, reg, IS_USER(s));
2935 if ((insn & 7) != 7) {
2936 tcg_gen_mov_i32(reg, tmp);
2937 }
2938 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2939 tcg_temp_free(tmp);
2940 }
2941
2942 DISAS_INSN(link)
2943 {
2944 int16_t offset;
2945
2946 offset = read_im16(env, s);
2947 gen_link(s, insn, offset);
2948 }
2949
2950 DISAS_INSN(linkl)
2951 {
2952 int32_t offset;
2953
2954 offset = read_im32(env, s);
2955 gen_link(s, insn, offset);
2956 }
2957
2958 DISAS_INSN(unlk)
2959 {
2960 TCGv src;
2961 TCGv reg;
2962 TCGv tmp;
2963
2964 src = tcg_temp_new();
2965 reg = AREG(insn, 0);
2966 tcg_gen_mov_i32(src, reg);
2967 tmp = gen_load(s, OS_LONG, src, 0, IS_USER(s));
2968 tcg_gen_mov_i32(reg, tmp);
2969 tcg_gen_addi_i32(QREG_SP, src, 4);
2970 tcg_temp_free(src);
2971 tcg_temp_free(tmp);
2972 }
2973
2974 #if defined(CONFIG_SOFTMMU)
2975 DISAS_INSN(reset)
2976 {
2977 if (IS_USER(s)) {
2978 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2979 return;
2980 }
2981
2982 gen_helper_reset(cpu_env);
2983 }
2984 #endif
2985
2986 DISAS_INSN(nop)
2987 {
2988 }
2989
2990 DISAS_INSN(rtd)
2991 {
2992 TCGv tmp;
2993 int16_t offset = read_im16(env, s);
2994
2995 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
2996 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2997 gen_jmp(s, tmp);
2998 }
2999
3000 DISAS_INSN(rtr)
3001 {
3002 TCGv tmp;
3003 TCGv ccr;
3004 TCGv sp;
3005
3006 sp = tcg_temp_new();
3007 ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
3008 tcg_gen_addi_i32(sp, QREG_SP, 2);
3009 tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
3010 tcg_gen_addi_i32(QREG_SP, sp, 4);
3011 tcg_temp_free(sp);
3012
3013 gen_set_sr(s, ccr, true);
3014 tcg_temp_free(ccr);
3015
3016 gen_jmp(s, tmp);
3017 }
3018
3019 DISAS_INSN(rts)
3020 {
3021 TCGv tmp;
3022
3023 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
3024 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
3025 gen_jmp(s, tmp);
3026 }
3027
3028 DISAS_INSN(jump)
3029 {
3030 TCGv tmp;
3031
3032 /*
3033 * Load the target address first to ensure correct exception
3034 * behavior.
3035 */
3036 tmp = gen_lea(env, s, insn, OS_LONG);
3037 if (IS_NULL_QREG(tmp)) {
3038 gen_addr_fault(s);
3039 return;
3040 }
3041 if ((insn & 0x40) == 0) {
3042 /* jsr */
3043 gen_push(s, tcg_const_i32(s->pc));
3044 }
3045 gen_jmp(s, tmp);
3046 }
3047
3048 DISAS_INSN(addsubq)
3049 {
3050 TCGv src;
3051 TCGv dest;
3052 TCGv val;
3053 int imm;
3054 TCGv addr;
3055 int opsize;
3056
3057 if ((insn & 070) == 010) {
3058 /* Operation on address register is always long. */
3059 opsize = OS_LONG;
3060 } else {
3061 opsize = insn_opsize(insn);
3062 }
3063 SRC_EA(env, src, opsize, 1, &addr);
3064 imm = (insn >> 9) & 7;
3065 if (imm == 0) {
3066 imm = 8;
3067 }
3068 val = tcg_const_i32(imm);
3069 dest = tcg_temp_new();
3070 tcg_gen_mov_i32(dest, src);
3071 if ((insn & 0x38) == 0x08) {
3072 /*
3073 * Don't update condition codes if the destination is an
3074 * address register.
3075 */
3076 if (insn & 0x0100) {
3077 tcg_gen_sub_i32(dest, dest, val);
3078 } else {
3079 tcg_gen_add_i32(dest, dest, val);
3080 }
3081 } else {
3082 if (insn & 0x0100) {
3083 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3084 tcg_gen_sub_i32(dest, dest, val);
3085 set_cc_op(s, CC_OP_SUBB + opsize);
3086 } else {
3087 tcg_gen_add_i32(dest, dest, val);
3088 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3089 set_cc_op(s, CC_OP_ADDB + opsize);
3090 }
3091 gen_update_cc_add(dest, val, opsize);
3092 }
3093 tcg_temp_free(val);
3094 DEST_EA(env, insn, opsize, dest, &addr);
3095 tcg_temp_free(dest);
3096 }
3097
3098 DISAS_INSN(tpf)
3099 {
3100 switch (insn & 7) {
3101 case 2: /* One extension word. */
3102 s->pc += 2;
3103 break;
3104 case 3: /* Two extension words. */
3105 s->pc += 4;
3106 break;
3107 case 4: /* No extension words. */
3108 break;
3109 default:
3110 disas_undef(env, s, insn);
3111 }
3112 }
3113
3114 DISAS_INSN(branch)
3115 {
3116 int32_t offset;
3117 uint32_t base;
3118 int op;
3119
3120 base = s->pc;
3121 op = (insn >> 8) & 0xf;
3122 offset = (int8_t)insn;
3123 if (offset == 0) {
3124 offset = (int16_t)read_im16(env, s);
3125 } else if (offset == -1) {
3126 offset = read_im32(env, s);
3127 }
3128 if (op == 1) {
3129 /* bsr */
3130 gen_push(s, tcg_const_i32(s->pc));
3131 }
3132 if (op > 1) {
3133 /* Bcc */
3134 TCGLabel *l1 = gen_new_label();
3135 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
3136 gen_jmp_tb(s, 1, base + offset);
3137 gen_set_label(l1);
3138 gen_jmp_tb(s, 0, s->pc);
3139 } else {
3140 /* Unconditional branch. */
3141 update_cc_op(s);
3142 gen_jmp_tb(s, 0, base + offset);
3143 }
3144 }
3145
3146 DISAS_INSN(moveq)
3147 {
3148 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
3149 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
3150 }
3151
3152 DISAS_INSN(mvzs)
3153 {
3154 int opsize;
3155 TCGv src;
3156 TCGv reg;
3157
3158 if (insn & 0x40)
3159 opsize = OS_WORD;
3160 else
3161 opsize = OS_BYTE;
3162 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
3163 reg = DREG(insn, 9);
3164 tcg_gen_mov_i32(reg, src);
3165 gen_logic_cc(s, src, opsize);
3166 }
3167
3168 DISAS_INSN(or)
3169 {
3170 TCGv reg;
3171 TCGv dest;
3172 TCGv src;
3173 TCGv addr;
3174 int opsize;
3175
3176 opsize = insn_opsize(insn);
3177 reg = gen_extend(s, DREG(insn, 9), opsize, 0);
3178 dest = tcg_temp_new();
3179 if (insn & 0x100) {
3180 SRC_EA(env, src, opsize, 0, &addr);
3181 tcg_gen_or_i32(dest, src, reg);
3182 DEST_EA(env, insn, opsize, dest, &addr);
3183 } else {
3184 SRC_EA(env, src, opsize, 0, NULL);
3185 tcg_gen_or_i32(dest, src, reg);
3186 gen_partset_reg(opsize, DREG(insn, 9), dest);
3187 }
3188 gen_logic_cc(s, dest, opsize);
3189 tcg_temp_free(dest);
3190 }
3191
3192 DISAS_INSN(suba)
3193 {
3194 TCGv src;
3195 TCGv reg;
3196
3197 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3198 reg = AREG(insn, 9);
3199 tcg_gen_sub_i32(reg, reg, src);
3200 }
3201
3202 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3203 {
3204 TCGv tmp;
3205
3206 gen_flush_flags(s); /* compute old Z */
3207
3208 /*
3209 * Perform subtract with borrow.
3210 * (X, N) = dest - (src + X);
3211 */
3212
3213 tmp = tcg_const_i32(0);
3214 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
3215 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
3216 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3217 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
3218
3219 /* Compute signed-overflow for subtract. */
3220
3221 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
3222 tcg_gen_xor_i32(tmp, dest, src);
3223 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
3224 tcg_temp_free(tmp);
3225
3226 /* Copy the rest of the results into place. */
3227 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3228 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3229
3230 set_cc_op(s, CC_OP_FLAGS);
3231
3232 /* result is in QREG_CC_N */
3233 }
3234
3235 DISAS_INSN(subx_reg)
3236 {
3237 TCGv dest;
3238 TCGv src;
3239 int opsize;
3240
3241 opsize = insn_opsize(insn);
3242
3243 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3244 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3245
3246 gen_subx(s, src, dest, opsize);
3247
3248 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3249 }
3250
3251 DISAS_INSN(subx_mem)
3252 {
3253 TCGv src;
3254 TCGv addr_src;
3255 TCGv dest;
3256 TCGv addr_dest;
3257 int opsize;
3258
3259 opsize = insn_opsize(insn);
3260
3261 addr_src = AREG(insn, 0);
3262 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3263 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3264
3265 addr_dest = AREG(insn, 9);
3266 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3267 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3268
3269 gen_subx(s, src, dest, opsize);
3270
3271 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3272
3273 tcg_temp_free(dest);
3274 tcg_temp_free(src);
3275 }
3276
3277 DISAS_INSN(mov3q)
3278 {
3279 TCGv src;
3280 int val;
3281
3282 val = (insn >> 9) & 7;
3283 if (val == 0)
3284 val = -1;
3285 src = tcg_const_i32(val);
3286 gen_logic_cc(s, src, OS_LONG);
3287 DEST_EA(env, insn, OS_LONG, src, NULL);
3288 tcg_temp_free(src);
3289 }
3290
3291 DISAS_INSN(cmp)
3292 {
3293 TCGv src;
3294 TCGv reg;
3295 int opsize;
3296
3297 opsize = insn_opsize(insn);
3298 SRC_EA(env, src, opsize, 1, NULL);
3299 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
3300 gen_update_cc_cmp(s, reg, src, opsize);
3301 }
3302
3303 DISAS_INSN(cmpa)
3304 {
3305 int opsize;
3306 TCGv src;
3307 TCGv reg;
3308
3309 if (insn & 0x100) {
3310 opsize = OS_LONG;
3311 } else {
3312 opsize = OS_WORD;
3313 }
3314 SRC_EA(env, src, opsize, 1, NULL);
3315 reg = AREG(insn, 9);
3316 gen_update_cc_cmp(s, reg, src, OS_LONG);
3317 }
3318
3319 DISAS_INSN(cmpm)
3320 {
3321 int opsize = insn_opsize(insn);
3322 TCGv src, dst;
3323
3324 /* Post-increment load (mode 3) from Ay. */
3325 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3326 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3327 /* Post-increment load (mode 3) from Ax. */
3328 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3329 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3330
3331 gen_update_cc_cmp(s, dst, src, opsize);
3332 }
3333
3334 DISAS_INSN(eor)
3335 {
3336 TCGv src;
3337 TCGv dest;
3338 TCGv addr;
3339 int opsize;
3340
3341 opsize = insn_opsize(insn);
3342
3343 SRC_EA(env, src, opsize, 0, &addr);
3344 dest = tcg_temp_new();
3345 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3346 gen_logic_cc(s, dest, opsize);
3347 DEST_EA(env, insn, opsize, dest, &addr);
3348 tcg_temp_free(dest);
3349 }
3350
3351 static void do_exg(TCGv reg1, TCGv reg2)
3352 {
3353 TCGv temp = tcg_temp_new();
3354 tcg_gen_mov_i32(temp, reg1);
3355 tcg_gen_mov_i32(reg1, reg2);
3356 tcg_gen_mov_i32(reg2, temp);
3357 tcg_temp_free(temp);
3358 }
3359
3360 DISAS_INSN(exg_dd)
3361 {
3362 /* exchange Dx and Dy */
3363 do_exg(DREG(insn, 9), DREG(insn, 0));
3364 }
3365
3366 DISAS_INSN(exg_aa)
3367 {
3368 /* exchange Ax and Ay */
3369 do_exg(AREG(insn, 9), AREG(insn, 0));
3370 }
3371
3372 DISAS_INSN(exg_da)
3373 {
3374 /* exchange Dx and Ay */
3375 do_exg(DREG(insn, 9), AREG(insn, 0));
3376 }
3377
3378 DISAS_INSN(and)
3379 {
3380 TCGv src;
3381 TCGv reg;
3382 TCGv dest;
3383 TCGv addr;
3384 int opsize;
3385
3386 dest = tcg_temp_new();
3387
3388 opsize = insn_opsize(insn);
3389 reg = DREG(insn, 9);
3390 if (insn & 0x100) {
3391 SRC_EA(env, src, opsize, 0, &addr);
3392 tcg_gen_and_i32(dest, src, reg);
3393 DEST_EA(env, insn, opsize, dest, &addr);
3394 } else {
3395 SRC_EA(env, src, opsize, 0, NULL);
3396 tcg_gen_and_i32(dest, src, reg);
3397 gen_partset_reg(opsize, reg, dest);
3398 }
3399 gen_logic_cc(s, dest, opsize);
3400 tcg_temp_free(dest);
3401 }
3402
3403 DISAS_INSN(adda)
3404 {
3405 TCGv src;
3406 TCGv reg;
3407
3408 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3409 reg = AREG(insn, 9);
3410 tcg_gen_add_i32(reg, reg, src);
3411 }
3412
3413 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3414 {
3415 TCGv tmp;
3416
3417 gen_flush_flags(s); /* compute old Z */
3418
3419 /*
3420 * Perform addition with carry.
3421 * (X, N) = src + dest + X;
3422 */
3423
3424 tmp = tcg_const_i32(0);
3425 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3426 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3427 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3428
3429 /* Compute signed-overflow for addition. */
3430
3431 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3432 tcg_gen_xor_i32(tmp, dest, src);
3433 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3434 tcg_temp_free(tmp);
3435
3436 /* Copy the rest of the results into place. */
3437 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3438 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3439
3440 set_cc_op(s, CC_OP_FLAGS);
3441
3442 /* result is in QREG_CC_N */
3443 }
3444
3445 DISAS_INSN(addx_reg)
3446 {
3447 TCGv dest;
3448 TCGv src;
3449 int opsize;
3450
3451 opsize = insn_opsize(insn);
3452
3453 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3454 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3455
3456 gen_addx(s, src, dest, opsize);
3457
3458 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3459 }
3460
3461 DISAS_INSN(addx_mem)
3462 {
3463 TCGv src;
3464 TCGv addr_src;
3465 TCGv dest;
3466 TCGv addr_dest;
3467 int opsize;
3468
3469 opsize = insn_opsize(insn);
3470
3471 addr_src = AREG(insn, 0);
3472 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3473 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3474
3475 addr_dest = AREG(insn, 9);
3476 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3477 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3478
3479 gen_addx(s, src, dest, opsize);
3480
3481 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3482
3483 tcg_temp_free(dest);
3484 tcg_temp_free(src);
3485 }
3486
3487 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3488 {
3489 int count = (insn >> 9) & 7;
3490 int logical = insn & 8;
3491 int left = insn & 0x100;
3492 int bits = opsize_bytes(opsize) * 8;
3493 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3494
3495 if (count == 0) {
3496 count = 8;
3497 }
3498
3499 tcg_gen_movi_i32(QREG_CC_V, 0);
3500 if (left) {
3501 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3502 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3503
3504 /*
3505 * Note that ColdFire always clears V (done above),
3506 * while M68000 sets if the most significant bit is changed at
3507 * any time during the shift operation.
3508 */
3509 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3510 /* if shift count >= bits, V is (reg != 0) */
3511 if (count >= bits) {
3512 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3513 } else {
3514 TCGv t0 = tcg_temp_new();
3515 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3516 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3517 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3518 tcg_temp_free(t0);
3519 }
3520 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3521 }
3522 } else {
3523 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3524 if (logical) {
3525 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3526 } else {
3527 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3528 }
3529 }
3530
3531 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3532 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3533 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3534 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3535
3536 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3537 set_cc_op(s, CC_OP_FLAGS);
3538 }
3539
3540 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3541 {
3542 int logical = insn & 8;
3543 int left = insn & 0x100;
3544 int bits = opsize_bytes(opsize) * 8;
3545 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3546 TCGv s32;
3547 TCGv_i64 t64, s64;
3548
3549 t64 = tcg_temp_new_i64();
3550 s64 = tcg_temp_new_i64();
3551 s32 = tcg_temp_new();
3552
3553 /*
3554 * Note that m68k truncates the shift count modulo 64, not 32.
3555 * In addition, a 64-bit shift makes it easy to find "the last
3556 * bit shifted out", for the carry flag.
3557 */
3558 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3559 tcg_gen_extu_i32_i64(s64, s32);
3560 tcg_gen_extu_i32_i64(t64, reg);
3561
3562 /* Optimistically set V=0. Also used as a zero source below. */
3563 tcg_gen_movi_i32(QREG_CC_V, 0);
3564 if (left) {
3565 tcg_gen_shl_i64(t64, t64, s64);
3566
3567 if (opsize == OS_LONG) {
3568 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3569 /* Note that C=0 if shift count is 0, and we get that for free. */
3570 } else {
3571 TCGv zero = tcg_const_i32(0);
3572 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3573 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3574 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3575 s32, zero, zero, QREG_CC_C);
3576 tcg_temp_free(zero);
3577 }
3578 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3579
3580 /* X = C, but only if the shift count was non-zero. */
3581 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3582 QREG_CC_C, QREG_CC_X);
3583
3584 /*
3585 * M68000 sets V if the most significant bit is changed at
3586 * any time during the shift operation. Do this via creating
3587 * an extension of the sign bit, comparing, and discarding
3588 * the bits below the sign bit. I.e.
3589 * int64_t s = (intN_t)reg;
3590 * int64_t t = (int64_t)(intN_t)reg << count;
3591 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3592 */
3593 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3594 TCGv_i64 tt = tcg_const_i64(32);
3595 /* if shift is greater than 32, use 32 */
3596 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3597 tcg_temp_free_i64(tt);
3598 /* Sign extend the input to 64 bits; re-do the shift. */
3599 tcg_gen_ext_i32_i64(t64, reg);
3600 tcg_gen_shl_i64(s64, t64, s64);
3601 /* Clear all bits that are unchanged. */
3602 tcg_gen_xor_i64(t64, t64, s64);
3603 /* Ignore the bits below the sign bit. */
3604 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3605 /* If any bits remain set, we have overflow. */
3606 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3607 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3608 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3609 }
3610 } else {
3611 tcg_gen_shli_i64(t64, t64, 32);
3612 if (logical) {
3613 tcg_gen_shr_i64(t64, t64, s64);
3614 } else {
3615 tcg_gen_sar_i64(t64, t64, s64);
3616 }
3617 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3618
3619 /* Note that C=0 if shift count is 0, and we get that for free. */
3620 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3621
3622 /* X = C, but only if the shift count was non-zero. */
3623 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3624 QREG_CC_C, QREG_CC_X);
3625 }
3626 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3627 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3628
3629 tcg_temp_free(s32);
3630 tcg_temp_free_i64(s64);
3631 tcg_temp_free_i64(t64);
3632
3633 /* Write back the result. */
3634 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3635 set_cc_op(s, CC_OP_FLAGS);
3636 }
3637
3638 DISAS_INSN(shift8_im)
3639 {
3640 shift_im(s, insn, OS_BYTE);
3641 }
3642
3643 DISAS_INSN(shift16_im)
3644 {
3645 shift_im(s, insn, OS_WORD);
3646 }
3647
3648 DISAS_INSN(shift_im)
3649 {
3650 shift_im(s, insn, OS_LONG);
3651 }
3652
3653 DISAS_INSN(shift8_reg)
3654 {
3655 shift_reg(s, insn, OS_BYTE);
3656 }
3657
3658 DISAS_INSN(shift16_reg)
3659 {
3660 shift_reg(s, insn, OS_WORD);
3661 }
3662
3663 DISAS_INSN(shift_reg)
3664 {
3665 shift_reg(s, insn, OS_LONG);
3666 }
3667
3668 DISAS_INSN(shift_mem)
3669 {
3670 int logical = insn & 8;
3671 int left = insn & 0x100;
3672 TCGv src;
3673 TCGv addr;
3674
3675 SRC_EA(env, src, OS_WORD, !logical, &addr);
3676 tcg_gen_movi_i32(QREG_CC_V, 0);
3677 if (left) {
3678 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3679 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3680
3681 /*
3682 * Note that ColdFire always clears V,
3683 * while M68000 sets if the most significant bit is changed at
3684 * any time during the shift operation
3685 */
3686 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3687 src = gen_extend(s, src, OS_WORD, 1);
3688 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3689 }
3690 } else {
3691 tcg_gen_mov_i32(QREG_CC_C, src);
3692 if (logical) {
3693 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3694 } else {
3695 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3696 }
3697 }
3698
3699 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3700 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3701 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3702 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3703
3704 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3705 set_cc_op(s, CC_OP_FLAGS);
3706 }
3707
3708 static void rotate(TCGv reg, TCGv shift, int left, int size)
3709 {
3710 switch (size) {
3711 case 8:
3712 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3713 tcg_gen_ext8u_i32(reg, reg);
3714 tcg_gen_muli_i32(reg, reg, 0x01010101);
3715 goto do_long;
3716 case 16:
3717 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3718 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3719 goto do_long;
3720 do_long:
3721 default:
3722 if (left) {
3723 tcg_gen_rotl_i32(reg, reg, shift);
3724 } else {
3725 tcg_gen_rotr_i32(reg, reg, shift);
3726 }
3727 }
3728
3729 /* compute flags */
3730
3731 switch (size) {
3732 case 8:
3733 tcg_gen_ext8s_i32(reg, reg);
3734 break;
3735 case 16:
3736 tcg_gen_ext16s_i32(reg, reg);
3737 break;
3738 default:
3739 break;
3740 }
3741
3742 /* QREG_CC_X is not affected */
3743
3744 tcg_gen_mov_i32(QREG_CC_N, reg);
3745 tcg_gen_mov_i32(QREG_CC_Z, reg);
3746
3747 if (left) {
3748 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3749 } else {
3750 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3751 }
3752
3753 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3754 }
3755
3756 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3757 {
3758 switch (size) {
3759 case 8:
3760 tcg_gen_ext8s_i32(reg, reg);
3761 break;
3762 case 16:
3763 tcg_gen_ext16s_i32(reg, reg);
3764 break;
3765 default:
3766 break;
3767 }
3768 tcg_gen_mov_i32(QREG_CC_N, reg);
3769 tcg_gen_mov_i32(QREG_CC_Z, reg);
3770 tcg_gen_mov_i32(QREG_CC_X, X);
3771 tcg_gen_mov_i32(QREG_CC_C, X);
3772 tcg_gen_movi_i32(QREG_CC_V, 0);
3773 }
3774
3775 /* Result of rotate_x() is valid if 0 <= shift <= size */
3776 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3777 {
3778 TCGv X, shl, shr, shx, sz, zero;
3779
3780 sz = tcg_const_i32(size);
3781
3782 shr = tcg_temp_new();
3783 shl = tcg_temp_new();
3784 shx = tcg_temp_new();
3785 if (left) {
3786 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3787 tcg_gen_movi_i32(shr, size + 1);
3788 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3789 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3790 /* shx = shx < 0 ? size : shx; */
3791 zero = tcg_const_i32(0);
3792 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3793 tcg_temp_free(zero);
3794 } else {
3795 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3796 tcg_gen_movi_i32(shl, size + 1);
3797 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3798 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3799 }
3800 tcg_temp_free_i32(sz);
3801
3802 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3803
3804 tcg_gen_shl_i32(shl, reg, shl);
3805 tcg_gen_shr_i32(shr, reg, shr);
3806 tcg_gen_or_i32(reg, shl, shr);
3807 tcg_temp_free(shl);
3808 tcg_temp_free(shr);
3809 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3810 tcg_gen_or_i32(reg, reg, shx);
3811 tcg_temp_free(shx);
3812
3813 /* X = (reg >> size) & 1 */
3814
3815 X = tcg_temp_new();
3816 tcg_gen_extract_i32(X, reg, size, 1);
3817
3818 return X;
3819 }
3820
3821 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3822 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3823 {
3824 TCGv_i64 t0, shift64;
3825 TCGv X, lo, hi, zero;
3826
3827 shift64 = tcg_temp_new_i64();
3828 tcg_gen_extu_i32_i64(shift64, shift);
3829
3830 t0 = tcg_temp_new_i64();
3831
3832 X = tcg_temp_new();
3833 lo = tcg_temp_new();
3834 hi = tcg_temp_new();
3835
3836 if (left) {
3837 /* create [reg:X:..] */
3838
3839 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3840 tcg_gen_concat_i32_i64(t0, lo, reg);
3841
3842 /* rotate */
3843
3844 tcg_gen_rotl_i64(t0, t0, shift64);
3845 tcg_temp_free_i64(shift64);
3846
3847 /* result is [reg:..:reg:X] */
3848
3849 tcg_gen_extr_i64_i32(lo, hi, t0);
3850 tcg_gen_andi_i32(X, lo, 1);
3851
3852 tcg_gen_shri_i32(lo, lo, 1);
3853 } else {
3854 /* create [..:X:reg] */
3855
3856 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3857
3858 tcg_gen_rotr_i64(t0, t0, shift64);
3859 tcg_temp_free_i64(shift64);
3860
3861 /* result is value: [X:reg:..:reg] */
3862
3863 tcg_gen_extr_i64_i32(lo, hi, t0);
3864
3865 /* extract X */
3866
3867 tcg_gen_shri_i32(X, hi, 31);
3868
3869 /* extract result */
3870
3871 tcg_gen_shli_i32(hi, hi, 1);
3872 }
3873 tcg_temp_free_i64(t0);
3874 tcg_gen_or_i32(lo, lo, hi);
3875 tcg_temp_free(hi);
3876
3877 /* if shift == 0, register and X are not affected */
3878
3879 zero = tcg_const_i32(0);
3880 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3881 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3882 tcg_temp_free(zero);
3883 tcg_temp_free(lo);
3884
3885 return X;
3886 }
3887
3888 DISAS_INSN(rotate_im)
3889 {
3890 TCGv shift;
3891 int tmp;
3892 int left = (insn & 0x100);
3893
3894 tmp = (insn >> 9) & 7;
3895 if (tmp == 0) {
3896 tmp = 8;
3897 }
3898
3899 shift = tcg_const_i32(tmp);
3900 if (insn & 8) {
3901 rotate(DREG(insn, 0), shift, left, 32);
3902 } else {
3903 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3904 rotate_x_flags(DREG(insn, 0), X, 32);
3905 tcg_temp_free(X);
3906 }
3907 tcg_temp_free(shift);
3908
3909 set_cc_op(s, CC_OP_FLAGS);
3910 }
3911
3912 DISAS_INSN(rotate8_im)
3913 {
3914 int left = (insn & 0x100);
3915 TCGv reg;
3916 TCGv shift;
3917 int tmp;
3918
3919 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3920
3921 tmp = (insn >> 9) & 7;
3922 if (tmp == 0) {
3923 tmp = 8;
3924 }
3925
3926 shift = tcg_const_i32(tmp);
3927 if (insn & 8) {
3928 rotate(reg, shift, left, 8);
3929 } else {
3930 TCGv X = rotate_x(reg, shift, left, 8);
3931 rotate_x_flags(reg, X, 8);
3932 tcg_temp_free(X);
3933 }
3934 tcg_temp_free(shift);
3935 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3936 set_cc_op(s, CC_OP_FLAGS);
3937 }
3938
3939 DISAS_INSN(rotate16_im)
3940 {
3941 int left = (insn & 0x100);
3942 TCGv reg;
3943 TCGv shift;
3944 int tmp;
3945
3946 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3947 tmp = (insn >> 9) & 7;
3948 if (tmp == 0) {
3949 tmp = 8;
3950 }
3951
3952 shift = tcg_const_i32(tmp);
3953 if (insn & 8) {
3954 rotate(reg, shift, left, 16);
3955 } else {
3956 TCGv X = rotate_x(reg, shift, left, 16);
3957 rotate_x_flags(reg, X, 16);
3958 tcg_temp_free(X);
3959 }
3960 tcg_temp_free(shift);
3961 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3962 set_cc_op(s, CC_OP_FLAGS);
3963 }
3964
3965 DISAS_INSN(rotate_reg)
3966 {
3967 TCGv reg;
3968 TCGv src;
3969 TCGv t0, t1;
3970 int left = (insn & 0x100);
3971
3972 reg = DREG(insn, 0);
3973 src = DREG(insn, 9);
3974 /* shift in [0..63] */
3975 t0 = tcg_temp_new();
3976 tcg_gen_andi_i32(t0, src, 63);
3977 t1 = tcg_temp_new_i32();
3978 if (insn & 8) {
3979 tcg_gen_andi_i32(t1, src, 31);
3980 rotate(reg, t1, left, 32);
3981 /* if shift == 0, clear C */
3982 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3983 t0, QREG_CC_V /* 0 */,
3984 QREG_CC_V /* 0 */, QREG_CC_C);
3985 } else {
3986 TCGv X;
3987 /* modulo 33 */
3988 tcg_gen_movi_i32(t1, 33);
3989 tcg_gen_remu_i32(t1, t0, t1);
3990 X = rotate32_x(DREG(insn, 0), t1, left);
3991 rotate_x_flags(DREG(insn, 0), X, 32);
3992 tcg_temp_free(X);
3993 }
3994 tcg_temp_free(t1);
3995 tcg_temp_free(t0);
3996 set_cc_op(s, CC_OP_FLAGS);
3997 }
3998
3999 DISAS_INSN(rotate8_reg)
4000 {
4001 TCGv reg;
4002 TCGv src;
4003 TCGv t0, t1;
4004 int left = (insn & 0x100);
4005
4006 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
4007 src = DREG(insn, 9);
4008 /* shift in [0..63] */
4009 t0 = tcg_temp_new_i32();
4010 tcg_gen_andi_i32(t0, src, 63);
4011 t1 = tcg_temp_new_i32();
4012 if (insn & 8) {
4013 tcg_gen_andi_i32(t1, src, 7);
4014 rotate(reg, t1, left, 8);
4015 /* if shift == 0, clear C */
4016 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4017 t0, QREG_CC_V /* 0 */,
4018 QREG_CC_V /* 0 */, QREG_CC_C);
4019 } else {
4020 TCGv X;
4021 /* modulo 9 */
4022 tcg_gen_movi_i32(t1, 9);
4023 tcg_gen_remu_i32(t1, t0, t1);
4024 X = rotate_x(reg, t1, left, 8);
4025 rotate_x_flags(reg, X, 8);
4026 tcg_temp_free(X);
4027 }
4028 tcg_temp_free(t1);
4029 tcg_temp_free(t0);
4030 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
4031 set_cc_op(s, CC_OP_FLAGS);
4032 }
4033
4034 DISAS_INSN(rotate16_reg)
4035 {
4036 TCGv reg;
4037 TCGv src;
4038 TCGv t0, t1;
4039 int left = (insn & 0x100);
4040
4041 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
4042 src = DREG(insn, 9);
4043 /* shift in [0..63] */
4044 t0 = tcg_temp_new_i32();
4045 tcg_gen_andi_i32(t0, src, 63);
4046 t1 = tcg_temp_new_i32();
4047 if (insn & 8) {
4048 tcg_gen_andi_i32(t1, src, 15);
4049 rotate(reg, t1, left, 16);
4050 /* if shift == 0, clear C */
4051 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4052 t0, QREG_CC_V /* 0 */,
4053 QREG_CC_V /* 0 */, QREG_CC_C);
4054 } else {
4055 TCGv X;
4056 /* modulo 17 */
4057 tcg_gen_movi_i32(t1, 17);
4058 tcg_gen_remu_i32(t1, t0, t1);
4059 X = rotate_x(reg, t1, left, 16);
4060 rotate_x_flags(reg, X, 16);
4061 tcg_temp_free(X);
4062 }
4063 tcg_temp_free(t1);
4064 tcg_temp_free(t0);
4065 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
4066 set_cc_op(s, CC_OP_FLAGS);
4067 }
4068
4069 DISAS_INSN(rotate_mem)
4070 {
4071 TCGv src;
4072 TCGv addr;
4073 TCGv shift;
4074 int left = (insn & 0x100);
4075
4076 SRC_EA(env, src, OS_WORD, 0, &addr);
4077
4078 shift = tcg_const_i32(1);
4079 if (insn & 0x0200) {
4080 rotate(src, shift, left, 16);
4081 } else {
4082 TCGv X = rotate_x(src, shift, left, 16);
4083 rotate_x_flags(src, X, 16);
4084 tcg_temp_free(X);
4085 }
4086 tcg_temp_free(shift);
4087 DEST_EA(env, insn, OS_WORD, src, &addr);
4088 set_cc_op(s, CC_OP_FLAGS);
4089 }
4090
4091 DISAS_INSN(bfext_reg)
4092 {
4093 int ext = read_im16(env, s);
4094 int is_sign = insn & 0x200;
4095 TCGv src = DREG(insn, 0);
4096 TCGv dst = DREG(ext, 12);
4097 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4098 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4099 int pos = 32 - ofs - len; /* little bit-endian */
4100 TCGv tmp = tcg_temp_new();
4101 TCGv shift;
4102
4103 /*
4104 * In general, we're going to rotate the field so that it's at the
4105 * top of the word and then right-shift by the complement of the
4106 * width to extend the field.
4107 */
4108 if (ext & 0x20) {
4109 /* Variable width. */
4110 if (ext & 0x800) {
4111 /* Variable offset. */
4112 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4113 tcg_gen_rotl_i32(tmp, src, tmp);
4114 } else {
4115 tcg_gen_rotli_i32(tmp, src, ofs);
4116 }
4117
4118 shift = tcg_temp_new();
4119 tcg_gen_neg_i32(shift, DREG(ext, 0));
4120 tcg_gen_andi_i32(shift, shift, 31);
4121 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
4122 if (is_sign) {
4123 tcg_gen_mov_i32(dst, QREG_CC_N);
4124 } else {
4125 tcg_gen_shr_i32(dst, tmp, shift);
4126 }
4127 tcg_temp_free(shift);
4128 } else {
4129 /* Immediate width. */
4130 if (ext & 0x800) {
4131 /* Variable offset */
4132 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4133 tcg_gen_rotl_i32(tmp, src, tmp);
4134 src = tmp;
4135 pos = 32 - len;
4136 } else {
4137 /*
4138 * Immediate offset. If the field doesn't wrap around the
4139 * end of the word, rely on (s)extract completely.
4140 */
4141 if (pos < 0) {
4142 tcg_gen_rotli_i32(tmp, src, ofs);
4143 src = tmp;
4144 pos = 32 - len;
4145 }
4146 }
4147
4148 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
4149 if (is_sign) {
4150 tcg_gen_mov_i32(dst, QREG_CC_N);
4151 } else {
4152 tcg_gen_extract_i32(dst, src, pos, len);
4153 }
4154 }
4155
4156 tcg_temp_free(tmp);
4157 set_cc_op(s, CC_OP_LOGIC);
4158 }
4159
4160 DISAS_INSN(bfext_mem)
4161 {
4162 int ext = read_im16(env, s);
4163 int is_sign = insn & 0x200;
4164 TCGv dest = DREG(ext, 12);
4165 TCGv addr, len, ofs;
4166
4167 addr = gen_lea(env, s, insn, OS_UNSIZED);
4168 if (IS_NULL_QREG(addr)) {
4169 gen_addr_fault(s);
4170 return;
4171 }
4172
4173 if (ext & 0x20) {
4174 len = DREG(ext, 0);
4175 } else {
4176 len = tcg_const_i32(extract32(ext, 0, 5));
4177 }
4178 if (ext & 0x800) {
4179 ofs = DREG(ext, 6);
4180 } else {
4181 ofs = tcg_const_i32(extract32(ext, 6, 5));
4182 }
4183
4184 if (is_sign) {
4185 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
4186 tcg_gen_mov_i32(QREG_CC_N, dest);
4187 } else {
4188 TCGv_i64 tmp = tcg_temp_new_i64();
4189 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
4190 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
4191 tcg_temp_free_i64(tmp);
4192 }
4193 set_cc_op(s, CC_OP_LOGIC);
4194
4195 if (!(ext & 0x20)) {
4196 tcg_temp_free(len);
4197 }
4198 if (!(ext & 0x800)) {
4199 tcg_temp_free(ofs);
4200 }
4201 }
4202
4203 DISAS_INSN(bfop_reg)
4204 {
4205 int ext = read_im16(env, s);
4206 TCGv src = DREG(insn, 0);
4207 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4208 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4209 TCGv mask, tofs, tlen;
4210
4211 tofs = NULL;
4212 tlen = NULL;
4213 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
4214 tofs = tcg_temp_new();
4215 tlen = tcg_temp_new();
4216 }
4217
4218 if ((ext & 0x820) == 0) {
4219 /* Immediate width and offset. */
4220 uint32_t maski = 0x7fffffffu >> (len - 1);
4221 if (ofs + len <= 32) {
4222 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
4223 } else {
4224 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4225 }
4226 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
4227 mask = tcg_const_i32(ror32(maski, ofs));
4228 if (tofs) {
4229 tcg_gen_movi_i32(tofs, ofs);
4230 tcg_gen_movi_i32(tlen, len);
4231 }
4232 } else {
4233 TCGv tmp = tcg_temp_new();
4234 if (ext & 0x20) {
4235 /* Variable width */
4236 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
4237 tcg_gen_andi_i32(tmp, tmp, 31);
4238 mask = tcg_const_i32(0x7fffffffu);
4239 tcg_gen_shr_i32(mask, mask, tmp);
4240 if (tlen) {
4241 tcg_gen_addi_i32(tlen, tmp, 1);
4242 }
4243 } else {
4244 /* Immediate width */
4245 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
4246 if (tlen) {
4247 tcg_gen_movi_i32(tlen, len);
4248 }
4249 }
4250 if (ext & 0x800) {
4251 /* Variable offset */
4252 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4253 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
4254 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4255 tcg_gen_rotr_i32(mask, mask, tmp);
4256 if (tofs) {
4257 tcg_gen_mov_i32(tofs, tmp);
4258 }
4259 } else {
4260 /* Immediate offset (and variable width) */
4261 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4262 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4263 tcg_gen_rotri_i32(mask, mask, ofs);
4264 if (tofs) {
4265 tcg_gen_movi_i32(tofs, ofs);
4266 }
4267 }
4268 tcg_temp_free(tmp);
4269 }
4270 set_cc_op(s, CC_OP_LOGIC);
4271
4272 switch (insn & 0x0f00) {
4273 case 0x0a00: /* bfchg */
4274 tcg_gen_eqv_i32(src, src, mask);
4275 break;
4276 case 0x0c00: /* bfclr */
4277 tcg_gen_and_i32(src, src, mask);
4278 break;
4279 case 0x0d00: /* bfffo */
4280 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4281 tcg_temp_free(tlen);
4282 tcg_temp_free(tofs);
4283 break;
4284 case 0x0e00: /* bfset */
4285 tcg_gen_orc_i32(src, src, mask);
4286 break;
4287 case 0x0800: /* bftst */
4288 /* flags already set; no other work to do. */
4289 break;
4290 default:
4291 g_assert_not_reached();
4292 }
4293 tcg_temp_free(mask);
4294 }
4295
4296 DISAS_INSN(bfop_mem)
4297 {
4298 int ext = read_im16(env, s);
4299 TCGv addr, len, ofs;
4300 TCGv_i64 t64;
4301
4302 addr = gen_lea(env, s, insn, OS_UNSIZED);
4303 if (IS_NULL_QREG(addr)) {
4304 gen_addr_fault(s);
4305 return;
4306 }
4307
4308 if (ext & 0x20) {
4309 len = DREG(ext, 0);
4310 } else {
4311 len = tcg_const_i32(extract32(ext, 0, 5));
4312 }
4313 if (ext & 0x800) {
4314 ofs = DREG(ext, 6);
4315 } else {
4316 ofs = tcg_const_i32(extract32(ext, 6, 5));
4317 }
4318
4319 switch (insn & 0x0f00) {
4320 case 0x0a00: /* bfchg */
4321 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4322 break;
4323 case 0x0c00: /* bfclr */
4324 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4325 break;
4326 case 0x0d00: /* bfffo */
4327 t64 = tcg_temp_new_i64();
4328 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4329 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4330 tcg_temp_free_i64(t64);
4331 break;
4332 case 0x0e00: /* bfset */
4333 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4334 break;
4335 case 0x0800: /* bftst */
4336 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4337 break;
4338 default:
4339 g_assert_not_reached();
4340 }
4341 set_cc_op(s, CC_OP_LOGIC);
4342
4343 if (!(ext & 0x20)) {
4344 tcg_temp_free(len);
4345 }
4346 if (!(ext & 0x800)) {
4347 tcg_temp_free(ofs);
4348 }
4349 }
4350
4351 DISAS_INSN(bfins_reg)
4352 {
4353 int ext = read_im16(env, s);
4354 TCGv dst = DREG(insn, 0);
4355 TCGv src = DREG(ext, 12);
4356 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4357 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4358 int pos = 32 - ofs - len; /* little bit-endian */
4359 TCGv tmp;
4360
4361 tmp = tcg_temp_new();
4362
4363 if (ext & 0x20) {
4364 /* Variable width */
4365 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4366 tcg_gen_andi_i32(tmp, tmp, 31);
4367 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4368 } else {
4369 /* Immediate width */
4370 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4371 }
4372 set_cc_op(s, CC_OP_LOGIC);
4373
4374 /* Immediate width and offset */
4375 if ((ext & 0x820) == 0) {
4376 /* Check for suitability for deposit. */
4377 if (pos >= 0) {
4378 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4379 } else {
4380 uint32_t maski = -2U << (len - 1);
4381 uint32_t roti = (ofs + len) & 31;
4382 tcg_gen_andi_i32(tmp, src, ~maski);
4383 tcg_gen_rotri_i32(tmp, tmp, roti);
4384 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4385 tcg_gen_or_i32(dst, dst, tmp);
4386 }
4387 } else {
4388 TCGv mask = tcg_temp_new();
4389 TCGv rot = tcg_temp_new();
4390
4391 if (ext & 0x20) {
4392 /* Variable width */
4393 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4394 tcg_gen_andi_i32(rot, rot, 31);
4395 tcg_gen_movi_i32(mask, -2);
4396 tcg_gen_shl_i32(mask, mask, rot);
4397 tcg_gen_mov_i32(rot, DREG(ext, 0));
4398 tcg_gen_andc_i32(tmp, src, mask);
4399 } else {
4400 /* Immediate width (variable offset) */
4401 uint32_t maski = -2U << (len - 1);
4402 tcg_gen_andi_i32(tmp, src, ~maski);
4403 tcg_gen_movi_i32(mask, maski);
4404 tcg_gen_movi_i32(rot, len & 31);
4405 }
4406 if (ext & 0x800) {
4407 /* Variable offset */
4408 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4409 } else {
4410 /* Immediate offset (variable width) */
4411 tcg_gen_addi_i32(rot, rot, ofs);
4412 }
4413 tcg_gen_andi_i32(rot, rot, 31);
4414 tcg_gen_rotr_i32(mask, mask, rot);
4415 tcg_gen_rotr_i32(tmp, tmp, rot);
4416 tcg_gen_and_i32(dst, dst, mask);
4417 tcg_gen_or_i32(dst, dst, tmp);
4418
4419 tcg_temp_free(rot);
4420 tcg_temp_free(mask);
4421 }
4422 tcg_temp_free(tmp);
4423 }
4424
4425 DISAS_INSN(bfins_mem)
4426 {
4427 int ext = read_im16(env, s);
4428 TCGv src = DREG(ext, 12);
4429 TCGv addr, len, ofs;
4430
4431 addr = gen_lea(env, s, insn, OS_UNSIZED);
4432 if (IS_NULL_QREG(addr)) {
4433 gen_addr_fault(s);
4434 return;
4435 }
4436
4437 if (ext & 0x20) {
4438 len = DREG(ext, 0);
4439 } else {
4440 len = tcg_const_i32(extract32(ext, 0, 5));
4441 }
4442 if (ext & 0x800) {
4443 ofs = DREG(ext, 6);
4444 } else {
4445 ofs = tcg_const_i32(extract32(ext, 6, 5));
4446 }
4447
4448 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4449 set_cc_op(s, CC_OP_LOGIC);
4450
4451 if (!(ext & 0x20)) {
4452 tcg_temp_free(len);
4453 }
4454 if (!(ext & 0x800)) {
4455 tcg_temp_free(ofs);
4456 }
4457 }
4458
4459 DISAS_INSN(ff1)
4460 {
4461 TCGv reg;
4462 reg = DREG(insn, 0);
4463 gen_logic_cc(s, reg, OS_LONG);
4464 gen_helper_ff1(reg, reg);
4465 }
4466
4467 DISAS_INSN(chk)
4468 {
4469 TCGv src, reg;
4470 int opsize;
4471
4472 switch ((insn >> 7) & 3) {
4473 case 3:
4474 opsize = OS_WORD;
4475 break;
4476 case 2:
4477 if (m68k_feature(env, M68K_FEATURE_CHK2)) {
4478 opsize = OS_LONG;
4479 break;
4480 }
4481 /* fallthru */
4482 default:
4483 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4484 return;
4485 }
4486 SRC_EA(env, src, opsize, 1, NULL);
4487 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
4488
4489 gen_flush_flags(s);
4490 gen_helper_chk(cpu_env, reg, src);
4491 }
4492
4493 DISAS_INSN(chk2)
4494 {
4495 uint16_t ext;
4496 TCGv addr1, addr2, bound1, bound2, reg;
4497 int opsize;
4498
4499 switch ((insn >> 9) & 3) {
4500 case 0:
4501 opsize = OS_BYTE;
4502 break;
4503 case 1:
4504 opsize = OS_WORD;
4505 break;
4506 case 2:
4507 opsize = OS_LONG;
4508 break;
4509 default:
4510 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4511 return;
4512 }
4513
4514 ext = read_im16(env, s);
4515 if ((ext & 0x0800) == 0) {
4516 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4517 return;
4518 }
4519
4520 addr1 = gen_lea(env, s, insn, OS_UNSIZED);
4521 addr2 = tcg_temp_new();
4522 tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize));
4523
4524 bound1 = gen_load(s, opsize, addr1, 1, IS_USER(s));
4525 tcg_temp_free(addr1);
4526 bound2 = gen_load(s, opsize, addr2, 1, IS_USER(s));
4527 tcg_temp_free(addr2);
4528
4529 reg = tcg_temp_new();
4530 if (ext & 0x8000) {
4531 tcg_gen_mov_i32(reg, AREG(ext, 12));
4532 } else {
4533 gen_ext(reg, DREG(ext, 12), opsize, 1);
4534 }
4535
4536 gen_flush_flags(s);
4537 gen_helper_chk2(cpu_env, reg, bound1, bound2);
4538 tcg_temp_free(reg);
4539 tcg_temp_free(bound1);
4540 tcg_temp_free(bound2);
4541 }
4542
4543 static void m68k_copy_line(TCGv dst, TCGv src, int index)
4544 {
4545 TCGv addr;
4546 TCGv_i64 t0, t1;
4547
4548 addr = tcg_temp_new();
4549
4550 t0 = tcg_temp_new_i64();
4551 t1 = tcg_temp_new_i64();
4552
4553 tcg_gen_andi_i32(addr, src, ~15);
4554 tcg_gen_qemu_ld64(t0, addr, index);
4555 tcg_gen_addi_i32(addr, addr, 8);
4556 tcg_gen_qemu_ld64(t1, addr, index);
4557
4558 tcg_gen_andi_i32(addr, dst, ~15);
4559 tcg_gen_qemu_st64(t0, addr, index);
4560 tcg_gen_addi_i32(addr, addr, 8);
4561 tcg_gen_qemu_st64(t1, addr, index);
4562
4563 tcg_temp_free_i64(t0);
4564 tcg_temp_free_i64(t1);
4565 tcg_temp_free(addr);
4566 }
4567
4568 DISAS_INSN(move16_reg)
4569 {
4570 int index = IS_USER(s);
4571 TCGv tmp;
4572 uint16_t ext;
4573
4574 ext = read_im16(env, s);
4575 if ((ext & (1 << 15)) == 0) {
4576 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4577 }
4578
4579 m68k_copy_line(AREG(ext, 12), AREG(insn, 0), index);
4580
4581 /* Ax can be Ay, so save Ay before incrementing Ax */
4582 tmp = tcg_temp_new();
4583 tcg_gen_mov_i32(tmp, AREG(ext, 12));
4584 tcg_gen_addi_i32(AREG(insn, 0), AREG(insn, 0), 16);
4585 tcg_gen_addi_i32(AREG(ext, 12), tmp, 16);
4586 tcg_temp_free(tmp);
4587 }
4588
4589 DISAS_INSN(move16_mem)
4590 {
4591 int index = IS_USER(s);
4592 TCGv reg, addr;
4593
4594 reg = AREG(insn, 0);
4595 addr = tcg_const_i32(read_im32(env, s));
4596
4597 if ((insn >> 3) & 1) {
4598 /* MOVE16 (xxx).L, (Ay) */
4599 m68k_copy_line(reg, addr, index);
4600 } else {
4601 /* MOVE16 (Ay), (xxx).L */
4602 m68k_copy_line(addr, reg, index);
4603 }
4604
4605 tcg_temp_free(addr);
4606
4607 if (((insn >> 3) & 2) == 0) {
4608 /* (Ay)+ */
4609 tcg_gen_addi_i32(reg, reg, 16);
4610 }
4611 }
4612
4613 DISAS_INSN(strldsr)
4614 {
4615 uint16_t ext;
4616 uint32_t addr;
4617
4618 addr = s->pc - 2;
4619 ext = read_im16(env, s);
4620 if (ext != 0x46FC) {
4621 gen_exception(s, addr, EXCP_ILLEGAL);
4622 return;
4623 }
4624 ext = read_im16(env, s);
4625 if (IS_USER(s) || (ext & SR_S) == 0) {
4626 gen_exception(s, addr, EXCP_PRIVILEGE);
4627 return;
4628 }
4629 gen_push(s, gen_get_sr(s));
4630 gen_set_sr_im(s, ext, 0);
4631 }
4632
4633 DISAS_INSN(move_from_sr)
4634 {
4635 TCGv sr;
4636
4637 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
4638 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4639 return;
4640 }
4641 sr = gen_get_sr(s);
4642 DEST_EA(env, insn, OS_WORD, sr, NULL);
4643 }
4644
4645 #if defined(CONFIG_SOFTMMU)
4646 DISAS_INSN(moves)
4647 {
4648 int opsize;
4649 uint16_t ext;
4650 TCGv reg;
4651 TCGv addr;
4652 int extend;
4653
4654 if (IS_USER(s)) {
4655 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4656 return;
4657 }
4658
4659 ext = read_im16(env, s);
4660
4661 opsize = insn_opsize(insn);
4662
4663 if (ext & 0x8000) {
4664 /* address register */
4665 reg = AREG(ext, 12);
4666 extend = 1;
4667 } else {
4668 /* data register */
4669 reg = DREG(ext, 12);
4670 extend = 0;
4671 }
4672
4673 addr = gen_lea(env, s, insn, opsize);
4674 if (IS_NULL_QREG(addr)) {
4675 gen_addr_fault(s);
4676 return;
4677 }
4678
4679 if (ext & 0x0800) {
4680 /* from reg to ea */
4681 gen_store(s, opsize, addr, reg, DFC_INDEX(s));
4682 } else {
4683 /* from ea to reg */
4684 TCGv tmp = gen_load(s, opsize, addr, 0, SFC_INDEX(s));
4685 if (extend) {
4686 gen_ext(reg, tmp, opsize, 1);
4687 } else {
4688 gen_partset_reg(opsize, reg, tmp);
4689 }
4690 tcg_temp_free(tmp);
4691 }
4692 switch (extract32(insn, 3, 3)) {
4693 case 3: /* Indirect postincrement. */
4694 tcg_gen_addi_i32(AREG(insn, 0), addr,
4695 REG(insn, 0) == 7 && opsize == OS_BYTE
4696 ? 2
4697 : opsize_bytes(opsize));
4698 break;
4699 case 4: /* Indirect predecrememnt. */
4700 tcg_gen_mov_i32(AREG(insn, 0), addr);
4701 break;
4702 }
4703 }
4704
4705 DISAS_INSN(move_to_sr)
4706 {
4707 if (IS_USER(s)) {
4708 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4709 return;
4710 }
4711 gen_move_to_sr(env, s, insn, false);
4712 gen_exit_tb(s);
4713 }
4714
4715 DISAS_INSN(move_from_usp)
4716 {
4717 if (IS_USER(s)) {
4718 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4719 return;
4720 }
4721 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4722 offsetof(CPUM68KState, sp[M68K_USP]));
4723 }
4724
4725 DISAS_INSN(move_to_usp)
4726 {
4727 if (IS_USER(s)) {
4728 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4729 return;
4730 }
4731 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4732 offsetof(CPUM68KState, sp[M68K_USP]));
4733 }
4734
4735 DISAS_INSN(halt)
4736 {
4737 if (IS_USER(s)) {
4738 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4739 return;
4740 }
4741
4742 gen_exception(s, s->pc, EXCP_HALT_INSN);
4743 }
4744
4745 DISAS_INSN(stop)
4746 {
4747 uint16_t ext;
4748
4749 if (IS_USER(s)) {
4750 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4751 return;
4752 }
4753
4754 ext = read_im16(env, s);
4755
4756 gen_set_sr_im(s, ext, 0);
4757 tcg_gen_movi_i32(cpu_halted, 1);
4758 gen_exception(s, s->pc, EXCP_HLT);
4759 }
4760
4761 DISAS_INSN(rte)
4762 {
4763 if (IS_USER(s)) {
4764 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4765 return;
4766 }
4767 gen_exception(s, s->base.pc_next, EXCP_RTE);
4768 }
4769
4770 DISAS_INSN(cf_movec)
4771 {
4772 uint16_t ext;
4773 TCGv reg;
4774
4775 if (IS_USER(s)) {
4776 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4777 return;
4778 }
4779
4780 ext = read_im16(env, s);
4781
4782 if (ext & 0x8000) {
4783 reg = AREG(ext, 12);
4784 } else {
4785 reg = DREG(ext, 12);
4786 }
4787 gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4788 gen_exit_tb(s);
4789 }
4790
4791 DISAS_INSN(m68k_movec)
4792 {
4793 uint16_t ext;
4794 TCGv reg;
4795
4796 if (IS_USER(s)) {
4797 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4798 return;
4799 }
4800
4801 ext = read_im16(env, s);
4802
4803 if (ext & 0x8000) {
4804 reg = AREG(ext, 12);
4805 } else {
4806 reg = DREG(ext, 12);
4807 }
4808 if (insn & 1) {
4809 gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4810 } else {
4811 gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
4812 }
4813 gen_exit_tb(s);
4814 }
4815
4816 DISAS_INSN(intouch)
4817 {
4818 if (IS_USER(s)) {
4819 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4820 return;
4821 }
4822 /* ICache fetch. Implement as no-op. */
4823 }
4824
4825 DISAS_INSN(cpushl)
4826 {
4827 if (IS_USER(s)) {
4828 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4829 return;
4830 }
4831 /* Cache push/invalidate. Implement as no-op. */
4832 }
4833
4834 DISAS_INSN(cpush)
4835 {
4836 if (IS_USER(s)) {
4837 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4838 return;
4839 }
4840 /* Cache push/invalidate. Implement as no-op. */
4841 }
4842
4843 DISAS_INSN(cinv)
4844 {
4845 if (IS_USER(s)) {
4846 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4847 return;
4848 }
4849 /* Invalidate cache line. Implement as no-op. */
4850 }
4851
4852 #if defined(CONFIG_SOFTMMU)
4853 DISAS_INSN(pflush)
4854 {
4855 TCGv opmode;
4856
4857 if (IS_USER(s)) {
4858 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4859 return;
4860 }
4861
4862 opmode = tcg_const_i32((insn >> 3) & 3);
4863 gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
4864 tcg_temp_free(opmode);
4865 }
4866
4867 DISAS_INSN(ptest)
4868 {
4869 TCGv is_read;
4870
4871 if (IS_USER(s)) {
4872 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4873 return;
4874 }
4875 is_read = tcg_const_i32((insn >> 5) & 1);
4876 gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
4877 tcg_temp_free(is_read);
4878 }
4879 #endif
4880
4881 DISAS_INSN(wddata)
4882 {
4883 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4884 }
4885
4886 DISAS_INSN(wdebug)
4887 {
4888 if (IS_USER(s)) {
4889 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4890 return;
4891 }
4892 /* TODO: Implement wdebug. */
4893 cpu_abort(env_cpu(env), "WDEBUG not implemented");
4894 }
4895 #endif
4896
4897 DISAS_INSN(trap)
4898 {
4899 gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf));
4900 }
4901
4902 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4903 {
4904 switch (reg) {
4905 case M68K_FPIAR:
4906 tcg_gen_movi_i32(res, 0);
4907 break;
4908 case M68K_FPSR:
4909 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4910 break;
4911 case M68K_FPCR:
4912 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4913 break;
4914 }
4915 }
4916
4917 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4918 {
4919 switch (reg) {
4920 case M68K_FPIAR:
4921 break;
4922 case M68K_FPSR:
4923 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4924 break;
4925 case M68K_FPCR:
4926 gen_helper_set_fpcr(cpu_env, val);
4927 break;
4928 }
4929 }
4930
4931 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4932 {
4933 int index = IS_USER(s);
4934 TCGv tmp;
4935
4936 tmp = tcg_temp_new();
4937 gen_load_fcr(s, tmp, reg);
4938 tcg_gen_qemu_st32(tmp, addr, index);
4939 tcg_temp_free(tmp);
4940 }
4941
4942 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4943 {
4944 int index = IS_USER(s);
4945 TCGv tmp;
4946
4947 tmp = tcg_temp_new();
4948 tcg_gen_qemu_ld32u(tmp, addr, index);
4949 gen_store_fcr(s, tmp, reg);
4950 tcg_temp_free(tmp);
4951 }
4952
4953
4954 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4955 uint32_t insn, uint32_t ext)
4956 {
4957 int mask = (ext >> 10) & 7;
4958 int is_write = (ext >> 13) & 1;
4959 int mode = extract32(insn, 3, 3);
4960 int i;
4961 TCGv addr, tmp;
4962
4963 switch (mode) {
4964 case 0: /* Dn */
4965 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4966 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4967 return;
4968 }
4969 if (is_write) {
4970 gen_load_fcr(s, DREG(insn, 0), mask);
4971 } else {
4972 gen_store_fcr(s, DREG(insn, 0), mask);
4973 }
4974 return;
4975 case 1: /* An, only with FPIAR */
4976 if (mask != M68K_FPIAR) {
4977 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4978 return;
4979 }
4980 if (is_write) {
4981 gen_load_fcr(s, AREG(insn, 0), mask);
4982 } else {
4983 gen_store_fcr(s, AREG(insn, 0), mask);
4984 }
4985 return;
4986 case 7: /* Immediate */
4987 if (REG(insn, 0) == 4) {
4988 if (is_write ||
4989 (mask != M68K_FPIAR && mask != M68K_FPSR &&
4990 mask != M68K_FPCR)) {
4991 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4992 return;
4993 }
4994 tmp = tcg_const_i32(read_im32(env, s));
4995 gen_store_fcr(s, tmp, mask);
4996 tcg_temp_free(tmp);
4997 return;
4998 }
4999 break;
5000 default:
5001 break;
5002 }
5003
5004 tmp = gen_lea(env, s, insn, OS_LONG);
5005 if (IS_NULL_QREG(tmp)) {
5006 gen_addr_fault(s);
5007 return;
5008 }
5009
5010 addr = tcg_temp_new();
5011 tcg_gen_mov_i32(addr, tmp);
5012
5013 /*
5014 * mask:
5015 *
5016 * 0b100 Floating-Point Control Register
5017 * 0b010 Floating-Point Status Register
5018 * 0b001 Floating-Point Instruction Address Register
5019 *
5020 */
5021
5022 if (is_write && mode == 4) {
5023 for (i = 2; i >= 0; i--, mask >>= 1) {
5024 if (mask & 1) {
5025 gen_qemu_store_fcr(s, addr, 1 << i);
5026 if (mask != 1) {
5027 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
5028 }
5029 }
5030 }
5031 tcg_gen_mov_i32(AREG(insn, 0), addr);
5032 } else {
5033 for (i = 0; i < 3; i++, mask >>= 1) {
5034 if (mask & 1) {
5035 if (is_write) {
5036 gen_qemu_store_fcr(s, addr, 1 << i);
5037 } else {
5038 gen_qemu_load_fcr(s, addr, 1 << i);
5039 }
5040 if (mask != 1 || mode == 3) {
5041 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
5042 }
5043 }
5044 }
5045 if (mode == 3) {
5046 tcg_gen_mov_i32(AREG(insn, 0), addr);
5047 }
5048 }
5049 tcg_temp_free_i32(addr);
5050 }
5051
5052 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
5053 uint32_t insn, uint32_t ext)
5054 {
5055 int opsize;
5056 TCGv addr, tmp;
5057 int mode = (ext >> 11) & 0x3;
5058 int is_load = ((ext & 0x2000) == 0);
5059
5060 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
5061 opsize = OS_EXTENDED;
5062 } else {
5063 opsize = OS_DOUBLE; /* FIXME */
5064 }
5065
5066 addr = gen_lea(env, s, insn, opsize);
5067 if (IS_NULL_QREG(addr)) {
5068 gen_addr_fault(s);
5069 return;
5070 }
5071
5072 tmp = tcg_temp_new();
5073 if (mode & 0x1) {
5074 /* Dynamic register list */
5075 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
5076 } else {
5077 /* Static register list */
5078 tcg_gen_movi_i32(tmp, ext & 0xff);
5079 }
5080
5081 if (!is_load && (mode & 2) == 0) {
5082 /*
5083 * predecrement addressing mode
5084 * only available to store register to memory
5085 */
5086 if (opsize == OS_EXTENDED) {
5087 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
5088 } else {
5089 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
5090 }
5091 } else {
5092 /* postincrement addressing mode */
5093 if (opsize == OS_EXTENDED) {
5094 if (is_load) {
5095 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
5096 } else {
5097 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
5098 }
5099 } else {
5100 if (is_load) {
5101 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
5102 } else {
5103 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
5104 }
5105 }
5106 }
5107 if ((insn & 070) == 030 || (insn & 070) == 040) {
5108 tcg_gen_mov_i32(AREG(insn, 0), tmp);
5109 }
5110 tcg_temp_free(tmp);
5111 }
5112
5113 /*
5114 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5115 * immediately before the next FP instruction is executed.
5116 */
5117 DISAS_INSN(fpu)
5118 {
5119 uint16_t ext;
5120 int opmode;
5121 int opsize;
5122 TCGv_ptr cpu_src, cpu_dest;
5123
5124 ext = read_im16(env, s);
5125 opmode = ext & 0x7f;
5126 switch ((ext >> 13) & 7) {
5127 case 0:
5128 break;
5129 case 1:
5130 goto undef;
5131 case 2:
5132 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
5133 /* fmovecr */
5134 TCGv rom_offset = tcg_const_i32(opmode);
5135 cpu_dest = gen_fp_ptr(REG(ext, 7));
5136 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
5137 tcg_temp_free_ptr(cpu_dest);
5138 tcg_temp_free(rom_offset);
5139 return;
5140 }
5141 break;
5142 case 3: /* fmove out */
5143 cpu_src = gen_fp_ptr(REG(ext, 7));
5144 opsize = ext_opsize(ext, 10);
5145 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5146 EA_STORE, IS_USER(s)) == -1) {
5147 gen_addr_fault(s);
5148 }
5149 gen_helper_ftst(cpu_env, cpu_src);
5150 tcg_temp_free_ptr(cpu_src);
5151 return;
5152 case 4: /* fmove to control register. */
5153 case 5: /* fmove from control register. */
5154 gen_op_fmove_fcr(env, s, insn, ext);
5155 return;
5156 case 6: /* fmovem */
5157 case 7:
5158 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
5159 goto undef;
5160 }
5161 gen_op_fmovem(env, s, insn, ext);
5162 return;
5163 }
5164 if (ext & (1 << 14)) {
5165 /* Source effective address. */
5166 opsize = ext_opsize(ext, 10);
5167 cpu_src = gen_fp_result_ptr();
5168 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5169 EA_LOADS, IS_USER(s)) == -1) {
5170 gen_addr_fault(s);
5171 return;
5172 }
5173 } else {
5174 /* Source register. */
5175 opsize = OS_EXTENDED;
5176 cpu_src = gen_fp_ptr(REG(ext, 10));
5177 }
5178 cpu_dest = gen_fp_ptr(REG(ext, 7));
5179 switch (opmode) {
5180 case 0: /* fmove */
5181 gen_fp_move(cpu_dest, cpu_src);
5182 break;
5183 case 0x40: /* fsmove */
5184 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
5185 break;
5186 case 0x44: /* fdmove */
5187 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
5188 break;
5189 case 1: /* fint */
5190 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
5191 break;
5192 case 2: /* fsinh */
5193 gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
5194 break;
5195 case 3: /* fintrz */
5196 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
5197 break;
5198 case 4: /* fsqrt */
5199 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
5200 break;
5201 case 0x41: /* fssqrt */
5202 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
5203 break;
5204 case 0x45: /* fdsqrt */
5205 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
5206 break;
5207 case 0x06: /* flognp1 */
5208 gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
5209 break;
5210 case 0x08: /* fetoxm1 */
5211 gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src);
5212 break;
5213 case 0x09: /* ftanh */
5214 gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
5215 break;
5216 case 0x0a: /* fatan */
5217 gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
5218 break;
5219 case 0x0c: /* fasin */
5220 gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
5221 break;
5222 case 0x0d: /* fatanh */
5223 gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
5224 break;
5225 case 0x0e: /* fsin */
5226 gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
5227 break;
5228 case 0x0f: /* ftan */
5229 gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
5230 break;
5231 case 0x10: /* fetox */
5232 gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
5233 break;
5234 case 0x11: /* ftwotox */
5235 gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
5236 break;
5237 case 0x12: /* ftentox */
5238 gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
5239 break;
5240 case 0x14: /* flogn */
5241 gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
5242 break;
5243 case 0x15: /* flog10 */
5244 gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
5245 break;
5246 case 0x16: /* flog2 */
5247 gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
5248 break;
5249 case 0x18: /* fabs */
5250 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
5251 break;
5252 case 0x58: /* fsabs */
5253 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
5254 break;
5255 case 0x5c: /* fdabs */
5256 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
5257 break;
5258 case 0x19: /* fcosh */
5259 gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
5260 break;
5261 case 0x1a: /* fneg */
5262 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
5263 break;
5264 case 0x5a: /* fsneg */
5265 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
5266 break;
5267 case 0x5e: /* fdneg */
5268 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
5269 break;
5270 case 0x1c: /* facos */
5271 gen_helper_facos(cpu_env, cpu_dest, cpu_src);
5272 break;
5273 case 0x1d: /* fcos */
5274 gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
5275 break;
5276 case 0x1e: /* fgetexp */
5277 gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
5278 break;
5279 case 0x1f: /* fgetman */
5280 gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
5281 break;
5282 case 0x20: /* fdiv */
5283 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5284 break;
5285 case 0x60: /* fsdiv */
5286 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5287 break;
5288 case 0x64: /* fddiv */
5289 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5290 break;
5291 case 0x21: /* fmod */
5292 gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
5293 break;
5294 case 0x22: /* fadd */
5295 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5296 break;
5297 case 0x62: /* fsadd */
5298 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5299 break;
5300 case 0x66: /* fdadd */
5301 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5302 break;
5303 case 0x23: /* fmul */
5304 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5305 break;
5306 case 0x63: /* fsmul */
5307 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5308 break;
5309 case 0x67: /* fdmul */
5310 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5311 break;
5312 case 0x24: /* fsgldiv */
5313 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5314 break;
5315 case 0x25: /* frem */
5316 gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
5317 break;
5318 case 0x26: /* fscale */
5319 gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
5320 break;
5321 case 0x27: /* fsglmul */
5322 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5323 break;
5324 case 0x28: /* fsub */
5325 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5326 break;
5327 case 0x68: /* fssub */
5328 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5329 break;
5330 case 0x6c: /* fdsub */
5331 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5332 break;
5333 case 0x30: case 0x31: case 0x32:
5334 case 0x33: case 0x34: case 0x35:
5335 case 0x36: case 0x37: {
5336 TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
5337 gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
5338 tcg_temp_free_ptr(cpu_dest2);
5339 }
5340 break;
5341 case 0x38: /* fcmp */
5342 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
5343 return;
5344 case 0x3a: /* ftst */
5345 gen_helper_ftst(cpu_env, cpu_src);
5346 return;
5347 default:
5348 goto undef;
5349 }
5350 tcg_temp_free_ptr(cpu_src);
5351 gen_helper_ftst(cpu_env, cpu_dest);
5352 tcg_temp_free_ptr(cpu_dest);
5353 return;
5354 undef:
5355 /* FIXME: Is this right for offset addressing modes? */
5356 s->pc -= 2;
5357 disas_undef_fpu(env, s, insn);
5358 }
5359
5360 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
5361 {
5362 TCGv fpsr;
5363
5364 c->g1 = 1;
5365 c->v2 = tcg_const_i32(0);
5366 c->g2 = 0;
5367 /* TODO: Raise BSUN exception. */
5368 fpsr = tcg_temp_new();
5369 gen_load_fcr(s, fpsr, M68K_FPSR);
5370 switch (cond) {
5371 case 0: /* False */
5372 case 16: /* Signaling False */
5373 c->v1 = c->v2;
5374 c->tcond = TCG_COND_NEVER;
5375 break;
5376 case 1: /* EQual Z */
5377 case 17: /* Signaling EQual Z */
5378 c->v1 = tcg_temp_new();
5379 c->g1 = 0;
5380 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5381 c->tcond = TCG_COND_NE;
5382 break;
5383 case 2: /* Ordered Greater Than !(A || Z || N) */
5384 case 18: /* Greater Than !(A || Z || N) */
5385 c->v1 = tcg_temp_new();
5386 c->g1 = 0;
5387 tcg_gen_andi_i32(c->v1, fpsr,
5388 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5389 c->tcond = TCG_COND_EQ;
5390 break;
5391 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5392 case 19: /* Greater than or Equal Z || !(A || N) */
5393 c->v1 = tcg_temp_new();
5394 c->g1 = 0;
5395 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5396 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5397 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
5398 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5399 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5400 c->tcond = TCG_COND_NE;
5401 break;
5402 case 4: /* Ordered Less Than !(!N || A || Z); */
5403 case 20: /* Less Than !(!N || A || Z); */
5404 c->v1 = tcg_temp_new();
5405 c->g1 = 0;
5406 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
5407 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
5408 c->tcond = TCG_COND_EQ;
5409 break;
5410 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5411 case 21: /* Less than or Equal Z || (N && !A) */
5412 c->v1 = tcg_temp_new();
5413 c->g1 = 0;
5414 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5415 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5416 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5417 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
5418 c->tcond = TCG_COND_NE;
5419 break;
5420 case 6: /* Ordered Greater or Less than !(A || Z) */
5421 case 22: /* Greater or Less than !(A || Z) */
5422 c->v1 = tcg_temp_new();
5423 c->g1 = 0;
5424 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5425 c->tcond = TCG_COND_EQ;
5426 break;
5427 case 7: /* Ordered !A */
5428 case 23: /* Greater, Less or Equal !A */
5429 c->v1 = tcg_temp_new();
5430 c->g1 = 0;
5431 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5432 c->tcond = TCG_COND_EQ;
5433 break;
5434 case 8: /* Unordered A */
5435 case 24: /* Not Greater, Less or Equal A */
5436 c->v1 = tcg_temp_new();
5437 c->g1 = 0;
5438 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5439 c->tcond = TCG_COND_NE;
5440 break;
5441 case 9: /* Unordered or Equal A || Z */
5442 case 25: /* Not Greater or Less then A || Z */
5443 c->v1 = tcg_temp_new();
5444 c->g1 = 0;
5445 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5446 c->tcond = TCG_COND_NE;
5447 break;
5448 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5449 case 26: /* Not Less or Equal A || !(N || Z)) */
5450 c->v1 = tcg_temp_new();
5451 c->g1 = 0;
5452 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5453 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5454 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
5455 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5456 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5457 c->tcond = TCG_COND_NE;
5458 break;
5459 case 11: /* Unordered or Greater or Equal A || Z || !N */
5460 case 27: /* Not Less Than A || Z || !N */
5461 c->v1 = tcg_temp_new();
5462 c->g1 = 0;
5463 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5464 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5465 c->tcond = TCG_COND_NE;
5466 break;
5467 case 12: /* Unordered or Less Than A || (N && !Z) */
5468 case 28: /* Not Greater than or Equal A || (N && !Z) */
5469 c->v1 = tcg_temp_new();
5470 c->g1 = 0;
5471 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5472 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5473 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5474 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
5475 c->tcond = TCG_COND_NE;
5476 break;
5477 case 13: /* Unordered or Less or Equal A || Z || N */
5478 case 29: /* Not Greater Than A || Z || N */
5479 c->v1 = tcg_temp_new();
5480 c->g1 = 0;
5481 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5482 c->tcond = TCG_COND_NE;
5483 break;
5484 case 14: /* Not Equal !Z */
5485 case 30: /* Signaling Not Equal !Z */
5486 c->v1 = tcg_temp_new();
5487 c->g1 = 0;
5488 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5489 c->tcond = TCG_COND_EQ;
5490 break;
5491 case 15: /* True */
5492 case 31: /* Signaling True */
5493 c->v1 = c->v2;
5494 c->tcond = TCG_COND_ALWAYS;
5495 break;
5496 }
5497 tcg_temp_free(fpsr);
5498 }
5499
5500 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
5501 {
5502 DisasCompare c;
5503
5504 gen_fcc_cond(&c, s, cond);
5505 update_cc_op(s);
5506 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
5507 free_cond(&c);
5508 }
5509
5510 DISAS_INSN(fbcc)
5511 {
5512 uint32_t offset;
5513 uint32_t base;
5514 TCGLabel *l1;
5515
5516 base = s->pc;
5517 offset = (int16_t)read_im16(env, s);
5518 if (insn & (1 << 6)) {
5519 offset = (offset << 16) | read_im16(env, s);
5520 }
5521
5522 l1 = gen_new_label();
5523 update_cc_op(s);
5524 gen_fjmpcc(s, insn & 0x3f, l1);
5525 gen_jmp_tb(s, 0, s->pc);
5526 gen_set_label(l1);
5527 gen_jmp_tb(s, 1, base + offset);
5528 }
5529
5530 DISAS_INSN(fscc)
5531 {
5532 DisasCompare c;
5533 int cond;
5534 TCGv tmp;
5535 uint16_t ext;
5536
5537 ext = read_im16(env, s);
5538 cond = ext & 0x3f;
5539 gen_fcc_cond(&c, s, cond);
5540
5541 tmp = tcg_temp_new();
5542 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
5543 free_cond(&c);
5544
5545 tcg_gen_neg_i32(tmp, tmp);
5546 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
5547 tcg_temp_free(tmp);
5548 }
5549
5550 #if defined(CONFIG_SOFTMMU)
5551 DISAS_INSN(frestore)
5552 {
5553 TCGv addr;
5554
5555 if (IS_USER(s)) {
5556 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5557 return;
5558 }
5559 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5560 SRC_EA(env, addr, OS_LONG, 0, NULL);
5561 /* FIXME: check the state frame */
5562 } else {
5563 disas_undef(env, s, insn);
5564 }
5565 }
5566
5567 DISAS_INSN(fsave)
5568 {
5569 if (IS_USER(s)) {
5570 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5571 return;
5572 }
5573
5574 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5575 /* always write IDLE */
5576 TCGv idle = tcg_const_i32(0x41000000);
5577 DEST_EA(env, insn, OS_LONG, idle, NULL);
5578 tcg_temp_free(idle);
5579 } else {
5580 disas_undef(env, s, insn);
5581 }
5582 }
5583 #endif
5584
5585 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
5586 {
5587 TCGv tmp = tcg_temp_new();
5588 if (s->env->macsr & MACSR_FI) {
5589 if (upper)
5590 tcg_gen_andi_i32(tmp, val, 0xffff0000);
5591 else
5592 tcg_gen_shli_i32(tmp, val, 16);
5593 } else if (s->env->macsr & MACSR_SU) {
5594 if (upper)
5595 tcg_gen_sari_i32(tmp, val, 16);
5596 else
5597 tcg_gen_ext16s_i32(tmp, val);
5598 } else {
5599 if (upper)
5600 tcg_gen_shri_i32(tmp, val, 16);
5601 else
5602 tcg_gen_ext16u_i32(tmp, val);
5603 }
5604 return tmp;
5605 }
5606
5607 static void gen_mac_clear_flags(void)
5608 {
5609 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
5610 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
5611 }
5612
5613 DISAS_INSN(mac)
5614 {
5615 TCGv rx;
5616 TCGv ry;
5617 uint16_t ext;
5618 int acc;
5619 TCGv tmp;
5620 TCGv addr;
5621 TCGv loadval;
5622 int dual;
5623 TCGv saved_flags;
5624
5625 if (!s->done_mac) {
5626 s->mactmp = tcg_temp_new_i64();
5627 s->done_mac = 1;
5628 }
5629
5630 ext = read_im16(env, s);
5631
5632 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
5633 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
5634 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
5635 disas_undef(env, s, insn);
5636 return;
5637 }
5638 if (insn & 0x30) {
5639 /* MAC with load. */
5640 tmp = gen_lea(env, s, insn, OS_LONG);
5641 addr = tcg_temp_new();
5642 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5643 /*
5644 * Load the value now to ensure correct exception behavior.
5645 * Perform writeback after reading the MAC inputs.
5646 */
5647 loadval = gen_load(s, OS_LONG, addr, 0, IS_USER(s));
5648
5649 acc ^= 1;
5650 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5651 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5652 } else {
5653 loadval = addr = NULL_QREG;
5654 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5655 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5656 }
5657
5658 gen_mac_clear_flags();
5659 #if 0
5660 l1 = -1;
5661 /* Disabled because conditional branches clobber temporary vars. */
5662 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5663 /* Skip the multiply if we know we will ignore it. */
5664 l1 = gen_new_label();
5665 tmp = tcg_temp_new();
5666 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5667 gen_op_jmp_nz32(tmp, l1);
5668 }
5669 #endif
5670
5671 if ((ext & 0x0800) == 0) {
5672 /* Word. */
5673 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5674 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5675 }
5676 if (s->env->macsr & MACSR_FI) {
5677 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5678 } else {
5679 if (s->env->macsr & MACSR_SU)
5680 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5681 else
5682 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5683 switch ((ext >> 9) & 3) {
5684 case 1:
5685 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5686 break;
5687 case 3:
5688 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5689 break;
5690 }
5691 }
5692
5693 if (dual) {
5694 /* Save the overflow flag from the multiply. */
5695 saved_flags = tcg_temp_new();
5696 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5697 } else {
5698 saved_flags = NULL_QREG;
5699 }
5700
5701 #if 0
5702 /* Disabled because conditional branches clobber temporary vars. */
5703 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5704 /* Skip the accumulate if the value is already saturated. */
5705 l1 = gen_new_label();
5706 tmp = tcg_temp_new();
5707 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5708 gen_op_jmp_nz32(tmp, l1);
5709 }
5710 #endif
5711
5712 if (insn & 0x100)
5713 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5714 else
5715 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5716
5717 if (s->env->macsr & MACSR_FI)
5718 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5719 else if (s->env->macsr & MACSR_SU)
5720 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5721 else
5722 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5723
5724 #if 0
5725 /* Disabled because conditional branches clobber temporary vars. */
5726 if (l1 != -1)
5727 gen_set_label(l1);
5728 #endif
5729
5730 if (dual) {
5731 /* Dual accumulate variant. */
5732 acc = (ext >> 2) & 3;
5733 /* Restore the overflow flag from the multiplier. */
5734 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5735 #if 0
5736 /* Disabled because conditional branches clobber temporary vars. */
5737 if ((s->env->macsr & MACSR_OMC) != 0) {
5738 /* Skip the accumulate if the value is already saturated. */
5739 l1 = gen_new_label();
5740 tmp = tcg_temp_new();
5741 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5742 gen_op_jmp_nz32(tmp, l1);
5743 }
5744 #endif
5745 if (ext & 2)
5746 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5747 else
5748 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5749 if (s->env->macsr & MACSR_FI)
5750 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5751 else if (s->env->macsr & MACSR_SU)
5752 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5753 else
5754 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5755 #if 0
5756 /* Disabled because conditional branches clobber temporary vars. */
5757 if (l1 != -1)
5758 gen_set_label(l1);
5759 #endif
5760 }
5761 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5762
5763 if (insn & 0x30) {
5764 TCGv rw;
5765 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5766 tcg_gen_mov_i32(rw, loadval);
5767 /*
5768 * FIXME: Should address writeback happen with the masked or
5769 * unmasked value?
5770 */
5771 switch ((insn >> 3) & 7) {
5772 case 3: /* Post-increment. */
5773 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5774 break;
5775 case 4: /* Pre-decrement. */
5776 tcg_gen_mov_i32(AREG(insn, 0), addr);
5777 }
5778 tcg_temp_free(loadval);
5779 }
5780 }
5781
5782 DISAS_INSN(from_mac)
5783 {
5784 TCGv rx;
5785 TCGv_i64 acc;
5786 int accnum;
5787
5788 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5789 accnum = (insn >> 9) & 3;
5790 acc = MACREG(accnum);
5791 if (s->env->macsr & MACSR_FI) {
5792 gen_helper_get_macf(rx, cpu_env, acc);
5793 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5794 tcg_gen_extrl_i64_i32(rx, acc);
5795 } else if (s->env->macsr & MACSR_SU) {
5796 gen_helper_get_macs(rx, acc);
5797 } else {
5798 gen_helper_get_macu(rx, acc);
5799 }
5800 if (insn & 0x40) {
5801 tcg_gen_movi_i64(acc, 0);
5802 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5803 }
5804 }
5805
5806 DISAS_INSN(move_mac)
5807 {
5808 /* FIXME: This can be done without a helper. */
5809 int src;
5810 TCGv dest;
5811 src = insn & 3;
5812 dest = tcg_const_i32((insn >> 9) & 3);
5813 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5814 gen_mac_clear_flags();
5815 gen_helper_mac_set_flags(cpu_env, dest);
5816 }
5817
5818 DISAS_INSN(from_macsr)
5819 {
5820 TCGv reg;
5821
5822 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5823 tcg_gen_mov_i32(reg, QREG_MACSR);
5824 }
5825
5826 DISAS_INSN(from_mask)
5827 {
5828 TCGv reg;
5829 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5830 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5831 }
5832
5833 DISAS_INSN(from_mext)
5834 {
5835 TCGv reg;
5836 TCGv acc;
5837 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5838 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5839 if (s->env->macsr & MACSR_FI)
5840 gen_helper_get_mac_extf(reg, cpu_env, acc);
5841 else
5842 gen_helper_get_mac_exti(reg, cpu_env, acc);
5843 }
5844
5845 DISAS_INSN(macsr_to_ccr)
5846 {
5847 TCGv tmp = tcg_temp_new();
5848 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5849 gen_helper_set_sr(cpu_env, tmp);
5850 tcg_temp_free(tmp);
5851 set_cc_op(s, CC_OP_FLAGS);
5852 }
5853
5854 DISAS_INSN(to_mac)
5855 {
5856 TCGv_i64 acc;
5857 TCGv val;
5858 int accnum;
5859 accnum = (insn >> 9) & 3;
5860 acc = MACREG(accnum);
5861 SRC_EA(env, val, OS_LONG, 0, NULL);
5862 if (s->env->macsr & MACSR_FI) {
5863 tcg_gen_ext_i32_i64(acc, val);
5864 tcg_gen_shli_i64(acc, acc, 8);
5865 } else if (s->env->macsr & MACSR_SU) {
5866 tcg_gen_ext_i32_i64(acc, val);
5867 } else {
5868 tcg_gen_extu_i32_i64(acc, val);
5869 }
5870 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5871 gen_mac_clear_flags();
5872 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5873 }
5874
5875 DISAS_INSN(to_macsr)
5876 {
5877 TCGv val;
5878 SRC_EA(env, val, OS_LONG, 0, NULL);
5879 gen_helper_set_macsr(cpu_env, val);
5880 gen_exit_tb(s);
5881 }
5882
5883 DISAS_INSN(to_mask)
5884 {
5885 TCGv val;
5886 SRC_EA(env, val, OS_LONG, 0, NULL);
5887 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5888 }
5889
5890 DISAS_INSN(to_mext)
5891 {
5892 TCGv val;
5893 TCGv acc;
5894 SRC_EA(env, val, OS_LONG, 0, NULL);
5895 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5896 if (s->env->macsr & MACSR_FI)
5897 gen_helper_set_mac_extf(cpu_env, val, acc);
5898 else if (s->env->macsr & MACSR_SU)
5899 gen_helper_set_mac_exts(cpu_env, val, acc);
5900 else
5901 gen_helper_set_mac_extu(cpu_env, val, acc);
5902 }
5903
5904 static disas_proc opcode_table[65536];
5905
5906 static void
5907 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5908 {
5909 int i;
5910 int from;
5911 int to;
5912
5913 /* Sanity check. All set bits must be included in the mask. */
5914 if (opcode & ~mask) {
5915 fprintf(stderr,
5916 "qemu internal error: bogus opcode definition %04x/%04x\n",
5917 opcode, mask);
5918 abort();
5919 }
5920 /*
5921 * This could probably be cleverer. For now just optimize the case where
5922 * the top bits are known.
5923 */
5924 /* Find the first zero bit in the mask. */
5925 i = 0x8000;
5926 while ((i & mask) != 0)
5927 i >>= 1;
5928 /* Iterate over all combinations of this and lower bits. */
5929 if (i == 0)
5930 i = 1;
5931 else
5932 i <<= 1;
5933 from = opcode & ~(i - 1);
5934 to = from + i;
5935 for (i = from; i < to; i++) {
5936 if ((i & mask) == opcode)
5937 opcode_table[i] = proc;
5938 }
5939 }
5940
5941 /*
5942 * Register m68k opcode handlers. Order is important.
5943 * Later insn override earlier ones.
5944 */
5945 void register_m68k_insns (CPUM68KState *env)
5946 {
5947 /*
5948 * Build the opcode table only once to avoid
5949 * multithreading issues.
5950 */
5951 if (opcode_table[0] != NULL) {
5952 return;
5953 }
5954
5955 /*
5956 * use BASE() for instruction available
5957 * for CF_ISA_A and M68000.
5958 */
5959 #define BASE(name, opcode, mask) \
5960 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5961 #define INSN(name, opcode, mask, feature) do { \
5962 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5963 BASE(name, opcode, mask); \
5964 } while(0)
5965 BASE(undef, 0000, 0000);
5966 INSN(arith_im, 0080, fff8, CF_ISA_A);
5967 INSN(arith_im, 0000, ff00, M68000);
5968 INSN(chk2, 00c0, f9c0, CHK2);
5969 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
5970 BASE(bitop_reg, 0100, f1c0);
5971 BASE(bitop_reg, 0140, f1c0);
5972 BASE(bitop_reg, 0180, f1c0);
5973 BASE(bitop_reg, 01c0, f1c0);
5974 INSN(movep, 0108, f138, MOVEP);
5975 INSN(arith_im, 0280, fff8, CF_ISA_A);
5976 INSN(arith_im, 0200, ff00, M68000);
5977 INSN(undef, 02c0, ffc0, M68000);
5978 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
5979 INSN(arith_im, 0480, fff8, CF_ISA_A);
5980 INSN(arith_im, 0400, ff00, M68000);
5981 INSN(undef, 04c0, ffc0, M68000);
5982 INSN(arith_im, 0600, ff00, M68000);
5983 INSN(undef, 06c0, ffc0, M68000);
5984 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
5985 INSN(arith_im, 0680, fff8, CF_ISA_A);
5986 INSN(arith_im, 0c00, ff38, CF_ISA_A);
5987 INSN(arith_im, 0c00, ff00, M68000);
5988 BASE(bitop_im, 0800, ffc0);
5989 BASE(bitop_im, 0840, ffc0);
5990 BASE(bitop_im, 0880, ffc0);
5991 BASE(bitop_im, 08c0, ffc0);
5992 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5993 INSN(arith_im, 0a00, ff00, M68000);
5994 #if defined(CONFIG_SOFTMMU)
5995 INSN(moves, 0e00, ff00, M68000);
5996 #endif
5997 INSN(cas, 0ac0, ffc0, CAS);
5998 INSN(cas, 0cc0, ffc0, CAS);
5999 INSN(cas, 0ec0, ffc0, CAS);
6000 INSN(cas2w, 0cfc, ffff, CAS);
6001 INSN(cas2l, 0efc, ffff, CAS);
6002 BASE(move, 1000, f000);
6003 BASE(move, 2000, f000);
6004 BASE(move, 3000, f000);
6005 INSN(chk, 4000, f040, M68000);
6006 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
6007 INSN(negx, 4080, fff8, CF_ISA_A);
6008 INSN(negx, 4000, ff00, M68000);
6009 INSN(undef, 40c0, ffc0, M68000);
6010 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
6011 INSN(move_from_sr, 40c0, ffc0, M68000);
6012 BASE(lea, 41c0, f1c0);
6013 BASE(clr, 4200, ff00);
6014 BASE(undef, 42c0, ffc0);
6015 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
6016 INSN(move_from_ccr, 42c0, ffc0, M68000);
6017 INSN(neg, 4480, fff8, CF_ISA_A);
6018 INSN(neg, 4400, ff00, M68000);
6019 INSN(undef, 44c0, ffc0, M68000);
6020 BASE(move_to_ccr, 44c0, ffc0);
6021 INSN(not, 4680, fff8, CF_ISA_A);
6022 INSN(not, 4600, ff00, M68000);
6023 #if defined(CONFIG_SOFTMMU)
6024 BASE(move_to_sr, 46c0, ffc0);
6025 #endif
6026 INSN(nbcd, 4800, ffc0, M68000);
6027 INSN(linkl, 4808, fff8, M68000);
6028 BASE(pea, 4840, ffc0);
6029 BASE(swap, 4840, fff8);
6030 INSN(bkpt, 4848, fff8, BKPT);
6031 INSN(movem, 48d0, fbf8, CF_ISA_A);
6032 INSN(movem, 48e8, fbf8, CF_ISA_A);
6033 INSN(movem, 4880, fb80, M68000);
6034 BASE(ext, 4880, fff8);
6035 BASE(ext, 48c0, fff8);
6036 BASE(ext, 49c0, fff8);
6037 BASE(tst, 4a00, ff00);
6038 INSN(tas, 4ac0, ffc0, CF_ISA_B);
6039 INSN(tas, 4ac0, ffc0, M68000);
6040 #if defined(CONFIG_SOFTMMU)
6041 INSN(halt, 4ac8, ffff, CF_ISA_A);
6042 #endif
6043 INSN(pulse, 4acc, ffff, CF_ISA_A);
6044 BASE(illegal, 4afc, ffff);
6045 INSN(mull, 4c00, ffc0, CF_ISA_A);
6046 INSN(mull, 4c00, ffc0, LONG_MULDIV);
6047 INSN(divl, 4c40, ffc0, CF_ISA_A);
6048 INSN(divl, 4c40, ffc0, LONG_MULDIV);
6049 INSN(sats, 4c80, fff8, CF_ISA_B);
6050 BASE(trap, 4e40, fff0);
6051 BASE(link, 4e50, fff8);
6052 BASE(unlk, 4e58, fff8);
6053 #if defined(CONFIG_SOFTMMU)
6054 INSN(move_to_usp, 4e60, fff8, USP);
6055 INSN(move_from_usp, 4e68, fff8, USP);
6056 INSN(reset, 4e70, ffff, M68000);
6057 BASE(stop, 4e72, ffff);
6058 BASE(rte, 4e73, ffff);
6059 INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
6060 INSN(m68k_movec, 4e7a, fffe, MOVEC);
6061 #endif
6062 BASE(nop, 4e71, ffff);
6063 INSN(rtd, 4e74, ffff, RTD);
6064 BASE(rts, 4e75, ffff);
6065 INSN(rtr, 4e77, ffff, M68000);
6066 BASE(jump, 4e80, ffc0);
6067 BASE(jump, 4ec0, ffc0);
6068 INSN(addsubq, 5000, f080, M68000);
6069 BASE(addsubq, 5080, f0c0);
6070 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
6071 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
6072 INSN(dbcc, 50c8, f0f8, M68000);
6073 INSN(tpf, 51f8, fff8, CF_ISA_A);
6074
6075 /* Branch instructions. */
6076 BASE(branch, 6000, f000);
6077 /* Disable long branch instructions, then add back the ones we want. */
6078 BASE(undef, 60ff, f0ff); /* All long branches. */
6079 INSN(branch, 60ff, f0ff, CF_ISA_B);
6080 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
6081 INSN(branch, 60ff, ffff, BRAL);
6082 INSN(branch, 60ff, f0ff, BCCL);
6083
6084 BASE(moveq, 7000, f100);
6085 INSN(mvzs, 7100, f100, CF_ISA_B);
6086 BASE(or, 8000, f000);
6087 BASE(divw, 80c0, f0c0);
6088 INSN(sbcd_reg, 8100, f1f8, M68000);
6089 INSN(sbcd_mem, 8108, f1f8, M68000);
6090 BASE(addsub, 9000, f000);
6091 INSN(undef, 90c0, f0c0, CF_ISA_A);
6092 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
6093 INSN(subx_reg, 9100, f138, M68000);
6094 INSN(subx_mem, 9108, f138, M68000);
6095 INSN(suba, 91c0, f1c0, CF_ISA_A);
6096 INSN(suba, 90c0, f0c0, M68000);
6097
6098 BASE(undef_mac, a000, f000);
6099 INSN(mac, a000, f100, CF_EMAC);
6100 INSN(from_mac, a180, f9b0, CF_EMAC);
6101 INSN(move_mac, a110, f9fc, CF_EMAC);
6102 INSN(from_macsr,a980, f9f0, CF_EMAC);
6103 INSN(from_mask, ad80, fff0, CF_EMAC);
6104 INSN(from_mext, ab80, fbf0, CF_EMAC);
6105 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
6106 INSN(to_mac, a100, f9c0, CF_EMAC);
6107 INSN(to_macsr, a900, ffc0, CF_EMAC);
6108 INSN(to_mext, ab00, fbc0, CF_EMAC);
6109 INSN(to_mask, ad00, ffc0, CF_EMAC);
6110
6111 INSN(mov3q, a140, f1c0, CF_ISA_B);
6112 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
6113 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
6114 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
6115 INSN(cmp, b080, f1c0, CF_ISA_A);
6116 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
6117 INSN(cmp, b000, f100, M68000);
6118 INSN(eor, b100, f100, M68000);
6119 INSN(cmpm, b108, f138, M68000);
6120 INSN(cmpa, b0c0, f0c0, M68000);
6121 INSN(eor, b180, f1c0, CF_ISA_A);
6122 BASE(and, c000, f000);
6123 INSN(exg_dd, c140, f1f8, M68000);
6124 INSN(exg_aa, c148, f1f8, M68000);
6125 INSN(exg_da, c188, f1f8, M68000);
6126 BASE(mulw, c0c0, f0c0);
6127 INSN(abcd_reg, c100, f1f8, M68000);
6128 INSN(abcd_mem, c108, f1f8, M68000);
6129 BASE(addsub, d000, f000);
6130 INSN(undef, d0c0, f0c0, CF_ISA_A);
6131 INSN(addx_reg, d180, f1f8, CF_ISA_A);
6132 INSN(addx_reg, d100, f138, M68000);
6133 INSN(addx_mem, d108, f138, M68000);
6134 INSN(adda, d1c0, f1c0, CF_ISA_A);
6135 INSN(adda, d0c0, f0c0, M68000);
6136 INSN(shift_im, e080, f0f0, CF_ISA_A);
6137 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
6138 INSN(shift8_im, e000, f0f0, M68000);
6139 INSN(shift16_im, e040, f0f0, M68000);
6140 INSN(shift_im, e080, f0f0, M68000);
6141 INSN(shift8_reg, e020, f0f0, M68000);
6142 INSN(shift16_reg, e060, f0f0, M68000);
6143 INSN(shift_reg, e0a0, f0f0, M68000);
6144 INSN(shift_mem, e0c0, fcc0, M68000);
6145 INSN(rotate_im, e090, f0f0, M68000);
6146 INSN(rotate8_im, e010, f0f0, M68000);
6147 INSN(rotate16_im, e050, f0f0, M68000);
6148 INSN(rotate_reg, e0b0, f0f0, M68000);
6149 INSN(rotate8_reg, e030, f0f0, M68000);
6150 INSN(rotate16_reg, e070, f0f0, M68000);
6151 INSN(rotate_mem, e4c0, fcc0, M68000);
6152 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
6153 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
6154 INSN(bfins_mem, efc0, ffc0, BITFIELD);
6155 INSN(bfins_reg, efc0, fff8, BITFIELD);
6156 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
6157 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
6158 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
6159 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
6160 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
6161 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
6162 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
6163 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
6164 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
6165 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
6166 BASE(undef_fpu, f000, f000);
6167 INSN(fpu, f200, ffc0, CF_FPU);
6168 INSN(fbcc, f280, ffc0, CF_FPU);
6169 INSN(fpu, f200, ffc0, FPU);
6170 INSN(fscc, f240, ffc0, FPU);
6171 INSN(fbcc, f280, ff80, FPU);
6172 #if defined(CONFIG_SOFTMMU)
6173 INSN(frestore, f340, ffc0, CF_FPU);
6174 INSN(fsave, f300, ffc0, CF_FPU);
6175 INSN(frestore, f340, ffc0, FPU);
6176 INSN(fsave, f300, ffc0, FPU);
6177 INSN(intouch, f340, ffc0, CF_ISA_A);
6178 INSN(cpushl, f428, ff38, CF_ISA_A);
6179 INSN(cpush, f420, ff20, M68040);
6180 INSN(cinv, f400, ff20, M68040);
6181 INSN(pflush, f500, ffe0, M68040);
6182 INSN(ptest, f548, ffd8, M68040);
6183 INSN(wddata, fb00, ff00, CF_ISA_A);
6184 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
6185 #endif
6186 INSN(move16_mem, f600, ffe0, M68040);
6187 INSN(move16_reg, f620, fff8, M68040);
6188 #undef INSN
6189 }
6190
6191 static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
6192 {
6193 DisasContext *dc = container_of(dcbase, DisasContext, base);
6194 CPUM68KState *env = cpu->env_ptr;
6195
6196 dc->env = env;
6197 dc->pc = dc->base.pc_first;
6198 dc->cc_op = CC_OP_DYNAMIC;
6199 dc->cc_op_synced = 1;
6200 dc->done_mac = 0;
6201 dc->writeback_mask = 0;
6202 init_release_array(dc);
6203
6204 dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
6205 /* If architectural single step active, limit to 1 */
6206 if (is_singlestepping(dc)) {
6207 dc->base.max_insns = 1;
6208 }
6209 }
6210
6211 static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
6212 {
6213 }
6214
6215 static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
6216 {
6217 DisasContext *dc = container_of(dcbase, DisasContext, base);
6218 tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
6219 }
6220
6221 static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
6222 const CPUBreakpoint *bp)
6223 {
6224 DisasContext *dc = container_of(dcbase, DisasContext, base);
6225
6226 gen_exception(dc, dc->base.pc_next, EXCP_DEBUG);
6227 /*
6228 * The address covered by the breakpoint must be included in
6229 * [tb->pc, tb->pc + tb->size) in order to for it to be
6230 * properly cleared -- thus we increment the PC here so that
6231 * the logic setting tb->size below does the right thing.
6232 */
6233 dc->base.pc_next += 2;
6234
6235 return true;
6236 }
6237
6238 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
6239 {
6240 DisasContext *dc = container_of(dcbase, DisasContext, base);
6241 CPUM68KState *env = cpu->env_ptr;
6242 uint16_t insn = read_im16(env, dc);
6243
6244 opcode_table[insn](env, dc, insn);
6245 do_writebacks(dc);
6246 do_release(dc);
6247
6248 dc->base.pc_next = dc->pc;
6249
6250 if (dc->base.is_jmp == DISAS_NEXT) {
6251 /*
6252 * Stop translation when the next insn might touch a new page.
6253 * This ensures that prefetch aborts at the right place.
6254 *
6255 * We cannot determine the size of the next insn without
6256 * completely decoding it. However, the maximum insn size
6257 * is 32 bytes, so end if we do not have that much remaining.
6258 * This may produce several small TBs at the end of each page,
6259 * but they will all be linked with goto_tb.
6260 *
6261 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6262 * smaller than MC68020's.
6263 */
6264 target_ulong start_page_offset
6265 = dc->pc - (dc->base.pc_first & TARGET_PAGE_MASK);
6266
6267 if (start_page_offset >= TARGET_PAGE_SIZE - 32) {
6268 dc->base.is_jmp = DISAS_TOO_MANY;
6269 }
6270 }
6271 }
6272
6273 static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
6274 {
6275 DisasContext *dc = container_of(dcbase, DisasContext, base);
6276
6277 switch (dc->base.is_jmp) {
6278 case DISAS_NORETURN:
6279 break;
6280 case DISAS_TOO_MANY:
6281 update_cc_op(dc);
6282 if (is_singlestepping(dc)) {
6283 tcg_gen_movi_i32(QREG_PC, dc->pc);
6284 gen_singlestep_exception(dc);
6285 } else {
6286 gen_jmp_tb(dc, 0, dc->pc);
6287 }
6288 break;
6289 case DISAS_JUMP:
6290 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6291 if (is_singlestepping(dc)) {
6292 gen_singlestep_exception(dc);
6293 } else {
6294 tcg_gen_lookup_and_goto_ptr();
6295 }
6296 break;
6297 case DISAS_EXIT:
6298 /*
6299 * We updated CC_OP and PC in gen_exit_tb, but also modified
6300 * other state that may require returning to the main loop.
6301 */
6302 if (is_singlestepping(dc)) {
6303 gen_singlestep_exception(dc);
6304 } else {
6305 tcg_gen_exit_tb(NULL, 0);
6306 }
6307 break;
6308 default:
6309 g_assert_not_reached();
6310 }
6311 }
6312
6313 static void m68k_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
6314 {
6315 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
6316 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
6317 }
6318
6319 static const TranslatorOps m68k_tr_ops = {
6320 .init_disas_context = m68k_tr_init_disas_context,
6321 .tb_start = m68k_tr_tb_start,
6322 .insn_start = m68k_tr_insn_start,
6323 .breakpoint_check = m68k_tr_breakpoint_check,
6324 .translate_insn = m68k_tr_translate_insn,
6325 .tb_stop = m68k_tr_tb_stop,
6326 .disas_log = m68k_tr_disas_log,
6327 };
6328
6329 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
6330 {
6331 DisasContext dc;
6332 translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
6333 }
6334
6335 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
6336 {
6337 floatx80 a = { .high = high, .low = low };
6338 union {
6339 float64 f64;
6340 double d;
6341 } u;
6342
6343 u.f64 = floatx80_to_float64(a, &env->fp_status);
6344 return u.d;
6345 }
6346
6347 void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags)
6348 {
6349 M68kCPU *cpu = M68K_CPU(cs);
6350 CPUM68KState *env = &cpu->env;
6351 int i;
6352 uint16_t sr;
6353 for (i = 0; i < 8; i++) {
6354 qemu_fprintf(f, "D%d = %08x A%d = %08x "
6355 "F%d = %04x %016"PRIx64" (%12g)\n",
6356 i, env->dregs[i], i, env->aregs[i],
6357 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
6358 floatx80_to_double(env, env->fregs[i].l.upper,
6359 env->fregs[i].l.lower));
6360 }
6361 qemu_fprintf(f, "PC = %08x ", env->pc);
6362 sr = env->sr | cpu_m68k_get_ccr(env);
6363 qemu_fprintf(f, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6364 sr, (sr & SR_T) >> SR_T_SHIFT, (sr & SR_I) >> SR_I_SHIFT,
6365 (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I',
6366 (sr & CCF_X) ? 'X' : '-', (sr & CCF_N) ? 'N' : '-',
6367 (sr & CCF_Z) ? 'Z' : '-', (sr & CCF_V) ? 'V' : '-',
6368 (sr & CCF_C) ? 'C' : '-');
6369 qemu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
6370 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
6371 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
6372 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
6373 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
6374 qemu_fprintf(f, "\n "
6375 "FPCR = %04x ", env->fpcr);
6376 switch (env->fpcr & FPCR_PREC_MASK) {
6377 case FPCR_PREC_X:
6378 qemu_fprintf(f, "X ");
6379 break;
6380 case FPCR_PREC_S:
6381 qemu_fprintf(f, "S ");
6382 break;
6383 case FPCR_PREC_D:
6384 qemu_fprintf(f, "D ");
6385 break;
6386 }
6387 switch (env->fpcr & FPCR_RND_MASK) {
6388 case FPCR_RND_N:
6389 qemu_fprintf(f, "RN ");
6390 break;
6391 case FPCR_RND_Z:
6392 qemu_fprintf(f, "RZ ");
6393 break;
6394 case FPCR_RND_M:
6395 qemu_fprintf(f, "RM ");
6396 break;
6397 case FPCR_RND_P:
6398 qemu_fprintf(f, "RP ");
6399 break;
6400 }
6401 qemu_fprintf(f, "\n");
6402 #ifdef CONFIG_SOFTMMU
6403 qemu_fprintf(f, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6404 env->current_sp == M68K_SSP ? "->" : " ", env->sp[M68K_SSP],
6405 env->current_sp == M68K_USP ? "->" : " ", env->sp[M68K_USP],
6406 env->current_sp == M68K_ISP ? "->" : " ", env->sp[M68K_ISP]);
6407 qemu_fprintf(f, "VBR = 0x%08x\n", env->vbr);
6408 qemu_fprintf(f, "SFC = %x DFC %x\n", env->sfc, env->dfc);
6409 qemu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6410 env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp);
6411 qemu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6412 env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1],
6413 env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]);
6414 qemu_fprintf(f, "MMUSR %08x, fault at %08x\n",
6415 env->mmu.mmusr, env->mmu.ar);
6416 #endif
6417 }
6418
6419 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
6420 target_ulong *data)
6421 {
6422 int cc_op = data[1];
6423 env->pc = data[0];
6424 if (cc_op != CC_OP_DYNAMIC) {
6425 env->cc_op = cc_op;
6426 }
6427 }
AR7 emulation for QEMU