4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "translate-a64.h"
39 #include "qemu/atomic128.h"
41 static TCGv_i64 cpu_X
[32];
42 static TCGv_i64 cpu_pc
;
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_high
;
47 static const char *regnames
[] = {
48 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
49 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
50 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
51 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 A64_SHIFT_TYPE_LSL
= 0,
56 A64_SHIFT_TYPE_LSR
= 1,
57 A64_SHIFT_TYPE_ASR
= 2,
58 A64_SHIFT_TYPE_ROR
= 3
61 /* Table based decoder typedefs - used when the relevant bits for decode
62 * are too awkwardly scattered across the instruction (eg SIMD).
64 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
66 typedef struct AArch64DecodeTable
{
69 AArch64DecodeFn
*disas_fn
;
72 /* initialize TCG globals. */
73 void a64_translate_init(void)
77 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
78 offsetof(CPUARMState
, pc
),
80 for (i
= 0; i
< 32; i
++) {
81 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
82 offsetof(CPUARMState
, xregs
[i
]),
86 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
87 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
91 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
93 static int get_a64_user_mem_index(DisasContext
*s
)
96 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
97 * which is the usual mmu_idx for this cpu state.
99 ARMMMUIdx useridx
= s
->mmu_idx
;
103 * We have pre-computed the condition for AccType_UNPRIV.
104 * Therefore we should never get here with a mmu_idx for
105 * which we do not know the corresponding user mmu_idx.
108 case ARMMMUIdx_E10_1
:
109 case ARMMMUIdx_E10_1_PAN
:
110 useridx
= ARMMMUIdx_E10_0
;
112 case ARMMMUIdx_E20_2
:
113 case ARMMMUIdx_E20_2_PAN
:
114 useridx
= ARMMMUIdx_E20_0
;
116 case ARMMMUIdx_SE10_1
:
117 case ARMMMUIdx_SE10_1_PAN
:
118 useridx
= ARMMMUIdx_SE10_0
;
120 case ARMMMUIdx_SE20_2
:
121 case ARMMMUIdx_SE20_2_PAN
:
122 useridx
= ARMMMUIdx_SE20_0
;
125 g_assert_not_reached();
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void gen_a64_set_pc_im(uint64_t val
)
156 tcg_gen_movi_i64(cpu_pc
, val
);
160 * Handle Top Byte Ignore (TBI) bits.
162 * If address tagging is enabled via the TCR TBI bits:
163 * + for EL2 and EL3 there is only one TBI bit, and if it is set
164 * then the address is zero-extended, clearing bits [63:56]
165 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
166 * and TBI1 controls addressses with bit 55 == 1.
167 * If the appropriate TBI bit is set for the address then
168 * the address is sign-extended from bit 55 into bits [63:56]
170 * Here We have concatenated TBI{1,0} into tbi.
172 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
173 TCGv_i64 src
, int tbi
)
176 /* Load unmodified address */
177 tcg_gen_mov_i64(dst
, src
);
178 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
179 /* Force tag byte to all zero */
180 tcg_gen_extract_i64(dst
, src
, 0, 56);
182 /* Sign-extend from bit 55. */
183 tcg_gen_sextract_i64(dst
, src
, 0, 56);
187 /* tbi0 but !tbi1: only use the extension if positive */
188 tcg_gen_and_i64(dst
, dst
, src
);
191 /* !tbi0 but tbi1: only use the extension if negative */
192 tcg_gen_or_i64(dst
, dst
, src
);
195 /* tbi0 and tbi1: always use the extension */
198 g_assert_not_reached();
203 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
206 * If address tagging is enabled for instructions via the TCR TBI bits,
207 * then loading an address into the PC will clear out any tag.
209 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
213 * Handle MTE and/or TBI.
215 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
216 * for the tag to be present in the FAR_ELx register. But for user-only
217 * mode we do not have a TLB with which to implement this, so we must
218 * remove the top byte now.
220 * Always return a fresh temporary that we can increment independently
221 * of the write-back address.
224 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
226 TCGv_i64 clean
= new_tmp_a64(s
);
227 #ifdef CONFIG_USER_ONLY
228 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
230 tcg_gen_mov_i64(clean
, addr
);
235 /* Insert a zero tag into src, with the result at dst. */
236 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
238 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
241 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
242 MMUAccessType acc
, int log2_size
)
244 TCGv_i32 t_acc
= tcg_const_i32(acc
);
245 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
246 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
248 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
249 tcg_temp_free_i32(t_acc
);
250 tcg_temp_free_i32(t_idx
);
251 tcg_temp_free_i32(t_size
);
255 * For MTE, check a single logical or atomic access. This probes a single
256 * address, the exact one specified. The size and alignment of the access
257 * is not relevant to MTE, per se, but watchpoints do require the size,
258 * and we want to recognize those before making any other changes to state.
260 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
261 bool is_write
, bool tag_checked
,
262 int log2_size
, bool is_unpriv
,
265 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
270 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
271 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
272 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
273 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
274 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
275 tcg_desc
= tcg_const_i32(desc
);
277 ret
= new_tmp_a64(s
);
278 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
279 tcg_temp_free_i32(tcg_desc
);
283 return clean_data_tbi(s
, addr
);
286 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
287 bool tag_checked
, int log2_size
)
289 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
290 false, get_mem_index(s
));
294 * For MTE, check multiple logical sequential accesses.
296 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
297 bool tag_checked
, int size
)
299 if (tag_checked
&& s
->mte_active
[0]) {
304 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
305 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
306 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
307 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
308 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
309 tcg_desc
= tcg_const_i32(desc
);
311 ret
= new_tmp_a64(s
);
312 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
313 tcg_temp_free_i32(tcg_desc
);
317 return clean_data_tbi(s
, addr
);
320 typedef struct DisasCompare64
{
325 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
329 arm_test_cc(&c32
, cc
);
331 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
332 * properly. The NE/EQ comparisons are also fine with this choice. */
333 c64
->cond
= c32
.cond
;
334 c64
->value
= tcg_temp_new_i64();
335 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
340 static void a64_free_cc(DisasCompare64
*c64
)
342 tcg_temp_free_i64(c64
->value
);
345 static void gen_exception_internal(int excp
)
347 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
349 assert(excp_is_internal(excp
));
350 gen_helper_exception_internal(cpu_env
, tcg_excp
);
351 tcg_temp_free_i32(tcg_excp
);
354 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
356 gen_a64_set_pc_im(pc
);
357 gen_exception_internal(excp
);
358 s
->base
.is_jmp
= DISAS_NORETURN
;
361 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
365 gen_a64_set_pc_im(s
->pc_curr
);
366 tcg_syn
= tcg_const_i32(syndrome
);
367 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
368 tcg_temp_free_i32(tcg_syn
);
369 s
->base
.is_jmp
= DISAS_NORETURN
;
372 static void gen_step_complete_exception(DisasContext
*s
)
374 /* We just completed step of an insn. Move from Active-not-pending
375 * to Active-pending, and then also take the swstep exception.
376 * This corresponds to making the (IMPDEF) choice to prioritize
377 * swstep exceptions over asynchronous exceptions taken to an exception
378 * level where debug is disabled. This choice has the advantage that
379 * we do not need to maintain internal state corresponding to the
380 * ISV/EX syndrome bits between completion of the step and generation
381 * of the exception, and our syndrome information is always correct.
384 gen_swstep_exception(s
, 1, s
->is_ldex
);
385 s
->base
.is_jmp
= DISAS_NORETURN
;
388 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
390 /* No direct tb linking with singlestep (either QEMU's or the ARM
391 * debug architecture kind) or deterministic io
393 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
394 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
398 #ifndef CONFIG_USER_ONLY
399 /* Only link tbs from inside the same guest page */
400 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
408 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
410 const TranslationBlock
*tb
;
413 if (use_goto_tb(s
, n
, dest
)) {
415 gen_a64_set_pc_im(dest
);
416 tcg_gen_exit_tb(tb
, n
);
417 s
->base
.is_jmp
= DISAS_NORETURN
;
419 gen_a64_set_pc_im(dest
);
421 gen_step_complete_exception(s
);
422 } else if (s
->base
.singlestep_enabled
) {
423 gen_exception_internal(EXCP_DEBUG
);
425 tcg_gen_lookup_and_goto_ptr();
426 s
->base
.is_jmp
= DISAS_NORETURN
;
431 static void init_tmp_a64_array(DisasContext
*s
)
433 #ifdef CONFIG_DEBUG_TCG
434 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
436 s
->tmp_a64_count
= 0;
439 static void free_tmp_a64(DisasContext
*s
)
442 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
443 tcg_temp_free_i64(s
->tmp_a64
[i
]);
445 init_tmp_a64_array(s
);
448 TCGv_i64
new_tmp_a64(DisasContext
*s
)
450 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
451 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
454 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
456 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
457 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
460 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
462 TCGv_i64 t
= new_tmp_a64(s
);
463 tcg_gen_movi_i64(t
, 0);
468 * Register access functions
470 * These functions are used for directly accessing a register in where
471 * changes to the final register value are likely to be made. If you
472 * need to use a register for temporary calculation (e.g. index type
473 * operations) use the read_* form.
475 * B1.2.1 Register mappings
477 * In instruction register encoding 31 can refer to ZR (zero register) or
478 * the SP (stack pointer) depending on context. In QEMU's case we map SP
479 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
480 * This is the point of the _sp forms.
482 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
485 return new_tmp_a64_zero(s
);
491 /* register access for when 31 == SP */
492 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
497 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
498 * representing the register contents. This TCGv is an auto-freed
499 * temporary so it need not be explicitly freed, and may be modified.
501 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
503 TCGv_i64 v
= new_tmp_a64(s
);
506 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
508 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
511 tcg_gen_movi_i64(v
, 0);
516 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
518 TCGv_i64 v
= new_tmp_a64(s
);
520 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
522 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
527 /* Return the offset into CPUARMState of a slice (from
528 * the least significant end) of FP register Qn (ie
530 * (Note that this is not the same mapping as for A32; see cpu.h)
532 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
534 return vec_reg_offset(s
, regno
, 0, size
);
537 /* Offset of the high half of the 128 bit vector Qn */
538 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
540 return vec_reg_offset(s
, regno
, 1, MO_64
);
543 /* Convenience accessors for reading and writing single and double
544 * FP registers. Writing clears the upper parts of the associated
545 * 128 bit vector register, as required by the architecture.
546 * Note that unlike the GP register accessors, the values returned
547 * by the read functions must be manually freed.
549 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
551 TCGv_i64 v
= tcg_temp_new_i64();
553 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
557 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
559 TCGv_i32 v
= tcg_temp_new_i32();
561 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
565 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
567 TCGv_i32 v
= tcg_temp_new_i32();
569 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
573 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
574 * If SVE is not enabled, then there are only 128 bits in the vector.
576 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
578 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
579 unsigned vsz
= vec_full_reg_size(s
);
581 /* Nop move, with side effect of clearing the tail. */
582 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
585 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
587 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
589 tcg_gen_st_i64(v
, cpu_env
, ofs
);
590 clear_vec_high(s
, false, reg
);
593 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
595 TCGv_i64 tmp
= tcg_temp_new_i64();
597 tcg_gen_extu_i32_i64(tmp
, v
);
598 write_fp_dreg(s
, reg
, tmp
);
599 tcg_temp_free_i64(tmp
);
602 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
603 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
604 GVecGen2Fn
*gvec_fn
, int vece
)
606 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
607 is_q
? 16 : 8, vec_full_reg_size(s
));
610 /* Expand a 2-operand + immediate AdvSIMD vector operation using
611 * an expander function.
613 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
614 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
616 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
617 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
620 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
621 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
622 GVecGen3Fn
*gvec_fn
, int vece
)
624 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
625 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
628 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
629 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
630 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
632 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
633 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
634 is_q
? 16 : 8, vec_full_reg_size(s
));
637 /* Expand a 2-operand operation using an out-of-line helper. */
638 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
639 int rn
, int data
, gen_helper_gvec_2
*fn
)
641 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
642 vec_full_reg_offset(s
, rn
),
643 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
646 /* Expand a 3-operand operation using an out-of-line helper. */
647 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
648 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
650 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
651 vec_full_reg_offset(s
, rn
),
652 vec_full_reg_offset(s
, rm
),
653 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
656 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
657 * an out-of-line helper.
659 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
660 int rm
, bool is_fp16
, int data
,
661 gen_helper_gvec_3_ptr
*fn
)
663 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
664 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
665 vec_full_reg_offset(s
, rn
),
666 vec_full_reg_offset(s
, rm
), fpst
,
667 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
668 tcg_temp_free_ptr(fpst
);
671 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
672 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
673 int rm
, gen_helper_gvec_3_ptr
*fn
)
675 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
677 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
678 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
679 vec_full_reg_offset(s
, rn
),
680 vec_full_reg_offset(s
, rm
), qc_ptr
,
681 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
682 tcg_temp_free_ptr(qc_ptr
);
685 /* Expand a 4-operand operation using an out-of-line helper. */
686 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
687 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
689 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
690 vec_full_reg_offset(s
, rn
),
691 vec_full_reg_offset(s
, rm
),
692 vec_full_reg_offset(s
, ra
),
693 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
697 * Expand a 4-operand + fpstatus pointer + simd data value operation using
698 * an out-of-line helper.
700 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
701 int rm
, int ra
, bool is_fp16
, int data
,
702 gen_helper_gvec_4_ptr
*fn
)
704 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
705 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
706 vec_full_reg_offset(s
, rn
),
707 vec_full_reg_offset(s
, rm
),
708 vec_full_reg_offset(s
, ra
), fpst
,
709 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
710 tcg_temp_free_ptr(fpst
);
713 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
714 * than the 32 bit equivalent.
716 static inline void gen_set_NZ64(TCGv_i64 result
)
718 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
719 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
722 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
723 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
726 gen_set_NZ64(result
);
728 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
729 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
731 tcg_gen_movi_i32(cpu_CF
, 0);
732 tcg_gen_movi_i32(cpu_VF
, 0);
735 /* dest = T0 + T1; compute C, N, V and Z flags */
736 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
739 TCGv_i64 result
, flag
, tmp
;
740 result
= tcg_temp_new_i64();
741 flag
= tcg_temp_new_i64();
742 tmp
= tcg_temp_new_i64();
744 tcg_gen_movi_i64(tmp
, 0);
745 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
747 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
749 gen_set_NZ64(result
);
751 tcg_gen_xor_i64(flag
, result
, t0
);
752 tcg_gen_xor_i64(tmp
, t0
, t1
);
753 tcg_gen_andc_i64(flag
, flag
, tmp
);
754 tcg_temp_free_i64(tmp
);
755 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
757 tcg_gen_mov_i64(dest
, result
);
758 tcg_temp_free_i64(result
);
759 tcg_temp_free_i64(flag
);
761 /* 32 bit arithmetic */
762 TCGv_i32 t0_32
= tcg_temp_new_i32();
763 TCGv_i32 t1_32
= tcg_temp_new_i32();
764 TCGv_i32 tmp
= tcg_temp_new_i32();
766 tcg_gen_movi_i32(tmp
, 0);
767 tcg_gen_extrl_i64_i32(t0_32
, t0
);
768 tcg_gen_extrl_i64_i32(t1_32
, t1
);
769 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
770 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
771 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
772 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
773 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
774 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
776 tcg_temp_free_i32(tmp
);
777 tcg_temp_free_i32(t0_32
);
778 tcg_temp_free_i32(t1_32
);
782 /* dest = T0 - T1; compute C, N, V and Z flags */
783 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
786 /* 64 bit arithmetic */
787 TCGv_i64 result
, flag
, tmp
;
789 result
= tcg_temp_new_i64();
790 flag
= tcg_temp_new_i64();
791 tcg_gen_sub_i64(result
, t0
, t1
);
793 gen_set_NZ64(result
);
795 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
796 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
798 tcg_gen_xor_i64(flag
, result
, t0
);
799 tmp
= tcg_temp_new_i64();
800 tcg_gen_xor_i64(tmp
, t0
, t1
);
801 tcg_gen_and_i64(flag
, flag
, tmp
);
802 tcg_temp_free_i64(tmp
);
803 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
804 tcg_gen_mov_i64(dest
, result
);
805 tcg_temp_free_i64(flag
);
806 tcg_temp_free_i64(result
);
808 /* 32 bit arithmetic */
809 TCGv_i32 t0_32
= tcg_temp_new_i32();
810 TCGv_i32 t1_32
= tcg_temp_new_i32();
813 tcg_gen_extrl_i64_i32(t0_32
, t0
);
814 tcg_gen_extrl_i64_i32(t1_32
, t1
);
815 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
816 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
817 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
818 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
819 tmp
= tcg_temp_new_i32();
820 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
821 tcg_temp_free_i32(t0_32
);
822 tcg_temp_free_i32(t1_32
);
823 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
824 tcg_temp_free_i32(tmp
);
825 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
829 /* dest = T0 + T1 + CF; do not compute flags. */
830 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
832 TCGv_i64 flag
= tcg_temp_new_i64();
833 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
834 tcg_gen_add_i64(dest
, t0
, t1
);
835 tcg_gen_add_i64(dest
, dest
, flag
);
836 tcg_temp_free_i64(flag
);
839 tcg_gen_ext32u_i64(dest
, dest
);
843 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
844 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
847 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
848 result
= tcg_temp_new_i64();
849 cf_64
= tcg_temp_new_i64();
850 vf_64
= tcg_temp_new_i64();
851 tmp
= tcg_const_i64(0);
853 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
854 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
855 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
856 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
857 gen_set_NZ64(result
);
859 tcg_gen_xor_i64(vf_64
, result
, t0
);
860 tcg_gen_xor_i64(tmp
, t0
, t1
);
861 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
862 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
864 tcg_gen_mov_i64(dest
, result
);
866 tcg_temp_free_i64(tmp
);
867 tcg_temp_free_i64(vf_64
);
868 tcg_temp_free_i64(cf_64
);
869 tcg_temp_free_i64(result
);
871 TCGv_i32 t0_32
, t1_32
, tmp
;
872 t0_32
= tcg_temp_new_i32();
873 t1_32
= tcg_temp_new_i32();
874 tmp
= tcg_const_i32(0);
876 tcg_gen_extrl_i64_i32(t0_32
, t0
);
877 tcg_gen_extrl_i64_i32(t1_32
, t1
);
878 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
879 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
881 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
882 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
883 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
884 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
885 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
887 tcg_temp_free_i32(tmp
);
888 tcg_temp_free_i32(t1_32
);
889 tcg_temp_free_i32(t0_32
);
894 * Load/Store generators
898 * Store from GPR register to memory.
900 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
901 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
903 unsigned int iss_srt
,
904 bool iss_sf
, bool iss_ar
)
906 memop
= finalize_memop(s
, memop
);
907 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
912 syn
= syn_data_abort_with_iss(0,
918 0, 0, 0, 0, 0, false);
919 disas_set_insn_syndrome(s
, syn
);
923 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
924 TCGv_i64 tcg_addr
, MemOp memop
,
926 unsigned int iss_srt
,
927 bool iss_sf
, bool iss_ar
)
929 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
930 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
934 * Load from memory to GPR register
936 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
937 MemOp memop
, bool extend
, int memidx
,
938 bool iss_valid
, unsigned int iss_srt
,
939 bool iss_sf
, bool iss_ar
)
941 memop
= finalize_memop(s
, memop
);
942 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
944 if (extend
&& (memop
& MO_SIGN
)) {
945 g_assert((memop
& MO_SIZE
) <= MO_32
);
946 tcg_gen_ext32u_i64(dest
, dest
);
952 syn
= syn_data_abort_with_iss(0,
954 (memop
& MO_SIGN
) != 0,
958 0, 0, 0, 0, 0, false);
959 disas_set_insn_syndrome(s
, syn
);
963 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
964 MemOp memop
, bool extend
,
965 bool iss_valid
, unsigned int iss_srt
,
966 bool iss_sf
, bool iss_ar
)
968 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
969 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
973 * Store from FP register to memory
975 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
977 /* This writes the bottom N bits of a 128 bit wide vector to memory */
978 TCGv_i64 tmplo
= tcg_temp_new_i64();
981 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
984 mop
= finalize_memop(s
, size
);
985 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
987 bool be
= s
->be_data
== MO_BE
;
988 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
989 TCGv_i64 tmphi
= tcg_temp_new_i64();
991 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
993 mop
= s
->be_data
| MO_Q
;
994 tcg_gen_qemu_st_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
995 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
996 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
997 tcg_gen_qemu_st_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
998 get_mem_index(s
), mop
);
1000 tcg_temp_free_i64(tcg_hiaddr
);
1001 tcg_temp_free_i64(tmphi
);
1004 tcg_temp_free_i64(tmplo
);
1008 * Load from memory to FP register
1010 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1012 /* This always zero-extends and writes to a full 128 bit wide vector */
1013 TCGv_i64 tmplo
= tcg_temp_new_i64();
1014 TCGv_i64 tmphi
= NULL
;
1018 mop
= finalize_memop(s
, size
);
1019 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
1021 bool be
= s
->be_data
== MO_BE
;
1022 TCGv_i64 tcg_hiaddr
;
1024 tmphi
= tcg_temp_new_i64();
1025 tcg_hiaddr
= tcg_temp_new_i64();
1027 mop
= s
->be_data
| MO_Q
;
1028 tcg_gen_qemu_ld_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
1029 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
1030 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1031 tcg_gen_qemu_ld_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
1032 get_mem_index(s
), mop
);
1033 tcg_temp_free_i64(tcg_hiaddr
);
1036 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1037 tcg_temp_free_i64(tmplo
);
1040 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1041 tcg_temp_free_i64(tmphi
);
1043 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1047 * Vector load/store helpers.
1049 * The principal difference between this and a FP load is that we don't
1050 * zero extend as we are filling a partial chunk of the vector register.
1051 * These functions don't support 128 bit loads/stores, which would be
1052 * normal load/store operations.
1054 * The _i32 versions are useful when operating on 32 bit quantities
1055 * (eg for floating point single or using Neon helper functions).
1058 /* Get value of an element within a vector register */
1059 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1060 int element
, MemOp memop
)
1062 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1065 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1068 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1071 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1074 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1077 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1080 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1084 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1087 g_assert_not_reached();
1091 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1092 int element
, MemOp memop
)
1094 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1097 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1100 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1103 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1106 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1110 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1113 g_assert_not_reached();
1117 /* Set value of an element within a vector register */
1118 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1119 int element
, MemOp memop
)
1121 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1124 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1127 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1130 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1133 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1136 g_assert_not_reached();
1140 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1141 int destidx
, int element
, MemOp memop
)
1143 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1146 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1149 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1152 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1155 g_assert_not_reached();
1159 /* Store from vector register to memory */
1160 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1161 TCGv_i64 tcg_addr
, MemOp mop
)
1163 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1165 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1166 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1168 tcg_temp_free_i64(tcg_tmp
);
1171 /* Load from memory to vector register */
1172 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1173 TCGv_i64 tcg_addr
, MemOp mop
)
1175 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1177 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1178 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1180 tcg_temp_free_i64(tcg_tmp
);
1183 /* Check that FP/Neon access is enabled. If it is, return
1184 * true. If not, emit code to generate an appropriate exception,
1185 * and return false; the caller should not emit any code for
1186 * the instruction. Note that this check must happen after all
1187 * unallocated-encoding checks (otherwise the syndrome information
1188 * for the resulting exception will be incorrect).
1190 static bool fp_access_check(DisasContext
*s
)
1192 if (s
->fp_excp_el
) {
1193 assert(!s
->fp_access_checked
);
1194 s
->fp_access_checked
= true;
1196 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1197 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1200 s
->fp_access_checked
= true;
1204 /* Check that SVE access is enabled. If it is, return true.
1205 * If not, emit code to generate an appropriate exception and return false.
1207 bool sve_access_check(DisasContext
*s
)
1209 if (s
->sve_excp_el
) {
1210 assert(!s
->sve_access_checked
);
1211 s
->sve_access_checked
= true;
1213 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1214 syn_sve_access_trap(), s
->sve_excp_el
);
1217 s
->sve_access_checked
= true;
1218 return fp_access_check(s
);
1222 * This utility function is for doing register extension with an
1223 * optional shift. You will likely want to pass a temporary for the
1224 * destination register. See DecodeRegExtend() in the ARM ARM.
1226 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1227 int option
, unsigned int shift
)
1229 int extsize
= extract32(option
, 0, 2);
1230 bool is_signed
= extract32(option
, 2, 1);
1235 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1238 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1241 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1244 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1250 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1253 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1256 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1259 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1265 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1269 static inline void gen_check_sp_alignment(DisasContext
*s
)
1271 /* The AArch64 architecture mandates that (if enabled via PSTATE
1272 * or SCTLR bits) there is a check that SP is 16-aligned on every
1273 * SP-relative load or store (with an exception generated if it is not).
1274 * In line with general QEMU practice regarding misaligned accesses,
1275 * we omit these checks for the sake of guest program performance.
1276 * This function is provided as a hook so we can more easily add these
1277 * checks in future (possibly as a "favour catching guest program bugs
1278 * over speed" user selectable option).
1283 * This provides a simple table based table lookup decoder. It is
1284 * intended to be used when the relevant bits for decode are too
1285 * awkwardly placed and switch/if based logic would be confusing and
1286 * deeply nested. Since it's a linear search through the table, tables
1287 * should be kept small.
1289 * It returns the first handler where insn & mask == pattern, or
1290 * NULL if there is no match.
1291 * The table is terminated by an empty mask (i.e. 0)
1293 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1296 const AArch64DecodeTable
*tptr
= table
;
1298 while (tptr
->mask
) {
1299 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1300 return tptr
->disas_fn
;
1308 * The instruction disassembly implemented here matches
1309 * the instruction encoding classifications in chapter C4
1310 * of the ARM Architecture Reference Manual (DDI0487B_a);
1311 * classification names and decode diagrams here should generally
1312 * match up with those in the manual.
1315 /* Unconditional branch (immediate)
1317 * +----+-----------+-------------------------------------+
1318 * | op | 0 0 1 0 1 | imm26 |
1319 * +----+-----------+-------------------------------------+
1321 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1323 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1325 if (insn
& (1U << 31)) {
1326 /* BL Branch with link */
1327 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1330 /* B Branch / BL Branch with link */
1332 gen_goto_tb(s
, 0, addr
);
1335 /* Compare and branch (immediate)
1336 * 31 30 25 24 23 5 4 0
1337 * +----+-------------+----+---------------------+--------+
1338 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1339 * +----+-------------+----+---------------------+--------+
1341 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1343 unsigned int sf
, op
, rt
;
1345 TCGLabel
*label_match
;
1348 sf
= extract32(insn
, 31, 1);
1349 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1350 rt
= extract32(insn
, 0, 5);
1351 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1353 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1354 label_match
= gen_new_label();
1357 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1358 tcg_cmp
, 0, label_match
);
1360 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1361 gen_set_label(label_match
);
1362 gen_goto_tb(s
, 1, addr
);
1365 /* Test and branch (immediate)
1366 * 31 30 25 24 23 19 18 5 4 0
1367 * +----+-------------+----+-------+-------------+------+
1368 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1369 * +----+-------------+----+-------+-------------+------+
1371 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1373 unsigned int bit_pos
, op
, rt
;
1375 TCGLabel
*label_match
;
1378 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1379 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1380 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1381 rt
= extract32(insn
, 0, 5);
1383 tcg_cmp
= tcg_temp_new_i64();
1384 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1385 label_match
= gen_new_label();
1388 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1389 tcg_cmp
, 0, label_match
);
1390 tcg_temp_free_i64(tcg_cmp
);
1391 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1392 gen_set_label(label_match
);
1393 gen_goto_tb(s
, 1, addr
);
1396 /* Conditional branch (immediate)
1397 * 31 25 24 23 5 4 3 0
1398 * +---------------+----+---------------------+----+------+
1399 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1400 * +---------------+----+---------------------+----+------+
1402 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1407 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1408 unallocated_encoding(s
);
1411 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1412 cond
= extract32(insn
, 0, 4);
1416 /* genuinely conditional branches */
1417 TCGLabel
*label_match
= gen_new_label();
1418 arm_gen_test_cc(cond
, label_match
);
1419 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1420 gen_set_label(label_match
);
1421 gen_goto_tb(s
, 1, addr
);
1423 /* 0xe and 0xf are both "always" conditions */
1424 gen_goto_tb(s
, 0, addr
);
1428 /* HINT instruction group, including various allocated HINTs */
1429 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1430 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1432 unsigned int selector
= crm
<< 3 | op2
;
1435 unallocated_encoding(s
);
1440 case 0b00000: /* NOP */
1442 case 0b00011: /* WFI */
1443 s
->base
.is_jmp
= DISAS_WFI
;
1445 case 0b00001: /* YIELD */
1446 /* When running in MTTCG we don't generate jumps to the yield and
1447 * WFE helpers as it won't affect the scheduling of other vCPUs.
1448 * If we wanted to more completely model WFE/SEV so we don't busy
1449 * spin unnecessarily we would need to do something more involved.
1451 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1452 s
->base
.is_jmp
= DISAS_YIELD
;
1455 case 0b00010: /* WFE */
1456 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1457 s
->base
.is_jmp
= DISAS_WFE
;
1460 case 0b00100: /* SEV */
1461 case 0b00101: /* SEVL */
1462 /* we treat all as NOP at least for now */
1464 case 0b00111: /* XPACLRI */
1465 if (s
->pauth_active
) {
1466 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1469 case 0b01000: /* PACIA1716 */
1470 if (s
->pauth_active
) {
1471 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1474 case 0b01010: /* PACIB1716 */
1475 if (s
->pauth_active
) {
1476 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1479 case 0b01100: /* AUTIA1716 */
1480 if (s
->pauth_active
) {
1481 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1484 case 0b01110: /* AUTIB1716 */
1485 if (s
->pauth_active
) {
1486 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1489 case 0b11000: /* PACIAZ */
1490 if (s
->pauth_active
) {
1491 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1492 new_tmp_a64_zero(s
));
1495 case 0b11001: /* PACIASP */
1496 if (s
->pauth_active
) {
1497 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1500 case 0b11010: /* PACIBZ */
1501 if (s
->pauth_active
) {
1502 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1503 new_tmp_a64_zero(s
));
1506 case 0b11011: /* PACIBSP */
1507 if (s
->pauth_active
) {
1508 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1511 case 0b11100: /* AUTIAZ */
1512 if (s
->pauth_active
) {
1513 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1514 new_tmp_a64_zero(s
));
1517 case 0b11101: /* AUTIASP */
1518 if (s
->pauth_active
) {
1519 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1522 case 0b11110: /* AUTIBZ */
1523 if (s
->pauth_active
) {
1524 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1525 new_tmp_a64_zero(s
));
1528 case 0b11111: /* AUTIBSP */
1529 if (s
->pauth_active
) {
1530 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1534 /* default specified as NOP equivalent */
1539 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1541 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1544 /* CLREX, DSB, DMB, ISB */
1545 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1546 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1551 unallocated_encoding(s
);
1562 case 1: /* MBReqTypes_Reads */
1563 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1565 case 2: /* MBReqTypes_Writes */
1566 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1568 default: /* MBReqTypes_All */
1569 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1575 /* We need to break the TB after this insn to execute
1576 * a self-modified code correctly and also to take
1577 * any pending interrupts immediately.
1580 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1584 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1585 goto do_unallocated
;
1588 * TODO: There is no speculation barrier opcode for TCG;
1589 * MB and end the TB instead.
1591 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1592 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1597 unallocated_encoding(s
);
1602 static void gen_xaflag(void)
1604 TCGv_i32 z
= tcg_temp_new_i32();
1606 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1615 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1616 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1619 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1620 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1622 /* (!C & Z) << 31 -> -(Z & ~C) */
1623 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1624 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1627 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1629 tcg_temp_free_i32(z
);
1632 static void gen_axflag(void)
1634 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1635 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1637 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1638 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1640 tcg_gen_movi_i32(cpu_NF
, 0);
1641 tcg_gen_movi_i32(cpu_VF
, 0);
1644 /* MSR (immediate) - move immediate to processor state field */
1645 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1646 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1649 int op
= op1
<< 3 | op2
;
1651 /* End the TB by default, chaining is ok. */
1652 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1655 case 0x00: /* CFINV */
1656 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1657 goto do_unallocated
;
1659 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1660 s
->base
.is_jmp
= DISAS_NEXT
;
1663 case 0x01: /* XAFlag */
1664 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1665 goto do_unallocated
;
1668 s
->base
.is_jmp
= DISAS_NEXT
;
1671 case 0x02: /* AXFlag */
1672 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1673 goto do_unallocated
;
1676 s
->base
.is_jmp
= DISAS_NEXT
;
1679 case 0x03: /* UAO */
1680 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1681 goto do_unallocated
;
1684 set_pstate_bits(PSTATE_UAO
);
1686 clear_pstate_bits(PSTATE_UAO
);
1688 t1
= tcg_const_i32(s
->current_el
);
1689 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1690 tcg_temp_free_i32(t1
);
1693 case 0x04: /* PAN */
1694 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1695 goto do_unallocated
;
1698 set_pstate_bits(PSTATE_PAN
);
1700 clear_pstate_bits(PSTATE_PAN
);
1702 t1
= tcg_const_i32(s
->current_el
);
1703 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1704 tcg_temp_free_i32(t1
);
1707 case 0x05: /* SPSel */
1708 if (s
->current_el
== 0) {
1709 goto do_unallocated
;
1711 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1712 gen_helper_msr_i_spsel(cpu_env
, t1
);
1713 tcg_temp_free_i32(t1
);
1716 case 0x19: /* SSBS */
1717 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1718 goto do_unallocated
;
1721 set_pstate_bits(PSTATE_SSBS
);
1723 clear_pstate_bits(PSTATE_SSBS
);
1725 /* Don't need to rebuild hflags since SSBS is a nop */
1728 case 0x1a: /* DIT */
1729 if (!dc_isar_feature(aa64_dit
, s
)) {
1730 goto do_unallocated
;
1733 set_pstate_bits(PSTATE_DIT
);
1735 clear_pstate_bits(PSTATE_DIT
);
1737 /* There's no need to rebuild hflags because DIT is a nop */
1740 case 0x1e: /* DAIFSet */
1741 t1
= tcg_const_i32(crm
);
1742 gen_helper_msr_i_daifset(cpu_env
, t1
);
1743 tcg_temp_free_i32(t1
);
1746 case 0x1f: /* DAIFClear */
1747 t1
= tcg_const_i32(crm
);
1748 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1749 tcg_temp_free_i32(t1
);
1750 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1751 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1754 case 0x1c: /* TCO */
1755 if (dc_isar_feature(aa64_mte
, s
)) {
1756 /* Full MTE is enabled -- set the TCO bit as directed. */
1758 set_pstate_bits(PSTATE_TCO
);
1760 clear_pstate_bits(PSTATE_TCO
);
1762 t1
= tcg_const_i32(s
->current_el
);
1763 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1764 tcg_temp_free_i32(t1
);
1765 /* Many factors, including TCO, go into MTE_ACTIVE. */
1766 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1767 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1768 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1769 s
->base
.is_jmp
= DISAS_NEXT
;
1771 goto do_unallocated
;
1777 unallocated_encoding(s
);
1782 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1784 TCGv_i32 tmp
= tcg_temp_new_i32();
1785 TCGv_i32 nzcv
= tcg_temp_new_i32();
1787 /* build bit 31, N */
1788 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1789 /* build bit 30, Z */
1790 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1791 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1792 /* build bit 29, C */
1793 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1794 /* build bit 28, V */
1795 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1796 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1797 /* generate result */
1798 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1800 tcg_temp_free_i32(nzcv
);
1801 tcg_temp_free_i32(tmp
);
1804 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1806 TCGv_i32 nzcv
= tcg_temp_new_i32();
1808 /* take NZCV from R[t] */
1809 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1812 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1814 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1815 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1817 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1818 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1820 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1821 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1822 tcg_temp_free_i32(nzcv
);
1825 /* MRS - move from system register
1826 * MSR (register) - move to system register
1829 * These are all essentially the same insn in 'read' and 'write'
1830 * versions, with varying op0 fields.
1832 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1833 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1834 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1836 const ARMCPRegInfo
*ri
;
1839 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1840 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1841 crn
, crm
, op0
, op1
, op2
));
1844 /* Unknown register; this might be a guest error or a QEMU
1845 * unimplemented feature.
1847 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1848 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1849 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1850 unallocated_encoding(s
);
1854 /* Check access permissions */
1855 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1856 unallocated_encoding(s
);
1861 /* Emit code to perform further access permissions checks at
1862 * runtime; this may result in an exception.
1865 TCGv_i32 tcg_syn
, tcg_isread
;
1868 gen_a64_set_pc_im(s
->pc_curr
);
1869 tmpptr
= tcg_const_ptr(ri
);
1870 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1871 tcg_syn
= tcg_const_i32(syndrome
);
1872 tcg_isread
= tcg_const_i32(isread
);
1873 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1874 tcg_temp_free_ptr(tmpptr
);
1875 tcg_temp_free_i32(tcg_syn
);
1876 tcg_temp_free_i32(tcg_isread
);
1877 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1879 * The readfn or writefn might raise an exception;
1880 * synchronize the CPU state in case it does.
1882 gen_a64_set_pc_im(s
->pc_curr
);
1885 /* Handle special cases first */
1886 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1890 tcg_rt
= cpu_reg(s
, rt
);
1892 gen_get_nzcv(tcg_rt
);
1894 gen_set_nzcv(tcg_rt
);
1897 case ARM_CP_CURRENTEL
:
1898 /* Reads as current EL value from pstate, which is
1899 * guaranteed to be constant by the tb flags.
1901 tcg_rt
= cpu_reg(s
, rt
);
1902 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1905 /* Writes clear the aligned block of memory which rt points into. */
1906 if (s
->mte_active
[0]) {
1910 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1911 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1912 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1913 t_desc
= tcg_const_i32(desc
);
1915 tcg_rt
= new_tmp_a64(s
);
1916 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1917 tcg_temp_free_i32(t_desc
);
1919 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1921 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1925 TCGv_i64 clean_addr
, tag
;
1928 * DC_GVA, like DC_ZVA, requires that we supply the original
1929 * pointer for an invalid page. Probe that address first.
1931 tcg_rt
= cpu_reg(s
, rt
);
1932 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1933 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1936 /* Extract the tag from the register to match STZGM. */
1937 tag
= tcg_temp_new_i64();
1938 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1939 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1940 tcg_temp_free_i64(tag
);
1944 case ARM_CP_DC_GZVA
:
1946 TCGv_i64 clean_addr
, tag
;
1948 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1949 tcg_rt
= cpu_reg(s
, rt
);
1950 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1951 gen_helper_dc_zva(cpu_env
, clean_addr
);
1954 /* Extract the tag from the register to match STZGM. */
1955 tag
= tcg_temp_new_i64();
1956 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1957 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1958 tcg_temp_free_i64(tag
);
1965 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1967 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1971 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1975 tcg_rt
= cpu_reg(s
, rt
);
1978 if (ri
->type
& ARM_CP_CONST
) {
1979 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1980 } else if (ri
->readfn
) {
1982 tmpptr
= tcg_const_ptr(ri
);
1983 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1984 tcg_temp_free_ptr(tmpptr
);
1986 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1989 if (ri
->type
& ARM_CP_CONST
) {
1990 /* If not forbidden by access permissions, treat as WI */
1992 } else if (ri
->writefn
) {
1994 tmpptr
= tcg_const_ptr(ri
);
1995 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1996 tcg_temp_free_ptr(tmpptr
);
1998 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2002 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
2003 /* I/O operations must end the TB here (whether read or write) */
2004 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2006 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
2008 * A write to any coprocessor regiser that ends a TB
2009 * must rebuild the hflags for the next TB.
2011 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
2012 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
2013 tcg_temp_free_i32(tcg_el
);
2015 * We default to ending the TB on a coprocessor register write,
2016 * but allow this to be suppressed by the register definition
2017 * (usually only necessary to work around guest bugs).
2019 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2024 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2025 * +---------------------+---+-----+-----+-------+-------+-----+------+
2026 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2027 * +---------------------+---+-----+-----+-------+-------+-----+------+
2029 static void disas_system(DisasContext
*s
, uint32_t insn
)
2031 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2032 l
= extract32(insn
, 21, 1);
2033 op0
= extract32(insn
, 19, 2);
2034 op1
= extract32(insn
, 16, 3);
2035 crn
= extract32(insn
, 12, 4);
2036 crm
= extract32(insn
, 8, 4);
2037 op2
= extract32(insn
, 5, 3);
2038 rt
= extract32(insn
, 0, 5);
2041 if (l
|| rt
!= 31) {
2042 unallocated_encoding(s
);
2046 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2047 handle_hint(s
, insn
, op1
, op2
, crm
);
2049 case 3: /* CLREX, DSB, DMB, ISB */
2050 handle_sync(s
, insn
, op1
, op2
, crm
);
2052 case 4: /* MSR (immediate) */
2053 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2056 unallocated_encoding(s
);
2061 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2064 /* Exception generation
2066 * 31 24 23 21 20 5 4 2 1 0
2067 * +-----------------+-----+------------------------+-----+----+
2068 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2069 * +-----------------------+------------------------+----------+
2071 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2073 int opc
= extract32(insn
, 21, 3);
2074 int op2_ll
= extract32(insn
, 0, 5);
2075 int imm16
= extract32(insn
, 5, 16);
2080 /* For SVC, HVC and SMC we advance the single-step state
2081 * machine before taking the exception. This is architecturally
2082 * mandated, to ensure that single-stepping a system call
2083 * instruction works properly.
2088 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2089 syn_aa64_svc(imm16
), default_exception_el(s
));
2092 if (s
->current_el
== 0) {
2093 unallocated_encoding(s
);
2096 /* The pre HVC helper handles cases when HVC gets trapped
2097 * as an undefined insn by runtime configuration.
2099 gen_a64_set_pc_im(s
->pc_curr
);
2100 gen_helper_pre_hvc(cpu_env
);
2102 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2103 syn_aa64_hvc(imm16
), 2);
2106 if (s
->current_el
== 0) {
2107 unallocated_encoding(s
);
2110 gen_a64_set_pc_im(s
->pc_curr
);
2111 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2112 gen_helper_pre_smc(cpu_env
, tmp
);
2113 tcg_temp_free_i32(tmp
);
2115 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2116 syn_aa64_smc(imm16
), 3);
2119 unallocated_encoding(s
);
2125 unallocated_encoding(s
);
2129 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2133 unallocated_encoding(s
);
2136 /* HLT. This has two purposes.
2137 * Architecturally, it is an external halting debug instruction.
2138 * Since QEMU doesn't implement external debug, we treat this as
2139 * it is required for halting debug disabled: it will UNDEF.
2140 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2142 if (semihosting_enabled() && imm16
== 0xf000) {
2143 #ifndef CONFIG_USER_ONLY
2144 /* In system mode, don't allow userspace access to semihosting,
2145 * to provide some semblance of security (and for consistency
2146 * with our 32-bit semihosting).
2148 if (s
->current_el
== 0) {
2149 unsupported_encoding(s
, insn
);
2153 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2155 unsupported_encoding(s
, insn
);
2159 if (op2_ll
< 1 || op2_ll
> 3) {
2160 unallocated_encoding(s
);
2163 /* DCPS1, DCPS2, DCPS3 */
2164 unsupported_encoding(s
, insn
);
2167 unallocated_encoding(s
);
2172 /* Unconditional branch (register)
2173 * 31 25 24 21 20 16 15 10 9 5 4 0
2174 * +---------------+-------+-------+-------+------+-------+
2175 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2176 * +---------------+-------+-------+-------+------+-------+
2178 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2180 unsigned int opc
, op2
, op3
, rn
, op4
;
2181 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2185 opc
= extract32(insn
, 21, 4);
2186 op2
= extract32(insn
, 16, 5);
2187 op3
= extract32(insn
, 10, 6);
2188 rn
= extract32(insn
, 5, 5);
2189 op4
= extract32(insn
, 0, 5);
2192 goto do_unallocated
;
2204 goto do_unallocated
;
2206 dst
= cpu_reg(s
, rn
);
2211 if (!dc_isar_feature(aa64_pauth
, s
)) {
2212 goto do_unallocated
;
2216 if (rn
!= 0x1f || op4
!= 0x1f) {
2217 goto do_unallocated
;
2220 modifier
= cpu_X
[31];
2222 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2224 goto do_unallocated
;
2226 modifier
= new_tmp_a64_zero(s
);
2228 if (s
->pauth_active
) {
2229 dst
= new_tmp_a64(s
);
2231 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2233 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2236 dst
= cpu_reg(s
, rn
);
2241 goto do_unallocated
;
2243 gen_a64_set_pc(s
, dst
);
2244 /* BLR also needs to load return address */
2246 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2252 if (!dc_isar_feature(aa64_pauth
, s
)) {
2253 goto do_unallocated
;
2255 if ((op3
& ~1) != 2) {
2256 goto do_unallocated
;
2258 btype_mod
= opc
& 1;
2259 if (s
->pauth_active
) {
2260 dst
= new_tmp_a64(s
);
2261 modifier
= cpu_reg_sp(s
, op4
);
2263 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2265 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2268 dst
= cpu_reg(s
, rn
);
2270 gen_a64_set_pc(s
, dst
);
2271 /* BLRAA also needs to load return address */
2273 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2278 if (s
->current_el
== 0) {
2279 goto do_unallocated
;
2284 goto do_unallocated
;
2286 dst
= tcg_temp_new_i64();
2287 tcg_gen_ld_i64(dst
, cpu_env
,
2288 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2291 case 2: /* ERETAA */
2292 case 3: /* ERETAB */
2293 if (!dc_isar_feature(aa64_pauth
, s
)) {
2294 goto do_unallocated
;
2296 if (rn
!= 0x1f || op4
!= 0x1f) {
2297 goto do_unallocated
;
2299 dst
= tcg_temp_new_i64();
2300 tcg_gen_ld_i64(dst
, cpu_env
,
2301 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2302 if (s
->pauth_active
) {
2303 modifier
= cpu_X
[31];
2305 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2307 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2313 goto do_unallocated
;
2315 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2319 gen_helper_exception_return(cpu_env
, dst
);
2320 tcg_temp_free_i64(dst
);
2321 /* Must exit loop to check un-masked IRQs */
2322 s
->base
.is_jmp
= DISAS_EXIT
;
2326 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2327 goto do_unallocated
;
2329 unsupported_encoding(s
, insn
);
2335 unallocated_encoding(s
);
2339 switch (btype_mod
) {
2341 if (dc_isar_feature(aa64_bti
, s
)) {
2342 /* BR to {x16,x17} or !guard -> 1, else 3. */
2343 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2348 if (dc_isar_feature(aa64_bti
, s
)) {
2349 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2354 default: /* RET or none of the above. */
2355 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2359 s
->base
.is_jmp
= DISAS_JUMP
;
2362 /* Branches, exception generating and system instructions */
2363 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2365 switch (extract32(insn
, 25, 7)) {
2366 case 0x0a: case 0x0b:
2367 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2368 disas_uncond_b_imm(s
, insn
);
2370 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2371 disas_comp_b_imm(s
, insn
);
2373 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2374 disas_test_b_imm(s
, insn
);
2376 case 0x2a: /* Conditional branch (immediate) */
2377 disas_cond_b_imm(s
, insn
);
2379 case 0x6a: /* Exception generation / System */
2380 if (insn
& (1 << 24)) {
2381 if (extract32(insn
, 22, 2) == 0) {
2382 disas_system(s
, insn
);
2384 unallocated_encoding(s
);
2390 case 0x6b: /* Unconditional branch (register) */
2391 disas_uncond_b_reg(s
, insn
);
2394 unallocated_encoding(s
);
2400 * Load/Store exclusive instructions are implemented by remembering
2401 * the value/address loaded, and seeing if these are the same
2402 * when the store is performed. This is not actually the architecturally
2403 * mandated semantics, but it works for typical guest code sequences
2404 * and avoids having to monitor regular stores.
2406 * The store exclusive uses the atomic cmpxchg primitives to avoid
2407 * races in multi-threaded linux-user and when MTTCG softmmu is
2410 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2411 TCGv_i64 addr
, int size
, bool is_pair
)
2413 int idx
= get_mem_index(s
);
2414 MemOp memop
= s
->be_data
;
2416 g_assert(size
<= 3);
2418 g_assert(size
>= 2);
2420 /* The pair must be single-copy atomic for the doubleword. */
2421 memop
|= MO_64
| MO_ALIGN
;
2422 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2423 if (s
->be_data
== MO_LE
) {
2424 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2425 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2427 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2428 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2431 /* The pair must be single-copy atomic for *each* doubleword, not
2432 the entire quadword, however it must be quadword aligned. */
2434 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2435 memop
| MO_ALIGN_16
);
2437 TCGv_i64 addr2
= tcg_temp_new_i64();
2438 tcg_gen_addi_i64(addr2
, addr
, 8);
2439 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2440 tcg_temp_free_i64(addr2
);
2442 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2443 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2446 memop
|= size
| MO_ALIGN
;
2447 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2448 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2450 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2453 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2454 TCGv_i64 addr
, int size
, int is_pair
)
2456 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2457 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2460 * [addr + datasize] = {Rt2};
2466 * env->exclusive_addr = -1;
2468 TCGLabel
*fail_label
= gen_new_label();
2469 TCGLabel
*done_label
= gen_new_label();
2472 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2474 tmp
= tcg_temp_new_i64();
2477 if (s
->be_data
== MO_LE
) {
2478 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2480 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2482 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2483 cpu_exclusive_val
, tmp
,
2485 MO_64
| MO_ALIGN
| s
->be_data
);
2486 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2487 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2488 if (!HAVE_CMPXCHG128
) {
2489 gen_helper_exit_atomic(cpu_env
);
2490 s
->base
.is_jmp
= DISAS_NORETURN
;
2491 } else if (s
->be_data
== MO_LE
) {
2492 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2497 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2502 } else if (s
->be_data
== MO_LE
) {
2503 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2504 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2506 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2507 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2510 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2511 cpu_reg(s
, rt
), get_mem_index(s
),
2512 size
| MO_ALIGN
| s
->be_data
);
2513 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2515 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2516 tcg_temp_free_i64(tmp
);
2517 tcg_gen_br(done_label
);
2519 gen_set_label(fail_label
);
2520 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2521 gen_set_label(done_label
);
2522 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2525 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2528 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2529 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2530 int memidx
= get_mem_index(s
);
2531 TCGv_i64 clean_addr
;
2534 gen_check_sp_alignment(s
);
2536 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2537 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2538 size
| MO_ALIGN
| s
->be_data
);
2541 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2544 TCGv_i64 s1
= cpu_reg(s
, rs
);
2545 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2546 TCGv_i64 t1
= cpu_reg(s
, rt
);
2547 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2548 TCGv_i64 clean_addr
;
2549 int memidx
= get_mem_index(s
);
2552 gen_check_sp_alignment(s
);
2555 /* This is a single atomic access, despite the "pair". */
2556 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2559 TCGv_i64 cmp
= tcg_temp_new_i64();
2560 TCGv_i64 val
= tcg_temp_new_i64();
2562 if (s
->be_data
== MO_LE
) {
2563 tcg_gen_concat32_i64(val
, t1
, t2
);
2564 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2566 tcg_gen_concat32_i64(val
, t2
, t1
);
2567 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2570 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2571 MO_64
| MO_ALIGN
| s
->be_data
);
2572 tcg_temp_free_i64(val
);
2574 if (s
->be_data
== MO_LE
) {
2575 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2577 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2579 tcg_temp_free_i64(cmp
);
2580 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2581 if (HAVE_CMPXCHG128
) {
2582 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2583 if (s
->be_data
== MO_LE
) {
2584 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2585 clean_addr
, t1
, t2
);
2587 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2588 clean_addr
, t1
, t2
);
2590 tcg_temp_free_i32(tcg_rs
);
2592 gen_helper_exit_atomic(cpu_env
);
2593 s
->base
.is_jmp
= DISAS_NORETURN
;
2596 TCGv_i64 d1
= tcg_temp_new_i64();
2597 TCGv_i64 d2
= tcg_temp_new_i64();
2598 TCGv_i64 a2
= tcg_temp_new_i64();
2599 TCGv_i64 c1
= tcg_temp_new_i64();
2600 TCGv_i64 c2
= tcg_temp_new_i64();
2601 TCGv_i64 zero
= tcg_const_i64(0);
2603 /* Load the two words, in memory order. */
2604 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2605 MO_64
| MO_ALIGN_16
| s
->be_data
);
2606 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2607 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2609 /* Compare the two words, also in memory order. */
2610 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2611 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2612 tcg_gen_and_i64(c2
, c2
, c1
);
2614 /* If compare equal, write back new data, else write back old data. */
2615 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2616 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2617 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2618 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2619 tcg_temp_free_i64(a2
);
2620 tcg_temp_free_i64(c1
);
2621 tcg_temp_free_i64(c2
);
2622 tcg_temp_free_i64(zero
);
2624 /* Write back the data from memory to Rs. */
2625 tcg_gen_mov_i64(s1
, d1
);
2626 tcg_gen_mov_i64(s2
, d2
);
2627 tcg_temp_free_i64(d1
);
2628 tcg_temp_free_i64(d2
);
2632 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2633 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2635 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2637 int opc0
= extract32(opc
, 0, 1);
2641 regsize
= opc0
? 32 : 64;
2643 regsize
= size
== 3 ? 64 : 32;
2645 return regsize
== 64;
2648 /* Load/store exclusive
2650 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2651 * +-----+-------------+----+---+----+------+----+-------+------+------+
2652 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2653 * +-----+-------------+----+---+----+------+----+-------+------+------+
2655 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2656 * L: 0 -> store, 1 -> load
2657 * o2: 0 -> exclusive, 1 -> not
2658 * o1: 0 -> single register, 1 -> register pair
2659 * o0: 1 -> load-acquire/store-release, 0 -> not
2661 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2663 int rt
= extract32(insn
, 0, 5);
2664 int rn
= extract32(insn
, 5, 5);
2665 int rt2
= extract32(insn
, 10, 5);
2666 int rs
= extract32(insn
, 16, 5);
2667 int is_lasr
= extract32(insn
, 15, 1);
2668 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2669 int size
= extract32(insn
, 30, 2);
2670 TCGv_i64 clean_addr
;
2672 switch (o2_L_o1_o0
) {
2673 case 0x0: /* STXR */
2674 case 0x1: /* STLXR */
2676 gen_check_sp_alignment(s
);
2679 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2681 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2682 true, rn
!= 31, size
);
2683 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2686 case 0x4: /* LDXR */
2687 case 0x5: /* LDAXR */
2689 gen_check_sp_alignment(s
);
2691 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2692 false, rn
!= 31, size
);
2694 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2696 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2700 case 0x8: /* STLLR */
2701 if (!dc_isar_feature(aa64_lor
, s
)) {
2704 /* StoreLORelease is the same as Store-Release for QEMU. */
2706 case 0x9: /* STLR */
2707 /* Generate ISS for non-exclusive accesses including LASR. */
2709 gen_check_sp_alignment(s
);
2711 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2712 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2713 true, rn
!= 31, size
);
2714 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2715 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2716 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2719 case 0xc: /* LDLAR */
2720 if (!dc_isar_feature(aa64_lor
, s
)) {
2723 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2725 case 0xd: /* LDAR */
2726 /* Generate ISS for non-exclusive accesses including LASR. */
2728 gen_check_sp_alignment(s
);
2730 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2731 false, rn
!= 31, size
);
2732 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2733 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2734 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2735 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2738 case 0x2: case 0x3: /* CASP / STXP */
2739 if (size
& 2) { /* STXP / STLXP */
2741 gen_check_sp_alignment(s
);
2744 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2746 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2747 true, rn
!= 31, size
);
2748 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2752 && ((rt
| rs
) & 1) == 0
2753 && dc_isar_feature(aa64_atomics
, s
)) {
2755 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2760 case 0x6: case 0x7: /* CASPA / LDXP */
2761 if (size
& 2) { /* LDXP / LDAXP */
2763 gen_check_sp_alignment(s
);
2765 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2766 false, rn
!= 31, size
);
2768 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2770 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2775 && ((rt
| rs
) & 1) == 0
2776 && dc_isar_feature(aa64_atomics
, s
)) {
2777 /* CASPA / CASPAL */
2778 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2784 case 0xb: /* CASL */
2785 case 0xe: /* CASA */
2786 case 0xf: /* CASAL */
2787 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2788 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2793 unallocated_encoding(s
);
2797 * Load register (literal)
2799 * 31 30 29 27 26 25 24 23 5 4 0
2800 * +-----+-------+---+-----+-------------------+-------+
2801 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2802 * +-----+-------+---+-----+-------------------+-------+
2804 * V: 1 -> vector (simd/fp)
2805 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2806 * 10-> 32 bit signed, 11 -> prefetch
2807 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2809 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2811 int rt
= extract32(insn
, 0, 5);
2812 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2813 bool is_vector
= extract32(insn
, 26, 1);
2814 int opc
= extract32(insn
, 30, 2);
2815 bool is_signed
= false;
2817 TCGv_i64 tcg_rt
, clean_addr
;
2821 unallocated_encoding(s
);
2825 if (!fp_access_check(s
)) {
2830 /* PRFM (literal) : prefetch */
2833 size
= 2 + extract32(opc
, 0, 1);
2834 is_signed
= extract32(opc
, 1, 1);
2837 tcg_rt
= cpu_reg(s
, rt
);
2839 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2841 do_fp_ld(s
, rt
, clean_addr
, size
);
2843 /* Only unsigned 32bit loads target 32bit registers. */
2844 bool iss_sf
= opc
!= 0;
2846 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2847 false, true, rt
, iss_sf
, false);
2849 tcg_temp_free_i64(clean_addr
);
2853 * LDNP (Load Pair - non-temporal hint)
2854 * LDP (Load Pair - non vector)
2855 * LDPSW (Load Pair Signed Word - non vector)
2856 * STNP (Store Pair - non-temporal hint)
2857 * STP (Store Pair - non vector)
2858 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2859 * LDP (Load Pair of SIMD&FP)
2860 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2861 * STP (Store Pair of SIMD&FP)
2863 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2864 * +-----+-------+---+---+-------+---+-----------------------------+
2865 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2866 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2868 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2870 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2871 * V: 0 -> GPR, 1 -> Vector
2872 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2873 * 10 -> signed offset, 11 -> pre-index
2874 * L: 0 -> Store 1 -> Load
2876 * Rt, Rt2 = GPR or SIMD registers to be stored
2877 * Rn = general purpose register containing address
2878 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2880 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2882 int rt
= extract32(insn
, 0, 5);
2883 int rn
= extract32(insn
, 5, 5);
2884 int rt2
= extract32(insn
, 10, 5);
2885 uint64_t offset
= sextract64(insn
, 15, 7);
2886 int index
= extract32(insn
, 23, 2);
2887 bool is_vector
= extract32(insn
, 26, 1);
2888 bool is_load
= extract32(insn
, 22, 1);
2889 int opc
= extract32(insn
, 30, 2);
2891 bool is_signed
= false;
2892 bool postindex
= false;
2894 bool set_tag
= false;
2896 TCGv_i64 clean_addr
, dirty_addr
;
2901 unallocated_encoding(s
);
2907 } else if (opc
== 1 && !is_load
) {
2909 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2910 unallocated_encoding(s
);
2916 size
= 2 + extract32(opc
, 1, 1);
2917 is_signed
= extract32(opc
, 0, 1);
2918 if (!is_load
&& is_signed
) {
2919 unallocated_encoding(s
);
2925 case 1: /* post-index */
2930 /* signed offset with "non-temporal" hint. Since we don't emulate
2931 * caches we don't care about hints to the cache system about
2932 * data access patterns, and handle this identically to plain
2936 /* There is no non-temporal-hint version of LDPSW */
2937 unallocated_encoding(s
);
2942 case 2: /* signed offset, rn not updated */
2945 case 3: /* pre-index */
2951 if (is_vector
&& !fp_access_check(s
)) {
2955 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2958 gen_check_sp_alignment(s
);
2961 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2963 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2969 * TODO: We could rely on the stores below, at least for
2970 * system mode, if we arrange to add MO_ALIGN_16.
2972 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2973 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2974 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2976 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2980 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2981 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
2985 do_fp_ld(s
, rt
, clean_addr
, size
);
2987 do_fp_st(s
, rt
, clean_addr
, size
);
2989 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2991 do_fp_ld(s
, rt2
, clean_addr
, size
);
2993 do_fp_st(s
, rt2
, clean_addr
, size
);
2996 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2997 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
3000 TCGv_i64 tmp
= tcg_temp_new_i64();
3002 /* Do not modify tcg_rt before recognizing any exception
3003 * from the second load.
3005 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3006 false, false, 0, false, false);
3007 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3008 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3009 false, false, 0, false, false);
3011 tcg_gen_mov_i64(tcg_rt
, tmp
);
3012 tcg_temp_free_i64(tmp
);
3014 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3015 false, 0, false, false);
3016 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3017 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3018 false, 0, false, false);
3024 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3026 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3031 * Load/store (immediate post-indexed)
3032 * Load/store (immediate pre-indexed)
3033 * Load/store (unscaled immediate)
3035 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3036 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3037 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3038 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3040 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3042 * V = 0 -> non-vector
3043 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3044 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3046 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3052 int rn
= extract32(insn
, 5, 5);
3053 int imm9
= sextract32(insn
, 12, 9);
3054 int idx
= extract32(insn
, 10, 2);
3055 bool is_signed
= false;
3056 bool is_store
= false;
3057 bool is_extended
= false;
3058 bool is_unpriv
= (idx
== 2);
3059 bool iss_valid
= !is_vector
;
3064 TCGv_i64 clean_addr
, dirty_addr
;
3067 size
|= (opc
& 2) << 1;
3068 if (size
> 4 || is_unpriv
) {
3069 unallocated_encoding(s
);
3072 is_store
= ((opc
& 1) == 0);
3073 if (!fp_access_check(s
)) {
3077 if (size
== 3 && opc
== 2) {
3078 /* PRFM - prefetch */
3080 unallocated_encoding(s
);
3085 if (opc
== 3 && size
> 1) {
3086 unallocated_encoding(s
);
3089 is_store
= (opc
== 0);
3090 is_signed
= extract32(opc
, 1, 1);
3091 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3109 g_assert_not_reached();
3113 gen_check_sp_alignment(s
);
3116 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3118 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3121 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3122 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3123 writeback
|| rn
!= 31,
3124 size
, is_unpriv
, memidx
);
3128 do_fp_st(s
, rt
, clean_addr
, size
);
3130 do_fp_ld(s
, rt
, clean_addr
, size
);
3133 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3134 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3137 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3138 iss_valid
, rt
, iss_sf
, false);
3140 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3141 is_extended
, memidx
,
3142 iss_valid
, rt
, iss_sf
, false);
3147 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3149 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3151 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3156 * Load/store (register offset)
3158 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3159 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3160 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3161 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3164 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3165 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3167 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3168 * opc<0>: 0 -> store, 1 -> load
3169 * V: 1 -> vector/simd
3170 * opt: extend encoding (see DecodeRegExtend)
3171 * S: if S=1 then scale (essentially index by sizeof(size))
3172 * Rt: register to transfer into/out of
3173 * Rn: address register or SP for base
3174 * Rm: offset register or ZR for offset
3176 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3182 int rn
= extract32(insn
, 5, 5);
3183 int shift
= extract32(insn
, 12, 1);
3184 int rm
= extract32(insn
, 16, 5);
3185 int opt
= extract32(insn
, 13, 3);
3186 bool is_signed
= false;
3187 bool is_store
= false;
3188 bool is_extended
= false;
3190 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3192 if (extract32(opt
, 1, 1) == 0) {
3193 unallocated_encoding(s
);
3198 size
|= (opc
& 2) << 1;
3200 unallocated_encoding(s
);
3203 is_store
= !extract32(opc
, 0, 1);
3204 if (!fp_access_check(s
)) {
3208 if (size
== 3 && opc
== 2) {
3209 /* PRFM - prefetch */
3212 if (opc
== 3 && size
> 1) {
3213 unallocated_encoding(s
);
3216 is_store
= (opc
== 0);
3217 is_signed
= extract32(opc
, 1, 1);
3218 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3222 gen_check_sp_alignment(s
);
3224 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3226 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3227 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3229 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3230 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3234 do_fp_st(s
, rt
, clean_addr
, size
);
3236 do_fp_ld(s
, rt
, clean_addr
, size
);
3239 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3240 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3242 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3243 true, rt
, iss_sf
, false);
3245 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3246 is_extended
, true, rt
, iss_sf
, false);
3252 * Load/store (unsigned immediate)
3254 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3255 * +----+-------+---+-----+-----+------------+-------+------+
3256 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3257 * +----+-------+---+-----+-----+------------+-------+------+
3260 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3261 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3263 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3264 * opc<0>: 0 -> store, 1 -> load
3265 * Rn: base address register (inc SP)
3266 * Rt: target register
3268 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3274 int rn
= extract32(insn
, 5, 5);
3275 unsigned int imm12
= extract32(insn
, 10, 12);
3276 unsigned int offset
;
3278 TCGv_i64 clean_addr
, dirty_addr
;
3281 bool is_signed
= false;
3282 bool is_extended
= false;
3285 size
|= (opc
& 2) << 1;
3287 unallocated_encoding(s
);
3290 is_store
= !extract32(opc
, 0, 1);
3291 if (!fp_access_check(s
)) {
3295 if (size
== 3 && opc
== 2) {
3296 /* PRFM - prefetch */
3299 if (opc
== 3 && size
> 1) {
3300 unallocated_encoding(s
);
3303 is_store
= (opc
== 0);
3304 is_signed
= extract32(opc
, 1, 1);
3305 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3309 gen_check_sp_alignment(s
);
3311 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3312 offset
= imm12
<< size
;
3313 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3314 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3318 do_fp_st(s
, rt
, clean_addr
, size
);
3320 do_fp_ld(s
, rt
, clean_addr
, size
);
3323 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3324 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3326 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3327 true, rt
, iss_sf
, false);
3329 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3330 is_extended
, true, rt
, iss_sf
, false);
3335 /* Atomic memory operations
3337 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3338 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3339 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3340 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3342 * Rt: the result register
3343 * Rn: base address or SP
3344 * Rs: the source register for the operation
3345 * V: vector flag (always 0 as of v8.3)
3349 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3350 int size
, int rt
, bool is_vector
)
3352 int rs
= extract32(insn
, 16, 5);
3353 int rn
= extract32(insn
, 5, 5);
3354 int o3_opc
= extract32(insn
, 12, 4);
3355 bool r
= extract32(insn
, 22, 1);
3356 bool a
= extract32(insn
, 23, 1);
3357 TCGv_i64 tcg_rs
, tcg_rt
, clean_addr
;
3358 AtomicThreeOpFn
*fn
= NULL
;
3359 MemOp mop
= s
->be_data
| size
| MO_ALIGN
;
3361 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3362 unallocated_encoding(s
);
3366 case 000: /* LDADD */
3367 fn
= tcg_gen_atomic_fetch_add_i64
;
3369 case 001: /* LDCLR */
3370 fn
= tcg_gen_atomic_fetch_and_i64
;
3372 case 002: /* LDEOR */
3373 fn
= tcg_gen_atomic_fetch_xor_i64
;
3375 case 003: /* LDSET */
3376 fn
= tcg_gen_atomic_fetch_or_i64
;
3378 case 004: /* LDSMAX */
3379 fn
= tcg_gen_atomic_fetch_smax_i64
;
3382 case 005: /* LDSMIN */
3383 fn
= tcg_gen_atomic_fetch_smin_i64
;
3386 case 006: /* LDUMAX */
3387 fn
= tcg_gen_atomic_fetch_umax_i64
;
3389 case 007: /* LDUMIN */
3390 fn
= tcg_gen_atomic_fetch_umin_i64
;
3393 fn
= tcg_gen_atomic_xchg_i64
;
3395 case 014: /* LDAPR, LDAPRH, LDAPRB */
3396 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3397 rs
!= 31 || a
!= 1 || r
!= 0) {
3398 unallocated_encoding(s
);
3403 unallocated_encoding(s
);
3408 gen_check_sp_alignment(s
);
3410 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3412 if (o3_opc
== 014) {
3414 * LDAPR* are a special case because they are a simple load, not a
3415 * fetch-and-do-something op.
3416 * The architectural consistency requirements here are weaker than
3417 * full load-acquire (we only need "load-acquire processor consistent"),
3418 * but we choose to implement them as full LDAQ.
3420 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3421 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3422 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3426 tcg_rs
= read_cpu_reg(s
, rs
, true);
3427 tcg_rt
= cpu_reg(s
, rt
);
3429 if (o3_opc
== 1) { /* LDCLR */
3430 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3433 /* The tcg atomic primitives are all full barriers. Therefore we
3434 * can ignore the Acquire and Release bits of this instruction.
3436 fn(tcg_rt
, clean_addr
, tcg_rs
, get_mem_index(s
), mop
);
3438 if ((mop
& MO_SIGN
) && size
!= MO_64
) {
3439 tcg_gen_ext32u_i64(tcg_rt
, tcg_rt
);
3444 * PAC memory operations
3446 * 31 30 27 26 24 22 21 12 11 10 5 0
3447 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3448 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3449 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3451 * Rt: the result register
3452 * Rn: base address or SP
3453 * V: vector flag (always 0 as of v8.3)
3454 * M: clear for key DA, set for key DB
3455 * W: pre-indexing flag
3458 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3459 int size
, int rt
, bool is_vector
)
3461 int rn
= extract32(insn
, 5, 5);
3462 bool is_wback
= extract32(insn
, 11, 1);
3463 bool use_key_a
= !extract32(insn
, 23, 1);
3465 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3467 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3468 unallocated_encoding(s
);
3473 gen_check_sp_alignment(s
);
3475 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3477 if (s
->pauth_active
) {
3479 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3480 new_tmp_a64_zero(s
));
3482 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3483 new_tmp_a64_zero(s
));
3487 /* Form the 10-bit signed, scaled offset. */
3488 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3489 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3490 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3492 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3493 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3494 is_wback
|| rn
!= 31, size
);
3496 tcg_rt
= cpu_reg(s
, rt
);
3497 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3498 /* extend */ false, /* iss_valid */ !is_wback
,
3499 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3502 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3507 * LDAPR/STLR (unscaled immediate)
3509 * 31 30 24 22 21 12 10 5 0
3510 * +------+-------------+-----+---+--------+-----+----+-----+
3511 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3512 * +------+-------------+-----+---+--------+-----+----+-----+
3514 * Rt: source or destination register
3516 * imm9: unscaled immediate offset
3517 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3518 * size: size of load/store
3520 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3522 int rt
= extract32(insn
, 0, 5);
3523 int rn
= extract32(insn
, 5, 5);
3524 int offset
= sextract32(insn
, 12, 9);
3525 int opc
= extract32(insn
, 22, 2);
3526 int size
= extract32(insn
, 30, 2);
3527 TCGv_i64 clean_addr
, dirty_addr
;
3528 bool is_store
= false;
3529 bool extend
= false;
3533 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3534 unallocated_encoding(s
);
3538 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3539 mop
= size
| MO_ALIGN
;
3542 case 0: /* STLURB */
3545 case 1: /* LDAPUR* */
3547 case 2: /* LDAPURS* 64-bit variant */
3549 unallocated_encoding(s
);
3554 case 3: /* LDAPURS* 32-bit variant */
3556 unallocated_encoding(s
);
3560 extend
= true; /* zero-extend 32->64 after signed load */
3563 g_assert_not_reached();
3566 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3569 gen_check_sp_alignment(s
);
3572 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3573 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3574 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3577 /* Store-Release semantics */
3578 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3579 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3582 * Load-AcquirePC semantics; we implement as the slightly more
3583 * restrictive Load-Acquire.
3585 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3586 extend
, true, rt
, iss_sf
, true);
3587 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3591 /* Load/store register (all forms) */
3592 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3594 int rt
= extract32(insn
, 0, 5);
3595 int opc
= extract32(insn
, 22, 2);
3596 bool is_vector
= extract32(insn
, 26, 1);
3597 int size
= extract32(insn
, 30, 2);
3599 switch (extract32(insn
, 24, 2)) {
3601 if (extract32(insn
, 21, 1) == 0) {
3602 /* Load/store register (unscaled immediate)
3603 * Load/store immediate pre/post-indexed
3604 * Load/store register unprivileged
3606 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3609 switch (extract32(insn
, 10, 2)) {
3611 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3614 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3617 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3622 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3625 unallocated_encoding(s
);
3628 /* AdvSIMD load/store multiple structures
3630 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3631 * +---+---+---------------+---+-------------+--------+------+------+------+
3632 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3633 * +---+---+---------------+---+-------------+--------+------+------+------+
3635 * AdvSIMD load/store multiple structures (post-indexed)
3637 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3638 * +---+---+---------------+---+---+---------+--------+------+------+------+
3639 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3640 * +---+---+---------------+---+---+---------+--------+------+------+------+
3642 * Rt: first (or only) SIMD&FP register to be transferred
3643 * Rn: base address or SP
3644 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3646 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3648 int rt
= extract32(insn
, 0, 5);
3649 int rn
= extract32(insn
, 5, 5);
3650 int rm
= extract32(insn
, 16, 5);
3651 int size
= extract32(insn
, 10, 2);
3652 int opcode
= extract32(insn
, 12, 4);
3653 bool is_store
= !extract32(insn
, 22, 1);
3654 bool is_postidx
= extract32(insn
, 23, 1);
3655 bool is_q
= extract32(insn
, 30, 1);
3656 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3657 MemOp endian
, align
, mop
;
3659 int total
; /* total bytes */
3660 int elements
; /* elements per vector */
3661 int rpt
; /* num iterations */
3662 int selem
; /* structure elements */
3665 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3666 unallocated_encoding(s
);
3670 if (!is_postidx
&& rm
!= 0) {
3671 unallocated_encoding(s
);
3675 /* From the shared decode logic */
3706 unallocated_encoding(s
);
3710 if (size
== 3 && !is_q
&& selem
!= 1) {
3712 unallocated_encoding(s
);
3716 if (!fp_access_check(s
)) {
3721 gen_check_sp_alignment(s
);
3724 /* For our purposes, bytes are always little-endian. */
3725 endian
= s
->be_data
;
3730 total
= rpt
* selem
* (is_q
? 16 : 8);
3731 tcg_rn
= cpu_reg_sp(s
, rn
);
3734 * Issue the MTE check vs the logical repeat count, before we
3735 * promote consecutive little-endian elements below.
3737 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3741 * Consecutive little-endian elements from a single register
3742 * can be promoted to a larger little-endian operation.
3745 if (selem
== 1 && endian
== MO_LE
) {
3746 align
= pow2_align(size
);
3749 if (!s
->align_mem
) {
3752 mop
= endian
| size
| align
;
3754 elements
= (is_q
? 16 : 8) >> size
;
3755 tcg_ebytes
= tcg_const_i64(1 << size
);
3756 for (r
= 0; r
< rpt
; r
++) {
3758 for (e
= 0; e
< elements
; e
++) {
3760 for (xs
= 0; xs
< selem
; xs
++) {
3761 int tt
= (rt
+ r
+ xs
) % 32;
3763 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3765 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3767 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3771 tcg_temp_free_i64(tcg_ebytes
);
3774 /* For non-quad operations, setting a slice of the low
3775 * 64 bits of the register clears the high 64 bits (in
3776 * the ARM ARM pseudocode this is implicit in the fact
3777 * that 'rval' is a 64 bit wide variable).
3778 * For quad operations, we might still need to zero the
3781 for (r
= 0; r
< rpt
* selem
; r
++) {
3782 int tt
= (rt
+ r
) % 32;
3783 clear_vec_high(s
, is_q
, tt
);
3789 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3791 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3796 /* AdvSIMD load/store single structure
3798 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3799 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3800 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3801 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3803 * AdvSIMD load/store single structure (post-indexed)
3805 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3806 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3807 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3808 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3810 * Rt: first (or only) SIMD&FP register to be transferred
3811 * Rn: base address or SP
3812 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3813 * index = encoded in Q:S:size dependent on size
3815 * lane_size = encoded in R, opc
3816 * transfer width = encoded in opc, S, size
3818 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3820 int rt
= extract32(insn
, 0, 5);
3821 int rn
= extract32(insn
, 5, 5);
3822 int rm
= extract32(insn
, 16, 5);
3823 int size
= extract32(insn
, 10, 2);
3824 int S
= extract32(insn
, 12, 1);
3825 int opc
= extract32(insn
, 13, 3);
3826 int R
= extract32(insn
, 21, 1);
3827 int is_load
= extract32(insn
, 22, 1);
3828 int is_postidx
= extract32(insn
, 23, 1);
3829 int is_q
= extract32(insn
, 30, 1);
3831 int scale
= extract32(opc
, 1, 2);
3832 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3833 bool replicate
= false;
3834 int index
= is_q
<< 3 | S
<< 2 | size
;
3836 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3839 if (extract32(insn
, 31, 1)) {
3840 unallocated_encoding(s
);
3843 if (!is_postidx
&& rm
!= 0) {
3844 unallocated_encoding(s
);
3850 if (!is_load
|| S
) {
3851 unallocated_encoding(s
);
3860 if (extract32(size
, 0, 1)) {
3861 unallocated_encoding(s
);
3867 if (extract32(size
, 1, 1)) {
3868 unallocated_encoding(s
);
3871 if (!extract32(size
, 0, 1)) {
3875 unallocated_encoding(s
);
3883 g_assert_not_reached();
3886 if (!fp_access_check(s
)) {
3891 gen_check_sp_alignment(s
);
3894 total
= selem
<< scale
;
3895 tcg_rn
= cpu_reg_sp(s
, rn
);
3897 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3899 mop
= finalize_memop(s
, scale
);
3901 tcg_ebytes
= tcg_const_i64(1 << scale
);
3902 for (xs
= 0; xs
< selem
; xs
++) {
3904 /* Load and replicate to all elements */
3905 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3907 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3908 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3909 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3911 tcg_temp_free_i64(tcg_tmp
);
3913 /* Load/store one element per register */
3915 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3917 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3920 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3923 tcg_temp_free_i64(tcg_ebytes
);
3927 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3929 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3935 * Load/Store memory tags
3937 * 31 30 29 24 22 21 12 10 5 0
3938 * +-----+-------------+-----+---+------+-----+------+------+
3939 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3940 * +-----+-------------+-----+---+------+-----+------+------+
3942 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3944 int rt
= extract32(insn
, 0, 5);
3945 int rn
= extract32(insn
, 5, 5);
3946 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3947 int op2
= extract32(insn
, 10, 2);
3948 int op1
= extract32(insn
, 22, 2);
3949 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3951 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3953 /* We checked insn bits [29:24,21] in the caller. */
3954 if (extract32(insn
, 30, 2) != 3) {
3955 goto do_unallocated
;
3959 * @index is a tri-state variable which has 3 states:
3960 * < 0 : post-index, writeback
3961 * = 0 : signed offset
3962 * > 0 : pre-index, writeback
3971 if (s
->current_el
== 0 || offset
!= 0) {
3972 goto do_unallocated
;
3974 is_mult
= is_zero
= true;
3994 if (s
->current_el
== 0 || offset
!= 0) {
3995 goto do_unallocated
;
4003 is_pair
= is_zero
= true;
4007 if (s
->current_el
== 0 || offset
!= 0) {
4008 goto do_unallocated
;
4010 is_mult
= is_load
= true;
4016 unallocated_encoding(s
);
4021 ? !dc_isar_feature(aa64_mte
, s
)
4022 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4023 goto do_unallocated
;
4027 gen_check_sp_alignment(s
);
4030 addr
= read_cpu_reg_sp(s
, rn
, true);
4032 /* pre-index or signed offset */
4033 tcg_gen_addi_i64(addr
, addr
, offset
);
4037 tcg_rt
= cpu_reg(s
, rt
);
4040 int size
= 4 << s
->dcz_blocksize
;
4043 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4046 * The non-tags portion of STZGM is mostly like DC_ZVA,
4047 * except the alignment happens before the access.
4049 clean_addr
= clean_data_tbi(s
, addr
);
4050 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4051 gen_helper_dc_zva(cpu_env
, clean_addr
);
4052 } else if (s
->ata
) {
4054 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4056 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4059 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4060 int size
= 4 << GMID_EL1_BS
;
4062 clean_addr
= clean_data_tbi(s
, addr
);
4063 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4064 gen_probe_access(s
, clean_addr
, acc
, size
);
4067 /* The result tags are zeros. */
4068 tcg_gen_movi_i64(tcg_rt
, 0);
4075 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4076 tcg_rt
= cpu_reg(s
, rt
);
4078 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4080 clean_addr
= clean_data_tbi(s
, addr
);
4081 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4082 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4085 tcg_rt
= cpu_reg_sp(s
, rt
);
4088 * For STG and ST2G, we need to check alignment and probe memory.
4089 * TODO: For STZG and STZ2G, we could rely on the stores below,
4090 * at least for system mode; user-only won't enforce alignment.
4093 gen_helper_st2g_stub(cpu_env
, addr
);
4095 gen_helper_stg_stub(cpu_env
, addr
);
4097 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4099 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4101 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4105 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4107 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4113 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4114 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4115 int mem_index
= get_mem_index(s
);
4116 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4118 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4119 MO_Q
| MO_ALIGN_16
);
4120 for (i
= 8; i
< n
; i
+= 8) {
4121 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4122 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4124 tcg_temp_free_i64(tcg_zero
);
4128 /* pre-index or post-index */
4131 tcg_gen_addi_i64(addr
, addr
, offset
);
4133 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4137 /* Loads and stores */
4138 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4140 switch (extract32(insn
, 24, 6)) {
4141 case 0x08: /* Load/store exclusive */
4142 disas_ldst_excl(s
, insn
);
4144 case 0x18: case 0x1c: /* Load register (literal) */
4145 disas_ld_lit(s
, insn
);
4147 case 0x28: case 0x29:
4148 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4149 disas_ldst_pair(s
, insn
);
4151 case 0x38: case 0x39:
4152 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4153 disas_ldst_reg(s
, insn
);
4155 case 0x0c: /* AdvSIMD load/store multiple structures */
4156 disas_ldst_multiple_struct(s
, insn
);
4158 case 0x0d: /* AdvSIMD load/store single structure */
4159 disas_ldst_single_struct(s
, insn
);
4162 if (extract32(insn
, 21, 1) != 0) {
4163 disas_ldst_tag(s
, insn
);
4164 } else if (extract32(insn
, 10, 2) == 0) {
4165 disas_ldst_ldapr_stlr(s
, insn
);
4167 unallocated_encoding(s
);
4171 unallocated_encoding(s
);
4176 /* PC-rel. addressing
4177 * 31 30 29 28 24 23 5 4 0
4178 * +----+-------+-----------+-------------------+------+
4179 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4180 * +----+-------+-----------+-------------------+------+
4182 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4184 unsigned int page
, rd
;
4188 page
= extract32(insn
, 31, 1);
4189 /* SignExtend(immhi:immlo) -> offset */
4190 offset
= sextract64(insn
, 5, 19);
4191 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4192 rd
= extract32(insn
, 0, 5);
4196 /* ADRP (page based) */
4201 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4205 * Add/subtract (immediate)
4207 * 31 30 29 28 23 22 21 10 9 5 4 0
4208 * +--+--+--+-------------+--+-------------+-----+-----+
4209 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4210 * +--+--+--+-------------+--+-------------+-----+-----+
4212 * sf: 0 -> 32bit, 1 -> 64bit
4213 * op: 0 -> add , 1 -> sub
4215 * sh: 1 -> LSL imm by 12
4217 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4219 int rd
= extract32(insn
, 0, 5);
4220 int rn
= extract32(insn
, 5, 5);
4221 uint64_t imm
= extract32(insn
, 10, 12);
4222 bool shift
= extract32(insn
, 22, 1);
4223 bool setflags
= extract32(insn
, 29, 1);
4224 bool sub_op
= extract32(insn
, 30, 1);
4225 bool is_64bit
= extract32(insn
, 31, 1);
4227 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4228 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4229 TCGv_i64 tcg_result
;
4235 tcg_result
= tcg_temp_new_i64();
4238 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4240 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4243 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4245 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4247 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4249 tcg_temp_free_i64(tcg_imm
);
4253 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4255 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4258 tcg_temp_free_i64(tcg_result
);
4262 * Add/subtract (immediate, with tags)
4264 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4265 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4266 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4267 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4269 * op: 0 -> add, 1 -> sub
4271 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4273 int rd
= extract32(insn
, 0, 5);
4274 int rn
= extract32(insn
, 5, 5);
4275 int uimm4
= extract32(insn
, 10, 4);
4276 int uimm6
= extract32(insn
, 16, 6);
4277 bool sub_op
= extract32(insn
, 30, 1);
4278 TCGv_i64 tcg_rn
, tcg_rd
;
4281 /* Test all of sf=1, S=0, o2=0, o3=0. */
4282 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4283 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4284 unallocated_encoding(s
);
4288 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4293 tcg_rn
= cpu_reg_sp(s
, rn
);
4294 tcg_rd
= cpu_reg_sp(s
, rd
);
4297 TCGv_i32 offset
= tcg_const_i32(imm
);
4298 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4300 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4301 tcg_temp_free_i32(tag_offset
);
4302 tcg_temp_free_i32(offset
);
4304 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4305 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4309 /* The input should be a value in the bottom e bits (with higher
4310 * bits zero); returns that value replicated into every element
4311 * of size e in a 64 bit integer.
4313 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4323 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4324 static inline uint64_t bitmask64(unsigned int length
)
4326 assert(length
> 0 && length
<= 64);
4327 return ~0ULL >> (64 - length
);
4330 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4331 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4332 * value (ie should cause a guest UNDEF exception), and true if they are
4333 * valid, in which case the decoded bit pattern is written to result.
4335 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4336 unsigned int imms
, unsigned int immr
)
4339 unsigned e
, levels
, s
, r
;
4342 assert(immn
< 2 && imms
< 64 && immr
< 64);
4344 /* The bit patterns we create here are 64 bit patterns which
4345 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4346 * 64 bits each. Each element contains the same value: a run
4347 * of between 1 and e-1 non-zero bits, rotated within the
4348 * element by between 0 and e-1 bits.
4350 * The element size and run length are encoded into immn (1 bit)
4351 * and imms (6 bits) as follows:
4352 * 64 bit elements: immn = 1, imms = <length of run - 1>
4353 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4354 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4355 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4356 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4357 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4358 * Notice that immn = 0, imms = 11111x is the only combination
4359 * not covered by one of the above options; this is reserved.
4360 * Further, <length of run - 1> all-ones is a reserved pattern.
4362 * In all cases the rotation is by immr % e (and immr is 6 bits).
4365 /* First determine the element size */
4366 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4368 /* This is the immn == 0, imms == 0x11111x case */
4378 /* <length of run - 1> mustn't be all-ones. */
4382 /* Create the value of one element: s+1 set bits rotated
4383 * by r within the element (which is e bits wide)...
4385 mask
= bitmask64(s
+ 1);
4387 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4388 mask
&= bitmask64(e
);
4390 /* ...then replicate the element over the whole 64 bit value */
4391 mask
= bitfield_replicate(mask
, e
);
4396 /* Logical (immediate)
4397 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4398 * +----+-----+-------------+---+------+------+------+------+
4399 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4400 * +----+-----+-------------+---+------+------+------+------+
4402 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4404 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4405 TCGv_i64 tcg_rd
, tcg_rn
;
4407 bool is_and
= false;
4409 sf
= extract32(insn
, 31, 1);
4410 opc
= extract32(insn
, 29, 2);
4411 is_n
= extract32(insn
, 22, 1);
4412 immr
= extract32(insn
, 16, 6);
4413 imms
= extract32(insn
, 10, 6);
4414 rn
= extract32(insn
, 5, 5);
4415 rd
= extract32(insn
, 0, 5);
4418 unallocated_encoding(s
);
4422 if (opc
== 0x3) { /* ANDS */
4423 tcg_rd
= cpu_reg(s
, rd
);
4425 tcg_rd
= cpu_reg_sp(s
, rd
);
4427 tcg_rn
= cpu_reg(s
, rn
);
4429 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4430 /* some immediate field values are reserved */
4431 unallocated_encoding(s
);
4436 wmask
&= 0xffffffff;
4440 case 0x3: /* ANDS */
4442 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4446 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4449 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4452 assert(FALSE
); /* must handle all above */
4456 if (!sf
&& !is_and
) {
4457 /* zero extend final result; we know we can skip this for AND
4458 * since the immediate had the high 32 bits clear.
4460 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4463 if (opc
== 3) { /* ANDS */
4464 gen_logic_CC(sf
, tcg_rd
);
4469 * Move wide (immediate)
4471 * 31 30 29 28 23 22 21 20 5 4 0
4472 * +--+-----+-------------+-----+----------------+------+
4473 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4474 * +--+-----+-------------+-----+----------------+------+
4476 * sf: 0 -> 32 bit, 1 -> 64 bit
4477 * opc: 00 -> N, 10 -> Z, 11 -> K
4478 * hw: shift/16 (0,16, and sf only 32, 48)
4480 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4482 int rd
= extract32(insn
, 0, 5);
4483 uint64_t imm
= extract32(insn
, 5, 16);
4484 int sf
= extract32(insn
, 31, 1);
4485 int opc
= extract32(insn
, 29, 2);
4486 int pos
= extract32(insn
, 21, 2) << 4;
4487 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4490 if (!sf
&& (pos
>= 32)) {
4491 unallocated_encoding(s
);
4505 tcg_gen_movi_i64(tcg_rd
, imm
);
4508 tcg_imm
= tcg_const_i64(imm
);
4509 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4510 tcg_temp_free_i64(tcg_imm
);
4512 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4516 unallocated_encoding(s
);
4522 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4523 * +----+-----+-------------+---+------+------+------+------+
4524 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4525 * +----+-----+-------------+---+------+------+------+------+
4527 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4529 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4530 TCGv_i64 tcg_rd
, tcg_tmp
;
4532 sf
= extract32(insn
, 31, 1);
4533 opc
= extract32(insn
, 29, 2);
4534 n
= extract32(insn
, 22, 1);
4535 ri
= extract32(insn
, 16, 6);
4536 si
= extract32(insn
, 10, 6);
4537 rn
= extract32(insn
, 5, 5);
4538 rd
= extract32(insn
, 0, 5);
4539 bitsize
= sf
? 64 : 32;
4541 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4542 unallocated_encoding(s
);
4546 tcg_rd
= cpu_reg(s
, rd
);
4548 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4549 to be smaller than bitsize, we'll never reference data outside the
4550 low 32-bits anyway. */
4551 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4553 /* Recognize simple(r) extractions. */
4555 /* Wd<s-r:0> = Wn<s:r> */
4556 len
= (si
- ri
) + 1;
4557 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4558 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4560 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4561 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4564 /* opc == 1, BFXIL fall through to deposit */
4565 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4568 /* Handle the ri > si case with a deposit
4569 * Wd<32+s-r,32-r> = Wn<s:0>
4572 pos
= (bitsize
- ri
) & (bitsize
- 1);
4575 if (opc
== 0 && len
< ri
) {
4576 /* SBFM: sign extend the destination field from len to fill
4577 the balance of the word. Let the deposit below insert all
4578 of those sign bits. */
4579 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4583 if (opc
== 1) { /* BFM, BFXIL */
4584 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4586 /* SBFM or UBFM: We start with zero, and we haven't modified
4587 any bits outside bitsize, therefore the zero-extension
4588 below is unneeded. */
4589 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4594 if (!sf
) { /* zero extend final result */
4595 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4600 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4601 * +----+------+-------------+---+----+------+--------+------+------+
4602 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4603 * +----+------+-------------+---+----+------+--------+------+------+
4605 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4607 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4609 sf
= extract32(insn
, 31, 1);
4610 n
= extract32(insn
, 22, 1);
4611 rm
= extract32(insn
, 16, 5);
4612 imm
= extract32(insn
, 10, 6);
4613 rn
= extract32(insn
, 5, 5);
4614 rd
= extract32(insn
, 0, 5);
4615 op21
= extract32(insn
, 29, 2);
4616 op0
= extract32(insn
, 21, 1);
4617 bitsize
= sf
? 64 : 32;
4619 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4620 unallocated_encoding(s
);
4622 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4624 tcg_rd
= cpu_reg(s
, rd
);
4626 if (unlikely(imm
== 0)) {
4627 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4628 * so an extract from bit 0 is a special case.
4631 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4633 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4636 tcg_rm
= cpu_reg(s
, rm
);
4637 tcg_rn
= cpu_reg(s
, rn
);
4640 /* Specialization to ROR happens in EXTRACT2. */
4641 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4643 TCGv_i32 t0
= tcg_temp_new_i32();
4645 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4647 tcg_gen_rotri_i32(t0
, t0
, imm
);
4649 TCGv_i32 t1
= tcg_temp_new_i32();
4650 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4651 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4652 tcg_temp_free_i32(t1
);
4654 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4655 tcg_temp_free_i32(t0
);
4661 /* Data processing - immediate */
4662 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4664 switch (extract32(insn
, 23, 6)) {
4665 case 0x20: case 0x21: /* PC-rel. addressing */
4666 disas_pc_rel_adr(s
, insn
);
4668 case 0x22: /* Add/subtract (immediate) */
4669 disas_add_sub_imm(s
, insn
);
4671 case 0x23: /* Add/subtract (immediate, with tags) */
4672 disas_add_sub_imm_with_tags(s
, insn
);
4674 case 0x24: /* Logical (immediate) */
4675 disas_logic_imm(s
, insn
);
4677 case 0x25: /* Move wide (immediate) */
4678 disas_movw_imm(s
, insn
);
4680 case 0x26: /* Bitfield */
4681 disas_bitfield(s
, insn
);
4683 case 0x27: /* Extract */
4684 disas_extract(s
, insn
);
4687 unallocated_encoding(s
);
4692 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4693 * Note that it is the caller's responsibility to ensure that the
4694 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4695 * mandated semantics for out of range shifts.
4697 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4698 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4700 switch (shift_type
) {
4701 case A64_SHIFT_TYPE_LSL
:
4702 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4704 case A64_SHIFT_TYPE_LSR
:
4705 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4707 case A64_SHIFT_TYPE_ASR
:
4709 tcg_gen_ext32s_i64(dst
, src
);
4711 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4713 case A64_SHIFT_TYPE_ROR
:
4715 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4718 t0
= tcg_temp_new_i32();
4719 t1
= tcg_temp_new_i32();
4720 tcg_gen_extrl_i64_i32(t0
, src
);
4721 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4722 tcg_gen_rotr_i32(t0
, t0
, t1
);
4723 tcg_gen_extu_i32_i64(dst
, t0
);
4724 tcg_temp_free_i32(t0
);
4725 tcg_temp_free_i32(t1
);
4729 assert(FALSE
); /* all shift types should be handled */
4733 if (!sf
) { /* zero extend final result */
4734 tcg_gen_ext32u_i64(dst
, dst
);
4738 /* Shift a TCGv src by immediate, put result in dst.
4739 * The shift amount must be in range (this should always be true as the
4740 * relevant instructions will UNDEF on bad shift immediates).
4742 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4743 enum a64_shift_type shift_type
, unsigned int shift_i
)
4745 assert(shift_i
< (sf
? 64 : 32));
4748 tcg_gen_mov_i64(dst
, src
);
4750 TCGv_i64 shift_const
;
4752 shift_const
= tcg_const_i64(shift_i
);
4753 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4754 tcg_temp_free_i64(shift_const
);
4758 /* Logical (shifted register)
4759 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4760 * +----+-----+-----------+-------+---+------+--------+------+------+
4761 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4762 * +----+-----+-----------+-------+---+------+--------+------+------+
4764 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4766 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4767 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4769 sf
= extract32(insn
, 31, 1);
4770 opc
= extract32(insn
, 29, 2);
4771 shift_type
= extract32(insn
, 22, 2);
4772 invert
= extract32(insn
, 21, 1);
4773 rm
= extract32(insn
, 16, 5);
4774 shift_amount
= extract32(insn
, 10, 6);
4775 rn
= extract32(insn
, 5, 5);
4776 rd
= extract32(insn
, 0, 5);
4778 if (!sf
&& (shift_amount
& (1 << 5))) {
4779 unallocated_encoding(s
);
4783 tcg_rd
= cpu_reg(s
, rd
);
4785 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4786 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4787 * register-register MOV and MVN, so it is worth special casing.
4789 tcg_rm
= cpu_reg(s
, rm
);
4791 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4793 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4797 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4799 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4805 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4808 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4811 tcg_rn
= cpu_reg(s
, rn
);
4813 switch (opc
| (invert
<< 2)) {
4816 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4819 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4822 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4826 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4829 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4832 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4840 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4844 gen_logic_CC(sf
, tcg_rd
);
4849 * Add/subtract (extended register)
4851 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4852 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4853 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4854 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4856 * sf: 0 -> 32bit, 1 -> 64bit
4857 * op: 0 -> add , 1 -> sub
4860 * option: extension type (see DecodeRegExtend)
4861 * imm3: optional shift to Rm
4863 * Rd = Rn + LSL(extend(Rm), amount)
4865 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4867 int rd
= extract32(insn
, 0, 5);
4868 int rn
= extract32(insn
, 5, 5);
4869 int imm3
= extract32(insn
, 10, 3);
4870 int option
= extract32(insn
, 13, 3);
4871 int rm
= extract32(insn
, 16, 5);
4872 int opt
= extract32(insn
, 22, 2);
4873 bool setflags
= extract32(insn
, 29, 1);
4874 bool sub_op
= extract32(insn
, 30, 1);
4875 bool sf
= extract32(insn
, 31, 1);
4877 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4879 TCGv_i64 tcg_result
;
4881 if (imm3
> 4 || opt
!= 0) {
4882 unallocated_encoding(s
);
4886 /* non-flag setting ops may use SP */
4888 tcg_rd
= cpu_reg_sp(s
, rd
);
4890 tcg_rd
= cpu_reg(s
, rd
);
4892 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4894 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4895 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4897 tcg_result
= tcg_temp_new_i64();
4901 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4903 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4907 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4909 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4914 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4916 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4919 tcg_temp_free_i64(tcg_result
);
4923 * Add/subtract (shifted register)
4925 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4926 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4927 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4928 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4930 * sf: 0 -> 32bit, 1 -> 64bit
4931 * op: 0 -> add , 1 -> sub
4933 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4934 * imm6: Shift amount to apply to Rm before the add/sub
4936 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4938 int rd
= extract32(insn
, 0, 5);
4939 int rn
= extract32(insn
, 5, 5);
4940 int imm6
= extract32(insn
, 10, 6);
4941 int rm
= extract32(insn
, 16, 5);
4942 int shift_type
= extract32(insn
, 22, 2);
4943 bool setflags
= extract32(insn
, 29, 1);
4944 bool sub_op
= extract32(insn
, 30, 1);
4945 bool sf
= extract32(insn
, 31, 1);
4947 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4948 TCGv_i64 tcg_rn
, tcg_rm
;
4949 TCGv_i64 tcg_result
;
4951 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4952 unallocated_encoding(s
);
4956 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4957 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4959 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4961 tcg_result
= tcg_temp_new_i64();
4965 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4967 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4971 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4973 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4978 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4980 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4983 tcg_temp_free_i64(tcg_result
);
4986 /* Data-processing (3 source)
4988 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4989 * +--+------+-----------+------+------+----+------+------+------+
4990 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4991 * +--+------+-----------+------+------+----+------+------+------+
4993 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4995 int rd
= extract32(insn
, 0, 5);
4996 int rn
= extract32(insn
, 5, 5);
4997 int ra
= extract32(insn
, 10, 5);
4998 int rm
= extract32(insn
, 16, 5);
4999 int op_id
= (extract32(insn
, 29, 3) << 4) |
5000 (extract32(insn
, 21, 3) << 1) |
5001 extract32(insn
, 15, 1);
5002 bool sf
= extract32(insn
, 31, 1);
5003 bool is_sub
= extract32(op_id
, 0, 1);
5004 bool is_high
= extract32(op_id
, 2, 1);
5005 bool is_signed
= false;
5010 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
5012 case 0x42: /* SMADDL */
5013 case 0x43: /* SMSUBL */
5014 case 0x44: /* SMULH */
5017 case 0x0: /* MADD (32bit) */
5018 case 0x1: /* MSUB (32bit) */
5019 case 0x40: /* MADD (64bit) */
5020 case 0x41: /* MSUB (64bit) */
5021 case 0x4a: /* UMADDL */
5022 case 0x4b: /* UMSUBL */
5023 case 0x4c: /* UMULH */
5026 unallocated_encoding(s
);
5031 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5032 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5033 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5034 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5037 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5039 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5042 tcg_temp_free_i64(low_bits
);
5046 tcg_op1
= tcg_temp_new_i64();
5047 tcg_op2
= tcg_temp_new_i64();
5048 tcg_tmp
= tcg_temp_new_i64();
5051 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5052 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5055 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5056 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5058 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5059 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5063 if (ra
== 31 && !is_sub
) {
5064 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5065 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5067 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5069 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5071 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5076 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5079 tcg_temp_free_i64(tcg_op1
);
5080 tcg_temp_free_i64(tcg_op2
);
5081 tcg_temp_free_i64(tcg_tmp
);
5084 /* Add/subtract (with carry)
5085 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5086 * +--+--+--+------------------------+------+-------------+------+-----+
5087 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5088 * +--+--+--+------------------------+------+-------------+------+-----+
5091 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5093 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5094 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5096 sf
= extract32(insn
, 31, 1);
5097 op
= extract32(insn
, 30, 1);
5098 setflags
= extract32(insn
, 29, 1);
5099 rm
= extract32(insn
, 16, 5);
5100 rn
= extract32(insn
, 5, 5);
5101 rd
= extract32(insn
, 0, 5);
5103 tcg_rd
= cpu_reg(s
, rd
);
5104 tcg_rn
= cpu_reg(s
, rn
);
5107 tcg_y
= new_tmp_a64(s
);
5108 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5110 tcg_y
= cpu_reg(s
, rm
);
5114 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5116 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5121 * Rotate right into flags
5122 * 31 30 29 21 15 10 5 4 0
5123 * +--+--+--+-----------------+--------+-----------+------+--+------+
5124 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5125 * +--+--+--+-----------------+--------+-----------+------+--+------+
5127 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5129 int mask
= extract32(insn
, 0, 4);
5130 int o2
= extract32(insn
, 4, 1);
5131 int rn
= extract32(insn
, 5, 5);
5132 int imm6
= extract32(insn
, 15, 6);
5133 int sf_op_s
= extract32(insn
, 29, 3);
5137 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5138 unallocated_encoding(s
);
5142 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5143 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5145 nzcv
= tcg_temp_new_i32();
5146 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5148 if (mask
& 8) { /* N */
5149 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5151 if (mask
& 4) { /* Z */
5152 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5153 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5155 if (mask
& 2) { /* C */
5156 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5158 if (mask
& 1) { /* V */
5159 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5162 tcg_temp_free_i32(nzcv
);
5166 * Evaluate into flags
5167 * 31 30 29 21 15 14 10 5 4 0
5168 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5169 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5170 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5172 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5174 int o3_mask
= extract32(insn
, 0, 5);
5175 int rn
= extract32(insn
, 5, 5);
5176 int o2
= extract32(insn
, 15, 6);
5177 int sz
= extract32(insn
, 14, 1);
5178 int sf_op_s
= extract32(insn
, 29, 3);
5182 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5183 !dc_isar_feature(aa64_condm_4
, s
)) {
5184 unallocated_encoding(s
);
5187 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5189 tmp
= tcg_temp_new_i32();
5190 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5191 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5192 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5193 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5194 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5195 tcg_temp_free_i32(tmp
);
5198 /* Conditional compare (immediate / register)
5199 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5200 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5201 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5202 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5205 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5207 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5208 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5209 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5212 if (!extract32(insn
, 29, 1)) {
5213 unallocated_encoding(s
);
5216 if (insn
& (1 << 10 | 1 << 4)) {
5217 unallocated_encoding(s
);
5220 sf
= extract32(insn
, 31, 1);
5221 op
= extract32(insn
, 30, 1);
5222 is_imm
= extract32(insn
, 11, 1);
5223 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5224 cond
= extract32(insn
, 12, 4);
5225 rn
= extract32(insn
, 5, 5);
5226 nzcv
= extract32(insn
, 0, 4);
5228 /* Set T0 = !COND. */
5229 tcg_t0
= tcg_temp_new_i32();
5230 arm_test_cc(&c
, cond
);
5231 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5234 /* Load the arguments for the new comparison. */
5236 tcg_y
= new_tmp_a64(s
);
5237 tcg_gen_movi_i64(tcg_y
, y
);
5239 tcg_y
= cpu_reg(s
, y
);
5241 tcg_rn
= cpu_reg(s
, rn
);
5243 /* Set the flags for the new comparison. */
5244 tcg_tmp
= tcg_temp_new_i64();
5246 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5248 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5250 tcg_temp_free_i64(tcg_tmp
);
5252 /* If COND was false, force the flags to #nzcv. Compute two masks
5253 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5254 * For tcg hosts that support ANDC, we can make do with just T1.
5255 * In either case, allow the tcg optimizer to delete any unused mask.
5257 tcg_t1
= tcg_temp_new_i32();
5258 tcg_t2
= tcg_temp_new_i32();
5259 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5260 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5262 if (nzcv
& 8) { /* N */
5263 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5265 if (TCG_TARGET_HAS_andc_i32
) {
5266 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5268 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5271 if (nzcv
& 4) { /* Z */
5272 if (TCG_TARGET_HAS_andc_i32
) {
5273 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5275 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5278 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5280 if (nzcv
& 2) { /* C */
5281 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5283 if (TCG_TARGET_HAS_andc_i32
) {
5284 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5286 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5289 if (nzcv
& 1) { /* V */
5290 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5292 if (TCG_TARGET_HAS_andc_i32
) {
5293 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5295 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5298 tcg_temp_free_i32(tcg_t0
);
5299 tcg_temp_free_i32(tcg_t1
);
5300 tcg_temp_free_i32(tcg_t2
);
5303 /* Conditional select
5304 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5305 * +----+----+---+-----------------+------+------+-----+------+------+
5306 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5307 * +----+----+---+-----------------+------+------+-----+------+------+
5309 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5311 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5312 TCGv_i64 tcg_rd
, zero
;
5315 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5316 /* S == 1 or op2<1> == 1 */
5317 unallocated_encoding(s
);
5320 sf
= extract32(insn
, 31, 1);
5321 else_inv
= extract32(insn
, 30, 1);
5322 rm
= extract32(insn
, 16, 5);
5323 cond
= extract32(insn
, 12, 4);
5324 else_inc
= extract32(insn
, 10, 1);
5325 rn
= extract32(insn
, 5, 5);
5326 rd
= extract32(insn
, 0, 5);
5328 tcg_rd
= cpu_reg(s
, rd
);
5330 a64_test_cc(&c
, cond
);
5331 zero
= tcg_const_i64(0);
5333 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5335 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5337 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5340 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5341 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5342 if (else_inv
&& else_inc
) {
5343 tcg_gen_neg_i64(t_false
, t_false
);
5344 } else if (else_inv
) {
5345 tcg_gen_not_i64(t_false
, t_false
);
5346 } else if (else_inc
) {
5347 tcg_gen_addi_i64(t_false
, t_false
, 1);
5349 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5352 tcg_temp_free_i64(zero
);
5356 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5360 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5361 unsigned int rn
, unsigned int rd
)
5363 TCGv_i64 tcg_rd
, tcg_rn
;
5364 tcg_rd
= cpu_reg(s
, rd
);
5365 tcg_rn
= cpu_reg(s
, rn
);
5368 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5370 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5371 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5372 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5373 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5374 tcg_temp_free_i32(tcg_tmp32
);
5378 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5379 unsigned int rn
, unsigned int rd
)
5381 TCGv_i64 tcg_rd
, tcg_rn
;
5382 tcg_rd
= cpu_reg(s
, rd
);
5383 tcg_rn
= cpu_reg(s
, rn
);
5386 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5388 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5389 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5390 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5391 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5392 tcg_temp_free_i32(tcg_tmp32
);
5396 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5397 unsigned int rn
, unsigned int rd
)
5399 TCGv_i64 tcg_rd
, tcg_rn
;
5400 tcg_rd
= cpu_reg(s
, rd
);
5401 tcg_rn
= cpu_reg(s
, rn
);
5404 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5406 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5407 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5408 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5409 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5410 tcg_temp_free_i32(tcg_tmp32
);
5414 /* REV with sf==1, opcode==3 ("REV64") */
5415 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5416 unsigned int rn
, unsigned int rd
)
5419 unallocated_encoding(s
);
5422 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5425 /* REV with sf==0, opcode==2
5426 * REV32 (sf==1, opcode==2)
5428 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5429 unsigned int rn
, unsigned int rd
)
5431 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5432 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5435 tcg_gen_bswap64_i64(tcg_rd
, tcg_rn
);
5436 tcg_gen_rotri_i64(tcg_rd
, tcg_rd
, 32);
5438 tcg_gen_bswap32_i64(tcg_rd
, tcg_rn
, TCG_BSWAP_OZ
);
5442 /* REV16 (opcode==1) */
5443 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5444 unsigned int rn
, unsigned int rd
)
5446 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5447 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5448 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5449 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5451 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5452 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5453 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5454 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5455 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5457 tcg_temp_free_i64(mask
);
5458 tcg_temp_free_i64(tcg_tmp
);
5461 /* Data-processing (1 source)
5462 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5463 * +----+---+---+-----------------+---------+--------+------+------+
5464 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5465 * +----+---+---+-----------------+---------+--------+------+------+
5467 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5469 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5472 if (extract32(insn
, 29, 1)) {
5473 unallocated_encoding(s
);
5477 sf
= extract32(insn
, 31, 1);
5478 opcode
= extract32(insn
, 10, 6);
5479 opcode2
= extract32(insn
, 16, 5);
5480 rn
= extract32(insn
, 5, 5);
5481 rd
= extract32(insn
, 0, 5);
5483 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5485 switch (MAP(sf
, opcode2
, opcode
)) {
5486 case MAP(0, 0x00, 0x00): /* RBIT */
5487 case MAP(1, 0x00, 0x00):
5488 handle_rbit(s
, sf
, rn
, rd
);
5490 case MAP(0, 0x00, 0x01): /* REV16 */
5491 case MAP(1, 0x00, 0x01):
5492 handle_rev16(s
, sf
, rn
, rd
);
5494 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5495 case MAP(1, 0x00, 0x02):
5496 handle_rev32(s
, sf
, rn
, rd
);
5498 case MAP(1, 0x00, 0x03): /* REV64 */
5499 handle_rev64(s
, sf
, rn
, rd
);
5501 case MAP(0, 0x00, 0x04): /* CLZ */
5502 case MAP(1, 0x00, 0x04):
5503 handle_clz(s
, sf
, rn
, rd
);
5505 case MAP(0, 0x00, 0x05): /* CLS */
5506 case MAP(1, 0x00, 0x05):
5507 handle_cls(s
, sf
, rn
, rd
);
5509 case MAP(1, 0x01, 0x00): /* PACIA */
5510 if (s
->pauth_active
) {
5511 tcg_rd
= cpu_reg(s
, rd
);
5512 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5513 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5514 goto do_unallocated
;
5517 case MAP(1, 0x01, 0x01): /* PACIB */
5518 if (s
->pauth_active
) {
5519 tcg_rd
= cpu_reg(s
, rd
);
5520 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5521 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5522 goto do_unallocated
;
5525 case MAP(1, 0x01, 0x02): /* PACDA */
5526 if (s
->pauth_active
) {
5527 tcg_rd
= cpu_reg(s
, rd
);
5528 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5529 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5530 goto do_unallocated
;
5533 case MAP(1, 0x01, 0x03): /* PACDB */
5534 if (s
->pauth_active
) {
5535 tcg_rd
= cpu_reg(s
, rd
);
5536 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5537 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5538 goto do_unallocated
;
5541 case MAP(1, 0x01, 0x04): /* AUTIA */
5542 if (s
->pauth_active
) {
5543 tcg_rd
= cpu_reg(s
, rd
);
5544 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5545 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5546 goto do_unallocated
;
5549 case MAP(1, 0x01, 0x05): /* AUTIB */
5550 if (s
->pauth_active
) {
5551 tcg_rd
= cpu_reg(s
, rd
);
5552 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5553 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5554 goto do_unallocated
;
5557 case MAP(1, 0x01, 0x06): /* AUTDA */
5558 if (s
->pauth_active
) {
5559 tcg_rd
= cpu_reg(s
, rd
);
5560 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5561 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5562 goto do_unallocated
;
5565 case MAP(1, 0x01, 0x07): /* AUTDB */
5566 if (s
->pauth_active
) {
5567 tcg_rd
= cpu_reg(s
, rd
);
5568 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5569 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5570 goto do_unallocated
;
5573 case MAP(1, 0x01, 0x08): /* PACIZA */
5574 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5575 goto do_unallocated
;
5576 } else if (s
->pauth_active
) {
5577 tcg_rd
= cpu_reg(s
, rd
);
5578 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5581 case MAP(1, 0x01, 0x09): /* PACIZB */
5582 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5583 goto do_unallocated
;
5584 } else if (s
->pauth_active
) {
5585 tcg_rd
= cpu_reg(s
, rd
);
5586 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5589 case MAP(1, 0x01, 0x0a): /* PACDZA */
5590 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5591 goto do_unallocated
;
5592 } else if (s
->pauth_active
) {
5593 tcg_rd
= cpu_reg(s
, rd
);
5594 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5597 case MAP(1, 0x01, 0x0b): /* PACDZB */
5598 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5599 goto do_unallocated
;
5600 } else if (s
->pauth_active
) {
5601 tcg_rd
= cpu_reg(s
, rd
);
5602 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5605 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5606 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5607 goto do_unallocated
;
5608 } else if (s
->pauth_active
) {
5609 tcg_rd
= cpu_reg(s
, rd
);
5610 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5613 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5614 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5615 goto do_unallocated
;
5616 } else if (s
->pauth_active
) {
5617 tcg_rd
= cpu_reg(s
, rd
);
5618 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5621 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5622 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5623 goto do_unallocated
;
5624 } else if (s
->pauth_active
) {
5625 tcg_rd
= cpu_reg(s
, rd
);
5626 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5629 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5630 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5631 goto do_unallocated
;
5632 } else if (s
->pauth_active
) {
5633 tcg_rd
= cpu_reg(s
, rd
);
5634 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5637 case MAP(1, 0x01, 0x10): /* XPACI */
5638 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5639 goto do_unallocated
;
5640 } else if (s
->pauth_active
) {
5641 tcg_rd
= cpu_reg(s
, rd
);
5642 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5645 case MAP(1, 0x01, 0x11): /* XPACD */
5646 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5647 goto do_unallocated
;
5648 } else if (s
->pauth_active
) {
5649 tcg_rd
= cpu_reg(s
, rd
);
5650 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5655 unallocated_encoding(s
);
5662 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5663 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5665 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5666 tcg_rd
= cpu_reg(s
, rd
);
5668 if (!sf
&& is_signed
) {
5669 tcg_n
= new_tmp_a64(s
);
5670 tcg_m
= new_tmp_a64(s
);
5671 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5672 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5674 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5675 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5679 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5681 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5684 if (!sf
) { /* zero extend final result */
5685 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5689 /* LSLV, LSRV, ASRV, RORV */
5690 static void handle_shift_reg(DisasContext
*s
,
5691 enum a64_shift_type shift_type
, unsigned int sf
,
5692 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5694 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5695 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5696 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5698 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5699 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5700 tcg_temp_free_i64(tcg_shift
);
5703 /* CRC32[BHWX], CRC32C[BHWX] */
5704 static void handle_crc32(DisasContext
*s
,
5705 unsigned int sf
, unsigned int sz
, bool crc32c
,
5706 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5708 TCGv_i64 tcg_acc
, tcg_val
;
5711 if (!dc_isar_feature(aa64_crc32
, s
)
5712 || (sf
== 1 && sz
!= 3)
5713 || (sf
== 0 && sz
== 3)) {
5714 unallocated_encoding(s
);
5719 tcg_val
= cpu_reg(s
, rm
);
5733 g_assert_not_reached();
5735 tcg_val
= new_tmp_a64(s
);
5736 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5739 tcg_acc
= cpu_reg(s
, rn
);
5740 tcg_bytes
= tcg_const_i32(1 << sz
);
5743 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5745 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5748 tcg_temp_free_i32(tcg_bytes
);
5751 /* Data-processing (2 source)
5752 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5753 * +----+---+---+-----------------+------+--------+------+------+
5754 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5755 * +----+---+---+-----------------+------+--------+------+------+
5757 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5759 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5760 sf
= extract32(insn
, 31, 1);
5761 setflag
= extract32(insn
, 29, 1);
5762 rm
= extract32(insn
, 16, 5);
5763 opcode
= extract32(insn
, 10, 6);
5764 rn
= extract32(insn
, 5, 5);
5765 rd
= extract32(insn
, 0, 5);
5767 if (setflag
&& opcode
!= 0) {
5768 unallocated_encoding(s
);
5773 case 0: /* SUBP(S) */
5774 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5775 goto do_unallocated
;
5777 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5779 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5780 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5781 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5782 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5783 tcg_d
= cpu_reg(s
, rd
);
5786 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5788 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5793 handle_div(s
, false, sf
, rm
, rn
, rd
);
5796 handle_div(s
, true, sf
, rm
, rn
, rd
);
5799 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5800 goto do_unallocated
;
5803 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5804 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5806 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5811 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5812 goto do_unallocated
;
5814 TCGv_i64 t1
= tcg_const_i64(1);
5815 TCGv_i64 t2
= tcg_temp_new_i64();
5817 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5818 tcg_gen_shl_i64(t1
, t1
, t2
);
5819 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5821 tcg_temp_free_i64(t1
);
5822 tcg_temp_free_i64(t2
);
5826 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5829 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5832 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5835 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5837 case 12: /* PACGA */
5838 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5839 goto do_unallocated
;
5841 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5842 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5851 case 23: /* CRC32 */
5853 int sz
= extract32(opcode
, 0, 2);
5854 bool crc32c
= extract32(opcode
, 2, 1);
5855 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5860 unallocated_encoding(s
);
5866 * Data processing - register
5867 * 31 30 29 28 25 21 20 16 10 0
5868 * +--+---+--+---+-------+-----+-------+-------+---------+
5869 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5870 * +--+---+--+---+-------+-----+-------+-------+---------+
5872 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5874 int op0
= extract32(insn
, 30, 1);
5875 int op1
= extract32(insn
, 28, 1);
5876 int op2
= extract32(insn
, 21, 4);
5877 int op3
= extract32(insn
, 10, 6);
5882 /* Add/sub (extended register) */
5883 disas_add_sub_ext_reg(s
, insn
);
5885 /* Add/sub (shifted register) */
5886 disas_add_sub_reg(s
, insn
);
5889 /* Logical (shifted register) */
5890 disas_logic_reg(s
, insn
);
5898 case 0x00: /* Add/subtract (with carry) */
5899 disas_adc_sbc(s
, insn
);
5902 case 0x01: /* Rotate right into flags */
5904 disas_rotate_right_into_flags(s
, insn
);
5907 case 0x02: /* Evaluate into flags */
5911 disas_evaluate_into_flags(s
, insn
);
5915 goto do_unallocated
;
5919 case 0x2: /* Conditional compare */
5920 disas_cc(s
, insn
); /* both imm and reg forms */
5923 case 0x4: /* Conditional select */
5924 disas_cond_select(s
, insn
);
5927 case 0x6: /* Data-processing */
5928 if (op0
) { /* (1 source) */
5929 disas_data_proc_1src(s
, insn
);
5930 } else { /* (2 source) */
5931 disas_data_proc_2src(s
, insn
);
5934 case 0x8 ... 0xf: /* (3 source) */
5935 disas_data_proc_3src(s
, insn
);
5940 unallocated_encoding(s
);
5945 static void handle_fp_compare(DisasContext
*s
, int size
,
5946 unsigned int rn
, unsigned int rm
,
5947 bool cmp_with_zero
, bool signal_all_nans
)
5949 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5950 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5952 if (size
== MO_64
) {
5953 TCGv_i64 tcg_vn
, tcg_vm
;
5955 tcg_vn
= read_fp_dreg(s
, rn
);
5956 if (cmp_with_zero
) {
5957 tcg_vm
= tcg_const_i64(0);
5959 tcg_vm
= read_fp_dreg(s
, rm
);
5961 if (signal_all_nans
) {
5962 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5964 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5966 tcg_temp_free_i64(tcg_vn
);
5967 tcg_temp_free_i64(tcg_vm
);
5969 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5970 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5972 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5973 if (cmp_with_zero
) {
5974 tcg_gen_movi_i32(tcg_vm
, 0);
5976 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5981 if (signal_all_nans
) {
5982 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5984 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5988 if (signal_all_nans
) {
5989 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5991 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5995 g_assert_not_reached();
5998 tcg_temp_free_i32(tcg_vn
);
5999 tcg_temp_free_i32(tcg_vm
);
6002 tcg_temp_free_ptr(fpst
);
6004 gen_set_nzcv(tcg_flags
);
6006 tcg_temp_free_i64(tcg_flags
);
6009 /* Floating point compare
6010 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
6011 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6012 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
6013 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6015 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
6017 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
6020 mos
= extract32(insn
, 29, 3);
6021 type
= extract32(insn
, 22, 2);
6022 rm
= extract32(insn
, 16, 5);
6023 op
= extract32(insn
, 14, 2);
6024 rn
= extract32(insn
, 5, 5);
6025 opc
= extract32(insn
, 3, 2);
6026 op2r
= extract32(insn
, 0, 3);
6028 if (mos
|| op
|| op2r
) {
6029 unallocated_encoding(s
);
6042 if (dc_isar_feature(aa64_fp16
, s
)) {
6047 unallocated_encoding(s
);
6051 if (!fp_access_check(s
)) {
6055 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6058 /* Floating point conditional compare
6059 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6060 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6061 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6062 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6064 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6066 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6068 TCGLabel
*label_continue
= NULL
;
6071 mos
= extract32(insn
, 29, 3);
6072 type
= extract32(insn
, 22, 2);
6073 rm
= extract32(insn
, 16, 5);
6074 cond
= extract32(insn
, 12, 4);
6075 rn
= extract32(insn
, 5, 5);
6076 op
= extract32(insn
, 4, 1);
6077 nzcv
= extract32(insn
, 0, 4);
6080 unallocated_encoding(s
);
6093 if (dc_isar_feature(aa64_fp16
, s
)) {
6098 unallocated_encoding(s
);
6102 if (!fp_access_check(s
)) {
6106 if (cond
< 0x0e) { /* not always */
6107 TCGLabel
*label_match
= gen_new_label();
6108 label_continue
= gen_new_label();
6109 arm_gen_test_cc(cond
, label_match
);
6111 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6112 gen_set_nzcv(tcg_flags
);
6113 tcg_temp_free_i64(tcg_flags
);
6114 tcg_gen_br(label_continue
);
6115 gen_set_label(label_match
);
6118 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6121 gen_set_label(label_continue
);
6125 /* Floating point conditional select
6126 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6127 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6128 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6129 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6131 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6133 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6134 TCGv_i64 t_true
, t_false
, t_zero
;
6138 mos
= extract32(insn
, 29, 3);
6139 type
= extract32(insn
, 22, 2);
6140 rm
= extract32(insn
, 16, 5);
6141 cond
= extract32(insn
, 12, 4);
6142 rn
= extract32(insn
, 5, 5);
6143 rd
= extract32(insn
, 0, 5);
6146 unallocated_encoding(s
);
6159 if (dc_isar_feature(aa64_fp16
, s
)) {
6164 unallocated_encoding(s
);
6168 if (!fp_access_check(s
)) {
6172 /* Zero extend sreg & hreg inputs to 64 bits now. */
6173 t_true
= tcg_temp_new_i64();
6174 t_false
= tcg_temp_new_i64();
6175 read_vec_element(s
, t_true
, rn
, 0, sz
);
6176 read_vec_element(s
, t_false
, rm
, 0, sz
);
6178 a64_test_cc(&c
, cond
);
6179 t_zero
= tcg_const_i64(0);
6180 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6181 tcg_temp_free_i64(t_zero
);
6182 tcg_temp_free_i64(t_false
);
6185 /* Note that sregs & hregs write back zeros to the high bits,
6186 and we've already done the zero-extension. */
6187 write_fp_dreg(s
, rd
, t_true
);
6188 tcg_temp_free_i64(t_true
);
6191 /* Floating-point data-processing (1 source) - half precision */
6192 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6194 TCGv_ptr fpst
= NULL
;
6195 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6196 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6199 case 0x0: /* FMOV */
6200 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6202 case 0x1: /* FABS */
6203 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6205 case 0x2: /* FNEG */
6206 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6208 case 0x3: /* FSQRT */
6209 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6210 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6212 case 0x8: /* FRINTN */
6213 case 0x9: /* FRINTP */
6214 case 0xa: /* FRINTM */
6215 case 0xb: /* FRINTZ */
6216 case 0xc: /* FRINTA */
6218 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6219 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6221 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6222 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6224 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6225 tcg_temp_free_i32(tcg_rmode
);
6228 case 0xe: /* FRINTX */
6229 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6230 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6232 case 0xf: /* FRINTI */
6233 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6234 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6240 write_fp_sreg(s
, rd
, tcg_res
);
6243 tcg_temp_free_ptr(fpst
);
6245 tcg_temp_free_i32(tcg_op
);
6246 tcg_temp_free_i32(tcg_res
);
6249 /* Floating-point data-processing (1 source) - single precision */
6250 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6252 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6253 TCGv_i32 tcg_op
, tcg_res
;
6257 tcg_op
= read_fp_sreg(s
, rn
);
6258 tcg_res
= tcg_temp_new_i32();
6261 case 0x0: /* FMOV */
6262 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6264 case 0x1: /* FABS */
6265 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6267 case 0x2: /* FNEG */
6268 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6270 case 0x3: /* FSQRT */
6271 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6273 case 0x6: /* BFCVT */
6274 gen_fpst
= gen_helper_bfcvt
;
6276 case 0x8: /* FRINTN */
6277 case 0x9: /* FRINTP */
6278 case 0xa: /* FRINTM */
6279 case 0xb: /* FRINTZ */
6280 case 0xc: /* FRINTA */
6281 rmode
= arm_rmode_to_sf(opcode
& 7);
6282 gen_fpst
= gen_helper_rints
;
6284 case 0xe: /* FRINTX */
6285 gen_fpst
= gen_helper_rints_exact
;
6287 case 0xf: /* FRINTI */
6288 gen_fpst
= gen_helper_rints
;
6290 case 0x10: /* FRINT32Z */
6291 rmode
= float_round_to_zero
;
6292 gen_fpst
= gen_helper_frint32_s
;
6294 case 0x11: /* FRINT32X */
6295 gen_fpst
= gen_helper_frint32_s
;
6297 case 0x12: /* FRINT64Z */
6298 rmode
= float_round_to_zero
;
6299 gen_fpst
= gen_helper_frint64_s
;
6301 case 0x13: /* FRINT64X */
6302 gen_fpst
= gen_helper_frint64_s
;
6305 g_assert_not_reached();
6308 fpst
= fpstatus_ptr(FPST_FPCR
);
6310 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6311 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6312 gen_fpst(tcg_res
, tcg_op
, fpst
);
6313 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6314 tcg_temp_free_i32(tcg_rmode
);
6316 gen_fpst(tcg_res
, tcg_op
, fpst
);
6318 tcg_temp_free_ptr(fpst
);
6321 write_fp_sreg(s
, rd
, tcg_res
);
6322 tcg_temp_free_i32(tcg_op
);
6323 tcg_temp_free_i32(tcg_res
);
6326 /* Floating-point data-processing (1 source) - double precision */
6327 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6329 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6330 TCGv_i64 tcg_op
, tcg_res
;
6335 case 0x0: /* FMOV */
6336 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6340 tcg_op
= read_fp_dreg(s
, rn
);
6341 tcg_res
= tcg_temp_new_i64();
6344 case 0x1: /* FABS */
6345 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6347 case 0x2: /* FNEG */
6348 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6350 case 0x3: /* FSQRT */
6351 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6353 case 0x8: /* FRINTN */
6354 case 0x9: /* FRINTP */
6355 case 0xa: /* FRINTM */
6356 case 0xb: /* FRINTZ */
6357 case 0xc: /* FRINTA */
6358 rmode
= arm_rmode_to_sf(opcode
& 7);
6359 gen_fpst
= gen_helper_rintd
;
6361 case 0xe: /* FRINTX */
6362 gen_fpst
= gen_helper_rintd_exact
;
6364 case 0xf: /* FRINTI */
6365 gen_fpst
= gen_helper_rintd
;
6367 case 0x10: /* FRINT32Z */
6368 rmode
= float_round_to_zero
;
6369 gen_fpst
= gen_helper_frint32_d
;
6371 case 0x11: /* FRINT32X */
6372 gen_fpst
= gen_helper_frint32_d
;
6374 case 0x12: /* FRINT64Z */
6375 rmode
= float_round_to_zero
;
6376 gen_fpst
= gen_helper_frint64_d
;
6378 case 0x13: /* FRINT64X */
6379 gen_fpst
= gen_helper_frint64_d
;
6382 g_assert_not_reached();
6385 fpst
= fpstatus_ptr(FPST_FPCR
);
6387 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6388 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6389 gen_fpst(tcg_res
, tcg_op
, fpst
);
6390 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6391 tcg_temp_free_i32(tcg_rmode
);
6393 gen_fpst(tcg_res
, tcg_op
, fpst
);
6395 tcg_temp_free_ptr(fpst
);
6398 write_fp_dreg(s
, rd
, tcg_res
);
6399 tcg_temp_free_i64(tcg_op
);
6400 tcg_temp_free_i64(tcg_res
);
6403 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6404 int rd
, int rn
, int dtype
, int ntype
)
6409 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6411 /* Single to double */
6412 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6413 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6414 write_fp_dreg(s
, rd
, tcg_rd
);
6415 tcg_temp_free_i64(tcg_rd
);
6417 /* Single to half */
6418 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6419 TCGv_i32 ahp
= get_ahp_flag();
6420 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6422 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6423 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6424 write_fp_sreg(s
, rd
, tcg_rd
);
6425 tcg_temp_free_i32(tcg_rd
);
6426 tcg_temp_free_i32(ahp
);
6427 tcg_temp_free_ptr(fpst
);
6429 tcg_temp_free_i32(tcg_rn
);
6434 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6435 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6437 /* Double to single */
6438 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6440 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6441 TCGv_i32 ahp
= get_ahp_flag();
6442 /* Double to half */
6443 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6444 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6445 tcg_temp_free_ptr(fpst
);
6446 tcg_temp_free_i32(ahp
);
6448 write_fp_sreg(s
, rd
, tcg_rd
);
6449 tcg_temp_free_i32(tcg_rd
);
6450 tcg_temp_free_i64(tcg_rn
);
6455 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6456 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6457 TCGv_i32 tcg_ahp
= get_ahp_flag();
6458 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6460 /* Half to single */
6461 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6462 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6463 write_fp_sreg(s
, rd
, tcg_rd
);
6464 tcg_temp_free_i32(tcg_rd
);
6466 /* Half to double */
6467 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6468 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6469 write_fp_dreg(s
, rd
, tcg_rd
);
6470 tcg_temp_free_i64(tcg_rd
);
6472 tcg_temp_free_i32(tcg_rn
);
6473 tcg_temp_free_ptr(tcg_fpst
);
6474 tcg_temp_free_i32(tcg_ahp
);
6482 /* Floating point data-processing (1 source)
6483 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6484 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6485 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6486 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6488 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6490 int mos
= extract32(insn
, 29, 3);
6491 int type
= extract32(insn
, 22, 2);
6492 int opcode
= extract32(insn
, 15, 6);
6493 int rn
= extract32(insn
, 5, 5);
6494 int rd
= extract32(insn
, 0, 5);
6497 goto do_unallocated
;
6501 case 0x4: case 0x5: case 0x7:
6503 /* FCVT between half, single and double precision */
6504 int dtype
= extract32(opcode
, 0, 2);
6505 if (type
== 2 || dtype
== type
) {
6506 goto do_unallocated
;
6508 if (!fp_access_check(s
)) {
6512 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6516 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6517 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6518 goto do_unallocated
;
6524 /* 32-to-32 and 64-to-64 ops */
6527 if (!fp_access_check(s
)) {
6530 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6533 if (!fp_access_check(s
)) {
6536 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6539 if (!dc_isar_feature(aa64_fp16
, s
)) {
6540 goto do_unallocated
;
6543 if (!fp_access_check(s
)) {
6546 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6549 goto do_unallocated
;
6556 if (!dc_isar_feature(aa64_bf16
, s
)) {
6557 goto do_unallocated
;
6559 if (!fp_access_check(s
)) {
6562 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6565 goto do_unallocated
;
6571 unallocated_encoding(s
);
6576 /* Floating-point data-processing (2 source) - single precision */
6577 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6578 int rd
, int rn
, int rm
)
6585 tcg_res
= tcg_temp_new_i32();
6586 fpst
= fpstatus_ptr(FPST_FPCR
);
6587 tcg_op1
= read_fp_sreg(s
, rn
);
6588 tcg_op2
= read_fp_sreg(s
, rm
);
6591 case 0x0: /* FMUL */
6592 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6594 case 0x1: /* FDIV */
6595 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6597 case 0x2: /* FADD */
6598 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6600 case 0x3: /* FSUB */
6601 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6603 case 0x4: /* FMAX */
6604 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6606 case 0x5: /* FMIN */
6607 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6609 case 0x6: /* FMAXNM */
6610 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6612 case 0x7: /* FMINNM */
6613 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6615 case 0x8: /* FNMUL */
6616 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6617 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6621 write_fp_sreg(s
, rd
, tcg_res
);
6623 tcg_temp_free_ptr(fpst
);
6624 tcg_temp_free_i32(tcg_op1
);
6625 tcg_temp_free_i32(tcg_op2
);
6626 tcg_temp_free_i32(tcg_res
);
6629 /* Floating-point data-processing (2 source) - double precision */
6630 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6631 int rd
, int rn
, int rm
)
6638 tcg_res
= tcg_temp_new_i64();
6639 fpst
= fpstatus_ptr(FPST_FPCR
);
6640 tcg_op1
= read_fp_dreg(s
, rn
);
6641 tcg_op2
= read_fp_dreg(s
, rm
);
6644 case 0x0: /* FMUL */
6645 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6647 case 0x1: /* FDIV */
6648 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6650 case 0x2: /* FADD */
6651 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6653 case 0x3: /* FSUB */
6654 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6656 case 0x4: /* FMAX */
6657 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6659 case 0x5: /* FMIN */
6660 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6662 case 0x6: /* FMAXNM */
6663 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6665 case 0x7: /* FMINNM */
6666 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6668 case 0x8: /* FNMUL */
6669 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6670 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6674 write_fp_dreg(s
, rd
, tcg_res
);
6676 tcg_temp_free_ptr(fpst
);
6677 tcg_temp_free_i64(tcg_op1
);
6678 tcg_temp_free_i64(tcg_op2
);
6679 tcg_temp_free_i64(tcg_res
);
6682 /* Floating-point data-processing (2 source) - half precision */
6683 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6684 int rd
, int rn
, int rm
)
6691 tcg_res
= tcg_temp_new_i32();
6692 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6693 tcg_op1
= read_fp_hreg(s
, rn
);
6694 tcg_op2
= read_fp_hreg(s
, rm
);
6697 case 0x0: /* FMUL */
6698 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6700 case 0x1: /* FDIV */
6701 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6703 case 0x2: /* FADD */
6704 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6706 case 0x3: /* FSUB */
6707 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6709 case 0x4: /* FMAX */
6710 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6712 case 0x5: /* FMIN */
6713 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6715 case 0x6: /* FMAXNM */
6716 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6718 case 0x7: /* FMINNM */
6719 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6721 case 0x8: /* FNMUL */
6722 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6723 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6726 g_assert_not_reached();
6729 write_fp_sreg(s
, rd
, tcg_res
);
6731 tcg_temp_free_ptr(fpst
);
6732 tcg_temp_free_i32(tcg_op1
);
6733 tcg_temp_free_i32(tcg_op2
);
6734 tcg_temp_free_i32(tcg_res
);
6737 /* Floating point data-processing (2 source)
6738 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6739 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6740 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6741 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6743 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6745 int mos
= extract32(insn
, 29, 3);
6746 int type
= extract32(insn
, 22, 2);
6747 int rd
= extract32(insn
, 0, 5);
6748 int rn
= extract32(insn
, 5, 5);
6749 int rm
= extract32(insn
, 16, 5);
6750 int opcode
= extract32(insn
, 12, 4);
6752 if (opcode
> 8 || mos
) {
6753 unallocated_encoding(s
);
6759 if (!fp_access_check(s
)) {
6762 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6765 if (!fp_access_check(s
)) {
6768 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6771 if (!dc_isar_feature(aa64_fp16
, s
)) {
6772 unallocated_encoding(s
);
6775 if (!fp_access_check(s
)) {
6778 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6781 unallocated_encoding(s
);
6785 /* Floating-point data-processing (3 source) - single precision */
6786 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6787 int rd
, int rn
, int rm
, int ra
)
6789 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6790 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6791 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6793 tcg_op1
= read_fp_sreg(s
, rn
);
6794 tcg_op2
= read_fp_sreg(s
, rm
);
6795 tcg_op3
= read_fp_sreg(s
, ra
);
6797 /* These are fused multiply-add, and must be done as one
6798 * floating point operation with no rounding between the
6799 * multiplication and addition steps.
6800 * NB that doing the negations here as separate steps is
6801 * correct : an input NaN should come out with its sign bit
6802 * flipped if it is a negated-input.
6805 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6809 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6812 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6814 write_fp_sreg(s
, rd
, tcg_res
);
6816 tcg_temp_free_ptr(fpst
);
6817 tcg_temp_free_i32(tcg_op1
);
6818 tcg_temp_free_i32(tcg_op2
);
6819 tcg_temp_free_i32(tcg_op3
);
6820 tcg_temp_free_i32(tcg_res
);
6823 /* Floating-point data-processing (3 source) - double precision */
6824 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6825 int rd
, int rn
, int rm
, int ra
)
6827 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6828 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6829 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6831 tcg_op1
= read_fp_dreg(s
, rn
);
6832 tcg_op2
= read_fp_dreg(s
, rm
);
6833 tcg_op3
= read_fp_dreg(s
, ra
);
6835 /* These are fused multiply-add, and must be done as one
6836 * floating point operation with no rounding between the
6837 * multiplication and addition steps.
6838 * NB that doing the negations here as separate steps is
6839 * correct : an input NaN should come out with its sign bit
6840 * flipped if it is a negated-input.
6843 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6847 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6850 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6852 write_fp_dreg(s
, rd
, tcg_res
);
6854 tcg_temp_free_ptr(fpst
);
6855 tcg_temp_free_i64(tcg_op1
);
6856 tcg_temp_free_i64(tcg_op2
);
6857 tcg_temp_free_i64(tcg_op3
);
6858 tcg_temp_free_i64(tcg_res
);
6861 /* Floating-point data-processing (3 source) - half precision */
6862 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6863 int rd
, int rn
, int rm
, int ra
)
6865 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6866 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6867 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6869 tcg_op1
= read_fp_hreg(s
, rn
);
6870 tcg_op2
= read_fp_hreg(s
, rm
);
6871 tcg_op3
= read_fp_hreg(s
, ra
);
6873 /* These are fused multiply-add, and must be done as one
6874 * floating point operation with no rounding between the
6875 * multiplication and addition steps.
6876 * NB that doing the negations here as separate steps is
6877 * correct : an input NaN should come out with its sign bit
6878 * flipped if it is a negated-input.
6881 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6885 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6888 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6890 write_fp_sreg(s
, rd
, tcg_res
);
6892 tcg_temp_free_ptr(fpst
);
6893 tcg_temp_free_i32(tcg_op1
);
6894 tcg_temp_free_i32(tcg_op2
);
6895 tcg_temp_free_i32(tcg_op3
);
6896 tcg_temp_free_i32(tcg_res
);
6899 /* Floating point data-processing (3 source)
6900 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6901 * +---+---+---+-----------+------+----+------+----+------+------+------+
6902 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6903 * +---+---+---+-----------+------+----+------+----+------+------+------+
6905 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6907 int mos
= extract32(insn
, 29, 3);
6908 int type
= extract32(insn
, 22, 2);
6909 int rd
= extract32(insn
, 0, 5);
6910 int rn
= extract32(insn
, 5, 5);
6911 int ra
= extract32(insn
, 10, 5);
6912 int rm
= extract32(insn
, 16, 5);
6913 bool o0
= extract32(insn
, 15, 1);
6914 bool o1
= extract32(insn
, 21, 1);
6917 unallocated_encoding(s
);
6923 if (!fp_access_check(s
)) {
6926 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6929 if (!fp_access_check(s
)) {
6932 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6935 if (!dc_isar_feature(aa64_fp16
, s
)) {
6936 unallocated_encoding(s
);
6939 if (!fp_access_check(s
)) {
6942 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6945 unallocated_encoding(s
);
6949 /* Floating point immediate
6950 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6951 * +---+---+---+-----------+------+---+------------+-------+------+------+
6952 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6953 * +---+---+---+-----------+------+---+------------+-------+------+------+
6955 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6957 int rd
= extract32(insn
, 0, 5);
6958 int imm5
= extract32(insn
, 5, 5);
6959 int imm8
= extract32(insn
, 13, 8);
6960 int type
= extract32(insn
, 22, 2);
6961 int mos
= extract32(insn
, 29, 3);
6967 unallocated_encoding(s
);
6980 if (dc_isar_feature(aa64_fp16
, s
)) {
6985 unallocated_encoding(s
);
6989 if (!fp_access_check(s
)) {
6993 imm
= vfp_expand_imm(sz
, imm8
);
6995 tcg_res
= tcg_const_i64(imm
);
6996 write_fp_dreg(s
, rd
, tcg_res
);
6997 tcg_temp_free_i64(tcg_res
);
7000 /* Handle floating point <=> fixed point conversions. Note that we can
7001 * also deal with fp <=> integer conversions as a special case (scale == 64)
7002 * OPTME: consider handling that special case specially or at least skipping
7003 * the call to scalbn in the helpers for zero shifts.
7005 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
7006 bool itof
, int rmode
, int scale
, int sf
, int type
)
7008 bool is_signed
= !(opcode
& 1);
7009 TCGv_ptr tcg_fpstatus
;
7010 TCGv_i32 tcg_shift
, tcg_single
;
7011 TCGv_i64 tcg_double
;
7013 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
7015 tcg_shift
= tcg_const_i32(64 - scale
);
7018 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
7020 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
7023 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
7025 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
7028 tcg_int
= tcg_extend
;
7032 case 1: /* float64 */
7033 tcg_double
= tcg_temp_new_i64();
7035 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
7036 tcg_shift
, tcg_fpstatus
);
7038 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
7039 tcg_shift
, tcg_fpstatus
);
7041 write_fp_dreg(s
, rd
, tcg_double
);
7042 tcg_temp_free_i64(tcg_double
);
7045 case 0: /* float32 */
7046 tcg_single
= tcg_temp_new_i32();
7048 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
7049 tcg_shift
, tcg_fpstatus
);
7051 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
7052 tcg_shift
, tcg_fpstatus
);
7054 write_fp_sreg(s
, rd
, tcg_single
);
7055 tcg_temp_free_i32(tcg_single
);
7058 case 3: /* float16 */
7059 tcg_single
= tcg_temp_new_i32();
7061 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7062 tcg_shift
, tcg_fpstatus
);
7064 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7065 tcg_shift
, tcg_fpstatus
);
7067 write_fp_sreg(s
, rd
, tcg_single
);
7068 tcg_temp_free_i32(tcg_single
);
7072 g_assert_not_reached();
7075 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7078 if (extract32(opcode
, 2, 1)) {
7079 /* There are too many rounding modes to all fit into rmode,
7080 * so FCVTA[US] is a special case.
7082 rmode
= FPROUNDING_TIEAWAY
;
7085 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7087 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7090 case 1: /* float64 */
7091 tcg_double
= read_fp_dreg(s
, rn
);
7094 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7095 tcg_shift
, tcg_fpstatus
);
7097 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7098 tcg_shift
, tcg_fpstatus
);
7102 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7103 tcg_shift
, tcg_fpstatus
);
7105 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7106 tcg_shift
, tcg_fpstatus
);
7110 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7112 tcg_temp_free_i64(tcg_double
);
7115 case 0: /* float32 */
7116 tcg_single
= read_fp_sreg(s
, rn
);
7119 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7120 tcg_shift
, tcg_fpstatus
);
7122 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7123 tcg_shift
, tcg_fpstatus
);
7126 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7128 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7129 tcg_shift
, tcg_fpstatus
);
7131 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7132 tcg_shift
, tcg_fpstatus
);
7134 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7135 tcg_temp_free_i32(tcg_dest
);
7137 tcg_temp_free_i32(tcg_single
);
7140 case 3: /* float16 */
7141 tcg_single
= read_fp_sreg(s
, rn
);
7144 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7145 tcg_shift
, tcg_fpstatus
);
7147 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7148 tcg_shift
, tcg_fpstatus
);
7151 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7153 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7154 tcg_shift
, tcg_fpstatus
);
7156 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7157 tcg_shift
, tcg_fpstatus
);
7159 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7160 tcg_temp_free_i32(tcg_dest
);
7162 tcg_temp_free_i32(tcg_single
);
7166 g_assert_not_reached();
7169 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7170 tcg_temp_free_i32(tcg_rmode
);
7173 tcg_temp_free_ptr(tcg_fpstatus
);
7174 tcg_temp_free_i32(tcg_shift
);
7177 /* Floating point <-> fixed point conversions
7178 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7179 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7180 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7181 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7183 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7185 int rd
= extract32(insn
, 0, 5);
7186 int rn
= extract32(insn
, 5, 5);
7187 int scale
= extract32(insn
, 10, 6);
7188 int opcode
= extract32(insn
, 16, 3);
7189 int rmode
= extract32(insn
, 19, 2);
7190 int type
= extract32(insn
, 22, 2);
7191 bool sbit
= extract32(insn
, 29, 1);
7192 bool sf
= extract32(insn
, 31, 1);
7195 if (sbit
|| (!sf
&& scale
< 32)) {
7196 unallocated_encoding(s
);
7201 case 0: /* float32 */
7202 case 1: /* float64 */
7204 case 3: /* float16 */
7205 if (dc_isar_feature(aa64_fp16
, s
)) {
7210 unallocated_encoding(s
);
7214 switch ((rmode
<< 3) | opcode
) {
7215 case 0x2: /* SCVTF */
7216 case 0x3: /* UCVTF */
7219 case 0x18: /* FCVTZS */
7220 case 0x19: /* FCVTZU */
7224 unallocated_encoding(s
);
7228 if (!fp_access_check(s
)) {
7232 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7235 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7237 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7238 * without conversion.
7242 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7248 tmp
= tcg_temp_new_i64();
7249 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7250 write_fp_dreg(s
, rd
, tmp
);
7251 tcg_temp_free_i64(tmp
);
7255 write_fp_dreg(s
, rd
, tcg_rn
);
7258 /* 64 bit to top half. */
7259 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7260 clear_vec_high(s
, true, rd
);
7264 tmp
= tcg_temp_new_i64();
7265 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7266 write_fp_dreg(s
, rd
, tmp
);
7267 tcg_temp_free_i64(tmp
);
7270 g_assert_not_reached();
7273 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7278 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7282 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7285 /* 64 bits from top half */
7286 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7290 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7293 g_assert_not_reached();
7298 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7300 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7301 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7303 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7305 tcg_temp_free_ptr(fpstatus
);
7307 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7308 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7309 tcg_gen_movi_i32(cpu_CF
, 0);
7310 tcg_gen_movi_i32(cpu_NF
, 0);
7311 tcg_gen_movi_i32(cpu_VF
, 0);
7313 tcg_temp_free_i64(t
);
7316 /* Floating point <-> integer conversions
7317 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7318 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7319 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7320 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7322 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7324 int rd
= extract32(insn
, 0, 5);
7325 int rn
= extract32(insn
, 5, 5);
7326 int opcode
= extract32(insn
, 16, 3);
7327 int rmode
= extract32(insn
, 19, 2);
7328 int type
= extract32(insn
, 22, 2);
7329 bool sbit
= extract32(insn
, 29, 1);
7330 bool sf
= extract32(insn
, 31, 1);
7334 goto do_unallocated
;
7342 case 4: /* FCVTAS */
7343 case 5: /* FCVTAU */
7345 goto do_unallocated
;
7348 case 0: /* FCVT[NPMZ]S */
7349 case 1: /* FCVT[NPMZ]U */
7351 case 0: /* float32 */
7352 case 1: /* float64 */
7354 case 3: /* float16 */
7355 if (!dc_isar_feature(aa64_fp16
, s
)) {
7356 goto do_unallocated
;
7360 goto do_unallocated
;
7362 if (!fp_access_check(s
)) {
7365 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7369 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7370 case 0b01100110: /* FMOV half <-> 32-bit int */
7372 case 0b11100110: /* FMOV half <-> 64-bit int */
7374 if (!dc_isar_feature(aa64_fp16
, s
)) {
7375 goto do_unallocated
;
7378 case 0b00000110: /* FMOV 32-bit */
7380 case 0b10100110: /* FMOV 64-bit */
7382 case 0b11001110: /* FMOV top half of 128-bit */
7384 if (!fp_access_check(s
)) {
7388 handle_fmov(s
, rd
, rn
, type
, itof
);
7391 case 0b00111110: /* FJCVTZS */
7392 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7393 goto do_unallocated
;
7394 } else if (fp_access_check(s
)) {
7395 handle_fjcvtzs(s
, rd
, rn
);
7401 unallocated_encoding(s
);
7408 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7409 * 31 30 29 28 25 24 0
7410 * +---+---+---+---------+-----------------------------+
7411 * | | 0 | | 1 1 1 1 | |
7412 * +---+---+---+---------+-----------------------------+
7414 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7416 if (extract32(insn
, 24, 1)) {
7417 /* Floating point data-processing (3 source) */
7418 disas_fp_3src(s
, insn
);
7419 } else if (extract32(insn
, 21, 1) == 0) {
7420 /* Floating point to fixed point conversions */
7421 disas_fp_fixed_conv(s
, insn
);
7423 switch (extract32(insn
, 10, 2)) {
7425 /* Floating point conditional compare */
7426 disas_fp_ccomp(s
, insn
);
7429 /* Floating point data-processing (2 source) */
7430 disas_fp_2src(s
, insn
);
7433 /* Floating point conditional select */
7434 disas_fp_csel(s
, insn
);
7437 switch (ctz32(extract32(insn
, 12, 4))) {
7438 case 0: /* [15:12] == xxx1 */
7439 /* Floating point immediate */
7440 disas_fp_imm(s
, insn
);
7442 case 1: /* [15:12] == xx10 */
7443 /* Floating point compare */
7444 disas_fp_compare(s
, insn
);
7446 case 2: /* [15:12] == x100 */
7447 /* Floating point data-processing (1 source) */
7448 disas_fp_1src(s
, insn
);
7450 case 3: /* [15:12] == 1000 */
7451 unallocated_encoding(s
);
7453 default: /* [15:12] == 0000 */
7454 /* Floating point <-> integer conversions */
7455 disas_fp_int_conv(s
, insn
);
7463 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7466 /* Extract 64 bits from the middle of two concatenated 64 bit
7467 * vector register slices left:right. The extracted bits start
7468 * at 'pos' bits into the right (least significant) side.
7469 * We return the result in tcg_right, and guarantee not to
7472 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7473 assert(pos
> 0 && pos
< 64);
7475 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7476 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7477 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7479 tcg_temp_free_i64(tcg_tmp
);
7483 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7484 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7485 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7486 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7488 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7490 int is_q
= extract32(insn
, 30, 1);
7491 int op2
= extract32(insn
, 22, 2);
7492 int imm4
= extract32(insn
, 11, 4);
7493 int rm
= extract32(insn
, 16, 5);
7494 int rn
= extract32(insn
, 5, 5);
7495 int rd
= extract32(insn
, 0, 5);
7496 int pos
= imm4
<< 3;
7497 TCGv_i64 tcg_resl
, tcg_resh
;
7499 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7500 unallocated_encoding(s
);
7504 if (!fp_access_check(s
)) {
7508 tcg_resh
= tcg_temp_new_i64();
7509 tcg_resl
= tcg_temp_new_i64();
7511 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7512 * either extracting 128 bits from a 128:128 concatenation, or
7513 * extracting 64 bits from a 64:64 concatenation.
7516 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7518 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7519 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7527 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7528 EltPosns
*elt
= eltposns
;
7535 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7537 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7540 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7541 tcg_hh
= tcg_temp_new_i64();
7542 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7543 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7544 tcg_temp_free_i64(tcg_hh
);
7548 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7549 tcg_temp_free_i64(tcg_resl
);
7551 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7553 tcg_temp_free_i64(tcg_resh
);
7554 clear_vec_high(s
, is_q
, rd
);
7558 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7559 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7560 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7561 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7563 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7565 int op2
= extract32(insn
, 22, 2);
7566 int is_q
= extract32(insn
, 30, 1);
7567 int rm
= extract32(insn
, 16, 5);
7568 int rn
= extract32(insn
, 5, 5);
7569 int rd
= extract32(insn
, 0, 5);
7570 int is_tbx
= extract32(insn
, 12, 1);
7571 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7574 unallocated_encoding(s
);
7578 if (!fp_access_check(s
)) {
7582 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7583 vec_full_reg_offset(s
, rm
), cpu_env
,
7584 is_q
? 16 : 8, vec_full_reg_size(s
),
7585 (len
<< 6) | (is_tbx
<< 5) | rn
,
7586 gen_helper_simd_tblx
);
7590 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7591 * +---+---+-------------+------+---+------+---+------------------+------+
7592 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7593 * +---+---+-------------+------+---+------+---+------------------+------+
7595 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7597 int rd
= extract32(insn
, 0, 5);
7598 int rn
= extract32(insn
, 5, 5);
7599 int rm
= extract32(insn
, 16, 5);
7600 int size
= extract32(insn
, 22, 2);
7601 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7602 * bit 2 indicates 1 vs 2 variant of the insn.
7604 int opcode
= extract32(insn
, 12, 2);
7605 bool part
= extract32(insn
, 14, 1);
7606 bool is_q
= extract32(insn
, 30, 1);
7607 int esize
= 8 << size
;
7609 int datasize
= is_q
? 128 : 64;
7610 int elements
= datasize
/ esize
;
7611 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7613 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7614 unallocated_encoding(s
);
7618 if (!fp_access_check(s
)) {
7622 tcg_resl
= tcg_const_i64(0);
7623 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7624 tcg_res
= tcg_temp_new_i64();
7626 for (i
= 0; i
< elements
; i
++) {
7628 case 1: /* UZP1/2 */
7630 int midpoint
= elements
/ 2;
7632 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7634 read_vec_element(s
, tcg_res
, rm
,
7635 2 * (i
- midpoint
) + part
, size
);
7639 case 2: /* TRN1/2 */
7641 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7643 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7646 case 3: /* ZIP1/2 */
7648 int base
= part
* elements
/ 2;
7650 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7652 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7657 g_assert_not_reached();
7662 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7663 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7665 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7666 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7670 tcg_temp_free_i64(tcg_res
);
7672 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7673 tcg_temp_free_i64(tcg_resl
);
7676 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7677 tcg_temp_free_i64(tcg_resh
);
7679 clear_vec_high(s
, is_q
, rd
);
7683 * do_reduction_op helper
7685 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7686 * important for correct NaN propagation that we do these
7687 * operations in exactly the order specified by the pseudocode.
7689 * This is a recursive function, TCG temps should be freed by the
7690 * calling function once it is done with the values.
7692 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7693 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7695 if (esize
== size
) {
7697 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7700 /* We should have one register left here */
7701 assert(ctpop8(vmap
) == 1);
7702 element
= ctz32(vmap
);
7703 assert(element
< 8);
7705 tcg_elem
= tcg_temp_new_i32();
7706 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7709 int bits
= size
/ 2;
7710 int shift
= ctpop8(vmap
) / 2;
7711 int vmap_lo
= (vmap
>> shift
) & vmap
;
7712 int vmap_hi
= (vmap
& ~vmap_lo
);
7713 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7715 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7716 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7717 tcg_res
= tcg_temp_new_i32();
7720 case 0x0c: /* fmaxnmv half-precision */
7721 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7723 case 0x0f: /* fmaxv half-precision */
7724 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7726 case 0x1c: /* fminnmv half-precision */
7727 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7729 case 0x1f: /* fminv half-precision */
7730 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7732 case 0x2c: /* fmaxnmv */
7733 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7735 case 0x2f: /* fmaxv */
7736 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7738 case 0x3c: /* fminnmv */
7739 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7741 case 0x3f: /* fminv */
7742 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7745 g_assert_not_reached();
7748 tcg_temp_free_i32(tcg_hi
);
7749 tcg_temp_free_i32(tcg_lo
);
7754 /* AdvSIMD across lanes
7755 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7756 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7757 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7758 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7760 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7762 int rd
= extract32(insn
, 0, 5);
7763 int rn
= extract32(insn
, 5, 5);
7764 int size
= extract32(insn
, 22, 2);
7765 int opcode
= extract32(insn
, 12, 5);
7766 bool is_q
= extract32(insn
, 30, 1);
7767 bool is_u
= extract32(insn
, 29, 1);
7769 bool is_min
= false;
7773 TCGv_i64 tcg_res
, tcg_elt
;
7776 case 0x1b: /* ADDV */
7778 unallocated_encoding(s
);
7782 case 0x3: /* SADDLV, UADDLV */
7783 case 0xa: /* SMAXV, UMAXV */
7784 case 0x1a: /* SMINV, UMINV */
7785 if (size
== 3 || (size
== 2 && !is_q
)) {
7786 unallocated_encoding(s
);
7790 case 0xc: /* FMAXNMV, FMINNMV */
7791 case 0xf: /* FMAXV, FMINV */
7792 /* Bit 1 of size field encodes min vs max and the actual size
7793 * depends on the encoding of the U bit. If not set (and FP16
7794 * enabled) then we do half-precision float instead of single
7797 is_min
= extract32(size
, 1, 1);
7799 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7801 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7802 unallocated_encoding(s
);
7809 unallocated_encoding(s
);
7813 if (!fp_access_check(s
)) {
7818 elements
= (is_q
? 128 : 64) / esize
;
7820 tcg_res
= tcg_temp_new_i64();
7821 tcg_elt
= tcg_temp_new_i64();
7823 /* These instructions operate across all lanes of a vector
7824 * to produce a single result. We can guarantee that a 64
7825 * bit intermediate is sufficient:
7826 * + for [US]ADDLV the maximum element size is 32 bits, and
7827 * the result type is 64 bits
7828 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7829 * same as the element size, which is 32 bits at most
7830 * For the integer operations we can choose to work at 64
7831 * or 32 bits and truncate at the end; for simplicity
7832 * we use 64 bits always. The floating point
7833 * ops do require 32 bit intermediates, though.
7836 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7838 for (i
= 1; i
< elements
; i
++) {
7839 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7842 case 0x03: /* SADDLV / UADDLV */
7843 case 0x1b: /* ADDV */
7844 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7846 case 0x0a: /* SMAXV / UMAXV */
7848 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7850 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7853 case 0x1a: /* SMINV / UMINV */
7855 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7857 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7861 g_assert_not_reached();
7866 /* Floating point vector reduction ops which work across 32
7867 * bit (single) or 16 bit (half-precision) intermediates.
7868 * Note that correct NaN propagation requires that we do these
7869 * operations in exactly the order specified by the pseudocode.
7871 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7872 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7873 int vmap
= (1 << elements
) - 1;
7874 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7875 (is_q
? 128 : 64), vmap
, fpst
);
7876 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7877 tcg_temp_free_i32(tcg_res32
);
7878 tcg_temp_free_ptr(fpst
);
7881 tcg_temp_free_i64(tcg_elt
);
7883 /* Now truncate the result to the width required for the final output */
7884 if (opcode
== 0x03) {
7885 /* SADDLV, UADDLV: result is 2*esize */
7891 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7894 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7897 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7902 g_assert_not_reached();
7905 write_fp_dreg(s
, rd
, tcg_res
);
7906 tcg_temp_free_i64(tcg_res
);
7909 /* DUP (Element, Vector)
7911 * 31 30 29 21 20 16 15 10 9 5 4 0
7912 * +---+---+-------------------+--------+-------------+------+------+
7913 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7914 * +---+---+-------------------+--------+-------------+------+------+
7916 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7918 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7921 int size
= ctz32(imm5
);
7924 if (size
> 3 || (size
== 3 && !is_q
)) {
7925 unallocated_encoding(s
);
7929 if (!fp_access_check(s
)) {
7933 index
= imm5
>> (size
+ 1);
7934 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7935 vec_reg_offset(s
, rn
, index
, size
),
7936 is_q
? 16 : 8, vec_full_reg_size(s
));
7939 /* DUP (element, scalar)
7940 * 31 21 20 16 15 10 9 5 4 0
7941 * +-----------------------+--------+-------------+------+------+
7942 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7943 * +-----------------------+--------+-------------+------+------+
7945 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7948 int size
= ctz32(imm5
);
7953 unallocated_encoding(s
);
7957 if (!fp_access_check(s
)) {
7961 index
= imm5
>> (size
+ 1);
7963 /* This instruction just extracts the specified element and
7964 * zero-extends it into the bottom of the destination register.
7966 tmp
= tcg_temp_new_i64();
7967 read_vec_element(s
, tmp
, rn
, index
, size
);
7968 write_fp_dreg(s
, rd
, tmp
);
7969 tcg_temp_free_i64(tmp
);
7974 * 31 30 29 21 20 16 15 10 9 5 4 0
7975 * +---+---+-------------------+--------+-------------+------+------+
7976 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7977 * +---+---+-------------------+--------+-------------+------+------+
7979 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7981 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7984 int size
= ctz32(imm5
);
7985 uint32_t dofs
, oprsz
, maxsz
;
7987 if (size
> 3 || ((size
== 3) && !is_q
)) {
7988 unallocated_encoding(s
);
7992 if (!fp_access_check(s
)) {
7996 dofs
= vec_full_reg_offset(s
, rd
);
7997 oprsz
= is_q
? 16 : 8;
7998 maxsz
= vec_full_reg_size(s
);
8000 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
8005 * 31 21 20 16 15 14 11 10 9 5 4 0
8006 * +-----------------------+--------+------------+---+------+------+
8007 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8008 * +-----------------------+--------+------------+---+------+------+
8010 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8011 * index: encoded in imm5<4:size+1>
8013 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
8016 int size
= ctz32(imm5
);
8017 int src_index
, dst_index
;
8021 unallocated_encoding(s
);
8025 if (!fp_access_check(s
)) {
8029 dst_index
= extract32(imm5
, 1+size
, 5);
8030 src_index
= extract32(imm4
, size
, 4);
8032 tmp
= tcg_temp_new_i64();
8034 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8035 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8037 tcg_temp_free_i64(tmp
);
8039 /* INS is considered a 128-bit write for SVE. */
8040 clear_vec_high(s
, true, rd
);
8046 * 31 21 20 16 15 10 9 5 4 0
8047 * +-----------------------+--------+-------------+------+------+
8048 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8049 * +-----------------------+--------+-------------+------+------+
8051 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8052 * index: encoded in imm5<4:size+1>
8054 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8056 int size
= ctz32(imm5
);
8060 unallocated_encoding(s
);
8064 if (!fp_access_check(s
)) {
8068 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8069 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8071 /* INS is considered a 128-bit write for SVE. */
8072 clear_vec_high(s
, true, rd
);
8079 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8080 * +---+---+-------------------+--------+-------------+------+------+
8081 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8082 * +---+---+-------------------+--------+-------------+------+------+
8084 * U: unsigned when set
8085 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8087 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8088 int rn
, int rd
, int imm5
)
8090 int size
= ctz32(imm5
);
8094 /* Check for UnallocatedEncodings */
8096 if (size
> 2 || (size
== 2 && !is_q
)) {
8097 unallocated_encoding(s
);
8102 || (size
< 3 && is_q
)
8103 || (size
== 3 && !is_q
)) {
8104 unallocated_encoding(s
);
8109 if (!fp_access_check(s
)) {
8113 element
= extract32(imm5
, 1+size
, 4);
8115 tcg_rd
= cpu_reg(s
, rd
);
8116 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8117 if (is_signed
&& !is_q
) {
8118 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8123 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8124 * +---+---+----+-----------------+------+---+------+---+------+------+
8125 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8126 * +---+---+----+-----------------+------+---+------+---+------+------+
8128 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8130 int rd
= extract32(insn
, 0, 5);
8131 int rn
= extract32(insn
, 5, 5);
8132 int imm4
= extract32(insn
, 11, 4);
8133 int op
= extract32(insn
, 29, 1);
8134 int is_q
= extract32(insn
, 30, 1);
8135 int imm5
= extract32(insn
, 16, 5);
8140 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8142 unallocated_encoding(s
);
8147 /* DUP (element - vector) */
8148 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8152 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8157 handle_simd_insg(s
, rd
, rn
, imm5
);
8159 unallocated_encoding(s
);
8164 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8165 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8168 unallocated_encoding(s
);
8174 /* AdvSIMD modified immediate
8175 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8176 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8177 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8178 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8180 * There are a number of operations that can be carried out here:
8181 * MOVI - move (shifted) imm into register
8182 * MVNI - move inverted (shifted) imm into register
8183 * ORR - bitwise OR of (shifted) imm with register
8184 * BIC - bitwise clear of (shifted) imm with register
8185 * With ARMv8.2 we also have:
8186 * FMOV half-precision
8188 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8190 int rd
= extract32(insn
, 0, 5);
8191 int cmode
= extract32(insn
, 12, 4);
8192 int o2
= extract32(insn
, 11, 1);
8193 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8194 bool is_neg
= extract32(insn
, 29, 1);
8195 bool is_q
= extract32(insn
, 30, 1);
8198 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8199 /* Check for FMOV (vector, immediate) - half-precision */
8200 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8201 unallocated_encoding(s
);
8206 if (!fp_access_check(s
)) {
8210 if (cmode
== 15 && o2
&& !is_neg
) {
8211 /* FMOV (vector, immediate) - half-precision */
8212 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8213 /* now duplicate across the lanes */
8214 imm
= dup_const(MO_16
, imm
);
8216 imm
= asimd_imm_const(abcdefgh
, cmode
, is_neg
);
8219 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8220 /* MOVI or MVNI, with MVNI negation handled above. */
8221 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8222 vec_full_reg_size(s
), imm
);
8224 /* ORR or BIC, with BIC negation to AND handled above. */
8226 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8228 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8233 /* AdvSIMD scalar copy
8234 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8235 * +-----+----+-----------------+------+---+------+---+------+------+
8236 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8237 * +-----+----+-----------------+------+---+------+---+------+------+
8239 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8241 int rd
= extract32(insn
, 0, 5);
8242 int rn
= extract32(insn
, 5, 5);
8243 int imm4
= extract32(insn
, 11, 4);
8244 int imm5
= extract32(insn
, 16, 5);
8245 int op
= extract32(insn
, 29, 1);
8247 if (op
!= 0 || imm4
!= 0) {
8248 unallocated_encoding(s
);
8252 /* DUP (element, scalar) */
8253 handle_simd_dupes(s
, rd
, rn
, imm5
);
8256 /* AdvSIMD scalar pairwise
8257 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8258 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8259 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8260 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8262 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8264 int u
= extract32(insn
, 29, 1);
8265 int size
= extract32(insn
, 22, 2);
8266 int opcode
= extract32(insn
, 12, 5);
8267 int rn
= extract32(insn
, 5, 5);
8268 int rd
= extract32(insn
, 0, 5);
8271 /* For some ops (the FP ones), size[1] is part of the encoding.
8272 * For ADDP strictly it is not but size[1] is always 1 for valid
8275 opcode
|= (extract32(size
, 1, 1) << 5);
8278 case 0x3b: /* ADDP */
8279 if (u
|| size
!= 3) {
8280 unallocated_encoding(s
);
8283 if (!fp_access_check(s
)) {
8289 case 0xc: /* FMAXNMP */
8290 case 0xd: /* FADDP */
8291 case 0xf: /* FMAXP */
8292 case 0x2c: /* FMINNMP */
8293 case 0x2f: /* FMINP */
8294 /* FP op, size[0] is 32 or 64 bit*/
8296 if (!dc_isar_feature(aa64_fp16
, s
)) {
8297 unallocated_encoding(s
);
8303 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8306 if (!fp_access_check(s
)) {
8310 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8313 unallocated_encoding(s
);
8317 if (size
== MO_64
) {
8318 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8319 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8320 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8322 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8323 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8326 case 0x3b: /* ADDP */
8327 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8329 case 0xc: /* FMAXNMP */
8330 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8332 case 0xd: /* FADDP */
8333 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8335 case 0xf: /* FMAXP */
8336 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8338 case 0x2c: /* FMINNMP */
8339 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8341 case 0x2f: /* FMINP */
8342 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8345 g_assert_not_reached();
8348 write_fp_dreg(s
, rd
, tcg_res
);
8350 tcg_temp_free_i64(tcg_op1
);
8351 tcg_temp_free_i64(tcg_op2
);
8352 tcg_temp_free_i64(tcg_res
);
8354 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8355 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8356 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8358 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8359 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8361 if (size
== MO_16
) {
8363 case 0xc: /* FMAXNMP */
8364 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8366 case 0xd: /* FADDP */
8367 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8369 case 0xf: /* FMAXP */
8370 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8372 case 0x2c: /* FMINNMP */
8373 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8375 case 0x2f: /* FMINP */
8376 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8379 g_assert_not_reached();
8383 case 0xc: /* FMAXNMP */
8384 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8386 case 0xd: /* FADDP */
8387 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8389 case 0xf: /* FMAXP */
8390 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8392 case 0x2c: /* FMINNMP */
8393 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8395 case 0x2f: /* FMINP */
8396 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8399 g_assert_not_reached();
8403 write_fp_sreg(s
, rd
, tcg_res
);
8405 tcg_temp_free_i32(tcg_op1
);
8406 tcg_temp_free_i32(tcg_op2
);
8407 tcg_temp_free_i32(tcg_res
);
8411 tcg_temp_free_ptr(fpst
);
8416 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8418 * This code is handles the common shifting code and is used by both
8419 * the vector and scalar code.
8421 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8422 TCGv_i64 tcg_rnd
, bool accumulate
,
8423 bool is_u
, int size
, int shift
)
8425 bool extended_result
= false;
8426 bool round
= tcg_rnd
!= NULL
;
8428 TCGv_i64 tcg_src_hi
;
8430 if (round
&& size
== 3) {
8431 extended_result
= true;
8432 ext_lshift
= 64 - shift
;
8433 tcg_src_hi
= tcg_temp_new_i64();
8434 } else if (shift
== 64) {
8435 if (!accumulate
&& is_u
) {
8436 /* result is zero */
8437 tcg_gen_movi_i64(tcg_res
, 0);
8442 /* Deal with the rounding step */
8444 if (extended_result
) {
8445 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8447 /* take care of sign extending tcg_res */
8448 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8449 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8450 tcg_src
, tcg_src_hi
,
8453 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8457 tcg_temp_free_i64(tcg_zero
);
8459 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8463 /* Now do the shift right */
8464 if (round
&& extended_result
) {
8465 /* extended case, >64 bit precision required */
8466 if (ext_lshift
== 0) {
8467 /* special case, only high bits matter */
8468 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8470 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8471 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8472 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8477 /* essentially shifting in 64 zeros */
8478 tcg_gen_movi_i64(tcg_src
, 0);
8480 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8484 /* effectively extending the sign-bit */
8485 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8487 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8493 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8495 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8498 if (extended_result
) {
8499 tcg_temp_free_i64(tcg_src_hi
);
8503 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8504 static void handle_scalar_simd_shri(DisasContext
*s
,
8505 bool is_u
, int immh
, int immb
,
8506 int opcode
, int rn
, int rd
)
8509 int immhb
= immh
<< 3 | immb
;
8510 int shift
= 2 * (8 << size
) - immhb
;
8511 bool accumulate
= false;
8513 bool insert
= false;
8518 if (!extract32(immh
, 3, 1)) {
8519 unallocated_encoding(s
);
8523 if (!fp_access_check(s
)) {
8528 case 0x02: /* SSRA / USRA (accumulate) */
8531 case 0x04: /* SRSHR / URSHR (rounding) */
8534 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8535 accumulate
= round
= true;
8537 case 0x08: /* SRI */
8543 uint64_t round_const
= 1ULL << (shift
- 1);
8544 tcg_round
= tcg_const_i64(round_const
);
8549 tcg_rn
= read_fp_dreg(s
, rn
);
8550 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8553 /* shift count same as element size is valid but does nothing;
8554 * special case to avoid potential shift by 64.
8556 int esize
= 8 << size
;
8557 if (shift
!= esize
) {
8558 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8559 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8562 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8563 accumulate
, is_u
, size
, shift
);
8566 write_fp_dreg(s
, rd
, tcg_rd
);
8568 tcg_temp_free_i64(tcg_rn
);
8569 tcg_temp_free_i64(tcg_rd
);
8571 tcg_temp_free_i64(tcg_round
);
8575 /* SHL/SLI - Scalar shift left */
8576 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8577 int immh
, int immb
, int opcode
,
8580 int size
= 32 - clz32(immh
) - 1;
8581 int immhb
= immh
<< 3 | immb
;
8582 int shift
= immhb
- (8 << size
);
8586 if (!extract32(immh
, 3, 1)) {
8587 unallocated_encoding(s
);
8591 if (!fp_access_check(s
)) {
8595 tcg_rn
= read_fp_dreg(s
, rn
);
8596 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8599 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8601 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8604 write_fp_dreg(s
, rd
, tcg_rd
);
8606 tcg_temp_free_i64(tcg_rn
);
8607 tcg_temp_free_i64(tcg_rd
);
8610 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8611 * (signed/unsigned) narrowing */
8612 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8613 bool is_u_shift
, bool is_u_narrow
,
8614 int immh
, int immb
, int opcode
,
8617 int immhb
= immh
<< 3 | immb
;
8618 int size
= 32 - clz32(immh
) - 1;
8619 int esize
= 8 << size
;
8620 int shift
= (2 * esize
) - immhb
;
8621 int elements
= is_scalar
? 1 : (64 / esize
);
8622 bool round
= extract32(opcode
, 0, 1);
8623 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8624 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8625 TCGv_i32 tcg_rd_narrowed
;
8628 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8629 { gen_helper_neon_narrow_sat_s8
,
8630 gen_helper_neon_unarrow_sat8
},
8631 { gen_helper_neon_narrow_sat_s16
,
8632 gen_helper_neon_unarrow_sat16
},
8633 { gen_helper_neon_narrow_sat_s32
,
8634 gen_helper_neon_unarrow_sat32
},
8637 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8638 gen_helper_neon_narrow_sat_u8
,
8639 gen_helper_neon_narrow_sat_u16
,
8640 gen_helper_neon_narrow_sat_u32
,
8643 NeonGenNarrowEnvFn
*narrowfn
;
8649 if (extract32(immh
, 3, 1)) {
8650 unallocated_encoding(s
);
8654 if (!fp_access_check(s
)) {
8659 narrowfn
= unsigned_narrow_fns
[size
];
8661 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8664 tcg_rn
= tcg_temp_new_i64();
8665 tcg_rd
= tcg_temp_new_i64();
8666 tcg_rd_narrowed
= tcg_temp_new_i32();
8667 tcg_final
= tcg_const_i64(0);
8670 uint64_t round_const
= 1ULL << (shift
- 1);
8671 tcg_round
= tcg_const_i64(round_const
);
8676 for (i
= 0; i
< elements
; i
++) {
8677 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8678 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8679 false, is_u_shift
, size
+1, shift
);
8680 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8681 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8682 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8686 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8688 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8692 tcg_temp_free_i64(tcg_round
);
8694 tcg_temp_free_i64(tcg_rn
);
8695 tcg_temp_free_i64(tcg_rd
);
8696 tcg_temp_free_i32(tcg_rd_narrowed
);
8697 tcg_temp_free_i64(tcg_final
);
8699 clear_vec_high(s
, is_q
, rd
);
8702 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8703 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8704 bool src_unsigned
, bool dst_unsigned
,
8705 int immh
, int immb
, int rn
, int rd
)
8707 int immhb
= immh
<< 3 | immb
;
8708 int size
= 32 - clz32(immh
) - 1;
8709 int shift
= immhb
- (8 << size
);
8713 assert(!(scalar
&& is_q
));
8716 if (!is_q
&& extract32(immh
, 3, 1)) {
8717 unallocated_encoding(s
);
8721 /* Since we use the variable-shift helpers we must
8722 * replicate the shift count into each element of
8723 * the tcg_shift value.
8727 shift
|= shift
<< 8;
8730 shift
|= shift
<< 16;
8736 g_assert_not_reached();
8740 if (!fp_access_check(s
)) {
8745 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8746 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8747 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8748 { NULL
, gen_helper_neon_qshl_u64
},
8750 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8751 int maxpass
= is_q
? 2 : 1;
8753 for (pass
= 0; pass
< maxpass
; pass
++) {
8754 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8756 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8757 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8758 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8760 tcg_temp_free_i64(tcg_op
);
8762 tcg_temp_free_i64(tcg_shift
);
8763 clear_vec_high(s
, is_q
, rd
);
8765 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8766 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8768 { gen_helper_neon_qshl_s8
,
8769 gen_helper_neon_qshl_s16
,
8770 gen_helper_neon_qshl_s32
},
8771 { gen_helper_neon_qshlu_s8
,
8772 gen_helper_neon_qshlu_s16
,
8773 gen_helper_neon_qshlu_s32
}
8775 { NULL
, NULL
, NULL
},
8776 { gen_helper_neon_qshl_u8
,
8777 gen_helper_neon_qshl_u16
,
8778 gen_helper_neon_qshl_u32
}
8781 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8782 MemOp memop
= scalar
? size
: MO_32
;
8783 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8785 for (pass
= 0; pass
< maxpass
; pass
++) {
8786 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8788 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8789 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8793 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8796 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8801 g_assert_not_reached();
8803 write_fp_sreg(s
, rd
, tcg_op
);
8805 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8808 tcg_temp_free_i32(tcg_op
);
8810 tcg_temp_free_i32(tcg_shift
);
8813 clear_vec_high(s
, is_q
, rd
);
8818 /* Common vector code for handling integer to FP conversion */
8819 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8820 int elements
, int is_signed
,
8821 int fracbits
, int size
)
8823 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8824 TCGv_i32 tcg_shift
= NULL
;
8826 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8829 if (fracbits
|| size
== MO_64
) {
8830 tcg_shift
= tcg_const_i32(fracbits
);
8833 if (size
== MO_64
) {
8834 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8835 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8837 for (pass
= 0; pass
< elements
; pass
++) {
8838 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8841 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8842 tcg_shift
, tcg_fpst
);
8844 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8845 tcg_shift
, tcg_fpst
);
8847 if (elements
== 1) {
8848 write_fp_dreg(s
, rd
, tcg_double
);
8850 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8854 tcg_temp_free_i64(tcg_int64
);
8855 tcg_temp_free_i64(tcg_double
);
8858 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8859 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8861 for (pass
= 0; pass
< elements
; pass
++) {
8862 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8868 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8869 tcg_shift
, tcg_fpst
);
8871 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8872 tcg_shift
, tcg_fpst
);
8876 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8878 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8885 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8886 tcg_shift
, tcg_fpst
);
8888 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8889 tcg_shift
, tcg_fpst
);
8893 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8895 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8900 g_assert_not_reached();
8903 if (elements
== 1) {
8904 write_fp_sreg(s
, rd
, tcg_float
);
8906 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8910 tcg_temp_free_i32(tcg_int32
);
8911 tcg_temp_free_i32(tcg_float
);
8914 tcg_temp_free_ptr(tcg_fpst
);
8916 tcg_temp_free_i32(tcg_shift
);
8919 clear_vec_high(s
, elements
<< size
== 16, rd
);
8922 /* UCVTF/SCVTF - Integer to FP conversion */
8923 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8924 bool is_q
, bool is_u
,
8925 int immh
, int immb
, int opcode
,
8928 int size
, elements
, fracbits
;
8929 int immhb
= immh
<< 3 | immb
;
8933 if (!is_scalar
&& !is_q
) {
8934 unallocated_encoding(s
);
8937 } else if (immh
& 4) {
8939 } else if (immh
& 2) {
8941 if (!dc_isar_feature(aa64_fp16
, s
)) {
8942 unallocated_encoding(s
);
8946 /* immh == 0 would be a failure of the decode logic */
8947 g_assert(immh
== 1);
8948 unallocated_encoding(s
);
8955 elements
= (8 << is_q
) >> size
;
8957 fracbits
= (16 << size
) - immhb
;
8959 if (!fp_access_check(s
)) {
8963 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8966 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8967 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8968 bool is_q
, bool is_u
,
8969 int immh
, int immb
, int rn
, int rd
)
8971 int immhb
= immh
<< 3 | immb
;
8972 int pass
, size
, fracbits
;
8973 TCGv_ptr tcg_fpstatus
;
8974 TCGv_i32 tcg_rmode
, tcg_shift
;
8978 if (!is_scalar
&& !is_q
) {
8979 unallocated_encoding(s
);
8982 } else if (immh
& 0x4) {
8984 } else if (immh
& 0x2) {
8986 if (!dc_isar_feature(aa64_fp16
, s
)) {
8987 unallocated_encoding(s
);
8991 /* Should have split out AdvSIMD modified immediate earlier. */
8993 unallocated_encoding(s
);
8997 if (!fp_access_check(s
)) {
9001 assert(!(is_scalar
&& is_q
));
9003 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9004 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9005 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9006 fracbits
= (16 << size
) - immhb
;
9007 tcg_shift
= tcg_const_i32(fracbits
);
9009 if (size
== MO_64
) {
9010 int maxpass
= is_scalar
? 1 : 2;
9012 for (pass
= 0; pass
< maxpass
; pass
++) {
9013 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9015 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9017 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9019 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9021 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9022 tcg_temp_free_i64(tcg_op
);
9024 clear_vec_high(s
, is_q
, rd
);
9026 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9027 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9032 fn
= gen_helper_vfp_touhh
;
9034 fn
= gen_helper_vfp_toshh
;
9039 fn
= gen_helper_vfp_touls
;
9041 fn
= gen_helper_vfp_tosls
;
9045 g_assert_not_reached();
9048 for (pass
= 0; pass
< maxpass
; pass
++) {
9049 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9051 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9052 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9054 write_fp_sreg(s
, rd
, tcg_op
);
9056 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9058 tcg_temp_free_i32(tcg_op
);
9061 clear_vec_high(s
, is_q
, rd
);
9065 tcg_temp_free_ptr(tcg_fpstatus
);
9066 tcg_temp_free_i32(tcg_shift
);
9067 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9068 tcg_temp_free_i32(tcg_rmode
);
9071 /* AdvSIMD scalar shift by immediate
9072 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9073 * +-----+---+-------------+------+------+--------+---+------+------+
9074 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9075 * +-----+---+-------------+------+------+--------+---+------+------+
9077 * This is the scalar version so it works on a fixed sized registers
9079 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9081 int rd
= extract32(insn
, 0, 5);
9082 int rn
= extract32(insn
, 5, 5);
9083 int opcode
= extract32(insn
, 11, 5);
9084 int immb
= extract32(insn
, 16, 3);
9085 int immh
= extract32(insn
, 19, 4);
9086 bool is_u
= extract32(insn
, 29, 1);
9089 unallocated_encoding(s
);
9094 case 0x08: /* SRI */
9096 unallocated_encoding(s
);
9100 case 0x00: /* SSHR / USHR */
9101 case 0x02: /* SSRA / USRA */
9102 case 0x04: /* SRSHR / URSHR */
9103 case 0x06: /* SRSRA / URSRA */
9104 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9106 case 0x0a: /* SHL / SLI */
9107 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9109 case 0x1c: /* SCVTF, UCVTF */
9110 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9113 case 0x10: /* SQSHRUN, SQSHRUN2 */
9114 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9116 unallocated_encoding(s
);
9119 handle_vec_simd_sqshrn(s
, true, false, false, true,
9120 immh
, immb
, opcode
, rn
, rd
);
9122 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9123 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9124 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9125 immh
, immb
, opcode
, rn
, rd
);
9127 case 0xc: /* SQSHLU */
9129 unallocated_encoding(s
);
9132 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9134 case 0xe: /* SQSHL, UQSHL */
9135 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9137 case 0x1f: /* FCVTZS, FCVTZU */
9138 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9141 unallocated_encoding(s
);
9146 /* AdvSIMD scalar three different
9147 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9148 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9149 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9150 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9152 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9154 bool is_u
= extract32(insn
, 29, 1);
9155 int size
= extract32(insn
, 22, 2);
9156 int opcode
= extract32(insn
, 12, 4);
9157 int rm
= extract32(insn
, 16, 5);
9158 int rn
= extract32(insn
, 5, 5);
9159 int rd
= extract32(insn
, 0, 5);
9162 unallocated_encoding(s
);
9167 case 0x9: /* SQDMLAL, SQDMLAL2 */
9168 case 0xb: /* SQDMLSL, SQDMLSL2 */
9169 case 0xd: /* SQDMULL, SQDMULL2 */
9170 if (size
== 0 || size
== 3) {
9171 unallocated_encoding(s
);
9176 unallocated_encoding(s
);
9180 if (!fp_access_check(s
)) {
9185 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9186 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9187 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9189 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9190 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9192 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9193 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9196 case 0xd: /* SQDMULL, SQDMULL2 */
9198 case 0xb: /* SQDMLSL, SQDMLSL2 */
9199 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9201 case 0x9: /* SQDMLAL, SQDMLAL2 */
9202 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9203 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9207 g_assert_not_reached();
9210 write_fp_dreg(s
, rd
, tcg_res
);
9212 tcg_temp_free_i64(tcg_op1
);
9213 tcg_temp_free_i64(tcg_op2
);
9214 tcg_temp_free_i64(tcg_res
);
9216 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9217 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9218 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9220 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9221 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9224 case 0xd: /* SQDMULL, SQDMULL2 */
9226 case 0xb: /* SQDMLSL, SQDMLSL2 */
9227 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9229 case 0x9: /* SQDMLAL, SQDMLAL2 */
9231 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9232 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9233 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9235 tcg_temp_free_i64(tcg_op3
);
9239 g_assert_not_reached();
9242 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9243 write_fp_dreg(s
, rd
, tcg_res
);
9245 tcg_temp_free_i32(tcg_op1
);
9246 tcg_temp_free_i32(tcg_op2
);
9247 tcg_temp_free_i64(tcg_res
);
9251 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9252 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9254 /* Handle 64x64->64 opcodes which are shared between the scalar
9255 * and vector 3-same groups. We cover every opcode where size == 3
9256 * is valid in either the three-reg-same (integer, not pairwise)
9257 * or scalar-three-reg-same groups.
9262 case 0x1: /* SQADD */
9264 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9266 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9269 case 0x5: /* SQSUB */
9271 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9273 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9276 case 0x6: /* CMGT, CMHI */
9277 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9278 * We implement this using setcond (test) and then negating.
9280 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9282 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9283 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9285 case 0x7: /* CMGE, CMHS */
9286 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9288 case 0x11: /* CMTST, CMEQ */
9293 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9295 case 0x8: /* SSHL, USHL */
9297 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9299 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9302 case 0x9: /* SQSHL, UQSHL */
9304 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9306 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9309 case 0xa: /* SRSHL, URSHL */
9311 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9313 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9316 case 0xb: /* SQRSHL, UQRSHL */
9318 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9320 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9323 case 0x10: /* ADD, SUB */
9325 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9327 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9331 g_assert_not_reached();
9335 /* Handle the 3-same-operands float operations; shared by the scalar
9336 * and vector encodings. The caller must filter out any encodings
9337 * not allocated for the encoding it is dealing with.
9339 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9340 int fpopcode
, int rd
, int rn
, int rm
)
9343 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9345 for (pass
= 0; pass
< elements
; pass
++) {
9348 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9349 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9350 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9352 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9353 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9356 case 0x39: /* FMLS */
9357 /* As usual for ARM, separate negation for fused multiply-add */
9358 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9360 case 0x19: /* FMLA */
9361 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9362 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9365 case 0x18: /* FMAXNM */
9366 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9368 case 0x1a: /* FADD */
9369 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9371 case 0x1b: /* FMULX */
9372 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9374 case 0x1c: /* FCMEQ */
9375 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9377 case 0x1e: /* FMAX */
9378 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9380 case 0x1f: /* FRECPS */
9381 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9383 case 0x38: /* FMINNM */
9384 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9386 case 0x3a: /* FSUB */
9387 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9389 case 0x3e: /* FMIN */
9390 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9392 case 0x3f: /* FRSQRTS */
9393 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9395 case 0x5b: /* FMUL */
9396 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9398 case 0x5c: /* FCMGE */
9399 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9401 case 0x5d: /* FACGE */
9402 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9404 case 0x5f: /* FDIV */
9405 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9407 case 0x7a: /* FABD */
9408 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9409 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9411 case 0x7c: /* FCMGT */
9412 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9414 case 0x7d: /* FACGT */
9415 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9418 g_assert_not_reached();
9421 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9423 tcg_temp_free_i64(tcg_res
);
9424 tcg_temp_free_i64(tcg_op1
);
9425 tcg_temp_free_i64(tcg_op2
);
9428 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9429 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9430 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9432 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9433 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9436 case 0x39: /* FMLS */
9437 /* As usual for ARM, separate negation for fused multiply-add */
9438 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9440 case 0x19: /* FMLA */
9441 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9442 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9445 case 0x1a: /* FADD */
9446 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9448 case 0x1b: /* FMULX */
9449 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9451 case 0x1c: /* FCMEQ */
9452 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9454 case 0x1e: /* FMAX */
9455 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9457 case 0x1f: /* FRECPS */
9458 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9460 case 0x18: /* FMAXNM */
9461 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9463 case 0x38: /* FMINNM */
9464 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9466 case 0x3a: /* FSUB */
9467 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9469 case 0x3e: /* FMIN */
9470 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9472 case 0x3f: /* FRSQRTS */
9473 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9475 case 0x5b: /* FMUL */
9476 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9478 case 0x5c: /* FCMGE */
9479 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9481 case 0x5d: /* FACGE */
9482 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9484 case 0x5f: /* FDIV */
9485 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9487 case 0x7a: /* FABD */
9488 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9489 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9491 case 0x7c: /* FCMGT */
9492 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9494 case 0x7d: /* FACGT */
9495 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9498 g_assert_not_reached();
9501 if (elements
== 1) {
9502 /* scalar single so clear high part */
9503 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9505 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9506 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9507 tcg_temp_free_i64(tcg_tmp
);
9509 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9512 tcg_temp_free_i32(tcg_res
);
9513 tcg_temp_free_i32(tcg_op1
);
9514 tcg_temp_free_i32(tcg_op2
);
9518 tcg_temp_free_ptr(fpst
);
9520 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9523 /* AdvSIMD scalar three same
9524 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9525 * +-----+---+-----------+------+---+------+--------+---+------+------+
9526 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9527 * +-----+---+-----------+------+---+------+--------+---+------+------+
9529 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9531 int rd
= extract32(insn
, 0, 5);
9532 int rn
= extract32(insn
, 5, 5);
9533 int opcode
= extract32(insn
, 11, 5);
9534 int rm
= extract32(insn
, 16, 5);
9535 int size
= extract32(insn
, 22, 2);
9536 bool u
= extract32(insn
, 29, 1);
9539 if (opcode
>= 0x18) {
9540 /* Floating point: U, size[1] and opcode indicate operation */
9541 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9543 case 0x1b: /* FMULX */
9544 case 0x1f: /* FRECPS */
9545 case 0x3f: /* FRSQRTS */
9546 case 0x5d: /* FACGE */
9547 case 0x7d: /* FACGT */
9548 case 0x1c: /* FCMEQ */
9549 case 0x5c: /* FCMGE */
9550 case 0x7c: /* FCMGT */
9551 case 0x7a: /* FABD */
9554 unallocated_encoding(s
);
9558 if (!fp_access_check(s
)) {
9562 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9567 case 0x1: /* SQADD, UQADD */
9568 case 0x5: /* SQSUB, UQSUB */
9569 case 0x9: /* SQSHL, UQSHL */
9570 case 0xb: /* SQRSHL, UQRSHL */
9572 case 0x8: /* SSHL, USHL */
9573 case 0xa: /* SRSHL, URSHL */
9574 case 0x6: /* CMGT, CMHI */
9575 case 0x7: /* CMGE, CMHS */
9576 case 0x11: /* CMTST, CMEQ */
9577 case 0x10: /* ADD, SUB (vector) */
9579 unallocated_encoding(s
);
9583 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9584 if (size
!= 1 && size
!= 2) {
9585 unallocated_encoding(s
);
9590 unallocated_encoding(s
);
9594 if (!fp_access_check(s
)) {
9598 tcg_rd
= tcg_temp_new_i64();
9601 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9602 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9604 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9605 tcg_temp_free_i64(tcg_rn
);
9606 tcg_temp_free_i64(tcg_rm
);
9608 /* Do a single operation on the lowest element in the vector.
9609 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9610 * no side effects for all these operations.
9611 * OPTME: special-purpose helpers would avoid doing some
9612 * unnecessary work in the helper for the 8 and 16 bit cases.
9614 NeonGenTwoOpEnvFn
*genenvfn
;
9615 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9616 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9617 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9619 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9620 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9623 case 0x1: /* SQADD, UQADD */
9625 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9626 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9627 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9628 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9630 genenvfn
= fns
[size
][u
];
9633 case 0x5: /* SQSUB, UQSUB */
9635 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9636 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9637 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9638 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9640 genenvfn
= fns
[size
][u
];
9643 case 0x9: /* SQSHL, UQSHL */
9645 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9646 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9647 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9648 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9650 genenvfn
= fns
[size
][u
];
9653 case 0xb: /* SQRSHL, UQRSHL */
9655 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9656 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9657 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9658 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9660 genenvfn
= fns
[size
][u
];
9663 case 0x16: /* SQDMULH, SQRDMULH */
9665 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9666 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9667 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9669 assert(size
== 1 || size
== 2);
9670 genenvfn
= fns
[size
- 1][u
];
9674 g_assert_not_reached();
9677 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9678 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9679 tcg_temp_free_i32(tcg_rd32
);
9680 tcg_temp_free_i32(tcg_rn
);
9681 tcg_temp_free_i32(tcg_rm
);
9684 write_fp_dreg(s
, rd
, tcg_rd
);
9686 tcg_temp_free_i64(tcg_rd
);
9689 /* AdvSIMD scalar three same FP16
9690 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9691 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9692 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9693 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9694 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9695 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9697 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9700 int rd
= extract32(insn
, 0, 5);
9701 int rn
= extract32(insn
, 5, 5);
9702 int opcode
= extract32(insn
, 11, 3);
9703 int rm
= extract32(insn
, 16, 5);
9704 bool u
= extract32(insn
, 29, 1);
9705 bool a
= extract32(insn
, 23, 1);
9706 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9713 case 0x03: /* FMULX */
9714 case 0x04: /* FCMEQ (reg) */
9715 case 0x07: /* FRECPS */
9716 case 0x0f: /* FRSQRTS */
9717 case 0x14: /* FCMGE (reg) */
9718 case 0x15: /* FACGE */
9719 case 0x1a: /* FABD */
9720 case 0x1c: /* FCMGT (reg) */
9721 case 0x1d: /* FACGT */
9724 unallocated_encoding(s
);
9728 if (!dc_isar_feature(aa64_fp16
, s
)) {
9729 unallocated_encoding(s
);
9732 if (!fp_access_check(s
)) {
9736 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9738 tcg_op1
= read_fp_hreg(s
, rn
);
9739 tcg_op2
= read_fp_hreg(s
, rm
);
9740 tcg_res
= tcg_temp_new_i32();
9743 case 0x03: /* FMULX */
9744 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9746 case 0x04: /* FCMEQ (reg) */
9747 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9749 case 0x07: /* FRECPS */
9750 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9752 case 0x0f: /* FRSQRTS */
9753 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9755 case 0x14: /* FCMGE (reg) */
9756 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9758 case 0x15: /* FACGE */
9759 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9761 case 0x1a: /* FABD */
9762 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9763 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9765 case 0x1c: /* FCMGT (reg) */
9766 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9768 case 0x1d: /* FACGT */
9769 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9772 g_assert_not_reached();
9775 write_fp_sreg(s
, rd
, tcg_res
);
9778 tcg_temp_free_i32(tcg_res
);
9779 tcg_temp_free_i32(tcg_op1
);
9780 tcg_temp_free_i32(tcg_op2
);
9781 tcg_temp_free_ptr(fpst
);
9784 /* AdvSIMD scalar three same extra
9785 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9786 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9787 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9788 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9790 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9793 int rd
= extract32(insn
, 0, 5);
9794 int rn
= extract32(insn
, 5, 5);
9795 int opcode
= extract32(insn
, 11, 4);
9796 int rm
= extract32(insn
, 16, 5);
9797 int size
= extract32(insn
, 22, 2);
9798 bool u
= extract32(insn
, 29, 1);
9799 TCGv_i32 ele1
, ele2
, ele3
;
9803 switch (u
* 16 + opcode
) {
9804 case 0x10: /* SQRDMLAH (vector) */
9805 case 0x11: /* SQRDMLSH (vector) */
9806 if (size
!= 1 && size
!= 2) {
9807 unallocated_encoding(s
);
9810 feature
= dc_isar_feature(aa64_rdm
, s
);
9813 unallocated_encoding(s
);
9817 unallocated_encoding(s
);
9820 if (!fp_access_check(s
)) {
9824 /* Do a single operation on the lowest element in the vector.
9825 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9826 * with no side effects for all these operations.
9827 * OPTME: special-purpose helpers would avoid doing some
9828 * unnecessary work in the helper for the 16 bit cases.
9830 ele1
= tcg_temp_new_i32();
9831 ele2
= tcg_temp_new_i32();
9832 ele3
= tcg_temp_new_i32();
9834 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9835 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9836 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9839 case 0x0: /* SQRDMLAH */
9841 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9843 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9846 case 0x1: /* SQRDMLSH */
9848 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9850 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9854 g_assert_not_reached();
9856 tcg_temp_free_i32(ele1
);
9857 tcg_temp_free_i32(ele2
);
9859 res
= tcg_temp_new_i64();
9860 tcg_gen_extu_i32_i64(res
, ele3
);
9861 tcg_temp_free_i32(ele3
);
9863 write_fp_dreg(s
, rd
, res
);
9864 tcg_temp_free_i64(res
);
9867 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9868 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9869 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9871 /* Handle 64->64 opcodes which are shared between the scalar and
9872 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9873 * is valid in either group and also the double-precision fp ops.
9874 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9880 case 0x4: /* CLS, CLZ */
9882 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9884 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9888 /* This opcode is shared with CNT and RBIT but we have earlier
9889 * enforced that size == 3 if and only if this is the NOT insn.
9891 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9893 case 0x7: /* SQABS, SQNEG */
9895 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9897 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9900 case 0xa: /* CMLT */
9901 /* 64 bit integer comparison against zero, result is
9902 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9907 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9908 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9910 case 0x8: /* CMGT, CMGE */
9911 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9913 case 0x9: /* CMEQ, CMLE */
9914 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9916 case 0xb: /* ABS, NEG */
9918 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9920 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9923 case 0x2f: /* FABS */
9924 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9926 case 0x6f: /* FNEG */
9927 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9929 case 0x7f: /* FSQRT */
9930 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9932 case 0x1a: /* FCVTNS */
9933 case 0x1b: /* FCVTMS */
9934 case 0x1c: /* FCVTAS */
9935 case 0x3a: /* FCVTPS */
9936 case 0x3b: /* FCVTZS */
9938 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9939 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9940 tcg_temp_free_i32(tcg_shift
);
9943 case 0x5a: /* FCVTNU */
9944 case 0x5b: /* FCVTMU */
9945 case 0x5c: /* FCVTAU */
9946 case 0x7a: /* FCVTPU */
9947 case 0x7b: /* FCVTZU */
9949 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9950 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9951 tcg_temp_free_i32(tcg_shift
);
9954 case 0x18: /* FRINTN */
9955 case 0x19: /* FRINTM */
9956 case 0x38: /* FRINTP */
9957 case 0x39: /* FRINTZ */
9958 case 0x58: /* FRINTA */
9959 case 0x79: /* FRINTI */
9960 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9962 case 0x59: /* FRINTX */
9963 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9965 case 0x1e: /* FRINT32Z */
9966 case 0x5e: /* FRINT32X */
9967 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9969 case 0x1f: /* FRINT64Z */
9970 case 0x5f: /* FRINT64X */
9971 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9974 g_assert_not_reached();
9978 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9979 bool is_scalar
, bool is_u
, bool is_q
,
9980 int size
, int rn
, int rd
)
9982 bool is_double
= (size
== MO_64
);
9985 if (!fp_access_check(s
)) {
9989 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9992 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9993 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9994 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9995 NeonGenTwoDoubleOpFn
*genfn
;
10000 case 0x2e: /* FCMLT (zero) */
10003 case 0x2c: /* FCMGT (zero) */
10004 genfn
= gen_helper_neon_cgt_f64
;
10006 case 0x2d: /* FCMEQ (zero) */
10007 genfn
= gen_helper_neon_ceq_f64
;
10009 case 0x6d: /* FCMLE (zero) */
10012 case 0x6c: /* FCMGE (zero) */
10013 genfn
= gen_helper_neon_cge_f64
;
10016 g_assert_not_reached();
10019 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10020 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10022 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10024 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10026 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10028 tcg_temp_free_i64(tcg_res
);
10029 tcg_temp_free_i64(tcg_zero
);
10030 tcg_temp_free_i64(tcg_op
);
10032 clear_vec_high(s
, !is_scalar
, rd
);
10034 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10035 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10036 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10037 NeonGenTwoSingleOpFn
*genfn
;
10039 int pass
, maxpasses
;
10041 if (size
== MO_16
) {
10043 case 0x2e: /* FCMLT (zero) */
10046 case 0x2c: /* FCMGT (zero) */
10047 genfn
= gen_helper_advsimd_cgt_f16
;
10049 case 0x2d: /* FCMEQ (zero) */
10050 genfn
= gen_helper_advsimd_ceq_f16
;
10052 case 0x6d: /* FCMLE (zero) */
10055 case 0x6c: /* FCMGE (zero) */
10056 genfn
= gen_helper_advsimd_cge_f16
;
10059 g_assert_not_reached();
10063 case 0x2e: /* FCMLT (zero) */
10066 case 0x2c: /* FCMGT (zero) */
10067 genfn
= gen_helper_neon_cgt_f32
;
10069 case 0x2d: /* FCMEQ (zero) */
10070 genfn
= gen_helper_neon_ceq_f32
;
10072 case 0x6d: /* FCMLE (zero) */
10075 case 0x6c: /* FCMGE (zero) */
10076 genfn
= gen_helper_neon_cge_f32
;
10079 g_assert_not_reached();
10086 int vector_size
= 8 << is_q
;
10087 maxpasses
= vector_size
>> size
;
10090 for (pass
= 0; pass
< maxpasses
; pass
++) {
10091 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10093 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10095 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10098 write_fp_sreg(s
, rd
, tcg_res
);
10100 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10103 tcg_temp_free_i32(tcg_res
);
10104 tcg_temp_free_i32(tcg_zero
);
10105 tcg_temp_free_i32(tcg_op
);
10107 clear_vec_high(s
, is_q
, rd
);
10111 tcg_temp_free_ptr(fpst
);
10114 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10115 bool is_scalar
, bool is_u
, bool is_q
,
10116 int size
, int rn
, int rd
)
10118 bool is_double
= (size
== 3);
10119 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10122 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10123 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10126 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10127 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10129 case 0x3d: /* FRECPE */
10130 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10132 case 0x3f: /* FRECPX */
10133 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10135 case 0x7d: /* FRSQRTE */
10136 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10139 g_assert_not_reached();
10141 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10143 tcg_temp_free_i64(tcg_res
);
10144 tcg_temp_free_i64(tcg_op
);
10145 clear_vec_high(s
, !is_scalar
, rd
);
10147 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10148 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10149 int pass
, maxpasses
;
10154 maxpasses
= is_q
? 4 : 2;
10157 for (pass
= 0; pass
< maxpasses
; pass
++) {
10158 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10161 case 0x3c: /* URECPE */
10162 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10164 case 0x3d: /* FRECPE */
10165 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10167 case 0x3f: /* FRECPX */
10168 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10170 case 0x7d: /* FRSQRTE */
10171 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10174 g_assert_not_reached();
10178 write_fp_sreg(s
, rd
, tcg_res
);
10180 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10183 tcg_temp_free_i32(tcg_res
);
10184 tcg_temp_free_i32(tcg_op
);
10186 clear_vec_high(s
, is_q
, rd
);
10189 tcg_temp_free_ptr(fpst
);
10192 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10193 int opcode
, bool u
, bool is_q
,
10194 int size
, int rn
, int rd
)
10196 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10197 * in the source becomes a size element in the destination).
10200 TCGv_i32 tcg_res
[2];
10201 int destelt
= is_q
? 2 : 0;
10202 int passes
= scalar
? 1 : 2;
10205 tcg_res
[1] = tcg_const_i32(0);
10208 for (pass
= 0; pass
< passes
; pass
++) {
10209 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10210 NeonGenNarrowFn
*genfn
= NULL
;
10211 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10214 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10216 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10218 tcg_res
[pass
] = tcg_temp_new_i32();
10221 case 0x12: /* XTN, SQXTUN */
10223 static NeonGenNarrowFn
* const xtnfns
[3] = {
10224 gen_helper_neon_narrow_u8
,
10225 gen_helper_neon_narrow_u16
,
10226 tcg_gen_extrl_i64_i32
,
10228 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10229 gen_helper_neon_unarrow_sat8
,
10230 gen_helper_neon_unarrow_sat16
,
10231 gen_helper_neon_unarrow_sat32
,
10234 genenvfn
= sqxtunfns
[size
];
10236 genfn
= xtnfns
[size
];
10240 case 0x14: /* SQXTN, UQXTN */
10242 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10243 { gen_helper_neon_narrow_sat_s8
,
10244 gen_helper_neon_narrow_sat_u8
},
10245 { gen_helper_neon_narrow_sat_s16
,
10246 gen_helper_neon_narrow_sat_u16
},
10247 { gen_helper_neon_narrow_sat_s32
,
10248 gen_helper_neon_narrow_sat_u32
},
10250 genenvfn
= fns
[size
][u
];
10253 case 0x16: /* FCVTN, FCVTN2 */
10254 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10256 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10258 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10259 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10260 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10261 TCGv_i32 ahp
= get_ahp_flag();
10263 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10264 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10265 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10266 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10267 tcg_temp_free_i32(tcg_lo
);
10268 tcg_temp_free_i32(tcg_hi
);
10269 tcg_temp_free_ptr(fpst
);
10270 tcg_temp_free_i32(ahp
);
10273 case 0x36: /* BFCVTN, BFCVTN2 */
10275 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10276 gen_helper_bfcvt_pair(tcg_res
[pass
], tcg_op
, fpst
);
10277 tcg_temp_free_ptr(fpst
);
10280 case 0x56: /* FCVTXN, FCVTXN2 */
10281 /* 64 bit to 32 bit float conversion
10282 * with von Neumann rounding (round to odd)
10285 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10288 g_assert_not_reached();
10292 genfn(tcg_res
[pass
], tcg_op
);
10293 } else if (genenvfn
) {
10294 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10297 tcg_temp_free_i64(tcg_op
);
10300 for (pass
= 0; pass
< 2; pass
++) {
10301 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10302 tcg_temp_free_i32(tcg_res
[pass
]);
10304 clear_vec_high(s
, is_q
, rd
);
10307 /* Remaining saturating accumulating ops */
10308 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10309 bool is_q
, int size
, int rn
, int rd
)
10311 bool is_double
= (size
== 3);
10314 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10315 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10318 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10319 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10320 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10322 if (is_u
) { /* USQADD */
10323 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10324 } else { /* SUQADD */
10325 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10327 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10329 tcg_temp_free_i64(tcg_rd
);
10330 tcg_temp_free_i64(tcg_rn
);
10331 clear_vec_high(s
, !is_scalar
, rd
);
10333 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10334 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10335 int pass
, maxpasses
;
10340 maxpasses
= is_q
? 4 : 2;
10343 for (pass
= 0; pass
< maxpasses
; pass
++) {
10345 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10346 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10348 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10349 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10352 if (is_u
) { /* USQADD */
10355 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10358 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10361 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10364 g_assert_not_reached();
10366 } else { /* SUQADD */
10369 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10372 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10375 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10378 g_assert_not_reached();
10383 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10384 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10385 tcg_temp_free_i64(tcg_zero
);
10387 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10389 tcg_temp_free_i32(tcg_rd
);
10390 tcg_temp_free_i32(tcg_rn
);
10391 clear_vec_high(s
, is_q
, rd
);
10395 /* AdvSIMD scalar two reg misc
10396 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10397 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10398 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10399 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10401 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10403 int rd
= extract32(insn
, 0, 5);
10404 int rn
= extract32(insn
, 5, 5);
10405 int opcode
= extract32(insn
, 12, 5);
10406 int size
= extract32(insn
, 22, 2);
10407 bool u
= extract32(insn
, 29, 1);
10408 bool is_fcvt
= false;
10410 TCGv_i32 tcg_rmode
;
10411 TCGv_ptr tcg_fpstatus
;
10414 case 0x3: /* USQADD / SUQADD*/
10415 if (!fp_access_check(s
)) {
10418 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10420 case 0x7: /* SQABS / SQNEG */
10422 case 0xa: /* CMLT */
10424 unallocated_encoding(s
);
10428 case 0x8: /* CMGT, CMGE */
10429 case 0x9: /* CMEQ, CMLE */
10430 case 0xb: /* ABS, NEG */
10432 unallocated_encoding(s
);
10436 case 0x12: /* SQXTUN */
10438 unallocated_encoding(s
);
10442 case 0x14: /* SQXTN, UQXTN */
10444 unallocated_encoding(s
);
10447 if (!fp_access_check(s
)) {
10450 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10453 case 0x16 ... 0x1d:
10455 /* Floating point: U, size[1] and opcode indicate operation;
10456 * size[0] indicates single or double precision.
10458 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10459 size
= extract32(size
, 0, 1) ? 3 : 2;
10461 case 0x2c: /* FCMGT (zero) */
10462 case 0x2d: /* FCMEQ (zero) */
10463 case 0x2e: /* FCMLT (zero) */
10464 case 0x6c: /* FCMGE (zero) */
10465 case 0x6d: /* FCMLE (zero) */
10466 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10468 case 0x1d: /* SCVTF */
10469 case 0x5d: /* UCVTF */
10471 bool is_signed
= (opcode
== 0x1d);
10472 if (!fp_access_check(s
)) {
10475 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10478 case 0x3d: /* FRECPE */
10479 case 0x3f: /* FRECPX */
10480 case 0x7d: /* FRSQRTE */
10481 if (!fp_access_check(s
)) {
10484 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10486 case 0x1a: /* FCVTNS */
10487 case 0x1b: /* FCVTMS */
10488 case 0x3a: /* FCVTPS */
10489 case 0x3b: /* FCVTZS */
10490 case 0x5a: /* FCVTNU */
10491 case 0x5b: /* FCVTMU */
10492 case 0x7a: /* FCVTPU */
10493 case 0x7b: /* FCVTZU */
10495 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10497 case 0x1c: /* FCVTAS */
10498 case 0x5c: /* FCVTAU */
10499 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10501 rmode
= FPROUNDING_TIEAWAY
;
10503 case 0x56: /* FCVTXN, FCVTXN2 */
10505 unallocated_encoding(s
);
10508 if (!fp_access_check(s
)) {
10511 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10514 unallocated_encoding(s
);
10519 unallocated_encoding(s
);
10523 if (!fp_access_check(s
)) {
10528 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10529 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10530 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10533 tcg_fpstatus
= NULL
;
10537 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10538 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10540 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10541 write_fp_dreg(s
, rd
, tcg_rd
);
10542 tcg_temp_free_i64(tcg_rd
);
10543 tcg_temp_free_i64(tcg_rn
);
10545 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10546 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10548 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10551 case 0x7: /* SQABS, SQNEG */
10553 NeonGenOneOpEnvFn
*genfn
;
10554 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10555 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10556 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10557 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10559 genfn
= fns
[size
][u
];
10560 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10563 case 0x1a: /* FCVTNS */
10564 case 0x1b: /* FCVTMS */
10565 case 0x1c: /* FCVTAS */
10566 case 0x3a: /* FCVTPS */
10567 case 0x3b: /* FCVTZS */
10569 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10570 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10571 tcg_temp_free_i32(tcg_shift
);
10574 case 0x5a: /* FCVTNU */
10575 case 0x5b: /* FCVTMU */
10576 case 0x5c: /* FCVTAU */
10577 case 0x7a: /* FCVTPU */
10578 case 0x7b: /* FCVTZU */
10580 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10581 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10582 tcg_temp_free_i32(tcg_shift
);
10586 g_assert_not_reached();
10589 write_fp_sreg(s
, rd
, tcg_rd
);
10590 tcg_temp_free_i32(tcg_rd
);
10591 tcg_temp_free_i32(tcg_rn
);
10595 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10596 tcg_temp_free_i32(tcg_rmode
);
10597 tcg_temp_free_ptr(tcg_fpstatus
);
10601 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10602 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10603 int immh
, int immb
, int opcode
, int rn
, int rd
)
10605 int size
= 32 - clz32(immh
) - 1;
10606 int immhb
= immh
<< 3 | immb
;
10607 int shift
= 2 * (8 << size
) - immhb
;
10608 GVecGen2iFn
*gvec_fn
;
10610 if (extract32(immh
, 3, 1) && !is_q
) {
10611 unallocated_encoding(s
);
10614 tcg_debug_assert(size
<= 3);
10616 if (!fp_access_check(s
)) {
10621 case 0x02: /* SSRA / USRA (accumulate) */
10622 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10625 case 0x08: /* SRI */
10626 gvec_fn
= gen_gvec_sri
;
10629 case 0x00: /* SSHR / USHR */
10631 if (shift
== 8 << size
) {
10632 /* Shift count the same size as element size produces zero. */
10633 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10634 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10637 gvec_fn
= tcg_gen_gvec_shri
;
10639 /* Shift count the same size as element size produces all sign. */
10640 if (shift
== 8 << size
) {
10643 gvec_fn
= tcg_gen_gvec_sari
;
10647 case 0x04: /* SRSHR / URSHR (rounding) */
10648 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10651 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10652 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10656 g_assert_not_reached();
10659 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10662 /* SHL/SLI - Vector shift left */
10663 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10664 int immh
, int immb
, int opcode
, int rn
, int rd
)
10666 int size
= 32 - clz32(immh
) - 1;
10667 int immhb
= immh
<< 3 | immb
;
10668 int shift
= immhb
- (8 << size
);
10670 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10671 assert(size
>= 0 && size
<= 3);
10673 if (extract32(immh
, 3, 1) && !is_q
) {
10674 unallocated_encoding(s
);
10678 if (!fp_access_check(s
)) {
10683 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10685 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10689 /* USHLL/SHLL - Vector shift left with widening */
10690 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10691 int immh
, int immb
, int opcode
, int rn
, int rd
)
10693 int size
= 32 - clz32(immh
) - 1;
10694 int immhb
= immh
<< 3 | immb
;
10695 int shift
= immhb
- (8 << size
);
10697 int esize
= 8 << size
;
10698 int elements
= dsize
/esize
;
10699 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10700 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10704 unallocated_encoding(s
);
10708 if (!fp_access_check(s
)) {
10712 /* For the LL variants the store is larger than the load,
10713 * so if rd == rn we would overwrite parts of our input.
10714 * So load everything right now and use shifts in the main loop.
10716 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10718 for (i
= 0; i
< elements
; i
++) {
10719 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10720 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10721 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10722 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10726 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10727 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10728 int immh
, int immb
, int opcode
, int rn
, int rd
)
10730 int immhb
= immh
<< 3 | immb
;
10731 int size
= 32 - clz32(immh
) - 1;
10733 int esize
= 8 << size
;
10734 int elements
= dsize
/esize
;
10735 int shift
= (2 * esize
) - immhb
;
10736 bool round
= extract32(opcode
, 0, 1);
10737 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10738 TCGv_i64 tcg_round
;
10741 if (extract32(immh
, 3, 1)) {
10742 unallocated_encoding(s
);
10746 if (!fp_access_check(s
)) {
10750 tcg_rn
= tcg_temp_new_i64();
10751 tcg_rd
= tcg_temp_new_i64();
10752 tcg_final
= tcg_temp_new_i64();
10753 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10756 uint64_t round_const
= 1ULL << (shift
- 1);
10757 tcg_round
= tcg_const_i64(round_const
);
10762 for (i
= 0; i
< elements
; i
++) {
10763 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10764 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10765 false, true, size
+1, shift
);
10767 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10771 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10773 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10776 tcg_temp_free_i64(tcg_round
);
10778 tcg_temp_free_i64(tcg_rn
);
10779 tcg_temp_free_i64(tcg_rd
);
10780 tcg_temp_free_i64(tcg_final
);
10782 clear_vec_high(s
, is_q
, rd
);
10786 /* AdvSIMD shift by immediate
10787 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10788 * +---+---+---+-------------+------+------+--------+---+------+------+
10789 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10790 * +---+---+---+-------------+------+------+--------+---+------+------+
10792 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10794 int rd
= extract32(insn
, 0, 5);
10795 int rn
= extract32(insn
, 5, 5);
10796 int opcode
= extract32(insn
, 11, 5);
10797 int immb
= extract32(insn
, 16, 3);
10798 int immh
= extract32(insn
, 19, 4);
10799 bool is_u
= extract32(insn
, 29, 1);
10800 bool is_q
= extract32(insn
, 30, 1);
10802 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10806 case 0x08: /* SRI */
10808 unallocated_encoding(s
);
10812 case 0x00: /* SSHR / USHR */
10813 case 0x02: /* SSRA / USRA (accumulate) */
10814 case 0x04: /* SRSHR / URSHR (rounding) */
10815 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10816 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10818 case 0x0a: /* SHL / SLI */
10819 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10821 case 0x10: /* SHRN */
10822 case 0x11: /* RSHRN / SQRSHRUN */
10824 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10827 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10830 case 0x12: /* SQSHRN / UQSHRN */
10831 case 0x13: /* SQRSHRN / UQRSHRN */
10832 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10835 case 0x14: /* SSHLL / USHLL */
10836 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10838 case 0x1c: /* SCVTF / UCVTF */
10839 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10842 case 0xc: /* SQSHLU */
10844 unallocated_encoding(s
);
10847 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10849 case 0xe: /* SQSHL, UQSHL */
10850 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10852 case 0x1f: /* FCVTZS/ FCVTZU */
10853 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10856 unallocated_encoding(s
);
10861 /* Generate code to do a "long" addition or subtraction, ie one done in
10862 * TCGv_i64 on vector lanes twice the width specified by size.
10864 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10865 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10867 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10868 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10869 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10870 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10872 NeonGenTwo64OpFn
*genfn
;
10875 genfn
= fns
[size
][is_sub
];
10876 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10879 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10880 int opcode
, int rd
, int rn
, int rm
)
10882 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10883 TCGv_i64 tcg_res
[2];
10886 tcg_res
[0] = tcg_temp_new_i64();
10887 tcg_res
[1] = tcg_temp_new_i64();
10889 /* Does this op do an adding accumulate, a subtracting accumulate,
10890 * or no accumulate at all?
10908 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10909 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10912 /* size == 2 means two 32x32->64 operations; this is worth special
10913 * casing because we can generally handle it inline.
10916 for (pass
= 0; pass
< 2; pass
++) {
10917 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10918 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10919 TCGv_i64 tcg_passres
;
10920 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10922 int elt
= pass
+ is_q
* 2;
10924 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10925 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10928 tcg_passres
= tcg_res
[pass
];
10930 tcg_passres
= tcg_temp_new_i64();
10934 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10935 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10937 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10938 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10940 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10941 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10943 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10944 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10946 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10947 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10948 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10950 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10951 tcg_temp_free_i64(tcg_tmp1
);
10952 tcg_temp_free_i64(tcg_tmp2
);
10955 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10956 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10957 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10958 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10960 case 9: /* SQDMLAL, SQDMLAL2 */
10961 case 11: /* SQDMLSL, SQDMLSL2 */
10962 case 13: /* SQDMULL, SQDMULL2 */
10963 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10964 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10965 tcg_passres
, tcg_passres
);
10968 g_assert_not_reached();
10971 if (opcode
== 9 || opcode
== 11) {
10972 /* saturating accumulate ops */
10974 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10976 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10977 tcg_res
[pass
], tcg_passres
);
10978 } else if (accop
> 0) {
10979 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10980 } else if (accop
< 0) {
10981 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10985 tcg_temp_free_i64(tcg_passres
);
10988 tcg_temp_free_i64(tcg_op1
);
10989 tcg_temp_free_i64(tcg_op2
);
10992 /* size 0 or 1, generally helper functions */
10993 for (pass
= 0; pass
< 2; pass
++) {
10994 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10995 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10996 TCGv_i64 tcg_passres
;
10997 int elt
= pass
+ is_q
* 2;
10999 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
11000 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11003 tcg_passres
= tcg_res
[pass
];
11005 tcg_passres
= tcg_temp_new_i64();
11009 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11010 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11012 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11013 static NeonGenWidenFn
* const widenfns
[2][2] = {
11014 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11015 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11017 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11019 widenfn(tcg_op2_64
, tcg_op2
);
11020 widenfn(tcg_passres
, tcg_op1
);
11021 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11022 tcg_passres
, tcg_op2_64
);
11023 tcg_temp_free_i64(tcg_op2_64
);
11026 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11027 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11030 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11032 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11036 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11038 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11042 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11043 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11044 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11047 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11049 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11053 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11055 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11059 case 9: /* SQDMLAL, SQDMLAL2 */
11060 case 11: /* SQDMLSL, SQDMLSL2 */
11061 case 13: /* SQDMULL, SQDMULL2 */
11063 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11064 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11065 tcg_passres
, tcg_passres
);
11068 g_assert_not_reached();
11070 tcg_temp_free_i32(tcg_op1
);
11071 tcg_temp_free_i32(tcg_op2
);
11074 if (opcode
== 9 || opcode
== 11) {
11075 /* saturating accumulate ops */
11077 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11079 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11083 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11084 tcg_res
[pass
], tcg_passres
);
11086 tcg_temp_free_i64(tcg_passres
);
11091 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11092 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11093 tcg_temp_free_i64(tcg_res
[0]);
11094 tcg_temp_free_i64(tcg_res
[1]);
11097 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11098 int opcode
, int rd
, int rn
, int rm
)
11100 TCGv_i64 tcg_res
[2];
11101 int part
= is_q
? 2 : 0;
11104 for (pass
= 0; pass
< 2; pass
++) {
11105 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11106 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11107 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11108 static NeonGenWidenFn
* const widenfns
[3][2] = {
11109 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11110 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11111 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11113 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11115 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11116 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11117 widenfn(tcg_op2_wide
, tcg_op2
);
11118 tcg_temp_free_i32(tcg_op2
);
11119 tcg_res
[pass
] = tcg_temp_new_i64();
11120 gen_neon_addl(size
, (opcode
== 3),
11121 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11122 tcg_temp_free_i64(tcg_op1
);
11123 tcg_temp_free_i64(tcg_op2_wide
);
11126 for (pass
= 0; pass
< 2; pass
++) {
11127 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11128 tcg_temp_free_i64(tcg_res
[pass
]);
11132 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11134 tcg_gen_addi_i64(in
, in
, 1U << 31);
11135 tcg_gen_extrh_i64_i32(res
, in
);
11138 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11139 int opcode
, int rd
, int rn
, int rm
)
11141 TCGv_i32 tcg_res
[2];
11142 int part
= is_q
? 2 : 0;
11145 for (pass
= 0; pass
< 2; pass
++) {
11146 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11147 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11148 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11149 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11150 { gen_helper_neon_narrow_high_u8
,
11151 gen_helper_neon_narrow_round_high_u8
},
11152 { gen_helper_neon_narrow_high_u16
,
11153 gen_helper_neon_narrow_round_high_u16
},
11154 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11156 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11158 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11159 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11161 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11163 tcg_temp_free_i64(tcg_op1
);
11164 tcg_temp_free_i64(tcg_op2
);
11166 tcg_res
[pass
] = tcg_temp_new_i32();
11167 gennarrow(tcg_res
[pass
], tcg_wideres
);
11168 tcg_temp_free_i64(tcg_wideres
);
11171 for (pass
= 0; pass
< 2; pass
++) {
11172 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11173 tcg_temp_free_i32(tcg_res
[pass
]);
11175 clear_vec_high(s
, is_q
, rd
);
11178 /* AdvSIMD three different
11179 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11180 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11181 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11182 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11184 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11186 /* Instructions in this group fall into three basic classes
11187 * (in each case with the operation working on each element in
11188 * the input vectors):
11189 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11191 * (2) wide 64 x 128 -> 128
11192 * (3) narrowing 128 x 128 -> 64
11193 * Here we do initial decode, catch unallocated cases and
11194 * dispatch to separate functions for each class.
11196 int is_q
= extract32(insn
, 30, 1);
11197 int is_u
= extract32(insn
, 29, 1);
11198 int size
= extract32(insn
, 22, 2);
11199 int opcode
= extract32(insn
, 12, 4);
11200 int rm
= extract32(insn
, 16, 5);
11201 int rn
= extract32(insn
, 5, 5);
11202 int rd
= extract32(insn
, 0, 5);
11205 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11206 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11207 /* 64 x 128 -> 128 */
11209 unallocated_encoding(s
);
11212 if (!fp_access_check(s
)) {
11215 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11217 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11218 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11219 /* 128 x 128 -> 64 */
11221 unallocated_encoding(s
);
11224 if (!fp_access_check(s
)) {
11227 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11229 case 14: /* PMULL, PMULL2 */
11231 unallocated_encoding(s
);
11235 case 0: /* PMULL.P8 */
11236 if (!fp_access_check(s
)) {
11239 /* The Q field specifies lo/hi half input for this insn. */
11240 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11241 gen_helper_neon_pmull_h
);
11244 case 3: /* PMULL.P64 */
11245 if (!dc_isar_feature(aa64_pmull
, s
)) {
11246 unallocated_encoding(s
);
11249 if (!fp_access_check(s
)) {
11252 /* The Q field specifies lo/hi half input for this insn. */
11253 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11254 gen_helper_gvec_pmull_q
);
11258 unallocated_encoding(s
);
11262 case 9: /* SQDMLAL, SQDMLAL2 */
11263 case 11: /* SQDMLSL, SQDMLSL2 */
11264 case 13: /* SQDMULL, SQDMULL2 */
11265 if (is_u
|| size
== 0) {
11266 unallocated_encoding(s
);
11270 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11271 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11272 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11273 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11274 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11275 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11276 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11277 /* 64 x 64 -> 128 */
11279 unallocated_encoding(s
);
11282 if (!fp_access_check(s
)) {
11286 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11289 /* opcode 15 not allocated */
11290 unallocated_encoding(s
);
11295 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11296 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11298 int rd
= extract32(insn
, 0, 5);
11299 int rn
= extract32(insn
, 5, 5);
11300 int rm
= extract32(insn
, 16, 5);
11301 int size
= extract32(insn
, 22, 2);
11302 bool is_u
= extract32(insn
, 29, 1);
11303 bool is_q
= extract32(insn
, 30, 1);
11305 if (!fp_access_check(s
)) {
11309 switch (size
+ 4 * is_u
) {
11311 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11314 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11317 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11320 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11323 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11326 case 5: /* BSL bitwise select */
11327 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11329 case 6: /* BIT, bitwise insert if true */
11330 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11332 case 7: /* BIF, bitwise insert if false */
11333 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11337 g_assert_not_reached();
11341 /* Pairwise op subgroup of C3.6.16.
11343 * This is called directly or via the handle_3same_float for float pairwise
11344 * operations where the opcode and size are calculated differently.
11346 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11347 int size
, int rn
, int rm
, int rd
)
11352 /* Floating point operations need fpst */
11353 if (opcode
>= 0x58) {
11354 fpst
= fpstatus_ptr(FPST_FPCR
);
11359 if (!fp_access_check(s
)) {
11363 /* These operations work on the concatenated rm:rn, with each pair of
11364 * adjacent elements being operated on to produce an element in the result.
11367 TCGv_i64 tcg_res
[2];
11369 for (pass
= 0; pass
< 2; pass
++) {
11370 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11371 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11372 int passreg
= (pass
== 0) ? rn
: rm
;
11374 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11375 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11376 tcg_res
[pass
] = tcg_temp_new_i64();
11379 case 0x17: /* ADDP */
11380 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11382 case 0x58: /* FMAXNMP */
11383 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11385 case 0x5a: /* FADDP */
11386 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11388 case 0x5e: /* FMAXP */
11389 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11391 case 0x78: /* FMINNMP */
11392 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11394 case 0x7e: /* FMINP */
11395 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11398 g_assert_not_reached();
11401 tcg_temp_free_i64(tcg_op1
);
11402 tcg_temp_free_i64(tcg_op2
);
11405 for (pass
= 0; pass
< 2; pass
++) {
11406 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11407 tcg_temp_free_i64(tcg_res
[pass
]);
11410 int maxpass
= is_q
? 4 : 2;
11411 TCGv_i32 tcg_res
[4];
11413 for (pass
= 0; pass
< maxpass
; pass
++) {
11414 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11415 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11416 NeonGenTwoOpFn
*genfn
= NULL
;
11417 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11418 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11420 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11421 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11422 tcg_res
[pass
] = tcg_temp_new_i32();
11425 case 0x17: /* ADDP */
11427 static NeonGenTwoOpFn
* const fns
[3] = {
11428 gen_helper_neon_padd_u8
,
11429 gen_helper_neon_padd_u16
,
11435 case 0x14: /* SMAXP, UMAXP */
11437 static NeonGenTwoOpFn
* const fns
[3][2] = {
11438 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11439 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11440 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11442 genfn
= fns
[size
][u
];
11445 case 0x15: /* SMINP, UMINP */
11447 static NeonGenTwoOpFn
* const fns
[3][2] = {
11448 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11449 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11450 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11452 genfn
= fns
[size
][u
];
11455 /* The FP operations are all on single floats (32 bit) */
11456 case 0x58: /* FMAXNMP */
11457 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11459 case 0x5a: /* FADDP */
11460 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11462 case 0x5e: /* FMAXP */
11463 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11465 case 0x78: /* FMINNMP */
11466 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11468 case 0x7e: /* FMINP */
11469 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11472 g_assert_not_reached();
11475 /* FP ops called directly, otherwise call now */
11477 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11480 tcg_temp_free_i32(tcg_op1
);
11481 tcg_temp_free_i32(tcg_op2
);
11484 for (pass
= 0; pass
< maxpass
; pass
++) {
11485 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11486 tcg_temp_free_i32(tcg_res
[pass
]);
11488 clear_vec_high(s
, is_q
, rd
);
11492 tcg_temp_free_ptr(fpst
);
11496 /* Floating point op subgroup of C3.6.16. */
11497 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11499 /* For floating point ops, the U, size[1] and opcode bits
11500 * together indicate the operation. size[0] indicates single
11503 int fpopcode
= extract32(insn
, 11, 5)
11504 | (extract32(insn
, 23, 1) << 5)
11505 | (extract32(insn
, 29, 1) << 6);
11506 int is_q
= extract32(insn
, 30, 1);
11507 int size
= extract32(insn
, 22, 1);
11508 int rm
= extract32(insn
, 16, 5);
11509 int rn
= extract32(insn
, 5, 5);
11510 int rd
= extract32(insn
, 0, 5);
11512 int datasize
= is_q
? 128 : 64;
11513 int esize
= 32 << size
;
11514 int elements
= datasize
/ esize
;
11516 if (size
== 1 && !is_q
) {
11517 unallocated_encoding(s
);
11521 switch (fpopcode
) {
11522 case 0x58: /* FMAXNMP */
11523 case 0x5a: /* FADDP */
11524 case 0x5e: /* FMAXP */
11525 case 0x78: /* FMINNMP */
11526 case 0x7e: /* FMINP */
11527 if (size
&& !is_q
) {
11528 unallocated_encoding(s
);
11531 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11534 case 0x1b: /* FMULX */
11535 case 0x1f: /* FRECPS */
11536 case 0x3f: /* FRSQRTS */
11537 case 0x5d: /* FACGE */
11538 case 0x7d: /* FACGT */
11539 case 0x19: /* FMLA */
11540 case 0x39: /* FMLS */
11541 case 0x18: /* FMAXNM */
11542 case 0x1a: /* FADD */
11543 case 0x1c: /* FCMEQ */
11544 case 0x1e: /* FMAX */
11545 case 0x38: /* FMINNM */
11546 case 0x3a: /* FSUB */
11547 case 0x3e: /* FMIN */
11548 case 0x5b: /* FMUL */
11549 case 0x5c: /* FCMGE */
11550 case 0x5f: /* FDIV */
11551 case 0x7a: /* FABD */
11552 case 0x7c: /* FCMGT */
11553 if (!fp_access_check(s
)) {
11556 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11559 case 0x1d: /* FMLAL */
11560 case 0x3d: /* FMLSL */
11561 case 0x59: /* FMLAL2 */
11562 case 0x79: /* FMLSL2 */
11563 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11564 unallocated_encoding(s
);
11567 if (fp_access_check(s
)) {
11568 int is_s
= extract32(insn
, 23, 1);
11569 int is_2
= extract32(insn
, 29, 1);
11570 int data
= (is_2
<< 1) | is_s
;
11571 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11572 vec_full_reg_offset(s
, rn
),
11573 vec_full_reg_offset(s
, rm
), cpu_env
,
11574 is_q
? 16 : 8, vec_full_reg_size(s
),
11575 data
, gen_helper_gvec_fmlal_a64
);
11580 unallocated_encoding(s
);
11585 /* Integer op subgroup of C3.6.16. */
11586 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11588 int is_q
= extract32(insn
, 30, 1);
11589 int u
= extract32(insn
, 29, 1);
11590 int size
= extract32(insn
, 22, 2);
11591 int opcode
= extract32(insn
, 11, 5);
11592 int rm
= extract32(insn
, 16, 5);
11593 int rn
= extract32(insn
, 5, 5);
11594 int rd
= extract32(insn
, 0, 5);
11599 case 0x13: /* MUL, PMUL */
11600 if (u
&& size
!= 0) {
11601 unallocated_encoding(s
);
11605 case 0x0: /* SHADD, UHADD */
11606 case 0x2: /* SRHADD, URHADD */
11607 case 0x4: /* SHSUB, UHSUB */
11608 case 0xc: /* SMAX, UMAX */
11609 case 0xd: /* SMIN, UMIN */
11610 case 0xe: /* SABD, UABD */
11611 case 0xf: /* SABA, UABA */
11612 case 0x12: /* MLA, MLS */
11614 unallocated_encoding(s
);
11618 case 0x16: /* SQDMULH, SQRDMULH */
11619 if (size
== 0 || size
== 3) {
11620 unallocated_encoding(s
);
11625 if (size
== 3 && !is_q
) {
11626 unallocated_encoding(s
);
11632 if (!fp_access_check(s
)) {
11637 case 0x01: /* SQADD, UQADD */
11639 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11641 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11644 case 0x05: /* SQSUB, UQSUB */
11646 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11648 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11651 case 0x08: /* SSHL, USHL */
11653 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11655 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11658 case 0x0c: /* SMAX, UMAX */
11660 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11662 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11665 case 0x0d: /* SMIN, UMIN */
11667 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11669 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11672 case 0xe: /* SABD, UABD */
11674 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11676 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11679 case 0xf: /* SABA, UABA */
11681 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11683 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11686 case 0x10: /* ADD, SUB */
11688 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11690 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11693 case 0x13: /* MUL, PMUL */
11694 if (!u
) { /* MUL */
11695 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11696 } else { /* PMUL */
11697 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11700 case 0x12: /* MLA, MLS */
11702 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11704 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11707 case 0x16: /* SQDMULH, SQRDMULH */
11709 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11710 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11711 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11713 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11717 if (!u
) { /* CMTST */
11718 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11722 cond
= TCG_COND_EQ
;
11724 case 0x06: /* CMGT, CMHI */
11725 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11727 case 0x07: /* CMGE, CMHS */
11728 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11730 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11731 vec_full_reg_offset(s
, rn
),
11732 vec_full_reg_offset(s
, rm
),
11733 is_q
? 16 : 8, vec_full_reg_size(s
));
11739 for (pass
= 0; pass
< 2; pass
++) {
11740 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11741 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11742 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11744 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11745 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11747 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11749 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11751 tcg_temp_free_i64(tcg_res
);
11752 tcg_temp_free_i64(tcg_op1
);
11753 tcg_temp_free_i64(tcg_op2
);
11756 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11757 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11758 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11759 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11760 NeonGenTwoOpFn
*genfn
= NULL
;
11761 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11763 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11764 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11767 case 0x0: /* SHADD, UHADD */
11769 static NeonGenTwoOpFn
* const fns
[3][2] = {
11770 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11771 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11772 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11774 genfn
= fns
[size
][u
];
11777 case 0x2: /* SRHADD, URHADD */
11779 static NeonGenTwoOpFn
* const fns
[3][2] = {
11780 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11781 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11782 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11784 genfn
= fns
[size
][u
];
11787 case 0x4: /* SHSUB, UHSUB */
11789 static NeonGenTwoOpFn
* const fns
[3][2] = {
11790 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11791 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11792 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11794 genfn
= fns
[size
][u
];
11797 case 0x9: /* SQSHL, UQSHL */
11799 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11800 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11801 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11802 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11804 genenvfn
= fns
[size
][u
];
11807 case 0xa: /* SRSHL, URSHL */
11809 static NeonGenTwoOpFn
* const fns
[3][2] = {
11810 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11811 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11812 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11814 genfn
= fns
[size
][u
];
11817 case 0xb: /* SQRSHL, UQRSHL */
11819 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11820 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11821 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11822 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11824 genenvfn
= fns
[size
][u
];
11828 g_assert_not_reached();
11832 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11834 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11837 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11839 tcg_temp_free_i32(tcg_res
);
11840 tcg_temp_free_i32(tcg_op1
);
11841 tcg_temp_free_i32(tcg_op2
);
11844 clear_vec_high(s
, is_q
, rd
);
11847 /* AdvSIMD three same
11848 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11849 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11850 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11851 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11853 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11855 int opcode
= extract32(insn
, 11, 5);
11858 case 0x3: /* logic ops */
11859 disas_simd_3same_logic(s
, insn
);
11861 case 0x17: /* ADDP */
11862 case 0x14: /* SMAXP, UMAXP */
11863 case 0x15: /* SMINP, UMINP */
11865 /* Pairwise operations */
11866 int is_q
= extract32(insn
, 30, 1);
11867 int u
= extract32(insn
, 29, 1);
11868 int size
= extract32(insn
, 22, 2);
11869 int rm
= extract32(insn
, 16, 5);
11870 int rn
= extract32(insn
, 5, 5);
11871 int rd
= extract32(insn
, 0, 5);
11872 if (opcode
== 0x17) {
11873 if (u
|| (size
== 3 && !is_q
)) {
11874 unallocated_encoding(s
);
11879 unallocated_encoding(s
);
11883 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11886 case 0x18 ... 0x31:
11887 /* floating point ops, sz[1] and U are part of opcode */
11888 disas_simd_3same_float(s
, insn
);
11891 disas_simd_3same_int(s
, insn
);
11897 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11899 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11900 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11901 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11902 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11904 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11905 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11908 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11910 int opcode
= extract32(insn
, 11, 3);
11911 int u
= extract32(insn
, 29, 1);
11912 int a
= extract32(insn
, 23, 1);
11913 int is_q
= extract32(insn
, 30, 1);
11914 int rm
= extract32(insn
, 16, 5);
11915 int rn
= extract32(insn
, 5, 5);
11916 int rd
= extract32(insn
, 0, 5);
11918 * For these floating point ops, the U, a and opcode bits
11919 * together indicate the operation.
11921 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11922 int datasize
= is_q
? 128 : 64;
11923 int elements
= datasize
/ 16;
11928 switch (fpopcode
) {
11929 case 0x0: /* FMAXNM */
11930 case 0x1: /* FMLA */
11931 case 0x2: /* FADD */
11932 case 0x3: /* FMULX */
11933 case 0x4: /* FCMEQ */
11934 case 0x6: /* FMAX */
11935 case 0x7: /* FRECPS */
11936 case 0x8: /* FMINNM */
11937 case 0x9: /* FMLS */
11938 case 0xa: /* FSUB */
11939 case 0xe: /* FMIN */
11940 case 0xf: /* FRSQRTS */
11941 case 0x13: /* FMUL */
11942 case 0x14: /* FCMGE */
11943 case 0x15: /* FACGE */
11944 case 0x17: /* FDIV */
11945 case 0x1a: /* FABD */
11946 case 0x1c: /* FCMGT */
11947 case 0x1d: /* FACGT */
11950 case 0x10: /* FMAXNMP */
11951 case 0x12: /* FADDP */
11952 case 0x16: /* FMAXP */
11953 case 0x18: /* FMINNMP */
11954 case 0x1e: /* FMINP */
11958 unallocated_encoding(s
);
11962 if (!dc_isar_feature(aa64_fp16
, s
)) {
11963 unallocated_encoding(s
);
11967 if (!fp_access_check(s
)) {
11971 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
11974 int maxpass
= is_q
? 8 : 4;
11975 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11976 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11977 TCGv_i32 tcg_res
[8];
11979 for (pass
= 0; pass
< maxpass
; pass
++) {
11980 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11981 int passelt
= (pass
<< 1) & (maxpass
- 1);
11983 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11984 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11985 tcg_res
[pass
] = tcg_temp_new_i32();
11987 switch (fpopcode
) {
11988 case 0x10: /* FMAXNMP */
11989 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11992 case 0x12: /* FADDP */
11993 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11995 case 0x16: /* FMAXP */
11996 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11998 case 0x18: /* FMINNMP */
11999 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12002 case 0x1e: /* FMINP */
12003 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12006 g_assert_not_reached();
12010 for (pass
= 0; pass
< maxpass
; pass
++) {
12011 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12012 tcg_temp_free_i32(tcg_res
[pass
]);
12015 tcg_temp_free_i32(tcg_op1
);
12016 tcg_temp_free_i32(tcg_op2
);
12019 for (pass
= 0; pass
< elements
; pass
++) {
12020 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12021 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12022 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12024 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12025 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12027 switch (fpopcode
) {
12028 case 0x0: /* FMAXNM */
12029 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12031 case 0x1: /* FMLA */
12032 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12033 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12036 case 0x2: /* FADD */
12037 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12039 case 0x3: /* FMULX */
12040 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12042 case 0x4: /* FCMEQ */
12043 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12045 case 0x6: /* FMAX */
12046 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12048 case 0x7: /* FRECPS */
12049 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12051 case 0x8: /* FMINNM */
12052 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12054 case 0x9: /* FMLS */
12055 /* As usual for ARM, separate negation for fused multiply-add */
12056 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12057 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12058 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12061 case 0xa: /* FSUB */
12062 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12064 case 0xe: /* FMIN */
12065 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12067 case 0xf: /* FRSQRTS */
12068 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12070 case 0x13: /* FMUL */
12071 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12073 case 0x14: /* FCMGE */
12074 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12076 case 0x15: /* FACGE */
12077 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12079 case 0x17: /* FDIV */
12080 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12082 case 0x1a: /* FABD */
12083 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12084 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12086 case 0x1c: /* FCMGT */
12087 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12089 case 0x1d: /* FACGT */
12090 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12093 g_assert_not_reached();
12096 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12097 tcg_temp_free_i32(tcg_res
);
12098 tcg_temp_free_i32(tcg_op1
);
12099 tcg_temp_free_i32(tcg_op2
);
12103 tcg_temp_free_ptr(fpst
);
12105 clear_vec_high(s
, is_q
, rd
);
12108 /* AdvSIMD three same extra
12109 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12110 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12111 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12112 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12114 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12116 int rd
= extract32(insn
, 0, 5);
12117 int rn
= extract32(insn
, 5, 5);
12118 int opcode
= extract32(insn
, 11, 4);
12119 int rm
= extract32(insn
, 16, 5);
12120 int size
= extract32(insn
, 22, 2);
12121 bool u
= extract32(insn
, 29, 1);
12122 bool is_q
= extract32(insn
, 30, 1);
12126 switch (u
* 16 + opcode
) {
12127 case 0x10: /* SQRDMLAH (vector) */
12128 case 0x11: /* SQRDMLSH (vector) */
12129 if (size
!= 1 && size
!= 2) {
12130 unallocated_encoding(s
);
12133 feature
= dc_isar_feature(aa64_rdm
, s
);
12135 case 0x02: /* SDOT (vector) */
12136 case 0x12: /* UDOT (vector) */
12137 if (size
!= MO_32
) {
12138 unallocated_encoding(s
);
12141 feature
= dc_isar_feature(aa64_dp
, s
);
12143 case 0x03: /* USDOT */
12144 if (size
!= MO_32
) {
12145 unallocated_encoding(s
);
12148 feature
= dc_isar_feature(aa64_i8mm
, s
);
12150 case 0x04: /* SMMLA */
12151 case 0x14: /* UMMLA */
12152 case 0x05: /* USMMLA */
12153 if (!is_q
|| size
!= MO_32
) {
12154 unallocated_encoding(s
);
12157 feature
= dc_isar_feature(aa64_i8mm
, s
);
12159 case 0x18: /* FCMLA, #0 */
12160 case 0x19: /* FCMLA, #90 */
12161 case 0x1a: /* FCMLA, #180 */
12162 case 0x1b: /* FCMLA, #270 */
12163 case 0x1c: /* FCADD, #90 */
12164 case 0x1e: /* FCADD, #270 */
12166 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12167 || (size
== 3 && !is_q
)) {
12168 unallocated_encoding(s
);
12171 feature
= dc_isar_feature(aa64_fcma
, s
);
12173 case 0x1d: /* BFMMLA */
12174 if (size
!= MO_16
|| !is_q
) {
12175 unallocated_encoding(s
);
12178 feature
= dc_isar_feature(aa64_bf16
, s
);
12182 case 1: /* BFDOT */
12183 case 3: /* BFMLAL{B,T} */
12184 feature
= dc_isar_feature(aa64_bf16
, s
);
12187 unallocated_encoding(s
);
12192 unallocated_encoding(s
);
12196 unallocated_encoding(s
);
12199 if (!fp_access_check(s
)) {
12204 case 0x0: /* SQRDMLAH (vector) */
12205 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12208 case 0x1: /* SQRDMLSH (vector) */
12209 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12212 case 0x2: /* SDOT / UDOT */
12213 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
12214 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12217 case 0x3: /* USDOT */
12218 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
12221 case 0x04: /* SMMLA, UMMLA */
12222 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
12223 u
? gen_helper_gvec_ummla_b
12224 : gen_helper_gvec_smmla_b
);
12226 case 0x05: /* USMMLA */
12227 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
12230 case 0x8: /* FCMLA, #0 */
12231 case 0x9: /* FCMLA, #90 */
12232 case 0xa: /* FCMLA, #180 */
12233 case 0xb: /* FCMLA, #270 */
12234 rot
= extract32(opcode
, 0, 2);
12237 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
12238 gen_helper_gvec_fcmlah
);
12241 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12242 gen_helper_gvec_fcmlas
);
12245 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12246 gen_helper_gvec_fcmlad
);
12249 g_assert_not_reached();
12253 case 0xc: /* FCADD, #90 */
12254 case 0xe: /* FCADD, #270 */
12255 rot
= extract32(opcode
, 1, 1);
12258 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12259 gen_helper_gvec_fcaddh
);
12262 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12263 gen_helper_gvec_fcadds
);
12266 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12267 gen_helper_gvec_fcaddd
);
12270 g_assert_not_reached();
12274 case 0xd: /* BFMMLA */
12275 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfmmla
);
12279 case 1: /* BFDOT */
12280 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfdot
);
12282 case 3: /* BFMLAL{B,T} */
12283 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, false, is_q
,
12284 gen_helper_gvec_bfmlal
);
12287 g_assert_not_reached();
12292 g_assert_not_reached();
12296 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12297 int size
, int rn
, int rd
)
12299 /* Handle 2-reg-misc ops which are widening (so each size element
12300 * in the source becomes a 2*size element in the destination.
12301 * The only instruction like this is FCVTL.
12306 /* 32 -> 64 bit fp conversion */
12307 TCGv_i64 tcg_res
[2];
12308 int srcelt
= is_q
? 2 : 0;
12310 for (pass
= 0; pass
< 2; pass
++) {
12311 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12312 tcg_res
[pass
] = tcg_temp_new_i64();
12314 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12315 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12316 tcg_temp_free_i32(tcg_op
);
12318 for (pass
= 0; pass
< 2; pass
++) {
12319 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12320 tcg_temp_free_i64(tcg_res
[pass
]);
12323 /* 16 -> 32 bit fp conversion */
12324 int srcelt
= is_q
? 4 : 0;
12325 TCGv_i32 tcg_res
[4];
12326 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12327 TCGv_i32 ahp
= get_ahp_flag();
12329 for (pass
= 0; pass
< 4; pass
++) {
12330 tcg_res
[pass
] = tcg_temp_new_i32();
12332 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12333 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12336 for (pass
= 0; pass
< 4; pass
++) {
12337 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12338 tcg_temp_free_i32(tcg_res
[pass
]);
12341 tcg_temp_free_ptr(fpst
);
12342 tcg_temp_free_i32(ahp
);
12346 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12347 bool is_q
, int size
, int rn
, int rd
)
12349 int op
= (opcode
<< 1) | u
;
12350 int opsz
= op
+ size
;
12351 int grp_size
= 3 - opsz
;
12352 int dsize
= is_q
? 128 : 64;
12356 unallocated_encoding(s
);
12360 if (!fp_access_check(s
)) {
12365 /* Special case bytes, use bswap op on each group of elements */
12366 int groups
= dsize
/ (8 << grp_size
);
12368 for (i
= 0; i
< groups
; i
++) {
12369 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12371 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12372 switch (grp_size
) {
12374 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
12377 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
12380 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12383 g_assert_not_reached();
12385 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12386 tcg_temp_free_i64(tcg_tmp
);
12388 clear_vec_high(s
, is_q
, rd
);
12390 int revmask
= (1 << grp_size
) - 1;
12391 int esize
= 8 << size
;
12392 int elements
= dsize
/ esize
;
12393 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12394 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12395 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12397 for (i
= 0; i
< elements
; i
++) {
12398 int e_rev
= (i
& 0xf) ^ revmask
;
12399 int off
= e_rev
* esize
;
12400 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12402 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12403 tcg_rn
, off
- 64, esize
);
12405 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12408 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12409 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12411 tcg_temp_free_i64(tcg_rd_hi
);
12412 tcg_temp_free_i64(tcg_rd
);
12413 tcg_temp_free_i64(tcg_rn
);
12417 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12418 bool is_q
, int size
, int rn
, int rd
)
12420 /* Implement the pairwise operations from 2-misc:
12421 * SADDLP, UADDLP, SADALP, UADALP.
12422 * These all add pairs of elements in the input to produce a
12423 * double-width result element in the output (possibly accumulating).
12425 bool accum
= (opcode
== 0x6);
12426 int maxpass
= is_q
? 2 : 1;
12428 TCGv_i64 tcg_res
[2];
12431 /* 32 + 32 -> 64 op */
12432 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12434 for (pass
= 0; pass
< maxpass
; pass
++) {
12435 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12436 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12438 tcg_res
[pass
] = tcg_temp_new_i64();
12440 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12441 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12442 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12444 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12445 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12448 tcg_temp_free_i64(tcg_op1
);
12449 tcg_temp_free_i64(tcg_op2
);
12452 for (pass
= 0; pass
< maxpass
; pass
++) {
12453 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12454 NeonGenOne64OpFn
*genfn
;
12455 static NeonGenOne64OpFn
* const fns
[2][2] = {
12456 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12457 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12460 genfn
= fns
[size
][u
];
12462 tcg_res
[pass
] = tcg_temp_new_i64();
12464 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12465 genfn(tcg_res
[pass
], tcg_op
);
12468 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12470 gen_helper_neon_addl_u16(tcg_res
[pass
],
12471 tcg_res
[pass
], tcg_op
);
12473 gen_helper_neon_addl_u32(tcg_res
[pass
],
12474 tcg_res
[pass
], tcg_op
);
12477 tcg_temp_free_i64(tcg_op
);
12481 tcg_res
[1] = tcg_const_i64(0);
12483 for (pass
= 0; pass
< 2; pass
++) {
12484 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12485 tcg_temp_free_i64(tcg_res
[pass
]);
12489 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12491 /* Implement SHLL and SHLL2 */
12493 int part
= is_q
? 2 : 0;
12494 TCGv_i64 tcg_res
[2];
12496 for (pass
= 0; pass
< 2; pass
++) {
12497 static NeonGenWidenFn
* const widenfns
[3] = {
12498 gen_helper_neon_widen_u8
,
12499 gen_helper_neon_widen_u16
,
12500 tcg_gen_extu_i32_i64
,
12502 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12503 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12505 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12506 tcg_res
[pass
] = tcg_temp_new_i64();
12507 widenfn(tcg_res
[pass
], tcg_op
);
12508 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12510 tcg_temp_free_i32(tcg_op
);
12513 for (pass
= 0; pass
< 2; pass
++) {
12514 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12515 tcg_temp_free_i64(tcg_res
[pass
]);
12519 /* AdvSIMD two reg misc
12520 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12521 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12522 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12523 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12525 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12527 int size
= extract32(insn
, 22, 2);
12528 int opcode
= extract32(insn
, 12, 5);
12529 bool u
= extract32(insn
, 29, 1);
12530 bool is_q
= extract32(insn
, 30, 1);
12531 int rn
= extract32(insn
, 5, 5);
12532 int rd
= extract32(insn
, 0, 5);
12533 bool need_fpstatus
= false;
12534 bool need_rmode
= false;
12536 TCGv_i32 tcg_rmode
;
12537 TCGv_ptr tcg_fpstatus
;
12540 case 0x0: /* REV64, REV32 */
12541 case 0x1: /* REV16 */
12542 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12544 case 0x5: /* CNT, NOT, RBIT */
12545 if (u
&& size
== 0) {
12548 } else if (u
&& size
== 1) {
12551 } else if (!u
&& size
== 0) {
12555 unallocated_encoding(s
);
12557 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12558 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12560 unallocated_encoding(s
);
12563 if (!fp_access_check(s
)) {
12567 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12569 case 0x4: /* CLS, CLZ */
12571 unallocated_encoding(s
);
12575 case 0x2: /* SADDLP, UADDLP */
12576 case 0x6: /* SADALP, UADALP */
12578 unallocated_encoding(s
);
12581 if (!fp_access_check(s
)) {
12584 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12586 case 0x13: /* SHLL, SHLL2 */
12587 if (u
== 0 || size
== 3) {
12588 unallocated_encoding(s
);
12591 if (!fp_access_check(s
)) {
12594 handle_shll(s
, is_q
, size
, rn
, rd
);
12596 case 0xa: /* CMLT */
12598 unallocated_encoding(s
);
12602 case 0x8: /* CMGT, CMGE */
12603 case 0x9: /* CMEQ, CMLE */
12604 case 0xb: /* ABS, NEG */
12605 if (size
== 3 && !is_q
) {
12606 unallocated_encoding(s
);
12610 case 0x3: /* SUQADD, USQADD */
12611 if (size
== 3 && !is_q
) {
12612 unallocated_encoding(s
);
12615 if (!fp_access_check(s
)) {
12618 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12620 case 0x7: /* SQABS, SQNEG */
12621 if (size
== 3 && !is_q
) {
12622 unallocated_encoding(s
);
12627 case 0x16 ... 0x1f:
12629 /* Floating point: U, size[1] and opcode indicate operation;
12630 * size[0] indicates single or double precision.
12632 int is_double
= extract32(size
, 0, 1);
12633 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12634 size
= is_double
? 3 : 2;
12636 case 0x2f: /* FABS */
12637 case 0x6f: /* FNEG */
12638 if (size
== 3 && !is_q
) {
12639 unallocated_encoding(s
);
12643 case 0x1d: /* SCVTF */
12644 case 0x5d: /* UCVTF */
12646 bool is_signed
= (opcode
== 0x1d) ? true : false;
12647 int elements
= is_double
? 2 : is_q
? 4 : 2;
12648 if (is_double
&& !is_q
) {
12649 unallocated_encoding(s
);
12652 if (!fp_access_check(s
)) {
12655 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12658 case 0x2c: /* FCMGT (zero) */
12659 case 0x2d: /* FCMEQ (zero) */
12660 case 0x2e: /* FCMLT (zero) */
12661 case 0x6c: /* FCMGE (zero) */
12662 case 0x6d: /* FCMLE (zero) */
12663 if (size
== 3 && !is_q
) {
12664 unallocated_encoding(s
);
12667 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12669 case 0x7f: /* FSQRT */
12670 if (size
== 3 && !is_q
) {
12671 unallocated_encoding(s
);
12675 case 0x1a: /* FCVTNS */
12676 case 0x1b: /* FCVTMS */
12677 case 0x3a: /* FCVTPS */
12678 case 0x3b: /* FCVTZS */
12679 case 0x5a: /* FCVTNU */
12680 case 0x5b: /* FCVTMU */
12681 case 0x7a: /* FCVTPU */
12682 case 0x7b: /* FCVTZU */
12683 need_fpstatus
= true;
12685 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12686 if (size
== 3 && !is_q
) {
12687 unallocated_encoding(s
);
12691 case 0x5c: /* FCVTAU */
12692 case 0x1c: /* FCVTAS */
12693 need_fpstatus
= true;
12695 rmode
= FPROUNDING_TIEAWAY
;
12696 if (size
== 3 && !is_q
) {
12697 unallocated_encoding(s
);
12701 case 0x3c: /* URECPE */
12703 unallocated_encoding(s
);
12707 case 0x3d: /* FRECPE */
12708 case 0x7d: /* FRSQRTE */
12709 if (size
== 3 && !is_q
) {
12710 unallocated_encoding(s
);
12713 if (!fp_access_check(s
)) {
12716 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12718 case 0x56: /* FCVTXN, FCVTXN2 */
12720 unallocated_encoding(s
);
12724 case 0x16: /* FCVTN, FCVTN2 */
12725 /* handle_2misc_narrow does a 2*size -> size operation, but these
12726 * instructions encode the source size rather than dest size.
12728 if (!fp_access_check(s
)) {
12731 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12733 case 0x36: /* BFCVTN, BFCVTN2 */
12734 if (!dc_isar_feature(aa64_bf16
, s
) || size
!= 2) {
12735 unallocated_encoding(s
);
12738 if (!fp_access_check(s
)) {
12741 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12743 case 0x17: /* FCVTL, FCVTL2 */
12744 if (!fp_access_check(s
)) {
12747 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12749 case 0x18: /* FRINTN */
12750 case 0x19: /* FRINTM */
12751 case 0x38: /* FRINTP */
12752 case 0x39: /* FRINTZ */
12754 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12756 case 0x59: /* FRINTX */
12757 case 0x79: /* FRINTI */
12758 need_fpstatus
= true;
12759 if (size
== 3 && !is_q
) {
12760 unallocated_encoding(s
);
12764 case 0x58: /* FRINTA */
12766 rmode
= FPROUNDING_TIEAWAY
;
12767 need_fpstatus
= true;
12768 if (size
== 3 && !is_q
) {
12769 unallocated_encoding(s
);
12773 case 0x7c: /* URSQRTE */
12775 unallocated_encoding(s
);
12779 case 0x1e: /* FRINT32Z */
12780 case 0x1f: /* FRINT64Z */
12782 rmode
= FPROUNDING_ZERO
;
12784 case 0x5e: /* FRINT32X */
12785 case 0x5f: /* FRINT64X */
12786 need_fpstatus
= true;
12787 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12788 unallocated_encoding(s
);
12793 unallocated_encoding(s
);
12799 unallocated_encoding(s
);
12803 if (!fp_access_check(s
)) {
12807 if (need_fpstatus
|| need_rmode
) {
12808 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12810 tcg_fpstatus
= NULL
;
12813 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12814 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12821 if (u
&& size
== 0) { /* NOT */
12822 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12826 case 0x8: /* CMGT, CMGE */
12828 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12830 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12833 case 0x9: /* CMEQ, CMLE */
12835 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12837 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12840 case 0xa: /* CMLT */
12841 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12844 if (u
) { /* ABS, NEG */
12845 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12847 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12853 /* All 64-bit element operations can be shared with scalar 2misc */
12856 /* Coverity claims (size == 3 && !is_q) has been eliminated
12857 * from all paths leading to here.
12859 tcg_debug_assert(is_q
);
12860 for (pass
= 0; pass
< 2; pass
++) {
12861 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12862 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12864 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12866 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12867 tcg_rmode
, tcg_fpstatus
);
12869 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12871 tcg_temp_free_i64(tcg_res
);
12872 tcg_temp_free_i64(tcg_op
);
12877 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12878 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12879 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12881 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12884 /* Special cases for 32 bit elements */
12886 case 0x4: /* CLS */
12888 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12890 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12893 case 0x7: /* SQABS, SQNEG */
12895 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12897 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12900 case 0x2f: /* FABS */
12901 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12903 case 0x6f: /* FNEG */
12904 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12906 case 0x7f: /* FSQRT */
12907 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12909 case 0x1a: /* FCVTNS */
12910 case 0x1b: /* FCVTMS */
12911 case 0x1c: /* FCVTAS */
12912 case 0x3a: /* FCVTPS */
12913 case 0x3b: /* FCVTZS */
12915 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12916 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12917 tcg_shift
, tcg_fpstatus
);
12918 tcg_temp_free_i32(tcg_shift
);
12921 case 0x5a: /* FCVTNU */
12922 case 0x5b: /* FCVTMU */
12923 case 0x5c: /* FCVTAU */
12924 case 0x7a: /* FCVTPU */
12925 case 0x7b: /* FCVTZU */
12927 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12928 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12929 tcg_shift
, tcg_fpstatus
);
12930 tcg_temp_free_i32(tcg_shift
);
12933 case 0x18: /* FRINTN */
12934 case 0x19: /* FRINTM */
12935 case 0x38: /* FRINTP */
12936 case 0x39: /* FRINTZ */
12937 case 0x58: /* FRINTA */
12938 case 0x79: /* FRINTI */
12939 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12941 case 0x59: /* FRINTX */
12942 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12944 case 0x7c: /* URSQRTE */
12945 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12947 case 0x1e: /* FRINT32Z */
12948 case 0x5e: /* FRINT32X */
12949 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12951 case 0x1f: /* FRINT64Z */
12952 case 0x5f: /* FRINT64X */
12953 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12956 g_assert_not_reached();
12959 /* Use helpers for 8 and 16 bit elements */
12961 case 0x5: /* CNT, RBIT */
12962 /* For these two insns size is part of the opcode specifier
12963 * (handled earlier); they always operate on byte elements.
12966 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12968 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12971 case 0x7: /* SQABS, SQNEG */
12973 NeonGenOneOpEnvFn
*genfn
;
12974 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12975 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12976 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12978 genfn
= fns
[size
][u
];
12979 genfn(tcg_res
, cpu_env
, tcg_op
);
12982 case 0x4: /* CLS, CLZ */
12985 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12987 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12991 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12993 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12998 g_assert_not_reached();
13002 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13004 tcg_temp_free_i32(tcg_res
);
13005 tcg_temp_free_i32(tcg_op
);
13008 clear_vec_high(s
, is_q
, rd
);
13011 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13012 tcg_temp_free_i32(tcg_rmode
);
13014 if (need_fpstatus
) {
13015 tcg_temp_free_ptr(tcg_fpstatus
);
13019 /* AdvSIMD [scalar] two register miscellaneous (FP16)
13021 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
13022 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13023 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
13024 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13025 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
13026 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
13028 * This actually covers two groups where scalar access is governed by
13029 * bit 28. A bunch of the instructions (float to integral) only exist
13030 * in the vector form and are un-allocated for the scalar decode. Also
13031 * in the scalar decode Q is always 1.
13033 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
13035 int fpop
, opcode
, a
, u
;
13039 bool only_in_vector
= false;
13042 TCGv_i32 tcg_rmode
= NULL
;
13043 TCGv_ptr tcg_fpstatus
= NULL
;
13044 bool need_rmode
= false;
13045 bool need_fpst
= true;
13048 if (!dc_isar_feature(aa64_fp16
, s
)) {
13049 unallocated_encoding(s
);
13053 rd
= extract32(insn
, 0, 5);
13054 rn
= extract32(insn
, 5, 5);
13056 a
= extract32(insn
, 23, 1);
13057 u
= extract32(insn
, 29, 1);
13058 is_scalar
= extract32(insn
, 28, 1);
13059 is_q
= extract32(insn
, 30, 1);
13061 opcode
= extract32(insn
, 12, 5);
13062 fpop
= deposit32(opcode
, 5, 1, a
);
13063 fpop
= deposit32(fpop
, 6, 1, u
);
13066 case 0x1d: /* SCVTF */
13067 case 0x5d: /* UCVTF */
13074 elements
= (is_q
? 8 : 4);
13077 if (!fp_access_check(s
)) {
13080 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13084 case 0x2c: /* FCMGT (zero) */
13085 case 0x2d: /* FCMEQ (zero) */
13086 case 0x2e: /* FCMLT (zero) */
13087 case 0x6c: /* FCMGE (zero) */
13088 case 0x6d: /* FCMLE (zero) */
13089 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13091 case 0x3d: /* FRECPE */
13092 case 0x3f: /* FRECPX */
13094 case 0x18: /* FRINTN */
13096 only_in_vector
= true;
13097 rmode
= FPROUNDING_TIEEVEN
;
13099 case 0x19: /* FRINTM */
13101 only_in_vector
= true;
13102 rmode
= FPROUNDING_NEGINF
;
13104 case 0x38: /* FRINTP */
13106 only_in_vector
= true;
13107 rmode
= FPROUNDING_POSINF
;
13109 case 0x39: /* FRINTZ */
13111 only_in_vector
= true;
13112 rmode
= FPROUNDING_ZERO
;
13114 case 0x58: /* FRINTA */
13116 only_in_vector
= true;
13117 rmode
= FPROUNDING_TIEAWAY
;
13119 case 0x59: /* FRINTX */
13120 case 0x79: /* FRINTI */
13121 only_in_vector
= true;
13122 /* current rounding mode */
13124 case 0x1a: /* FCVTNS */
13126 rmode
= FPROUNDING_TIEEVEN
;
13128 case 0x1b: /* FCVTMS */
13130 rmode
= FPROUNDING_NEGINF
;
13132 case 0x1c: /* FCVTAS */
13134 rmode
= FPROUNDING_TIEAWAY
;
13136 case 0x3a: /* FCVTPS */
13138 rmode
= FPROUNDING_POSINF
;
13140 case 0x3b: /* FCVTZS */
13142 rmode
= FPROUNDING_ZERO
;
13144 case 0x5a: /* FCVTNU */
13146 rmode
= FPROUNDING_TIEEVEN
;
13148 case 0x5b: /* FCVTMU */
13150 rmode
= FPROUNDING_NEGINF
;
13152 case 0x5c: /* FCVTAU */
13154 rmode
= FPROUNDING_TIEAWAY
;
13156 case 0x7a: /* FCVTPU */
13158 rmode
= FPROUNDING_POSINF
;
13160 case 0x7b: /* FCVTZU */
13162 rmode
= FPROUNDING_ZERO
;
13164 case 0x2f: /* FABS */
13165 case 0x6f: /* FNEG */
13168 case 0x7d: /* FRSQRTE */
13169 case 0x7f: /* FSQRT (vector) */
13172 unallocated_encoding(s
);
13177 /* Check additional constraints for the scalar encoding */
13180 unallocated_encoding(s
);
13183 /* FRINTxx is only in the vector form */
13184 if (only_in_vector
) {
13185 unallocated_encoding(s
);
13190 if (!fp_access_check(s
)) {
13194 if (need_rmode
|| need_fpst
) {
13195 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13199 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13200 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13204 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13205 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13208 case 0x1a: /* FCVTNS */
13209 case 0x1b: /* FCVTMS */
13210 case 0x1c: /* FCVTAS */
13211 case 0x3a: /* FCVTPS */
13212 case 0x3b: /* FCVTZS */
13213 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13215 case 0x3d: /* FRECPE */
13216 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13218 case 0x3f: /* FRECPX */
13219 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13221 case 0x5a: /* FCVTNU */
13222 case 0x5b: /* FCVTMU */
13223 case 0x5c: /* FCVTAU */
13224 case 0x7a: /* FCVTPU */
13225 case 0x7b: /* FCVTZU */
13226 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13228 case 0x6f: /* FNEG */
13229 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13231 case 0x7d: /* FRSQRTE */
13232 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13235 g_assert_not_reached();
13238 /* limit any sign extension going on */
13239 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13240 write_fp_sreg(s
, rd
, tcg_res
);
13242 tcg_temp_free_i32(tcg_res
);
13243 tcg_temp_free_i32(tcg_op
);
13245 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13246 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13247 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13249 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13252 case 0x1a: /* FCVTNS */
13253 case 0x1b: /* FCVTMS */
13254 case 0x1c: /* FCVTAS */
13255 case 0x3a: /* FCVTPS */
13256 case 0x3b: /* FCVTZS */
13257 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13259 case 0x3d: /* FRECPE */
13260 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13262 case 0x5a: /* FCVTNU */
13263 case 0x5b: /* FCVTMU */
13264 case 0x5c: /* FCVTAU */
13265 case 0x7a: /* FCVTPU */
13266 case 0x7b: /* FCVTZU */
13267 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13269 case 0x18: /* FRINTN */
13270 case 0x19: /* FRINTM */
13271 case 0x38: /* FRINTP */
13272 case 0x39: /* FRINTZ */
13273 case 0x58: /* FRINTA */
13274 case 0x79: /* FRINTI */
13275 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13277 case 0x59: /* FRINTX */
13278 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13280 case 0x2f: /* FABS */
13281 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13283 case 0x6f: /* FNEG */
13284 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13286 case 0x7d: /* FRSQRTE */
13287 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13289 case 0x7f: /* FSQRT */
13290 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13293 g_assert_not_reached();
13296 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13298 tcg_temp_free_i32(tcg_res
);
13299 tcg_temp_free_i32(tcg_op
);
13302 clear_vec_high(s
, is_q
, rd
);
13306 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13307 tcg_temp_free_i32(tcg_rmode
);
13310 if (tcg_fpstatus
) {
13311 tcg_temp_free_ptr(tcg_fpstatus
);
13315 /* AdvSIMD scalar x indexed element
13316 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13317 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13318 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13319 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13320 * AdvSIMD vector x indexed element
13321 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13322 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13323 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13324 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13326 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13328 /* This encoding has two kinds of instruction:
13329 * normal, where we perform elt x idxelt => elt for each
13330 * element in the vector
13331 * long, where we perform elt x idxelt and generate a result of
13332 * double the width of the input element
13333 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13335 bool is_scalar
= extract32(insn
, 28, 1);
13336 bool is_q
= extract32(insn
, 30, 1);
13337 bool u
= extract32(insn
, 29, 1);
13338 int size
= extract32(insn
, 22, 2);
13339 int l
= extract32(insn
, 21, 1);
13340 int m
= extract32(insn
, 20, 1);
13341 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13342 int rm
= extract32(insn
, 16, 4);
13343 int opcode
= extract32(insn
, 12, 4);
13344 int h
= extract32(insn
, 11, 1);
13345 int rn
= extract32(insn
, 5, 5);
13346 int rd
= extract32(insn
, 0, 5);
13347 bool is_long
= false;
13349 bool is_fp16
= false;
13353 switch (16 * u
+ opcode
) {
13354 case 0x08: /* MUL */
13355 case 0x10: /* MLA */
13356 case 0x14: /* MLS */
13358 unallocated_encoding(s
);
13362 case 0x02: /* SMLAL, SMLAL2 */
13363 case 0x12: /* UMLAL, UMLAL2 */
13364 case 0x06: /* SMLSL, SMLSL2 */
13365 case 0x16: /* UMLSL, UMLSL2 */
13366 case 0x0a: /* SMULL, SMULL2 */
13367 case 0x1a: /* UMULL, UMULL2 */
13369 unallocated_encoding(s
);
13374 case 0x03: /* SQDMLAL, SQDMLAL2 */
13375 case 0x07: /* SQDMLSL, SQDMLSL2 */
13376 case 0x0b: /* SQDMULL, SQDMULL2 */
13379 case 0x0c: /* SQDMULH */
13380 case 0x0d: /* SQRDMULH */
13382 case 0x01: /* FMLA */
13383 case 0x05: /* FMLS */
13384 case 0x09: /* FMUL */
13385 case 0x19: /* FMULX */
13388 case 0x1d: /* SQRDMLAH */
13389 case 0x1f: /* SQRDMLSH */
13390 if (!dc_isar_feature(aa64_rdm
, s
)) {
13391 unallocated_encoding(s
);
13395 case 0x0e: /* SDOT */
13396 case 0x1e: /* UDOT */
13397 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13398 unallocated_encoding(s
);
13404 case 0: /* SUDOT */
13405 case 2: /* USDOT */
13406 if (is_scalar
|| !dc_isar_feature(aa64_i8mm
, s
)) {
13407 unallocated_encoding(s
);
13412 case 1: /* BFDOT */
13413 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
13414 unallocated_encoding(s
);
13419 case 3: /* BFMLAL{B,T} */
13420 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
13421 unallocated_encoding(s
);
13424 /* can't set is_fp without other incorrect size checks */
13428 unallocated_encoding(s
);
13432 case 0x11: /* FCMLA #0 */
13433 case 0x13: /* FCMLA #90 */
13434 case 0x15: /* FCMLA #180 */
13435 case 0x17: /* FCMLA #270 */
13436 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13437 unallocated_encoding(s
);
13442 case 0x00: /* FMLAL */
13443 case 0x04: /* FMLSL */
13444 case 0x18: /* FMLAL2 */
13445 case 0x1c: /* FMLSL2 */
13446 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13447 unallocated_encoding(s
);
13451 /* is_fp, but we pass cpu_env not fp_status. */
13454 unallocated_encoding(s
);
13459 case 1: /* normal fp */
13460 /* convert insn encoded size to MemOp size */
13462 case 0: /* half-precision */
13466 case MO_32
: /* single precision */
13467 case MO_64
: /* double precision */
13470 unallocated_encoding(s
);
13475 case 2: /* complex fp */
13476 /* Each indexable element is a complex pair. */
13481 unallocated_encoding(s
);
13489 unallocated_encoding(s
);
13494 default: /* integer */
13498 unallocated_encoding(s
);
13503 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13504 unallocated_encoding(s
);
13508 /* Given MemOp size, adjust register and indexing. */
13511 index
= h
<< 2 | l
<< 1 | m
;
13514 index
= h
<< 1 | l
;
13519 unallocated_encoding(s
);
13526 g_assert_not_reached();
13529 if (!fp_access_check(s
)) {
13534 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13539 switch (16 * u
+ opcode
) {
13540 case 0x0e: /* SDOT */
13541 case 0x1e: /* UDOT */
13542 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13543 u
? gen_helper_gvec_udot_idx_b
13544 : gen_helper_gvec_sdot_idx_b
);
13547 switch (extract32(insn
, 22, 2)) {
13548 case 0: /* SUDOT */
13549 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13550 gen_helper_gvec_sudot_idx_b
);
13552 case 1: /* BFDOT */
13553 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13554 gen_helper_gvec_bfdot_idx
);
13556 case 2: /* USDOT */
13557 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13558 gen_helper_gvec_usdot_idx_b
);
13560 case 3: /* BFMLAL{B,T} */
13561 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, 0, (index
<< 1) | is_q
,
13562 gen_helper_gvec_bfmlal_idx
);
13565 g_assert_not_reached();
13566 case 0x11: /* FCMLA #0 */
13567 case 0x13: /* FCMLA #90 */
13568 case 0x15: /* FCMLA #180 */
13569 case 0x17: /* FCMLA #270 */
13571 int rot
= extract32(insn
, 13, 2);
13572 int data
= (index
<< 2) | rot
;
13573 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
13574 vec_full_reg_offset(s
, rn
),
13575 vec_full_reg_offset(s
, rm
),
13576 vec_full_reg_offset(s
, rd
), fpst
,
13577 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13579 ? gen_helper_gvec_fcmlas_idx
13580 : gen_helper_gvec_fcmlah_idx
);
13581 tcg_temp_free_ptr(fpst
);
13585 case 0x00: /* FMLAL */
13586 case 0x04: /* FMLSL */
13587 case 0x18: /* FMLAL2 */
13588 case 0x1c: /* FMLSL2 */
13590 int is_s
= extract32(opcode
, 2, 1);
13592 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13593 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13594 vec_full_reg_offset(s
, rn
),
13595 vec_full_reg_offset(s
, rm
), cpu_env
,
13596 is_q
? 16 : 8, vec_full_reg_size(s
),
13597 data
, gen_helper_gvec_fmlal_idx_a64
);
13601 case 0x08: /* MUL */
13602 if (!is_long
&& !is_scalar
) {
13603 static gen_helper_gvec_3
* const fns
[3] = {
13604 gen_helper_gvec_mul_idx_h
,
13605 gen_helper_gvec_mul_idx_s
,
13606 gen_helper_gvec_mul_idx_d
,
13608 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13609 vec_full_reg_offset(s
, rn
),
13610 vec_full_reg_offset(s
, rm
),
13611 is_q
? 16 : 8, vec_full_reg_size(s
),
13612 index
, fns
[size
- 1]);
13617 case 0x10: /* MLA */
13618 if (!is_long
&& !is_scalar
) {
13619 static gen_helper_gvec_4
* const fns
[3] = {
13620 gen_helper_gvec_mla_idx_h
,
13621 gen_helper_gvec_mla_idx_s
,
13622 gen_helper_gvec_mla_idx_d
,
13624 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13625 vec_full_reg_offset(s
, rn
),
13626 vec_full_reg_offset(s
, rm
),
13627 vec_full_reg_offset(s
, rd
),
13628 is_q
? 16 : 8, vec_full_reg_size(s
),
13629 index
, fns
[size
- 1]);
13634 case 0x14: /* MLS */
13635 if (!is_long
&& !is_scalar
) {
13636 static gen_helper_gvec_4
* const fns
[3] = {
13637 gen_helper_gvec_mls_idx_h
,
13638 gen_helper_gvec_mls_idx_s
,
13639 gen_helper_gvec_mls_idx_d
,
13641 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13642 vec_full_reg_offset(s
, rn
),
13643 vec_full_reg_offset(s
, rm
),
13644 vec_full_reg_offset(s
, rd
),
13645 is_q
? 16 : 8, vec_full_reg_size(s
),
13646 index
, fns
[size
- 1]);
13653 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13656 assert(is_fp
&& is_q
&& !is_long
);
13658 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13660 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13661 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13662 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13664 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13666 switch (16 * u
+ opcode
) {
13667 case 0x05: /* FMLS */
13668 /* As usual for ARM, separate negation for fused multiply-add */
13669 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13671 case 0x01: /* FMLA */
13672 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13673 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13675 case 0x09: /* FMUL */
13676 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13678 case 0x19: /* FMULX */
13679 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13682 g_assert_not_reached();
13685 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13686 tcg_temp_free_i64(tcg_op
);
13687 tcg_temp_free_i64(tcg_res
);
13690 tcg_temp_free_i64(tcg_idx
);
13691 clear_vec_high(s
, !is_scalar
, rd
);
13692 } else if (!is_long
) {
13693 /* 32 bit floating point, or 16 or 32 bit integer.
13694 * For the 16 bit scalar case we use the usual Neon helpers and
13695 * rely on the fact that 0 op 0 == 0 with no side effects.
13697 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13698 int pass
, maxpasses
;
13703 maxpasses
= is_q
? 4 : 2;
13706 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13708 if (size
== 1 && !is_scalar
) {
13709 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13710 * the index into both halves of the 32 bit tcg_idx and then use
13711 * the usual Neon helpers.
13713 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13716 for (pass
= 0; pass
< maxpasses
; pass
++) {
13717 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13718 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13720 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13722 switch (16 * u
+ opcode
) {
13723 case 0x08: /* MUL */
13724 case 0x10: /* MLA */
13725 case 0x14: /* MLS */
13727 static NeonGenTwoOpFn
* const fns
[2][2] = {
13728 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13729 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13731 NeonGenTwoOpFn
*genfn
;
13732 bool is_sub
= opcode
== 0x4;
13735 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13737 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13739 if (opcode
== 0x8) {
13742 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13743 genfn
= fns
[size
- 1][is_sub
];
13744 genfn(tcg_res
, tcg_op
, tcg_res
);
13747 case 0x05: /* FMLS */
13748 case 0x01: /* FMLA */
13749 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13750 is_scalar
? size
: MO_32
);
13753 if (opcode
== 0x5) {
13754 /* As usual for ARM, separate negation for fused
13756 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13759 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13762 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13767 if (opcode
== 0x5) {
13768 /* As usual for ARM, separate negation for
13769 * fused multiply-add */
13770 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13772 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13776 g_assert_not_reached();
13779 case 0x09: /* FMUL */
13783 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13786 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13791 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13794 g_assert_not_reached();
13797 case 0x19: /* FMULX */
13801 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13804 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13809 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13812 g_assert_not_reached();
13815 case 0x0c: /* SQDMULH */
13817 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13820 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13824 case 0x0d: /* SQRDMULH */
13826 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13829 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13833 case 0x1d: /* SQRDMLAH */
13834 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13835 is_scalar
? size
: MO_32
);
13837 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13838 tcg_op
, tcg_idx
, tcg_res
);
13840 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13841 tcg_op
, tcg_idx
, tcg_res
);
13844 case 0x1f: /* SQRDMLSH */
13845 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13846 is_scalar
? size
: MO_32
);
13848 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13849 tcg_op
, tcg_idx
, tcg_res
);
13851 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13852 tcg_op
, tcg_idx
, tcg_res
);
13856 g_assert_not_reached();
13860 write_fp_sreg(s
, rd
, tcg_res
);
13862 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13865 tcg_temp_free_i32(tcg_op
);
13866 tcg_temp_free_i32(tcg_res
);
13869 tcg_temp_free_i32(tcg_idx
);
13870 clear_vec_high(s
, is_q
, rd
);
13872 /* long ops: 16x16->32 or 32x32->64 */
13873 TCGv_i64 tcg_res
[2];
13875 bool satop
= extract32(opcode
, 0, 1);
13876 MemOp memop
= MO_32
;
13883 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13885 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13887 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13888 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13889 TCGv_i64 tcg_passres
;
13895 passelt
= pass
+ (is_q
* 2);
13898 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13900 tcg_res
[pass
] = tcg_temp_new_i64();
13902 if (opcode
== 0xa || opcode
== 0xb) {
13903 /* Non-accumulating ops */
13904 tcg_passres
= tcg_res
[pass
];
13906 tcg_passres
= tcg_temp_new_i64();
13909 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13910 tcg_temp_free_i64(tcg_op
);
13913 /* saturating, doubling */
13914 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13915 tcg_passres
, tcg_passres
);
13918 if (opcode
== 0xa || opcode
== 0xb) {
13922 /* Accumulating op: handle accumulate step */
13923 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13926 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13927 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13929 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13930 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13932 case 0x7: /* SQDMLSL, SQDMLSL2 */
13933 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13935 case 0x3: /* SQDMLAL, SQDMLAL2 */
13936 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13941 g_assert_not_reached();
13943 tcg_temp_free_i64(tcg_passres
);
13945 tcg_temp_free_i64(tcg_idx
);
13947 clear_vec_high(s
, !is_scalar
, rd
);
13949 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13952 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13955 /* The simplest way to handle the 16x16 indexed ops is to
13956 * duplicate the index into both halves of the 32 bit tcg_idx
13957 * and then use the usual Neon helpers.
13959 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13962 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13963 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13964 TCGv_i64 tcg_passres
;
13967 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13969 read_vec_element_i32(s
, tcg_op
, rn
,
13970 pass
+ (is_q
* 2), MO_32
);
13973 tcg_res
[pass
] = tcg_temp_new_i64();
13975 if (opcode
== 0xa || opcode
== 0xb) {
13976 /* Non-accumulating ops */
13977 tcg_passres
= tcg_res
[pass
];
13979 tcg_passres
= tcg_temp_new_i64();
13982 if (memop
& MO_SIGN
) {
13983 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13985 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13988 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13989 tcg_passres
, tcg_passres
);
13991 tcg_temp_free_i32(tcg_op
);
13993 if (opcode
== 0xa || opcode
== 0xb) {
13997 /* Accumulating op: handle accumulate step */
13998 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
14001 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
14002 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
14005 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
14006 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
14009 case 0x7: /* SQDMLSL, SQDMLSL2 */
14010 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
14012 case 0x3: /* SQDMLAL, SQDMLAL2 */
14013 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
14018 g_assert_not_reached();
14020 tcg_temp_free_i64(tcg_passres
);
14022 tcg_temp_free_i32(tcg_idx
);
14025 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
14030 tcg_res
[1] = tcg_const_i64(0);
14033 for (pass
= 0; pass
< 2; pass
++) {
14034 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
14035 tcg_temp_free_i64(tcg_res
[pass
]);
14040 tcg_temp_free_ptr(fpst
);
14045 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14046 * +-----------------+------+-----------+--------+-----+------+------+
14047 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14048 * +-----------------+------+-----------+--------+-----+------+------+
14050 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
14052 int size
= extract32(insn
, 22, 2);
14053 int opcode
= extract32(insn
, 12, 5);
14054 int rn
= extract32(insn
, 5, 5);
14055 int rd
= extract32(insn
, 0, 5);
14057 gen_helper_gvec_2
*genfn2
= NULL
;
14058 gen_helper_gvec_3
*genfn3
= NULL
;
14060 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
14061 unallocated_encoding(s
);
14066 case 0x4: /* AESE */
14068 genfn3
= gen_helper_crypto_aese
;
14070 case 0x6: /* AESMC */
14072 genfn2
= gen_helper_crypto_aesmc
;
14074 case 0x5: /* AESD */
14076 genfn3
= gen_helper_crypto_aese
;
14078 case 0x7: /* AESIMC */
14080 genfn2
= gen_helper_crypto_aesmc
;
14083 unallocated_encoding(s
);
14087 if (!fp_access_check(s
)) {
14091 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
14093 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
14097 /* Crypto three-reg SHA
14098 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
14099 * +-----------------+------+---+------+---+--------+-----+------+------+
14100 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
14101 * +-----------------+------+---+------+---+--------+-----+------+------+
14103 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
14105 int size
= extract32(insn
, 22, 2);
14106 int opcode
= extract32(insn
, 12, 3);
14107 int rm
= extract32(insn
, 16, 5);
14108 int rn
= extract32(insn
, 5, 5);
14109 int rd
= extract32(insn
, 0, 5);
14110 gen_helper_gvec_3
*genfn
;
14114 unallocated_encoding(s
);
14119 case 0: /* SHA1C */
14120 genfn
= gen_helper_crypto_sha1c
;
14121 feature
= dc_isar_feature(aa64_sha1
, s
);
14123 case 1: /* SHA1P */
14124 genfn
= gen_helper_crypto_sha1p
;
14125 feature
= dc_isar_feature(aa64_sha1
, s
);
14127 case 2: /* SHA1M */
14128 genfn
= gen_helper_crypto_sha1m
;
14129 feature
= dc_isar_feature(aa64_sha1
, s
);
14131 case 3: /* SHA1SU0 */
14132 genfn
= gen_helper_crypto_sha1su0
;
14133 feature
= dc_isar_feature(aa64_sha1
, s
);
14135 case 4: /* SHA256H */
14136 genfn
= gen_helper_crypto_sha256h
;
14137 feature
= dc_isar_feature(aa64_sha256
, s
);
14139 case 5: /* SHA256H2 */
14140 genfn
= gen_helper_crypto_sha256h2
;
14141 feature
= dc_isar_feature(aa64_sha256
, s
);
14143 case 6: /* SHA256SU1 */
14144 genfn
= gen_helper_crypto_sha256su1
;
14145 feature
= dc_isar_feature(aa64_sha256
, s
);
14148 unallocated_encoding(s
);
14153 unallocated_encoding(s
);
14157 if (!fp_access_check(s
)) {
14160 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14163 /* Crypto two-reg SHA
14164 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14165 * +-----------------+------+-----------+--------+-----+------+------+
14166 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14167 * +-----------------+------+-----------+--------+-----+------+------+
14169 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14171 int size
= extract32(insn
, 22, 2);
14172 int opcode
= extract32(insn
, 12, 5);
14173 int rn
= extract32(insn
, 5, 5);
14174 int rd
= extract32(insn
, 0, 5);
14175 gen_helper_gvec_2
*genfn
;
14179 unallocated_encoding(s
);
14184 case 0: /* SHA1H */
14185 feature
= dc_isar_feature(aa64_sha1
, s
);
14186 genfn
= gen_helper_crypto_sha1h
;
14188 case 1: /* SHA1SU1 */
14189 feature
= dc_isar_feature(aa64_sha1
, s
);
14190 genfn
= gen_helper_crypto_sha1su1
;
14192 case 2: /* SHA256SU0 */
14193 feature
= dc_isar_feature(aa64_sha256
, s
);
14194 genfn
= gen_helper_crypto_sha256su0
;
14197 unallocated_encoding(s
);
14202 unallocated_encoding(s
);
14206 if (!fp_access_check(s
)) {
14209 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14212 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14214 tcg_gen_rotli_i64(d
, m
, 1);
14215 tcg_gen_xor_i64(d
, d
, n
);
14218 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14220 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14221 tcg_gen_xor_vec(vece
, d
, d
, n
);
14224 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14225 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14227 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14228 static const GVecGen3 op
= {
14229 .fni8
= gen_rax1_i64
,
14230 .fniv
= gen_rax1_vec
,
14231 .opt_opc
= vecop_list
,
14232 .fno
= gen_helper_crypto_rax1
,
14235 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14238 /* Crypto three-reg SHA512
14239 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14240 * +-----------------------+------+---+---+-----+--------+------+------+
14241 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14242 * +-----------------------+------+---+---+-----+--------+------+------+
14244 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14246 int opcode
= extract32(insn
, 10, 2);
14247 int o
= extract32(insn
, 14, 1);
14248 int rm
= extract32(insn
, 16, 5);
14249 int rn
= extract32(insn
, 5, 5);
14250 int rd
= extract32(insn
, 0, 5);
14252 gen_helper_gvec_3
*oolfn
= NULL
;
14253 GVecGen3Fn
*gvecfn
= NULL
;
14257 case 0: /* SHA512H */
14258 feature
= dc_isar_feature(aa64_sha512
, s
);
14259 oolfn
= gen_helper_crypto_sha512h
;
14261 case 1: /* SHA512H2 */
14262 feature
= dc_isar_feature(aa64_sha512
, s
);
14263 oolfn
= gen_helper_crypto_sha512h2
;
14265 case 2: /* SHA512SU1 */
14266 feature
= dc_isar_feature(aa64_sha512
, s
);
14267 oolfn
= gen_helper_crypto_sha512su1
;
14270 feature
= dc_isar_feature(aa64_sha3
, s
);
14271 gvecfn
= gen_gvec_rax1
;
14274 g_assert_not_reached();
14278 case 0: /* SM3PARTW1 */
14279 feature
= dc_isar_feature(aa64_sm3
, s
);
14280 oolfn
= gen_helper_crypto_sm3partw1
;
14282 case 1: /* SM3PARTW2 */
14283 feature
= dc_isar_feature(aa64_sm3
, s
);
14284 oolfn
= gen_helper_crypto_sm3partw2
;
14286 case 2: /* SM4EKEY */
14287 feature
= dc_isar_feature(aa64_sm4
, s
);
14288 oolfn
= gen_helper_crypto_sm4ekey
;
14291 unallocated_encoding(s
);
14297 unallocated_encoding(s
);
14301 if (!fp_access_check(s
)) {
14306 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14308 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14312 /* Crypto two-reg SHA512
14313 * 31 12 11 10 9 5 4 0
14314 * +-----------------------------------------+--------+------+------+
14315 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14316 * +-----------------------------------------+--------+------+------+
14318 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14320 int opcode
= extract32(insn
, 10, 2);
14321 int rn
= extract32(insn
, 5, 5);
14322 int rd
= extract32(insn
, 0, 5);
14326 case 0: /* SHA512SU0 */
14327 feature
= dc_isar_feature(aa64_sha512
, s
);
14330 feature
= dc_isar_feature(aa64_sm4
, s
);
14333 unallocated_encoding(s
);
14338 unallocated_encoding(s
);
14342 if (!fp_access_check(s
)) {
14347 case 0: /* SHA512SU0 */
14348 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14351 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14354 g_assert_not_reached();
14358 /* Crypto four-register
14359 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14360 * +-------------------+-----+------+---+------+------+------+
14361 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14362 * +-------------------+-----+------+---+------+------+------+
14364 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14366 int op0
= extract32(insn
, 21, 2);
14367 int rm
= extract32(insn
, 16, 5);
14368 int ra
= extract32(insn
, 10, 5);
14369 int rn
= extract32(insn
, 5, 5);
14370 int rd
= extract32(insn
, 0, 5);
14376 feature
= dc_isar_feature(aa64_sha3
, s
);
14378 case 2: /* SM3SS1 */
14379 feature
= dc_isar_feature(aa64_sm3
, s
);
14382 unallocated_encoding(s
);
14387 unallocated_encoding(s
);
14391 if (!fp_access_check(s
)) {
14396 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14399 tcg_op1
= tcg_temp_new_i64();
14400 tcg_op2
= tcg_temp_new_i64();
14401 tcg_op3
= tcg_temp_new_i64();
14402 tcg_res
[0] = tcg_temp_new_i64();
14403 tcg_res
[1] = tcg_temp_new_i64();
14405 for (pass
= 0; pass
< 2; pass
++) {
14406 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14407 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14408 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14412 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14415 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14417 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14419 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14420 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14422 tcg_temp_free_i64(tcg_op1
);
14423 tcg_temp_free_i64(tcg_op2
);
14424 tcg_temp_free_i64(tcg_op3
);
14425 tcg_temp_free_i64(tcg_res
[0]);
14426 tcg_temp_free_i64(tcg_res
[1]);
14428 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14430 tcg_op1
= tcg_temp_new_i32();
14431 tcg_op2
= tcg_temp_new_i32();
14432 tcg_op3
= tcg_temp_new_i32();
14433 tcg_res
= tcg_temp_new_i32();
14434 tcg_zero
= tcg_const_i32(0);
14436 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14437 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14438 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14440 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14441 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14442 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14443 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14445 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14446 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14447 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14448 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14450 tcg_temp_free_i32(tcg_op1
);
14451 tcg_temp_free_i32(tcg_op2
);
14452 tcg_temp_free_i32(tcg_op3
);
14453 tcg_temp_free_i32(tcg_res
);
14454 tcg_temp_free_i32(tcg_zero
);
14459 * 31 21 20 16 15 10 9 5 4 0
14460 * +-----------------------+------+--------+------+------+
14461 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14462 * +-----------------------+------+--------+------+------+
14464 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14466 int rm
= extract32(insn
, 16, 5);
14467 int imm6
= extract32(insn
, 10, 6);
14468 int rn
= extract32(insn
, 5, 5);
14469 int rd
= extract32(insn
, 0, 5);
14471 if (!dc_isar_feature(aa64_sha3
, s
)) {
14472 unallocated_encoding(s
);
14476 if (!fp_access_check(s
)) {
14480 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
14481 vec_full_reg_offset(s
, rn
),
14482 vec_full_reg_offset(s
, rm
), imm6
, 16,
14483 vec_full_reg_size(s
));
14486 /* Crypto three-reg imm2
14487 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14488 * +-----------------------+------+-----+------+--------+------+------+
14489 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14490 * +-----------------------+------+-----+------+--------+------+------+
14492 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14494 static gen_helper_gvec_3
* const fns
[4] = {
14495 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14496 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14498 int opcode
= extract32(insn
, 10, 2);
14499 int imm2
= extract32(insn
, 12, 2);
14500 int rm
= extract32(insn
, 16, 5);
14501 int rn
= extract32(insn
, 5, 5);
14502 int rd
= extract32(insn
, 0, 5);
14504 if (!dc_isar_feature(aa64_sm3
, s
)) {
14505 unallocated_encoding(s
);
14509 if (!fp_access_check(s
)) {
14513 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14516 /* C3.6 Data processing - SIMD, inc Crypto
14518 * As the decode gets a little complex we are using a table based
14519 * approach for this part of the decode.
14521 static const AArch64DecodeTable data_proc_simd
[] = {
14522 /* pattern , mask , fn */
14523 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14524 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14525 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14526 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14527 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14528 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14529 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14530 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14531 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14532 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14533 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14534 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14535 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14536 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14537 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14538 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14539 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14540 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14541 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14542 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14543 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14544 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14545 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14546 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14547 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14548 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14549 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14550 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14551 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14552 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14553 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14554 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14555 { 0x00000000, 0x00000000, NULL
}
14558 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14560 /* Note that this is called with all non-FP cases from
14561 * table C3-6 so it must UNDEF for entries not specifically
14562 * allocated to instructions in that table.
14564 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14568 unallocated_encoding(s
);
14572 /* C3.6 Data processing - SIMD and floating point */
14573 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14575 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14576 disas_data_proc_fp(s
, insn
);
14578 /* SIMD, including crypto */
14579 disas_data_proc_simd(s
, insn
);
14585 * @env: The cpu environment
14586 * @s: The DisasContext
14588 * Return true if the page is guarded.
14590 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14592 uint64_t addr
= s
->base
.pc_first
;
14593 #ifdef CONFIG_USER_ONLY
14594 return page_get_flags(addr
) & PAGE_BTI
;
14596 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14597 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14598 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14601 * We test this immediately after reading an insn, which means
14602 * that any normal page must be in the TLB. The only exception
14603 * would be for executing from flash or device memory, which
14604 * does not retain the TLB entry.
14606 * FIXME: Assume false for those, for now. We could use
14607 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14608 * table entry even for that case.
14610 return (tlb_hit(entry
->addr_code
, addr
) &&
14611 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14616 * btype_destination_ok:
14617 * @insn: The instruction at the branch destination
14618 * @bt: SCTLR_ELx.BT
14619 * @btype: PSTATE.BTYPE, and is non-zero
14621 * On a guarded page, there are a limited number of insns
14622 * that may be present at the branch target:
14623 * - branch target identifiers,
14624 * - paciasp, pacibsp,
14627 * Anything else causes a Branch Target Exception.
14629 * Return true if the branch is compatible, false to raise BTITRAP.
14631 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14633 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14635 switch (extract32(insn
, 5, 7)) {
14636 case 0b011001: /* PACIASP */
14637 case 0b011011: /* PACIBSP */
14639 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14640 * with btype == 3. Otherwise all btype are ok.
14642 return !bt
|| btype
!= 3;
14643 case 0b100000: /* BTI */
14644 /* Not compatible with any btype. */
14646 case 0b100010: /* BTI c */
14647 /* Not compatible with btype == 3 */
14649 case 0b100100: /* BTI j */
14650 /* Not compatible with btype == 2 */
14652 case 0b100110: /* BTI jc */
14653 /* Compatible with any btype. */
14657 switch (insn
& 0xffe0001fu
) {
14658 case 0xd4200000u
: /* BRK */
14659 case 0xd4400000u
: /* HLT */
14660 /* Give priority to the breakpoint exception. */
14667 /* C3.1 A64 instruction index by encoding */
14668 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14672 s
->pc_curr
= s
->base
.pc_next
;
14673 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14675 s
->base
.pc_next
+= 4;
14677 s
->fp_access_checked
= false;
14678 s
->sve_access_checked
= false;
14680 if (dc_isar_feature(aa64_bti
, s
)) {
14681 if (s
->base
.num_insns
== 1) {
14683 * At the first insn of the TB, compute s->guarded_page.
14684 * We delayed computing this until successfully reading
14685 * the first insn of the TB, above. This (mostly) ensures
14686 * that the softmmu tlb entry has been populated, and the
14687 * page table GP bit is available.
14689 * Note that we need to compute this even if btype == 0,
14690 * because this value is used for BR instructions later
14691 * where ENV is not available.
14693 s
->guarded_page
= is_guarded_page(env
, s
);
14695 /* First insn can have btype set to non-zero. */
14696 tcg_debug_assert(s
->btype
>= 0);
14699 * Note that the Branch Target Exception has fairly high
14700 * priority -- below debugging exceptions but above most
14701 * everything else. This allows us to handle this now
14702 * instead of waiting until the insn is otherwise decoded.
14706 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14707 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14708 syn_btitrap(s
->btype
),
14709 default_exception_el(s
));
14713 /* Not the first insn: btype must be 0. */
14714 tcg_debug_assert(s
->btype
== 0);
14718 switch (extract32(insn
, 25, 4)) {
14719 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14720 unallocated_encoding(s
);
14723 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14724 unallocated_encoding(s
);
14727 case 0x8: case 0x9: /* Data processing - immediate */
14728 disas_data_proc_imm(s
, insn
);
14730 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14731 disas_b_exc_sys(s
, insn
);
14736 case 0xe: /* Loads and stores */
14737 disas_ldst(s
, insn
);
14740 case 0xd: /* Data processing - register */
14741 disas_data_proc_reg(s
, insn
);
14744 case 0xf: /* Data processing - SIMD and floating point */
14745 disas_data_proc_simd_fp(s
, insn
);
14748 assert(FALSE
); /* all 15 cases should be handled above */
14752 /* if we allocated any temporaries, free them here */
14756 * After execution of most insns, btype is reset to 0.
14757 * Note that we set btype == -1 when the insn sets btype.
14759 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14764 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14767 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14768 CPUARMState
*env
= cpu
->env_ptr
;
14769 ARMCPU
*arm_cpu
= env_archcpu(env
);
14770 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14771 int bound
, core_mmu_idx
;
14773 dc
->isar
= &arm_cpu
->isar
;
14777 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14778 * there is no secure EL1, so we route exceptions to EL3.
14780 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14781 !arm_el_is_aa64(env
, 3);
14784 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14785 dc
->condexec_mask
= 0;
14786 dc
->condexec_cond
= 0;
14787 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14788 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14789 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14790 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14791 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14792 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14793 #if !defined(CONFIG_USER_ONLY)
14794 dc
->user
= (dc
->current_el
== 0);
14796 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14797 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14798 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14799 dc
->sve_len
= (EX_TBFLAG_A64(tb_flags
, ZCR_LEN
) + 1) * 16;
14800 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14801 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14802 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14803 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14804 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14805 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14806 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14808 dc
->vec_stride
= 0;
14809 dc
->cp_regs
= arm_cpu
->cp_regs
;
14810 dc
->features
= env
->features
;
14811 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14813 #ifdef CONFIG_USER_ONLY
14814 /* In sve_probe_page, we assume TBI is enabled. */
14815 tcg_debug_assert(dc
->tbid
& 1);
14818 /* Single step state. The code-generation logic here is:
14820 * generate code with no special handling for single-stepping (except
14821 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14822 * this happens anyway because those changes are all system register or
14824 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14825 * emit code for one insn
14826 * emit code to clear PSTATE.SS
14827 * emit code to generate software step exception for completed step
14828 * end TB (as usual for having generated an exception)
14829 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14830 * emit code to generate a software step exception
14833 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14834 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14835 dc
->is_ldex
= false;
14836 dc
->debug_target_el
= EX_TBFLAG_ANY(tb_flags
, DEBUG_TARGET_EL
);
14838 /* Bound the number of insns to execute to those left on the page. */
14839 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14841 /* If architectural single step active, limit to 1. */
14842 if (dc
->ss_active
) {
14845 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14847 init_tmp_a64_array(dc
);
14850 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14854 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14856 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14858 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14859 dc
->insn_start
= tcg_last_op();
14862 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14863 const CPUBreakpoint
*bp
)
14865 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14867 if (bp
->flags
& BP_CPU
) {
14868 gen_a64_set_pc_im(dc
->base
.pc_next
);
14869 gen_helper_check_breakpoints(cpu_env
);
14870 /* End the TB early; it likely won't be executed */
14871 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14873 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14874 /* The address covered by the breakpoint must be
14875 included in [tb->pc, tb->pc + tb->size) in order
14876 to for it to be properly cleared -- thus we
14877 increment the PC here so that the logic setting
14878 tb->size below does the right thing. */
14879 dc
->base
.pc_next
+= 4;
14880 dc
->base
.is_jmp
= DISAS_NORETURN
;
14886 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14888 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14889 CPUARMState
*env
= cpu
->env_ptr
;
14891 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14892 /* Singlestep state is Active-pending.
14893 * If we're in this state at the start of a TB then either
14894 * a) we just took an exception to an EL which is being debugged
14895 * and this is the first insn in the exception handler
14896 * b) debug exceptions were masked and we just unmasked them
14897 * without changing EL (eg by clearing PSTATE.D)
14898 * In either case we're going to take a swstep exception in the
14899 * "did not step an insn" case, and so the syndrome ISV and EX
14900 * bits should be zero.
14902 assert(dc
->base
.num_insns
== 1);
14903 gen_swstep_exception(dc
, 0, 0);
14904 dc
->base
.is_jmp
= DISAS_NORETURN
;
14906 disas_a64_insn(env
, dc
);
14909 translator_loop_temp_check(&dc
->base
);
14912 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14914 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14916 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14917 /* Note that this means single stepping WFI doesn't halt the CPU.
14918 * For conditional branch insns this is harmless unreachable code as
14919 * gen_goto_tb() has already handled emitting the debug exception
14920 * (and thus a tb-jump is not possible when singlestepping).
14922 switch (dc
->base
.is_jmp
) {
14924 gen_a64_set_pc_im(dc
->base
.pc_next
);
14928 if (dc
->base
.singlestep_enabled
) {
14929 gen_exception_internal(EXCP_DEBUG
);
14931 gen_step_complete_exception(dc
);
14934 case DISAS_NORETURN
:
14938 switch (dc
->base
.is_jmp
) {
14940 case DISAS_TOO_MANY
:
14941 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14944 case DISAS_UPDATE_EXIT
:
14945 gen_a64_set_pc_im(dc
->base
.pc_next
);
14948 tcg_gen_exit_tb(NULL
, 0);
14950 case DISAS_UPDATE_NOCHAIN
:
14951 gen_a64_set_pc_im(dc
->base
.pc_next
);
14954 tcg_gen_lookup_and_goto_ptr();
14956 case DISAS_NORETURN
:
14960 gen_a64_set_pc_im(dc
->base
.pc_next
);
14961 gen_helper_wfe(cpu_env
);
14964 gen_a64_set_pc_im(dc
->base
.pc_next
);
14965 gen_helper_yield(cpu_env
);
14969 /* This is a special case because we don't want to just halt the CPU
14970 * if trying to debug across a WFI.
14972 TCGv_i32 tmp
= tcg_const_i32(4);
14974 gen_a64_set_pc_im(dc
->base
.pc_next
);
14975 gen_helper_wfi(cpu_env
, tmp
);
14976 tcg_temp_free_i32(tmp
);
14977 /* The helper doesn't necessarily throw an exception, but we
14978 * must go back to the main loop to check for interrupts anyway.
14980 tcg_gen_exit_tb(NULL
, 0);
14987 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14990 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14992 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14993 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14996 const TranslatorOps aarch64_translator_ops
= {
14997 .init_disas_context
= aarch64_tr_init_disas_context
,
14998 .tb_start
= aarch64_tr_tb_start
,
14999 .insn_start
= aarch64_tr_insn_start
,
15000 .breakpoint_check
= aarch64_tr_breakpoint_check
,
15001 .translate_insn
= aarch64_tr_translate_insn
,
15002 .tb_stop
= aarch64_tr_tb_stop
,
15003 .disas_log
= aarch64_tr_disas_log
,