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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170303' into staging
[qemu/ar7.git] / hw / ppc / spapr.c
blob14192accf4864b5abf322e57b5240dc42f4ff266
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "qom/cpu.h"
44
45 #include "hw/boards.h"
46 #include "hw/ppc/ppc.h"
47 #include "hw/loader.h"
48
49 #include "hw/ppc/fdt.h"
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66 #include "hw/intc/intc.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics,
100 const char *type_icp, int nr_servers,
101 int nr_irqs, Error **errp)
102 {
103 XICSFabric *xi = XICS_FABRIC(spapr);
104 Error *err = NULL, *local_err = NULL;
105 ICSState *ics = NULL;
106 int i;
107
108 ics = ICS_SIMPLE(object_new(type_ics));
109 qdev_set_parent_bus(DEVICE(ics), sysbus_get_default());
110 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL);
111 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err);
112 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL);
113 object_property_set_bool(OBJECT(ics), true, "realized", &local_err);
114 error_propagate(&err, local_err);
115 if (err) {
116 goto error;
117 }
118
119 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState));
120 spapr->nr_servers = nr_servers;
121
122 for (i = 0; i < nr_servers; i++) {
123 ICPState *icp = &spapr->icps[i];
124
125 object_initialize(icp, sizeof(*icp), type_icp);
126 qdev_set_parent_bus(DEVICE(icp), sysbus_get_default());
127 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL);
128 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL);
129 object_property_set_bool(OBJECT(icp), true, "realized", &err);
130 if (err) {
131 goto error;
132 }
133 object_unref(OBJECT(icp));
134 }
135
136 spapr->ics = ics;
137 return 0;
138
139 error:
140 error_propagate(errp, err);
141 if (ics) {
142 object_unparent(OBJECT(ics));
143 }
144 return -1;
145 }
146
147 static int xics_system_init(MachineState *machine,
148 int nr_servers, int nr_irqs, Error **errp)
149 {
150 int rc = -1;
151
152 if (kvm_enabled()) {
153 Error *err = NULL;
154
155 if (machine_kernel_irqchip_allowed(machine) &&
156 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) {
157 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM,
158 TYPE_KVM_ICP, nr_servers, nr_irqs, &err);
159 }
160 if (machine_kernel_irqchip_required(machine) && rc < 0) {
161 error_reportf_err(err,
162 "kernel_irqchip requested but unavailable: ");
163 } else {
164 error_free(err);
165 }
166 }
167
168 if (rc < 0) {
169 xics_spapr_init(SPAPR_MACHINE(machine), errp);
170 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE,
171 TYPE_ICP, nr_servers, nr_irqs, errp);
172 }
173
174 return rc;
175 }
176
177 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
178 int smt_threads)
179 {
180 int i, ret = 0;
181 uint32_t servers_prop[smt_threads];
182 uint32_t gservers_prop[smt_threads * 2];
183 int index = ppc_get_vcpu_dt_id(cpu);
184
185 if (cpu->compat_pvr) {
186 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
187 if (ret < 0) {
188 return ret;
189 }
190 }
191
192 /* Build interrupt servers and gservers properties */
193 for (i = 0; i < smt_threads; i++) {
194 servers_prop[i] = cpu_to_be32(index + i);
195 /* Hack, direct the group queues back to cpu 0 */
196 gservers_prop[i*2] = cpu_to_be32(index + i);
197 gservers_prop[i*2 + 1] = 0;
198 }
199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
200 servers_prop, sizeof(servers_prop));
201 if (ret < 0) {
202 return ret;
203 }
204 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
205 gservers_prop, sizeof(gservers_prop));
206
207 return ret;
208 }
209
210 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
211 {
212 int ret = 0;
213 PowerPCCPU *cpu = POWERPC_CPU(cs);
214 int index = ppc_get_vcpu_dt_id(cpu);
215 uint32_t associativity[] = {cpu_to_be32(0x5),
216 cpu_to_be32(0x0),
217 cpu_to_be32(0x0),
218 cpu_to_be32(0x0),
219 cpu_to_be32(cs->numa_node),
220 cpu_to_be32(index)};
221
222 /* Advertise NUMA via ibm,associativity */
223 if (nb_numa_nodes > 1) {
224 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
225 sizeof(associativity));
226 }
227
228 return ret;
229 }
230
231 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
232 {
233 int ret = 0, offset, cpus_offset;
234 CPUState *cs;
235 char cpu_model[32];
236 int smt = kvmppc_smt_threads();
237 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
238
239 CPU_FOREACH(cs) {
240 PowerPCCPU *cpu = POWERPC_CPU(cs);
241 DeviceClass *dc = DEVICE_GET_CLASS(cs);
242 int index = ppc_get_vcpu_dt_id(cpu);
243 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
244
245 if ((index % smt) != 0) {
246 continue;
247 }
248
249 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
250
251 cpus_offset = fdt_path_offset(fdt, "/cpus");
252 if (cpus_offset < 0) {
253 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
254 "cpus");
255 if (cpus_offset < 0) {
256 return cpus_offset;
257 }
258 }
259 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
260 if (offset < 0) {
261 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
262 if (offset < 0) {
263 return offset;
264 }
265 }
266
267 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
268 pft_size_prop, sizeof(pft_size_prop));
269 if (ret < 0) {
270 return ret;
271 }
272
273 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
274 if (ret < 0) {
275 return ret;
276 }
277
278 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
279 if (ret < 0) {
280 return ret;
281 }
282 }
283 return ret;
284 }
285
286 static hwaddr spapr_node0_size(void)
287 {
288 MachineState *machine = MACHINE(qdev_get_machine());
289
290 if (nb_numa_nodes) {
291 int i;
292 for (i = 0; i < nb_numa_nodes; ++i) {
293 if (numa_info[i].node_mem) {
294 return MIN(pow2floor(numa_info[i].node_mem),
295 machine->ram_size);
296 }
297 }
298 }
299 return machine->ram_size;
300 }
301
302 static void add_str(GString *s, const gchar *s1)
303 {
304 g_string_append_len(s, s1, strlen(s1) + 1);
305 }
306
307 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
308 hwaddr size)
309 {
310 uint32_t associativity[] = {
311 cpu_to_be32(0x4), /* length */
312 cpu_to_be32(0x0), cpu_to_be32(0x0),
313 cpu_to_be32(0x0), cpu_to_be32(nodeid)
314 };
315 char mem_name[32];
316 uint64_t mem_reg_property[2];
317 int off;
318
319 mem_reg_property[0] = cpu_to_be64(start);
320 mem_reg_property[1] = cpu_to_be64(size);
321
322 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
323 off = fdt_add_subnode(fdt, 0, mem_name);
324 _FDT(off);
325 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
326 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
327 sizeof(mem_reg_property))));
328 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
329 sizeof(associativity))));
330 return off;
331 }
332
333 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
334 {
335 MachineState *machine = MACHINE(spapr);
336 hwaddr mem_start, node_size;
337 int i, nb_nodes = nb_numa_nodes;
338 NodeInfo *nodes = numa_info;
339 NodeInfo ramnode;
340
341 /* No NUMA nodes, assume there is just one node with whole RAM */
342 if (!nb_numa_nodes) {
343 nb_nodes = 1;
344 ramnode.node_mem = machine->ram_size;
345 nodes = &ramnode;
346 }
347
348 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
349 if (!nodes[i].node_mem) {
350 continue;
351 }
352 if (mem_start >= machine->ram_size) {
353 node_size = 0;
354 } else {
355 node_size = nodes[i].node_mem;
356 if (node_size > machine->ram_size - mem_start) {
357 node_size = machine->ram_size - mem_start;
358 }
359 }
360 if (!mem_start) {
361 /* ppc_spapr_init() checks for rma_size <= node0_size already */
362 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
363 mem_start += spapr->rma_size;
364 node_size -= spapr->rma_size;
365 }
366 for ( ; node_size; ) {
367 hwaddr sizetmp = pow2floor(node_size);
368
369 /* mem_start != 0 here */
370 if (ctzl(mem_start) < ctzl(sizetmp)) {
371 sizetmp = 1ULL << ctzl(mem_start);
372 }
373
374 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
375 node_size -= sizetmp;
376 mem_start += sizetmp;
377 }
378 }
379
380 return 0;
381 }
382
383 /* Populate the "ibm,pa-features" property */
384 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
385 {
386 uint8_t pa_features_206[] = { 6, 0,
387 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
388 uint8_t pa_features_207[] = { 24, 0,
389 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
390 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
391 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
392 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
393 /* Currently we don't advertise any of the "new" ISAv3.00 functionality */
394 uint8_t pa_features_300[] = { 64, 0,
395 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
396 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
397 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
398 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
399 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
400 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
403 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
404 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
405 0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */
406
407 uint8_t *pa_features;
408 size_t pa_size;
409
410 switch (POWERPC_MMU_VER(env->mmu_model)) {
411 case POWERPC_MMU_VER_2_06:
412 pa_features = pa_features_206;
413 pa_size = sizeof(pa_features_206);
414 break;
415 case POWERPC_MMU_VER_2_07:
416 pa_features = pa_features_207;
417 pa_size = sizeof(pa_features_207);
418 break;
419 case POWERPC_MMU_VER_3_00:
420 pa_features = pa_features_300;
421 pa_size = sizeof(pa_features_300);
422 break;
423 default:
424 return;
425 }
426
427 if (env->ci_large_pages) {
428 /*
429 * Note: we keep CI large pages off by default because a 64K capable
430 * guest provisioned with large pages might otherwise try to map a qemu
431 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
432 * even if that qemu runs on a 4k host.
433 * We dd this bit back here if we are confident this is not an issue
434 */
435 pa_features[3] |= 0x20;
436 }
437 if (kvmppc_has_cap_htm() && pa_size > 24) {
438 pa_features[24] |= 0x80; /* Transactional memory support */
439 }
440
441 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
442 }
443
444 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
445 sPAPRMachineState *spapr)
446 {
447 PowerPCCPU *cpu = POWERPC_CPU(cs);
448 CPUPPCState *env = &cpu->env;
449 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
450 int index = ppc_get_vcpu_dt_id(cpu);
451 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
452 0xffffffff, 0xffffffff};
453 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
454 : SPAPR_TIMEBASE_FREQ;
455 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
456 uint32_t page_sizes_prop[64];
457 size_t page_sizes_prop_size;
458 uint32_t vcpus_per_socket = smp_threads * smp_cores;
459 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
460 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
461 sPAPRDRConnector *drc;
462 sPAPRDRConnectorClass *drck;
463 int drc_index;
464
465 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
466 if (drc) {
467 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
468 drc_index = drck->get_index(drc);
469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
470 }
471
472 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
473 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
474
475 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
476 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
477 env->dcache_line_size)));
478 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
479 env->dcache_line_size)));
480 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
481 env->icache_line_size)));
482 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
483 env->icache_line_size)));
484
485 if (pcc->l1_dcache_size) {
486 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
487 pcc->l1_dcache_size)));
488 } else {
489 error_report("Warning: Unknown L1 dcache size for cpu");
490 }
491 if (pcc->l1_icache_size) {
492 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
493 pcc->l1_icache_size)));
494 } else {
495 error_report("Warning: Unknown L1 icache size for cpu");
496 }
497
498 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
499 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
500 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
501 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
502 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
503 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
504
505 if (env->spr_cb[SPR_PURR].oea_read) {
506 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
507 }
508
509 if (env->mmu_model & POWERPC_MMU_1TSEG) {
510 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
511 segs, sizeof(segs))));
512 }
513
514 /* Advertise VMX/VSX (vector extensions) if available
515 * 0 / no property == no vector extensions
516 * 1 == VMX / Altivec available
517 * 2 == VSX available */
518 if (env->insns_flags & PPC_ALTIVEC) {
519 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
520
521 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
522 }
523
524 /* Advertise DFP (Decimal Floating Point) if available
525 * 0 / no property == no DFP
526 * 1 == DFP available */
527 if (env->insns_flags2 & PPC2_DFP) {
528 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
529 }
530
531 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
532 sizeof(page_sizes_prop));
533 if (page_sizes_prop_size) {
534 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
535 page_sizes_prop, page_sizes_prop_size)));
536 }
537
538 spapr_populate_pa_features(env, fdt, offset);
539
540 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
541 cs->cpu_index / vcpus_per_socket)));
542
543 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
544 pft_size_prop, sizeof(pft_size_prop))));
545
546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
547
548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
549 }
550
551 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
552 {
553 CPUState *cs;
554 int cpus_offset;
555 char *nodename;
556 int smt = kvmppc_smt_threads();
557
558 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
559 _FDT(cpus_offset);
560 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
561 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
562
563 /*
564 * We walk the CPUs in reverse order to ensure that CPU DT nodes
565 * created by fdt_add_subnode() end up in the right order in FDT
566 * for the guest kernel the enumerate the CPUs correctly.
567 */
568 CPU_FOREACH_REVERSE(cs) {
569 PowerPCCPU *cpu = POWERPC_CPU(cs);
570 int index = ppc_get_vcpu_dt_id(cpu);
571 DeviceClass *dc = DEVICE_GET_CLASS(cs);
572 int offset;
573
574 if ((index % smt) != 0) {
575 continue;
576 }
577
578 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
579 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
580 g_free(nodename);
581 _FDT(offset);
582 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
583 }
584
585 }
586
587 /*
588 * Adds ibm,dynamic-reconfiguration-memory node.
589 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
590 * of this device tree node.
591 */
592 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
593 {
594 MachineState *machine = MACHINE(spapr);
595 int ret, i, offset;
596 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
597 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
598 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
599 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
600 memory_region_size(&spapr->hotplug_memory.mr)) /
601 lmb_size;
602 uint32_t *int_buf, *cur_index, buf_len;
603 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
604
605 /*
606 * Don't create the node if there is no hotpluggable memory
607 */
608 if (machine->ram_size == machine->maxram_size) {
609 return 0;
610 }
611
612 /*
613 * Allocate enough buffer size to fit in ibm,dynamic-memory
614 * or ibm,associativity-lookup-arrays
615 */
616 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
617 * sizeof(uint32_t);
618 cur_index = int_buf = g_malloc0(buf_len);
619
620 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
621
622 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
623 sizeof(prop_lmb_size));
624 if (ret < 0) {
625 goto out;
626 }
627
628 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
629 if (ret < 0) {
630 goto out;
631 }
632
633 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
634 if (ret < 0) {
635 goto out;
636 }
637
638 /* ibm,dynamic-memory */
639 int_buf[0] = cpu_to_be32(nr_lmbs);
640 cur_index++;
641 for (i = 0; i < nr_lmbs; i++) {
642 uint64_t addr = i * lmb_size;
643 uint32_t *dynamic_memory = cur_index;
644
645 if (i >= hotplug_lmb_start) {
646 sPAPRDRConnector *drc;
647 sPAPRDRConnectorClass *drck;
648
649 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
650 g_assert(drc);
651 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
652
653 dynamic_memory[0] = cpu_to_be32(addr >> 32);
654 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
655 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
656 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
657 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
658 if (memory_region_present(get_system_memory(), addr)) {
659 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
660 } else {
661 dynamic_memory[5] = cpu_to_be32(0);
662 }
663 } else {
664 /*
665 * LMB information for RMA, boot time RAM and gap b/n RAM and
666 * hotplug memory region -- all these are marked as reserved
667 * and as having no valid DRC.
668 */
669 dynamic_memory[0] = cpu_to_be32(addr >> 32);
670 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
671 dynamic_memory[2] = cpu_to_be32(0);
672 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
673 dynamic_memory[4] = cpu_to_be32(-1);
674 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
675 SPAPR_LMB_FLAGS_DRC_INVALID);
676 }
677
678 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
679 }
680 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
681 if (ret < 0) {
682 goto out;
683 }
684
685 /* ibm,associativity-lookup-arrays */
686 cur_index = int_buf;
687 int_buf[0] = cpu_to_be32(nr_nodes);
688 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
689 cur_index += 2;
690 for (i = 0; i < nr_nodes; i++) {
691 uint32_t associativity[] = {
692 cpu_to_be32(0x0),
693 cpu_to_be32(0x0),
694 cpu_to_be32(0x0),
695 cpu_to_be32(i)
696 };
697 memcpy(cur_index, associativity, sizeof(associativity));
698 cur_index += 4;
699 }
700 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
701 (cur_index - int_buf) * sizeof(uint32_t));
702 out:
703 g_free(int_buf);
704 return ret;
705 }
706
707 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
708 sPAPROptionVector *ov5_updates)
709 {
710 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
711 int ret = 0, offset;
712
713 /* Generate ibm,dynamic-reconfiguration-memory node if required */
714 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
715 g_assert(smc->dr_lmb_enabled);
716 ret = spapr_populate_drconf_memory(spapr, fdt);
717 if (ret) {
718 goto out;
719 }
720 }
721
722 offset = fdt_path_offset(fdt, "/chosen");
723 if (offset < 0) {
724 offset = fdt_add_subnode(fdt, 0, "chosen");
725 if (offset < 0) {
726 return offset;
727 }
728 }
729 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
730 "ibm,architecture-vec-5");
731
732 out:
733 return ret;
734 }
735
736 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
737 target_ulong addr, target_ulong size,
738 sPAPROptionVector *ov5_updates)
739 {
740 void *fdt, *fdt_skel;
741 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
742
743 size -= sizeof(hdr);
744
745 /* Create sceleton */
746 fdt_skel = g_malloc0(size);
747 _FDT((fdt_create(fdt_skel, size)));
748 _FDT((fdt_begin_node(fdt_skel, "")));
749 _FDT((fdt_end_node(fdt_skel)));
750 _FDT((fdt_finish(fdt_skel)));
751 fdt = g_malloc0(size);
752 _FDT((fdt_open_into(fdt_skel, fdt, size)));
753 g_free(fdt_skel);
754
755 /* Fixup cpu nodes */
756 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
757
758 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
759 return -1;
760 }
761
762 /* Pack resulting tree */
763 _FDT((fdt_pack(fdt)));
764
765 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
766 trace_spapr_cas_failed(size);
767 return -1;
768 }
769
770 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
771 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
772 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
773 g_free(fdt);
774
775 return 0;
776 }
777
778 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
779 {
780 int rtas;
781 GString *hypertas = g_string_sized_new(256);
782 GString *qemu_hypertas = g_string_sized_new(256);
783 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
784 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
785 memory_region_size(&spapr->hotplug_memory.mr);
786 uint32_t lrdr_capacity[] = {
787 cpu_to_be32(max_hotplug_addr >> 32),
788 cpu_to_be32(max_hotplug_addr & 0xffffffff),
789 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
790 cpu_to_be32(max_cpus / smp_threads),
791 };
792
793 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
794
795 /* hypertas */
796 add_str(hypertas, "hcall-pft");
797 add_str(hypertas, "hcall-term");
798 add_str(hypertas, "hcall-dabr");
799 add_str(hypertas, "hcall-interrupt");
800 add_str(hypertas, "hcall-tce");
801 add_str(hypertas, "hcall-vio");
802 add_str(hypertas, "hcall-splpar");
803 add_str(hypertas, "hcall-bulk");
804 add_str(hypertas, "hcall-set-mode");
805 add_str(hypertas, "hcall-sprg0");
806 add_str(hypertas, "hcall-copy");
807 add_str(hypertas, "hcall-debug");
808 add_str(qemu_hypertas, "hcall-memop1");
809
810 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
811 add_str(hypertas, "hcall-multi-tce");
812 }
813 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
814 hypertas->str, hypertas->len));
815 g_string_free(hypertas, TRUE);
816 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
817 qemu_hypertas->str, qemu_hypertas->len));
818 g_string_free(qemu_hypertas, TRUE);
819
820 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
821 refpoints, sizeof(refpoints)));
822
823 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
824 RTAS_ERROR_LOG_MAX));
825 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
826 RTAS_EVENT_SCAN_RATE));
827
828 if (msi_nonbroken) {
829 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
830 }
831
832 /*
833 * According to PAPR, rtas ibm,os-term does not guarantee a return
834 * back to the guest cpu.
835 *
836 * While an additional ibm,extended-os-term property indicates
837 * that rtas call return will always occur. Set this property.
838 */
839 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
840
841 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
842 lrdr_capacity, sizeof(lrdr_capacity)));
843
844 spapr_dt_rtas_tokens(fdt, rtas);
845 }
846
847 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
848 {
849 MachineState *machine = MACHINE(spapr);
850 int chosen;
851 const char *boot_device = machine->boot_order;
852 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
853 size_t cb = 0;
854 char *bootlist = get_boot_devices_list(&cb, true);
855
856 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
857
858 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
859 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
860 spapr->initrd_base));
861 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
862 spapr->initrd_base + spapr->initrd_size));
863
864 if (spapr->kernel_size) {
865 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
866 cpu_to_be64(spapr->kernel_size) };
867
868 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
869 &kprop, sizeof(kprop)));
870 if (spapr->kernel_le) {
871 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
872 }
873 }
874 if (boot_menu) {
875 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
876 }
877 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
878 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
879 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
880
881 if (cb && bootlist) {
882 int i;
883
884 for (i = 0; i < cb; i++) {
885 if (bootlist[i] == '\n') {
886 bootlist[i] = ' ';
887 }
888 }
889 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
890 }
891
892 if (boot_device && strlen(boot_device)) {
893 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
894 }
895
896 if (!spapr->has_graphics && stdout_path) {
897 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
898 }
899
900 g_free(stdout_path);
901 g_free(bootlist);
902 }
903
904 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
905 {
906 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
907 * KVM to work under pHyp with some guest co-operation */
908 int hypervisor;
909 uint8_t hypercall[16];
910
911 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
912 /* indicate KVM hypercall interface */
913 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
914 if (kvmppc_has_cap_fixup_hcalls()) {
915 /*
916 * Older KVM versions with older guest kernels were broken
917 * with the magic page, don't allow the guest to map it.
918 */
919 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
920 sizeof(hypercall))) {
921 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
922 hypercall, sizeof(hypercall)));
923 }
924 }
925 }
926
927 static void *spapr_build_fdt(sPAPRMachineState *spapr,
928 hwaddr rtas_addr,
929 hwaddr rtas_size)
930 {
931 MachineState *machine = MACHINE(qdev_get_machine());
932 MachineClass *mc = MACHINE_GET_CLASS(machine);
933 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
934 int ret;
935 void *fdt;
936 sPAPRPHBState *phb;
937 char *buf;
938
939 fdt = g_malloc0(FDT_MAX_SIZE);
940 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
941
942 /* Root node */
943 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
944 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
945 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
946
947 /*
948 * Add info to guest to indentify which host is it being run on
949 * and what is the uuid of the guest
950 */
951 if (kvmppc_get_host_model(&buf)) {
952 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
953 g_free(buf);
954 }
955 if (kvmppc_get_host_serial(&buf)) {
956 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
957 g_free(buf);
958 }
959
960 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
961
962 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
963 if (qemu_uuid_set) {
964 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
965 }
966 g_free(buf);
967
968 if (qemu_get_vm_name()) {
969 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
970 qemu_get_vm_name()));
971 }
972
973 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
974 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
975
976 /* /interrupt controller */
977 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP);
978
979 ret = spapr_populate_memory(spapr, fdt);
980 if (ret < 0) {
981 error_report("couldn't setup memory nodes in fdt");
982 exit(1);
983 }
984
985 /* /vdevice */
986 spapr_dt_vdevice(spapr->vio_bus, fdt);
987
988 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
989 ret = spapr_rng_populate_dt(fdt);
990 if (ret < 0) {
991 error_report("could not set up rng device in the fdt");
992 exit(1);
993 }
994 }
995
996 QLIST_FOREACH(phb, &spapr->phbs, list) {
997 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
998 if (ret < 0) {
999 error_report("couldn't setup PCI devices in fdt");
1000 exit(1);
1001 }
1002 }
1003
1004 /* cpus */
1005 spapr_populate_cpus_dt_node(fdt, spapr);
1006
1007 if (smc->dr_lmb_enabled) {
1008 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1009 }
1010
1011 if (mc->has_hotpluggable_cpus) {
1012 int offset = fdt_path_offset(fdt, "/cpus");
1013 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1014 SPAPR_DR_CONNECTOR_TYPE_CPU);
1015 if (ret < 0) {
1016 error_report("Couldn't set up CPU DR device tree properties");
1017 exit(1);
1018 }
1019 }
1020
1021 /* /event-sources */
1022 spapr_dt_events(spapr, fdt);
1023
1024 /* /rtas */
1025 spapr_dt_rtas(spapr, fdt);
1026
1027 /* /chosen */
1028 spapr_dt_chosen(spapr, fdt);
1029
1030 /* /hypervisor */
1031 if (kvm_enabled()) {
1032 spapr_dt_hypervisor(spapr, fdt);
1033 }
1034
1035 /* Build memory reserve map */
1036 if (spapr->kernel_size) {
1037 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1038 }
1039 if (spapr->initrd_size) {
1040 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1041 }
1042
1043 /* ibm,client-architecture-support updates */
1044 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1045 if (ret < 0) {
1046 error_report("couldn't setup CAS properties fdt");
1047 exit(1);
1048 }
1049
1050 return fdt;
1051 }
1052
1053 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1054 {
1055 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1056 }
1057
1058 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1059 PowerPCCPU *cpu)
1060 {
1061 CPUPPCState *env = &cpu->env;
1062
1063 /* The TCG path should also be holding the BQL at this point */
1064 g_assert(qemu_mutex_iothread_locked());
1065
1066 if (msr_pr) {
1067 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1068 env->gpr[3] = H_PRIVILEGE;
1069 } else {
1070 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1071 }
1072 }
1073
1074 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1075 {
1076 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1077
1078 return spapr->patb_entry;
1079 }
1080
1081 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1082 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1083 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1084 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1085 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1086
1087 /*
1088 * Get the fd to access the kernel htab, re-opening it if necessary
1089 */
1090 static int get_htab_fd(sPAPRMachineState *spapr)
1091 {
1092 if (spapr->htab_fd >= 0) {
1093 return spapr->htab_fd;
1094 }
1095
1096 spapr->htab_fd = kvmppc_get_htab_fd(false);
1097 if (spapr->htab_fd < 0) {
1098 error_report("Unable to open fd for reading hash table from KVM: %s",
1099 strerror(errno));
1100 }
1101
1102 return spapr->htab_fd;
1103 }
1104
1105 static void close_htab_fd(sPAPRMachineState *spapr)
1106 {
1107 if (spapr->htab_fd >= 0) {
1108 close(spapr->htab_fd);
1109 }
1110 spapr->htab_fd = -1;
1111 }
1112
1113 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1114 {
1115 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1116
1117 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1118 }
1119
1120 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1121 hwaddr ptex, int n)
1122 {
1123 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1124 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1125
1126 if (!spapr->htab) {
1127 /*
1128 * HTAB is controlled by KVM. Fetch into temporary buffer
1129 */
1130 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1131 kvmppc_read_hptes(hptes, ptex, n);
1132 return hptes;
1133 }
1134
1135 /*
1136 * HTAB is controlled by QEMU. Just point to the internally
1137 * accessible PTEG.
1138 */
1139 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1140 }
1141
1142 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1143 const ppc_hash_pte64_t *hptes,
1144 hwaddr ptex, int n)
1145 {
1146 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1147
1148 if (!spapr->htab) {
1149 g_free((void *)hptes);
1150 }
1151
1152 /* Nothing to do for qemu managed HPT */
1153 }
1154
1155 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1156 uint64_t pte0, uint64_t pte1)
1157 {
1158 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1159 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1160
1161 if (!spapr->htab) {
1162 kvmppc_write_hpte(ptex, pte0, pte1);
1163 } else {
1164 stq_p(spapr->htab + offset, pte0);
1165 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1166 }
1167 }
1168
1169 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1170 {
1171 int shift;
1172
1173 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1174 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1175 * that's much more than is needed for Linux guests */
1176 shift = ctz64(pow2ceil(ramsize)) - 7;
1177 shift = MAX(shift, 18); /* Minimum architected size */
1178 shift = MIN(shift, 46); /* Maximum architected size */
1179 return shift;
1180 }
1181
1182 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1183 Error **errp)
1184 {
1185 long rc;
1186
1187 /* Clean up any HPT info from a previous boot */
1188 g_free(spapr->htab);
1189 spapr->htab = NULL;
1190 spapr->htab_shift = 0;
1191 close_htab_fd(spapr);
1192
1193 rc = kvmppc_reset_htab(shift);
1194 if (rc < 0) {
1195 /* kernel-side HPT needed, but couldn't allocate one */
1196 error_setg_errno(errp, errno,
1197 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1198 shift);
1199 /* This is almost certainly fatal, but if the caller really
1200 * wants to carry on with shift == 0, it's welcome to try */
1201 } else if (rc > 0) {
1202 /* kernel-side HPT allocated */
1203 if (rc != shift) {
1204 error_setg(errp,
1205 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1206 shift, rc);
1207 }
1208
1209 spapr->htab_shift = shift;
1210 spapr->htab = NULL;
1211 } else {
1212 /* kernel-side HPT not needed, allocate in userspace instead */
1213 size_t size = 1ULL << shift;
1214 int i;
1215
1216 spapr->htab = qemu_memalign(size, size);
1217 if (!spapr->htab) {
1218 error_setg_errno(errp, errno,
1219 "Could not allocate HPT of order %d", shift);
1220 return;
1221 }
1222
1223 memset(spapr->htab, 0, size);
1224 spapr->htab_shift = shift;
1225
1226 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1227 DIRTY_HPTE(HPTE(spapr->htab, i));
1228 }
1229 }
1230 }
1231
1232 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1233 {
1234 bool matched = false;
1235
1236 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1237 matched = true;
1238 }
1239
1240 if (!matched) {
1241 error_report("Device %s is not supported by this machine yet.",
1242 qdev_fw_name(DEVICE(sbdev)));
1243 exit(1);
1244 }
1245 }
1246
1247 static void ppc_spapr_reset(void)
1248 {
1249 MachineState *machine = MACHINE(qdev_get_machine());
1250 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1251 PowerPCCPU *first_ppc_cpu;
1252 uint32_t rtas_limit;
1253 hwaddr rtas_addr, fdt_addr;
1254 void *fdt;
1255 int rc;
1256
1257 /* Check for unknown sysbus devices */
1258 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1259
1260 spapr->patb_entry = 0;
1261
1262 /* Allocate and/or reset the hash page table */
1263 spapr_reallocate_hpt(spapr,
1264 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1265 &error_fatal);
1266
1267 /* Update the RMA size if necessary */
1268 if (spapr->vrma_adjust) {
1269 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1270 spapr->htab_shift);
1271 }
1272
1273 qemu_devices_reset();
1274
1275 /*
1276 * We place the device tree and RTAS just below either the top of the RMA,
1277 * or just below 2GB, whichever is lowere, so that it can be
1278 * processed with 32-bit real mode code if necessary
1279 */
1280 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1281 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1282 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1283
1284 /* if this reset wasn't generated by CAS, we should reset our
1285 * negotiated options and start from scratch */
1286 if (!spapr->cas_reboot) {
1287 spapr_ovec_cleanup(spapr->ov5_cas);
1288 spapr->ov5_cas = spapr_ovec_new();
1289 }
1290
1291 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1292
1293 spapr_load_rtas(spapr, fdt, rtas_addr);
1294
1295 rc = fdt_pack(fdt);
1296
1297 /* Should only fail if we've built a corrupted tree */
1298 assert(rc == 0);
1299
1300 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1301 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1302 fdt_totalsize(fdt), FDT_MAX_SIZE);
1303 exit(1);
1304 }
1305
1306 /* Load the fdt */
1307 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1308 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1309 g_free(fdt);
1310
1311 /* Set up the entry state */
1312 first_ppc_cpu = POWERPC_CPU(first_cpu);
1313 first_ppc_cpu->env.gpr[3] = fdt_addr;
1314 first_ppc_cpu->env.gpr[5] = 0;
1315 first_cpu->halted = 0;
1316 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1317
1318 spapr->cas_reboot = false;
1319 }
1320
1321 static void spapr_create_nvram(sPAPRMachineState *spapr)
1322 {
1323 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1324 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1325
1326 if (dinfo) {
1327 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1328 &error_fatal);
1329 }
1330
1331 qdev_init_nofail(dev);
1332
1333 spapr->nvram = (struct sPAPRNVRAM *)dev;
1334 }
1335
1336 static void spapr_rtc_create(sPAPRMachineState *spapr)
1337 {
1338 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1339
1340 qdev_init_nofail(dev);
1341 spapr->rtc = dev;
1342
1343 object_property_add_alias(qdev_get_machine(), "rtc-time",
1344 OBJECT(spapr->rtc), "date", NULL);
1345 }
1346
1347 /* Returns whether we want to use VGA or not */
1348 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1349 {
1350 switch (vga_interface_type) {
1351 case VGA_NONE:
1352 return false;
1353 case VGA_DEVICE:
1354 return true;
1355 case VGA_STD:
1356 case VGA_VIRTIO:
1357 return pci_vga_init(pci_bus) != NULL;
1358 default:
1359 error_setg(errp,
1360 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1361 return false;
1362 }
1363 }
1364
1365 static int spapr_post_load(void *opaque, int version_id)
1366 {
1367 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1368 int err = 0;
1369
1370 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1371 int i;
1372 for (i = 0; i < spapr->nr_servers; i++) {
1373 icp_resend(&spapr->icps[i]);
1374 }
1375 }
1376
1377 /* In earlier versions, there was no separate qdev for the PAPR
1378 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1379 * So when migrating from those versions, poke the incoming offset
1380 * value into the RTC device */
1381 if (version_id < 3) {
1382 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1383 }
1384
1385 return err;
1386 }
1387
1388 static bool version_before_3(void *opaque, int version_id)
1389 {
1390 return version_id < 3;
1391 }
1392
1393 static bool spapr_ov5_cas_needed(void *opaque)
1394 {
1395 sPAPRMachineState *spapr = opaque;
1396 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1397 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1398 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1399 bool cas_needed;
1400
1401 /* Prior to the introduction of sPAPROptionVector, we had two option
1402 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1403 * Both of these options encode machine topology into the device-tree
1404 * in such a way that the now-booted OS should still be able to interact
1405 * appropriately with QEMU regardless of what options were actually
1406 * negotiatied on the source side.
1407 *
1408 * As such, we can avoid migrating the CAS-negotiated options if these
1409 * are the only options available on the current machine/platform.
1410 * Since these are the only options available for pseries-2.7 and
1411 * earlier, this allows us to maintain old->new/new->old migration
1412 * compatibility.
1413 *
1414 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1415 * via default pseries-2.8 machines and explicit command-line parameters.
1416 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1417 * of the actual CAS-negotiated values to continue working properly. For
1418 * example, availability of memory unplug depends on knowing whether
1419 * OV5_HP_EVT was negotiated via CAS.
1420 *
1421 * Thus, for any cases where the set of available CAS-negotiatable
1422 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1423 * include the CAS-negotiated options in the migration stream.
1424 */
1425 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1426 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1427
1428 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1429 * the mask itself since in the future it's possible "legacy" bits may be
1430 * removed via machine options, which could generate a false positive
1431 * that breaks migration.
1432 */
1433 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1434 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1435
1436 spapr_ovec_cleanup(ov5_mask);
1437 spapr_ovec_cleanup(ov5_legacy);
1438 spapr_ovec_cleanup(ov5_removed);
1439
1440 return cas_needed;
1441 }
1442
1443 static const VMStateDescription vmstate_spapr_ov5_cas = {
1444 .name = "spapr_option_vector_ov5_cas",
1445 .version_id = 1,
1446 .minimum_version_id = 1,
1447 .needed = spapr_ov5_cas_needed,
1448 .fields = (VMStateField[]) {
1449 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1450 vmstate_spapr_ovec, sPAPROptionVector),
1451 VMSTATE_END_OF_LIST()
1452 },
1453 };
1454
1455 static bool spapr_patb_entry_needed(void *opaque)
1456 {
1457 sPAPRMachineState *spapr = opaque;
1458
1459 return !!spapr->patb_entry;
1460 }
1461
1462 static const VMStateDescription vmstate_spapr_patb_entry = {
1463 .name = "spapr_patb_entry",
1464 .version_id = 1,
1465 .minimum_version_id = 1,
1466 .needed = spapr_patb_entry_needed,
1467 .fields = (VMStateField[]) {
1468 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1469 VMSTATE_END_OF_LIST()
1470 },
1471 };
1472
1473 static const VMStateDescription vmstate_spapr = {
1474 .name = "spapr",
1475 .version_id = 3,
1476 .minimum_version_id = 1,
1477 .post_load = spapr_post_load,
1478 .fields = (VMStateField[]) {
1479 /* used to be @next_irq */
1480 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1481
1482 /* RTC offset */
1483 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1484
1485 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1486 VMSTATE_END_OF_LIST()
1487 },
1488 .subsections = (const VMStateDescription*[]) {
1489 &vmstate_spapr_ov5_cas,
1490 &vmstate_spapr_patb_entry,
1491 NULL
1492 }
1493 };
1494
1495 static int htab_save_setup(QEMUFile *f, void *opaque)
1496 {
1497 sPAPRMachineState *spapr = opaque;
1498
1499 /* "Iteration" header */
1500 qemu_put_be32(f, spapr->htab_shift);
1501
1502 if (spapr->htab) {
1503 spapr->htab_save_index = 0;
1504 spapr->htab_first_pass = true;
1505 } else {
1506 assert(kvm_enabled());
1507 }
1508
1509
1510 return 0;
1511 }
1512
1513 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1514 int64_t max_ns)
1515 {
1516 bool has_timeout = max_ns != -1;
1517 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1518 int index = spapr->htab_save_index;
1519 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1520
1521 assert(spapr->htab_first_pass);
1522
1523 do {
1524 int chunkstart;
1525
1526 /* Consume invalid HPTEs */
1527 while ((index < htabslots)
1528 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1529 index++;
1530 CLEAN_HPTE(HPTE(spapr->htab, index));
1531 }
1532
1533 /* Consume valid HPTEs */
1534 chunkstart = index;
1535 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1536 && HPTE_VALID(HPTE(spapr->htab, index))) {
1537 index++;
1538 CLEAN_HPTE(HPTE(spapr->htab, index));
1539 }
1540
1541 if (index > chunkstart) {
1542 int n_valid = index - chunkstart;
1543
1544 qemu_put_be32(f, chunkstart);
1545 qemu_put_be16(f, n_valid);
1546 qemu_put_be16(f, 0);
1547 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1548 HASH_PTE_SIZE_64 * n_valid);
1549
1550 if (has_timeout &&
1551 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1552 break;
1553 }
1554 }
1555 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1556
1557 if (index >= htabslots) {
1558 assert(index == htabslots);
1559 index = 0;
1560 spapr->htab_first_pass = false;
1561 }
1562 spapr->htab_save_index = index;
1563 }
1564
1565 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1566 int64_t max_ns)
1567 {
1568 bool final = max_ns < 0;
1569 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1570 int examined = 0, sent = 0;
1571 int index = spapr->htab_save_index;
1572 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1573
1574 assert(!spapr->htab_first_pass);
1575
1576 do {
1577 int chunkstart, invalidstart;
1578
1579 /* Consume non-dirty HPTEs */
1580 while ((index < htabslots)
1581 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1582 index++;
1583 examined++;
1584 }
1585
1586 chunkstart = index;
1587 /* Consume valid dirty HPTEs */
1588 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1589 && HPTE_DIRTY(HPTE(spapr->htab, index))
1590 && HPTE_VALID(HPTE(spapr->htab, index))) {
1591 CLEAN_HPTE(HPTE(spapr->htab, index));
1592 index++;
1593 examined++;
1594 }
1595
1596 invalidstart = index;
1597 /* Consume invalid dirty HPTEs */
1598 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1599 && HPTE_DIRTY(HPTE(spapr->htab, index))
1600 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1601 CLEAN_HPTE(HPTE(spapr->htab, index));
1602 index++;
1603 examined++;
1604 }
1605
1606 if (index > chunkstart) {
1607 int n_valid = invalidstart - chunkstart;
1608 int n_invalid = index - invalidstart;
1609
1610 qemu_put_be32(f, chunkstart);
1611 qemu_put_be16(f, n_valid);
1612 qemu_put_be16(f, n_invalid);
1613 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1614 HASH_PTE_SIZE_64 * n_valid);
1615 sent += index - chunkstart;
1616
1617 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1618 break;
1619 }
1620 }
1621
1622 if (examined >= htabslots) {
1623 break;
1624 }
1625
1626 if (index >= htabslots) {
1627 assert(index == htabslots);
1628 index = 0;
1629 }
1630 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1631
1632 if (index >= htabslots) {
1633 assert(index == htabslots);
1634 index = 0;
1635 }
1636
1637 spapr->htab_save_index = index;
1638
1639 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1640 }
1641
1642 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1643 #define MAX_KVM_BUF_SIZE 2048
1644
1645 static int htab_save_iterate(QEMUFile *f, void *opaque)
1646 {
1647 sPAPRMachineState *spapr = opaque;
1648 int fd;
1649 int rc = 0;
1650
1651 /* Iteration header */
1652 qemu_put_be32(f, 0);
1653
1654 if (!spapr->htab) {
1655 assert(kvm_enabled());
1656
1657 fd = get_htab_fd(spapr);
1658 if (fd < 0) {
1659 return fd;
1660 }
1661
1662 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1663 if (rc < 0) {
1664 return rc;
1665 }
1666 } else if (spapr->htab_first_pass) {
1667 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1668 } else {
1669 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1670 }
1671
1672 /* End marker */
1673 qemu_put_be32(f, 0);
1674 qemu_put_be16(f, 0);
1675 qemu_put_be16(f, 0);
1676
1677 return rc;
1678 }
1679
1680 static int htab_save_complete(QEMUFile *f, void *opaque)
1681 {
1682 sPAPRMachineState *spapr = opaque;
1683 int fd;
1684
1685 /* Iteration header */
1686 qemu_put_be32(f, 0);
1687
1688 if (!spapr->htab) {
1689 int rc;
1690
1691 assert(kvm_enabled());
1692
1693 fd = get_htab_fd(spapr);
1694 if (fd < 0) {
1695 return fd;
1696 }
1697
1698 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1699 if (rc < 0) {
1700 return rc;
1701 }
1702 } else {
1703 if (spapr->htab_first_pass) {
1704 htab_save_first_pass(f, spapr, -1);
1705 }
1706 htab_save_later_pass(f, spapr, -1);
1707 }
1708
1709 /* End marker */
1710 qemu_put_be32(f, 0);
1711 qemu_put_be16(f, 0);
1712 qemu_put_be16(f, 0);
1713
1714 return 0;
1715 }
1716
1717 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1718 {
1719 sPAPRMachineState *spapr = opaque;
1720 uint32_t section_hdr;
1721 int fd = -1;
1722
1723 if (version_id < 1 || version_id > 1) {
1724 error_report("htab_load() bad version");
1725 return -EINVAL;
1726 }
1727
1728 section_hdr = qemu_get_be32(f);
1729
1730 if (section_hdr) {
1731 Error *local_err = NULL;
1732
1733 /* First section gives the htab size */
1734 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1735 if (local_err) {
1736 error_report_err(local_err);
1737 return -EINVAL;
1738 }
1739 return 0;
1740 }
1741
1742 if (!spapr->htab) {
1743 assert(kvm_enabled());
1744
1745 fd = kvmppc_get_htab_fd(true);
1746 if (fd < 0) {
1747 error_report("Unable to open fd to restore KVM hash table: %s",
1748 strerror(errno));
1749 }
1750 }
1751
1752 while (true) {
1753 uint32_t index;
1754 uint16_t n_valid, n_invalid;
1755
1756 index = qemu_get_be32(f);
1757 n_valid = qemu_get_be16(f);
1758 n_invalid = qemu_get_be16(f);
1759
1760 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1761 /* End of Stream */
1762 break;
1763 }
1764
1765 if ((index + n_valid + n_invalid) >
1766 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1767 /* Bad index in stream */
1768 error_report(
1769 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1770 index, n_valid, n_invalid, spapr->htab_shift);
1771 return -EINVAL;
1772 }
1773
1774 if (spapr->htab) {
1775 if (n_valid) {
1776 qemu_get_buffer(f, HPTE(spapr->htab, index),
1777 HASH_PTE_SIZE_64 * n_valid);
1778 }
1779 if (n_invalid) {
1780 memset(HPTE(spapr->htab, index + n_valid), 0,
1781 HASH_PTE_SIZE_64 * n_invalid);
1782 }
1783 } else {
1784 int rc;
1785
1786 assert(fd >= 0);
1787
1788 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1789 if (rc < 0) {
1790 return rc;
1791 }
1792 }
1793 }
1794
1795 if (!spapr->htab) {
1796 assert(fd >= 0);
1797 close(fd);
1798 }
1799
1800 return 0;
1801 }
1802
1803 static void htab_cleanup(void *opaque)
1804 {
1805 sPAPRMachineState *spapr = opaque;
1806
1807 close_htab_fd(spapr);
1808 }
1809
1810 static SaveVMHandlers savevm_htab_handlers = {
1811 .save_live_setup = htab_save_setup,
1812 .save_live_iterate = htab_save_iterate,
1813 .save_live_complete_precopy = htab_save_complete,
1814 .cleanup = htab_cleanup,
1815 .load_state = htab_load,
1816 };
1817
1818 static void spapr_boot_set(void *opaque, const char *boot_device,
1819 Error **errp)
1820 {
1821 MachineState *machine = MACHINE(qdev_get_machine());
1822 machine->boot_order = g_strdup(boot_device);
1823 }
1824
1825 /*
1826 * Reset routine for LMB DR devices.
1827 *
1828 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1829 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1830 * when it walks all its children devices. LMB devices reset occurs
1831 * as part of spapr_ppc_reset().
1832 */
1833 static void spapr_drc_reset(void *opaque)
1834 {
1835 sPAPRDRConnector *drc = opaque;
1836 DeviceState *d = DEVICE(drc);
1837
1838 if (d) {
1839 device_reset(d);
1840 }
1841 }
1842
1843 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1844 {
1845 MachineState *machine = MACHINE(spapr);
1846 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1847 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1848 int i;
1849
1850 for (i = 0; i < nr_lmbs; i++) {
1851 sPAPRDRConnector *drc;
1852 uint64_t addr;
1853
1854 addr = i * lmb_size + spapr->hotplug_memory.base;
1855 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1856 addr/lmb_size);
1857 qemu_register_reset(spapr_drc_reset, drc);
1858 }
1859 }
1860
1861 /*
1862 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1863 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1864 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1865 */
1866 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1867 {
1868 int i;
1869
1870 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1871 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1872 " is not aligned to %llu MiB",
1873 machine->ram_size,
1874 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1875 return;
1876 }
1877
1878 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1879 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1880 " is not aligned to %llu MiB",
1881 machine->ram_size,
1882 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1883 return;
1884 }
1885
1886 for (i = 0; i < nb_numa_nodes; i++) {
1887 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1888 error_setg(errp,
1889 "Node %d memory size 0x%" PRIx64
1890 " is not aligned to %llu MiB",
1891 i, numa_info[i].node_mem,
1892 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1893 return;
1894 }
1895 }
1896 }
1897
1898 /* find cpu slot in machine->possible_cpus by core_id */
1899 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1900 {
1901 int index = id / smp_threads;
1902
1903 if (index >= ms->possible_cpus->len) {
1904 return NULL;
1905 }
1906 if (idx) {
1907 *idx = index;
1908 }
1909 return &ms->possible_cpus->cpus[index];
1910 }
1911
1912 static void spapr_init_cpus(sPAPRMachineState *spapr)
1913 {
1914 MachineState *machine = MACHINE(spapr);
1915 MachineClass *mc = MACHINE_GET_CLASS(machine);
1916 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1917 int smt = kvmppc_smt_threads();
1918 const CPUArchIdList *possible_cpus;
1919 int boot_cores_nr = smp_cpus / smp_threads;
1920 int i;
1921
1922 if (!type) {
1923 error_report("Unable to find sPAPR CPU Core definition");
1924 exit(1);
1925 }
1926
1927 possible_cpus = mc->possible_cpu_arch_ids(machine);
1928 if (mc->has_hotpluggable_cpus) {
1929 if (smp_cpus % smp_threads) {
1930 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1931 smp_cpus, smp_threads);
1932 exit(1);
1933 }
1934 if (max_cpus % smp_threads) {
1935 error_report("max_cpus (%u) must be multiple of threads (%u)",
1936 max_cpus, smp_threads);
1937 exit(1);
1938 }
1939 } else {
1940 if (max_cpus != smp_cpus) {
1941 error_report("This machine version does not support CPU hotplug");
1942 exit(1);
1943 }
1944 boot_cores_nr = possible_cpus->len;
1945 }
1946
1947 for (i = 0; i < possible_cpus->len; i++) {
1948 int core_id = i * smp_threads;
1949
1950 if (mc->has_hotpluggable_cpus) {
1951 sPAPRDRConnector *drc =
1952 spapr_dr_connector_new(OBJECT(spapr),
1953 SPAPR_DR_CONNECTOR_TYPE_CPU,
1954 (core_id / smp_threads) * smt);
1955
1956 qemu_register_reset(spapr_drc_reset, drc);
1957 }
1958
1959 if (i < boot_cores_nr) {
1960 Object *core = object_new(type);
1961 int nr_threads = smp_threads;
1962
1963 /* Handle the partially filled core for older machine types */
1964 if ((i + 1) * smp_threads >= smp_cpus) {
1965 nr_threads = smp_cpus - i * smp_threads;
1966 }
1967
1968 object_property_set_int(core, nr_threads, "nr-threads",
1969 &error_fatal);
1970 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1971 &error_fatal);
1972 object_property_set_bool(core, true, "realized", &error_fatal);
1973 }
1974 }
1975 g_free(type);
1976 }
1977
1978 /* pSeries LPAR / sPAPR hardware init */
1979 static void ppc_spapr_init(MachineState *machine)
1980 {
1981 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1982 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1983 const char *kernel_filename = machine->kernel_filename;
1984 const char *initrd_filename = machine->initrd_filename;
1985 PCIHostState *phb;
1986 int i;
1987 MemoryRegion *sysmem = get_system_memory();
1988 MemoryRegion *ram = g_new(MemoryRegion, 1);
1989 MemoryRegion *rma_region;
1990 void *rma = NULL;
1991 hwaddr rma_alloc_size;
1992 hwaddr node0_size = spapr_node0_size();
1993 long load_limit, fw_size;
1994 char *filename;
1995 int smt = kvmppc_smt_threads();
1996
1997 msi_nonbroken = true;
1998
1999 QLIST_INIT(&spapr->phbs);
2000
2001 /* Allocate RMA if necessary */
2002 rma_alloc_size = kvmppc_alloc_rma(&rma);
2003
2004 if (rma_alloc_size == -1) {
2005 error_report("Unable to create RMA");
2006 exit(1);
2007 }
2008
2009 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2010 spapr->rma_size = rma_alloc_size;
2011 } else {
2012 spapr->rma_size = node0_size;
2013
2014 /* With KVM, we don't actually know whether KVM supports an
2015 * unbounded RMA (PR KVM) or is limited by the hash table size
2016 * (HV KVM using VRMA), so we always assume the latter
2017 *
2018 * In that case, we also limit the initial allocations for RTAS
2019 * etc... to 256M since we have no way to know what the VRMA size
2020 * is going to be as it depends on the size of the hash table
2021 * isn't determined yet.
2022 */
2023 if (kvm_enabled()) {
2024 spapr->vrma_adjust = 1;
2025 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2026 }
2027
2028 /* Actually we don't support unbounded RMA anymore since we
2029 * added proper emulation of HV mode. The max we can get is
2030 * 16G which also happens to be what we configure for PAPR
2031 * mode so make sure we don't do anything bigger than that
2032 */
2033 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2034 }
2035
2036 if (spapr->rma_size > node0_size) {
2037 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2038 spapr->rma_size);
2039 exit(1);
2040 }
2041
2042 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2043 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2044
2045 /* Set up Interrupt Controller before we create the VCPUs */
2046 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads),
2047 XICS_IRQS_SPAPR, &error_fatal);
2048
2049 /* Set up containers for ibm,client-set-architecture negotiated options */
2050 spapr->ov5 = spapr_ovec_new();
2051 spapr->ov5_cas = spapr_ovec_new();
2052
2053 if (smc->dr_lmb_enabled) {
2054 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2055 spapr_validate_node_memory(machine, &error_fatal);
2056 }
2057
2058 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2059
2060 /* advertise support for dedicated HP event source to guests */
2061 if (spapr->use_hotplug_event_source) {
2062 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2063 }
2064
2065 /* init CPUs */
2066 if (machine->cpu_model == NULL) {
2067 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2068 }
2069
2070 ppc_cpu_parse_features(machine->cpu_model);
2071
2072 spapr_init_cpus(spapr);
2073
2074 if (kvm_enabled()) {
2075 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2076 kvmppc_enable_logical_ci_hcalls();
2077 kvmppc_enable_set_mode_hcall();
2078
2079 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2080 kvmppc_enable_clear_ref_mod_hcalls();
2081 }
2082
2083 /* allocate RAM */
2084 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2085 machine->ram_size);
2086 memory_region_add_subregion(sysmem, 0, ram);
2087
2088 if (rma_alloc_size && rma) {
2089 rma_region = g_new(MemoryRegion, 1);
2090 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2091 rma_alloc_size, rma);
2092 vmstate_register_ram_global(rma_region);
2093 memory_region_add_subregion(sysmem, 0, rma_region);
2094 }
2095
2096 /* initialize hotplug memory address space */
2097 if (machine->ram_size < machine->maxram_size) {
2098 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2099 /*
2100 * Limit the number of hotpluggable memory slots to half the number
2101 * slots that KVM supports, leaving the other half for PCI and other
2102 * devices. However ensure that number of slots doesn't drop below 32.
2103 */
2104 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2105 SPAPR_MAX_RAM_SLOTS;
2106
2107 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2108 max_memslots = SPAPR_MAX_RAM_SLOTS;
2109 }
2110 if (machine->ram_slots > max_memslots) {
2111 error_report("Specified number of memory slots %"
2112 PRIu64" exceeds max supported %d",
2113 machine->ram_slots, max_memslots);
2114 exit(1);
2115 }
2116
2117 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2118 SPAPR_HOTPLUG_MEM_ALIGN);
2119 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2120 "hotplug-memory", hotplug_mem_size);
2121 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2122 &spapr->hotplug_memory.mr);
2123 }
2124
2125 if (smc->dr_lmb_enabled) {
2126 spapr_create_lmb_dr_connectors(spapr);
2127 }
2128
2129 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2130 if (!filename) {
2131 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2132 exit(1);
2133 }
2134 spapr->rtas_size = get_image_size(filename);
2135 if (spapr->rtas_size < 0) {
2136 error_report("Could not get size of LPAR rtas '%s'", filename);
2137 exit(1);
2138 }
2139 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2140 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2141 error_report("Could not load LPAR rtas '%s'", filename);
2142 exit(1);
2143 }
2144 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2145 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2146 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2147 exit(1);
2148 }
2149 g_free(filename);
2150
2151 /* Set up RTAS event infrastructure */
2152 spapr_events_init(spapr);
2153
2154 /* Set up the RTC RTAS interfaces */
2155 spapr_rtc_create(spapr);
2156
2157 /* Set up VIO bus */
2158 spapr->vio_bus = spapr_vio_bus_init();
2159
2160 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2161 if (serial_hds[i]) {
2162 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2163 }
2164 }
2165
2166 /* We always have at least the nvram device on VIO */
2167 spapr_create_nvram(spapr);
2168
2169 /* Set up PCI */
2170 spapr_pci_rtas_init();
2171
2172 phb = spapr_create_phb(spapr, 0);
2173
2174 for (i = 0; i < nb_nics; i++) {
2175 NICInfo *nd = &nd_table[i];
2176
2177 if (!nd->model) {
2178 nd->model = g_strdup("ibmveth");
2179 }
2180
2181 if (strcmp(nd->model, "ibmveth") == 0) {
2182 spapr_vlan_create(spapr->vio_bus, nd);
2183 } else {
2184 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2185 }
2186 }
2187
2188 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2189 spapr_vscsi_create(spapr->vio_bus);
2190 }
2191
2192 /* Graphics */
2193 if (spapr_vga_init(phb->bus, &error_fatal)) {
2194 spapr->has_graphics = true;
2195 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2196 }
2197
2198 if (machine->usb) {
2199 if (smc->use_ohci_by_default) {
2200 pci_create_simple(phb->bus, -1, "pci-ohci");
2201 } else {
2202 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2203 }
2204
2205 if (spapr->has_graphics) {
2206 USBBus *usb_bus = usb_bus_find(-1);
2207
2208 usb_create_simple(usb_bus, "usb-kbd");
2209 usb_create_simple(usb_bus, "usb-mouse");
2210 }
2211 }
2212
2213 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2214 error_report(
2215 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2216 MIN_RMA_SLOF);
2217 exit(1);
2218 }
2219
2220 if (kernel_filename) {
2221 uint64_t lowaddr = 0;
2222
2223 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2224 NULL, NULL, &lowaddr, NULL, 1,
2225 PPC_ELF_MACHINE, 0, 0);
2226 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2227 spapr->kernel_size = load_elf(kernel_filename,
2228 translate_kernel_address, NULL, NULL,
2229 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2230 0, 0);
2231 spapr->kernel_le = spapr->kernel_size > 0;
2232 }
2233 if (spapr->kernel_size < 0) {
2234 error_report("error loading %s: %s", kernel_filename,
2235 load_elf_strerror(spapr->kernel_size));
2236 exit(1);
2237 }
2238
2239 /* load initrd */
2240 if (initrd_filename) {
2241 /* Try to locate the initrd in the gap between the kernel
2242 * and the firmware. Add a bit of space just in case
2243 */
2244 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2245 + 0x1ffff) & ~0xffff;
2246 spapr->initrd_size = load_image_targphys(initrd_filename,
2247 spapr->initrd_base,
2248 load_limit
2249 - spapr->initrd_base);
2250 if (spapr->initrd_size < 0) {
2251 error_report("could not load initial ram disk '%s'",
2252 initrd_filename);
2253 exit(1);
2254 }
2255 }
2256 }
2257
2258 if (bios_name == NULL) {
2259 bios_name = FW_FILE_NAME;
2260 }
2261 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2262 if (!filename) {
2263 error_report("Could not find LPAR firmware '%s'", bios_name);
2264 exit(1);
2265 }
2266 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2267 if (fw_size <= 0) {
2268 error_report("Could not load LPAR firmware '%s'", filename);
2269 exit(1);
2270 }
2271 g_free(filename);
2272
2273 /* FIXME: Should register things through the MachineState's qdev
2274 * interface, this is a legacy from the sPAPREnvironment structure
2275 * which predated MachineState but had a similar function */
2276 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2277 register_savevm_live(NULL, "spapr/htab", -1, 1,
2278 &savevm_htab_handlers, spapr);
2279
2280 /* used by RTAS */
2281 QTAILQ_INIT(&spapr->ccs_list);
2282 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2283
2284 qemu_register_boot_set(spapr_boot_set, spapr);
2285
2286 /* to stop and start vmclock */
2287 if (kvm_enabled()) {
2288 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2289 &spapr->tb);
2290 }
2291 }
2292
2293 static int spapr_kvm_type(const char *vm_type)
2294 {
2295 if (!vm_type) {
2296 return 0;
2297 }
2298
2299 if (!strcmp(vm_type, "HV")) {
2300 return 1;
2301 }
2302
2303 if (!strcmp(vm_type, "PR")) {
2304 return 2;
2305 }
2306
2307 error_report("Unknown kvm-type specified '%s'", vm_type);
2308 exit(1);
2309 }
2310
2311 /*
2312 * Implementation of an interface to adjust firmware path
2313 * for the bootindex property handling.
2314 */
2315 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2316 DeviceState *dev)
2317 {
2318 #define CAST(type, obj, name) \
2319 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2320 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2321 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2322
2323 if (d) {
2324 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2325 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2326 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2327
2328 if (spapr) {
2329 /*
2330 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2331 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2332 * in the top 16 bits of the 64-bit LUN
2333 */
2334 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2335 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2336 (uint64_t)id << 48);
2337 } else if (virtio) {
2338 /*
2339 * We use SRP luns of the form 01000000 | (target << 8) | lun
2340 * in the top 32 bits of the 64-bit LUN
2341 * Note: the quote above is from SLOF and it is wrong,
2342 * the actual binding is:
2343 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2344 */
2345 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2346 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2347 (uint64_t)id << 32);
2348 } else if (usb) {
2349 /*
2350 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2351 * in the top 32 bits of the 64-bit LUN
2352 */
2353 unsigned usb_port = atoi(usb->port->path);
2354 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2355 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2356 (uint64_t)id << 32);
2357 }
2358 }
2359
2360 /*
2361 * SLOF probes the USB devices, and if it recognizes that the device is a
2362 * storage device, it changes its name to "storage" instead of "usb-host",
2363 * and additionally adds a child node for the SCSI LUN, so the correct
2364 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2365 */
2366 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2367 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2368 if (usb_host_dev_is_scsi_storage(usbdev)) {
2369 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2370 }
2371 }
2372
2373 if (phb) {
2374 /* Replace "pci" with "pci@800000020000000" */
2375 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2376 }
2377
2378 return NULL;
2379 }
2380
2381 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2382 {
2383 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2384
2385 return g_strdup(spapr->kvm_type);
2386 }
2387
2388 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2389 {
2390 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2391
2392 g_free(spapr->kvm_type);
2393 spapr->kvm_type = g_strdup(value);
2394 }
2395
2396 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2397 {
2398 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2399
2400 return spapr->use_hotplug_event_source;
2401 }
2402
2403 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2404 Error **errp)
2405 {
2406 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2407
2408 spapr->use_hotplug_event_source = value;
2409 }
2410
2411 static void spapr_machine_initfn(Object *obj)
2412 {
2413 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2414
2415 spapr->htab_fd = -1;
2416 spapr->use_hotplug_event_source = true;
2417 object_property_add_str(obj, "kvm-type",
2418 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2419 object_property_set_description(obj, "kvm-type",
2420 "Specifies the KVM virtualization mode (HV, PR)",
2421 NULL);
2422 object_property_add_bool(obj, "modern-hotplug-events",
2423 spapr_get_modern_hotplug_events,
2424 spapr_set_modern_hotplug_events,
2425 NULL);
2426 object_property_set_description(obj, "modern-hotplug-events",
2427 "Use dedicated hotplug event mechanism in"
2428 " place of standard EPOW events when possible"
2429 " (required for memory hot-unplug support)",
2430 NULL);
2431 }
2432
2433 static void spapr_machine_finalizefn(Object *obj)
2434 {
2435 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2436
2437 g_free(spapr->kvm_type);
2438 }
2439
2440 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2441 {
2442 cpu_synchronize_state(cs);
2443 ppc_cpu_do_system_reset(cs);
2444 }
2445
2446 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2447 {
2448 CPUState *cs;
2449
2450 CPU_FOREACH(cs) {
2451 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2452 }
2453 }
2454
2455 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2456 uint32_t node, bool dedicated_hp_event_source,
2457 Error **errp)
2458 {
2459 sPAPRDRConnector *drc;
2460 sPAPRDRConnectorClass *drck;
2461 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2462 int i, fdt_offset, fdt_size;
2463 void *fdt;
2464 uint64_t addr = addr_start;
2465
2466 for (i = 0; i < nr_lmbs; i++) {
2467 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2468 addr/SPAPR_MEMORY_BLOCK_SIZE);
2469 g_assert(drc);
2470
2471 fdt = create_device_tree(&fdt_size);
2472 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2473 SPAPR_MEMORY_BLOCK_SIZE);
2474
2475 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2476 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2477 addr += SPAPR_MEMORY_BLOCK_SIZE;
2478 if (!dev->hotplugged) {
2479 /* guests expect coldplugged LMBs to be pre-allocated */
2480 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2481 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2482 }
2483 }
2484 /* send hotplug notification to the
2485 * guest only in case of hotplugged memory
2486 */
2487 if (dev->hotplugged) {
2488 if (dedicated_hp_event_source) {
2489 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2490 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2491 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2492 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2493 nr_lmbs,
2494 drck->get_index(drc));
2495 } else {
2496 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2497 nr_lmbs);
2498 }
2499 }
2500 }
2501
2502 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2503 uint32_t node, Error **errp)
2504 {
2505 Error *local_err = NULL;
2506 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2507 PCDIMMDevice *dimm = PC_DIMM(dev);
2508 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2509 MemoryRegion *mr = ddc->get_memory_region(dimm);
2510 uint64_t align = memory_region_get_alignment(mr);
2511 uint64_t size = memory_region_size(mr);
2512 uint64_t addr;
2513 char *mem_dev;
2514
2515 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2516 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2517 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2518 goto out;
2519 }
2520
2521 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2522 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2523 error_setg(&local_err, "Memory backend has bad page size. "
2524 "Use 'memory-backend-file' with correct mem-path.");
2525 goto out;
2526 }
2527
2528 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2529 if (local_err) {
2530 goto out;
2531 }
2532
2533 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2534 if (local_err) {
2535 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2536 goto out;
2537 }
2538
2539 spapr_add_lmbs(dev, addr, size, node,
2540 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2541 &error_abort);
2542
2543 out:
2544 error_propagate(errp, local_err);
2545 }
2546
2547 typedef struct sPAPRDIMMState {
2548 uint32_t nr_lmbs;
2549 } sPAPRDIMMState;
2550
2551 static void spapr_lmb_release(DeviceState *dev, void *opaque)
2552 {
2553 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque;
2554 HotplugHandler *hotplug_ctrl;
2555
2556 if (--ds->nr_lmbs) {
2557 return;
2558 }
2559
2560 g_free(ds);
2561
2562 /*
2563 * Now that all the LMBs have been removed by the guest, call the
2564 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2565 */
2566 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2567 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2568 }
2569
2570 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2571 Error **errp)
2572 {
2573 sPAPRDRConnector *drc;
2574 sPAPRDRConnectorClass *drck;
2575 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2576 int i;
2577 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState));
2578 uint64_t addr = addr_start;
2579
2580 ds->nr_lmbs = nr_lmbs;
2581 for (i = 0; i < nr_lmbs; i++) {
2582 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2583 addr / SPAPR_MEMORY_BLOCK_SIZE);
2584 g_assert(drc);
2585
2586 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2587 drck->detach(drc, dev, spapr_lmb_release, ds, errp);
2588 addr += SPAPR_MEMORY_BLOCK_SIZE;
2589 }
2590
2591 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2592 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2593 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2594 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2595 nr_lmbs,
2596 drck->get_index(drc));
2597 }
2598
2599 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2600 Error **errp)
2601 {
2602 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2603 PCDIMMDevice *dimm = PC_DIMM(dev);
2604 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2605 MemoryRegion *mr = ddc->get_memory_region(dimm);
2606
2607 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2608 object_unparent(OBJECT(dev));
2609 }
2610
2611 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2612 DeviceState *dev, Error **errp)
2613 {
2614 Error *local_err = NULL;
2615 PCDIMMDevice *dimm = PC_DIMM(dev);
2616 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2617 MemoryRegion *mr = ddc->get_memory_region(dimm);
2618 uint64_t size = memory_region_size(mr);
2619 uint64_t addr;
2620
2621 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2622 if (local_err) {
2623 goto out;
2624 }
2625
2626 spapr_del_lmbs(dev, addr, size, &error_abort);
2627 out:
2628 error_propagate(errp, local_err);
2629 }
2630
2631 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2632 sPAPRMachineState *spapr)
2633 {
2634 PowerPCCPU *cpu = POWERPC_CPU(cs);
2635 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2636 int id = ppc_get_vcpu_dt_id(cpu);
2637 void *fdt;
2638 int offset, fdt_size;
2639 char *nodename;
2640
2641 fdt = create_device_tree(&fdt_size);
2642 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2643 offset = fdt_add_subnode(fdt, 0, nodename);
2644
2645 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2646 g_free(nodename);
2647
2648 *fdt_offset = offset;
2649 return fdt;
2650 }
2651
2652 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2653 Error **errp)
2654 {
2655 MachineState *ms = MACHINE(qdev_get_machine());
2656 CPUCore *cc = CPU_CORE(dev);
2657 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2658
2659 core_slot->cpu = NULL;
2660 object_unparent(OBJECT(dev));
2661 }
2662
2663 static void spapr_core_release(DeviceState *dev, void *opaque)
2664 {
2665 HotplugHandler *hotplug_ctrl;
2666
2667 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2668 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2669 }
2670
2671 static
2672 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2673 Error **errp)
2674 {
2675 int index;
2676 sPAPRDRConnector *drc;
2677 sPAPRDRConnectorClass *drck;
2678 Error *local_err = NULL;
2679 CPUCore *cc = CPU_CORE(dev);
2680 int smt = kvmppc_smt_threads();
2681
2682 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2683 error_setg(errp, "Unable to find CPU core with core-id: %d",
2684 cc->core_id);
2685 return;
2686 }
2687 if (index == 0) {
2688 error_setg(errp, "Boot CPU core may not be unplugged");
2689 return;
2690 }
2691
2692 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2693 g_assert(drc);
2694
2695 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2696 drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
2697 if (local_err) {
2698 error_propagate(errp, local_err);
2699 return;
2700 }
2701
2702 spapr_hotplug_req_remove_by_index(drc);
2703 }
2704
2705 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2706 Error **errp)
2707 {
2708 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2709 MachineClass *mc = MACHINE_GET_CLASS(spapr);
2710 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2711 CPUCore *cc = CPU_CORE(dev);
2712 CPUState *cs = CPU(core->threads);
2713 sPAPRDRConnector *drc;
2714 Error *local_err = NULL;
2715 void *fdt = NULL;
2716 int fdt_offset = 0;
2717 int smt = kvmppc_smt_threads();
2718 CPUArchId *core_slot;
2719 int index;
2720
2721 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2722 if (!core_slot) {
2723 error_setg(errp, "Unable to find CPU core with core-id: %d",
2724 cc->core_id);
2725 return;
2726 }
2727 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2728
2729 g_assert(drc || !mc->has_hotpluggable_cpus);
2730
2731 /*
2732 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2733 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2734 */
2735 if (dev->hotplugged) {
2736 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2737 }
2738
2739 if (drc) {
2740 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2741 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2742 if (local_err) {
2743 g_free(fdt);
2744 error_propagate(errp, local_err);
2745 return;
2746 }
2747 }
2748
2749 if (dev->hotplugged) {
2750 /*
2751 * Send hotplug notification interrupt to the guest only in case
2752 * of hotplugged CPUs.
2753 */
2754 spapr_hotplug_req_add_by_index(drc);
2755 } else {
2756 /*
2757 * Set the right DRC states for cold plugged CPU.
2758 */
2759 if (drc) {
2760 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2761 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2762 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2763 }
2764 }
2765 core_slot->cpu = OBJECT(dev);
2766 }
2767
2768 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2769 Error **errp)
2770 {
2771 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2772 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2773 Error *local_err = NULL;
2774 CPUCore *cc = CPU_CORE(dev);
2775 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2776 const char *type = object_get_typename(OBJECT(dev));
2777 CPUArchId *core_slot;
2778 int index;
2779
2780 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2781 error_setg(&local_err, "CPU hotplug not supported for this machine");
2782 goto out;
2783 }
2784
2785 if (strcmp(base_core_type, type)) {
2786 error_setg(&local_err, "CPU core type should be %s", base_core_type);
2787 goto out;
2788 }
2789
2790 if (cc->core_id % smp_threads) {
2791 error_setg(&local_err, "invalid core id %d", cc->core_id);
2792 goto out;
2793 }
2794
2795 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2796 if (!core_slot) {
2797 error_setg(&local_err, "core id %d out of range", cc->core_id);
2798 goto out;
2799 }
2800
2801 if (core_slot->cpu) {
2802 error_setg(&local_err, "core %d already populated", cc->core_id);
2803 goto out;
2804 }
2805
2806 out:
2807 g_free(base_core_type);
2808 error_propagate(errp, local_err);
2809 }
2810
2811 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2812 DeviceState *dev, Error **errp)
2813 {
2814 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2815
2816 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2817 int node;
2818
2819 if (!smc->dr_lmb_enabled) {
2820 error_setg(errp, "Memory hotplug not supported for this machine");
2821 return;
2822 }
2823 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2824 if (*errp) {
2825 return;
2826 }
2827 if (node < 0 || node >= MAX_NODES) {
2828 error_setg(errp, "Invaild node %d", node);
2829 return;
2830 }
2831
2832 /*
2833 * Currently PowerPC kernel doesn't allow hot-adding memory to
2834 * memory-less node, but instead will silently add the memory
2835 * to the first node that has some memory. This causes two
2836 * unexpected behaviours for the user.
2837 *
2838 * - Memory gets hotplugged to a different node than what the user
2839 * specified.
2840 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2841 * to memory-less node, a reboot will set things accordingly
2842 * and the previously hotplugged memory now ends in the right node.
2843 * This appears as if some memory moved from one node to another.
2844 *
2845 * So until kernel starts supporting memory hotplug to memory-less
2846 * nodes, just prevent such attempts upfront in QEMU.
2847 */
2848 if (nb_numa_nodes && !numa_info[node].node_mem) {
2849 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2850 node);
2851 return;
2852 }
2853
2854 spapr_memory_plug(hotplug_dev, dev, node, errp);
2855 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2856 spapr_core_plug(hotplug_dev, dev, errp);
2857 }
2858 }
2859
2860 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2861 DeviceState *dev, Error **errp)
2862 {
2863 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2864 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2865
2866 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2867 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2868 spapr_memory_unplug(hotplug_dev, dev, errp);
2869 } else {
2870 error_setg(errp, "Memory hot unplug not supported for this guest");
2871 }
2872 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2873 if (!mc->has_hotpluggable_cpus) {
2874 error_setg(errp, "CPU hot unplug not supported on this machine");
2875 return;
2876 }
2877 spapr_core_unplug(hotplug_dev, dev, errp);
2878 }
2879 }
2880
2881 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
2882 DeviceState *dev, Error **errp)
2883 {
2884 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2885 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2886
2887 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2888 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2889 spapr_memory_unplug_request(hotplug_dev, dev, errp);
2890 } else {
2891 /* NOTE: this means there is a window after guest reset, prior to
2892 * CAS negotiation, where unplug requests will fail due to the
2893 * capability not being detected yet. This is a bit different than
2894 * the case with PCI unplug, where the events will be queued and
2895 * eventually handled by the guest after boot
2896 */
2897 error_setg(errp, "Memory hot unplug not supported for this guest");
2898 }
2899 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2900 if (!mc->has_hotpluggable_cpus) {
2901 error_setg(errp, "CPU hot unplug not supported on this machine");
2902 return;
2903 }
2904 spapr_core_unplug_request(hotplug_dev, dev, errp);
2905 }
2906 }
2907
2908 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2909 DeviceState *dev, Error **errp)
2910 {
2911 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2912 spapr_core_pre_plug(hotplug_dev, dev, errp);
2913 }
2914 }
2915
2916 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2917 DeviceState *dev)
2918 {
2919 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2920 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2921 return HOTPLUG_HANDLER(machine);
2922 }
2923 return NULL;
2924 }
2925
2926 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2927 {
2928 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2929 * socket means much for the paravirtualized PAPR platform) */
2930 return cpu_index / smp_threads / smp_cores;
2931 }
2932
2933 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
2934 {
2935 int i;
2936 int spapr_max_cores = max_cpus / smp_threads;
2937 MachineClass *mc = MACHINE_GET_CLASS(machine);
2938
2939 if (!mc->has_hotpluggable_cpus) {
2940 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
2941 }
2942 if (machine->possible_cpus) {
2943 assert(machine->possible_cpus->len == spapr_max_cores);
2944 return machine->possible_cpus;
2945 }
2946
2947 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2948 sizeof(CPUArchId) * spapr_max_cores);
2949 machine->possible_cpus->len = spapr_max_cores;
2950 for (i = 0; i < machine->possible_cpus->len; i++) {
2951 int core_id = i * smp_threads;
2952
2953 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
2954 machine->possible_cpus->cpus[i].arch_id = core_id;
2955 machine->possible_cpus->cpus[i].props.has_core_id = true;
2956 machine->possible_cpus->cpus[i].props.core_id = core_id;
2957 /* TODO: add 'has_node/node' here to describe
2958 to which node core belongs */
2959 }
2960 return machine->possible_cpus;
2961 }
2962
2963 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2964 uint64_t *buid, hwaddr *pio,
2965 hwaddr *mmio32, hwaddr *mmio64,
2966 unsigned n_dma, uint32_t *liobns, Error **errp)
2967 {
2968 /*
2969 * New-style PHB window placement.
2970 *
2971 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2972 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2973 * windows.
2974 *
2975 * Some guest kernels can't work with MMIO windows above 1<<46
2976 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2977 *
2978 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2979 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2980 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2981 * 1TiB 64-bit MMIO windows for each PHB.
2982 */
2983 const uint64_t base_buid = 0x800000020000000ULL;
2984 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
2985 SPAPR_PCI_MEM64_WIN_SIZE - 1)
2986 int i;
2987
2988 /* Sanity check natural alignments */
2989 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2990 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2991 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2992 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2993 /* Sanity check bounds */
2994 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
2995 SPAPR_PCI_MEM32_WIN_SIZE);
2996 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
2997 SPAPR_PCI_MEM64_WIN_SIZE);
2998
2999 if (index >= SPAPR_MAX_PHBS) {
3000 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3001 SPAPR_MAX_PHBS - 1);
3002 return;
3003 }
3004
3005 *buid = base_buid + index;
3006 for (i = 0; i < n_dma; ++i) {
3007 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3008 }
3009
3010 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3011 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3012 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3013 }
3014
3015 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3016 {
3017 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3018
3019 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3020 }
3021
3022 static void spapr_ics_resend(XICSFabric *dev)
3023 {
3024 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3025
3026 ics_resend(spapr->ics);
3027 }
3028
3029 static ICPState *spapr_icp_get(XICSFabric *xi, int server)
3030 {
3031 sPAPRMachineState *spapr = SPAPR_MACHINE(xi);
3032
3033 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL;
3034 }
3035
3036 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3037 Monitor *mon)
3038 {
3039 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3040 int i;
3041
3042 for (i = 0; i < spapr->nr_servers; i++) {
3043 icp_pic_print_info(&spapr->icps[i], mon);
3044 }
3045
3046 ics_pic_print_info(spapr->ics, mon);
3047 }
3048
3049 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3050 {
3051 MachineClass *mc = MACHINE_CLASS(oc);
3052 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3053 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3054 NMIClass *nc = NMI_CLASS(oc);
3055 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3056 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3057 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3058 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3059
3060 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3061
3062 /*
3063 * We set up the default / latest behaviour here. The class_init
3064 * functions for the specific versioned machine types can override
3065 * these details for backwards compatibility
3066 */
3067 mc->init = ppc_spapr_init;
3068 mc->reset = ppc_spapr_reset;
3069 mc->block_default_type = IF_SCSI;
3070 mc->max_cpus = 1024;
3071 mc->no_parallel = 1;
3072 mc->default_boot_order = "";
3073 mc->default_ram_size = 512 * M_BYTE;
3074 mc->kvm_type = spapr_kvm_type;
3075 mc->has_dynamic_sysbus = true;
3076 mc->pci_allow_0_address = true;
3077 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3078 hc->pre_plug = spapr_machine_device_pre_plug;
3079 hc->plug = spapr_machine_device_plug;
3080 hc->unplug = spapr_machine_device_unplug;
3081 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
3082 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3083 hc->unplug_request = spapr_machine_device_unplug_request;
3084
3085 smc->dr_lmb_enabled = true;
3086 smc->tcg_default_cpu = "POWER8";
3087 mc->has_hotpluggable_cpus = true;
3088 fwc->get_dev_path = spapr_get_fw_dev_path;
3089 nc->nmi_monitor_handler = spapr_nmi;
3090 smc->phb_placement = spapr_phb_placement;
3091 vhc->hypercall = emulate_spapr_hypercall;
3092 vhc->hpt_mask = spapr_hpt_mask;
3093 vhc->map_hptes = spapr_map_hptes;
3094 vhc->unmap_hptes = spapr_unmap_hptes;
3095 vhc->store_hpte = spapr_store_hpte;
3096 vhc->get_patbe = spapr_get_patbe;
3097 xic->ics_get = spapr_ics_get;
3098 xic->ics_resend = spapr_ics_resend;
3099 xic->icp_get = spapr_icp_get;
3100 ispc->print_info = spapr_pic_print_info;
3101 }
3102
3103 static const TypeInfo spapr_machine_info = {
3104 .name = TYPE_SPAPR_MACHINE,
3105 .parent = TYPE_MACHINE,
3106 .abstract = true,
3107 .instance_size = sizeof(sPAPRMachineState),
3108 .instance_init = spapr_machine_initfn,
3109 .instance_finalize = spapr_machine_finalizefn,
3110 .class_size = sizeof(sPAPRMachineClass),
3111 .class_init = spapr_machine_class_init,
3112 .interfaces = (InterfaceInfo[]) {
3113 { TYPE_FW_PATH_PROVIDER },
3114 { TYPE_NMI },
3115 { TYPE_HOTPLUG_HANDLER },
3116 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3117 { TYPE_XICS_FABRIC },
3118 { TYPE_INTERRUPT_STATS_PROVIDER },
3119 { }
3120 },
3121 };
3122
3123 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3124 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3125 void *data) \
3126 { \
3127 MachineClass *mc = MACHINE_CLASS(oc); \
3128 spapr_machine_##suffix##_class_options(mc); \
3129 if (latest) { \
3130 mc->alias = "pseries"; \
3131 mc->is_default = 1; \
3132 } \
3133 } \
3134 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3135 { \
3136 MachineState *machine = MACHINE(obj); \
3137 spapr_machine_##suffix##_instance_options(machine); \
3138 } \
3139 static const TypeInfo spapr_machine_##suffix##_info = { \
3140 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3141 .parent = TYPE_SPAPR_MACHINE, \
3142 .class_init = spapr_machine_##suffix##_class_init, \
3143 .instance_init = spapr_machine_##suffix##_instance_init, \
3144 }; \
3145 static void spapr_machine_register_##suffix(void) \
3146 { \
3147 type_register(&spapr_machine_##suffix##_info); \
3148 } \
3149 type_init(spapr_machine_register_##suffix)
3150
3151 /*
3152 * pseries-2.9
3153 */
3154 static void spapr_machine_2_9_instance_options(MachineState *machine)
3155 {
3156 }
3157
3158 static void spapr_machine_2_9_class_options(MachineClass *mc)
3159 {
3160 /* Defaults for the latest behaviour inherited from the base class */
3161 }
3162
3163 DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
3164
3165 /*
3166 * pseries-2.8
3167 */
3168 #define SPAPR_COMPAT_2_8 \
3169 HW_COMPAT_2_8
3170
3171 static void spapr_machine_2_8_instance_options(MachineState *machine)
3172 {
3173 spapr_machine_2_9_instance_options(machine);
3174 }
3175
3176 static void spapr_machine_2_8_class_options(MachineClass *mc)
3177 {
3178 spapr_machine_2_9_class_options(mc);
3179 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3180 }
3181
3182 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3183
3184 /*
3185 * pseries-2.7
3186 */
3187 #define SPAPR_COMPAT_2_7 \
3188 HW_COMPAT_2_7 \
3189 { \
3190 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3191 .property = "mem_win_size", \
3192 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3193 }, \
3194 { \
3195 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3196 .property = "mem64_win_size", \
3197 .value = "0", \
3198 }, \
3199 { \
3200 .driver = TYPE_POWERPC_CPU, \
3201 .property = "pre-2.8-migration", \
3202 .value = "on", \
3203 }, \
3204 { \
3205 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3206 .property = "pre-2.8-migration", \
3207 .value = "on", \
3208 },
3209
3210 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3211 uint64_t *buid, hwaddr *pio,
3212 hwaddr *mmio32, hwaddr *mmio64,
3213 unsigned n_dma, uint32_t *liobns, Error **errp)
3214 {
3215 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3216 const uint64_t base_buid = 0x800000020000000ULL;
3217 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3218 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3219 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3220 const uint32_t max_index = 255;
3221 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3222
3223 uint64_t ram_top = MACHINE(spapr)->ram_size;
3224 hwaddr phb0_base, phb_base;
3225 int i;
3226
3227 /* Do we have hotpluggable memory? */
3228 if (MACHINE(spapr)->maxram_size > ram_top) {
3229 /* Can't just use maxram_size, because there may be an
3230 * alignment gap between normal and hotpluggable memory
3231 * regions */
3232 ram_top = spapr->hotplug_memory.base +
3233 memory_region_size(&spapr->hotplug_memory.mr);
3234 }
3235
3236 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3237
3238 if (index > max_index) {
3239 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3240 max_index);
3241 return;
3242 }
3243
3244 *buid = base_buid + index;
3245 for (i = 0; i < n_dma; ++i) {
3246 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3247 }
3248
3249 phb_base = phb0_base + index * phb_spacing;
3250 *pio = phb_base + pio_offset;
3251 *mmio32 = phb_base + mmio_offset;
3252 /*
3253 * We don't set the 64-bit MMIO window, relying on the PHB's
3254 * fallback behaviour of automatically splitting a large "32-bit"
3255 * window into contiguous 32-bit and 64-bit windows
3256 */
3257 }
3258
3259 static void spapr_machine_2_7_instance_options(MachineState *machine)
3260 {
3261 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3262
3263 spapr_machine_2_8_instance_options(machine);
3264 spapr->use_hotplug_event_source = false;
3265 }
3266
3267 static void spapr_machine_2_7_class_options(MachineClass *mc)
3268 {
3269 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3270
3271 spapr_machine_2_8_class_options(mc);
3272 smc->tcg_default_cpu = "POWER7";
3273 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3274 smc->phb_placement = phb_placement_2_7;
3275 }
3276
3277 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3278
3279 /*
3280 * pseries-2.6
3281 */
3282 #define SPAPR_COMPAT_2_6 \
3283 HW_COMPAT_2_6 \
3284 { \
3285 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3286 .property = "ddw",\
3287 .value = stringify(off),\
3288 },
3289
3290 static void spapr_machine_2_6_instance_options(MachineState *machine)
3291 {
3292 spapr_machine_2_7_instance_options(machine);
3293 }
3294
3295 static void spapr_machine_2_6_class_options(MachineClass *mc)
3296 {
3297 spapr_machine_2_7_class_options(mc);
3298 mc->has_hotpluggable_cpus = false;
3299 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3300 }
3301
3302 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3303
3304 /*
3305 * pseries-2.5
3306 */
3307 #define SPAPR_COMPAT_2_5 \
3308 HW_COMPAT_2_5 \
3309 { \
3310 .driver = "spapr-vlan", \
3311 .property = "use-rx-buffer-pools", \
3312 .value = "off", \
3313 },
3314
3315 static void spapr_machine_2_5_instance_options(MachineState *machine)
3316 {
3317 spapr_machine_2_6_instance_options(machine);
3318 }
3319
3320 static void spapr_machine_2_5_class_options(MachineClass *mc)
3321 {
3322 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3323
3324 spapr_machine_2_6_class_options(mc);
3325 smc->use_ohci_by_default = true;
3326 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3327 }
3328
3329 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3330
3331 /*
3332 * pseries-2.4
3333 */
3334 #define SPAPR_COMPAT_2_4 \
3335 HW_COMPAT_2_4
3336
3337 static void spapr_machine_2_4_instance_options(MachineState *machine)
3338 {
3339 spapr_machine_2_5_instance_options(machine);
3340 }
3341
3342 static void spapr_machine_2_4_class_options(MachineClass *mc)
3343 {
3344 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3345
3346 spapr_machine_2_5_class_options(mc);
3347 smc->dr_lmb_enabled = false;
3348 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3349 }
3350
3351 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3352
3353 /*
3354 * pseries-2.3
3355 */
3356 #define SPAPR_COMPAT_2_3 \
3357 HW_COMPAT_2_3 \
3358 {\
3359 .driver = "spapr-pci-host-bridge",\
3360 .property = "dynamic-reconfiguration",\
3361 .value = "off",\
3362 },
3363
3364 static void spapr_machine_2_3_instance_options(MachineState *machine)
3365 {
3366 spapr_machine_2_4_instance_options(machine);
3367 savevm_skip_section_footers();
3368 global_state_set_optional();
3369 savevm_skip_configuration();
3370 }
3371
3372 static void spapr_machine_2_3_class_options(MachineClass *mc)
3373 {
3374 spapr_machine_2_4_class_options(mc);
3375 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3376 }
3377 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3378
3379 /*
3380 * pseries-2.2
3381 */
3382
3383 #define SPAPR_COMPAT_2_2 \
3384 HW_COMPAT_2_2 \
3385 {\
3386 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3387 .property = "mem_win_size",\
3388 .value = "0x20000000",\
3389 },
3390
3391 static void spapr_machine_2_2_instance_options(MachineState *machine)
3392 {
3393 spapr_machine_2_3_instance_options(machine);
3394 machine->suppress_vmdesc = true;
3395 }
3396
3397 static void spapr_machine_2_2_class_options(MachineClass *mc)
3398 {
3399 spapr_machine_2_3_class_options(mc);
3400 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3401 }
3402 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3403
3404 /*
3405 * pseries-2.1
3406 */
3407 #define SPAPR_COMPAT_2_1 \
3408 HW_COMPAT_2_1
3409
3410 static void spapr_machine_2_1_instance_options(MachineState *machine)
3411 {
3412 spapr_machine_2_2_instance_options(machine);
3413 }
3414
3415 static void spapr_machine_2_1_class_options(MachineClass *mc)
3416 {
3417 spapr_machine_2_2_class_options(mc);
3418 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3419 }
3420 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3421
3422 static void spapr_machine_register_types(void)
3423 {
3424 type_register_static(&spapr_machine_info);
3425 }
3426
3427 type_init(spapr_machine_register_types)
AR7 emulation for QEMU