hw/arm/smmu-common.c

   1 /*
   2  * Copyright (C) 2014-2016 Broadcom Corporation
   3  * Copyright (c) 2017 Red Hat, Inc.
   4  * Written by Prem Mallappa, Eric Auger
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * Author: Prem Mallappa <pmallapp@broadcom.com>
  16  *
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "exec/address-spaces.h"
  21 #include "trace.h"
  22 #include "exec/target_page.h"
  23 #include "hw/core/cpu.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/error.h"
  26 #include "qemu/jhash.h"
  27 #include "qemu/module.h"
  28
  29 #include "qemu/error-report.h"
  30 #include "hw/arm/smmu-common.h"
  31 #include "smmu-internal.h"
  32
  33 /* IOTLB Management */
  34
  35 inline void smmu_iotlb_inv_all(SMMUState *s)
  36 {
  37     trace_smmu_iotlb_inv_all();
  38     g_hash_table_remove_all(s->iotlb);
  39 }
  40
  41 static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
  42                                          gpointer user_data)
  43 {
  44     uint16_t asid = *(uint16_t *)user_data;
  45     SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
  46
  47     return iotlb_key->asid == asid;
  48 }
  49
  50 inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova)
  51 {
  52     SMMUIOTLBKey key = {.asid = asid, .iova = iova};
  53
  54     trace_smmu_iotlb_inv_iova(asid, iova);
  55     g_hash_table_remove(s->iotlb, &key);
  56 }
  57
  58 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
  59 {
  60     trace_smmu_iotlb_inv_asid(asid);
  61     g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
  62 }
  63
  64 /* VMSAv8-64 Translation */
  65
  66 /**
  67  * get_pte - Get the content of a page table entry located at
  68  * @base_addr[@index]
  69  */
  70 static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
  71                    SMMUPTWEventInfo *info)
  72 {
  73     int ret;
  74     dma_addr_t addr = baseaddr + index * sizeof(*pte);
  75
  76     /* TODO: guarantee 64-bit single-copy atomicity */
  77     ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte));
  78
  79     if (ret != MEMTX_OK) {
  80         info->type = SMMU_PTW_ERR_WALK_EABT;
  81         info->addr = addr;
  82         return -EINVAL;
  83     }
  84     trace_smmu_get_pte(baseaddr, index, addr, *pte);
  85     return 0;
  86 }
  87
  88 /* VMSAv8-64 Translation Table Format Descriptor Decoding */
  89
  90 /**
  91  * get_page_pte_address - returns the L3 descriptor output address,
  92  * ie. the page frame
  93  * ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format
  94  */
  95 static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz)
  96 {
  97     return PTE_ADDRESS(pte, granule_sz);
  98 }
  99
 100 /**
 101  * get_table_pte_address - return table descriptor output address,
 102  * ie. address of next level table
 103  * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
 104  */
 105 static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)
 106 {
 107     return PTE_ADDRESS(pte, granule_sz);
 108 }
 109
 110 /**
 111  * get_block_pte_address - return block descriptor output address and block size
 112  * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
 113  */
 114 static inline hwaddr get_block_pte_address(uint64_t pte, int level,
 115                                            int granule_sz, uint64_t *bsz)
 116 {
 117     int n = level_shift(level, granule_sz);
 118
 119     *bsz = 1ULL << n;
 120     return PTE_ADDRESS(pte, n);
 121 }
 122
 123 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
 124 {
 125     bool tbi = extract64(iova, 55, 1) ? TBI1(cfg->tbi) : TBI0(cfg->tbi);
 126     uint8_t tbi_byte = tbi * 8;
 127
 128     if (cfg->tt[0].tsz &&
 129         !extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - tbi_byte)) {
 130         /* there is a ttbr0 region and we are in it (high bits all zero) */
 131         return &cfg->tt[0];
 132     } else if (cfg->tt[1].tsz &&
 133            !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
 134         /* there is a ttbr1 region and we are in it (high bits all one) */
 135         return &cfg->tt[1];
 136     } else if (!cfg->tt[0].tsz) {
 137         /* ttbr0 region is "everything not in the ttbr1 region" */
 138         return &cfg->tt[0];
 139     } else if (!cfg->tt[1].tsz) {
 140         /* ttbr1 region is "everything not in the ttbr0 region" */
 141         return &cfg->tt[1];
 142     }
 143     /* in the gap between the two regions, this is a Translation fault */
 144     return NULL;
 145 }
 146
 147 /**
 148  * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
 149  * @cfg: translation config
 150  * @iova: iova to translate
 151  * @perm: access type
 152  * @tlbe: IOMMUTLBEntry (out)
 153  * @info: handle to an error info
 154  *
 155  * Return 0 on success, < 0 on error. In case of error, @info is filled
 156  * and tlbe->perm is set to IOMMU_NONE.
 157  * Upon success, @tlbe is filled with translated_addr and entry
 158  * permission rights.
 159  */
 160 static int smmu_ptw_64(SMMUTransCfg *cfg,
 161                        dma_addr_t iova, IOMMUAccessFlags perm,
 162                        IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
 163 {
 164     dma_addr_t baseaddr, indexmask;
 165     int stage = cfg->stage;
 166     SMMUTransTableInfo *tt = select_tt(cfg, iova);
 167     uint8_t level, granule_sz, inputsize, stride;
 168
 169     if (!tt || tt->disabled) {
 170         info->type = SMMU_PTW_ERR_TRANSLATION;
 171         goto error;
 172     }
 173
 174     granule_sz = tt->granule_sz;
 175     stride = granule_sz - 3;
 176     inputsize = 64 - tt->tsz;
 177     level = 4 - (inputsize - 4) / stride;
 178     indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
 179     baseaddr = extract64(tt->ttb, 0, 48);
 180     baseaddr &= ~indexmask;
 181
 182     tlbe->iova = iova;
 183     tlbe->addr_mask = (1 << granule_sz) - 1;
 184
 185     while (level <= 3) {
 186         uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
 187         uint64_t mask = subpage_size - 1;
 188         uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
 189         uint64_t pte, gpa;
 190         dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
 191         uint8_t ap;
 192
 193         if (get_pte(baseaddr, offset, &pte, info)) {
 194                 goto error;
 195         }
 196         trace_smmu_ptw_level(level, iova, subpage_size,
 197                              baseaddr, offset, pte);
 198
 199         if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
 200             trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
 201                                        pte_addr, offset, pte);
 202             break;
 203         }
 204
 205         if (is_table_pte(pte, level)) {
 206             ap = PTE_APTABLE(pte);
 207
 208             if (is_permission_fault(ap, perm)) {
 209                 info->type = SMMU_PTW_ERR_PERMISSION;
 210                 goto error;
 211             }
 212             baseaddr = get_table_pte_address(pte, granule_sz);
 213             level++;
 214             continue;
 215         } else if (is_page_pte(pte, level)) {
 216             gpa = get_page_pte_address(pte, granule_sz);
 217             trace_smmu_ptw_page_pte(stage, level, iova,
 218                                     baseaddr, pte_addr, pte, gpa);
 219         } else {
 220             uint64_t block_size;
 221
 222             gpa = get_block_pte_address(pte, level, granule_sz,
 223                                         &block_size);
 224             trace_smmu_ptw_block_pte(stage, level, baseaddr,
 225                                      pte_addr, pte, iova, gpa,
 226                                      block_size >> 20);
 227         }
 228         ap = PTE_AP(pte);
 229         if (is_permission_fault(ap, perm)) {
 230             info->type = SMMU_PTW_ERR_PERMISSION;
 231             goto error;
 232         }
 233
 234         tlbe->translated_addr = gpa + (iova & mask);
 235         tlbe->perm = PTE_AP_TO_PERM(ap);
 236         return 0;
 237     }
 238     info->type = SMMU_PTW_ERR_TRANSLATION;
 239
 240 error:
 241     tlbe->perm = IOMMU_NONE;
 242     return -EINVAL;
 243 }
 244
 245 /**
 246  * smmu_ptw - Walk the page tables for an IOVA, according to @cfg
 247  *
 248  * @cfg: translation configuration
 249  * @iova: iova to translate
 250  * @perm: tentative access type
 251  * @tlbe: returned entry
 252  * @info: ptw event handle
 253  *
 254  * return 0 on success
 255  */
 256 inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
 257              IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
 258 {
 259     if (!cfg->aa64) {
 260         /*
 261          * This code path is not entered as we check this while decoding
 262          * the configuration data in the derived SMMU model.
 263          */
 264         g_assert_not_reached();
 265     }
 266
 267     return smmu_ptw_64(cfg, iova, perm, tlbe, info);
 268 }
 269
 270 /**
 271  * The bus number is used for lookup when SID based invalidation occurs.
 272  * In that case we lazily populate the SMMUPciBus array from the bus hash
 273  * table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus
 274  * numbers may not be always initialized yet.
 275  */
 276 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num)
 277 {
 278     SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num];
 279     GHashTableIter iter;
 280
 281     if (smmu_pci_bus) {
 282         return smmu_pci_bus;
 283     }
 284
 285     g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr);
 286     while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) {
 287         if (pci_bus_num(smmu_pci_bus->bus) == bus_num) {
 288             s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus;
 289             return smmu_pci_bus;
 290         }
 291     }
 292
 293     return NULL;
 294 }
 295
 296 static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
 297 {
 298     SMMUState *s = opaque;
 299     SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus);
 300     SMMUDevice *sdev;
 301     static unsigned int index;
 302
 303     if (!sbus) {
 304         sbus = g_malloc0(sizeof(SMMUPciBus) +
 305                          sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX);
 306         sbus->bus = bus;
 307         g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus);
 308     }
 309
 310     sdev = sbus->pbdev[devfn];
 311     if (!sdev) {
 312         char *name = g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index++);
 313
 314         sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1);
 315
 316         sdev->smmu = s;
 317         sdev->bus = bus;
 318         sdev->devfn = devfn;
 319
 320         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
 321                                  s->mrtypename,
 322                                  OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
 323         address_space_init(&sdev->as,
 324                            MEMORY_REGION(&sdev->iommu), name);
 325         trace_smmu_add_mr(name);
 326         g_free(name);
 327     }
 328
 329     return &sdev->as;
 330 }
 331
 332 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
 333 {
 334     uint8_t bus_n, devfn;
 335     SMMUPciBus *smmu_bus;
 336     SMMUDevice *smmu;
 337
 338     bus_n = PCI_BUS_NUM(sid);
 339     smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
 340     if (smmu_bus) {
 341         devfn = SMMU_PCI_DEVFN(sid);
 342         smmu = smmu_bus->pbdev[devfn];
 343         if (smmu) {
 344             return &smmu->iommu;
 345         }
 346     }
 347     return NULL;
 348 }
 349
 350 static guint smmu_iotlb_key_hash(gconstpointer v)
 351 {
 352     SMMUIOTLBKey *key = (SMMUIOTLBKey *)v;
 353     uint32_t a, b, c;
 354
 355     /* Jenkins hash */
 356     a = b = c = JHASH_INITVAL + sizeof(*key);
 357     a += key->asid;
 358     b += extract64(key->iova, 0, 32);
 359     c += extract64(key->iova, 32, 32);
 360
 361     __jhash_mix(a, b, c);
 362     __jhash_final(a, b, c);
 363
 364     return c;
 365 }
 366
 367 static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
 368 {
 369     const SMMUIOTLBKey *k1 = v1;
 370     const SMMUIOTLBKey *k2 = v2;
 371
 372     return (k1->asid == k2->asid) && (k1->iova == k2->iova);
 373 }
 374
 375 /* Unmap the whole notifier's range */
 376 static void smmu_unmap_notifier_range(IOMMUNotifier *n)
 377 {
 378     IOMMUTLBEntry entry;
 379
 380     entry.target_as = &address_space_memory;
 381     entry.iova = n->start;
 382     entry.perm = IOMMU_NONE;
 383     entry.addr_mask = n->end - n->start;
 384
 385     memory_region_notify_one(n, &entry);
 386 }
 387
 388 /* Unmap all notifiers attached to @mr */
 389 inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
 390 {
 391     IOMMUNotifier *n;
 392
 393     trace_smmu_inv_notifiers_mr(mr->parent_obj.name);
 394     IOMMU_NOTIFIER_FOREACH(n, mr) {
 395         smmu_unmap_notifier_range(n);
 396     }
 397 }
 398
 399 /* Unmap all notifiers of all mr's */
 400 void smmu_inv_notifiers_all(SMMUState *s)
 401 {
 402     SMMUDevice *sdev;
 403
 404     QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) {
 405         smmu_inv_notifiers_mr(&sdev->iommu);
 406     }
 407 }
 408
 409 static void smmu_base_realize(DeviceState *dev, Error **errp)
 410 {
 411     SMMUState *s = ARM_SMMU(dev);
 412     SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev);
 413     Error *local_err = NULL;
 414
 415     sbc->parent_realize(dev, &local_err);
 416     if (local_err) {
 417         error_propagate(errp, local_err);
 418         return;
 419     }
 420     s->configs = g_hash_table_new_full(NULL, NULL, NULL, g_free);
 421     s->iotlb = g_hash_table_new_full(smmu_iotlb_key_hash, smmu_iotlb_key_equal,
 422                                      g_free, g_free);
 423     s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
 424
 425     if (s->primary_bus) {
 426         pci_setup_iommu(s->primary_bus, smmu_find_add_as, s);
 427     } else {
 428         error_setg(errp, "SMMU is not attached to any PCI bus!");
 429     }
 430 }
 431
 432 static void smmu_base_reset(DeviceState *dev)
 433 {
 434     SMMUState *s = ARM_SMMU(dev);
 435
 436     g_hash_table_remove_all(s->configs);
 437     g_hash_table_remove_all(s->iotlb);
 438 }
 439
 440 static Property smmu_dev_properties[] = {
 441     DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0),
 442     DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, "PCI", PCIBus *),
 443     DEFINE_PROP_END_OF_LIST(),
 444 };
 445
 446 static void smmu_base_class_init(ObjectClass *klass, void *data)
 447 {
 448     DeviceClass *dc = DEVICE_CLASS(klass);
 449     SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
 450
 451     device_class_set_props(dc, smmu_dev_properties);
 452     device_class_set_parent_realize(dc, smmu_base_realize,
 453                                     &sbc->parent_realize);
 454     dc->reset = smmu_base_reset;
 455 }
 456
 457 static const TypeInfo smmu_base_info = {
 458     .name          = TYPE_ARM_SMMU,
 459     .parent        = TYPE_SYS_BUS_DEVICE,
 460     .instance_size = sizeof(SMMUState),
 461     .class_data    = NULL,
 462     .class_size    = sizeof(SMMUBaseClass),
 463     .class_init    = smmu_base_class_init,
 464     .abstract      = true,
 465 };
 466
 467 static void smmu_base_register_types(void)
 468 {
 469     type_register_static(&smmu_base_info);
 470 }
 471
 472 type_init(smmu_base_register_types)
 473