target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
  42                       __func__, exception, error_code);
  43     }
  44     cs->exception_index = exception;
  45     env->error_code = error_code;
  46
  47     if (pc) {
  48         /* now we have a real cpu fault */
  49         cpu_restore_state(cs, pc);
  50     }
  51
  52     cpu_loop_exit(cs);
  53 }
  54
  55 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  56                                                     uint32_t exception,
  57                                                     uintptr_t pc)
  58 {
  59     do_raise_exception_err(env, exception, 0, pc);
  60 }
  61
  62 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  63                                 int error_code)
  64 {
  65     do_raise_exception_err(env, exception, error_code, 0);
  66 }
  67
  68 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  69 {
  70     do_raise_exception(env, exception, 0);
  71 }
  72
  73 #if defined(CONFIG_USER_ONLY)
  74 #define HELPER_LD(name, insn, type)                                     \
  75 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  76                              int mem_idx)                               \
  77 {                                                                       \
  78     return (type) cpu_##insn##_data(env, addr);                         \
  79 }
  80 #else
  81 #define HELPER_LD(name, insn, type)                                     \
  82 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  83                              int mem_idx)                               \
  84 {                                                                       \
  85     switch (mem_idx)                                                    \
  86     {                                                                   \
  87     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  88     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  89     default:                                                            \
  90     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  91     }                                                                   \
  92 }
  93 #endif
  94 HELPER_LD(lw, ldl, int32_t)
  95 #if defined(TARGET_MIPS64)
  96 HELPER_LD(ld, ldq, int64_t)
  97 #endif
  98 #undef HELPER_LD
  99
 100 #if defined(CONFIG_USER_ONLY)
 101 #define HELPER_ST(name, insn, type)                                     \
 102 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 103                              type val, int mem_idx)                     \
 104 {                                                                       \
 105     cpu_##insn##_data(env, addr, val);                                  \
 106 }
 107 #else
 108 #define HELPER_ST(name, insn, type)                                     \
 109 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 110                              type val, int mem_idx)                     \
 111 {                                                                       \
 112     switch (mem_idx)                                                    \
 113     {                                                                   \
 114     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 115     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 116     default:                                                            \
 117     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 118     }                                                                   \
 119 }
 120 #endif
 121 HELPER_ST(sb, stb, uint8_t)
 122 HELPER_ST(sw, stl, uint32_t)
 123 #if defined(TARGET_MIPS64)
 124 HELPER_ST(sd, stq, uint64_t)
 125 #endif
 126 #undef HELPER_ST
 127
 128 target_ulong helper_clo (target_ulong arg1)
 129 {
 130     return clo32(arg1);
 131 }
 132
 133 target_ulong helper_clz (target_ulong arg1)
 134 {
 135     return clz32(arg1);
 136 }
 137
 138 #if defined(TARGET_MIPS64)
 139 target_ulong helper_dclo (target_ulong arg1)
 140 {
 141     return clo64(arg1);
 142 }
 143
 144 target_ulong helper_dclz (target_ulong arg1)
 145 {
 146     return clz64(arg1);
 147 }
 148 #endif /* TARGET_MIPS64 */
 149
 150 /* 64 bits arithmetic for 32 bits hosts */
 151 static inline uint64_t get_HILO(CPUMIPSState *env)
 152 {
 153     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 154 }
 155
 156 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 157 {
 158     target_ulong tmp;
 159     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 160     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 161     return tmp;
 162 }
 163
 164 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 165 {
 166     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 167     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 168     return tmp;
 169 }
 170
 171 /* Multiplication variants of the vr54xx. */
 172 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 173                          target_ulong arg2)
 174 {
 175     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 176                                  (int64_t)(int32_t)arg2));
 177 }
 178
 179 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 180                           target_ulong arg2)
 181 {
 182     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 183                        (uint64_t)(uint32_t)arg2);
 184 }
 185
 186 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 187                          target_ulong arg2)
 188 {
 189     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 190                        (int64_t)(int32_t)arg2);
 191 }
 192
 193 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 194                            target_ulong arg2)
 195 {
 196     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 197                        (int64_t)(int32_t)arg2);
 198 }
 199
 200 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 201                           target_ulong arg2)
 202 {
 203     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 204                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 205 }
 206
 207 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 208                             target_ulong arg2)
 209 {
 210     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 211                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 212 }
 213
 214 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 215                          target_ulong arg2)
 216 {
 217     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 218                        (int64_t)(int32_t)arg2);
 219 }
 220
 221 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 222                            target_ulong arg2)
 223 {
 224     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 225                        (int64_t)(int32_t)arg2);
 226 }
 227
 228 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 229                           target_ulong arg2)
 230 {
 231     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 232                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 233 }
 234
 235 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 236                             target_ulong arg2)
 237 {
 238     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 239                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 240 }
 241
 242 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 243                           target_ulong arg2)
 244 {
 245     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 246 }
 247
 248 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 249                            target_ulong arg2)
 250 {
 251     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 252                        (uint64_t)(uint32_t)arg2);
 253 }
 254
 255 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 256                            target_ulong arg2)
 257 {
 258     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 259                        (int64_t)(int32_t)arg2);
 260 }
 261
 262 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 263                             target_ulong arg2)
 264 {
 265     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 266                        (uint64_t)(uint32_t)arg2);
 267 }
 268
 269 static inline target_ulong bitswap(target_ulong v)
 270 {
 271     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 272               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 273     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 274               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 275     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 276               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 277     return v;
 278 }
 279
 280 #ifdef TARGET_MIPS64
 281 target_ulong helper_dbitswap(target_ulong rt)
 282 {
 283     return bitswap(rt);
 284 }
 285 #endif
 286
 287 target_ulong helper_bitswap(target_ulong rt)
 288 {
 289     return (int32_t)bitswap(rt);
 290 }
 291
 292 #ifndef CONFIG_USER_ONLY
 293
 294 static inline hwaddr do_translate_address(CPUMIPSState *env,
 295                                                       target_ulong address,
 296                                                       int rw)
 297 {
 298     hwaddr lladdr;
 299
 300     lladdr = cpu_mips_translate_address(env, address, rw);
 301
 302     if (lladdr == -1LL) {
 303         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 304     } else {
 305         return lladdr;
 306     }
 307 }
 308
 309 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 310 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 311 {                                                                             \
 312     if (arg & almask) {                                                       \
 313         env->CP0_BadVAddr = arg;                                              \
 314         helper_raise_exception(env, EXCP_AdEL);                               \
 315     }                                                                         \
 316     env->lladdr = do_translate_address(env, arg, 0);                          \
 317     env->llval = do_##insn(env, arg, mem_idx);                                \
 318     return env->llval;                                                        \
 319 }
 320 HELPER_LD_ATOMIC(ll, lw, 0x3)
 321 #ifdef TARGET_MIPS64
 322 HELPER_LD_ATOMIC(lld, ld, 0x7)
 323 #endif
 324 #undef HELPER_LD_ATOMIC
 325
 326 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 327 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 328                            target_ulong arg2, int mem_idx)                    \
 329 {                                                                             \
 330     target_long tmp;                                                          \
 331                                                                               \
 332     if (arg2 & almask) {                                                      \
 333         env->CP0_BadVAddr = arg2;                                             \
 334         helper_raise_exception(env, EXCP_AdES);                               \
 335     }                                                                         \
 336     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 337         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 338         if (tmp == env->llval) {                                              \
 339             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 340             return 1;                                                         \
 341         }                                                                     \
 342     }                                                                         \
 343     return 0;                                                                 \
 344 }
 345 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 346 #ifdef TARGET_MIPS64
 347 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 348 #endif
 349 #undef HELPER_ST_ATOMIC
 350 #endif
 351
 352 #ifdef TARGET_WORDS_BIGENDIAN
 353 #define GET_LMASK(v) ((v) & 3)
 354 #define GET_OFFSET(addr, offset) (addr + (offset))
 355 #else
 356 #define GET_LMASK(v) (((v) & 3) ^ 3)
 357 #define GET_OFFSET(addr, offset) (addr - (offset))
 358 #endif
 359
 360 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 361                 int mem_idx)
 362 {
 363     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 364
 365     if (GET_LMASK(arg2) <= 2)
 366         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 367
 368     if (GET_LMASK(arg2) <= 1)
 369         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 370
 371     if (GET_LMASK(arg2) == 0)
 372         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 373 }
 374
 375 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 376                 int mem_idx)
 377 {
 378     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 379
 380     if (GET_LMASK(arg2) >= 1)
 381         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 382
 383     if (GET_LMASK(arg2) >= 2)
 384         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 385
 386     if (GET_LMASK(arg2) == 3)
 387         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 388 }
 389
 390 #if defined(TARGET_MIPS64)
 391 /* "half" load and stores.  We must do the memory access inline,
 392    or fault handling won't work.  */
 393
 394 #ifdef TARGET_WORDS_BIGENDIAN
 395 #define GET_LMASK64(v) ((v) & 7)
 396 #else
 397 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 398 #endif
 399
 400 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 401                 int mem_idx)
 402 {
 403     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 404
 405     if (GET_LMASK64(arg2) <= 6)
 406         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 407
 408     if (GET_LMASK64(arg2) <= 5)
 409         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 410
 411     if (GET_LMASK64(arg2) <= 4)
 412         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 413
 414     if (GET_LMASK64(arg2) <= 3)
 415         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 416
 417     if (GET_LMASK64(arg2) <= 2)
 418         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 419
 420     if (GET_LMASK64(arg2) <= 1)
 421         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 422
 423     if (GET_LMASK64(arg2) <= 0)
 424         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 425 }
 426
 427 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 428                 int mem_idx)
 429 {
 430     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 431
 432     if (GET_LMASK64(arg2) >= 1)
 433         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 434
 435     if (GET_LMASK64(arg2) >= 2)
 436         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 437
 438     if (GET_LMASK64(arg2) >= 3)
 439         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 440
 441     if (GET_LMASK64(arg2) >= 4)
 442         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 443
 444     if (GET_LMASK64(arg2) >= 5)
 445         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 446
 447     if (GET_LMASK64(arg2) >= 6)
 448         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 449
 450     if (GET_LMASK64(arg2) == 7)
 451         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 452 }
 453 #endif /* TARGET_MIPS64 */
 454
 455 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 456
 457 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 458                 uint32_t mem_idx)
 459 {
 460     target_ulong base_reglist = reglist & 0xf;
 461     target_ulong do_r31 = reglist & 0x10;
 462
 463     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 464         target_ulong i;
 465
 466         for (i = 0; i < base_reglist; i++) {
 467             env->active_tc.gpr[multiple_regs[i]] =
 468                 (target_long)do_lw(env, addr, mem_idx);
 469             addr += 4;
 470         }
 471     }
 472
 473     if (do_r31) {
 474         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 475     }
 476 }
 477
 478 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 479                 uint32_t mem_idx)
 480 {
 481     target_ulong base_reglist = reglist & 0xf;
 482     target_ulong do_r31 = reglist & 0x10;
 483
 484     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 485         target_ulong i;
 486
 487         for (i = 0; i < base_reglist; i++) {
 488             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 489             addr += 4;
 490         }
 491     }
 492
 493     if (do_r31) {
 494         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 495     }
 496 }
 497
 498 #if defined(TARGET_MIPS64)
 499 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 500                 uint32_t mem_idx)
 501 {
 502     target_ulong base_reglist = reglist & 0xf;
 503     target_ulong do_r31 = reglist & 0x10;
 504
 505     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 506         target_ulong i;
 507
 508         for (i = 0; i < base_reglist; i++) {
 509             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 510             addr += 8;
 511         }
 512     }
 513
 514     if (do_r31) {
 515         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 516     }
 517 }
 518
 519 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 520                 uint32_t mem_idx)
 521 {
 522     target_ulong base_reglist = reglist & 0xf;
 523     target_ulong do_r31 = reglist & 0x10;
 524
 525     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 526         target_ulong i;
 527
 528         for (i = 0; i < base_reglist; i++) {
 529             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 530             addr += 8;
 531         }
 532     }
 533
 534     if (do_r31) {
 535         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 536     }
 537 }
 538 #endif
 539
 540 #ifndef CONFIG_USER_ONLY
 541 /* SMP helpers.  */
 542 static bool mips_vpe_is_wfi(MIPSCPU *c)
 543 {
 544     CPUState *cpu = CPU(c);
 545     CPUMIPSState *env = &c->env;
 546
 547     /* If the VPE is halted but otherwise active, it means it's waiting for
 548        an interrupt.  */
 549     return cpu->halted && mips_vpe_active(env);
 550 }
 551
 552 static inline void mips_vpe_wake(MIPSCPU *c)
 553 {
 554     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 555        because there might be other conditions that state that c should
 556        be sleeping.  */
 557     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 558 }
 559
 560 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 561 {
 562     CPUState *cs = CPU(cpu);
 563
 564     /* The VPE was shut off, really go to bed.
 565        Reset any old _WAKE requests.  */
 566     cs->halted = 1;
 567     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 568 }
 569
 570 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 571 {
 572     CPUMIPSState *c = &cpu->env;
 573
 574     /* FIXME: TC reschedule.  */
 575     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 576         mips_vpe_wake(cpu);
 577     }
 578 }
 579
 580 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 581 {
 582     CPUMIPSState *c = &cpu->env;
 583
 584     /* FIXME: TC reschedule.  */
 585     if (!mips_vpe_active(c)) {
 586         mips_vpe_sleep(cpu);
 587     }
 588 }
 589
 590 /**
 591  * mips_cpu_map_tc:
 592  * @env: CPU from which mapping is performed.
 593  * @tc: Should point to an int with the value of the global TC index.
 594  *
 595  * This function will transform @tc into a local index within the
 596  * returned #CPUMIPSState.
 597  */
 598 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 599           which depends on runtime setup. Can probably be fixed by
 600           walking the list of CPUMIPSStates.  */
 601 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 602 {
 603     MIPSCPU *cpu;
 604     CPUState *cs;
 605     CPUState *other_cs;
 606     int vpe_idx;
 607     int tc_idx = *tc;
 608
 609     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 610         /* Not allowed to address other CPUs.  */
 611         *tc = env->current_tc;
 612         return env;
 613     }
 614
 615     cs = CPU(mips_env_get_cpu(env));
 616     vpe_idx = tc_idx / cs->nr_threads;
 617     *tc = tc_idx % cs->nr_threads;
 618     other_cs = qemu_get_cpu(vpe_idx);
 619     if (other_cs == NULL) {
 620         return env;
 621     }
 622     cpu = MIPS_CPU(other_cs);
 623     return &cpu->env;
 624 }
 625
 626 /* The per VPE CP0_Status register shares some fields with the per TC
 627    CP0_TCStatus registers. These fields are wired to the same registers,
 628    so changes to either of them should be reflected on both registers.
 629
 630    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 631
 632    These helper call synchronizes the regs for a given cpu.  */
 633
 634 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 635 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 636                                      int tc);  */
 637
 638 /* Called for updates to CP0_TCStatus.  */
 639 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 640                              target_ulong v)
 641 {
 642     uint32_t status;
 643     uint32_t tcu, tmx, tasid, tksu;
 644     uint32_t mask = ((1U << CP0St_CU3)
 645                        | (1 << CP0St_CU2)
 646                        | (1 << CP0St_CU1)
 647                        | (1 << CP0St_CU0)
 648                        | (1 << CP0St_MX)
 649                        | (3 << CP0St_KSU));
 650
 651     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 652     tmx = (v >> CP0TCSt_TMX) & 0x1;
 653     tasid = v & 0xff;
 654     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 655
 656     status = tcu << CP0St_CU0;
 657     status |= tmx << CP0St_MX;
 658     status |= tksu << CP0St_KSU;
 659
 660     cpu->CP0_Status &= ~mask;
 661     cpu->CP0_Status |= status;
 662
 663     /* Sync the TASID with EntryHi.  */
 664     cpu->CP0_EntryHi &= ~0xff;
 665     cpu->CP0_EntryHi |= tasid;
 666
 667     compute_hflags(cpu);
 668 }
 669
 670 /* Called for updates to CP0_EntryHi.  */
 671 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 672 {
 673     int32_t *tcst;
 674     uint32_t asid, v = cpu->CP0_EntryHi;
 675
 676     asid = v & 0xff;
 677
 678     if (tc == cpu->current_tc) {
 679         tcst = &cpu->active_tc.CP0_TCStatus;
 680     } else {
 681         tcst = &cpu->tcs[tc].CP0_TCStatus;
 682     }
 683
 684     *tcst &= ~0xff;
 685     *tcst |= asid;
 686 }
 687
 688 /* CP0 helpers */
 689 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 690 {
 691     return env->mvp->CP0_MVPControl;
 692 }
 693
 694 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 695 {
 696     return env->mvp->CP0_MVPConf0;
 697 }
 698
 699 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 700 {
 701     return env->mvp->CP0_MVPConf1;
 702 }
 703
 704 target_ulong helper_mfc0_random(CPUMIPSState *env)
 705 {
 706     return (int32_t)cpu_mips_get_random(env);
 707 }
 708
 709 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 710 {
 711     return env->active_tc.CP0_TCStatus;
 712 }
 713
 714 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 715 {
 716     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 717     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 718
 719     if (other_tc == other->current_tc)
 720         return other->active_tc.CP0_TCStatus;
 721     else
 722         return other->tcs[other_tc].CP0_TCStatus;
 723 }
 724
 725 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 726 {
 727     return env->active_tc.CP0_TCBind;
 728 }
 729
 730 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 731 {
 732     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 733     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 734
 735     if (other_tc == other->current_tc)
 736         return other->active_tc.CP0_TCBind;
 737     else
 738         return other->tcs[other_tc].CP0_TCBind;
 739 }
 740
 741 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 742 {
 743     return env->active_tc.PC;
 744 }
 745
 746 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 747 {
 748     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 749     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 750
 751     if (other_tc == other->current_tc)
 752         return other->active_tc.PC;
 753     else
 754         return other->tcs[other_tc].PC;
 755 }
 756
 757 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 758 {
 759     return env->active_tc.CP0_TCHalt;
 760 }
 761
 762 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 763 {
 764     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 765     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 766
 767     if (other_tc == other->current_tc)
 768         return other->active_tc.CP0_TCHalt;
 769     else
 770         return other->tcs[other_tc].CP0_TCHalt;
 771 }
 772
 773 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 774 {
 775     return env->active_tc.CP0_TCContext;
 776 }
 777
 778 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 779 {
 780     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 781     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 782
 783     if (other_tc == other->current_tc)
 784         return other->active_tc.CP0_TCContext;
 785     else
 786         return other->tcs[other_tc].CP0_TCContext;
 787 }
 788
 789 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 790 {
 791     return env->active_tc.CP0_TCSchedule;
 792 }
 793
 794 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 795 {
 796     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 797     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 798
 799     if (other_tc == other->current_tc)
 800         return other->active_tc.CP0_TCSchedule;
 801     else
 802         return other->tcs[other_tc].CP0_TCSchedule;
 803 }
 804
 805 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 806 {
 807     return env->active_tc.CP0_TCScheFBack;
 808 }
 809
 810 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 811 {
 812     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 813     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 814
 815     if (other_tc == other->current_tc)
 816         return other->active_tc.CP0_TCScheFBack;
 817     else
 818         return other->tcs[other_tc].CP0_TCScheFBack;
 819 }
 820
 821 target_ulong helper_mfc0_count(CPUMIPSState *env)
 822 {
 823     return (int32_t)cpu_mips_get_count(env);
 824 }
 825
 826 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 827 {
 828     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 829     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 830
 831     return other->CP0_EntryHi;
 832 }
 833
 834 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 835 {
 836     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 837     int32_t tccause;
 838     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 839
 840     if (other_tc == other->current_tc) {
 841         tccause = other->CP0_Cause;
 842     } else {
 843         tccause = other->CP0_Cause;
 844     }
 845
 846     return tccause;
 847 }
 848
 849 target_ulong helper_mftc0_status(CPUMIPSState *env)
 850 {
 851     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 852     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 853
 854     return other->CP0_Status;
 855 }
 856
 857 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 858 {
 859     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 860 }
 861
 862 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 863 {
 864     return (int32_t)env->CP0_WatchLo[sel];
 865 }
 866
 867 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 868 {
 869     return env->CP0_WatchHi[sel];
 870 }
 871
 872 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 873 {
 874     target_ulong t0 = env->CP0_Debug;
 875     if (env->hflags & MIPS_HFLAG_DM)
 876         t0 |= 1 << CP0DB_DM;
 877
 878     return t0;
 879 }
 880
 881 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 882 {
 883     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 884     int32_t tcstatus;
 885     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 886
 887     if (other_tc == other->current_tc)
 888         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 889     else
 890         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 891
 892     /* XXX: Might be wrong, check with EJTAG spec. */
 893     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 894             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 895 }
 896
 897 #if defined(TARGET_MIPS64)
 898 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 899 {
 900     return env->active_tc.PC;
 901 }
 902
 903 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 904 {
 905     return env->active_tc.CP0_TCHalt;
 906 }
 907
 908 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 909 {
 910     return env->active_tc.CP0_TCContext;
 911 }
 912
 913 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 914 {
 915     return env->active_tc.CP0_TCSchedule;
 916 }
 917
 918 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 919 {
 920     return env->active_tc.CP0_TCScheFBack;
 921 }
 922
 923 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 924 {
 925     return env->lladdr >> env->CP0_LLAddr_shift;
 926 }
 927
 928 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 929 {
 930     return env->CP0_WatchLo[sel];
 931 }
 932 #endif /* TARGET_MIPS64 */
 933
 934 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 935 {
 936     uint32_t index_p = env->CP0_Index & 0x80000000;
 937     uint32_t tlb_index = arg1 & 0x7fffffff;
 938     if (tlb_index < env->tlb->nb_tlb) {
 939         if (env->insn_flags & ISA_MIPS32R6) {
 940             index_p |= arg1 & 0x80000000;
 941         }
 942         env->CP0_Index = index_p | tlb_index;
 943     }
 944 }
 945
 946 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 947 {
 948     uint32_t mask = 0;
 949     uint32_t newval;
 950
 951     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 952         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 953                 (1 << CP0MVPCo_EVP);
 954     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 955         mask |= (1 << CP0MVPCo_STLB);
 956     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 957
 958     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 959
 960     env->mvp->CP0_MVPControl = newval;
 961 }
 962
 963 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 964 {
 965     uint32_t mask;
 966     uint32_t newval;
 967
 968     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 969            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 970     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 971
 972     /* Yield scheduler intercept not implemented. */
 973     /* Gating storage scheduler intercept not implemented. */
 974
 975     // TODO: Enable/disable TCs.
 976
 977     env->CP0_VPEControl = newval;
 978 }
 979
 980 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 981 {
 982     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 983     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 984     uint32_t mask;
 985     uint32_t newval;
 986
 987     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 988            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 989     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 990
 991     /* TODO: Enable/disable TCs.  */
 992
 993     other->CP0_VPEControl = newval;
 994 }
 995
 996 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 997 {
 998     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 999     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1000     /* FIXME: Mask away return zero on read bits.  */
1001     return other->CP0_VPEControl;
1002 }
1003
1004 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1005 {
1006     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1007     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1008
1009     return other->CP0_VPEConf0;
1010 }
1011
1012 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1013 {
1014     uint32_t mask = 0;
1015     uint32_t newval;
1016
1017     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1018         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1019             mask |= (0xff << CP0VPEC0_XTC);
1020         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1021     }
1022     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1023
1024     // TODO: TC exclusive handling due to ERL/EXL.
1025
1026     env->CP0_VPEConf0 = newval;
1027 }
1028
1029 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1030 {
1031     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1032     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1033     uint32_t mask = 0;
1034     uint32_t newval;
1035
1036     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1037     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1038
1039     /* TODO: TC exclusive handling due to ERL/EXL.  */
1040     other->CP0_VPEConf0 = newval;
1041 }
1042
1043 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1044 {
1045     uint32_t mask = 0;
1046     uint32_t newval;
1047
1048     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1049         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1050                 (0xff << CP0VPEC1_NCP1);
1051     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1052
1053     /* UDI not implemented. */
1054     /* CP2 not implemented. */
1055
1056     // TODO: Handle FPU (CP1) binding.
1057
1058     env->CP0_VPEConf1 = newval;
1059 }
1060
1061 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1062 {
1063     /* Yield qualifier inputs not implemented. */
1064     env->CP0_YQMask = 0x00000000;
1065 }
1066
1067 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1068 {
1069     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1070 }
1071
1072 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1073
1074 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1075 {
1076     /* 1k pages not implemented */
1077     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1078     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1079                         | (rxi << (CP0EnLo_XI - 30));
1080 }
1081
1082 #if defined(TARGET_MIPS64)
1083 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1084
1085 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1086 {
1087     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1088     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1089 }
1090 #endif
1091
1092 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1093 {
1094     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1095     uint32_t newval;
1096
1097     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1098
1099     env->active_tc.CP0_TCStatus = newval;
1100     sync_c0_tcstatus(env, env->current_tc, newval);
1101 }
1102
1103 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1104 {
1105     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1106     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1107
1108     if (other_tc == other->current_tc)
1109         other->active_tc.CP0_TCStatus = arg1;
1110     else
1111         other->tcs[other_tc].CP0_TCStatus = arg1;
1112     sync_c0_tcstatus(other, other_tc, arg1);
1113 }
1114
1115 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1116 {
1117     uint32_t mask = (1 << CP0TCBd_TBE);
1118     uint32_t newval;
1119
1120     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1121         mask |= (1 << CP0TCBd_CurVPE);
1122     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1123     env->active_tc.CP0_TCBind = newval;
1124 }
1125
1126 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1127 {
1128     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1129     uint32_t mask = (1 << CP0TCBd_TBE);
1130     uint32_t newval;
1131     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1132
1133     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1134         mask |= (1 << CP0TCBd_CurVPE);
1135     if (other_tc == other->current_tc) {
1136         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1137         other->active_tc.CP0_TCBind = newval;
1138     } else {
1139         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1140         other->tcs[other_tc].CP0_TCBind = newval;
1141     }
1142 }
1143
1144 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1145 {
1146     env->active_tc.PC = arg1;
1147     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1148     env->lladdr = 0ULL;
1149     /* MIPS16 not implemented. */
1150 }
1151
1152 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1153 {
1154     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1155     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1156
1157     if (other_tc == other->current_tc) {
1158         other->active_tc.PC = arg1;
1159         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1160         other->lladdr = 0ULL;
1161         /* MIPS16 not implemented. */
1162     } else {
1163         other->tcs[other_tc].PC = arg1;
1164         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1165         other->lladdr = 0ULL;
1166         /* MIPS16 not implemented. */
1167     }
1168 }
1169
1170 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1171 {
1172     MIPSCPU *cpu = mips_env_get_cpu(env);
1173
1174     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1175
1176     // TODO: Halt TC / Restart (if allocated+active) TC.
1177     if (env->active_tc.CP0_TCHalt & 1) {
1178         mips_tc_sleep(cpu, env->current_tc);
1179     } else {
1180         mips_tc_wake(cpu, env->current_tc);
1181     }
1182 }
1183
1184 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1185 {
1186     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1187     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1188     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1189
1190     // TODO: Halt TC / Restart (if allocated+active) TC.
1191
1192     if (other_tc == other->current_tc)
1193         other->active_tc.CP0_TCHalt = arg1;
1194     else
1195         other->tcs[other_tc].CP0_TCHalt = arg1;
1196
1197     if (arg1 & 1) {
1198         mips_tc_sleep(other_cpu, other_tc);
1199     } else {
1200         mips_tc_wake(other_cpu, other_tc);
1201     }
1202 }
1203
1204 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1205 {
1206     env->active_tc.CP0_TCContext = arg1;
1207 }
1208
1209 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1210 {
1211     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1212     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1213
1214     if (other_tc == other->current_tc)
1215         other->active_tc.CP0_TCContext = arg1;
1216     else
1217         other->tcs[other_tc].CP0_TCContext = arg1;
1218 }
1219
1220 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1221 {
1222     env->active_tc.CP0_TCSchedule = arg1;
1223 }
1224
1225 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1226 {
1227     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1228     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1229
1230     if (other_tc == other->current_tc)
1231         other->active_tc.CP0_TCSchedule = arg1;
1232     else
1233         other->tcs[other_tc].CP0_TCSchedule = arg1;
1234 }
1235
1236 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1237 {
1238     env->active_tc.CP0_TCScheFBack = arg1;
1239 }
1240
1241 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1242 {
1243     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1244     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1245
1246     if (other_tc == other->current_tc)
1247         other->active_tc.CP0_TCScheFBack = arg1;
1248     else
1249         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1250 }
1251
1252 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1253 {
1254     /* 1k pages not implemented */
1255     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1256     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1257                         | (rxi << (CP0EnLo_XI - 30));
1258 }
1259
1260 #if defined(TARGET_MIPS64)
1261 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1262 {
1263     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1264     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1265 }
1266 #endif
1267
1268 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1269 {
1270     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1271 }
1272
1273 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1274 {
1275     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1276     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1277         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1278          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1279          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1280         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1281     }
1282 }
1283
1284 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1285 {
1286     /* SmartMIPS not implemented */
1287     /* 1k pages not implemented */
1288     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1289                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1290     compute_hflags(env);
1291     restore_pamask(env);
1292 }
1293
1294 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1295 {
1296     if (env->insn_flags & ISA_MIPS32R6) {
1297         if (arg1 < env->tlb->nb_tlb) {
1298             env->CP0_Wired = arg1;
1299         }
1300     } else {
1301         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1302     }
1303 }
1304
1305 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1306 {
1307     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1308 }
1309
1310 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1311 {
1312     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1313 }
1314
1315 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1316 {
1317     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1318 }
1319
1320 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1321 {
1322     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1323 }
1324
1325 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1326 {
1327     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1328 }
1329
1330 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1331 {
1332     uint32_t mask = 0x0000000F;
1333
1334     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1335         mask |= (1 << 29);
1336
1337         if (arg1 & (1 << 29)) {
1338             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1339         } else {
1340             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1341         }
1342     }
1343
1344     env->CP0_HWREna = arg1 & mask;
1345 }
1346
1347 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1348 {
1349     cpu_mips_store_count(env, arg1);
1350 }
1351
1352 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1353 {
1354     target_ulong old, val, mask;
1355     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1356     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1357         mask |= 1 << CP0EnHi_EHINV;
1358     }
1359
1360     /* 1k pages not implemented */
1361 #if defined(TARGET_MIPS64)
1362     if (env->insn_flags & ISA_MIPS32R6) {
1363         int entryhi_r = extract64(arg1, 62, 2);
1364         int config0_at = extract32(env->CP0_Config0, 13, 2);
1365         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1366         if ((entryhi_r == 2) ||
1367             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1368             /* skip EntryHi.R field if new value is reserved */
1369             mask &= ~(0x3ull << 62);
1370         }
1371     }
1372     mask &= env->SEGMask;
1373 #endif
1374     old = env->CP0_EntryHi;
1375     val = (arg1 & mask) | (old & ~mask);
1376     env->CP0_EntryHi = val;
1377     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1378         sync_c0_entryhi(env, env->current_tc);
1379     }
1380     /* If the ASID changes, flush qemu's TLB.  */
1381     if ((old & 0xFF) != (val & 0xFF))
1382         cpu_mips_tlb_flush(env, 1);
1383 }
1384
1385 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1386 {
1387     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1388     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1389
1390     other->CP0_EntryHi = arg1;
1391     sync_c0_entryhi(other, other_tc);
1392 }
1393
1394 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1395 {
1396     cpu_mips_store_compare(env, arg1);
1397 }
1398
1399 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1400 {
1401     MIPSCPU *cpu = mips_env_get_cpu(env);
1402     uint32_t val, old;
1403
1404     old = env->CP0_Status;
1405     cpu_mips_store_status(env, arg1);
1406     val = env->CP0_Status;
1407
1408     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1409         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1410                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1411                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1412                 env->CP0_Cause);
1413         switch (env->hflags & MIPS_HFLAG_KSU) {
1414         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1415         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1416         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1417         default:
1418             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1419             break;
1420         }
1421     }
1422 }
1423
1424 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1425 {
1426     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1427     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1428     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1429
1430     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1431     sync_c0_status(env, other, other_tc);
1432 }
1433
1434 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1435 {
1436     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1437 }
1438
1439 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1440 {
1441     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1442     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1443 }
1444
1445 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1446 {
1447     cpu_mips_store_cause(env, arg1);
1448 }
1449
1450 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1451 {
1452     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1453     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1454
1455     cpu_mips_store_cause(other, arg1);
1456 }
1457
1458 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1459 {
1460     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1461     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1462
1463     return other->CP0_EPC;
1464 }
1465
1466 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1467 {
1468     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1469     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1470
1471     return other->CP0_EBase;
1472 }
1473
1474 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1475 {
1476     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1477 }
1478
1479 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1480 {
1481     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1482     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1483     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1484 }
1485
1486 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1487 {
1488     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1489     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1490
1491     switch (idx) {
1492     case 0: return other->CP0_Config0;
1493     case 1: return other->CP0_Config1;
1494     case 2: return other->CP0_Config2;
1495     case 3: return other->CP0_Config3;
1496     /* 4 and 5 are reserved.  */
1497     case 6: return other->CP0_Config6;
1498     case 7: return other->CP0_Config7;
1499     default:
1500         break;
1501     }
1502     return 0;
1503 }
1504
1505 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1506 {
1507     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1508 }
1509
1510 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1511 {
1512     /* tertiary/secondary caches not implemented */
1513     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1514 }
1515
1516 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1517 {
1518     if (env->insn_flags & ASE_MICROMIPS) {
1519         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1520                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1521     }
1522 }
1523
1524 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1525 {
1526     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1527                        (arg1 & env->CP0_Config4_rw_bitmask);
1528 }
1529
1530 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1531 {
1532     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1533                        (arg1 & env->CP0_Config5_rw_bitmask);
1534     compute_hflags(env);
1535 }
1536
1537 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1538 {
1539     target_long mask = env->CP0_LLAddr_rw_bitmask;
1540     arg1 = arg1 << env->CP0_LLAddr_shift;
1541     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1542 }
1543
1544 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1545 {
1546     /* Watch exceptions for instructions, data loads, data stores
1547        not implemented. */
1548     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1549 }
1550
1551 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1552 {
1553     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1554     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1555 }
1556
1557 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1558 {
1559     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1560     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1561 }
1562
1563 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1564 {
1565     env->CP0_Framemask = arg1; /* XXX */
1566 }
1567
1568 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1569 {
1570     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1571     if (arg1 & (1 << CP0DB_DM))
1572         env->hflags |= MIPS_HFLAG_DM;
1573     else
1574         env->hflags &= ~MIPS_HFLAG_DM;
1575 }
1576
1577 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1578 {
1579     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1580     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1581     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1582
1583     /* XXX: Might be wrong, check with EJTAG spec. */
1584     if (other_tc == other->current_tc)
1585         other->active_tc.CP0_Debug_tcstatus = val;
1586     else
1587         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1588     other->CP0_Debug = (other->CP0_Debug &
1589                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1590                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1591 }
1592
1593 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1594 {
1595     env->CP0_Performance0 = arg1 & 0x000007ff;
1596 }
1597
1598 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1599 {
1600     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1601 }
1602
1603 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1604 {
1605     env->CP0_DataLo = arg1; /* XXX */
1606 }
1607
1608 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1609 {
1610     env->CP0_TagHi = arg1; /* XXX */
1611 }
1612
1613 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1614 {
1615     env->CP0_DataHi = arg1; /* XXX */
1616 }
1617
1618 /* MIPS MT functions */
1619 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1620 {
1621     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1622     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1623
1624     if (other_tc == other->current_tc)
1625         return other->active_tc.gpr[sel];
1626     else
1627         return other->tcs[other_tc].gpr[sel];
1628 }
1629
1630 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1631 {
1632     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1633     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1634
1635     if (other_tc == other->current_tc)
1636         return other->active_tc.LO[sel];
1637     else
1638         return other->tcs[other_tc].LO[sel];
1639 }
1640
1641 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1642 {
1643     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1644     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1645
1646     if (other_tc == other->current_tc)
1647         return other->active_tc.HI[sel];
1648     else
1649         return other->tcs[other_tc].HI[sel];
1650 }
1651
1652 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1653 {
1654     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1655     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1656
1657     if (other_tc == other->current_tc)
1658         return other->active_tc.ACX[sel];
1659     else
1660         return other->tcs[other_tc].ACX[sel];
1661 }
1662
1663 target_ulong helper_mftdsp(CPUMIPSState *env)
1664 {
1665     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1666     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1667
1668     if (other_tc == other->current_tc)
1669         return other->active_tc.DSPControl;
1670     else
1671         return other->tcs[other_tc].DSPControl;
1672 }
1673
1674 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1675 {
1676     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1677     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1678
1679     if (other_tc == other->current_tc)
1680         other->active_tc.gpr[sel] = arg1;
1681     else
1682         other->tcs[other_tc].gpr[sel] = arg1;
1683 }
1684
1685 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1686 {
1687     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1688     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1689
1690     if (other_tc == other->current_tc)
1691         other->active_tc.LO[sel] = arg1;
1692     else
1693         other->tcs[other_tc].LO[sel] = arg1;
1694 }
1695
1696 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1697 {
1698     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1699     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1700
1701     if (other_tc == other->current_tc)
1702         other->active_tc.HI[sel] = arg1;
1703     else
1704         other->tcs[other_tc].HI[sel] = arg1;
1705 }
1706
1707 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1708 {
1709     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1710     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1711
1712     if (other_tc == other->current_tc)
1713         other->active_tc.ACX[sel] = arg1;
1714     else
1715         other->tcs[other_tc].ACX[sel] = arg1;
1716 }
1717
1718 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1719 {
1720     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1721     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1722
1723     if (other_tc == other->current_tc)
1724         other->active_tc.DSPControl = arg1;
1725     else
1726         other->tcs[other_tc].DSPControl = arg1;
1727 }
1728
1729 /* MIPS MT functions */
1730 target_ulong helper_dmt(void)
1731 {
1732     // TODO
1733      return 0;
1734 }
1735
1736 target_ulong helper_emt(void)
1737 {
1738     // TODO
1739     return 0;
1740 }
1741
1742 target_ulong helper_dvpe(CPUMIPSState *env)
1743 {
1744     CPUState *other_cs = first_cpu;
1745     target_ulong prev = env->mvp->CP0_MVPControl;
1746
1747     CPU_FOREACH(other_cs) {
1748         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1749         /* Turn off all VPEs except the one executing the dvpe.  */
1750         if (&other_cpu->env != env) {
1751             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1752             mips_vpe_sleep(other_cpu);
1753         }
1754     }
1755     return prev;
1756 }
1757
1758 target_ulong helper_evpe(CPUMIPSState *env)
1759 {
1760     CPUState *other_cs = first_cpu;
1761     target_ulong prev = env->mvp->CP0_MVPControl;
1762
1763     CPU_FOREACH(other_cs) {
1764         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1765
1766         if (&other_cpu->env != env
1767             /* If the VPE is WFI, don't disturb its sleep.  */
1768             && !mips_vpe_is_wfi(other_cpu)) {
1769             /* Enable the VPE.  */
1770             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1771             mips_vpe_wake(other_cpu); /* And wake it up.  */
1772         }
1773     }
1774     return prev;
1775 }
1776 #endif /* !CONFIG_USER_ONLY */
1777
1778 void helper_fork(target_ulong arg1, target_ulong arg2)
1779 {
1780     // arg1 = rt, arg2 = rs
1781     // TODO: store to TC register
1782 }
1783
1784 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1785 {
1786     target_long arg1 = arg;
1787
1788     if (arg1 < 0) {
1789         /* No scheduling policy implemented. */
1790         if (arg1 != -2) {
1791             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1792                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1793                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1794                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1795                 helper_raise_exception(env, EXCP_THREAD);
1796             }
1797         }
1798     } else if (arg1 == 0) {
1799         if (0 /* TODO: TC underflow */) {
1800             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1801             helper_raise_exception(env, EXCP_THREAD);
1802         } else {
1803             // TODO: Deallocate TC
1804         }
1805     } else if (arg1 > 0) {
1806         /* Yield qualifier inputs not implemented. */
1807         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1808         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1809         helper_raise_exception(env, EXCP_THREAD);
1810     }
1811     return env->CP0_YQMask;
1812 }
1813
1814 #ifndef CONFIG_USER_ONLY
1815 /* TLB management */
1816 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1817 {
1818     MIPSCPU *cpu = mips_env_get_cpu(env);
1819
1820     /* Flush qemu's TLB and discard all shadowed entries.  */
1821     tlb_flush(CPU(cpu), flush_global);
1822     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1823 }
1824
1825 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1826 {
1827     /* Discard entries from env->tlb[first] onwards.  */
1828     while (env->tlb->tlb_in_use > first) {
1829         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1830     }
1831 }
1832
1833 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1834 {
1835 #if defined(TARGET_MIPS64)
1836     return extract64(entrylo, 6, 54);
1837 #else
1838     return extract64(entrylo, 6, 24) | /* PFN */
1839            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1840 #endif
1841 }
1842
1843 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1844 {
1845     r4k_tlb_t *tlb;
1846
1847     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1848     tlb = &env->tlb->mmu.r4k.tlb[idx];
1849     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1850         tlb->EHINV = 1;
1851         return;
1852     }
1853     tlb->EHINV = 0;
1854     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1855 #if defined(TARGET_MIPS64)
1856     tlb->VPN &= env->SEGMask;
1857 #endif
1858     tlb->ASID = env->CP0_EntryHi & 0xFF;
1859     tlb->PageMask = env->CP0_PageMask;
1860     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1861     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1862     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1863     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1864     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1865     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1866     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1867     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1868     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1869     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1870     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1871     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1872     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1873 }
1874
1875 void r4k_helper_tlbinv(CPUMIPSState *env)
1876 {
1877     int idx;
1878     r4k_tlb_t *tlb;
1879     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1880
1881     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1882         tlb = &env->tlb->mmu.r4k.tlb[idx];
1883         if (!tlb->G && tlb->ASID == ASID) {
1884             tlb->EHINV = 1;
1885         }
1886     }
1887     cpu_mips_tlb_flush(env, 1);
1888 }
1889
1890 void r4k_helper_tlbinvf(CPUMIPSState *env)
1891 {
1892     int idx;
1893
1894     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1895         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1896     }
1897     cpu_mips_tlb_flush(env, 1);
1898 }
1899
1900 void r4k_helper_tlbwi(CPUMIPSState *env)
1901 {
1902     r4k_tlb_t *tlb;
1903     int idx;
1904     target_ulong VPN;
1905     uint8_t ASID;
1906     bool G, V0, D0, V1, D1;
1907
1908     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1909     tlb = &env->tlb->mmu.r4k.tlb[idx];
1910     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1911 #if defined(TARGET_MIPS64)
1912     VPN &= env->SEGMask;
1913 #endif
1914     ASID = env->CP0_EntryHi & 0xff;
1915     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1916     V0 = (env->CP0_EntryLo0 & 2) != 0;
1917     D0 = (env->CP0_EntryLo0 & 4) != 0;
1918     V1 = (env->CP0_EntryLo1 & 2) != 0;
1919     D1 = (env->CP0_EntryLo1 & 4) != 0;
1920
1921     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1922        permissions on the current entry. */
1923     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1924         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1925         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1926         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1927     }
1928
1929     r4k_invalidate_tlb(env, idx, 0);
1930     r4k_fill_tlb(env, idx);
1931 }
1932
1933 void r4k_helper_tlbwr(CPUMIPSState *env)
1934 {
1935     int r = cpu_mips_get_random(env);
1936
1937     r4k_invalidate_tlb(env, r, 1);
1938     r4k_fill_tlb(env, r);
1939 }
1940
1941 void r4k_helper_tlbp(CPUMIPSState *env)
1942 {
1943     r4k_tlb_t *tlb;
1944     target_ulong mask;
1945     target_ulong tag;
1946     target_ulong VPN;
1947     uint8_t ASID;
1948     int i;
1949
1950     ASID = env->CP0_EntryHi & 0xFF;
1951     for (i = 0; i < env->tlb->nb_tlb; i++) {
1952         tlb = &env->tlb->mmu.r4k.tlb[i];
1953         /* 1k pages are not supported. */
1954         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1955         tag = env->CP0_EntryHi & ~mask;
1956         VPN = tlb->VPN & ~mask;
1957 #if defined(TARGET_MIPS64)
1958         tag &= env->SEGMask;
1959 #endif
1960         /* Check ASID, virtual page number & size */
1961         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1962             /* TLB match */
1963             env->CP0_Index = i;
1964             break;
1965         }
1966     }
1967     if (i == env->tlb->nb_tlb) {
1968         /* No match.  Discard any shadow entries, if any of them match.  */
1969         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1970             tlb = &env->tlb->mmu.r4k.tlb[i];
1971             /* 1k pages are not supported. */
1972             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1973             tag = env->CP0_EntryHi & ~mask;
1974             VPN = tlb->VPN & ~mask;
1975 #if defined(TARGET_MIPS64)
1976             tag &= env->SEGMask;
1977 #endif
1978             /* Check ASID, virtual page number & size */
1979             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1980                 r4k_mips_tlb_flush_extra (env, i);
1981                 break;
1982             }
1983         }
1984
1985         env->CP0_Index |= 0x80000000;
1986     }
1987 }
1988
1989 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
1990 {
1991 #if defined(TARGET_MIPS64)
1992     return tlb_pfn << 6;
1993 #else
1994     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
1995            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
1996 #endif
1997 }
1998
1999 void r4k_helper_tlbr(CPUMIPSState *env)
2000 {
2001     r4k_tlb_t *tlb;
2002     uint8_t ASID;
2003     int idx;
2004
2005     ASID = env->CP0_EntryHi & 0xFF;
2006     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2007     tlb = &env->tlb->mmu.r4k.tlb[idx];
2008
2009     /* If this will change the current ASID, flush qemu's TLB.  */
2010     if (ASID != tlb->ASID)
2011         cpu_mips_tlb_flush (env, 1);
2012
2013     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2014
2015     if (tlb->EHINV) {
2016         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2017         env->CP0_PageMask = 0;
2018         env->CP0_EntryLo0 = 0;
2019         env->CP0_EntryLo1 = 0;
2020     } else {
2021         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2022         env->CP0_PageMask = tlb->PageMask;
2023         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2024                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2025                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2026                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2027         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2028                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2029                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2030                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2031     }
2032 }
2033
2034 void helper_tlbwi(CPUMIPSState *env)
2035 {
2036     env->tlb->helper_tlbwi(env);
2037 }
2038
2039 void helper_tlbwr(CPUMIPSState *env)
2040 {
2041     env->tlb->helper_tlbwr(env);
2042 }
2043
2044 void helper_tlbp(CPUMIPSState *env)
2045 {
2046     env->tlb->helper_tlbp(env);
2047 }
2048
2049 void helper_tlbr(CPUMIPSState *env)
2050 {
2051     env->tlb->helper_tlbr(env);
2052 }
2053
2054 void helper_tlbinv(CPUMIPSState *env)
2055 {
2056     env->tlb->helper_tlbinv(env);
2057 }
2058
2059 void helper_tlbinvf(CPUMIPSState *env)
2060 {
2061     env->tlb->helper_tlbinvf(env);
2062 }
2063
2064 /* Specials */
2065 target_ulong helper_di(CPUMIPSState *env)
2066 {
2067     target_ulong t0 = env->CP0_Status;
2068
2069     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2070     return t0;
2071 }
2072
2073 target_ulong helper_ei(CPUMIPSState *env)
2074 {
2075     target_ulong t0 = env->CP0_Status;
2076
2077     env->CP0_Status = t0 | (1 << CP0St_IE);
2078     return t0;
2079 }
2080
2081 static void debug_pre_eret(CPUMIPSState *env)
2082 {
2083     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2084         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2085                 env->active_tc.PC, env->CP0_EPC);
2086         if (env->CP0_Status & (1 << CP0St_ERL))
2087             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2088         if (env->hflags & MIPS_HFLAG_DM)
2089             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2090         qemu_log("\n");
2091     }
2092 }
2093
2094 static void debug_post_eret(CPUMIPSState *env)
2095 {
2096     MIPSCPU *cpu = mips_env_get_cpu(env);
2097
2098     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2099         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2100                 env->active_tc.PC, env->CP0_EPC);
2101         if (env->CP0_Status & (1 << CP0St_ERL))
2102             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2103         if (env->hflags & MIPS_HFLAG_DM)
2104             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2105         switch (env->hflags & MIPS_HFLAG_KSU) {
2106         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2107         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2108         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2109         default:
2110             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2111             break;
2112         }
2113     }
2114 }
2115
2116 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2117 {
2118     env->active_tc.PC = error_pc & ~(target_ulong)1;
2119     if (error_pc & 1) {
2120         env->hflags |= MIPS_HFLAG_M16;
2121     } else {
2122         env->hflags &= ~(MIPS_HFLAG_M16);
2123     }
2124 }
2125
2126 static inline void exception_return(CPUMIPSState *env)
2127 {
2128     debug_pre_eret(env);
2129     if (env->CP0_Status & (1 << CP0St_ERL)) {
2130         set_pc(env, env->CP0_ErrorEPC);
2131         env->CP0_Status &= ~(1 << CP0St_ERL);
2132     } else {
2133         set_pc(env, env->CP0_EPC);
2134         env->CP0_Status &= ~(1 << CP0St_EXL);
2135     }
2136     compute_hflags(env);
2137     debug_post_eret(env);
2138 }
2139
2140 void helper_eret(CPUMIPSState *env)
2141 {
2142     exception_return(env);
2143     env->lladdr = 1;
2144 }
2145
2146 void helper_eretnc(CPUMIPSState *env)
2147 {
2148     exception_return(env);
2149 }
2150
2151 void helper_deret(CPUMIPSState *env)
2152 {
2153     debug_pre_eret(env);
2154     set_pc(env, env->CP0_DEPC);
2155
2156     env->hflags &= ~MIPS_HFLAG_DM;
2157     compute_hflags(env);
2158     debug_post_eret(env);
2159 }
2160 #endif /* !CONFIG_USER_ONLY */
2161
2162 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2163 {
2164     if ((env->hflags & MIPS_HFLAG_CP0) ||
2165         (env->CP0_HWREna & (1 << 0)))
2166         return env->CP0_EBase & 0x3ff;
2167     else
2168         helper_raise_exception(env, EXCP_RI);
2169
2170     return 0;
2171 }
2172
2173 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2174 {
2175     if ((env->hflags & MIPS_HFLAG_CP0) ||
2176         (env->CP0_HWREna & (1 << 1)))
2177         return env->SYNCI_Step;
2178     else
2179         helper_raise_exception(env, EXCP_RI);
2180
2181     return 0;
2182 }
2183
2184 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2185 {
2186     if ((env->hflags & MIPS_HFLAG_CP0) ||
2187         (env->CP0_HWREna & (1 << 2)))
2188         return env->CP0_Count;
2189     else
2190         helper_raise_exception(env, EXCP_RI);
2191
2192     return 0;
2193 }
2194
2195 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2196 {
2197     if ((env->hflags & MIPS_HFLAG_CP0) ||
2198         (env->CP0_HWREna & (1 << 3)))
2199         return env->CCRes;
2200     else
2201         helper_raise_exception(env, EXCP_RI);
2202
2203     return 0;
2204 }
2205
2206 void helper_pmon(CPUMIPSState *env, int function)
2207 {
2208     function /= 2;
2209     switch (function) {
2210     case 2: /* TODO: char inbyte(int waitflag); */
2211         if (env->active_tc.gpr[4] == 0)
2212             env->active_tc.gpr[2] = -1;
2213         /* Fall through */
2214     case 11: /* TODO: char inbyte (void); */
2215         env->active_tc.gpr[2] = -1;
2216         break;
2217     case 3:
2218     case 12:
2219         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2220         break;
2221     case 17:
2222         break;
2223     case 158:
2224         {
2225             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2226             printf("%s", fmt);
2227         }
2228         break;
2229     }
2230 }
2231
2232 void helper_wait(CPUMIPSState *env)
2233 {
2234     CPUState *cs = CPU(mips_env_get_cpu(env));
2235
2236     cs->halted = 1;
2237     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2238     helper_raise_exception(env, EXCP_HLT);
2239 }
2240
2241 #if !defined(CONFIG_USER_ONLY)
2242
2243 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2244                                   int access_type, int is_user,
2245                                   uintptr_t retaddr)
2246 {
2247     MIPSCPU *cpu = MIPS_CPU(cs);
2248     CPUMIPSState *env = &cpu->env;
2249     int error_code = 0;
2250     int excp;
2251
2252     env->CP0_BadVAddr = addr;
2253
2254     if (access_type == MMU_DATA_STORE) {
2255         excp = EXCP_AdES;
2256     } else {
2257         excp = EXCP_AdEL;
2258         if (access_type == MMU_INST_FETCH) {
2259             error_code |= EXCP_INST_NOTAVAIL;
2260         }
2261     }
2262
2263     do_raise_exception_err(env, excp, error_code, retaddr);
2264 }
2265
2266 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2267               uintptr_t retaddr)
2268 {
2269     int ret;
2270
2271     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2272     if (ret) {
2273         MIPSCPU *cpu = MIPS_CPU(cs);
2274         CPUMIPSState *env = &cpu->env;
2275
2276         do_raise_exception_err(env, cs->exception_index,
2277                                env->error_code, retaddr);
2278     }
2279 }
2280
2281 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2282                                 bool is_write, bool is_exec, int unused,
2283                                 unsigned size)
2284 {
2285     MIPSCPU *cpu = MIPS_CPU(cs);
2286     CPUMIPSState *env = &cpu->env;
2287
2288     /*
2289      * Raising an exception with KVM enabled will crash because it won't be from
2290      * the main execution loop so the longjmp won't have a matching setjmp.
2291      * Until we can trigger a bus error exception through KVM lets just ignore
2292      * the access.
2293      */
2294     if (kvm_enabled()) {
2295         return;
2296     }
2297
2298     if (is_exec) {
2299         helper_raise_exception(env, EXCP_IBE);
2300     } else {
2301         helper_raise_exception(env, EXCP_DBE);
2302     }
2303 }
2304 #endif /* !CONFIG_USER_ONLY */
2305
2306 /* Complex FPU operations which may need stack space. */
2307
2308 #define FLOAT_TWO32 make_float32(1 << 30)
2309 #define FLOAT_TWO64 make_float64(1ULL << 62)
2310 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2311 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2312
2313 /* convert MIPS rounding mode in FCR31 to IEEE library */
2314 unsigned int ieee_rm[] = {
2315     float_round_nearest_even,
2316     float_round_to_zero,
2317     float_round_up,
2318     float_round_down
2319 };
2320
2321 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2322 {
2323     target_ulong arg1 = 0;
2324
2325     switch (reg) {
2326     case 0:
2327         arg1 = (int32_t)env->active_fpu.fcr0;
2328         break;
2329     case 1:
2330         /* UFR Support - Read Status FR */
2331         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2332             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2333                 arg1 = (int32_t)
2334                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2335             } else {
2336                 helper_raise_exception(env, EXCP_RI);
2337             }
2338         }
2339         break;
2340     case 5:
2341         /* FRE Support - read Config5.FRE bit */
2342         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2343             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2344                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2345             } else {
2346                 helper_raise_exception(env, EXCP_RI);
2347             }
2348         }
2349         break;
2350     case 25:
2351         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2352         break;
2353     case 26:
2354         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2355         break;
2356     case 28:
2357         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2358         break;
2359     default:
2360         arg1 = (int32_t)env->active_fpu.fcr31;
2361         break;
2362     }
2363
2364     return arg1;
2365 }
2366
2367 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2368 {
2369     switch (fs) {
2370     case 1:
2371         /* UFR Alias - Reset Status FR */
2372         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2373             return;
2374         }
2375         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2376             env->CP0_Status &= ~(1 << CP0St_FR);
2377             compute_hflags(env);
2378         } else {
2379             helper_raise_exception(env, EXCP_RI);
2380         }
2381         break;
2382     case 4:
2383         /* UNFR Alias - Set Status FR */
2384         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2385             return;
2386         }
2387         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2388             env->CP0_Status |= (1 << CP0St_FR);
2389             compute_hflags(env);
2390         } else {
2391             helper_raise_exception(env, EXCP_RI);
2392         }
2393         break;
2394     case 5:
2395         /* FRE Support - clear Config5.FRE bit */
2396         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2397             return;
2398         }
2399         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2400             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2401             compute_hflags(env);
2402         } else {
2403             helper_raise_exception(env, EXCP_RI);
2404         }
2405         break;
2406     case 6:
2407         /* FRE Support - set Config5.FRE bit */
2408         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2409             return;
2410         }
2411         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2412             env->CP0_Config5 |= (1 << CP0C5_FRE);
2413             compute_hflags(env);
2414         } else {
2415             helper_raise_exception(env, EXCP_RI);
2416         }
2417         break;
2418     case 25:
2419         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2420             return;
2421         }
2422         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2423                      ((arg1 & 0x1) << 23);
2424         break;
2425     case 26:
2426         if (arg1 & 0x007c0000)
2427             return;
2428         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2429         break;
2430     case 28:
2431         if (arg1 & 0x007c0000)
2432             return;
2433         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2434                      ((arg1 & 0x4) << 22);
2435         break;
2436     case 31:
2437         if (env->insn_flags & ISA_MIPS32R6) {
2438             uint32_t mask = 0xfefc0000;
2439             env->active_fpu.fcr31 = (arg1 & ~mask) |
2440                 (env->active_fpu.fcr31 & mask);
2441         } else if (!(arg1 & 0x007c0000)) {
2442             env->active_fpu.fcr31 = arg1;
2443         }
2444         break;
2445     default:
2446         return;
2447     }
2448     /* set rounding mode */
2449     restore_rounding_mode(env);
2450     /* set flush-to-zero mode */
2451     restore_flush_mode(env);
2452     set_float_exception_flags(0, &env->active_fpu.fp_status);
2453     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2454         do_raise_exception(env, EXCP_FPE, GETPC());
2455 }
2456
2457 int ieee_ex_to_mips(int xcpt)
2458 {
2459     int ret = 0;
2460     if (xcpt) {
2461         if (xcpt & float_flag_invalid) {
2462             ret |= FP_INVALID;
2463         }
2464         if (xcpt & float_flag_overflow) {
2465             ret |= FP_OVERFLOW;
2466         }
2467         if (xcpt & float_flag_underflow) {
2468             ret |= FP_UNDERFLOW;
2469         }
2470         if (xcpt & float_flag_divbyzero) {
2471             ret |= FP_DIV0;
2472         }
2473         if (xcpt & float_flag_inexact) {
2474             ret |= FP_INEXACT;
2475         }
2476     }
2477     return ret;
2478 }
2479
2480 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2481 {
2482     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2483
2484     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2485
2486     if (tmp) {
2487         set_float_exception_flags(0, &env->active_fpu.fp_status);
2488
2489         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2490             do_raise_exception(env, EXCP_FPE, pc);
2491         } else {
2492             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2493         }
2494     }
2495 }
2496
2497 /* Float support.
2498    Single precition routines have a "s" suffix, double precision a
2499    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2500    paired single lower "pl", paired single upper "pu".  */
2501
2502 /* unary operations, modifying fp status  */
2503 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2504 {
2505     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2506     update_fcr31(env, GETPC());
2507     return fdt0;
2508 }
2509
2510 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2511 {
2512     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2513     update_fcr31(env, GETPC());
2514     return fst0;
2515 }
2516
2517 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2518 {
2519     uint64_t fdt2;
2520
2521     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2522     update_fcr31(env, GETPC());
2523     return fdt2;
2524 }
2525
2526 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2527 {
2528     uint64_t fdt2;
2529
2530     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2531     update_fcr31(env, GETPC());
2532     return fdt2;
2533 }
2534
2535 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2536 {
2537     uint64_t fdt2;
2538
2539     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2540     update_fcr31(env, GETPC());
2541     return fdt2;
2542 }
2543
2544 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2545 {
2546     uint64_t dt2;
2547
2548     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2549     if (get_float_exception_flags(&env->active_fpu.fp_status)
2550         & (float_flag_invalid | float_flag_overflow)) {
2551         dt2 = FP_TO_INT64_OVERFLOW;
2552     }
2553     update_fcr31(env, GETPC());
2554     return dt2;
2555 }
2556
2557 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2558 {
2559     uint64_t dt2;
2560
2561     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2562     if (get_float_exception_flags(&env->active_fpu.fp_status)
2563         & (float_flag_invalid | float_flag_overflow)) {
2564         dt2 = FP_TO_INT64_OVERFLOW;
2565     }
2566     update_fcr31(env, GETPC());
2567     return dt2;
2568 }
2569
2570 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2571 {
2572     uint32_t fst2;
2573     uint32_t fsth2;
2574
2575     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2576     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2577     update_fcr31(env, GETPC());
2578     return ((uint64_t)fsth2 << 32) | fst2;
2579 }
2580
2581 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2582 {
2583     uint32_t wt2;
2584     uint32_t wth2;
2585     int excp, excph;
2586
2587     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2588     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2589     if (excp & (float_flag_overflow | float_flag_invalid)) {
2590         wt2 = FP_TO_INT32_OVERFLOW;
2591     }
2592
2593     set_float_exception_flags(0, &env->active_fpu.fp_status);
2594     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2595     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2596     if (excph & (float_flag_overflow | float_flag_invalid)) {
2597         wth2 = FP_TO_INT32_OVERFLOW;
2598     }
2599
2600     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2601     update_fcr31(env, GETPC());
2602
2603     return ((uint64_t)wth2 << 32) | wt2;
2604 }
2605
2606 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2607 {
2608     uint32_t fst2;
2609
2610     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2611     update_fcr31(env, GETPC());
2612     return fst2;
2613 }
2614
2615 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2616 {
2617     uint32_t fst2;
2618
2619     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2620     update_fcr31(env, GETPC());
2621     return fst2;
2622 }
2623
2624 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2625 {
2626     uint32_t fst2;
2627
2628     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2629     update_fcr31(env, GETPC());
2630     return fst2;
2631 }
2632
2633 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2634 {
2635     uint32_t wt2;
2636
2637     wt2 = wt0;
2638     update_fcr31(env, GETPC());
2639     return wt2;
2640 }
2641
2642 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2643 {
2644     uint32_t wt2;
2645
2646     wt2 = wth0;
2647     update_fcr31(env, GETPC());
2648     return wt2;
2649 }
2650
2651 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2652 {
2653     uint32_t wt2;
2654
2655     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2656     if (get_float_exception_flags(&env->active_fpu.fp_status)
2657         & (float_flag_invalid | float_flag_overflow)) {
2658         wt2 = FP_TO_INT32_OVERFLOW;
2659     }
2660     update_fcr31(env, GETPC());
2661     return wt2;
2662 }
2663
2664 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2665 {
2666     uint32_t wt2;
2667
2668     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2669     if (get_float_exception_flags(&env->active_fpu.fp_status)
2670         & (float_flag_invalid | float_flag_overflow)) {
2671         wt2 = FP_TO_INT32_OVERFLOW;
2672     }
2673     update_fcr31(env, GETPC());
2674     return wt2;
2675 }
2676
2677 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2678 {
2679     uint64_t dt2;
2680
2681     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2682     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2683     restore_rounding_mode(env);
2684     if (get_float_exception_flags(&env->active_fpu.fp_status)
2685         & (float_flag_invalid | float_flag_overflow)) {
2686         dt2 = FP_TO_INT64_OVERFLOW;
2687     }
2688     update_fcr31(env, GETPC());
2689     return dt2;
2690 }
2691
2692 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2693 {
2694     uint64_t dt2;
2695
2696     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2697     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2698     restore_rounding_mode(env);
2699     if (get_float_exception_flags(&env->active_fpu.fp_status)
2700         & (float_flag_invalid | float_flag_overflow)) {
2701         dt2 = FP_TO_INT64_OVERFLOW;
2702     }
2703     update_fcr31(env, GETPC());
2704     return dt2;
2705 }
2706
2707 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2708 {
2709     uint32_t wt2;
2710
2711     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2712     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2713     restore_rounding_mode(env);
2714     if (get_float_exception_flags(&env->active_fpu.fp_status)
2715         & (float_flag_invalid | float_flag_overflow)) {
2716         wt2 = FP_TO_INT32_OVERFLOW;
2717     }
2718     update_fcr31(env, GETPC());
2719     return wt2;
2720 }
2721
2722 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2723 {
2724     uint32_t wt2;
2725
2726     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2727     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2728     restore_rounding_mode(env);
2729     if (get_float_exception_flags(&env->active_fpu.fp_status)
2730         & (float_flag_invalid | float_flag_overflow)) {
2731         wt2 = FP_TO_INT32_OVERFLOW;
2732     }
2733     update_fcr31(env, GETPC());
2734     return wt2;
2735 }
2736
2737 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2738 {
2739     uint64_t dt2;
2740
2741     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2742     if (get_float_exception_flags(&env->active_fpu.fp_status)
2743         & (float_flag_invalid | float_flag_overflow)) {
2744         dt2 = FP_TO_INT64_OVERFLOW;
2745     }
2746     update_fcr31(env, GETPC());
2747     return dt2;
2748 }
2749
2750 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2751 {
2752     uint64_t dt2;
2753
2754     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2755     if (get_float_exception_flags(&env->active_fpu.fp_status)
2756         & (float_flag_invalid | float_flag_overflow)) {
2757         dt2 = FP_TO_INT64_OVERFLOW;
2758     }
2759     update_fcr31(env, GETPC());
2760     return dt2;
2761 }
2762
2763 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2764 {
2765     uint32_t wt2;
2766
2767     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2768     if (get_float_exception_flags(&env->active_fpu.fp_status)
2769         & (float_flag_invalid | float_flag_overflow)) {
2770         wt2 = FP_TO_INT32_OVERFLOW;
2771     }
2772     update_fcr31(env, GETPC());
2773     return wt2;
2774 }
2775
2776 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2777 {
2778     uint32_t wt2;
2779
2780     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2781     if (get_float_exception_flags(&env->active_fpu.fp_status)
2782         & (float_flag_invalid | float_flag_overflow)) {
2783         wt2 = FP_TO_INT32_OVERFLOW;
2784     }
2785     update_fcr31(env, GETPC());
2786     return wt2;
2787 }
2788
2789 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2790 {
2791     uint64_t dt2;
2792
2793     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2794     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2795     restore_rounding_mode(env);
2796     if (get_float_exception_flags(&env->active_fpu.fp_status)
2797         & (float_flag_invalid | float_flag_overflow)) {
2798         dt2 = FP_TO_INT64_OVERFLOW;
2799     }
2800     update_fcr31(env, GETPC());
2801     return dt2;
2802 }
2803
2804 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2805 {
2806     uint64_t dt2;
2807
2808     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2809     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2810     restore_rounding_mode(env);
2811     if (get_float_exception_flags(&env->active_fpu.fp_status)
2812         & (float_flag_invalid | float_flag_overflow)) {
2813         dt2 = FP_TO_INT64_OVERFLOW;
2814     }
2815     update_fcr31(env, GETPC());
2816     return dt2;
2817 }
2818
2819 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2820 {
2821     uint32_t wt2;
2822
2823     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2824     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2825     restore_rounding_mode(env);
2826     if (get_float_exception_flags(&env->active_fpu.fp_status)
2827         & (float_flag_invalid | float_flag_overflow)) {
2828         wt2 = FP_TO_INT32_OVERFLOW;
2829     }
2830     update_fcr31(env, GETPC());
2831     return wt2;
2832 }
2833
2834 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2835 {
2836     uint32_t wt2;
2837
2838     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2839     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2840     restore_rounding_mode(env);
2841     if (get_float_exception_flags(&env->active_fpu.fp_status)
2842         & (float_flag_invalid | float_flag_overflow)) {
2843         wt2 = FP_TO_INT32_OVERFLOW;
2844     }
2845     update_fcr31(env, GETPC());
2846     return wt2;
2847 }
2848
2849 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2850 {
2851     uint64_t dt2;
2852
2853     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2854     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2855     restore_rounding_mode(env);
2856     if (get_float_exception_flags(&env->active_fpu.fp_status)
2857         & (float_flag_invalid | float_flag_overflow)) {
2858         dt2 = FP_TO_INT64_OVERFLOW;
2859     }
2860     update_fcr31(env, GETPC());
2861     return dt2;
2862 }
2863
2864 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2865 {
2866     uint64_t dt2;
2867
2868     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2869     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2870     restore_rounding_mode(env);
2871     if (get_float_exception_flags(&env->active_fpu.fp_status)
2872         & (float_flag_invalid | float_flag_overflow)) {
2873         dt2 = FP_TO_INT64_OVERFLOW;
2874     }
2875     update_fcr31(env, GETPC());
2876     return dt2;
2877 }
2878
2879 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2880 {
2881     uint32_t wt2;
2882
2883     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2884     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2885     restore_rounding_mode(env);
2886     if (get_float_exception_flags(&env->active_fpu.fp_status)
2887         & (float_flag_invalid | float_flag_overflow)) {
2888         wt2 = FP_TO_INT32_OVERFLOW;
2889     }
2890     update_fcr31(env, GETPC());
2891     return wt2;
2892 }
2893
2894 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2895 {
2896     uint32_t wt2;
2897
2898     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2899     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2900     restore_rounding_mode(env);
2901     if (get_float_exception_flags(&env->active_fpu.fp_status)
2902         & (float_flag_invalid | float_flag_overflow)) {
2903         wt2 = FP_TO_INT32_OVERFLOW;
2904     }
2905     update_fcr31(env, GETPC());
2906     return wt2;
2907 }
2908
2909 /* unary operations, not modifying fp status  */
2910 #define FLOAT_UNOP(name)                                       \
2911 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2912 {                                                              \
2913     return float64_ ## name(fdt0);                             \
2914 }                                                              \
2915 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2916 {                                                              \
2917     return float32_ ## name(fst0);                             \
2918 }                                                              \
2919 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2920 {                                                              \
2921     uint32_t wt0;                                              \
2922     uint32_t wth0;                                             \
2923                                                                \
2924     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2925     wth0 = float32_ ## name(fdt0 >> 32);                       \
2926     return ((uint64_t)wth0 << 32) | wt0;                       \
2927 }
2928 FLOAT_UNOP(abs)
2929 FLOAT_UNOP(chs)
2930 #undef FLOAT_UNOP
2931
2932 /* MIPS specific unary operations */
2933 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2934 {
2935     uint64_t fdt2;
2936
2937     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2938     update_fcr31(env, GETPC());
2939     return fdt2;
2940 }
2941
2942 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2943 {
2944     uint32_t fst2;
2945
2946     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2947     update_fcr31(env, GETPC());
2948     return fst2;
2949 }
2950
2951 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2952 {
2953     uint64_t fdt2;
2954
2955     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2956     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2957     update_fcr31(env, GETPC());
2958     return fdt2;
2959 }
2960
2961 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2962 {
2963     uint32_t fst2;
2964
2965     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2966     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2967     update_fcr31(env, GETPC());
2968     return fst2;
2969 }
2970
2971 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2972 {
2973     uint64_t fdt2;
2974
2975     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2976     update_fcr31(env, GETPC());
2977     return fdt2;
2978 }
2979
2980 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2981 {
2982     uint32_t fst2;
2983
2984     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2985     update_fcr31(env, GETPC());
2986     return fst2;
2987 }
2988
2989 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2990 {
2991     uint32_t fst2;
2992     uint32_t fsth2;
2993
2994     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2995     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2996     update_fcr31(env, GETPC());
2997     return ((uint64_t)fsth2 << 32) | fst2;
2998 }
2999
3000 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3001 {
3002     uint64_t fdt2;
3003
3004     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3005     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3006     update_fcr31(env, GETPC());
3007     return fdt2;
3008 }
3009
3010 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3011 {
3012     uint32_t fst2;
3013
3014     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3015     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3016     update_fcr31(env, GETPC());
3017     return fst2;
3018 }
3019
3020 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3021 {
3022     uint32_t fst2;
3023     uint32_t fsth2;
3024
3025     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3026     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3027     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3028     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3029     update_fcr31(env, GETPC());
3030     return ((uint64_t)fsth2 << 32) | fst2;
3031 }
3032
3033 #define FLOAT_RINT(name, bits)                                              \
3034 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3035                                           uint ## bits ## _t fs)            \
3036 {                                                                           \
3037     uint ## bits ## _t fdret;                                               \
3038                                                                             \
3039     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3040     update_fcr31(env, GETPC());                                             \
3041     return fdret;                                                           \
3042 }
3043
3044 FLOAT_RINT(rint_s, 32)
3045 FLOAT_RINT(rint_d, 64)
3046 #undef FLOAT_RINT
3047
3048 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3049 #define FLOAT_CLASS_QUIET_NAN          0x002
3050 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3051 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3052 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3053 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3054 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3055 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3056 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3057 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3058
3059 #define FLOAT_CLASS(name, bits)                                      \
3060 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3061 {                                                                    \
3062     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3063         return FLOAT_CLASS_SIGNALING_NAN;                            \
3064     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3065         return FLOAT_CLASS_QUIET_NAN;                                \
3066     } else if (float ## bits ## _is_neg(arg)) {                      \
3067         if (float ## bits ## _is_infinity(arg)) {                    \
3068             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3069         } else if (float ## bits ## _is_zero(arg)) {                 \
3070             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3071         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3072             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3073         } else {                                                     \
3074             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3075         }                                                            \
3076     } else {                                                         \
3077         if (float ## bits ## _is_infinity(arg)) {                    \
3078             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3079         } else if (float ## bits ## _is_zero(arg)) {                 \
3080             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3081         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3082             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3083         } else {                                                     \
3084             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3085         }                                                            \
3086     }                                                                \
3087 }
3088
3089 FLOAT_CLASS(class_s, 32)
3090 FLOAT_CLASS(class_d, 64)
3091 #undef FLOAT_CLASS
3092
3093 /* binary operations */
3094 #define FLOAT_BINOP(name)                                          \
3095 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3096                                      uint64_t fdt0, uint64_t fdt1) \
3097 {                                                                  \
3098     uint64_t dt2;                                                  \
3099                                                                    \
3100     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3101     update_fcr31(env, GETPC());                                    \
3102     return dt2;                                                    \
3103 }                                                                  \
3104                                                                    \
3105 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3106                                      uint32_t fst0, uint32_t fst1) \
3107 {                                                                  \
3108     uint32_t wt2;                                                  \
3109                                                                    \
3110     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3111     update_fcr31(env, GETPC());                                    \
3112     return wt2;                                                    \
3113 }                                                                  \
3114                                                                    \
3115 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3116                                       uint64_t fdt0,               \
3117                                       uint64_t fdt1)               \
3118 {                                                                  \
3119     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3120     uint32_t fsth0 = fdt0 >> 32;                                   \
3121     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3122     uint32_t fsth1 = fdt1 >> 32;                                   \
3123     uint32_t wt2;                                                  \
3124     uint32_t wth2;                                                 \
3125                                                                    \
3126     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3127     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3128     update_fcr31(env, GETPC());                                    \
3129     return ((uint64_t)wth2 << 32) | wt2;                           \
3130 }
3131
3132 FLOAT_BINOP(add)
3133 FLOAT_BINOP(sub)
3134 FLOAT_BINOP(mul)
3135 FLOAT_BINOP(div)
3136 #undef FLOAT_BINOP
3137
3138 /* MIPS specific binary operations */
3139 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3140 {
3141     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3142     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3143     update_fcr31(env, GETPC());
3144     return fdt2;
3145 }
3146
3147 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3148 {
3149     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3150     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3151     update_fcr31(env, GETPC());
3152     return fst2;
3153 }
3154
3155 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3156 {
3157     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3158     uint32_t fsth0 = fdt0 >> 32;
3159     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3160     uint32_t fsth2 = fdt2 >> 32;
3161
3162     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3163     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3164     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3165     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3166     update_fcr31(env, GETPC());
3167     return ((uint64_t)fsth2 << 32) | fst2;
3168 }
3169
3170 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3171 {
3172     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3173     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3174     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3175     update_fcr31(env, GETPC());
3176     return fdt2;
3177 }
3178
3179 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3180 {
3181     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3182     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3183     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3184     update_fcr31(env, GETPC());
3185     return fst2;
3186 }
3187
3188 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3189 {
3190     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3191     uint32_t fsth0 = fdt0 >> 32;
3192     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3193     uint32_t fsth2 = fdt2 >> 32;
3194
3195     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3196     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3197     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3198     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3199     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3200     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3201     update_fcr31(env, GETPC());
3202     return ((uint64_t)fsth2 << 32) | fst2;
3203 }
3204
3205 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3206 {
3207     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3208     uint32_t fsth0 = fdt0 >> 32;
3209     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3210     uint32_t fsth1 = fdt1 >> 32;
3211     uint32_t fst2;
3212     uint32_t fsth2;
3213
3214     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3215     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3216     update_fcr31(env, GETPC());
3217     return ((uint64_t)fsth2 << 32) | fst2;
3218 }
3219
3220 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3221 {
3222     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3223     uint32_t fsth0 = fdt0 >> 32;
3224     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3225     uint32_t fsth1 = fdt1 >> 32;
3226     uint32_t fst2;
3227     uint32_t fsth2;
3228
3229     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3230     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3231     update_fcr31(env, GETPC());
3232     return ((uint64_t)fsth2 << 32) | fst2;
3233 }
3234
3235 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3236 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3237                                           uint ## bits ## _t fs,        \
3238                                           uint ## bits ## _t ft)        \
3239 {                                                                       \
3240     uint ## bits ## _t fdret;                                           \
3241                                                                         \
3242     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3243                                            &env->active_fpu.fp_status); \
3244     update_fcr31(env, GETPC());                                         \
3245     return fdret;                                                       \
3246 }
3247
3248 FLOAT_MINMAX(max_s, 32, maxnum)
3249 FLOAT_MINMAX(max_d, 64, maxnum)
3250 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3251 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3252
3253 FLOAT_MINMAX(min_s, 32, minnum)
3254 FLOAT_MINMAX(min_d, 64, minnum)
3255 FLOAT_MINMAX(mina_s, 32, minnummag)
3256 FLOAT_MINMAX(mina_d, 64, minnummag)
3257 #undef FLOAT_MINMAX
3258
3259 /* ternary operations */
3260 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3261 {                                                                    \
3262     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3263     if ((flags) & float_muladd_negate_c) {                           \
3264         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3265     } else {                                                         \
3266         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3267     }                                                                \
3268     if ((flags) & float_muladd_negate_result) {                      \
3269         a = prefix##_chs(a);                                         \
3270     }                                                                \
3271 }
3272
3273 /* FMA based operations */
3274 #define FLOAT_FMA(name, type)                                        \
3275 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3276                                      uint64_t fdt0, uint64_t fdt1,   \
3277                                      uint64_t fdt2)                  \
3278 {                                                                    \
3279     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3280     update_fcr31(env, GETPC());                                      \
3281     return fdt0;                                                     \
3282 }                                                                    \
3283                                                                      \
3284 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3285                                      uint32_t fst0, uint32_t fst1,   \
3286                                      uint32_t fst2)                  \
3287 {                                                                    \
3288     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3289     update_fcr31(env, GETPC());                                      \
3290     return fst0;                                                     \
3291 }                                                                    \
3292                                                                      \
3293 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3294                                       uint64_t fdt0, uint64_t fdt1,  \
3295                                       uint64_t fdt2)                 \
3296 {                                                                    \
3297     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3298     uint32_t fsth0 = fdt0 >> 32;                                     \
3299     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3300     uint32_t fsth1 = fdt1 >> 32;                                     \
3301     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3302     uint32_t fsth2 = fdt2 >> 32;                                     \
3303                                                                      \
3304     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3305     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3306     update_fcr31(env, GETPC());                                      \
3307     return ((uint64_t)fsth0 << 32) | fst0;                           \
3308 }
3309 FLOAT_FMA(madd, 0)
3310 FLOAT_FMA(msub, float_muladd_negate_c)
3311 FLOAT_FMA(nmadd, float_muladd_negate_result)
3312 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3313 #undef FLOAT_FMA
3314
3315 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3316 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3317                                           uint ## bits ## _t fs,        \
3318                                           uint ## bits ## _t ft,        \
3319                                           uint ## bits ## _t fd)        \
3320 {                                                                       \
3321     uint ## bits ## _t fdret;                                           \
3322                                                                         \
3323     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3324                                      &env->active_fpu.fp_status);       \
3325     update_fcr31(env, GETPC());                                         \
3326     return fdret;                                                       \
3327 }
3328
3329 FLOAT_FMADDSUB(maddf_s, 32, 0)
3330 FLOAT_FMADDSUB(maddf_d, 64, 0)
3331 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3332 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3333 #undef FLOAT_FMADDSUB
3334
3335 /* compare operations */
3336 #define FOP_COND_D(op, cond)                                   \
3337 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3338                          uint64_t fdt1, int cc)                \
3339 {                                                              \
3340     int c;                                                     \
3341     c = cond;                                                  \
3342     update_fcr31(env, GETPC());                                \
3343     if (c)                                                     \
3344         SET_FP_COND(cc, env->active_fpu);                      \
3345     else                                                       \
3346         CLEAR_FP_COND(cc, env->active_fpu);                    \
3347 }                                                              \
3348 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3349                             uint64_t fdt1, int cc)             \
3350 {                                                              \
3351     int c;                                                     \
3352     fdt0 = float64_abs(fdt0);                                  \
3353     fdt1 = float64_abs(fdt1);                                  \
3354     c = cond;                                                  \
3355     update_fcr31(env, GETPC());                                \
3356     if (c)                                                     \
3357         SET_FP_COND(cc, env->active_fpu);                      \
3358     else                                                       \
3359         CLEAR_FP_COND(cc, env->active_fpu);                    \
3360 }
3361
3362 /* NOTE: the comma operator will make "cond" to eval to false,
3363  * but float64_unordered_quiet() is still called. */
3364 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3365 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3366 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3367 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3368 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3369 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3370 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3371 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3372 /* NOTE: the comma operator will make "cond" to eval to false,
3373  * but float64_unordered() is still called. */
3374 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3375 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3376 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3377 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3378 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3379 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3380 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3381 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3382
3383 #define FOP_COND_S(op, cond)                                   \
3384 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3385                          uint32_t fst1, int cc)                \
3386 {                                                              \
3387     int c;                                                     \
3388     c = cond;                                                  \
3389     update_fcr31(env, GETPC());                                \
3390     if (c)                                                     \
3391         SET_FP_COND(cc, env->active_fpu);                      \
3392     else                                                       \
3393         CLEAR_FP_COND(cc, env->active_fpu);                    \
3394 }                                                              \
3395 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3396                             uint32_t fst1, int cc)             \
3397 {                                                              \
3398     int c;                                                     \
3399     fst0 = float32_abs(fst0);                                  \
3400     fst1 = float32_abs(fst1);                                  \
3401     c = cond;                                                  \
3402     update_fcr31(env, GETPC());                                \
3403     if (c)                                                     \
3404         SET_FP_COND(cc, env->active_fpu);                      \
3405     else                                                       \
3406         CLEAR_FP_COND(cc, env->active_fpu);                    \
3407 }
3408
3409 /* NOTE: the comma operator will make "cond" to eval to false,
3410  * but float32_unordered_quiet() is still called. */
3411 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3412 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3413 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3414 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3415 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3416 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3417 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3418 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3419 /* NOTE: the comma operator will make "cond" to eval to false,
3420  * but float32_unordered() is still called. */
3421 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3422 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3423 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3424 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3425 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3426 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3427 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3428 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3429
3430 #define FOP_COND_PS(op, condl, condh)                           \
3431 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3432                           uint64_t fdt1, int cc)                \
3433 {                                                               \
3434     uint32_t fst0, fsth0, fst1, fsth1;                          \
3435     int ch, cl;                                                 \
3436     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3437     fsth0 = fdt0 >> 32;                                         \
3438     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3439     fsth1 = fdt1 >> 32;                                         \
3440     cl = condl;                                                 \
3441     ch = condh;                                                 \
3442     update_fcr31(env, GETPC());                                 \
3443     if (cl)                                                     \
3444         SET_FP_COND(cc, env->active_fpu);                       \
3445     else                                                        \
3446         CLEAR_FP_COND(cc, env->active_fpu);                     \
3447     if (ch)                                                     \
3448         SET_FP_COND(cc + 1, env->active_fpu);                   \
3449     else                                                        \
3450         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3451 }                                                               \
3452 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3453                              uint64_t fdt1, int cc)             \
3454 {                                                               \
3455     uint32_t fst0, fsth0, fst1, fsth1;                          \
3456     int ch, cl;                                                 \
3457     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3458     fsth0 = float32_abs(fdt0 >> 32);                            \
3459     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3460     fsth1 = float32_abs(fdt1 >> 32);                            \
3461     cl = condl;                                                 \
3462     ch = condh;                                                 \
3463     update_fcr31(env, GETPC());                                 \
3464     if (cl)                                                     \
3465         SET_FP_COND(cc, env->active_fpu);                       \
3466     else                                                        \
3467         CLEAR_FP_COND(cc, env->active_fpu);                     \
3468     if (ch)                                                     \
3469         SET_FP_COND(cc + 1, env->active_fpu);                   \
3470     else                                                        \
3471         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3472 }
3473
3474 /* NOTE: the comma operator will make "cond" to eval to false,
3475  * but float32_unordered_quiet() is still called. */
3476 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3477                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3478 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3479                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3480 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3481                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3482 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3483                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3484 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3485                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3486 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3487                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3488 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3489                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3490 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3491                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3492 /* NOTE: the comma operator will make "cond" to eval to false,
3493  * but float32_unordered() is still called. */
3494 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3495                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3496 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3497                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3498 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3499                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3500 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3501                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3502 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3503                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3504 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3505                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3506 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3507                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3508 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3509                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3510
3511 /* R6 compare operations */
3512 #define FOP_CONDN_D(op, cond)                                       \
3513 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3514                          uint64_t fdt1)                             \
3515 {                                                                   \
3516     uint64_t c;                                                     \
3517     c = cond;                                                       \
3518     update_fcr31(env, GETPC());                                     \
3519     if (c) {                                                        \
3520         return -1;                                                  \
3521     } else {                                                        \
3522         return 0;                                                   \
3523     }                                                               \
3524 }
3525
3526 /* NOTE: the comma operator will make "cond" to eval to false,
3527  * but float64_unordered_quiet() is still called. */
3528 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3529 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3530 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3531 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3532                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3533 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3534 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3535                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3536 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3537 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3538                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3539 /* NOTE: the comma operator will make "cond" to eval to false,
3540  * but float64_unordered() is still called. */
3541 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3542 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3543 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3544 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3545                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3546 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3547 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3548                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3549 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3550 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3551                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3552 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3553                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3554 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3555                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3556                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3557 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3558                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3559 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3560                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3561 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3562                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3563                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3564 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3565                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3566
3567 #define FOP_CONDN_S(op, cond)                                       \
3568 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3569                          uint32_t fst1)                             \
3570 {                                                                   \
3571     uint64_t c;                                                     \
3572     c = cond;                                                       \
3573     update_fcr31(env, GETPC());                                     \
3574     if (c) {                                                        \
3575         return -1;                                                  \
3576     } else {                                                        \
3577         return 0;                                                   \
3578     }                                                               \
3579 }
3580
3581 /* NOTE: the comma operator will make "cond" to eval to false,
3582  * but float32_unordered_quiet() is still called. */
3583 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3584 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3585 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3586 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3587                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3588 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3589 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3590                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3591 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3592 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3593                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3594 /* NOTE: the comma operator will make "cond" to eval to false,
3595  * but float32_unordered() is still called. */
3596 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3597 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3598 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3599 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3600                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3601 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3602 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3603                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3604 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3605 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3606                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3607 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3608                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3609 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3610                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3611                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3612 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3613                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3614 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3615                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3616 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3617                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3618                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3619 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3620                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3621
3622 /* MSA */
3623 /* Data format min and max values */
3624 #define DF_BITS(df) (1 << ((df) + 3))
3625
3626 /* Element-by-element access macros */
3627 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3628
3629 #if !defined(CONFIG_USER_ONLY)
3630 #define MEMOP_IDX(DF)                                           \
3631         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3632                                         cpu_mmu_index(env));
3633 #else
3634 #define MEMOP_IDX(DF)
3635 #endif
3636
3637 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3638 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3639                             target_ulong addr)                          \
3640 {                                                                       \
3641     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3642     wr_t wx;                                                            \
3643     int i;                                                              \
3644     MEMOP_IDX(DF)                                                       \
3645     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3646         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3647     }                                                                   \
3648     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3649 }
3650
3651 #if !defined(CONFIG_USER_ONLY)
3652 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3653 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3654 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3655 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3656 #else
3657 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3658 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3659 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3660 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3661 #endif
3662
3663 #define MSA_PAGESPAN(x) \
3664         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3665
3666 static inline void ensure_writable_pages(CPUMIPSState *env,
3667                                          target_ulong addr,
3668                                          int mmu_idx,
3669                                          uintptr_t retaddr)
3670 {
3671 #if !defined(CONFIG_USER_ONLY)
3672     target_ulong page_addr;
3673     if (unlikely(MSA_PAGESPAN(addr))) {
3674         /* first page */
3675         probe_write(env, addr, mmu_idx, retaddr);
3676         /* second page */
3677         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3678         probe_write(env, page_addr, mmu_idx, retaddr);
3679     }
3680 #endif
3681 }
3682
3683 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3684 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3685                             target_ulong addr)                          \
3686 {                                                                       \
3687     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3688     int mmu_idx = cpu_mmu_index(env);                                   \
3689     int i;                                                              \
3690     MEMOP_IDX(DF)                                                       \
3691     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3692     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3693         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3694     }                                                                   \
3695 }
3696
3697 #if !defined(CONFIG_USER_ONLY)
3698 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3699 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3700 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3701 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3702 #else
3703 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3704 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3705 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3706 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3707 #endif