target-microblaze: Cleanup dec_mul
[qemu/ar7.git] / target-sparc / helper.c
blob359b0b15ed30ee7b712fc77b0049f0559548541d
1 /*
2 * Misc Sparc helpers
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "sysemu/sysemu.h"
27 void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra)
29 CPUState *cs = CPU(sparc_env_get_cpu(env));
31 cs->exception_index = tt;
32 cpu_loop_exit_restore(cs, ra);
35 void helper_raise_exception(CPUSPARCState *env, int tt)
37 CPUState *cs = CPU(sparc_env_get_cpu(env));
39 cs->exception_index = tt;
40 cpu_loop_exit(cs);
43 void helper_debug(CPUSPARCState *env)
45 CPUState *cs = CPU(sparc_env_get_cpu(env));
47 cs->exception_index = EXCP_DEBUG;
48 cpu_loop_exit(cs);
51 #ifdef TARGET_SPARC64
52 target_ulong helper_popc(target_ulong val)
54 return ctpop64(val);
57 void helper_tick_set_count(void *opaque, uint64_t count)
59 #if !defined(CONFIG_USER_ONLY)
60 cpu_tick_set_count(opaque, count);
61 #endif
64 uint64_t helper_tick_get_count(CPUSPARCState *env, void *opaque, int mem_idx)
66 #if !defined(CONFIG_USER_ONLY)
67 CPUTimer *timer = opaque;
69 if (timer->npt && mem_idx < MMU_KERNEL_IDX) {
70 cpu_raise_exception_ra(env, TT_PRIV_INSN, GETPC());
73 return cpu_tick_get_count(timer);
74 #else
75 return 0;
76 #endif
79 void helper_tick_set_limit(void *opaque, uint64_t limit)
81 #if !defined(CONFIG_USER_ONLY)
82 cpu_tick_set_limit(opaque, limit);
83 #endif
85 #endif
87 static target_ulong do_udiv(CPUSPARCState *env, target_ulong a,
88 target_ulong b, int cc, uintptr_t ra)
90 int overflow = 0;
91 uint64_t x0;
92 uint32_t x1;
94 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
95 x1 = (b & 0xffffffff);
97 if (x1 == 0) {
98 cpu_raise_exception_ra(env, TT_DIV_ZERO, ra);
101 x0 = x0 / x1;
102 if (x0 > UINT32_MAX) {
103 x0 = UINT32_MAX;
104 overflow = 1;
107 if (cc) {
108 env->cc_dst = x0;
109 env->cc_src2 = overflow;
110 env->cc_op = CC_OP_DIV;
112 return x0;
115 target_ulong helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong b)
117 return do_udiv(env, a, b, 0, GETPC());
120 target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)
122 return do_udiv(env, a, b, 1, GETPC());
125 static target_ulong do_sdiv(CPUSPARCState *env, target_ulong a,
126 target_ulong b, int cc, uintptr_t ra)
128 int overflow = 0;
129 int64_t x0;
130 int32_t x1;
132 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
133 x1 = (b & 0xffffffff);
135 if (x1 == 0) {
136 cpu_raise_exception_ra(env, TT_DIV_ZERO, ra);
137 } else if (x1 == -1 && x0 == INT64_MIN) {
138 x0 = INT32_MAX;
139 overflow = 1;
140 } else {
141 x0 = x0 / x1;
142 if ((int32_t) x0 != x0) {
143 x0 = x0 < 0 ? INT32_MIN : INT32_MAX;
144 overflow = 1;
148 if (cc) {
149 env->cc_dst = x0;
150 env->cc_src2 = overflow;
151 env->cc_op = CC_OP_DIV;
153 return x0;
156 target_ulong helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong b)
158 return do_sdiv(env, a, b, 0, GETPC());
161 target_ulong helper_sdiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)
163 return do_sdiv(env, a, b, 1, GETPC());
166 #ifdef TARGET_SPARC64
167 int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b)
169 if (b == 0) {
170 /* Raise divide by zero trap. */
171 cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC());
172 } else if (b == -1) {
173 /* Avoid overflow trap with i386 divide insn. */
174 return -a;
175 } else {
176 return a / b;
180 uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b)
182 if (b == 0) {
183 /* Raise divide by zero trap. */
184 cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC());
186 return a / b;
188 #endif
190 target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
191 target_ulong src2)
193 target_ulong dst;
195 /* Tag overflow occurs if either input has bits 0 or 1 set. */
196 if ((src1 | src2) & 3) {
197 goto tag_overflow;
200 dst = src1 + src2;
202 /* Tag overflow occurs if the addition overflows. */
203 if (~(src1 ^ src2) & (src1 ^ dst) & (1u << 31)) {
204 goto tag_overflow;
207 /* Only modify the CC after any exceptions have been generated. */
208 env->cc_op = CC_OP_TADDTV;
209 env->cc_src = src1;
210 env->cc_src2 = src2;
211 env->cc_dst = dst;
212 return dst;
214 tag_overflow:
215 cpu_raise_exception_ra(env, TT_TOVF, GETPC());
218 target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
219 target_ulong src2)
221 target_ulong dst;
223 /* Tag overflow occurs if either input has bits 0 or 1 set. */
224 if ((src1 | src2) & 3) {
225 goto tag_overflow;
228 dst = src1 - src2;
230 /* Tag overflow occurs if the subtraction overflows. */
231 if ((src1 ^ src2) & (src1 ^ dst) & (1u << 31)) {
232 goto tag_overflow;
235 /* Only modify the CC after any exceptions have been generated. */
236 env->cc_op = CC_OP_TSUBTV;
237 env->cc_src = src1;
238 env->cc_src2 = src2;
239 env->cc_dst = dst;
240 return dst;
242 tag_overflow:
243 cpu_raise_exception_ra(env, TT_TOVF, GETPC());
246 #ifndef TARGET_SPARC64
247 void helper_power_down(CPUSPARCState *env)
249 CPUState *cs = CPU(sparc_env_get_cpu(env));
251 cs->halted = 1;
252 cs->exception_index = EXCP_HLT;
253 env->pc = env->npc;
254 env->npc = env->pc + 4;
255 cpu_loop_exit(cs);
257 #endif