?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fdc: add disk field
[qemu/ar7.git] / hw / block / fdc.c
blob18e363bb5419e800ef161225e1d315905e183a9a
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/hw.h"
32 #include "hw/block/fdc.h"
33 #include "qemu/error-report.h"
34 #include "qemu/timer.h"
35 #include "hw/isa/isa.h"
36 #include "hw/sysbus.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/blockdev.h"
39 #include "sysemu/sysemu.h"
40 #include "qemu/log.h"
41
42 /********************************************************/
43 /* debug Floppy devices */
44 //#define DEBUG_FLOPPY
45
46 #ifdef DEBUG_FLOPPY
47 #define FLOPPY_DPRINTF(fmt, ...) \
48 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
49 #else
50 #define FLOPPY_DPRINTF(fmt, ...)
51 #endif
52
53 /********************************************************/
54 /* Floppy drive emulation */
55
56 typedef enum FDriveRate {
57 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
58 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
59 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
60 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
61 } FDriveRate;
62
63 typedef struct FDFormat {
64 FloppyDriveType drive;
65 uint8_t last_sect;
66 uint8_t max_track;
67 uint8_t max_head;
68 FDriveRate rate;
69 } FDFormat;
70
71 static const FDFormat fd_formats[] = {
72 /* First entry is default format */
73 /* 1.44 MB 3"1/2 floppy disks */
74 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, },
75 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, },
76 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
77 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
78 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
79 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
80 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
81 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
82 /* 2.88 MB 3"1/2 floppy disks */
83 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
84 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
85 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
86 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
87 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
88 /* 720 kB 3"1/2 floppy disks */
89 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, },
90 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
91 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
92 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
93 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
94 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
95 /* 1.2 MB 5"1/4 floppy disks */
96 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
97 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, },
98 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
99 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
100 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, },
101 /* 720 kB 5"1/4 floppy disks */
102 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, },
103 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
104 /* 360 kB 5"1/4 floppy disks */
105 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, },
106 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
107 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
108 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
109 /* 320 kB 5"1/4 floppy disks */
110 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
111 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
112 /* 360 kB must match 5"1/4 better than 3"1/2... */
113 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, },
114 /* end */
115 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
116 };
117
118 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
119 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
120
121 /* Will always be a fixed parameter for us */
122 #define FD_SECTOR_LEN 512
123 #define FD_SECTOR_SC 2 /* Sector size code */
124 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
125
126 typedef struct FDCtrl FDCtrl;
127
128 /* Floppy disk drive emulation */
129 typedef enum FDiskFlags {
130 FDISK_DBL_SIDES = 0x01,
131 } FDiskFlags;
132
133 typedef struct FDrive {
134 FDCtrl *fdctrl;
135 BlockBackend *blk;
136 /* Drive status */
137 FloppyDriveType drive; /* CMOS drive type */
138 uint8_t perpendicular; /* 2.88 MB access mode */
139 /* Position */
140 uint8_t head;
141 uint8_t track;
142 uint8_t sect;
143 /* Media */
144 FloppyDriveType disk; /* Current disk type */
145 FDiskFlags flags;
146 uint8_t last_sect; /* Nb sector per track */
147 uint8_t max_track; /* Nb of tracks */
148 uint16_t bps; /* Bytes per sector */
149 uint8_t ro; /* Is read-only */
150 uint8_t media_changed; /* Is media changed */
151 uint8_t media_rate; /* Data rate of medium */
152
153 bool media_inserted; /* Is there a medium in the tray */
154 } FDrive;
155
156 static void fd_init(FDrive *drv)
157 {
158 /* Drive */
159 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
160 drv->perpendicular = 0;
161 /* Disk */
162 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
163 drv->last_sect = 0;
164 drv->max_track = 0;
165 }
166
167 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
168
169 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
170 uint8_t last_sect, uint8_t num_sides)
171 {
172 return (((track * num_sides) + head) * last_sect) + sect - 1;
173 }
174
175 /* Returns current position, in sectors, for given drive */
176 static int fd_sector(FDrive *drv)
177 {
178 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
179 NUM_SIDES(drv));
180 }
181
182 /* Seek to a new position:
183 * returns 0 if already on right track
184 * returns 1 if track changed
185 * returns 2 if track is invalid
186 * returns 3 if sector is invalid
187 * returns 4 if seek is disabled
188 */
189 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
190 int enable_seek)
191 {
192 uint32_t sector;
193 int ret;
194
195 if (track > drv->max_track ||
196 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
197 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
198 head, track, sect, 1,
199 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
200 drv->max_track, drv->last_sect);
201 return 2;
202 }
203 if (sect > drv->last_sect) {
204 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
205 head, track, sect, 1,
206 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
207 drv->max_track, drv->last_sect);
208 return 3;
209 }
210 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
211 ret = 0;
212 if (sector != fd_sector(drv)) {
213 #if 0
214 if (!enable_seek) {
215 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
216 " (max=%d %02x %02x)\n",
217 head, track, sect, 1, drv->max_track,
218 drv->last_sect);
219 return 4;
220 }
221 #endif
222 drv->head = head;
223 if (drv->track != track) {
224 if (drv->media_inserted) {
225 drv->media_changed = 0;
226 }
227 ret = 1;
228 }
229 drv->track = track;
230 drv->sect = sect;
231 }
232
233 if (!drv->media_inserted) {
234 ret = 2;
235 }
236
237 return ret;
238 }
239
240 /* Set drive back to track 0 */
241 static void fd_recalibrate(FDrive *drv)
242 {
243 FLOPPY_DPRINTF("recalibrate\n");
244 fd_seek(drv, 0, 0, 1, 1);
245 }
246
247 static void pick_geometry(FDrive *drv)
248 {
249 BlockBackend *blk = drv->blk;
250 const FDFormat *parse;
251 uint64_t nb_sectors, size;
252 int i, first_match, match;
253
254 blk_get_geometry(blk, &nb_sectors);
255 match = -1;
256 first_match = -1;
257 for (i = 0; ; i++) {
258 parse = &fd_formats[i];
259 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
260 break;
261 }
262 if (drv->drive == parse->drive ||
263 drv->drive == FLOPPY_DRIVE_TYPE_NONE) {
264 size = (parse->max_head + 1) * parse->max_track *
265 parse->last_sect;
266 if (nb_sectors == size) {
267 match = i;
268 break;
269 }
270 if (first_match == -1) {
271 first_match = i;
272 }
273 }
274 }
275 if (match == -1) {
276 if (first_match == -1) {
277 match = 1;
278 } else {
279 match = first_match;
280 }
281 parse = &fd_formats[match];
282 }
283
284 if (parse->max_head == 0) {
285 drv->flags &= ~FDISK_DBL_SIDES;
286 } else {
287 drv->flags |= FDISK_DBL_SIDES;
288 }
289 drv->max_track = parse->max_track;
290 drv->last_sect = parse->last_sect;
291 drv->drive = parse->drive;
292 drv->disk = drv->media_inserted ? parse->drive : FLOPPY_DRIVE_TYPE_NONE;
293 drv->media_rate = parse->rate;
294 }
295
296 /* Revalidate a disk drive after a disk change */
297 static void fd_revalidate(FDrive *drv)
298 {
299 FLOPPY_DPRINTF("revalidate\n");
300 if (drv->blk != NULL) {
301 drv->ro = blk_is_read_only(drv->blk);
302 pick_geometry(drv);
303 if (!drv->media_inserted) {
304 FLOPPY_DPRINTF("No disk in drive\n");
305 } else {
306 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
307 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
308 drv->max_track, drv->last_sect,
309 drv->ro ? "ro" : "rw");
310 }
311 } else {
312 FLOPPY_DPRINTF("No drive connected\n");
313 drv->last_sect = 0;
314 drv->max_track = 0;
315 drv->flags &= ~FDISK_DBL_SIDES;
316 }
317 }
318
319 /********************************************************/
320 /* Intel 82078 floppy disk controller emulation */
321
322 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
323 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
324 static int fdctrl_transfer_handler (void *opaque, int nchan,
325 int dma_pos, int dma_len);
326 static void fdctrl_raise_irq(FDCtrl *fdctrl);
327 static FDrive *get_cur_drv(FDCtrl *fdctrl);
328
329 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
330 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
331 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
332 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
333 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
334 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
335 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
336 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
337 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
338 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
339 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
340 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
341
342 enum {
343 FD_DIR_WRITE = 0,
344 FD_DIR_READ = 1,
345 FD_DIR_SCANE = 2,
346 FD_DIR_SCANL = 3,
347 FD_DIR_SCANH = 4,
348 FD_DIR_VERIFY = 5,
349 };
350
351 enum {
352 FD_STATE_MULTI = 0x01, /* multi track flag */
353 FD_STATE_FORMAT = 0x02, /* format flag */
354 };
355
356 enum {
357 FD_REG_SRA = 0x00,
358 FD_REG_SRB = 0x01,
359 FD_REG_DOR = 0x02,
360 FD_REG_TDR = 0x03,
361 FD_REG_MSR = 0x04,
362 FD_REG_DSR = 0x04,
363 FD_REG_FIFO = 0x05,
364 FD_REG_DIR = 0x07,
365 FD_REG_CCR = 0x07,
366 };
367
368 enum {
369 FD_CMD_READ_TRACK = 0x02,
370 FD_CMD_SPECIFY = 0x03,
371 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
372 FD_CMD_WRITE = 0x05,
373 FD_CMD_READ = 0x06,
374 FD_CMD_RECALIBRATE = 0x07,
375 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
376 FD_CMD_WRITE_DELETED = 0x09,
377 FD_CMD_READ_ID = 0x0a,
378 FD_CMD_READ_DELETED = 0x0c,
379 FD_CMD_FORMAT_TRACK = 0x0d,
380 FD_CMD_DUMPREG = 0x0e,
381 FD_CMD_SEEK = 0x0f,
382 FD_CMD_VERSION = 0x10,
383 FD_CMD_SCAN_EQUAL = 0x11,
384 FD_CMD_PERPENDICULAR_MODE = 0x12,
385 FD_CMD_CONFIGURE = 0x13,
386 FD_CMD_LOCK = 0x14,
387 FD_CMD_VERIFY = 0x16,
388 FD_CMD_POWERDOWN_MODE = 0x17,
389 FD_CMD_PART_ID = 0x18,
390 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
391 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
392 FD_CMD_SAVE = 0x2e,
393 FD_CMD_OPTION = 0x33,
394 FD_CMD_RESTORE = 0x4e,
395 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
396 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
397 FD_CMD_FORMAT_AND_WRITE = 0xcd,
398 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
399 };
400
401 enum {
402 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
403 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
404 FD_CONFIG_POLL = 0x10, /* Poll enabled */
405 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
406 FD_CONFIG_EIS = 0x40, /* No implied seeks */
407 };
408
409 enum {
410 FD_SR0_DS0 = 0x01,
411 FD_SR0_DS1 = 0x02,
412 FD_SR0_HEAD = 0x04,
413 FD_SR0_EQPMT = 0x10,
414 FD_SR0_SEEK = 0x20,
415 FD_SR0_ABNTERM = 0x40,
416 FD_SR0_INVCMD = 0x80,
417 FD_SR0_RDYCHG = 0xc0,
418 };
419
420 enum {
421 FD_SR1_MA = 0x01, /* Missing address mark */
422 FD_SR1_NW = 0x02, /* Not writable */
423 FD_SR1_EC = 0x80, /* End of cylinder */
424 };
425
426 enum {
427 FD_SR2_SNS = 0x04, /* Scan not satisfied */
428 FD_SR2_SEH = 0x08, /* Scan equal hit */
429 };
430
431 enum {
432 FD_SRA_DIR = 0x01,
433 FD_SRA_nWP = 0x02,
434 FD_SRA_nINDX = 0x04,
435 FD_SRA_HDSEL = 0x08,
436 FD_SRA_nTRK0 = 0x10,
437 FD_SRA_STEP = 0x20,
438 FD_SRA_nDRV2 = 0x40,
439 FD_SRA_INTPEND = 0x80,
440 };
441
442 enum {
443 FD_SRB_MTR0 = 0x01,
444 FD_SRB_MTR1 = 0x02,
445 FD_SRB_WGATE = 0x04,
446 FD_SRB_RDATA = 0x08,
447 FD_SRB_WDATA = 0x10,
448 FD_SRB_DR0 = 0x20,
449 };
450
451 enum {
452 #if MAX_FD == 4
453 FD_DOR_SELMASK = 0x03,
454 #else
455 FD_DOR_SELMASK = 0x01,
456 #endif
457 FD_DOR_nRESET = 0x04,
458 FD_DOR_DMAEN = 0x08,
459 FD_DOR_MOTEN0 = 0x10,
460 FD_DOR_MOTEN1 = 0x20,
461 FD_DOR_MOTEN2 = 0x40,
462 FD_DOR_MOTEN3 = 0x80,
463 };
464
465 enum {
466 #if MAX_FD == 4
467 FD_TDR_BOOTSEL = 0x0c,
468 #else
469 FD_TDR_BOOTSEL = 0x04,
470 #endif
471 };
472
473 enum {
474 FD_DSR_DRATEMASK= 0x03,
475 FD_DSR_PWRDOWN = 0x40,
476 FD_DSR_SWRESET = 0x80,
477 };
478
479 enum {
480 FD_MSR_DRV0BUSY = 0x01,
481 FD_MSR_DRV1BUSY = 0x02,
482 FD_MSR_DRV2BUSY = 0x04,
483 FD_MSR_DRV3BUSY = 0x08,
484 FD_MSR_CMDBUSY = 0x10,
485 FD_MSR_NONDMA = 0x20,
486 FD_MSR_DIO = 0x40,
487 FD_MSR_RQM = 0x80,
488 };
489
490 enum {
491 FD_DIR_DSKCHG = 0x80,
492 };
493
494 /*
495 * See chapter 5.0 "Controller phases" of the spec:
496 *
497 * Command phase:
498 * The host writes a command and its parameters into the FIFO. The command
499 * phase is completed when all parameters for the command have been supplied,
500 * and execution phase is entered.
501 *
502 * Execution phase:
503 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
504 * contains the payload now, otherwise it's unused. When all bytes of the
505 * required data have been transferred, the state is switched to either result
506 * phase (if the command produces status bytes) or directly back into the
507 * command phase for the next command.
508 *
509 * Result phase:
510 * The host reads out the FIFO, which contains one or more result bytes now.
511 */
512 enum {
513 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
514 FD_PHASE_RECONSTRUCT = 0,
515
516 FD_PHASE_COMMAND = 1,
517 FD_PHASE_EXECUTION = 2,
518 FD_PHASE_RESULT = 3,
519 };
520
521 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
522 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
523
524 struct FDCtrl {
525 MemoryRegion iomem;
526 qemu_irq irq;
527 /* Controller state */
528 QEMUTimer *result_timer;
529 int dma_chann;
530 uint8_t phase;
531 /* Controller's identification */
532 uint8_t version;
533 /* HW */
534 uint8_t sra;
535 uint8_t srb;
536 uint8_t dor;
537 uint8_t dor_vmstate; /* only used as temp during vmstate */
538 uint8_t tdr;
539 uint8_t dsr;
540 uint8_t msr;
541 uint8_t cur_drv;
542 uint8_t status0;
543 uint8_t status1;
544 uint8_t status2;
545 /* Command FIFO */
546 uint8_t *fifo;
547 int32_t fifo_size;
548 uint32_t data_pos;
549 uint32_t data_len;
550 uint8_t data_state;
551 uint8_t data_dir;
552 uint8_t eot; /* last wanted sector */
553 /* States kept only to be returned back */
554 /* precompensation */
555 uint8_t precomp_trk;
556 uint8_t config;
557 uint8_t lock;
558 /* Power down config (also with status regB access mode */
559 uint8_t pwrd;
560 /* Floppy drives */
561 uint8_t num_floppies;
562 FDrive drives[MAX_FD];
563 int reset_sensei;
564 uint32_t check_media_rate;
565 /* Timers state */
566 uint8_t timer0;
567 uint8_t timer1;
568 };
569
570 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
571 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
572
573 typedef struct FDCtrlSysBus {
574 /*< private >*/
575 SysBusDevice parent_obj;
576 /*< public >*/
577
578 struct FDCtrl state;
579 } FDCtrlSysBus;
580
581 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
582
583 typedef struct FDCtrlISABus {
584 ISADevice parent_obj;
585
586 uint32_t iobase;
587 uint32_t irq;
588 uint32_t dma;
589 struct FDCtrl state;
590 int32_t bootindexA;
591 int32_t bootindexB;
592 } FDCtrlISABus;
593
594 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
595 {
596 FDCtrl *fdctrl = opaque;
597 uint32_t retval;
598
599 reg &= 7;
600 switch (reg) {
601 case FD_REG_SRA:
602 retval = fdctrl_read_statusA(fdctrl);
603 break;
604 case FD_REG_SRB:
605 retval = fdctrl_read_statusB(fdctrl);
606 break;
607 case FD_REG_DOR:
608 retval = fdctrl_read_dor(fdctrl);
609 break;
610 case FD_REG_TDR:
611 retval = fdctrl_read_tape(fdctrl);
612 break;
613 case FD_REG_MSR:
614 retval = fdctrl_read_main_status(fdctrl);
615 break;
616 case FD_REG_FIFO:
617 retval = fdctrl_read_data(fdctrl);
618 break;
619 case FD_REG_DIR:
620 retval = fdctrl_read_dir(fdctrl);
621 break;
622 default:
623 retval = (uint32_t)(-1);
624 break;
625 }
626 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
627
628 return retval;
629 }
630
631 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
632 {
633 FDCtrl *fdctrl = opaque;
634
635 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
636
637 reg &= 7;
638 switch (reg) {
639 case FD_REG_DOR:
640 fdctrl_write_dor(fdctrl, value);
641 break;
642 case FD_REG_TDR:
643 fdctrl_write_tape(fdctrl, value);
644 break;
645 case FD_REG_DSR:
646 fdctrl_write_rate(fdctrl, value);
647 break;
648 case FD_REG_FIFO:
649 fdctrl_write_data(fdctrl, value);
650 break;
651 case FD_REG_CCR:
652 fdctrl_write_ccr(fdctrl, value);
653 break;
654 default:
655 break;
656 }
657 }
658
659 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
660 unsigned ize)
661 {
662 return fdctrl_read(opaque, (uint32_t)reg);
663 }
664
665 static void fdctrl_write_mem (void *opaque, hwaddr reg,
666 uint64_t value, unsigned size)
667 {
668 fdctrl_write(opaque, (uint32_t)reg, value);
669 }
670
671 static const MemoryRegionOps fdctrl_mem_ops = {
672 .read = fdctrl_read_mem,
673 .write = fdctrl_write_mem,
674 .endianness = DEVICE_NATIVE_ENDIAN,
675 };
676
677 static const MemoryRegionOps fdctrl_mem_strict_ops = {
678 .read = fdctrl_read_mem,
679 .write = fdctrl_write_mem,
680 .endianness = DEVICE_NATIVE_ENDIAN,
681 .valid = {
682 .min_access_size = 1,
683 .max_access_size = 1,
684 },
685 };
686
687 static bool fdrive_media_changed_needed(void *opaque)
688 {
689 FDrive *drive = opaque;
690
691 return (drive->media_inserted && drive->media_changed != 1);
692 }
693
694 static const VMStateDescription vmstate_fdrive_media_changed = {
695 .name = "fdrive/media_changed",
696 .version_id = 1,
697 .minimum_version_id = 1,
698 .needed = fdrive_media_changed_needed,
699 .fields = (VMStateField[]) {
700 VMSTATE_UINT8(media_changed, FDrive),
701 VMSTATE_END_OF_LIST()
702 }
703 };
704
705 static bool fdrive_media_rate_needed(void *opaque)
706 {
707 FDrive *drive = opaque;
708
709 return drive->fdctrl->check_media_rate;
710 }
711
712 static const VMStateDescription vmstate_fdrive_media_rate = {
713 .name = "fdrive/media_rate",
714 .version_id = 1,
715 .minimum_version_id = 1,
716 .needed = fdrive_media_rate_needed,
717 .fields = (VMStateField[]) {
718 VMSTATE_UINT8(media_rate, FDrive),
719 VMSTATE_END_OF_LIST()
720 }
721 };
722
723 static bool fdrive_perpendicular_needed(void *opaque)
724 {
725 FDrive *drive = opaque;
726
727 return drive->perpendicular != 0;
728 }
729
730 static const VMStateDescription vmstate_fdrive_perpendicular = {
731 .name = "fdrive/perpendicular",
732 .version_id = 1,
733 .minimum_version_id = 1,
734 .needed = fdrive_perpendicular_needed,
735 .fields = (VMStateField[]) {
736 VMSTATE_UINT8(perpendicular, FDrive),
737 VMSTATE_END_OF_LIST()
738 }
739 };
740
741 static int fdrive_post_load(void *opaque, int version_id)
742 {
743 fd_revalidate(opaque);
744 return 0;
745 }
746
747 static const VMStateDescription vmstate_fdrive = {
748 .name = "fdrive",
749 .version_id = 1,
750 .minimum_version_id = 1,
751 .post_load = fdrive_post_load,
752 .fields = (VMStateField[]) {
753 VMSTATE_UINT8(head, FDrive),
754 VMSTATE_UINT8(track, FDrive),
755 VMSTATE_UINT8(sect, FDrive),
756 VMSTATE_END_OF_LIST()
757 },
758 .subsections = (const VMStateDescription*[]) {
759 &vmstate_fdrive_media_changed,
760 &vmstate_fdrive_media_rate,
761 &vmstate_fdrive_perpendicular,
762 NULL
763 }
764 };
765
766 /*
767 * Reconstructs the phase from register values according to the logic that was
768 * implemented in qemu 2.3. This is the default value that is used if the phase
769 * subsection is not present on migration.
770 *
771 * Don't change this function to reflect newer qemu versions, it is part of
772 * the migration ABI.
773 */
774 static int reconstruct_phase(FDCtrl *fdctrl)
775 {
776 if (fdctrl->msr & FD_MSR_NONDMA) {
777 return FD_PHASE_EXECUTION;
778 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
779 /* qemu 2.3 disabled RQM only during DMA transfers */
780 return FD_PHASE_EXECUTION;
781 } else if (fdctrl->msr & FD_MSR_DIO) {
782 return FD_PHASE_RESULT;
783 } else {
784 return FD_PHASE_COMMAND;
785 }
786 }
787
788 static void fdc_pre_save(void *opaque)
789 {
790 FDCtrl *s = opaque;
791
792 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
793 }
794
795 static int fdc_pre_load(void *opaque)
796 {
797 FDCtrl *s = opaque;
798 s->phase = FD_PHASE_RECONSTRUCT;
799 return 0;
800 }
801
802 static int fdc_post_load(void *opaque, int version_id)
803 {
804 FDCtrl *s = opaque;
805
806 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
807 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
808
809 if (s->phase == FD_PHASE_RECONSTRUCT) {
810 s->phase = reconstruct_phase(s);
811 }
812
813 return 0;
814 }
815
816 static bool fdc_reset_sensei_needed(void *opaque)
817 {
818 FDCtrl *s = opaque;
819
820 return s->reset_sensei != 0;
821 }
822
823 static const VMStateDescription vmstate_fdc_reset_sensei = {
824 .name = "fdc/reset_sensei",
825 .version_id = 1,
826 .minimum_version_id = 1,
827 .needed = fdc_reset_sensei_needed,
828 .fields = (VMStateField[]) {
829 VMSTATE_INT32(reset_sensei, FDCtrl),
830 VMSTATE_END_OF_LIST()
831 }
832 };
833
834 static bool fdc_result_timer_needed(void *opaque)
835 {
836 FDCtrl *s = opaque;
837
838 return timer_pending(s->result_timer);
839 }
840
841 static const VMStateDescription vmstate_fdc_result_timer = {
842 .name = "fdc/result_timer",
843 .version_id = 1,
844 .minimum_version_id = 1,
845 .needed = fdc_result_timer_needed,
846 .fields = (VMStateField[]) {
847 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
848 VMSTATE_END_OF_LIST()
849 }
850 };
851
852 static bool fdc_phase_needed(void *opaque)
853 {
854 FDCtrl *fdctrl = opaque;
855
856 return reconstruct_phase(fdctrl) != fdctrl->phase;
857 }
858
859 static const VMStateDescription vmstate_fdc_phase = {
860 .name = "fdc/phase",
861 .version_id = 1,
862 .minimum_version_id = 1,
863 .needed = fdc_phase_needed,
864 .fields = (VMStateField[]) {
865 VMSTATE_UINT8(phase, FDCtrl),
866 VMSTATE_END_OF_LIST()
867 }
868 };
869
870 static const VMStateDescription vmstate_fdc = {
871 .name = "fdc",
872 .version_id = 2,
873 .minimum_version_id = 2,
874 .pre_save = fdc_pre_save,
875 .pre_load = fdc_pre_load,
876 .post_load = fdc_post_load,
877 .fields = (VMStateField[]) {
878 /* Controller State */
879 VMSTATE_UINT8(sra, FDCtrl),
880 VMSTATE_UINT8(srb, FDCtrl),
881 VMSTATE_UINT8(dor_vmstate, FDCtrl),
882 VMSTATE_UINT8(tdr, FDCtrl),
883 VMSTATE_UINT8(dsr, FDCtrl),
884 VMSTATE_UINT8(msr, FDCtrl),
885 VMSTATE_UINT8(status0, FDCtrl),
886 VMSTATE_UINT8(status1, FDCtrl),
887 VMSTATE_UINT8(status2, FDCtrl),
888 /* Command FIFO */
889 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
890 uint8_t),
891 VMSTATE_UINT32(data_pos, FDCtrl),
892 VMSTATE_UINT32(data_len, FDCtrl),
893 VMSTATE_UINT8(data_state, FDCtrl),
894 VMSTATE_UINT8(data_dir, FDCtrl),
895 VMSTATE_UINT8(eot, FDCtrl),
896 /* States kept only to be returned back */
897 VMSTATE_UINT8(timer0, FDCtrl),
898 VMSTATE_UINT8(timer1, FDCtrl),
899 VMSTATE_UINT8(precomp_trk, FDCtrl),
900 VMSTATE_UINT8(config, FDCtrl),
901 VMSTATE_UINT8(lock, FDCtrl),
902 VMSTATE_UINT8(pwrd, FDCtrl),
903 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
904 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
905 vmstate_fdrive, FDrive),
906 VMSTATE_END_OF_LIST()
907 },
908 .subsections = (const VMStateDescription*[]) {
909 &vmstate_fdc_reset_sensei,
910 &vmstate_fdc_result_timer,
911 &vmstate_fdc_phase,
912 NULL
913 }
914 };
915
916 static void fdctrl_external_reset_sysbus(DeviceState *d)
917 {
918 FDCtrlSysBus *sys = SYSBUS_FDC(d);
919 FDCtrl *s = &sys->state;
920
921 fdctrl_reset(s, 0);
922 }
923
924 static void fdctrl_external_reset_isa(DeviceState *d)
925 {
926 FDCtrlISABus *isa = ISA_FDC(d);
927 FDCtrl *s = &isa->state;
928
929 fdctrl_reset(s, 0);
930 }
931
932 static void fdctrl_handle_tc(void *opaque, int irq, int level)
933 {
934 //FDCtrl *s = opaque;
935
936 if (level) {
937 // XXX
938 FLOPPY_DPRINTF("TC pulsed\n");
939 }
940 }
941
942 /* Change IRQ state */
943 static void fdctrl_reset_irq(FDCtrl *fdctrl)
944 {
945 fdctrl->status0 = 0;
946 if (!(fdctrl->sra & FD_SRA_INTPEND))
947 return;
948 FLOPPY_DPRINTF("Reset interrupt\n");
949 qemu_set_irq(fdctrl->irq, 0);
950 fdctrl->sra &= ~FD_SRA_INTPEND;
951 }
952
953 static void fdctrl_raise_irq(FDCtrl *fdctrl)
954 {
955 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
956 qemu_set_irq(fdctrl->irq, 1);
957 fdctrl->sra |= FD_SRA_INTPEND;
958 }
959
960 fdctrl->reset_sensei = 0;
961 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
962 }
963
964 /* Reset controller */
965 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
966 {
967 int i;
968
969 FLOPPY_DPRINTF("reset controller\n");
970 fdctrl_reset_irq(fdctrl);
971 /* Initialise controller */
972 fdctrl->sra = 0;
973 fdctrl->srb = 0xc0;
974 if (!fdctrl->drives[1].blk) {
975 fdctrl->sra |= FD_SRA_nDRV2;
976 }
977 fdctrl->cur_drv = 0;
978 fdctrl->dor = FD_DOR_nRESET;
979 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
980 fdctrl->msr = FD_MSR_RQM;
981 fdctrl->reset_sensei = 0;
982 timer_del(fdctrl->result_timer);
983 /* FIFO state */
984 fdctrl->data_pos = 0;
985 fdctrl->data_len = 0;
986 fdctrl->data_state = 0;
987 fdctrl->data_dir = FD_DIR_WRITE;
988 for (i = 0; i < MAX_FD; i++)
989 fd_recalibrate(&fdctrl->drives[i]);
990 fdctrl_to_command_phase(fdctrl);
991 if (do_irq) {
992 fdctrl->status0 |= FD_SR0_RDYCHG;
993 fdctrl_raise_irq(fdctrl);
994 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
995 }
996 }
997
998 static inline FDrive *drv0(FDCtrl *fdctrl)
999 {
1000 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1001 }
1002
1003 static inline FDrive *drv1(FDCtrl *fdctrl)
1004 {
1005 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1006 return &fdctrl->drives[1];
1007 else
1008 return &fdctrl->drives[0];
1009 }
1010
1011 #if MAX_FD == 4
1012 static inline FDrive *drv2(FDCtrl *fdctrl)
1013 {
1014 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1015 return &fdctrl->drives[2];
1016 else
1017 return &fdctrl->drives[1];
1018 }
1019
1020 static inline FDrive *drv3(FDCtrl *fdctrl)
1021 {
1022 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1023 return &fdctrl->drives[3];
1024 else
1025 return &fdctrl->drives[2];
1026 }
1027 #endif
1028
1029 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1030 {
1031 switch (fdctrl->cur_drv) {
1032 case 0: return drv0(fdctrl);
1033 case 1: return drv1(fdctrl);
1034 #if MAX_FD == 4
1035 case 2: return drv2(fdctrl);
1036 case 3: return drv3(fdctrl);
1037 #endif
1038 default: return NULL;
1039 }
1040 }
1041
1042 /* Status A register : 0x00 (read-only) */
1043 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1044 {
1045 uint32_t retval = fdctrl->sra;
1046
1047 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1048
1049 return retval;
1050 }
1051
1052 /* Status B register : 0x01 (read-only) */
1053 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1054 {
1055 uint32_t retval = fdctrl->srb;
1056
1057 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1058
1059 return retval;
1060 }
1061
1062 /* Digital output register : 0x02 */
1063 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1064 {
1065 uint32_t retval = fdctrl->dor;
1066
1067 /* Selected drive */
1068 retval |= fdctrl->cur_drv;
1069 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1070
1071 return retval;
1072 }
1073
1074 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1075 {
1076 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1077
1078 /* Motors */
1079 if (value & FD_DOR_MOTEN0)
1080 fdctrl->srb |= FD_SRB_MTR0;
1081 else
1082 fdctrl->srb &= ~FD_SRB_MTR0;
1083 if (value & FD_DOR_MOTEN1)
1084 fdctrl->srb |= FD_SRB_MTR1;
1085 else
1086 fdctrl->srb &= ~FD_SRB_MTR1;
1087
1088 /* Drive */
1089 if (value & 1)
1090 fdctrl->srb |= FD_SRB_DR0;
1091 else
1092 fdctrl->srb &= ~FD_SRB_DR0;
1093
1094 /* Reset */
1095 if (!(value & FD_DOR_nRESET)) {
1096 if (fdctrl->dor & FD_DOR_nRESET) {
1097 FLOPPY_DPRINTF("controller enter RESET state\n");
1098 }
1099 } else {
1100 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1101 FLOPPY_DPRINTF("controller out of RESET state\n");
1102 fdctrl_reset(fdctrl, 1);
1103 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1104 }
1105 }
1106 /* Selected drive */
1107 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1108
1109 fdctrl->dor = value;
1110 }
1111
1112 /* Tape drive register : 0x03 */
1113 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1114 {
1115 uint32_t retval = fdctrl->tdr;
1116
1117 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1118
1119 return retval;
1120 }
1121
1122 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1123 {
1124 /* Reset mode */
1125 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1126 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1127 return;
1128 }
1129 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1130 /* Disk boot selection indicator */
1131 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1132 /* Tape indicators: never allow */
1133 }
1134
1135 /* Main status register : 0x04 (read) */
1136 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1137 {
1138 uint32_t retval = fdctrl->msr;
1139
1140 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1141 fdctrl->dor |= FD_DOR_nRESET;
1142
1143 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1144
1145 return retval;
1146 }
1147
1148 /* Data select rate register : 0x04 (write) */
1149 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1150 {
1151 /* Reset mode */
1152 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1153 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1154 return;
1155 }
1156 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1157 /* Reset: autoclear */
1158 if (value & FD_DSR_SWRESET) {
1159 fdctrl->dor &= ~FD_DOR_nRESET;
1160 fdctrl_reset(fdctrl, 1);
1161 fdctrl->dor |= FD_DOR_nRESET;
1162 }
1163 if (value & FD_DSR_PWRDOWN) {
1164 fdctrl_reset(fdctrl, 1);
1165 }
1166 fdctrl->dsr = value;
1167 }
1168
1169 /* Configuration control register: 0x07 (write) */
1170 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1171 {
1172 /* Reset mode */
1173 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1174 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1175 return;
1176 }
1177 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1178
1179 /* Only the rate selection bits used in AT mode, and we
1180 * store those in the DSR.
1181 */
1182 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1183 (value & FD_DSR_DRATEMASK);
1184 }
1185
1186 static int fdctrl_media_changed(FDrive *drv)
1187 {
1188 return drv->media_changed;
1189 }
1190
1191 /* Digital input register : 0x07 (read-only) */
1192 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1193 {
1194 uint32_t retval = 0;
1195
1196 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1197 retval |= FD_DIR_DSKCHG;
1198 }
1199 if (retval != 0) {
1200 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1201 }
1202
1203 return retval;
1204 }
1205
1206 /* Clear the FIFO and update the state for receiving the next command */
1207 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1208 {
1209 fdctrl->phase = FD_PHASE_COMMAND;
1210 fdctrl->data_dir = FD_DIR_WRITE;
1211 fdctrl->data_pos = 0;
1212 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1213 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1214 fdctrl->msr |= FD_MSR_RQM;
1215 }
1216
1217 /* Update the state to allow the guest to read out the command status.
1218 * @fifo_len is the number of result bytes to be read out. */
1219 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1220 {
1221 fdctrl->phase = FD_PHASE_RESULT;
1222 fdctrl->data_dir = FD_DIR_READ;
1223 fdctrl->data_len = fifo_len;
1224 fdctrl->data_pos = 0;
1225 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1226 }
1227
1228 /* Set an error: unimplemented/unknown command */
1229 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1230 {
1231 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1232 fdctrl->fifo[0]);
1233 fdctrl->fifo[0] = FD_SR0_INVCMD;
1234 fdctrl_to_result_phase(fdctrl, 1);
1235 }
1236
1237 /* Seek to next sector
1238 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1239 * otherwise returns 1
1240 */
1241 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1242 {
1243 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1244 cur_drv->head, cur_drv->track, cur_drv->sect,
1245 fd_sector(cur_drv));
1246 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1247 error in fact */
1248 uint8_t new_head = cur_drv->head;
1249 uint8_t new_track = cur_drv->track;
1250 uint8_t new_sect = cur_drv->sect;
1251
1252 int ret = 1;
1253
1254 if (new_sect >= cur_drv->last_sect ||
1255 new_sect == fdctrl->eot) {
1256 new_sect = 1;
1257 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1258 if (new_head == 0 &&
1259 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1260 new_head = 1;
1261 } else {
1262 new_head = 0;
1263 new_track++;
1264 fdctrl->status0 |= FD_SR0_SEEK;
1265 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1266 ret = 0;
1267 }
1268 }
1269 } else {
1270 fdctrl->status0 |= FD_SR0_SEEK;
1271 new_track++;
1272 ret = 0;
1273 }
1274 if (ret == 1) {
1275 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1276 new_head, new_track, new_sect, fd_sector(cur_drv));
1277 }
1278 } else {
1279 new_sect++;
1280 }
1281 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1282 return ret;
1283 }
1284
1285 /* Callback for transfer end (stop or abort) */
1286 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1287 uint8_t status1, uint8_t status2)
1288 {
1289 FDrive *cur_drv;
1290 cur_drv = get_cur_drv(fdctrl);
1291
1292 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1293 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1294 if (cur_drv->head) {
1295 fdctrl->status0 |= FD_SR0_HEAD;
1296 }
1297 fdctrl->status0 |= status0;
1298
1299 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1300 status0, status1, status2, fdctrl->status0);
1301 fdctrl->fifo[0] = fdctrl->status0;
1302 fdctrl->fifo[1] = status1;
1303 fdctrl->fifo[2] = status2;
1304 fdctrl->fifo[3] = cur_drv->track;
1305 fdctrl->fifo[4] = cur_drv->head;
1306 fdctrl->fifo[5] = cur_drv->sect;
1307 fdctrl->fifo[6] = FD_SECTOR_SC;
1308 fdctrl->data_dir = FD_DIR_READ;
1309 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1310 DMA_release_DREQ(fdctrl->dma_chann);
1311 }
1312 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1313 fdctrl->msr &= ~FD_MSR_NONDMA;
1314
1315 fdctrl_to_result_phase(fdctrl, 7);
1316 fdctrl_raise_irq(fdctrl);
1317 }
1318
1319 /* Prepare a data transfer (either DMA or FIFO) */
1320 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1321 {
1322 FDrive *cur_drv;
1323 uint8_t kh, kt, ks;
1324
1325 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1326 cur_drv = get_cur_drv(fdctrl);
1327 kt = fdctrl->fifo[2];
1328 kh = fdctrl->fifo[3];
1329 ks = fdctrl->fifo[4];
1330 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1331 GET_CUR_DRV(fdctrl), kh, kt, ks,
1332 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1333 NUM_SIDES(cur_drv)));
1334 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1335 case 2:
1336 /* sect too big */
1337 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1338 fdctrl->fifo[3] = kt;
1339 fdctrl->fifo[4] = kh;
1340 fdctrl->fifo[5] = ks;
1341 return;
1342 case 3:
1343 /* track too big */
1344 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1345 fdctrl->fifo[3] = kt;
1346 fdctrl->fifo[4] = kh;
1347 fdctrl->fifo[5] = ks;
1348 return;
1349 case 4:
1350 /* No seek enabled */
1351 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1352 fdctrl->fifo[3] = kt;
1353 fdctrl->fifo[4] = kh;
1354 fdctrl->fifo[5] = ks;
1355 return;
1356 case 1:
1357 fdctrl->status0 |= FD_SR0_SEEK;
1358 break;
1359 default:
1360 break;
1361 }
1362
1363 /* Check the data rate. If the programmed data rate does not match
1364 * the currently inserted medium, the operation has to fail. */
1365 if (fdctrl->check_media_rate &&
1366 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1367 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1368 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1369 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1370 fdctrl->fifo[3] = kt;
1371 fdctrl->fifo[4] = kh;
1372 fdctrl->fifo[5] = ks;
1373 return;
1374 }
1375
1376 /* Set the FIFO state */
1377 fdctrl->data_dir = direction;
1378 fdctrl->data_pos = 0;
1379 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1380 if (fdctrl->fifo[0] & 0x80)
1381 fdctrl->data_state |= FD_STATE_MULTI;
1382 else
1383 fdctrl->data_state &= ~FD_STATE_MULTI;
1384 if (fdctrl->fifo[5] == 0) {
1385 fdctrl->data_len = fdctrl->fifo[8];
1386 } else {
1387 int tmp;
1388 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1389 tmp = (fdctrl->fifo[6] - ks + 1);
1390 if (fdctrl->fifo[0] & 0x80)
1391 tmp += fdctrl->fifo[6];
1392 fdctrl->data_len *= tmp;
1393 }
1394 fdctrl->eot = fdctrl->fifo[6];
1395 if (fdctrl->dor & FD_DOR_DMAEN) {
1396 int dma_mode;
1397 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1398 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1399 dma_mode = (dma_mode >> 2) & 3;
1400 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1401 dma_mode, direction,
1402 (128 << fdctrl->fifo[5]) *
1403 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1404 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1405 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1406 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1407 (direction == FD_DIR_READ && dma_mode == 1) ||
1408 (direction == FD_DIR_VERIFY)) {
1409 /* No access is allowed until DMA transfer has completed */
1410 fdctrl->msr &= ~FD_MSR_RQM;
1411 if (direction != FD_DIR_VERIFY) {
1412 /* Now, we just have to wait for the DMA controller to
1413 * recall us...
1414 */
1415 DMA_hold_DREQ(fdctrl->dma_chann);
1416 DMA_schedule();
1417 } else {
1418 /* Start transfer */
1419 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1420 fdctrl->data_len);
1421 }
1422 return;
1423 } else {
1424 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1425 direction);
1426 }
1427 }
1428 FLOPPY_DPRINTF("start non-DMA transfer\n");
1429 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1430 if (direction != FD_DIR_WRITE)
1431 fdctrl->msr |= FD_MSR_DIO;
1432 /* IO based transfer: calculate len */
1433 fdctrl_raise_irq(fdctrl);
1434 }
1435
1436 /* Prepare a transfer of deleted data */
1437 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1438 {
1439 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1440
1441 /* We don't handle deleted data,
1442 * so we don't return *ANYTHING*
1443 */
1444 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1445 }
1446
1447 /* handlers for DMA transfers */
1448 static int fdctrl_transfer_handler (void *opaque, int nchan,
1449 int dma_pos, int dma_len)
1450 {
1451 FDCtrl *fdctrl;
1452 FDrive *cur_drv;
1453 int len, start_pos, rel_pos;
1454 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1455
1456 fdctrl = opaque;
1457 if (fdctrl->msr & FD_MSR_RQM) {
1458 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1459 return 0;
1460 }
1461 cur_drv = get_cur_drv(fdctrl);
1462 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1463 fdctrl->data_dir == FD_DIR_SCANH)
1464 status2 = FD_SR2_SNS;
1465 if (dma_len > fdctrl->data_len)
1466 dma_len = fdctrl->data_len;
1467 if (cur_drv->blk == NULL) {
1468 if (fdctrl->data_dir == FD_DIR_WRITE)
1469 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1470 else
1471 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1472 len = 0;
1473 goto transfer_error;
1474 }
1475 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1476 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1477 len = dma_len - fdctrl->data_pos;
1478 if (len + rel_pos > FD_SECTOR_LEN)
1479 len = FD_SECTOR_LEN - rel_pos;
1480 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1481 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1482 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1483 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1484 fd_sector(cur_drv) * FD_SECTOR_LEN);
1485 if (fdctrl->data_dir != FD_DIR_WRITE ||
1486 len < FD_SECTOR_LEN || rel_pos != 0) {
1487 /* READ & SCAN commands and realign to a sector for WRITE */
1488 if (blk_read(cur_drv->blk, fd_sector(cur_drv),
1489 fdctrl->fifo, 1) < 0) {
1490 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1491 fd_sector(cur_drv));
1492 /* Sure, image size is too small... */
1493 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1494 }
1495 }
1496 switch (fdctrl->data_dir) {
1497 case FD_DIR_READ:
1498 /* READ commands */
1499 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1500 fdctrl->data_pos, len);
1501 break;
1502 case FD_DIR_WRITE:
1503 /* WRITE commands */
1504 if (cur_drv->ro) {
1505 /* Handle readonly medium early, no need to do DMA, touch the
1506 * LED or attempt any writes. A real floppy doesn't attempt
1507 * to write to readonly media either. */
1508 fdctrl_stop_transfer(fdctrl,
1509 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1510 0x00);
1511 goto transfer_error;
1512 }
1513
1514 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1515 fdctrl->data_pos, len);
1516 if (blk_write(cur_drv->blk, fd_sector(cur_drv),
1517 fdctrl->fifo, 1) < 0) {
1518 FLOPPY_DPRINTF("error writing sector %d\n",
1519 fd_sector(cur_drv));
1520 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1521 goto transfer_error;
1522 }
1523 break;
1524 case FD_DIR_VERIFY:
1525 /* VERIFY commands */
1526 break;
1527 default:
1528 /* SCAN commands */
1529 {
1530 uint8_t tmpbuf[FD_SECTOR_LEN];
1531 int ret;
1532 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1533 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1534 if (ret == 0) {
1535 status2 = FD_SR2_SEH;
1536 goto end_transfer;
1537 }
1538 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1539 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1540 status2 = 0x00;
1541 goto end_transfer;
1542 }
1543 }
1544 break;
1545 }
1546 fdctrl->data_pos += len;
1547 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1548 if (rel_pos == 0) {
1549 /* Seek to next sector */
1550 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1551 break;
1552 }
1553 }
1554 end_transfer:
1555 len = fdctrl->data_pos - start_pos;
1556 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1557 fdctrl->data_pos, len, fdctrl->data_len);
1558 if (fdctrl->data_dir == FD_DIR_SCANE ||
1559 fdctrl->data_dir == FD_DIR_SCANL ||
1560 fdctrl->data_dir == FD_DIR_SCANH)
1561 status2 = FD_SR2_SEH;
1562 fdctrl->data_len -= len;
1563 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1564 transfer_error:
1565
1566 return len;
1567 }
1568
1569 /* Data register : 0x05 */
1570 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1571 {
1572 FDrive *cur_drv;
1573 uint32_t retval = 0;
1574 uint32_t pos;
1575
1576 cur_drv = get_cur_drv(fdctrl);
1577 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1578 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1579 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1580 return 0;
1581 }
1582
1583 /* If data_len spans multiple sectors, the current position in the FIFO
1584 * wraps around while fdctrl->data_pos is the real position in the whole
1585 * request. */
1586 pos = fdctrl->data_pos;
1587 pos %= FD_SECTOR_LEN;
1588
1589 switch (fdctrl->phase) {
1590 case FD_PHASE_EXECUTION:
1591 assert(fdctrl->msr & FD_MSR_NONDMA);
1592 if (pos == 0) {
1593 if (fdctrl->data_pos != 0)
1594 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1595 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1596 fd_sector(cur_drv));
1597 return 0;
1598 }
1599 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1600 < 0) {
1601 FLOPPY_DPRINTF("error getting sector %d\n",
1602 fd_sector(cur_drv));
1603 /* Sure, image size is too small... */
1604 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1605 }
1606 }
1607
1608 if (++fdctrl->data_pos == fdctrl->data_len) {
1609 fdctrl->msr &= ~FD_MSR_RQM;
1610 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1611 }
1612 break;
1613
1614 case FD_PHASE_RESULT:
1615 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1616 if (++fdctrl->data_pos == fdctrl->data_len) {
1617 fdctrl->msr &= ~FD_MSR_RQM;
1618 fdctrl_to_command_phase(fdctrl);
1619 fdctrl_reset_irq(fdctrl);
1620 }
1621 break;
1622
1623 case FD_PHASE_COMMAND:
1624 default:
1625 abort();
1626 }
1627
1628 retval = fdctrl->fifo[pos];
1629 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1630
1631 return retval;
1632 }
1633
1634 static void fdctrl_format_sector(FDCtrl *fdctrl)
1635 {
1636 FDrive *cur_drv;
1637 uint8_t kh, kt, ks;
1638
1639 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1640 cur_drv = get_cur_drv(fdctrl);
1641 kt = fdctrl->fifo[6];
1642 kh = fdctrl->fifo[7];
1643 ks = fdctrl->fifo[8];
1644 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1645 GET_CUR_DRV(fdctrl), kh, kt, ks,
1646 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1647 NUM_SIDES(cur_drv)));
1648 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1649 case 2:
1650 /* sect too big */
1651 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1652 fdctrl->fifo[3] = kt;
1653 fdctrl->fifo[4] = kh;
1654 fdctrl->fifo[5] = ks;
1655 return;
1656 case 3:
1657 /* track too big */
1658 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1659 fdctrl->fifo[3] = kt;
1660 fdctrl->fifo[4] = kh;
1661 fdctrl->fifo[5] = ks;
1662 return;
1663 case 4:
1664 /* No seek enabled */
1665 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1666 fdctrl->fifo[3] = kt;
1667 fdctrl->fifo[4] = kh;
1668 fdctrl->fifo[5] = ks;
1669 return;
1670 case 1:
1671 fdctrl->status0 |= FD_SR0_SEEK;
1672 break;
1673 default:
1674 break;
1675 }
1676 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1677 if (cur_drv->blk == NULL ||
1678 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1679 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1680 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1681 } else {
1682 if (cur_drv->sect == cur_drv->last_sect) {
1683 fdctrl->data_state &= ~FD_STATE_FORMAT;
1684 /* Last sector done */
1685 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1686 } else {
1687 /* More to do */
1688 fdctrl->data_pos = 0;
1689 fdctrl->data_len = 4;
1690 }
1691 }
1692 }
1693
1694 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1695 {
1696 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1697 fdctrl->fifo[0] = fdctrl->lock << 4;
1698 fdctrl_to_result_phase(fdctrl, 1);
1699 }
1700
1701 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1702 {
1703 FDrive *cur_drv = get_cur_drv(fdctrl);
1704
1705 /* Drives position */
1706 fdctrl->fifo[0] = drv0(fdctrl)->track;
1707 fdctrl->fifo[1] = drv1(fdctrl)->track;
1708 #if MAX_FD == 4
1709 fdctrl->fifo[2] = drv2(fdctrl)->track;
1710 fdctrl->fifo[3] = drv3(fdctrl)->track;
1711 #else
1712 fdctrl->fifo[2] = 0;
1713 fdctrl->fifo[3] = 0;
1714 #endif
1715 /* timers */
1716 fdctrl->fifo[4] = fdctrl->timer0;
1717 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1718 fdctrl->fifo[6] = cur_drv->last_sect;
1719 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1720 (cur_drv->perpendicular << 2);
1721 fdctrl->fifo[8] = fdctrl->config;
1722 fdctrl->fifo[9] = fdctrl->precomp_trk;
1723 fdctrl_to_result_phase(fdctrl, 10);
1724 }
1725
1726 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1727 {
1728 /* Controller's version */
1729 fdctrl->fifo[0] = fdctrl->version;
1730 fdctrl_to_result_phase(fdctrl, 1);
1731 }
1732
1733 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1734 {
1735 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1736 fdctrl_to_result_phase(fdctrl, 1);
1737 }
1738
1739 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1740 {
1741 FDrive *cur_drv = get_cur_drv(fdctrl);
1742
1743 /* Drives position */
1744 drv0(fdctrl)->track = fdctrl->fifo[3];
1745 drv1(fdctrl)->track = fdctrl->fifo[4];
1746 #if MAX_FD == 4
1747 drv2(fdctrl)->track = fdctrl->fifo[5];
1748 drv3(fdctrl)->track = fdctrl->fifo[6];
1749 #endif
1750 /* timers */
1751 fdctrl->timer0 = fdctrl->fifo[7];
1752 fdctrl->timer1 = fdctrl->fifo[8];
1753 cur_drv->last_sect = fdctrl->fifo[9];
1754 fdctrl->lock = fdctrl->fifo[10] >> 7;
1755 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1756 fdctrl->config = fdctrl->fifo[11];
1757 fdctrl->precomp_trk = fdctrl->fifo[12];
1758 fdctrl->pwrd = fdctrl->fifo[13];
1759 fdctrl_to_command_phase(fdctrl);
1760 }
1761
1762 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1763 {
1764 FDrive *cur_drv = get_cur_drv(fdctrl);
1765
1766 fdctrl->fifo[0] = 0;
1767 fdctrl->fifo[1] = 0;
1768 /* Drives position */
1769 fdctrl->fifo[2] = drv0(fdctrl)->track;
1770 fdctrl->fifo[3] = drv1(fdctrl)->track;
1771 #if MAX_FD == 4
1772 fdctrl->fifo[4] = drv2(fdctrl)->track;
1773 fdctrl->fifo[5] = drv3(fdctrl)->track;
1774 #else
1775 fdctrl->fifo[4] = 0;
1776 fdctrl->fifo[5] = 0;
1777 #endif
1778 /* timers */
1779 fdctrl->fifo[6] = fdctrl->timer0;
1780 fdctrl->fifo[7] = fdctrl->timer1;
1781 fdctrl->fifo[8] = cur_drv->last_sect;
1782 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1783 (cur_drv->perpendicular << 2);
1784 fdctrl->fifo[10] = fdctrl->config;
1785 fdctrl->fifo[11] = fdctrl->precomp_trk;
1786 fdctrl->fifo[12] = fdctrl->pwrd;
1787 fdctrl->fifo[13] = 0;
1788 fdctrl->fifo[14] = 0;
1789 fdctrl_to_result_phase(fdctrl, 15);
1790 }
1791
1792 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1793 {
1794 FDrive *cur_drv = get_cur_drv(fdctrl);
1795
1796 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1797 timer_mod(fdctrl->result_timer,
1798 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
1799 }
1800
1801 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1802 {
1803 FDrive *cur_drv;
1804
1805 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1806 cur_drv = get_cur_drv(fdctrl);
1807 fdctrl->data_state |= FD_STATE_FORMAT;
1808 if (fdctrl->fifo[0] & 0x80)
1809 fdctrl->data_state |= FD_STATE_MULTI;
1810 else
1811 fdctrl->data_state &= ~FD_STATE_MULTI;
1812 cur_drv->bps =
1813 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1814 #if 0
1815 cur_drv->last_sect =
1816 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1817 fdctrl->fifo[3] / 2;
1818 #else
1819 cur_drv->last_sect = fdctrl->fifo[3];
1820 #endif
1821 /* TODO: implement format using DMA expected by the Bochs BIOS
1822 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1823 * the sector with the specified fill byte
1824 */
1825 fdctrl->data_state &= ~FD_STATE_FORMAT;
1826 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1827 }
1828
1829 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1830 {
1831 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1832 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1833 if (fdctrl->fifo[2] & 1)
1834 fdctrl->dor &= ~FD_DOR_DMAEN;
1835 else
1836 fdctrl->dor |= FD_DOR_DMAEN;
1837 /* No result back */
1838 fdctrl_to_command_phase(fdctrl);
1839 }
1840
1841 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1842 {
1843 FDrive *cur_drv;
1844
1845 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1846 cur_drv = get_cur_drv(fdctrl);
1847 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1848 /* 1 Byte status back */
1849 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1850 (cur_drv->track == 0 ? 0x10 : 0x00) |
1851 (cur_drv->head << 2) |
1852 GET_CUR_DRV(fdctrl) |
1853 0x28;
1854 fdctrl_to_result_phase(fdctrl, 1);
1855 }
1856
1857 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1858 {
1859 FDrive *cur_drv;
1860
1861 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1862 cur_drv = get_cur_drv(fdctrl);
1863 fd_recalibrate(cur_drv);
1864 fdctrl_to_command_phase(fdctrl);
1865 /* Raise Interrupt */
1866 fdctrl->status0 |= FD_SR0_SEEK;
1867 fdctrl_raise_irq(fdctrl);
1868 }
1869
1870 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1871 {
1872 FDrive *cur_drv = get_cur_drv(fdctrl);
1873
1874 if (fdctrl->reset_sensei > 0) {
1875 fdctrl->fifo[0] =
1876 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1877 fdctrl->reset_sensei--;
1878 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1879 fdctrl->fifo[0] = FD_SR0_INVCMD;
1880 fdctrl_to_result_phase(fdctrl, 1);
1881 return;
1882 } else {
1883 fdctrl->fifo[0] =
1884 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1885 | GET_CUR_DRV(fdctrl);
1886 }
1887
1888 fdctrl->fifo[1] = cur_drv->track;
1889 fdctrl_to_result_phase(fdctrl, 2);
1890 fdctrl_reset_irq(fdctrl);
1891 fdctrl->status0 = FD_SR0_RDYCHG;
1892 }
1893
1894 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1895 {
1896 FDrive *cur_drv;
1897
1898 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1899 cur_drv = get_cur_drv(fdctrl);
1900 fdctrl_to_command_phase(fdctrl);
1901 /* The seek command just sends step pulses to the drive and doesn't care if
1902 * there is a medium inserted of if it's banging the head against the drive.
1903 */
1904 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1905 /* Raise Interrupt */
1906 fdctrl->status0 |= FD_SR0_SEEK;
1907 fdctrl_raise_irq(fdctrl);
1908 }
1909
1910 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1911 {
1912 FDrive *cur_drv = get_cur_drv(fdctrl);
1913
1914 if (fdctrl->fifo[1] & 0x80)
1915 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1916 /* No result back */
1917 fdctrl_to_command_phase(fdctrl);
1918 }
1919
1920 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1921 {
1922 fdctrl->config = fdctrl->fifo[2];
1923 fdctrl->precomp_trk = fdctrl->fifo[3];
1924 /* No result back */
1925 fdctrl_to_command_phase(fdctrl);
1926 }
1927
1928 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1929 {
1930 fdctrl->pwrd = fdctrl->fifo[1];
1931 fdctrl->fifo[0] = fdctrl->fifo[1];
1932 fdctrl_to_result_phase(fdctrl, 1);
1933 }
1934
1935 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1936 {
1937 /* No result back */
1938 fdctrl_to_command_phase(fdctrl);
1939 }
1940
1941 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1942 {
1943 FDrive *cur_drv = get_cur_drv(fdctrl);
1944 uint32_t pos;
1945
1946 pos = fdctrl->data_pos - 1;
1947 pos %= FD_SECTOR_LEN;
1948 if (fdctrl->fifo[pos] & 0x80) {
1949 /* Command parameters done */
1950 if (fdctrl->fifo[pos] & 0x40) {
1951 fdctrl->fifo[0] = fdctrl->fifo[1];
1952 fdctrl->fifo[2] = 0;
1953 fdctrl->fifo[3] = 0;
1954 fdctrl_to_result_phase(fdctrl, 4);
1955 } else {
1956 fdctrl_to_command_phase(fdctrl);
1957 }
1958 } else if (fdctrl->data_len > 7) {
1959 /* ERROR */
1960 fdctrl->fifo[0] = 0x80 |
1961 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1962 fdctrl_to_result_phase(fdctrl, 1);
1963 }
1964 }
1965
1966 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1967 {
1968 FDrive *cur_drv;
1969
1970 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1971 cur_drv = get_cur_drv(fdctrl);
1972 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1973 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1974 cur_drv->sect, 1);
1975 } else {
1976 fd_seek(cur_drv, cur_drv->head,
1977 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
1978 }
1979 fdctrl_to_command_phase(fdctrl);
1980 /* Raise Interrupt */
1981 fdctrl->status0 |= FD_SR0_SEEK;
1982 fdctrl_raise_irq(fdctrl);
1983 }
1984
1985 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1986 {
1987 FDrive *cur_drv;
1988
1989 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1990 cur_drv = get_cur_drv(fdctrl);
1991 if (fdctrl->fifo[2] > cur_drv->track) {
1992 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1993 } else {
1994 fd_seek(cur_drv, cur_drv->head,
1995 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
1996 }
1997 fdctrl_to_command_phase(fdctrl);
1998 /* Raise Interrupt */
1999 fdctrl->status0 |= FD_SR0_SEEK;
2000 fdctrl_raise_irq(fdctrl);
2001 }
2002
2003 /*
2004 * Handlers for the execution phase of each command
2005 */
2006 typedef struct FDCtrlCommand {
2007 uint8_t value;
2008 uint8_t mask;
2009 const char* name;
2010 int parameters;
2011 void (*handler)(FDCtrl *fdctrl, int direction);
2012 int direction;
2013 } FDCtrlCommand;
2014
2015 static const FDCtrlCommand handlers[] = {
2016 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2017 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2018 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2019 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2020 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2021 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2022 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2023 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2024 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2025 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2026 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2027 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2028 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2029 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2030 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2031 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2032 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2033 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2034 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2035 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2036 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2037 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2038 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2039 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2040 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2041 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2042 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2043 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2044 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2045 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2046 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2047 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2048 };
2049 /* Associate command to an index in the 'handlers' array */
2050 static uint8_t command_to_handler[256];
2051
2052 static const FDCtrlCommand *get_command(uint8_t cmd)
2053 {
2054 int idx;
2055
2056 idx = command_to_handler[cmd];
2057 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2058 return &handlers[idx];
2059 }
2060
2061 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2062 {
2063 FDrive *cur_drv;
2064 const FDCtrlCommand *cmd;
2065 uint32_t pos;
2066
2067 /* Reset mode */
2068 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2069 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2070 return;
2071 }
2072 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2073 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2074 return;
2075 }
2076 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2077
2078 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2079
2080 /* If data_len spans multiple sectors, the current position in the FIFO
2081 * wraps around while fdctrl->data_pos is the real position in the whole
2082 * request. */
2083 pos = fdctrl->data_pos++;
2084 pos %= FD_SECTOR_LEN;
2085 fdctrl->fifo[pos] = value;
2086
2087 if (fdctrl->data_pos == fdctrl->data_len) {
2088 fdctrl->msr &= ~FD_MSR_RQM;
2089 }
2090
2091 switch (fdctrl->phase) {
2092 case FD_PHASE_EXECUTION:
2093 /* For DMA requests, RQM should be cleared during execution phase, so
2094 * we would have errored out above. */
2095 assert(fdctrl->msr & FD_MSR_NONDMA);
2096
2097 /* FIFO data write */
2098 if (pos == FD_SECTOR_LEN - 1 ||
2099 fdctrl->data_pos == fdctrl->data_len) {
2100 cur_drv = get_cur_drv(fdctrl);
2101 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
2102 < 0) {
2103 FLOPPY_DPRINTF("error writing sector %d\n",
2104 fd_sector(cur_drv));
2105 break;
2106 }
2107 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2108 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2109 fd_sector(cur_drv));
2110 break;
2111 }
2112 }
2113
2114 /* Switch to result phase when done with the transfer */
2115 if (fdctrl->data_pos == fdctrl->data_len) {
2116 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2117 }
2118 break;
2119
2120 case FD_PHASE_COMMAND:
2121 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2122 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2123
2124 if (pos == 0) {
2125 /* The first byte specifies the command. Now we start reading
2126 * as many parameters as this command requires. */
2127 cmd = get_command(value);
2128 fdctrl->data_len = cmd->parameters + 1;
2129 if (cmd->parameters) {
2130 fdctrl->msr |= FD_MSR_RQM;
2131 }
2132 fdctrl->msr |= FD_MSR_CMDBUSY;
2133 }
2134
2135 if (fdctrl->data_pos == fdctrl->data_len) {
2136 /* We have all parameters now, execute the command */
2137 fdctrl->phase = FD_PHASE_EXECUTION;
2138
2139 if (fdctrl->data_state & FD_STATE_FORMAT) {
2140 fdctrl_format_sector(fdctrl);
2141 break;
2142 }
2143
2144 cmd = get_command(fdctrl->fifo[0]);
2145 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2146 cmd->handler(fdctrl, cmd->direction);
2147 }
2148 break;
2149
2150 case FD_PHASE_RESULT:
2151 default:
2152 abort();
2153 }
2154 }
2155
2156 static void fdctrl_result_timer(void *opaque)
2157 {
2158 FDCtrl *fdctrl = opaque;
2159 FDrive *cur_drv = get_cur_drv(fdctrl);
2160
2161 /* Pretend we are spinning.
2162 * This is needed for Coherent, which uses READ ID to check for
2163 * sector interleaving.
2164 */
2165 if (cur_drv->last_sect != 0) {
2166 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2167 }
2168 /* READ_ID can't automatically succeed! */
2169 if (fdctrl->check_media_rate &&
2170 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2171 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2172 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2173 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2174 } else {
2175 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2176 }
2177 }
2178
2179 static void fdctrl_change_cb(void *opaque, bool load)
2180 {
2181 FDrive *drive = opaque;
2182
2183 drive->media_inserted = load && drive->blk && blk_is_inserted(drive->blk);
2184
2185 drive->media_changed = 1;
2186 fd_revalidate(drive);
2187 }
2188
2189 static bool fdctrl_is_tray_open(void *opaque)
2190 {
2191 FDrive *drive = opaque;
2192 return !drive->media_inserted;
2193 }
2194
2195 static const BlockDevOps fdctrl_block_ops = {
2196 .change_media_cb = fdctrl_change_cb,
2197 .is_tray_open = fdctrl_is_tray_open,
2198 };
2199
2200 /* Init functions */
2201 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
2202 {
2203 unsigned int i;
2204 FDrive *drive;
2205
2206 for (i = 0; i < MAX_FD; i++) {
2207 drive = &fdctrl->drives[i];
2208 drive->fdctrl = fdctrl;
2209
2210 if (drive->blk) {
2211 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2212 error_setg(errp, "fdc doesn't support drive option werror");
2213 return;
2214 }
2215 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2216 error_setg(errp, "fdc doesn't support drive option rerror");
2217 return;
2218 }
2219 }
2220
2221 fd_init(drive);
2222 fdctrl_change_cb(drive, 0);
2223 if (drive->blk) {
2224 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2225 drive->media_inserted = blk_is_inserted(drive->blk);
2226 }
2227 }
2228 }
2229
2230 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2231 {
2232 DeviceState *dev;
2233 ISADevice *isadev;
2234
2235 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2236 if (!isadev) {
2237 return NULL;
2238 }
2239 dev = DEVICE(isadev);
2240
2241 if (fds[0]) {
2242 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2243 &error_fatal);
2244 }
2245 if (fds[1]) {
2246 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2247 &error_fatal);
2248 }
2249 qdev_init_nofail(dev);
2250
2251 return isadev;
2252 }
2253
2254 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2255 hwaddr mmio_base, DriveInfo **fds)
2256 {
2257 FDCtrl *fdctrl;
2258 DeviceState *dev;
2259 SysBusDevice *sbd;
2260 FDCtrlSysBus *sys;
2261
2262 dev = qdev_create(NULL, "sysbus-fdc");
2263 sys = SYSBUS_FDC(dev);
2264 fdctrl = &sys->state;
2265 fdctrl->dma_chann = dma_chann; /* FIXME */
2266 if (fds[0]) {
2267 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2268 &error_fatal);
2269 }
2270 if (fds[1]) {
2271 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2272 &error_fatal);
2273 }
2274 qdev_init_nofail(dev);
2275 sbd = SYS_BUS_DEVICE(dev);
2276 sysbus_connect_irq(sbd, 0, irq);
2277 sysbus_mmio_map(sbd, 0, mmio_base);
2278 }
2279
2280 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2281 DriveInfo **fds, qemu_irq *fdc_tc)
2282 {
2283 DeviceState *dev;
2284 FDCtrlSysBus *sys;
2285
2286 dev = qdev_create(NULL, "SUNW,fdtwo");
2287 if (fds[0]) {
2288 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2289 &error_fatal);
2290 }
2291 qdev_init_nofail(dev);
2292 sys = SYSBUS_FDC(dev);
2293 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2294 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2295 *fdc_tc = qdev_get_gpio_in(dev, 0);
2296 }
2297
2298 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
2299 {
2300 int i, j;
2301 static int command_tables_inited = 0;
2302
2303 /* Fill 'command_to_handler' lookup table */
2304 if (!command_tables_inited) {
2305 command_tables_inited = 1;
2306 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2307 for (j = 0; j < sizeof(command_to_handler); j++) {
2308 if ((j & handlers[i].mask) == handlers[i].value) {
2309 command_to_handler[j] = i;
2310 }
2311 }
2312 }
2313 }
2314
2315 FLOPPY_DPRINTF("init controller\n");
2316 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2317 fdctrl->fifo_size = 512;
2318 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2319 fdctrl_result_timer, fdctrl);
2320
2321 fdctrl->version = 0x90; /* Intel 82078 controller */
2322 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2323 fdctrl->num_floppies = MAX_FD;
2324
2325 if (fdctrl->dma_chann != -1) {
2326 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2327 }
2328 fdctrl_connect_drives(fdctrl, errp);
2329 }
2330
2331 static const MemoryRegionPortio fdc_portio_list[] = {
2332 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2333 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2334 PORTIO_END_OF_LIST(),
2335 };
2336
2337 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2338 {
2339 ISADevice *isadev = ISA_DEVICE(dev);
2340 FDCtrlISABus *isa = ISA_FDC(dev);
2341 FDCtrl *fdctrl = &isa->state;
2342 Error *err = NULL;
2343
2344 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2345 "fdc");
2346
2347 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2348 fdctrl->dma_chann = isa->dma;
2349
2350 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2351 fdctrl_realize_common(fdctrl, &err);
2352 if (err != NULL) {
2353 error_propagate(errp, err);
2354 return;
2355 }
2356 }
2357
2358 static void sysbus_fdc_initfn(Object *obj)
2359 {
2360 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2361 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2362 FDCtrl *fdctrl = &sys->state;
2363
2364 fdctrl->dma_chann = -1;
2365
2366 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2367 "fdc", 0x08);
2368 sysbus_init_mmio(sbd, &fdctrl->iomem);
2369 }
2370
2371 static void sun4m_fdc_initfn(Object *obj)
2372 {
2373 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2374 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2375 FDCtrl *fdctrl = &sys->state;
2376
2377 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2378 fdctrl, "fdctrl", 0x08);
2379 sysbus_init_mmio(sbd, &fdctrl->iomem);
2380 }
2381
2382 static void sysbus_fdc_common_initfn(Object *obj)
2383 {
2384 DeviceState *dev = DEVICE(obj);
2385 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2386 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2387 FDCtrl *fdctrl = &sys->state;
2388
2389 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2390
2391 sysbus_init_irq(sbd, &fdctrl->irq);
2392 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2393 }
2394
2395 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2396 {
2397 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2398 FDCtrl *fdctrl = &sys->state;
2399
2400 fdctrl_realize_common(fdctrl, errp);
2401 }
2402
2403 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2404 {
2405 FDCtrlISABus *isa = ISA_FDC(fdc);
2406
2407 return isa->state.drives[i].drive;
2408 }
2409
2410 static const VMStateDescription vmstate_isa_fdc ={
2411 .name = "fdc",
2412 .version_id = 2,
2413 .minimum_version_id = 2,
2414 .fields = (VMStateField[]) {
2415 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2416 VMSTATE_END_OF_LIST()
2417 }
2418 };
2419
2420 static Property isa_fdc_properties[] = {
2421 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2422 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2423 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2424 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2425 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
2426 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2427 0, true),
2428 DEFINE_PROP_END_OF_LIST(),
2429 };
2430
2431 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2432 {
2433 DeviceClass *dc = DEVICE_CLASS(klass);
2434
2435 dc->realize = isabus_fdc_realize;
2436 dc->fw_name = "fdc";
2437 dc->reset = fdctrl_external_reset_isa;
2438 dc->vmsd = &vmstate_isa_fdc;
2439 dc->props = isa_fdc_properties;
2440 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2441 }
2442
2443 static void isabus_fdc_instance_init(Object *obj)
2444 {
2445 FDCtrlISABus *isa = ISA_FDC(obj);
2446
2447 device_add_bootindex_property(obj, &isa->bootindexA,
2448 "bootindexA", "/floppy@0",
2449 DEVICE(obj), NULL);
2450 device_add_bootindex_property(obj, &isa->bootindexB,
2451 "bootindexB", "/floppy@1",
2452 DEVICE(obj), NULL);
2453 }
2454
2455 static const TypeInfo isa_fdc_info = {
2456 .name = TYPE_ISA_FDC,
2457 .parent = TYPE_ISA_DEVICE,
2458 .instance_size = sizeof(FDCtrlISABus),
2459 .class_init = isabus_fdc_class_init,
2460 .instance_init = isabus_fdc_instance_init,
2461 };
2462
2463 static const VMStateDescription vmstate_sysbus_fdc ={
2464 .name = "fdc",
2465 .version_id = 2,
2466 .minimum_version_id = 2,
2467 .fields = (VMStateField[]) {
2468 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2469 VMSTATE_END_OF_LIST()
2470 }
2471 };
2472
2473 static Property sysbus_fdc_properties[] = {
2474 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2475 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
2476 DEFINE_PROP_END_OF_LIST(),
2477 };
2478
2479 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2480 {
2481 DeviceClass *dc = DEVICE_CLASS(klass);
2482
2483 dc->props = sysbus_fdc_properties;
2484 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2485 }
2486
2487 static const TypeInfo sysbus_fdc_info = {
2488 .name = "sysbus-fdc",
2489 .parent = TYPE_SYSBUS_FDC,
2490 .instance_init = sysbus_fdc_initfn,
2491 .class_init = sysbus_fdc_class_init,
2492 };
2493
2494 static Property sun4m_fdc_properties[] = {
2495 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
2496 DEFINE_PROP_END_OF_LIST(),
2497 };
2498
2499 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2500 {
2501 DeviceClass *dc = DEVICE_CLASS(klass);
2502
2503 dc->props = sun4m_fdc_properties;
2504 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2505 }
2506
2507 static const TypeInfo sun4m_fdc_info = {
2508 .name = "SUNW,fdtwo",
2509 .parent = TYPE_SYSBUS_FDC,
2510 .instance_init = sun4m_fdc_initfn,
2511 .class_init = sun4m_fdc_class_init,
2512 };
2513
2514 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2515 {
2516 DeviceClass *dc = DEVICE_CLASS(klass);
2517
2518 dc->realize = sysbus_fdc_common_realize;
2519 dc->reset = fdctrl_external_reset_sysbus;
2520 dc->vmsd = &vmstate_sysbus_fdc;
2521 }
2522
2523 static const TypeInfo sysbus_fdc_type_info = {
2524 .name = TYPE_SYSBUS_FDC,
2525 .parent = TYPE_SYS_BUS_DEVICE,
2526 .instance_size = sizeof(FDCtrlSysBus),
2527 .instance_init = sysbus_fdc_common_initfn,
2528 .abstract = true,
2529 .class_init = sysbus_fdc_common_class_init,
2530 };
2531
2532 static void fdc_register_types(void)
2533 {
2534 type_register_static(&isa_fdc_info);
2535 type_register_static(&sysbus_fdc_type_info);
2536 type_register_static(&sysbus_fdc_info);
2537 type_register_static(&sun4m_fdc_info);
2538 }
2539
2540 type_init(fdc_register_types)
AR7 emulation for QEMU